Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.73 98.25 93.97 91.35 91.28 96.37 99.77 92.08


Total test records in report: 1130
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T1021 /workspace/coverage/cover_reg_top/43.edn_intr_test.4026592674 Jul 13 06:34:27 PM PDT 24 Jul 13 06:34:28 PM PDT 24 11545103 ps
T268 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3043727842 Jul 13 06:34:13 PM PDT 24 Jul 13 06:34:15 PM PDT 24 36909293 ps
T1022 /workspace/coverage/cover_reg_top/19.edn_tl_errors.993320705 Jul 13 06:34:14 PM PDT 24 Jul 13 06:34:17 PM PDT 24 179387126 ps
T282 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.960647160 Jul 13 06:34:08 PM PDT 24 Jul 13 06:34:10 PM PDT 24 47591710 ps
T1023 /workspace/coverage/cover_reg_top/14.edn_tl_errors.3947234620 Jul 13 06:34:18 PM PDT 24 Jul 13 06:34:21 PM PDT 24 90254390 ps
T1024 /workspace/coverage/cover_reg_top/11.edn_csr_rw.2163477313 Jul 13 06:34:04 PM PDT 24 Jul 13 06:34:06 PM PDT 24 38184804 ps
T1025 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2011826292 Jul 13 06:34:10 PM PDT 24 Jul 13 06:34:14 PM PDT 24 172098052 ps
T1026 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.1557834343 Jul 13 06:33:56 PM PDT 24 Jul 13 06:33:58 PM PDT 24 41512993 ps
T269 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3864214410 Jul 13 06:33:59 PM PDT 24 Jul 13 06:34:03 PM PDT 24 22087255 ps
T1027 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1755398694 Jul 13 06:34:05 PM PDT 24 Jul 13 06:34:08 PM PDT 24 26382583 ps
T307 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.768133137 Jul 13 06:34:05 PM PDT 24 Jul 13 06:34:09 PM PDT 24 211981159 ps
T283 /workspace/coverage/cover_reg_top/16.edn_csr_rw.548403462 Jul 13 06:34:15 PM PDT 24 Jul 13 06:34:18 PM PDT 24 13534868 ps
T1028 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.528402178 Jul 13 06:34:15 PM PDT 24 Jul 13 06:34:18 PM PDT 24 120584293 ps
T1029 /workspace/coverage/cover_reg_top/48.edn_intr_test.1929747325 Jul 13 06:34:24 PM PDT 24 Jul 13 06:34:26 PM PDT 24 60758051 ps
T1030 /workspace/coverage/cover_reg_top/35.edn_intr_test.2807169231 Jul 13 06:34:26 PM PDT 24 Jul 13 06:34:28 PM PDT 24 57974089 ps
T1031 /workspace/coverage/cover_reg_top/29.edn_intr_test.3195854916 Jul 13 06:34:21 PM PDT 24 Jul 13 06:34:23 PM PDT 24 15746140 ps
T1032 /workspace/coverage/cover_reg_top/31.edn_intr_test.3706814248 Jul 13 06:34:27 PM PDT 24 Jul 13 06:34:28 PM PDT 24 74360390 ps
T284 /workspace/coverage/cover_reg_top/12.edn_csr_rw.1801244015 Jul 13 06:34:10 PM PDT 24 Jul 13 06:34:12 PM PDT 24 15485919 ps
T1033 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3388741811 Jul 13 06:33:59 PM PDT 24 Jul 13 06:34:02 PM PDT 24 27432206 ps
T1034 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2479786660 Jul 13 06:34:13 PM PDT 24 Jul 13 06:34:15 PM PDT 24 73036170 ps
T285 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3547327437 Jul 13 06:34:15 PM PDT 24 Jul 13 06:34:18 PM PDT 24 42100128 ps
T286 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.76106296 Jul 13 06:33:59 PM PDT 24 Jul 13 06:34:02 PM PDT 24 27269089 ps
T1035 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1242120775 Jul 13 06:34:06 PM PDT 24 Jul 13 06:34:09 PM PDT 24 51209949 ps
T1036 /workspace/coverage/cover_reg_top/37.edn_intr_test.2660411492 Jul 13 06:34:23 PM PDT 24 Jul 13 06:34:25 PM PDT 24 66326287 ps
T1037 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1110339236 Jul 13 06:34:03 PM PDT 24 Jul 13 06:34:06 PM PDT 24 25486528 ps
T1038 /workspace/coverage/cover_reg_top/33.edn_intr_test.1541146315 Jul 13 06:34:22 PM PDT 24 Jul 13 06:34:24 PM PDT 24 26640189 ps
T1039 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3264402581 Jul 13 06:34:02 PM PDT 24 Jul 13 06:34:06 PM PDT 24 24096410 ps
T1040 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3123721911 Jul 13 06:34:13 PM PDT 24 Jul 13 06:34:15 PM PDT 24 24391542 ps
T1041 /workspace/coverage/cover_reg_top/1.edn_csr_rw.3801245530 Jul 13 06:33:58 PM PDT 24 Jul 13 06:34:00 PM PDT 24 63574224 ps
T1042 /workspace/coverage/cover_reg_top/42.edn_intr_test.3204821779 Jul 13 06:34:22 PM PDT 24 Jul 13 06:34:24 PM PDT 24 25812679 ps
T1043 /workspace/coverage/cover_reg_top/10.edn_tl_errors.1607382142 Jul 13 06:34:06 PM PDT 24 Jul 13 06:34:08 PM PDT 24 44639453 ps
T1044 /workspace/coverage/cover_reg_top/11.edn_intr_test.2210417842 Jul 13 06:34:07 PM PDT 24 Jul 13 06:34:09 PM PDT 24 35255272 ps
T1045 /workspace/coverage/cover_reg_top/5.edn_tl_errors.1357820846 Jul 13 06:33:57 PM PDT 24 Jul 13 06:34:01 PM PDT 24 208947538 ps
T1046 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2484486384 Jul 13 06:33:59 PM PDT 24 Jul 13 06:34:03 PM PDT 24 100679200 ps
T304 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2904394939 Jul 13 06:33:58 PM PDT 24 Jul 13 06:34:02 PM PDT 24 56563216 ps
T1047 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3369450873 Jul 13 06:34:15 PM PDT 24 Jul 13 06:34:18 PM PDT 24 157626574 ps
T1048 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3541463112 Jul 13 06:34:15 PM PDT 24 Jul 13 06:34:17 PM PDT 24 33607231 ps
T270 /workspace/coverage/cover_reg_top/13.edn_csr_rw.1291305681 Jul 13 06:34:15 PM PDT 24 Jul 13 06:34:18 PM PDT 24 14865287 ps
T1049 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3072254698 Jul 13 06:34:04 PM PDT 24 Jul 13 06:34:07 PM PDT 24 138239797 ps
T1050 /workspace/coverage/cover_reg_top/5.edn_csr_rw.594123881 Jul 13 06:33:57 PM PDT 24 Jul 13 06:33:59 PM PDT 24 59541039 ps
T1051 /workspace/coverage/cover_reg_top/41.edn_intr_test.1447189100 Jul 13 06:34:24 PM PDT 24 Jul 13 06:34:26 PM PDT 24 19136088 ps
T1052 /workspace/coverage/cover_reg_top/16.edn_tl_errors.4037504797 Jul 13 06:34:16 PM PDT 24 Jul 13 06:34:22 PM PDT 24 124577250 ps
T1053 /workspace/coverage/cover_reg_top/18.edn_tl_errors.2495661049 Jul 13 06:34:14 PM PDT 24 Jul 13 06:34:16 PM PDT 24 45563153 ps
T1054 /workspace/coverage/cover_reg_top/7.edn_intr_test.2501272134 Jul 13 06:34:10 PM PDT 24 Jul 13 06:34:12 PM PDT 24 23239907 ps
T1055 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2953499577 Jul 13 06:34:02 PM PDT 24 Jul 13 06:34:06 PM PDT 24 64798256 ps
T1056 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2967827900 Jul 13 06:34:16 PM PDT 24 Jul 13 06:34:18 PM PDT 24 42011670 ps
T1057 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.319901479 Jul 13 06:34:15 PM PDT 24 Jul 13 06:34:17 PM PDT 24 68302430 ps
T1058 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2323724666 Jul 13 06:33:59 PM PDT 24 Jul 13 06:34:02 PM PDT 24 91779007 ps
T1059 /workspace/coverage/cover_reg_top/10.edn_csr_rw.3226042266 Jul 13 06:34:05 PM PDT 24 Jul 13 06:34:07 PM PDT 24 21656634 ps
T1060 /workspace/coverage/cover_reg_top/28.edn_intr_test.1284099167 Jul 13 06:34:22 PM PDT 24 Jul 13 06:34:25 PM PDT 24 51039368 ps
T1061 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3408852505 Jul 13 06:34:01 PM PDT 24 Jul 13 06:34:04 PM PDT 24 21313969 ps
T1062 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1858275826 Jul 13 06:34:11 PM PDT 24 Jul 13 06:34:13 PM PDT 24 42151454 ps
T1063 /workspace/coverage/cover_reg_top/34.edn_intr_test.936047272 Jul 13 06:34:23 PM PDT 24 Jul 13 06:34:25 PM PDT 24 11662245 ps
T1064 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2117636876 Jul 13 06:34:08 PM PDT 24 Jul 13 06:34:10 PM PDT 24 17788494 ps
T308 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2365291432 Jul 13 06:34:14 PM PDT 24 Jul 13 06:34:17 PM PDT 24 149253230 ps
T1065 /workspace/coverage/cover_reg_top/0.edn_intr_test.2918998796 Jul 13 06:33:59 PM PDT 24 Jul 13 06:34:03 PM PDT 24 91085332 ps
T1066 /workspace/coverage/cover_reg_top/15.edn_intr_test.1241761340 Jul 13 06:34:14 PM PDT 24 Jul 13 06:34:16 PM PDT 24 19743728 ps
T1067 /workspace/coverage/cover_reg_top/17.edn_intr_test.3800448854 Jul 13 06:34:15 PM PDT 24 Jul 13 06:34:18 PM PDT 24 42576655 ps
T1068 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3740982879 Jul 13 06:34:14 PM PDT 24 Jul 13 06:34:15 PM PDT 24 13826524 ps
T1069 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.518219268 Jul 13 06:34:06 PM PDT 24 Jul 13 06:34:08 PM PDT 24 23833456 ps
T1070 /workspace/coverage/cover_reg_top/2.edn_tl_errors.1750495731 Jul 13 06:33:58 PM PDT 24 Jul 13 06:34:00 PM PDT 24 55682199 ps
T1071 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.774722131 Jul 13 06:34:16 PM PDT 24 Jul 13 06:34:19 PM PDT 24 34914764 ps
T1072 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.503764839 Jul 13 06:34:19 PM PDT 24 Jul 13 06:34:21 PM PDT 24 21596955 ps
T1073 /workspace/coverage/cover_reg_top/1.edn_intr_test.1989525969 Jul 13 06:34:00 PM PDT 24 Jul 13 06:34:03 PM PDT 24 22663754 ps
T1074 /workspace/coverage/cover_reg_top/23.edn_intr_test.2499563589 Jul 13 06:34:21 PM PDT 24 Jul 13 06:34:22 PM PDT 24 19144058 ps
T1075 /workspace/coverage/cover_reg_top/13.edn_intr_test.1967839614 Jul 13 06:34:07 PM PDT 24 Jul 13 06:34:09 PM PDT 24 25258711 ps
T1076 /workspace/coverage/cover_reg_top/7.edn_tl_errors.3404602040 Jul 13 06:34:05 PM PDT 24 Jul 13 06:34:10 PM PDT 24 41938479 ps
T1077 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.22785566 Jul 13 06:34:06 PM PDT 24 Jul 13 06:34:09 PM PDT 24 39794815 ps
T1078 /workspace/coverage/cover_reg_top/39.edn_intr_test.3954319194 Jul 13 06:34:24 PM PDT 24 Jul 13 06:34:26 PM PDT 24 18427223 ps
T1079 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.117480833 Jul 13 06:34:17 PM PDT 24 Jul 13 06:34:20 PM PDT 24 38909288 ps
T1080 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.951644274 Jul 13 06:33:57 PM PDT 24 Jul 13 06:34:01 PM PDT 24 159692824 ps
T1081 /workspace/coverage/cover_reg_top/13.edn_tl_errors.2995180797 Jul 13 06:34:07 PM PDT 24 Jul 13 06:34:12 PM PDT 24 1086102761 ps
T1082 /workspace/coverage/cover_reg_top/4.edn_tl_errors.4246938803 Jul 13 06:33:56 PM PDT 24 Jul 13 06:33:58 PM PDT 24 112306114 ps
T1083 /workspace/coverage/cover_reg_top/9.edn_intr_test.2328628057 Jul 13 06:34:10 PM PDT 24 Jul 13 06:34:11 PM PDT 24 14023924 ps
T1084 /workspace/coverage/cover_reg_top/3.edn_tl_errors.4255722138 Jul 13 06:33:57 PM PDT 24 Jul 13 06:34:01 PM PDT 24 136103490 ps
T1085 /workspace/coverage/cover_reg_top/27.edn_intr_test.3445594566 Jul 13 06:34:21 PM PDT 24 Jul 13 06:34:23 PM PDT 24 26080857 ps
T1086 /workspace/coverage/cover_reg_top/14.edn_intr_test.206119208 Jul 13 06:34:13 PM PDT 24 Jul 13 06:34:15 PM PDT 24 17063005 ps
T1087 /workspace/coverage/cover_reg_top/14.edn_csr_rw.1013831877 Jul 13 06:34:16 PM PDT 24 Jul 13 06:34:19 PM PDT 24 23036428 ps
T1088 /workspace/coverage/cover_reg_top/22.edn_intr_test.3680966463 Jul 13 06:34:19 PM PDT 24 Jul 13 06:34:20 PM PDT 24 54566252 ps
T1089 /workspace/coverage/cover_reg_top/8.edn_tl_errors.833233654 Jul 13 06:34:06 PM PDT 24 Jul 13 06:34:09 PM PDT 24 159847913 ps
T305 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1701275404 Jul 13 06:34:12 PM PDT 24 Jul 13 06:34:14 PM PDT 24 98973609 ps
T1090 /workspace/coverage/cover_reg_top/10.edn_intr_test.3326497184 Jul 13 06:34:08 PM PDT 24 Jul 13 06:34:10 PM PDT 24 15125948 ps
T271 /workspace/coverage/cover_reg_top/4.edn_csr_rw.4227842739 Jul 13 06:34:00 PM PDT 24 Jul 13 06:34:03 PM PDT 24 13374159 ps
T1091 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.4211253618 Jul 13 06:34:08 PM PDT 24 Jul 13 06:34:11 PM PDT 24 613508645 ps
T272 /workspace/coverage/cover_reg_top/7.edn_csr_rw.80434242 Jul 13 06:34:06 PM PDT 24 Jul 13 06:34:08 PM PDT 24 20305739 ps
T1092 /workspace/coverage/cover_reg_top/6.edn_intr_test.4290870998 Jul 13 06:34:03 PM PDT 24 Jul 13 06:34:06 PM PDT 24 12924274 ps
T1093 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1137413477 Jul 13 06:33:59 PM PDT 24 Jul 13 06:34:02 PM PDT 24 16210912 ps
T1094 /workspace/coverage/cover_reg_top/49.edn_intr_test.2926204879 Jul 13 06:34:23 PM PDT 24 Jul 13 06:34:25 PM PDT 24 23877736 ps
T1095 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1812532250 Jul 13 06:34:07 PM PDT 24 Jul 13 06:34:10 PM PDT 24 104495630 ps
T1096 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1656884690 Jul 13 06:34:15 PM PDT 24 Jul 13 06:34:17 PM PDT 24 71227598 ps
T1097 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.4294705441 Jul 13 06:34:17 PM PDT 24 Jul 13 06:34:20 PM PDT 24 70989373 ps
T1098 /workspace/coverage/cover_reg_top/9.edn_tl_errors.1195825148 Jul 13 06:34:06 PM PDT 24 Jul 13 06:34:10 PM PDT 24 146968181 ps
T1099 /workspace/coverage/cover_reg_top/38.edn_intr_test.3644294965 Jul 13 06:34:22 PM PDT 24 Jul 13 06:34:24 PM PDT 24 42345001 ps
T1100 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2577951719 Jul 13 06:34:04 PM PDT 24 Jul 13 06:34:07 PM PDT 24 47407686 ps
T1101 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2074688257 Jul 13 06:33:58 PM PDT 24 Jul 13 06:34:01 PM PDT 24 63795722 ps
T273 /workspace/coverage/cover_reg_top/9.edn_csr_rw.4264809187 Jul 13 06:34:06 PM PDT 24 Jul 13 06:34:09 PM PDT 24 12302625 ps
T1102 /workspace/coverage/cover_reg_top/12.edn_intr_test.3564817511 Jul 13 06:34:11 PM PDT 24 Jul 13 06:34:12 PM PDT 24 55315923 ps
T1103 /workspace/coverage/cover_reg_top/17.edn_tl_errors.3742711245 Jul 13 06:34:15 PM PDT 24 Jul 13 06:34:18 PM PDT 24 37700630 ps
T1104 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.561099232 Jul 13 06:34:15 PM PDT 24 Jul 13 06:34:18 PM PDT 24 31464226 ps
T1105 /workspace/coverage/cover_reg_top/47.edn_intr_test.863521328 Jul 13 06:34:22 PM PDT 24 Jul 13 06:34:25 PM PDT 24 12195514 ps
T1106 /workspace/coverage/cover_reg_top/15.edn_csr_rw.878248232 Jul 13 06:34:15 PM PDT 24 Jul 13 06:34:18 PM PDT 24 15876049 ps
T1107 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3433156114 Jul 13 06:33:58 PM PDT 24 Jul 13 06:34:03 PM PDT 24 218136337 ps
T1108 /workspace/coverage/cover_reg_top/8.edn_intr_test.23184430 Jul 13 06:34:10 PM PDT 24 Jul 13 06:34:11 PM PDT 24 23102718 ps
T274 /workspace/coverage/cover_reg_top/0.edn_csr_rw.752981895 Jul 13 06:33:59 PM PDT 24 Jul 13 06:34:02 PM PDT 24 11658537 ps
T1109 /workspace/coverage/cover_reg_top/8.edn_csr_rw.3326829526 Jul 13 06:34:05 PM PDT 24 Jul 13 06:34:08 PM PDT 24 22185187 ps
T1110 /workspace/coverage/cover_reg_top/40.edn_intr_test.3584461895 Jul 13 06:34:22 PM PDT 24 Jul 13 06:34:24 PM PDT 24 22185553 ps
T1111 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1805964583 Jul 13 06:34:00 PM PDT 24 Jul 13 06:34:04 PM PDT 24 139849143 ps
T1112 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.77998192 Jul 13 06:34:07 PM PDT 24 Jul 13 06:34:10 PM PDT 24 34701153 ps
T1113 /workspace/coverage/cover_reg_top/5.edn_intr_test.1986569999 Jul 13 06:34:01 PM PDT 24 Jul 13 06:34:04 PM PDT 24 13663756 ps
T1114 /workspace/coverage/cover_reg_top/36.edn_intr_test.3377493641 Jul 13 06:34:22 PM PDT 24 Jul 13 06:34:24 PM PDT 24 30201858 ps
T275 /workspace/coverage/cover_reg_top/17.edn_csr_rw.3627748331 Jul 13 06:34:15 PM PDT 24 Jul 13 06:34:17 PM PDT 24 28265608 ps
T1115 /workspace/coverage/cover_reg_top/4.edn_intr_test.747288174 Jul 13 06:33:59 PM PDT 24 Jul 13 06:34:03 PM PDT 24 28015277 ps
T1116 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2578507807 Jul 13 06:33:57 PM PDT 24 Jul 13 06:33:59 PM PDT 24 51793769 ps
T1117 /workspace/coverage/cover_reg_top/46.edn_intr_test.3254123986 Jul 13 06:34:20 PM PDT 24 Jul 13 06:34:21 PM PDT 24 15704602 ps
T1118 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.597835492 Jul 13 06:34:10 PM PDT 24 Jul 13 06:34:12 PM PDT 24 100341206 ps
T1119 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.490366414 Jul 13 06:33:59 PM PDT 24 Jul 13 06:34:03 PM PDT 24 95176861 ps
T1120 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1540012281 Jul 13 06:34:01 PM PDT 24 Jul 13 06:34:06 PM PDT 24 212192114 ps
T1121 /workspace/coverage/cover_reg_top/26.edn_intr_test.544200952 Jul 13 06:34:24 PM PDT 24 Jul 13 06:34:26 PM PDT 24 22037855 ps
T1122 /workspace/coverage/cover_reg_top/19.edn_intr_test.458201936 Jul 13 06:34:13 PM PDT 24 Jul 13 06:34:15 PM PDT 24 34356473 ps
T1123 /workspace/coverage/cover_reg_top/32.edn_intr_test.4220110246 Jul 13 06:34:23 PM PDT 24 Jul 13 06:34:25 PM PDT 24 14838193 ps
T1124 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2344939613 Jul 13 06:34:06 PM PDT 24 Jul 13 06:34:09 PM PDT 24 98239053 ps
T1125 /workspace/coverage/cover_reg_top/25.edn_intr_test.3778225003 Jul 13 06:34:22 PM PDT 24 Jul 13 06:34:24 PM PDT 24 26216902 ps
T276 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.354220439 Jul 13 06:33:58 PM PDT 24 Jul 13 06:34:03 PM PDT 24 159047217 ps
T277 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1036242201 Jul 13 06:33:58 PM PDT 24 Jul 13 06:34:00 PM PDT 24 15063810 ps
T278 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.4011175452 Jul 13 06:34:01 PM PDT 24 Jul 13 06:34:05 PM PDT 24 336295704 ps
T1126 /workspace/coverage/cover_reg_top/15.edn_tl_errors.3866054356 Jul 13 06:34:12 PM PDT 24 Jul 13 06:34:15 PM PDT 24 35121387 ps
T1127 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3909143789 Jul 13 06:33:58 PM PDT 24 Jul 13 06:34:01 PM PDT 24 70979874 ps
T1128 /workspace/coverage/cover_reg_top/16.edn_intr_test.534890449 Jul 13 06:34:16 PM PDT 24 Jul 13 06:34:18 PM PDT 24 33886414 ps
T1129 /workspace/coverage/cover_reg_top/6.edn_tl_errors.3092313266 Jul 13 06:33:59 PM PDT 24 Jul 13 06:34:05 PM PDT 24 392935401 ps
T1130 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.307586564 Jul 13 06:34:08 PM PDT 24 Jul 13 06:34:10 PM PDT 24 36917368 ps

Test location /workspace/coverage/default/282.edn_genbits.686218318
Short name T24
Test name
Test status
Simulation time 60190449 ps
CPU time 1.99 seconds
Started Jul 13 06:42:00 PM PDT 24
Finished Jul 13 06:42:02 PM PDT 24
Peak memory 218776 kb
Host smart-8b239e25-eb17-403e-8dd4-795d99a07d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686218318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.686218318
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.1755918190
Short name T15
Test name
Test status
Simulation time 39698207 ps
CPU time 1.24 seconds
Started Jul 13 06:41:43 PM PDT 24
Finished Jul 13 06:41:45 PM PDT 24
Peak memory 220140 kb
Host smart-7e7239b0-fd66-4165-81f0-4e7c653d27bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755918190 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.1755918190
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.1937520313
Short name T40
Test name
Test status
Simulation time 161335967239 ps
CPU time 363.75 seconds
Started Jul 13 06:39:18 PM PDT 24
Finished Jul 13 06:45:23 PM PDT 24
Peak memory 219084 kb
Host smart-54212fbd-1262-44b8-bfbd-3f7c68dc4604
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937520313 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.1937520313
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/111.edn_genbits.130823929
Short name T12
Test name
Test status
Simulation time 152209334 ps
CPU time 1.32 seconds
Started Jul 13 06:41:17 PM PDT 24
Finished Jul 13 06:41:21 PM PDT 24
Peak memory 220728 kb
Host smart-df285f81-f483-4dcc-bd47-0b6080deb311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130823929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.130823929
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_sec_cm.1793496546
Short name T17
Test name
Test status
Simulation time 1954885172 ps
CPU time 8.55 seconds
Started Jul 13 06:38:50 PM PDT 24
Finished Jul 13 06:38:59 PM PDT 24
Peak memory 237824 kb
Host smart-af957849-4661-4016-8785-b1b298bc4d32
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793496546 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.1793496546
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/14.edn_intr.2911160594
Short name T4
Test name
Test status
Simulation time 20731790 ps
CPU time 1.21 seconds
Started Jul 13 06:39:22 PM PDT 24
Finished Jul 13 06:39:25 PM PDT 24
Peak memory 224324 kb
Host smart-3c25635f-0c64-4f27-b701-accd54cc0f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911160594 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.2911160594
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/13.edn_stress_all.3938528008
Short name T111
Test name
Test status
Simulation time 390267096 ps
CPU time 4.31 seconds
Started Jul 13 06:39:22 PM PDT 24
Finished Jul 13 06:39:28 PM PDT 24
Peak memory 217488 kb
Host smart-667aa359-166f-47f9-b659-def7ab5c9467
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938528008 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3938528008
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/165.edn_alert.2117762744
Short name T2
Test name
Test status
Simulation time 71114175 ps
CPU time 1.13 seconds
Started Jul 13 06:41:37 PM PDT 24
Finished Jul 13 06:41:39 PM PDT 24
Peak memory 219220 kb
Host smart-2f39657b-aa6d-4508-a97e-8e70764f363c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117762744 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.2117762744
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/180.edn_alert.2546333788
Short name T169
Test name
Test status
Simulation time 23558851 ps
CPU time 1.23 seconds
Started Jul 13 06:41:35 PM PDT 24
Finished Jul 13 06:41:37 PM PDT 24
Peak memory 221292 kb
Host smart-8474d680-73e3-40aa-a51c-58571f05b3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546333788 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.2546333788
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.3578312970
Short name T21
Test name
Test status
Simulation time 45998148 ps
CPU time 1.46 seconds
Started Jul 13 06:40:14 PM PDT 24
Finished Jul 13 06:40:17 PM PDT 24
Peak memory 217092 kb
Host smart-207289fa-7fed-434f-aaad-93875aa93cc3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578312970 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.3578312970
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.2923964950
Short name T41
Test name
Test status
Simulation time 81339977061 ps
CPU time 538.72 seconds
Started Jul 13 06:39:10 PM PDT 24
Finished Jul 13 06:48:11 PM PDT 24
Peak memory 224080 kb
Host smart-8466df11-2996-401b-8a1a-6c1b4e6e4065
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923964950 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.2923964950
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_regwen.373634154
Short name T309
Test name
Test status
Simulation time 45625583 ps
CPU time 0.92 seconds
Started Jul 13 06:38:41 PM PDT 24
Finished Jul 13 06:38:43 PM PDT 24
Peak memory 207404 kb
Host smart-461da456-c508-4309-b37c-88123baeada5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373634154 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.373634154
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/19.edn_alert.2192697649
Short name T86
Test name
Test status
Simulation time 82404865 ps
CPU time 1.2 seconds
Started Jul 13 06:39:31 PM PDT 24
Finished Jul 13 06:39:33 PM PDT 24
Peak memory 220216 kb
Host smart-81aeb330-43dd-4b51-9cb9-c74502f6cb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192697649 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.2192697649
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/189.edn_alert.1461848348
Short name T158
Test name
Test status
Simulation time 43832703 ps
CPU time 1.23 seconds
Started Jul 13 06:41:38 PM PDT 24
Finished Jul 13 06:41:40 PM PDT 24
Peak memory 219016 kb
Host smart-f48a675d-777f-44e5-b1e6-1067b18f175d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461848348 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.1461848348
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2366960266
Short name T303
Test name
Test status
Simulation time 496754338 ps
CPU time 2.67 seconds
Started Jul 13 06:33:58 PM PDT 24
Finished Jul 13 06:34:03 PM PDT 24
Peak memory 206936 kb
Host smart-1f6e3583-ae71-4307-bfe3-90a040055c2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366960266 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.2366960266
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/default/151.edn_alert.997865145
Short name T23
Test name
Test status
Simulation time 91062551 ps
CPU time 1.08 seconds
Started Jul 13 06:41:29 PM PDT 24
Finished Jul 13 06:41:32 PM PDT 24
Peak memory 220152 kb
Host smart-bb176042-6e3e-401f-91c1-eaf5925074de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997865145 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.997865145
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1921444292
Short name T264
Test name
Test status
Simulation time 49867088 ps
CPU time 0.89 seconds
Started Jul 13 06:33:58 PM PDT 24
Finished Jul 13 06:34:01 PM PDT 24
Peak memory 206912 kb
Host smart-a1f1300a-6ce6-429d-b9da-3c62b5ea02b1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921444292 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1921444292
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/default/69.edn_err.2824702180
Short name T63
Test name
Test status
Simulation time 22182545 ps
CPU time 1.09 seconds
Started Jul 13 06:40:44 PM PDT 24
Finished Jul 13 06:40:47 PM PDT 24
Peak memory 224240 kb
Host smart-b59b4363-6ecf-4ec6-a990-c5bf0c126db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824702180 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2824702180
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/206.edn_genbits.1055470273
Short name T114
Test name
Test status
Simulation time 56746821 ps
CPU time 1.43 seconds
Started Jul 13 06:41:44 PM PDT 24
Finished Jul 13 06:41:47 PM PDT 24
Peak memory 219072 kb
Host smart-7237e3fe-73b3-4f9f-a0f0-9d78099c28b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055470273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.1055470273
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_disable.847347705
Short name T219
Test name
Test status
Simulation time 18329426 ps
CPU time 0.9 seconds
Started Jul 13 06:40:01 PM PDT 24
Finished Jul 13 06:40:04 PM PDT 24
Peak memory 216540 kb
Host smart-f6b9f173-c5ac-4512-b455-2393973f5b7a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847347705 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.847347705
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable.2803665788
Short name T208
Test name
Test status
Simulation time 33124229 ps
CPU time 0.87 seconds
Started Jul 13 06:40:24 PM PDT 24
Finished Jul 13 06:40:25 PM PDT 24
Peak memory 216536 kb
Host smart-09763bb5-3922-41a5-8acc-dccc72f1c12f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803665788 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2803665788
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.386072452
Short name T757
Test name
Test status
Simulation time 39765575 ps
CPU time 1.08 seconds
Started Jul 13 06:39:32 PM PDT 24
Finished Jul 13 06:39:34 PM PDT 24
Peak memory 217192 kb
Host smart-6b3a0fb5-f408-43f2-9292-1e46b65b872b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386072452 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_di
sable_auto_req_mode.386072452
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_disable.4183943548
Short name T179
Test name
Test status
Simulation time 42778748 ps
CPU time 0.85 seconds
Started Jul 13 06:39:49 PM PDT 24
Finished Jul 13 06:39:51 PM PDT 24
Peak memory 216528 kb
Host smart-273a4d92-067a-4776-a9f7-8813e2845ca7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183943548 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.4183943548
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/105.edn_alert.1950330229
Short name T164
Test name
Test status
Simulation time 95272131 ps
CPU time 1.29 seconds
Started Jul 13 06:41:19 PM PDT 24
Finished Jul 13 06:41:21 PM PDT 24
Peak memory 220056 kb
Host smart-98a0d407-5afa-4c3e-b35b-de70589cde1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950330229 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.1950330229
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/36.edn_intr.2427308874
Short name T100
Test name
Test status
Simulation time 22156556 ps
CPU time 1.15 seconds
Started Jul 13 06:40:16 PM PDT 24
Finished Jul 13 06:40:19 PM PDT 24
Peak memory 216192 kb
Host smart-380db1e2-7f0f-435b-8b2a-915e2cb60b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427308874 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.2427308874
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/263.edn_genbits.3587286968
Short name T13
Test name
Test status
Simulation time 197730671 ps
CPU time 1.34 seconds
Started Jul 13 06:42:01 PM PDT 24
Finished Jul 13 06:42:03 PM PDT 24
Peak memory 220332 kb
Host smart-0335917f-ea39-4dfc-ab55-664ee6858838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587286968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.3587286968
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.775992312
Short name T80
Test name
Test status
Simulation time 154861463 ps
CPU time 1.28 seconds
Started Jul 13 06:39:32 PM PDT 24
Finished Jul 13 06:39:34 PM PDT 24
Peak memory 217104 kb
Host smart-ca95acd4-72fc-431e-96e0-91bf58b515ab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775992312 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_di
sable_auto_req_mode.775992312
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/158.edn_alert.466121234
Short name T231
Test name
Test status
Simulation time 24366044 ps
CPU time 1.2 seconds
Started Jul 13 06:41:29 PM PDT 24
Finished Jul 13 06:41:32 PM PDT 24
Peak memory 219556 kb
Host smart-9315e540-08ae-4892-b98e-c0c51a18def1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466121234 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.466121234
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert.211673225
Short name T150
Test name
Test status
Simulation time 76576031 ps
CPU time 1.2 seconds
Started Jul 13 06:39:11 PM PDT 24
Finished Jul 13 06:39:14 PM PDT 24
Peak memory 219984 kb
Host smart-2580be5a-3513-4399-891a-c432de547ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211673225 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.211673225
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/137.edn_alert.1044021654
Short name T296
Test name
Test status
Simulation time 429580412 ps
CPU time 1.28 seconds
Started Jul 13 06:41:26 PM PDT 24
Finished Jul 13 06:41:30 PM PDT 24
Peak memory 218864 kb
Host smart-324069a4-4fb7-470d-b620-9885651c274c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044021654 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.1044021654
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert.2532032677
Short name T312
Test name
Test status
Simulation time 42542830 ps
CPU time 1.18 seconds
Started Jul 13 06:39:57 PM PDT 24
Finished Jul 13 06:39:59 PM PDT 24
Peak memory 221056 kb
Host smart-41957492-7209-46b0-8bab-e17f86fb422c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532032677 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2532032677
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert.1241809196
Short name T191
Test name
Test status
Simulation time 21663777 ps
CPU time 1.14 seconds
Started Jul 13 06:40:01 PM PDT 24
Finished Jul 13 06:40:04 PM PDT 24
Peak memory 218956 kb
Host smart-0e7efa4e-8fc8-4233-9e27-5a7dbda995b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241809196 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1241809196
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/98.edn_alert.3196580859
Short name T120
Test name
Test status
Simulation time 45126457 ps
CPU time 1.19 seconds
Started Jul 13 06:41:15 PM PDT 24
Finished Jul 13 06:41:19 PM PDT 24
Peak memory 220088 kb
Host smart-3cc72226-0ab7-441b-bf30-537f71986928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196580859 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.3196580859
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/19.edn_intr.3307175347
Short name T39
Test name
Test status
Simulation time 24819273 ps
CPU time 0.95 seconds
Started Jul 13 06:39:28 PM PDT 24
Finished Jul 13 06:39:30 PM PDT 24
Peak memory 216004 kb
Host smart-6e1a2eec-a68e-4760-acb1-fd30a4e03be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307175347 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3307175347
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/45.edn_disable.3889375647
Short name T721
Test name
Test status
Simulation time 29973273 ps
CPU time 0.88 seconds
Started Jul 13 06:40:30 PM PDT 24
Finished Jul 13 06:40:33 PM PDT 24
Peak memory 215728 kb
Host smart-1c711a9e-c370-48a0-bd77-6d7d1c677917
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889375647 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3889375647
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/54.edn_alert.2187635577
Short name T202
Test name
Test status
Simulation time 30079484 ps
CPU time 1.24 seconds
Started Jul 13 06:40:35 PM PDT 24
Finished Jul 13 06:40:37 PM PDT 24
Peak memory 215952 kb
Host smart-b1c9aa33-7968-4e64-b5da-ed8a9cd0dec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187635577 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.2187635577
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.1641595129
Short name T953
Test name
Test status
Simulation time 65814240 ps
CPU time 1.08 seconds
Started Jul 13 06:39:20 PM PDT 24
Finished Jul 13 06:39:24 PM PDT 24
Peak memory 217076 kb
Host smart-4ec84895-3c86-4ac3-a3c0-48b2e1d669ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641595129 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.1641595129
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/103.edn_alert.542369120
Short name T195
Test name
Test status
Simulation time 25932205 ps
CPU time 1.19 seconds
Started Jul 13 06:41:13 PM PDT 24
Finished Jul 13 06:41:15 PM PDT 24
Peak memory 219980 kb
Host smart-24de47b9-49aa-4a39-b177-590a4eb4ac17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542369120 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.542369120
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/106.edn_alert.1246803029
Short name T572
Test name
Test status
Simulation time 270125611 ps
CPU time 1.2 seconds
Started Jul 13 06:41:11 PM PDT 24
Finished Jul 13 06:41:12 PM PDT 24
Peak memory 219076 kb
Host smart-b0f945d5-117d-469c-98bd-3c971f1ac3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246803029 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.1246803029
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.999889514
Short name T988
Test name
Test status
Simulation time 52349995 ps
CPU time 1.17 seconds
Started Jul 13 06:39:41 PM PDT 24
Finished Jul 13 06:39:43 PM PDT 24
Peak memory 217320 kb
Host smart-a39cba69-a849-4840-8d1a-d65cfc7320db
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999889514 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_di
sable_auto_req_mode.999889514
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_disable.513498454
Short name T223
Test name
Test status
Simulation time 33934924 ps
CPU time 0.85 seconds
Started Jul 13 06:38:58 PM PDT 24
Finished Jul 13 06:39:00 PM PDT 24
Peak memory 216500 kb
Host smart-8f1d5bca-7d4b-4719-a870-e975a40a17f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513498454 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.513498454
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable.3937148821
Short name T187
Test name
Test status
Simulation time 13799102 ps
CPU time 0.93 seconds
Started Jul 13 06:40:01 PM PDT 24
Finished Jul 13 06:40:04 PM PDT 24
Peak memory 216760 kb
Host smart-62642fb9-074b-42f9-99c8-a1b347cab0e4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937148821 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3937148821
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable.3530371133
Short name T216
Test name
Test status
Simulation time 17892639 ps
CPU time 0.87 seconds
Started Jul 13 06:40:14 PM PDT 24
Finished Jul 13 06:40:17 PM PDT 24
Peak memory 216440 kb
Host smart-4defc5d6-1c0f-4bd1-a336-a4bd9bc953b6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530371133 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3530371133
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable.2032614999
Short name T200
Test name
Test status
Simulation time 16369457 ps
CPU time 0.9 seconds
Started Jul 13 06:40:16 PM PDT 24
Finished Jul 13 06:40:19 PM PDT 24
Peak memory 216868 kb
Host smart-d77ed562-1561-48a7-8fd4-3936dad876dd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032614999 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2032614999
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.2996257596
Short name T156
Test name
Test status
Simulation time 38087630 ps
CPU time 1.31 seconds
Started Jul 13 06:40:13 PM PDT 24
Finished Jul 13 06:40:15 PM PDT 24
Peak memory 217300 kb
Host smart-e1a232c7-96b3-42f4-977b-f066b1ca9067
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996257596 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.2996257596
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.3431524333
Short name T206
Test name
Test status
Simulation time 22554582 ps
CPU time 0.93 seconds
Started Jul 13 06:40:27 PM PDT 24
Finished Jul 13 06:40:30 PM PDT 24
Peak memory 219816 kb
Host smart-e2895c8b-bec5-438a-9dd6-42a425937cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431524333 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3431524333
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.2769894207
Short name T55
Test name
Test status
Simulation time 53425735 ps
CPU time 1.87 seconds
Started Jul 13 06:41:05 PM PDT 24
Finished Jul 13 06:41:08 PM PDT 24
Peak memory 218768 kb
Host smart-90c83b32-388a-4dfa-80bd-6c5b575bce00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769894207 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2769894207
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_err.2160096728
Short name T106
Test name
Test status
Simulation time 24138557 ps
CPU time 0.98 seconds
Started Jul 13 06:39:20 PM PDT 24
Finished Jul 13 06:39:24 PM PDT 24
Peak memory 219152 kb
Host smart-044cdaf1-3795-438f-b66f-77c5fffdcdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160096728 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.2160096728
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/100.edn_genbits.231050271
Short name T337
Test name
Test status
Simulation time 87799956 ps
CPU time 1.21 seconds
Started Jul 13 06:41:15 PM PDT 24
Finished Jul 13 06:41:19 PM PDT 24
Peak memory 219312 kb
Host smart-cba5d397-17a7-4bec-9ca6-725ff689b94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231050271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.231050271
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.4072105982
Short name T380
Test name
Test status
Simulation time 66202900 ps
CPU time 1.63 seconds
Started Jul 13 06:41:51 PM PDT 24
Finished Jul 13 06:41:54 PM PDT 24
Peak memory 220308 kb
Host smart-fdef44ab-adee-4725-9eb0-5e87a5127e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072105982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.4072105982
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_alert_test.3865408902
Short name T391
Test name
Test status
Simulation time 224201213 ps
CPU time 0.92 seconds
Started Jul 13 06:38:39 PM PDT 24
Finished Jul 13 06:38:42 PM PDT 24
Peak memory 215176 kb
Host smart-a6b3011c-cc3a-4143-a741-40688e075992
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865408902 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.3865408902
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/53.edn_genbits.3909710411
Short name T88
Test name
Test status
Simulation time 58965273 ps
CPU time 2.17 seconds
Started Jul 13 06:40:32 PM PDT 24
Finished Jul 13 06:40:36 PM PDT 24
Peak memory 219408 kb
Host smart-86f73eaa-d15f-459c-a648-ad1709eed069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909710411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.3909710411
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3200478598
Short name T37
Test name
Test status
Simulation time 23410788 ps
CPU time 1.02 seconds
Started Jul 13 06:39:33 PM PDT 24
Finished Jul 13 06:39:35 PM PDT 24
Peak memory 216060 kb
Host smart-28600e51-49f5-4293-88bc-ffa3d594b6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200478598 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3200478598
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/120.edn_alert.3535262478
Short name T176
Test name
Test status
Simulation time 22621068 ps
CPU time 1.14 seconds
Started Jul 13 06:41:12 PM PDT 24
Finished Jul 13 06:41:14 PM PDT 24
Peak memory 219964 kb
Host smart-2e7e6375-4fb5-4b29-bef1-dace73208735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535262478 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.3535262478
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.904309550
Short name T287
Test name
Test status
Simulation time 89481089 ps
CPU time 1.34 seconds
Started Jul 13 06:41:14 PM PDT 24
Finished Jul 13 06:41:18 PM PDT 24
Peak memory 219032 kb
Host smart-52eeee10-223f-469f-a780-8c75a4609daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904309550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.904309550
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.2233000477
Short name T325
Test name
Test status
Simulation time 42262365 ps
CPU time 1.5 seconds
Started Jul 13 06:41:41 PM PDT 24
Finished Jul 13 06:41:43 PM PDT 24
Peak memory 218816 kb
Host smart-8f9fa56f-ec57-426d-bebd-c80ba17dc3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233000477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.2233000477
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.76106296
Short name T286
Test name
Test status
Simulation time 27269089 ps
CPU time 1 seconds
Started Jul 13 06:33:59 PM PDT 24
Finished Jul 13 06:34:02 PM PDT 24
Peak memory 206928 kb
Host smart-57c106e1-7387-4a62-8a62-37753c972c27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76106296 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_outs
tanding.76106296
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.768133137
Short name T307
Test name
Test status
Simulation time 211981159 ps
CPU time 2.72 seconds
Started Jul 13 06:34:05 PM PDT 24
Finished Jul 13 06:34:09 PM PDT 24
Peak memory 207112 kb
Host smart-6e69f335-11b2-4ea9-a6e2-320e899af6d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768133137 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.768133137
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/default/108.edn_genbits.1244142992
Short name T448
Test name
Test status
Simulation time 154469863 ps
CPU time 1.07 seconds
Started Jul 13 06:41:13 PM PDT 24
Finished Jul 13 06:41:16 PM PDT 24
Peak memory 215624 kb
Host smart-90c22139-dd46-46c0-af82-0eb087ea2518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244142992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.1244142992
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.988490046
Short name T251
Test name
Test status
Simulation time 85293764 ps
CPU time 1.16 seconds
Started Jul 13 06:41:16 PM PDT 24
Finished Jul 13 06:41:19 PM PDT 24
Peak memory 217488 kb
Host smart-110aa963-8c4f-4e34-a721-bab5eb746d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988490046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.988490046
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.310075320
Short name T340
Test name
Test status
Simulation time 59006370434 ps
CPU time 347.43 seconds
Started Jul 13 06:39:21 PM PDT 24
Finished Jul 13 06:45:11 PM PDT 24
Peak memory 224024 kb
Host smart-7573a538-919c-4f17-b5a8-435fb96d3e0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310075320 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.310075320
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.edn_genbits.2232938236
Short name T330
Test name
Test status
Simulation time 52963438 ps
CPU time 1.21 seconds
Started Jul 13 06:39:35 PM PDT 24
Finished Jul 13 06:39:37 PM PDT 24
Peak memory 219020 kb
Host smart-e20d96a5-ff35-4374-9d55-fe8fc16fe670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232938236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2232938236
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.2782411717
Short name T876
Test name
Test status
Simulation time 99431536216 ps
CPU time 1040.97 seconds
Started Jul 13 06:39:32 PM PDT 24
Finished Jul 13 06:56:54 PM PDT 24
Peak memory 223992 kb
Host smart-b0f5c89a-b267-4b30-8032-60151d4492e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782411717 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.2782411717
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.263449281
Short name T342
Test name
Test status
Simulation time 80063087 ps
CPU time 1.21 seconds
Started Jul 13 06:41:34 PM PDT 24
Finished Jul 13 06:41:35 PM PDT 24
Peak memory 218964 kb
Host smart-9cb87a9b-7507-4ef8-ab5f-128e6a48b3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263449281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.263449281
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.3203858512
Short name T497
Test name
Test status
Simulation time 55443001 ps
CPU time 1.37 seconds
Started Jul 13 06:41:43 PM PDT 24
Finished Jul 13 06:41:45 PM PDT 24
Peak memory 218940 kb
Host smart-60fa4f4e-aace-454e-8957-fa0cf4f502d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203858512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.3203858512
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.71392279
Short name T288
Test name
Test status
Simulation time 57442451 ps
CPU time 1.28 seconds
Started Jul 13 06:41:56 PM PDT 24
Finished Jul 13 06:41:59 PM PDT 24
Peak memory 219208 kb
Host smart-e3a3bcd7-c43a-40eb-9769-80b931be8b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71392279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.71392279
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.4239674469
Short name T882
Test name
Test status
Simulation time 25573909 ps
CPU time 0.98 seconds
Started Jul 13 06:39:19 PM PDT 24
Finished Jul 13 06:39:22 PM PDT 24
Peak memory 216060 kb
Host smart-ba83387f-4c39-4ebd-b463-a9a532172f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239674469 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.4239674469
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/130.edn_alert.3967868530
Short name T122
Test name
Test status
Simulation time 84134211 ps
CPU time 1.18 seconds
Started Jul 13 06:41:14 PM PDT 24
Finished Jul 13 06:41:18 PM PDT 24
Peak memory 218700 kb
Host smart-f010c30b-fad6-4ab9-b260-cba8911b6211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967868530 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.3967868530
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.1192762217
Short name T96
Test name
Test status
Simulation time 73891945 ps
CPU time 1.45 seconds
Started Jul 13 06:41:13 PM PDT 24
Finished Jul 13 06:41:16 PM PDT 24
Peak memory 219892 kb
Host smart-734d0c10-e6ec-4acd-878c-350dfab3c9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192762217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.1192762217
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_err.755281473
Short name T9
Test name
Test status
Simulation time 33405735 ps
CPU time 1.04 seconds
Started Jul 13 06:39:21 PM PDT 24
Finished Jul 13 06:39:24 PM PDT 24
Peak memory 219020 kb
Host smart-88438a69-1f03-4fed-a534-1a69c99c10e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755281473 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.755281473
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.349363351
Short name T265
Test name
Test status
Simulation time 34100229 ps
CPU time 1.28 seconds
Started Jul 13 06:34:01 PM PDT 24
Finished Jul 13 06:34:05 PM PDT 24
Peak memory 207008 kb
Host smart-5ba04900-e810-4697-9fe2-d58b6b8c5e80
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349363351 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.349363351
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3443780660
Short name T266
Test name
Test status
Simulation time 132626300 ps
CPU time 2.04 seconds
Started Jul 13 06:34:03 PM PDT 24
Finished Jul 13 06:34:07 PM PDT 24
Peak memory 207032 kb
Host smart-90b87bd2-8058-40a7-b939-c09c5d6142ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443780660 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.3443780660
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.970156340
Short name T1016
Test name
Test status
Simulation time 57452179 ps
CPU time 0.97 seconds
Started Jul 13 06:34:00 PM PDT 24
Finished Jul 13 06:34:03 PM PDT 24
Peak memory 206940 kb
Host smart-acda37ac-1f18-4926-b7f2-4b20c9717390
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970156340 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.970156340
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2118069098
Short name T1018
Test name
Test status
Simulation time 55690440 ps
CPU time 2.24 seconds
Started Jul 13 06:33:59 PM PDT 24
Finished Jul 13 06:34:03 PM PDT 24
Peak memory 215212 kb
Host smart-a389ca76-1646-487f-b739-123d492ec131
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118069098 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2118069098
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.752981895
Short name T274
Test name
Test status
Simulation time 11658537 ps
CPU time 0.91 seconds
Started Jul 13 06:33:59 PM PDT 24
Finished Jul 13 06:34:02 PM PDT 24
Peak memory 206892 kb
Host smart-6d64dfa4-bd4b-4b8b-bb25-187336b0c2fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752981895 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.752981895
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.2918998796
Short name T1065
Test name
Test status
Simulation time 91085332 ps
CPU time 0.88 seconds
Started Jul 13 06:33:59 PM PDT 24
Finished Jul 13 06:34:03 PM PDT 24
Peak memory 206716 kb
Host smart-13605cc1-7e22-406b-b110-b4011f657755
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918998796 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.2918998796
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2074688257
Short name T1101
Test name
Test status
Simulation time 63795722 ps
CPU time 1.18 seconds
Started Jul 13 06:33:58 PM PDT 24
Finished Jul 13 06:34:01 PM PDT 24
Peak memory 206956 kb
Host smart-315f9621-aa77-4cd5-aaba-573e52656476
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074688257 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.2074688257
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.2650807551
Short name T1007
Test name
Test status
Simulation time 84757344 ps
CPU time 3.15 seconds
Started Jul 13 06:33:58 PM PDT 24
Finished Jul 13 06:34:02 PM PDT 24
Peak memory 215196 kb
Host smart-b840c1cb-d38d-481c-afa6-192d8e3c4f9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650807551 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.2650807551
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3264402581
Short name T1039
Test name
Test status
Simulation time 24096410 ps
CPU time 1.18 seconds
Started Jul 13 06:34:02 PM PDT 24
Finished Jul 13 06:34:06 PM PDT 24
Peak memory 206944 kb
Host smart-f3146995-4a4d-4fab-afdd-b813ada6a42e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264402581 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.3264402581
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3433156114
Short name T1107
Test name
Test status
Simulation time 218136337 ps
CPU time 3.35 seconds
Started Jul 13 06:33:58 PM PDT 24
Finished Jul 13 06:34:03 PM PDT 24
Peak memory 207000 kb
Host smart-dc562997-be47-4b5e-964b-8586b7108b1e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433156114 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.3433156114
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3864214410
Short name T269
Test name
Test status
Simulation time 22087255 ps
CPU time 0.92 seconds
Started Jul 13 06:33:59 PM PDT 24
Finished Jul 13 06:34:03 PM PDT 24
Peak memory 206936 kb
Host smart-255a5081-4882-493e-be2a-91bc6673ea3f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864214410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.3864214410
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2953499577
Short name T1055
Test name
Test status
Simulation time 64798256 ps
CPU time 1.54 seconds
Started Jul 13 06:34:02 PM PDT 24
Finished Jul 13 06:34:06 PM PDT 24
Peak memory 215300 kb
Host smart-7c8a19bb-368c-4861-9e90-c03fe7993e2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953499577 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2953499577
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.3801245530
Short name T1041
Test name
Test status
Simulation time 63574224 ps
CPU time 0.98 seconds
Started Jul 13 06:33:58 PM PDT 24
Finished Jul 13 06:34:00 PM PDT 24
Peak memory 206932 kb
Host smart-25994d63-1ace-406c-8df1-affaa47b6847
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801245530 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3801245530
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.1989525969
Short name T1073
Test name
Test status
Simulation time 22663754 ps
CPU time 0.94 seconds
Started Jul 13 06:34:00 PM PDT 24
Finished Jul 13 06:34:03 PM PDT 24
Peak memory 207008 kb
Host smart-18bd07a7-f467-4f45-a4f5-93bc37659522
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989525969 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.1989525969
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.2061167820
Short name T1010
Test name
Test status
Simulation time 22206768 ps
CPU time 1.69 seconds
Started Jul 13 06:34:00 PM PDT 24
Finished Jul 13 06:34:04 PM PDT 24
Peak memory 215164 kb
Host smart-c110ac38-2e7a-48a5-90f4-9bf862296545
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061167820 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.2061167820
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.815899281
Short name T298
Test name
Test status
Simulation time 192021993 ps
CPU time 2.4 seconds
Started Jul 13 06:34:03 PM PDT 24
Finished Jul 13 06:34:07 PM PDT 24
Peak memory 206860 kb
Host smart-4b0be649-5803-4313-a211-befee1c20ec3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815899281 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.815899281
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1110339236
Short name T1037
Test name
Test status
Simulation time 25486528 ps
CPU time 1.04 seconds
Started Jul 13 06:34:03 PM PDT 24
Finished Jul 13 06:34:06 PM PDT 24
Peak memory 215168 kb
Host smart-ff2851cd-1e57-4421-8eff-35ce40fb6b56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110339236 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.1110339236
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.3226042266
Short name T1059
Test name
Test status
Simulation time 21656634 ps
CPU time 0.84 seconds
Started Jul 13 06:34:05 PM PDT 24
Finished Jul 13 06:34:07 PM PDT 24
Peak memory 206756 kb
Host smart-06823d4a-ae45-440e-ba07-254631511c1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226042266 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.3226042266
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.3326497184
Short name T1090
Test name
Test status
Simulation time 15125948 ps
CPU time 0.9 seconds
Started Jul 13 06:34:08 PM PDT 24
Finished Jul 13 06:34:10 PM PDT 24
Peak memory 206800 kb
Host smart-babb4f2e-9257-4f3e-889b-6eb373cdee1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326497184 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.3326497184
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2344939613
Short name T1124
Test name
Test status
Simulation time 98239053 ps
CPU time 1.38 seconds
Started Jul 13 06:34:06 PM PDT 24
Finished Jul 13 06:34:09 PM PDT 24
Peak memory 206952 kb
Host smart-3aae8f9a-0b35-405a-9f74-2f1a17acad9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344939613 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2344939613
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.1607382142
Short name T1043
Test name
Test status
Simulation time 44639453 ps
CPU time 1.41 seconds
Started Jul 13 06:34:06 PM PDT 24
Finished Jul 13 06:34:08 PM PDT 24
Peak memory 215260 kb
Host smart-85dc05b6-ee3f-4ed0-ab45-13cc0e495a9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607382142 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1607382142
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1755398694
Short name T1027
Test name
Test status
Simulation time 26382583 ps
CPU time 1.87 seconds
Started Jul 13 06:34:05 PM PDT 24
Finished Jul 13 06:34:08 PM PDT 24
Peak memory 215280 kb
Host smart-c6b1769f-3c9b-4ed5-8fa5-ac8ed3ecc8f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755398694 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.1755398694
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.2163477313
Short name T1024
Test name
Test status
Simulation time 38184804 ps
CPU time 0.82 seconds
Started Jul 13 06:34:04 PM PDT 24
Finished Jul 13 06:34:06 PM PDT 24
Peak memory 206744 kb
Host smart-75187635-6433-444c-b483-497037d00b1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163477313 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.2163477313
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.2210417842
Short name T1044
Test name
Test status
Simulation time 35255272 ps
CPU time 0.84 seconds
Started Jul 13 06:34:07 PM PDT 24
Finished Jul 13 06:34:09 PM PDT 24
Peak memory 206684 kb
Host smart-8868c994-bc8c-4976-ad6e-dbd473a18113
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210417842 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2210417842
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2577951719
Short name T1100
Test name
Test status
Simulation time 47407686 ps
CPU time 0.91 seconds
Started Jul 13 06:34:04 PM PDT 24
Finished Jul 13 06:34:07 PM PDT 24
Peak memory 206956 kb
Host smart-98a2c668-a4d9-4547-8e53-92e09a9128dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577951719 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.2577951719
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.5268729
Short name T1001
Test name
Test status
Simulation time 611578482 ps
CPU time 5.22 seconds
Started Jul 13 06:34:06 PM PDT 24
Finished Jul 13 06:34:13 PM PDT 24
Peak memory 215252 kb
Host smart-23fe892d-9115-401a-b148-1ca354c5598d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5268729 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.5268729
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1812532250
Short name T1095
Test name
Test status
Simulation time 104495630 ps
CPU time 1.67 seconds
Started Jul 13 06:34:07 PM PDT 24
Finished Jul 13 06:34:10 PM PDT 24
Peak memory 215220 kb
Host smart-4a9a3092-962d-4a0a-b7f9-6c8460550bf7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812532250 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1812532250
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3010678808
Short name T1020
Test name
Test status
Simulation time 33077537 ps
CPU time 1.47 seconds
Started Jul 13 06:34:07 PM PDT 24
Finished Jul 13 06:34:10 PM PDT 24
Peak memory 215232 kb
Host smart-ac097485-3177-4dcb-9bc4-f39168bc155e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010678808 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.3010678808
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.1801244015
Short name T284
Test name
Test status
Simulation time 15485919 ps
CPU time 0.95 seconds
Started Jul 13 06:34:10 PM PDT 24
Finished Jul 13 06:34:12 PM PDT 24
Peak memory 206932 kb
Host smart-ccd348d7-7a65-4e12-a523-e7038eafc0e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801244015 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.1801244015
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.3564817511
Short name T1102
Test name
Test status
Simulation time 55315923 ps
CPU time 0.95 seconds
Started Jul 13 06:34:11 PM PDT 24
Finished Jul 13 06:34:12 PM PDT 24
Peak memory 206868 kb
Host smart-5aec2083-e850-4ab6-8df7-0d38801b18d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564817511 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.3564817511
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.597835492
Short name T1118
Test name
Test status
Simulation time 100341206 ps
CPU time 1.26 seconds
Started Jul 13 06:34:10 PM PDT 24
Finished Jul 13 06:34:12 PM PDT 24
Peak memory 206764 kb
Host smart-ed079ee9-bb27-49da-9d66-7eec4d44e9e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597835492 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_ou
tstanding.597835492
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3574424186
Short name T999
Test name
Test status
Simulation time 188481793 ps
CPU time 5.01 seconds
Started Jul 13 06:34:06 PM PDT 24
Finished Jul 13 06:34:12 PM PDT 24
Peak memory 215124 kb
Host smart-f7946569-7577-4a58-881a-5c0e42374e14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574424186 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3574424186
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2011826292
Short name T1025
Test name
Test status
Simulation time 172098052 ps
CPU time 2.46 seconds
Started Jul 13 06:34:10 PM PDT 24
Finished Jul 13 06:34:14 PM PDT 24
Peak memory 207080 kb
Host smart-d9d3228c-c53d-4960-b5f9-02fe50211bbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011826292 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.2011826292
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.117480833
Short name T1079
Test name
Test status
Simulation time 38909288 ps
CPU time 2.06 seconds
Started Jul 13 06:34:17 PM PDT 24
Finished Jul 13 06:34:20 PM PDT 24
Peak memory 215240 kb
Host smart-b5981fa7-8bb0-4b4a-ba69-948ea8b1421a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117480833 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.117480833
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.1291305681
Short name T270
Test name
Test status
Simulation time 14865287 ps
CPU time 0.97 seconds
Started Jul 13 06:34:15 PM PDT 24
Finished Jul 13 06:34:18 PM PDT 24
Peak memory 206940 kb
Host smart-f7133ea2-b876-4fdc-b608-144a78051045
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291305681 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1291305681
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.1967839614
Short name T1075
Test name
Test status
Simulation time 25258711 ps
CPU time 0.9 seconds
Started Jul 13 06:34:07 PM PDT 24
Finished Jul 13 06:34:09 PM PDT 24
Peak memory 206816 kb
Host smart-8aa019e8-5259-4811-abc0-92d46a438acf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967839614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.1967839614
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.4294705441
Short name T1097
Test name
Test status
Simulation time 70989373 ps
CPU time 1.53 seconds
Started Jul 13 06:34:17 PM PDT 24
Finished Jul 13 06:34:20 PM PDT 24
Peak memory 206908 kb
Host smart-44a9c495-c048-4ad9-9459-5384bf5489cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294705441 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.4294705441
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.2995180797
Short name T1081
Test name
Test status
Simulation time 1086102761 ps
CPU time 3.79 seconds
Started Jul 13 06:34:07 PM PDT 24
Finished Jul 13 06:34:12 PM PDT 24
Peak memory 215224 kb
Host smart-519cd5a5-33c9-49f6-8963-01a412f20678
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995180797 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2995180797
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1941805134
Short name T306
Test name
Test status
Simulation time 142052739 ps
CPU time 1.55 seconds
Started Jul 13 06:34:07 PM PDT 24
Finished Jul 13 06:34:10 PM PDT 24
Peak memory 206936 kb
Host smart-be8a0a41-02b4-4b38-bb40-1afdedc51819
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941805134 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1941805134
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3541463112
Short name T1048
Test name
Test status
Simulation time 33607231 ps
CPU time 1.1 seconds
Started Jul 13 06:34:15 PM PDT 24
Finished Jul 13 06:34:17 PM PDT 24
Peak memory 206916 kb
Host smart-ac0f3c0d-dc94-44fa-9cfd-897adf31ce42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541463112 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.3541463112
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.1013831877
Short name T1087
Test name
Test status
Simulation time 23036428 ps
CPU time 0.91 seconds
Started Jul 13 06:34:16 PM PDT 24
Finished Jul 13 06:34:19 PM PDT 24
Peak memory 206888 kb
Host smart-458b4bb6-1247-43f5-93c2-c8ee1c2b8a7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013831877 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1013831877
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.206119208
Short name T1086
Test name
Test status
Simulation time 17063005 ps
CPU time 0.88 seconds
Started Jul 13 06:34:13 PM PDT 24
Finished Jul 13 06:34:15 PM PDT 24
Peak memory 206808 kb
Host smart-cbd7495c-e7b3-4a7c-82d8-172c2f4d3f4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206119208 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.206119208
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3740982879
Short name T1068
Test name
Test status
Simulation time 13826524 ps
CPU time 1.01 seconds
Started Jul 13 06:34:14 PM PDT 24
Finished Jul 13 06:34:15 PM PDT 24
Peak memory 206976 kb
Host smart-86fcd1b1-a662-4921-9675-eaab10f07ea5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740982879 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.3740982879
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.3947234620
Short name T1023
Test name
Test status
Simulation time 90254390 ps
CPU time 2.34 seconds
Started Jul 13 06:34:18 PM PDT 24
Finished Jul 13 06:34:21 PM PDT 24
Peak memory 223432 kb
Host smart-ea8c98c8-e539-4aac-b332-8d98644d29c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947234620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3947234620
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.528402178
Short name T1028
Test name
Test status
Simulation time 120584293 ps
CPU time 1.57 seconds
Started Jul 13 06:34:15 PM PDT 24
Finished Jul 13 06:34:18 PM PDT 24
Peak memory 206976 kb
Host smart-eaab41ea-eb57-4f35-9d2e-e0326a71fd12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528402178 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.528402178
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2967827900
Short name T1056
Test name
Test status
Simulation time 42011670 ps
CPU time 1.26 seconds
Started Jul 13 06:34:16 PM PDT 24
Finished Jul 13 06:34:18 PM PDT 24
Peak memory 215196 kb
Host smart-14b2b9f0-2770-4151-af92-0ecc66b55155
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967827900 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2967827900
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.878248232
Short name T1106
Test name
Test status
Simulation time 15876049 ps
CPU time 0.93 seconds
Started Jul 13 06:34:15 PM PDT 24
Finished Jul 13 06:34:18 PM PDT 24
Peak memory 206768 kb
Host smart-0e519862-f32e-4c60-ae21-78ca9904c189
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878248232 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.878248232
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.1241761340
Short name T1066
Test name
Test status
Simulation time 19743728 ps
CPU time 0.84 seconds
Started Jul 13 06:34:14 PM PDT 24
Finished Jul 13 06:34:16 PM PDT 24
Peak memory 206868 kb
Host smart-e6323b56-0de6-43a8-a47f-591657e34dcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241761340 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1241761340
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3547327437
Short name T285
Test name
Test status
Simulation time 42100128 ps
CPU time 1.1 seconds
Started Jul 13 06:34:15 PM PDT 24
Finished Jul 13 06:34:18 PM PDT 24
Peak memory 206708 kb
Host smart-071486fe-1f05-4018-b6f3-494bb5989bf1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547327437 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.3547327437
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.3866054356
Short name T1126
Test name
Test status
Simulation time 35121387 ps
CPU time 2.43 seconds
Started Jul 13 06:34:12 PM PDT 24
Finished Jul 13 06:34:15 PM PDT 24
Peak memory 215180 kb
Host smart-31270dff-830f-4589-889c-7cbcc0185f48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866054356 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.3866054356
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2365291432
Short name T308
Test name
Test status
Simulation time 149253230 ps
CPU time 1.55 seconds
Started Jul 13 06:34:14 PM PDT 24
Finished Jul 13 06:34:17 PM PDT 24
Peak memory 206980 kb
Host smart-bafbabeb-7367-48fb-ac6a-3dc7d8b57e3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365291432 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2365291432
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3123721911
Short name T1040
Test name
Test status
Simulation time 24391542 ps
CPU time 1.24 seconds
Started Jul 13 06:34:13 PM PDT 24
Finished Jul 13 06:34:15 PM PDT 24
Peak memory 215208 kb
Host smart-c088b900-e052-46d9-ae45-ef9dc6cbd88e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123721911 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.3123721911
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.548403462
Short name T283
Test name
Test status
Simulation time 13534868 ps
CPU time 0.91 seconds
Started Jul 13 06:34:15 PM PDT 24
Finished Jul 13 06:34:18 PM PDT 24
Peak memory 206956 kb
Host smart-a05f5fcd-7218-4631-adeb-8ee39de8224e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548403462 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.548403462
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.534890449
Short name T1128
Test name
Test status
Simulation time 33886414 ps
CPU time 0.82 seconds
Started Jul 13 06:34:16 PM PDT 24
Finished Jul 13 06:34:18 PM PDT 24
Peak memory 206656 kb
Host smart-44077108-6799-4414-ba73-7ed7635e7f48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534890449 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.534890449
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.561099232
Short name T1104
Test name
Test status
Simulation time 31464226 ps
CPU time 1.37 seconds
Started Jul 13 06:34:15 PM PDT 24
Finished Jul 13 06:34:18 PM PDT 24
Peak memory 207016 kb
Host smart-728d7f16-bddc-4494-a425-c665b105c8df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561099232 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_ou
tstanding.561099232
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.4037504797
Short name T1052
Test name
Test status
Simulation time 124577250 ps
CPU time 4.57 seconds
Started Jul 13 06:34:16 PM PDT 24
Finished Jul 13 06:34:22 PM PDT 24
Peak memory 215260 kb
Host smart-90a27d43-cd16-4cce-9f21-722a9a495d23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037504797 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.4037504797
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2479786660
Short name T1034
Test name
Test status
Simulation time 73036170 ps
CPU time 1.54 seconds
Started Jul 13 06:34:13 PM PDT 24
Finished Jul 13 06:34:15 PM PDT 24
Peak memory 207060 kb
Host smart-b2cfb0a8-0796-49d2-b354-a24f65a24a27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479786660 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.2479786660
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.774722131
Short name T1071
Test name
Test status
Simulation time 34914764 ps
CPU time 1.59 seconds
Started Jul 13 06:34:16 PM PDT 24
Finished Jul 13 06:34:19 PM PDT 24
Peak memory 223328 kb
Host smart-73158a2e-3df9-411f-8fa1-47d9be16aa67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774722131 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.774722131
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.3627748331
Short name T275
Test name
Test status
Simulation time 28265608 ps
CPU time 0.8 seconds
Started Jul 13 06:34:15 PM PDT 24
Finished Jul 13 06:34:17 PM PDT 24
Peak memory 206604 kb
Host smart-11cd019b-200b-45df-9444-04f179d9167f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627748331 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.3627748331
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.3800448854
Short name T1067
Test name
Test status
Simulation time 42576655 ps
CPU time 0.86 seconds
Started Jul 13 06:34:15 PM PDT 24
Finished Jul 13 06:34:18 PM PDT 24
Peak memory 206668 kb
Host smart-f9a18284-5a6c-4bc1-bd2e-9747d1e6db84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800448854 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.3800448854
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3043727842
Short name T268
Test name
Test status
Simulation time 36909293 ps
CPU time 1.45 seconds
Started Jul 13 06:34:13 PM PDT 24
Finished Jul 13 06:34:15 PM PDT 24
Peak memory 207032 kb
Host smart-567c0339-1145-46c8-b947-3cf02bce9c64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043727842 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.3043727842
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.3742711245
Short name T1103
Test name
Test status
Simulation time 37700630 ps
CPU time 1.52 seconds
Started Jul 13 06:34:15 PM PDT 24
Finished Jul 13 06:34:18 PM PDT 24
Peak memory 215328 kb
Host smart-3064d863-9ee6-4473-a994-d538958ce558
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742711245 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3742711245
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3369450873
Short name T1047
Test name
Test status
Simulation time 157626574 ps
CPU time 2.33 seconds
Started Jul 13 06:34:15 PM PDT 24
Finished Jul 13 06:34:18 PM PDT 24
Peak memory 215192 kb
Host smart-a36b7fb2-e1e7-4089-9237-6f6aadf3ca1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369450873 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3369450873
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1656884690
Short name T1096
Test name
Test status
Simulation time 71227598 ps
CPU time 1.37 seconds
Started Jul 13 06:34:15 PM PDT 24
Finished Jul 13 06:34:17 PM PDT 24
Peak memory 215176 kb
Host smart-7225d12c-3179-43d9-9bc5-27f0f07aeede
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656884690 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.1656884690
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1665012143
Short name T267
Test name
Test status
Simulation time 20968626 ps
CPU time 0.92 seconds
Started Jul 13 06:34:17 PM PDT 24
Finished Jul 13 06:34:19 PM PDT 24
Peak memory 206924 kb
Host smart-5fc05f8b-43eb-4823-a655-f3806d037aba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665012143 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1665012143
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.788366565
Short name T1015
Test name
Test status
Simulation time 26874260 ps
CPU time 0.89 seconds
Started Jul 13 06:34:17 PM PDT 24
Finished Jul 13 06:34:19 PM PDT 24
Peak memory 206800 kb
Host smart-470d4359-8722-4cf3-900a-6d73c9638257
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788366565 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.788366565
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1627252486
Short name T279
Test name
Test status
Simulation time 55665945 ps
CPU time 0.99 seconds
Started Jul 13 06:34:14 PM PDT 24
Finished Jul 13 06:34:16 PM PDT 24
Peak memory 206872 kb
Host smart-6705e5a6-2d96-4e3e-8cc6-ba6c237b3956
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627252486 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.1627252486
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.2495661049
Short name T1053
Test name
Test status
Simulation time 45563153 ps
CPU time 1.89 seconds
Started Jul 13 06:34:14 PM PDT 24
Finished Jul 13 06:34:16 PM PDT 24
Peak memory 215184 kb
Host smart-98694ed8-abda-453a-9c28-09b7602fe9a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495661049 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.2495661049
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1701275404
Short name T305
Test name
Test status
Simulation time 98973609 ps
CPU time 1.67 seconds
Started Jul 13 06:34:12 PM PDT 24
Finished Jul 13 06:34:14 PM PDT 24
Peak memory 206992 kb
Host smart-c9679653-c663-49b0-8cee-1e856c7088b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701275404 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1701275404
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.503764839
Short name T1072
Test name
Test status
Simulation time 21596955 ps
CPU time 1.37 seconds
Started Jul 13 06:34:19 PM PDT 24
Finished Jul 13 06:34:21 PM PDT 24
Peak memory 206648 kb
Host smart-2ee21d07-9828-45cf-b97a-3bd50d1949c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503764839 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.503764839
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2744594531
Short name T280
Test name
Test status
Simulation time 39792017 ps
CPU time 0.89 seconds
Started Jul 13 06:34:15 PM PDT 24
Finished Jul 13 06:34:18 PM PDT 24
Peak memory 206864 kb
Host smart-d73f363c-a2f7-4a23-a6ed-80fc10db3cb3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744594531 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2744594531
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.458201936
Short name T1122
Test name
Test status
Simulation time 34356473 ps
CPU time 0.92 seconds
Started Jul 13 06:34:13 PM PDT 24
Finished Jul 13 06:34:15 PM PDT 24
Peak memory 206804 kb
Host smart-68a6122a-b429-40e2-8d4e-0bbff0914021
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458201936 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.458201936
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.319901479
Short name T1057
Test name
Test status
Simulation time 68302430 ps
CPU time 1.47 seconds
Started Jul 13 06:34:15 PM PDT 24
Finished Jul 13 06:34:17 PM PDT 24
Peak memory 206916 kb
Host smart-e97b11e6-62c0-4171-b322-f166950975d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319901479 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_ou
tstanding.319901479
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.993320705
Short name T1022
Test name
Test status
Simulation time 179387126 ps
CPU time 1.84 seconds
Started Jul 13 06:34:14 PM PDT 24
Finished Jul 13 06:34:17 PM PDT 24
Peak memory 215172 kb
Host smart-b0180bdd-9bcf-4c94-bc8c-48c5c2a45314
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993320705 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.993320705
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1600147444
Short name T302
Test name
Test status
Simulation time 309130895 ps
CPU time 1.5 seconds
Started Jul 13 06:34:19 PM PDT 24
Finished Jul 13 06:34:21 PM PDT 24
Peak memory 206392 kb
Host smart-90162319-ca61-4bc5-9d27-ec45dc3cebf4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600147444 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1600147444
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.4011175452
Short name T278
Test name
Test status
Simulation time 336295704 ps
CPU time 1.1 seconds
Started Jul 13 06:34:01 PM PDT 24
Finished Jul 13 06:34:05 PM PDT 24
Peak memory 206992 kb
Host smart-586c838f-a666-4bdb-8267-3f35dc6a7acc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011175452 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.4011175452
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1193867627
Short name T1000
Test name
Test status
Simulation time 610739412 ps
CPU time 2.3 seconds
Started Jul 13 06:34:03 PM PDT 24
Finished Jul 13 06:34:07 PM PDT 24
Peak memory 206876 kb
Host smart-b3bb2064-baa5-4710-a4c8-f26724473c36
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193867627 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1193867627
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3388741811
Short name T1033
Test name
Test status
Simulation time 27432206 ps
CPU time 1.48 seconds
Started Jul 13 06:33:59 PM PDT 24
Finished Jul 13 06:34:02 PM PDT 24
Peak memory 215296 kb
Host smart-021e5e95-1f77-4085-9944-eeaea6b9773e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388741811 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3388741811
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.3729415735
Short name T1006
Test name
Test status
Simulation time 53165196 ps
CPU time 0.95 seconds
Started Jul 13 06:34:04 PM PDT 24
Finished Jul 13 06:34:06 PM PDT 24
Peak memory 206940 kb
Host smart-6314d725-e5ca-4b7f-a0af-275c31fecd8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729415735 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3729415735
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.889422713
Short name T1003
Test name
Test status
Simulation time 43250160 ps
CPU time 0.8 seconds
Started Jul 13 06:33:57 PM PDT 24
Finished Jul 13 06:33:59 PM PDT 24
Peak memory 206628 kb
Host smart-50cf8f97-dc97-489d-b7ef-44be55b948fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889422713 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.889422713
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3331804928
Short name T281
Test name
Test status
Simulation time 37970411 ps
CPU time 1.12 seconds
Started Jul 13 06:34:03 PM PDT 24
Finished Jul 13 06:34:06 PM PDT 24
Peak memory 206872 kb
Host smart-00cc9513-7b97-407c-8465-97c74c80d732
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331804928 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.3331804928
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.1750495731
Short name T1070
Test name
Test status
Simulation time 55682199 ps
CPU time 1.62 seconds
Started Jul 13 06:33:58 PM PDT 24
Finished Jul 13 06:34:00 PM PDT 24
Peak memory 223408 kb
Host smart-27880e40-6d8b-4836-b525-c61c0f2bb51a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750495731 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1750495731
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2484486384
Short name T1046
Test name
Test status
Simulation time 100679200 ps
CPU time 1.73 seconds
Started Jul 13 06:33:59 PM PDT 24
Finished Jul 13 06:34:03 PM PDT 24
Peak memory 207164 kb
Host smart-d3e43a60-da63-4c0a-9b13-ad56af1f50b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484486384 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.2484486384
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.1647990312
Short name T1005
Test name
Test status
Simulation time 16265262 ps
CPU time 0.97 seconds
Started Jul 13 06:34:14 PM PDT 24
Finished Jul 13 06:34:16 PM PDT 24
Peak memory 206868 kb
Host smart-55c5849b-9db9-43d5-b9ef-5255e8cdf4ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647990312 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.1647990312
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.1875221155
Short name T1009
Test name
Test status
Simulation time 108002727 ps
CPU time 0.88 seconds
Started Jul 13 06:34:22 PM PDT 24
Finished Jul 13 06:34:24 PM PDT 24
Peak memory 206800 kb
Host smart-d112c163-a392-4701-b71c-1c73975c14a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875221155 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.1875221155
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.3680966463
Short name T1088
Test name
Test status
Simulation time 54566252 ps
CPU time 0.75 seconds
Started Jul 13 06:34:19 PM PDT 24
Finished Jul 13 06:34:20 PM PDT 24
Peak memory 206684 kb
Host smart-a577e2ec-1cb9-419c-9be7-cb12956c9b07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680966463 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.3680966463
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.2499563589
Short name T1074
Test name
Test status
Simulation time 19144058 ps
CPU time 0.92 seconds
Started Jul 13 06:34:21 PM PDT 24
Finished Jul 13 06:34:22 PM PDT 24
Peak memory 206868 kb
Host smart-4d48af2f-de9f-4c7c-bb58-628ce39598d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499563589 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2499563589
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.3342898076
Short name T1019
Test name
Test status
Simulation time 14450185 ps
CPU time 0.9 seconds
Started Jul 13 06:34:22 PM PDT 24
Finished Jul 13 06:34:23 PM PDT 24
Peak memory 206864 kb
Host smart-4f60640b-167c-4ae6-9526-1571452351fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342898076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3342898076
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3778225003
Short name T1125
Test name
Test status
Simulation time 26216902 ps
CPU time 0.86 seconds
Started Jul 13 06:34:22 PM PDT 24
Finished Jul 13 06:34:24 PM PDT 24
Peak memory 206800 kb
Host smart-938c8101-1169-418e-bbed-b61d31c06ca7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778225003 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3778225003
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.544200952
Short name T1121
Test name
Test status
Simulation time 22037855 ps
CPU time 0.86 seconds
Started Jul 13 06:34:24 PM PDT 24
Finished Jul 13 06:34:26 PM PDT 24
Peak memory 206836 kb
Host smart-1bd9546b-0a04-47eb-a27e-f22e1d01c7a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544200952 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.544200952
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.3445594566
Short name T1085
Test name
Test status
Simulation time 26080857 ps
CPU time 0.87 seconds
Started Jul 13 06:34:21 PM PDT 24
Finished Jul 13 06:34:23 PM PDT 24
Peak memory 206856 kb
Host smart-5f7736a6-f306-49af-ac88-8215569a3ab7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445594566 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3445594566
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.1284099167
Short name T1060
Test name
Test status
Simulation time 51039368 ps
CPU time 0.89 seconds
Started Jul 13 06:34:22 PM PDT 24
Finished Jul 13 06:34:25 PM PDT 24
Peak memory 206860 kb
Host smart-e68e29c0-0262-4127-8134-3355837e2a40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284099167 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.1284099167
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.3195854916
Short name T1031
Test name
Test status
Simulation time 15746140 ps
CPU time 0.91 seconds
Started Jul 13 06:34:21 PM PDT 24
Finished Jul 13 06:34:23 PM PDT 24
Peak memory 206856 kb
Host smart-7785f1e6-3b4d-4b61-b3be-1ab23c562123
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195854916 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.3195854916
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2323724666
Short name T1058
Test name
Test status
Simulation time 91779007 ps
CPU time 1.24 seconds
Started Jul 13 06:33:59 PM PDT 24
Finished Jul 13 06:34:02 PM PDT 24
Peak memory 206968 kb
Host smart-906df69a-d5c3-4142-abeb-059e49e854a9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323724666 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.2323724666
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.951644274
Short name T1080
Test name
Test status
Simulation time 159692824 ps
CPU time 3.24 seconds
Started Jul 13 06:33:57 PM PDT 24
Finished Jul 13 06:34:01 PM PDT 24
Peak memory 206916 kb
Host smart-1956c668-6eff-4a3f-9db4-8badda6dfaeb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951644274 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.951644274
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.1557834343
Short name T1026
Test name
Test status
Simulation time 41512993 ps
CPU time 0.88 seconds
Started Jul 13 06:33:56 PM PDT 24
Finished Jul 13 06:33:58 PM PDT 24
Peak memory 206908 kb
Host smart-73f8c270-4aa8-4a45-bd98-3492a819f56c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557834343 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.1557834343
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1635122674
Short name T1012
Test name
Test status
Simulation time 49977120 ps
CPU time 1.73 seconds
Started Jul 13 06:34:03 PM PDT 24
Finished Jul 13 06:34:07 PM PDT 24
Peak memory 215124 kb
Host smart-88ecf224-8daa-456f-9bb5-907a96485398
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635122674 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.1635122674
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.595336344
Short name T1013
Test name
Test status
Simulation time 158712429 ps
CPU time 0.96 seconds
Started Jul 13 06:34:00 PM PDT 24
Finished Jul 13 06:34:03 PM PDT 24
Peak memory 206764 kb
Host smart-a7d7e497-1018-4a2d-a712-cfd41f1c3226
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595336344 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.595336344
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.3077561073
Short name T1008
Test name
Test status
Simulation time 23487390 ps
CPU time 0.87 seconds
Started Jul 13 06:34:02 PM PDT 24
Finished Jul 13 06:34:05 PM PDT 24
Peak memory 206852 kb
Host smart-688c8cc2-ecb0-4859-80d5-b2c7e0300c5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077561073 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.3077561073
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3408852505
Short name T1061
Test name
Test status
Simulation time 21313969 ps
CPU time 1.27 seconds
Started Jul 13 06:34:01 PM PDT 24
Finished Jul 13 06:34:04 PM PDT 24
Peak memory 206976 kb
Host smart-a54e6ac5-f0e6-4fc1-bd78-c41e7ae8a0a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408852505 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.3408852505
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.4255722138
Short name T1084
Test name
Test status
Simulation time 136103490 ps
CPU time 2.85 seconds
Started Jul 13 06:33:57 PM PDT 24
Finished Jul 13 06:34:01 PM PDT 24
Peak memory 215288 kb
Host smart-83390b8a-a199-465b-8eb0-3384fe9dac81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255722138 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.4255722138
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2904394939
Short name T304
Test name
Test status
Simulation time 56563216 ps
CPU time 1.88 seconds
Started Jul 13 06:33:58 PM PDT 24
Finished Jul 13 06:34:02 PM PDT 24
Peak memory 215112 kb
Host smart-fb5c8d51-656c-4314-9785-99da4c60dbf7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904394939 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.2904394939
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.699523818
Short name T1014
Test name
Test status
Simulation time 16964646 ps
CPU time 0.94 seconds
Started Jul 13 06:34:21 PM PDT 24
Finished Jul 13 06:34:22 PM PDT 24
Peak memory 206880 kb
Host smart-3876ad3a-1a98-446d-a78d-65cb21f078fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699523818 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.699523818
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.3706814248
Short name T1032
Test name
Test status
Simulation time 74360390 ps
CPU time 0.89 seconds
Started Jul 13 06:34:27 PM PDT 24
Finished Jul 13 06:34:28 PM PDT 24
Peak memory 206708 kb
Host smart-678be341-a301-4573-a07f-a4aa86a39808
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706814248 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.3706814248
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.4220110246
Short name T1123
Test name
Test status
Simulation time 14838193 ps
CPU time 0.93 seconds
Started Jul 13 06:34:23 PM PDT 24
Finished Jul 13 06:34:25 PM PDT 24
Peak memory 206860 kb
Host smart-0c138db9-36d1-44e5-9d9b-ffcaedc8c868
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220110246 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.4220110246
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.1541146315
Short name T1038
Test name
Test status
Simulation time 26640189 ps
CPU time 0.82 seconds
Started Jul 13 06:34:22 PM PDT 24
Finished Jul 13 06:34:24 PM PDT 24
Peak memory 206676 kb
Host smart-a5b58075-8ff3-427d-8bf7-6c9f24dd67e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541146315 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.1541146315
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.936047272
Short name T1063
Test name
Test status
Simulation time 11662245 ps
CPU time 0.87 seconds
Started Jul 13 06:34:23 PM PDT 24
Finished Jul 13 06:34:25 PM PDT 24
Peak memory 206896 kb
Host smart-61614c6e-12b9-41b0-8266-dcdff4fa43a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936047272 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.936047272
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.2807169231
Short name T1030
Test name
Test status
Simulation time 57974089 ps
CPU time 0.81 seconds
Started Jul 13 06:34:26 PM PDT 24
Finished Jul 13 06:34:28 PM PDT 24
Peak memory 206592 kb
Host smart-0fdc1580-6c3b-43b5-be7d-9ab7da2daaa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807169231 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.2807169231
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3377493641
Short name T1114
Test name
Test status
Simulation time 30201858 ps
CPU time 0.8 seconds
Started Jul 13 06:34:22 PM PDT 24
Finished Jul 13 06:34:24 PM PDT 24
Peak memory 206664 kb
Host smart-c861229e-b647-424a-ae45-3f35621b0004
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377493641 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3377493641
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.2660411492
Short name T1036
Test name
Test status
Simulation time 66326287 ps
CPU time 0.8 seconds
Started Jul 13 06:34:23 PM PDT 24
Finished Jul 13 06:34:25 PM PDT 24
Peak memory 206660 kb
Host smart-dfb8fe74-d1c4-4102-9d47-043258eb804b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660411492 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.2660411492
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.3644294965
Short name T1099
Test name
Test status
Simulation time 42345001 ps
CPU time 0.88 seconds
Started Jul 13 06:34:22 PM PDT 24
Finished Jul 13 06:34:24 PM PDT 24
Peak memory 206856 kb
Host smart-683399cd-e3ef-4268-a0a1-43f82b5cc94b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644294965 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3644294965
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.3954319194
Short name T1078
Test name
Test status
Simulation time 18427223 ps
CPU time 0.87 seconds
Started Jul 13 06:34:24 PM PDT 24
Finished Jul 13 06:34:26 PM PDT 24
Peak memory 206680 kb
Host smart-a8a4fe36-e479-4df1-b86c-1bb08ba1be5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954319194 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3954319194
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3072254698
Short name T1049
Test name
Test status
Simulation time 138239797 ps
CPU time 1.5 seconds
Started Jul 13 06:34:04 PM PDT 24
Finished Jul 13 06:34:07 PM PDT 24
Peak memory 206952 kb
Host smart-cb559264-cab7-46b6-b93c-73b956c7dfa2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072254698 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.3072254698
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.354220439
Short name T276
Test name
Test status
Simulation time 159047217 ps
CPU time 3.37 seconds
Started Jul 13 06:33:58 PM PDT 24
Finished Jul 13 06:34:03 PM PDT 24
Peak memory 206916 kb
Host smart-e7c215d2-3af5-4be5-a533-de8a7726b530
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354220439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.354220439
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1036242201
Short name T277
Test name
Test status
Simulation time 15063810 ps
CPU time 0.9 seconds
Started Jul 13 06:33:58 PM PDT 24
Finished Jul 13 06:34:00 PM PDT 24
Peak memory 206908 kb
Host smart-f3436313-ae1a-44f8-b514-2f488edc7e31
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036242201 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.1036242201
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.490366414
Short name T1119
Test name
Test status
Simulation time 95176861 ps
CPU time 1.25 seconds
Started Jul 13 06:33:59 PM PDT 24
Finished Jul 13 06:34:03 PM PDT 24
Peak memory 215216 kb
Host smart-3b37ac65-a466-4310-95c0-116aa98278c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490366414 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.490366414
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.4227842739
Short name T271
Test name
Test status
Simulation time 13374159 ps
CPU time 0.97 seconds
Started Jul 13 06:34:00 PM PDT 24
Finished Jul 13 06:34:03 PM PDT 24
Peak memory 206944 kb
Host smart-a6effd26-f6e1-475a-8b61-e5168ef9449b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227842739 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.4227842739
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.747288174
Short name T1115
Test name
Test status
Simulation time 28015277 ps
CPU time 0.95 seconds
Started Jul 13 06:33:59 PM PDT 24
Finished Jul 13 06:34:03 PM PDT 24
Peak memory 206804 kb
Host smart-8df63da8-e4bc-4ed8-a8a3-efddd87231b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747288174 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.747288174
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1805964583
Short name T1111
Test name
Test status
Simulation time 139849143 ps
CPU time 1.25 seconds
Started Jul 13 06:34:00 PM PDT 24
Finished Jul 13 06:34:04 PM PDT 24
Peak memory 206944 kb
Host smart-9f8fcf57-afc5-42c9-9e06-42e40cf2630b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805964583 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.1805964583
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.4246938803
Short name T1082
Test name
Test status
Simulation time 112306114 ps
CPU time 1.78 seconds
Started Jul 13 06:33:56 PM PDT 24
Finished Jul 13 06:33:58 PM PDT 24
Peak memory 215180 kb
Host smart-64d5ae17-c2d7-43e8-a6f5-dd0c4c5799ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246938803 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.4246938803
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2578507807
Short name T1116
Test name
Test status
Simulation time 51793769 ps
CPU time 1.73 seconds
Started Jul 13 06:33:57 PM PDT 24
Finished Jul 13 06:33:59 PM PDT 24
Peak memory 206872 kb
Host smart-6f8f64e0-24cf-487f-8fbc-fc3d979063e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578507807 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.2578507807
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.3584461895
Short name T1110
Test name
Test status
Simulation time 22185553 ps
CPU time 0.91 seconds
Started Jul 13 06:34:22 PM PDT 24
Finished Jul 13 06:34:24 PM PDT 24
Peak memory 206856 kb
Host smart-656d5a0d-c8bd-473d-b351-9e97b710f210
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584461895 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.3584461895
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.1447189100
Short name T1051
Test name
Test status
Simulation time 19136088 ps
CPU time 0.83 seconds
Started Jul 13 06:34:24 PM PDT 24
Finished Jul 13 06:34:26 PM PDT 24
Peak memory 206680 kb
Host smart-728ab98e-0929-484b-957a-3fc073b133bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447189100 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1447189100
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.3204821779
Short name T1042
Test name
Test status
Simulation time 25812679 ps
CPU time 0.91 seconds
Started Jul 13 06:34:22 PM PDT 24
Finished Jul 13 06:34:24 PM PDT 24
Peak memory 206856 kb
Host smart-e8340daf-d97e-43a6-a885-d812a22f007b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204821779 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3204821779
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.4026592674
Short name T1021
Test name
Test status
Simulation time 11545103 ps
CPU time 0.85 seconds
Started Jul 13 06:34:27 PM PDT 24
Finished Jul 13 06:34:28 PM PDT 24
Peak memory 206728 kb
Host smart-566dbb2a-d84b-4e67-974a-c9c9efed9339
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026592674 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.4026592674
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.921102734
Short name T1002
Test name
Test status
Simulation time 17415826 ps
CPU time 0.94 seconds
Started Jul 13 06:34:22 PM PDT 24
Finished Jul 13 06:34:24 PM PDT 24
Peak memory 206860 kb
Host smart-6f9b7ef0-9b84-418d-8dde-89459fd34234
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921102734 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.921102734
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.1593992594
Short name T1017
Test name
Test status
Simulation time 12091589 ps
CPU time 0.9 seconds
Started Jul 13 06:34:24 PM PDT 24
Finished Jul 13 06:34:26 PM PDT 24
Peak memory 206800 kb
Host smart-6caf1d5c-4390-4419-b52e-214307606c4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593992594 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1593992594
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.3254123986
Short name T1117
Test name
Test status
Simulation time 15704602 ps
CPU time 0.87 seconds
Started Jul 13 06:34:20 PM PDT 24
Finished Jul 13 06:34:21 PM PDT 24
Peak memory 206816 kb
Host smart-27fee697-1067-4f1f-8391-c4535198ef09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254123986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.3254123986
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.863521328
Short name T1105
Test name
Test status
Simulation time 12195514 ps
CPU time 0.91 seconds
Started Jul 13 06:34:22 PM PDT 24
Finished Jul 13 06:34:25 PM PDT 24
Peak memory 206860 kb
Host smart-17f23e5a-7987-43f7-b7e2-e24e7062cbbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863521328 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.863521328
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.1929747325
Short name T1029
Test name
Test status
Simulation time 60758051 ps
CPU time 0.85 seconds
Started Jul 13 06:34:24 PM PDT 24
Finished Jul 13 06:34:26 PM PDT 24
Peak memory 206864 kb
Host smart-3f6532c6-ca5a-49bb-a431-0fa8e2f773b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929747325 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.1929747325
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.2926204879
Short name T1094
Test name
Test status
Simulation time 23877736 ps
CPU time 0.86 seconds
Started Jul 13 06:34:23 PM PDT 24
Finished Jul 13 06:34:25 PM PDT 24
Peak memory 206800 kb
Host smart-4c8ef62e-5d9a-46b2-b987-10be713a09ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926204879 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.2926204879
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1137413477
Short name T1093
Test name
Test status
Simulation time 16210912 ps
CPU time 1.05 seconds
Started Jul 13 06:33:59 PM PDT 24
Finished Jul 13 06:34:02 PM PDT 24
Peak memory 206980 kb
Host smart-c8405bec-8427-4825-97b0-0e9cc31bae40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137413477 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1137413477
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.594123881
Short name T1050
Test name
Test status
Simulation time 59541039 ps
CPU time 0.85 seconds
Started Jul 13 06:33:57 PM PDT 24
Finished Jul 13 06:33:59 PM PDT 24
Peak memory 206752 kb
Host smart-09341d9a-7f34-4e9f-9e5a-a82afd822466
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594123881 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.594123881
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.1986569999
Short name T1113
Test name
Test status
Simulation time 13663756 ps
CPU time 0.95 seconds
Started Jul 13 06:34:01 PM PDT 24
Finished Jul 13 06:34:04 PM PDT 24
Peak memory 206856 kb
Host smart-f3e3325c-2404-4f59-9aeb-28ad2f8bf214
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986569999 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1986569999
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3909143789
Short name T1127
Test name
Test status
Simulation time 70979874 ps
CPU time 1.35 seconds
Started Jul 13 06:33:58 PM PDT 24
Finished Jul 13 06:34:01 PM PDT 24
Peak memory 207060 kb
Host smart-f9f52856-c7e0-4563-abfe-f48d23115a98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909143789 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.3909143789
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.1357820846
Short name T1045
Test name
Test status
Simulation time 208947538 ps
CPU time 3.82 seconds
Started Jul 13 06:33:57 PM PDT 24
Finished Jul 13 06:34:01 PM PDT 24
Peak memory 215264 kb
Host smart-72389e25-4daa-4cb6-b836-ec51c2295c50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357820846 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.1357820846
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1542957152
Short name T1011
Test name
Test status
Simulation time 44250031 ps
CPU time 1.52 seconds
Started Jul 13 06:33:57 PM PDT 24
Finished Jul 13 06:34:00 PM PDT 24
Peak memory 207076 kb
Host smart-d47f5ef3-a340-42a8-a819-b431ff5fb13d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542957152 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1542957152
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.22785566
Short name T1077
Test name
Test status
Simulation time 39794815 ps
CPU time 1.17 seconds
Started Jul 13 06:34:06 PM PDT 24
Finished Jul 13 06:34:09 PM PDT 24
Peak memory 216848 kb
Host smart-c5057787-1905-4852-9a4f-9381757538e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22785566 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.22785566
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.2483478563
Short name T1004
Test name
Test status
Simulation time 41461810 ps
CPU time 0.93 seconds
Started Jul 13 06:34:00 PM PDT 24
Finished Jul 13 06:34:03 PM PDT 24
Peak memory 206944 kb
Host smart-3a229e47-76fe-443f-a719-9c137b2a3903
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483478563 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.2483478563
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.4290870998
Short name T1092
Test name
Test status
Simulation time 12924274 ps
CPU time 0.87 seconds
Started Jul 13 06:34:03 PM PDT 24
Finished Jul 13 06:34:06 PM PDT 24
Peak memory 206800 kb
Host smart-eaf3f933-0128-4afe-8712-363ec5b6516f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290870998 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.4290870998
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.518219268
Short name T1069
Test name
Test status
Simulation time 23833456 ps
CPU time 1.22 seconds
Started Jul 13 06:34:06 PM PDT 24
Finished Jul 13 06:34:08 PM PDT 24
Peak memory 206916 kb
Host smart-ddde13c5-d1fc-4c21-90d0-bb1daaa83cc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518219268 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_out
standing.518219268
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3092313266
Short name T1129
Test name
Test status
Simulation time 392935401 ps
CPU time 3.82 seconds
Started Jul 13 06:33:59 PM PDT 24
Finished Jul 13 06:34:05 PM PDT 24
Peak memory 215160 kb
Host smart-4bd573f5-e4c8-4654-b686-e52975cca7d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092313266 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3092313266
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1540012281
Short name T1120
Test name
Test status
Simulation time 212192114 ps
CPU time 2.62 seconds
Started Jul 13 06:34:01 PM PDT 24
Finished Jul 13 06:34:06 PM PDT 24
Peak memory 215656 kb
Host smart-112f407d-a207-44a8-9c88-f733330ab635
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540012281 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.1540012281
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1858275826
Short name T1062
Test name
Test status
Simulation time 42151454 ps
CPU time 1.43 seconds
Started Jul 13 06:34:11 PM PDT 24
Finished Jul 13 06:34:13 PM PDT 24
Peak memory 215208 kb
Host smart-9de06142-1c8c-4616-818f-8adc42f2248a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858275826 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1858275826
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.80434242
Short name T272
Test name
Test status
Simulation time 20305739 ps
CPU time 0.88 seconds
Started Jul 13 06:34:06 PM PDT 24
Finished Jul 13 06:34:08 PM PDT 24
Peak memory 206944 kb
Host smart-046e72a0-adb8-46c7-851d-ed7f5cda78b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80434242 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.80434242
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.2501272134
Short name T1054
Test name
Test status
Simulation time 23239907 ps
CPU time 0.83 seconds
Started Jul 13 06:34:10 PM PDT 24
Finished Jul 13 06:34:12 PM PDT 24
Peak memory 206960 kb
Host smart-6aebeb6d-d640-4dfa-9c5c-0dc36b46b686
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501272134 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.2501272134
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2117636876
Short name T1064
Test name
Test status
Simulation time 17788494 ps
CPU time 1.05 seconds
Started Jul 13 06:34:08 PM PDT 24
Finished Jul 13 06:34:10 PM PDT 24
Peak memory 206872 kb
Host smart-7cb7e4a2-d666-4fff-afdf-5e48f9232764
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117636876 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.2117636876
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.3404602040
Short name T1076
Test name
Test status
Simulation time 41938479 ps
CPU time 2.77 seconds
Started Jul 13 06:34:05 PM PDT 24
Finished Jul 13 06:34:10 PM PDT 24
Peak memory 215244 kb
Host smart-02395d33-7f1c-4a2e-97f9-5e391cf2a0a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404602040 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.3404602040
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3472701168
Short name T297
Test name
Test status
Simulation time 74156536 ps
CPU time 2.36 seconds
Started Jul 13 06:34:08 PM PDT 24
Finished Jul 13 06:34:12 PM PDT 24
Peak memory 215056 kb
Host smart-5d476e41-04aa-41f4-aa2c-159a135c2486
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472701168 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.3472701168
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1242120775
Short name T1035
Test name
Test status
Simulation time 51209949 ps
CPU time 1.37 seconds
Started Jul 13 06:34:06 PM PDT 24
Finished Jul 13 06:34:09 PM PDT 24
Peak memory 217936 kb
Host smart-222cab0c-557e-4839-bdae-e115468fcec1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242120775 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1242120775
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.3326829526
Short name T1109
Test name
Test status
Simulation time 22185187 ps
CPU time 0.93 seconds
Started Jul 13 06:34:05 PM PDT 24
Finished Jul 13 06:34:08 PM PDT 24
Peak memory 206912 kb
Host smart-aecfb452-1e10-411a-879a-f9ec3aa89da6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326829526 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.3326829526
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.23184430
Short name T1108
Test name
Test status
Simulation time 23102718 ps
CPU time 0.86 seconds
Started Jul 13 06:34:10 PM PDT 24
Finished Jul 13 06:34:11 PM PDT 24
Peak memory 206708 kb
Host smart-42746807-aba6-40c3-bf21-25682def1ee1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23184430 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.23184430
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.960647160
Short name T282
Test name
Test status
Simulation time 47591710 ps
CPU time 1.07 seconds
Started Jul 13 06:34:08 PM PDT 24
Finished Jul 13 06:34:10 PM PDT 24
Peak memory 206868 kb
Host smart-cb760be1-8053-42bd-8de7-e7a0315568cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960647160 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_out
standing.960647160
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.833233654
Short name T1089
Test name
Test status
Simulation time 159847913 ps
CPU time 1.81 seconds
Started Jul 13 06:34:06 PM PDT 24
Finished Jul 13 06:34:09 PM PDT 24
Peak memory 215132 kb
Host smart-e4edeb7f-f626-4e87-840c-215b13bb574a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833233654 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.833233654
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.4211253618
Short name T1091
Test name
Test status
Simulation time 613508645 ps
CPU time 1.83 seconds
Started Jul 13 06:34:08 PM PDT 24
Finished Jul 13 06:34:11 PM PDT 24
Peak memory 206992 kb
Host smart-4cd0b620-6f29-4d12-9ee0-28e1ca9dfd50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211253618 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.4211253618
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.307586564
Short name T1130
Test name
Test status
Simulation time 36917368 ps
CPU time 1.24 seconds
Started Jul 13 06:34:08 PM PDT 24
Finished Jul 13 06:34:10 PM PDT 24
Peak memory 216676 kb
Host smart-6d43fd93-95b2-4912-bf1d-2d16e02c0e88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307586564 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.307586564
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.4264809187
Short name T273
Test name
Test status
Simulation time 12302625 ps
CPU time 0.93 seconds
Started Jul 13 06:34:06 PM PDT 24
Finished Jul 13 06:34:09 PM PDT 24
Peak memory 206916 kb
Host smart-85455371-8529-47cf-b658-99fec165d2b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264809187 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.4264809187
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2328628057
Short name T1083
Test name
Test status
Simulation time 14023924 ps
CPU time 0.92 seconds
Started Jul 13 06:34:10 PM PDT 24
Finished Jul 13 06:34:11 PM PDT 24
Peak memory 206796 kb
Host smart-144a57ff-b71d-4607-8441-993c097061a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328628057 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2328628057
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.77998192
Short name T1112
Test name
Test status
Simulation time 34701153 ps
CPU time 1.48 seconds
Started Jul 13 06:34:07 PM PDT 24
Finished Jul 13 06:34:10 PM PDT 24
Peak memory 206996 kb
Host smart-1fe25c2c-c9cd-4694-bc59-bcdee643342a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77998192 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_outs
tanding.77998192
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.1195825148
Short name T1098
Test name
Test status
Simulation time 146968181 ps
CPU time 2.62 seconds
Started Jul 13 06:34:06 PM PDT 24
Finished Jul 13 06:34:10 PM PDT 24
Peak memory 215276 kb
Host smart-1934d318-d180-4715-a941-33ca21efa751
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195825148 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1195825148
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1855564132
Short name T299
Test name
Test status
Simulation time 136615078 ps
CPU time 1.51 seconds
Started Jul 13 06:34:06 PM PDT 24
Finished Jul 13 06:34:09 PM PDT 24
Peak memory 206944 kb
Host smart-ffc0d448-f926-47bf-8a99-857551d46bdf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855564132 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.1855564132
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.666644343
Short name T451
Test name
Test status
Simulation time 24879960 ps
CPU time 1.14 seconds
Started Jul 13 06:38:39 PM PDT 24
Finished Jul 13 06:38:43 PM PDT 24
Peak memory 220168 kb
Host smart-7873a894-ccda-4040-948e-59fb9bfa23cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666644343 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.666644343
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_disable.408596835
Short name T821
Test name
Test status
Simulation time 19147642 ps
CPU time 0.87 seconds
Started Jul 13 06:38:41 PM PDT 24
Finished Jul 13 06:38:43 PM PDT 24
Peak memory 215692 kb
Host smart-c64973db-0509-4321-bbb4-4be3d6ab96c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408596835 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.408596835
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.1826799338
Short name T807
Test name
Test status
Simulation time 26321861 ps
CPU time 1.08 seconds
Started Jul 13 06:38:38 PM PDT 24
Finished Jul 13 06:38:41 PM PDT 24
Peak memory 218676 kb
Host smart-7b2d71e4-499c-4648-a7ce-3f9f978b368a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826799338 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.1826799338
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.171790713
Short name T462
Test name
Test status
Simulation time 21810425 ps
CPU time 1.07 seconds
Started Jul 13 06:38:40 PM PDT 24
Finished Jul 13 06:38:43 PM PDT 24
Peak memory 224224 kb
Host smart-c11dabf9-30af-4e17-b1bb-d4fa2c914024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171790713 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.171790713
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.3694202638
Short name T447
Test name
Test status
Simulation time 82331814 ps
CPU time 1.48 seconds
Started Jul 13 06:38:40 PM PDT 24
Finished Jul 13 06:38:44 PM PDT 24
Peak memory 219184 kb
Host smart-c2b19972-7fc5-4f9f-a775-e4659fbd314a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694202638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.3694202638
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.3970547461
Short name T109
Test name
Test status
Simulation time 21409257 ps
CPU time 1.11 seconds
Started Jul 13 06:38:43 PM PDT 24
Finished Jul 13 06:38:45 PM PDT 24
Peak memory 215692 kb
Host smart-be763a95-78ef-4564-b935-8cb02ca4c284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970547461 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.3970547461
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.2716166548
Short name T560
Test name
Test status
Simulation time 27118682 ps
CPU time 0.91 seconds
Started Jul 13 06:38:42 PM PDT 24
Finished Jul 13 06:38:44 PM PDT 24
Peak memory 207412 kb
Host smart-61f8755d-4c15-4ce6-a955-3c30b5393fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716166548 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.2716166548
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.2700774296
Short name T67
Test name
Test status
Simulation time 1008719248 ps
CPU time 8.4 seconds
Started Jul 13 06:38:41 PM PDT 24
Finished Jul 13 06:38:51 PM PDT 24
Peak memory 238504 kb
Host smart-db30af8b-650e-4968-bf54-4fbd4b017511
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700774296 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.2700774296
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.2380788102
Short name T612
Test name
Test status
Simulation time 22509619 ps
CPU time 0.97 seconds
Started Jul 13 06:38:41 PM PDT 24
Finished Jul 13 06:38:44 PM PDT 24
Peak memory 215468 kb
Host smart-da7f47ad-20e6-4fcb-b5f0-b9c02e48765c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380788102 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2380788102
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.4163490186
Short name T504
Test name
Test status
Simulation time 661821054 ps
CPU time 3.64 seconds
Started Jul 13 06:38:44 PM PDT 24
Finished Jul 13 06:38:48 PM PDT 24
Peak memory 215600 kb
Host smart-71972caf-a09e-490e-95ec-23011e3017d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163490186 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.4163490186
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.258386459
Short name T242
Test name
Test status
Simulation time 39474407715 ps
CPU time 251.48 seconds
Started Jul 13 06:38:40 PM PDT 24
Finished Jul 13 06:42:54 PM PDT 24
Peak memory 219784 kb
Host smart-d0be8a6f-fe9a-4967-a4d9-f7cd805fd32a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258386459 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.258386459
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.2402549598
Short name T315
Test name
Test status
Simulation time 54587093 ps
CPU time 1.12 seconds
Started Jul 13 06:38:43 PM PDT 24
Finished Jul 13 06:38:45 PM PDT 24
Peak memory 218984 kb
Host smart-dec0fa46-99f8-4243-8573-05916806b444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402549598 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.2402549598
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.1920906078
Short name T921
Test name
Test status
Simulation time 16927872 ps
CPU time 0.93 seconds
Started Jul 13 06:38:50 PM PDT 24
Finished Jul 13 06:38:51 PM PDT 24
Peak memory 207024 kb
Host smart-27bdd31c-a97b-4c86-999f-5604a676b6cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920906078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1920906078
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.4265397350
Short name T658
Test name
Test status
Simulation time 13199735 ps
CPU time 0.82 seconds
Started Jul 13 06:38:47 PM PDT 24
Finished Jul 13 06:38:48 PM PDT 24
Peak memory 207528 kb
Host smart-56cd8552-bd02-4788-b377-9ba53bc10b62
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265397350 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.4265397350
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.3560729633
Short name T310
Test name
Test status
Simulation time 258341009 ps
CPU time 1.41 seconds
Started Jul 13 06:38:46 PM PDT 24
Finished Jul 13 06:38:49 PM PDT 24
Peak memory 217336 kb
Host smart-6b9206c7-10da-4b26-bc1f-5d1f8916ac68
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560729633 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.3560729633
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.2889748526
Short name T458
Test name
Test status
Simulation time 22396393 ps
CPU time 1.15 seconds
Started Jul 13 06:38:53 PM PDT 24
Finished Jul 13 06:38:54 PM PDT 24
Peak memory 219024 kb
Host smart-09e4de16-7d3e-4081-a1b6-61e4d436fbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889748526 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.2889748526
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.2496827484
Short name T677
Test name
Test status
Simulation time 48185110 ps
CPU time 1.6 seconds
Started Jul 13 06:38:45 PM PDT 24
Finished Jul 13 06:38:47 PM PDT 24
Peak memory 219932 kb
Host smart-6433b18b-e969-48dd-b6ad-487fc37ebd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496827484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2496827484
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.1611164673
Short name T650
Test name
Test status
Simulation time 35593623 ps
CPU time 0.85 seconds
Started Jul 13 06:38:38 PM PDT 24
Finished Jul 13 06:38:40 PM PDT 24
Peak memory 215952 kb
Host smart-b65681b0-d892-4bc5-ab82-c9fe5835f14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611164673 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.1611164673
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_smoke.1646107340
Short name T443
Test name
Test status
Simulation time 50646374 ps
CPU time 0.91 seconds
Started Jul 13 06:38:42 PM PDT 24
Finished Jul 13 06:38:44 PM PDT 24
Peak memory 215640 kb
Host smart-aab33d43-207a-4531-8b9f-0d227bacf825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646107340 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1646107340
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.3658979842
Short name T540
Test name
Test status
Simulation time 589227116 ps
CPU time 3.48 seconds
Started Jul 13 06:38:39 PM PDT 24
Finished Jul 13 06:38:44 PM PDT 24
Peak memory 217516 kb
Host smart-72dfef35-aaf8-42ab-9ae6-2deee2c774a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658979842 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.3658979842
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.3272074764
Short name T235
Test name
Test status
Simulation time 105291291803 ps
CPU time 2549.97 seconds
Started Jul 13 06:38:42 PM PDT 24
Finished Jul 13 07:21:13 PM PDT 24
Peak memory 233648 kb
Host smart-c8bb3229-86ca-4802-b992-cad5870afe7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272074764 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.3272074764
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert_test.1741186757
Short name T611
Test name
Test status
Simulation time 32048821 ps
CPU time 0.96 seconds
Started Jul 13 06:39:21 PM PDT 24
Finished Jul 13 06:39:24 PM PDT 24
Peak memory 215228 kb
Host smart-69b4f9a8-191e-49c7-a76a-b29ec5777fab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741186757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.1741186757
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.3271805538
Short name T225
Test name
Test status
Simulation time 28672179 ps
CPU time 0.83 seconds
Started Jul 13 06:39:10 PM PDT 24
Finished Jul 13 06:39:13 PM PDT 24
Peak memory 215740 kb
Host smart-c1e56eab-850a-47fb-8438-49212b4a06df
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271805538 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.3271805538
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_err.3287554033
Short name T902
Test name
Test status
Simulation time 56455222 ps
CPU time 0.9 seconds
Started Jul 13 06:39:09 PM PDT 24
Finished Jul 13 06:39:12 PM PDT 24
Peak memory 218732 kb
Host smart-5cc74adb-1b8b-4be7-a93f-c5091cca216a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287554033 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.3287554033
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.2053659252
Short name T474
Test name
Test status
Simulation time 62170283 ps
CPU time 1.59 seconds
Started Jul 13 06:39:10 PM PDT 24
Finished Jul 13 06:39:14 PM PDT 24
Peak memory 218792 kb
Host smart-53b19565-a114-4b04-b989-29c34bf1f7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053659252 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.2053659252
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.243554937
Short name T501
Test name
Test status
Simulation time 20956953 ps
CPU time 1.13 seconds
Started Jul 13 06:39:09 PM PDT 24
Finished Jul 13 06:39:13 PM PDT 24
Peak memory 215792 kb
Host smart-629bdfd8-8eb0-4378-b683-35bb9b8e6ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243554937 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.243554937
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.1750140492
Short name T599
Test name
Test status
Simulation time 19592942 ps
CPU time 1.03 seconds
Started Jul 13 06:39:13 PM PDT 24
Finished Jul 13 06:39:15 PM PDT 24
Peak memory 215612 kb
Host smart-b0d75dfb-d947-4a05-9846-c302bbd5c666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750140492 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1750140492
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.1728641143
Short name T478
Test name
Test status
Simulation time 24294387 ps
CPU time 1.08 seconds
Started Jul 13 06:39:12 PM PDT 24
Finished Jul 13 06:39:15 PM PDT 24
Peak memory 215564 kb
Host smart-5d723efc-401a-4ce0-a653-264f420c53dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728641143 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1728641143
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.2409823428
Short name T243
Test name
Test status
Simulation time 35859029194 ps
CPU time 260.15 seconds
Started Jul 13 06:39:10 PM PDT 24
Finished Jul 13 06:43:32 PM PDT 24
Peak memory 223936 kb
Host smart-2ad51031-db6d-4aa1-bfb8-614a3069e641
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409823428 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.2409823428
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.3630516340
Short name T72
Test name
Test status
Simulation time 40393612 ps
CPU time 1.28 seconds
Started Jul 13 06:41:16 PM PDT 24
Finished Jul 13 06:41:20 PM PDT 24
Peak memory 221524 kb
Host smart-a6a404ae-19c5-411c-ac7a-e8e657caa3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630516340 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.3630516340
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/101.edn_alert.1924777954
Short name T399
Test name
Test status
Simulation time 39170193 ps
CPU time 1.15 seconds
Started Jul 13 06:41:15 PM PDT 24
Finished Jul 13 06:41:19 PM PDT 24
Peak memory 220172 kb
Host smart-b9226e08-b8a8-465e-a70d-44a05c30bbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924777954 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.1924777954
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.37121692
Short name T52
Test name
Test status
Simulation time 30655071 ps
CPU time 1.37 seconds
Started Jul 13 06:41:15 PM PDT 24
Finished Jul 13 06:41:19 PM PDT 24
Peak memory 218872 kb
Host smart-7c7efd9a-9528-4ce9-9d38-77208f058273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37121692 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.37121692
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.515762151
Short name T982
Test name
Test status
Simulation time 26913114 ps
CPU time 1.36 seconds
Started Jul 13 06:41:18 PM PDT 24
Finished Jul 13 06:41:21 PM PDT 24
Peak memory 219868 kb
Host smart-84142534-9fec-4ad0-9818-da5e112decf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515762151 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.515762151
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.799218784
Short name T748
Test name
Test status
Simulation time 59579747 ps
CPU time 1.07 seconds
Started Jul 13 06:41:14 PM PDT 24
Finished Jul 13 06:41:16 PM PDT 24
Peak memory 219240 kb
Host smart-acf47e12-fa0c-4a0c-8db2-c01dc217d592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799218784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.799218784
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.360879301
Short name T762
Test name
Test status
Simulation time 38184605 ps
CPU time 1.19 seconds
Started Jul 13 06:41:13 PM PDT 24
Finished Jul 13 06:41:16 PM PDT 24
Peak memory 218964 kb
Host smart-57423fd0-e12f-4513-bf82-d1417d5b46a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360879301 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.360879301
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.3433781149
Short name T338
Test name
Test status
Simulation time 77482868 ps
CPU time 2.98 seconds
Started Jul 13 06:41:14 PM PDT 24
Finished Jul 13 06:41:20 PM PDT 24
Peak memory 220724 kb
Host smart-3ea53889-4e68-4af5-b9b2-0825c8987c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433781149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.3433781149
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.2126356706
Short name T331
Test name
Test status
Simulation time 141677456 ps
CPU time 2.21 seconds
Started Jul 13 06:41:14 PM PDT 24
Finished Jul 13 06:41:19 PM PDT 24
Peak memory 220540 kb
Host smart-fdebe129-9f19-462a-bf79-29d309488ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126356706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.2126356706
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.1550910850
Short name T796
Test name
Test status
Simulation time 51292596 ps
CPU time 1.05 seconds
Started Jul 13 06:41:14 PM PDT 24
Finished Jul 13 06:41:17 PM PDT 24
Peak memory 217880 kb
Host smart-61fe6943-40de-4484-baa2-068d88925744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550910850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1550910850
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.2110575624
Short name T10
Test name
Test status
Simulation time 39679403 ps
CPU time 1.18 seconds
Started Jul 13 06:41:15 PM PDT 24
Finished Jul 13 06:41:19 PM PDT 24
Peak memory 219064 kb
Host smart-6ecf8f7a-59df-4cf2-81c5-e9e82f0bdb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110575624 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.2110575624
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.222021574
Short name T833
Test name
Test status
Simulation time 80732193 ps
CPU time 1.19 seconds
Started Jul 13 06:41:14 PM PDT 24
Finished Jul 13 06:41:18 PM PDT 24
Peak memory 218920 kb
Host smart-9919e0ca-fba2-49fb-b414-11615195f9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222021574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.222021574
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.581129668
Short name T204
Test name
Test status
Simulation time 41758237 ps
CPU time 1.13 seconds
Started Jul 13 06:41:12 PM PDT 24
Finished Jul 13 06:41:14 PM PDT 24
Peak memory 220104 kb
Host smart-050d9a6f-48b7-402d-9060-669734431ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581129668 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.581129668
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/109.edn_alert.3226359591
Short name T934
Test name
Test status
Simulation time 24902161 ps
CPU time 1.29 seconds
Started Jul 13 06:41:15 PM PDT 24
Finished Jul 13 06:41:18 PM PDT 24
Peak memory 220724 kb
Host smart-879291e0-a328-4113-b3f0-9acaef184c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226359591 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.3226359591
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.1290192734
Short name T93
Test name
Test status
Simulation time 39944494 ps
CPU time 1.58 seconds
Started Jul 13 06:41:15 PM PDT 24
Finished Jul 13 06:41:19 PM PDT 24
Peak memory 218884 kb
Host smart-59f8f8ef-6ff9-4a47-93a9-dae1328d01c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290192734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.1290192734
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.2437058301
Short name T190
Test name
Test status
Simulation time 70897557 ps
CPU time 1.09 seconds
Started Jul 13 06:39:21 PM PDT 24
Finished Jul 13 06:39:24 PM PDT 24
Peak memory 218644 kb
Host smart-03ad3c29-3ca8-4857-9cf1-75391e0e0d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437058301 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.2437058301
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.4227268825
Short name T781
Test name
Test status
Simulation time 30919474 ps
CPU time 0.98 seconds
Started Jul 13 06:39:20 PM PDT 24
Finished Jul 13 06:39:23 PM PDT 24
Peak memory 207020 kb
Host smart-73992674-becf-4f4b-86d4-f8bfbe414614
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227268825 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.4227268825
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.3600970350
Short name T402
Test name
Test status
Simulation time 29763120 ps
CPU time 0.83 seconds
Started Jul 13 06:39:20 PM PDT 24
Finished Jul 13 06:39:24 PM PDT 24
Peak memory 216228 kb
Host smart-ec6bd622-6f9a-462d-b0d9-8d802a75ab4a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600970350 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3600970350
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.2402203574
Short name T131
Test name
Test status
Simulation time 22228549 ps
CPU time 1.11 seconds
Started Jul 13 06:39:19 PM PDT 24
Finished Jul 13 06:39:23 PM PDT 24
Peak memory 217240 kb
Host smart-2ced1c44-a24f-462f-885c-8753c98f1e89
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402203574 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.2402203574
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.2638414114
Short name T794
Test name
Test status
Simulation time 32964796 ps
CPU time 1.04 seconds
Started Jul 13 06:39:21 PM PDT 24
Finished Jul 13 06:39:24 PM PDT 24
Peak memory 224280 kb
Host smart-acedde1d-f3cc-4799-97b6-bfc7bc040811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638414114 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.2638414114
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.3891968996
Short name T410
Test name
Test status
Simulation time 246013186 ps
CPU time 1.13 seconds
Started Jul 13 06:39:18 PM PDT 24
Finished Jul 13 06:39:21 PM PDT 24
Peak memory 217636 kb
Host smart-9c0a34c8-631e-4063-accc-9c39b4994366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891968996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.3891968996
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.3715646294
Short name T615
Test name
Test status
Simulation time 23780555 ps
CPU time 1.06 seconds
Started Jul 13 06:39:18 PM PDT 24
Finished Jul 13 06:39:21 PM PDT 24
Peak memory 216024 kb
Host smart-b99ba530-17fc-4f15-be9e-514cb523924a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715646294 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.3715646294
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.409560445
Short name T575
Test name
Test status
Simulation time 26693707 ps
CPU time 0.97 seconds
Started Jul 13 06:39:19 PM PDT 24
Finished Jul 13 06:39:22 PM PDT 24
Peak memory 215592 kb
Host smart-b326dac3-25cb-401e-b328-c340d9021b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409560445 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.409560445
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.316016281
Short name T937
Test name
Test status
Simulation time 728231133 ps
CPU time 4.52 seconds
Started Jul 13 06:39:17 PM PDT 24
Finished Jul 13 06:39:23 PM PDT 24
Peak memory 217620 kb
Host smart-ae7b59c4-463f-4a90-9569-062f643eefc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316016281 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.316016281
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.1418944901
Short name T755
Test name
Test status
Simulation time 81566415943 ps
CPU time 467.14 seconds
Started Jul 13 06:39:19 PM PDT 24
Finished Jul 13 06:47:09 PM PDT 24
Peak memory 219580 kb
Host smart-8f7ea821-4897-440e-9248-b1c9025f9daf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418944901 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.1418944901
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.3909120851
Short name T903
Test name
Test status
Simulation time 55745464 ps
CPU time 1.27 seconds
Started Jul 13 06:41:16 PM PDT 24
Finished Jul 13 06:41:19 PM PDT 24
Peak memory 215968 kb
Host smart-f1c6575c-b023-44d1-b97e-8a49e03fcfca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909120851 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.3909120851
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.646645416
Short name T468
Test name
Test status
Simulation time 210934976 ps
CPU time 1.19 seconds
Started Jul 13 06:41:13 PM PDT 24
Finished Jul 13 06:41:16 PM PDT 24
Peak memory 217424 kb
Host smart-8be6319f-8f49-4197-9c61-7d1ad1658ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646645416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.646645416
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.3584929455
Short name T126
Test name
Test status
Simulation time 145957631 ps
CPU time 1.18 seconds
Started Jul 13 06:41:13 PM PDT 24
Finished Jul 13 06:41:16 PM PDT 24
Peak memory 220984 kb
Host smart-4ce6c9df-9898-4b88-90d8-b9445449d525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584929455 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.3584929455
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/112.edn_alert.4114880737
Short name T751
Test name
Test status
Simulation time 73509887 ps
CPU time 1.1 seconds
Started Jul 13 06:41:15 PM PDT 24
Finished Jul 13 06:41:19 PM PDT 24
Peak memory 221380 kb
Host smart-bc64d1ac-57e1-41a5-8dc8-04b7b10bfbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114880737 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.4114880737
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.2884768255
Short name T672
Test name
Test status
Simulation time 292746800 ps
CPU time 4.01 seconds
Started Jul 13 06:41:12 PM PDT 24
Finished Jul 13 06:41:16 PM PDT 24
Peak memory 217752 kb
Host smart-f5b6f865-0af6-48dc-9fcf-a7b3362e060a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884768255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.2884768255
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.3146886598
Short name T370
Test name
Test status
Simulation time 228085081 ps
CPU time 1.11 seconds
Started Jul 13 06:41:16 PM PDT 24
Finished Jul 13 06:41:19 PM PDT 24
Peak memory 218840 kb
Host smart-88f14c56-b041-41e7-952e-06fd5667d935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146886598 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.3146886598
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.3949983861
Short name T804
Test name
Test status
Simulation time 71833302 ps
CPU time 2.85 seconds
Started Jul 13 06:41:11 PM PDT 24
Finished Jul 13 06:41:14 PM PDT 24
Peak memory 220376 kb
Host smart-ee11360a-30f7-402c-9467-ec34fe3c1a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949983861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.3949983861
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.3804407372
Short name T765
Test name
Test status
Simulation time 31433960 ps
CPU time 1.35 seconds
Started Jul 13 06:41:18 PM PDT 24
Finished Jul 13 06:41:21 PM PDT 24
Peak memory 220592 kb
Host smart-69c0a535-5b7e-48c9-a5db-9ca256c10b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804407372 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.3804407372
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.1491981491
Short name T948
Test name
Test status
Simulation time 44647727 ps
CPU time 1.43 seconds
Started Jul 13 06:41:17 PM PDT 24
Finished Jul 13 06:41:21 PM PDT 24
Peak memory 218796 kb
Host smart-8969a5dd-3a72-4050-a526-677e19431a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491981491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.1491981491
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.188830277
Short name T706
Test name
Test status
Simulation time 71390179 ps
CPU time 1.21 seconds
Started Jul 13 06:41:16 PM PDT 24
Finished Jul 13 06:41:19 PM PDT 24
Peak memory 219556 kb
Host smart-3e24f164-9d3c-45ef-9e92-d4540d6e8e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188830277 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.188830277
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.3346651186
Short name T428
Test name
Test status
Simulation time 33924782 ps
CPU time 1.47 seconds
Started Jul 13 06:41:13 PM PDT 24
Finished Jul 13 06:41:16 PM PDT 24
Peak memory 218700 kb
Host smart-e94b08d8-da1f-43f8-9ff6-f13d7db19e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346651186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.3346651186
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.74099811
Short name T651
Test name
Test status
Simulation time 43955430 ps
CPU time 1.09 seconds
Started Jul 13 06:41:13 PM PDT 24
Finished Jul 13 06:41:15 PM PDT 24
Peak memory 220076 kb
Host smart-c2174925-08dc-4802-bacb-3bdc20d52028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74099811 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.74099811
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.1826915564
Short name T345
Test name
Test status
Simulation time 38158178 ps
CPU time 1.69 seconds
Started Jul 13 06:41:13 PM PDT 24
Finished Jul 13 06:41:16 PM PDT 24
Peak memory 218824 kb
Host smart-0102b10d-fe5c-4948-82b4-ef0fb635416f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826915564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1826915564
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.586195716
Short name T519
Test name
Test status
Simulation time 82526113 ps
CPU time 1.22 seconds
Started Jul 13 06:41:14 PM PDT 24
Finished Jul 13 06:41:18 PM PDT 24
Peak memory 219040 kb
Host smart-b00136cf-150f-4674-8c4e-c3b793416039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586195716 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.586195716
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.2560587717
Short name T955
Test name
Test status
Simulation time 167512702 ps
CPU time 1.45 seconds
Started Jul 13 06:41:16 PM PDT 24
Finished Jul 13 06:41:19 PM PDT 24
Peak memory 219316 kb
Host smart-7bc11fd9-bd59-4fa7-a010-3f4146c05361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560587717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.2560587717
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.3160114570
Short name T652
Test name
Test status
Simulation time 50057033 ps
CPU time 1.2 seconds
Started Jul 13 06:41:14 PM PDT 24
Finished Jul 13 06:41:18 PM PDT 24
Peak memory 220112 kb
Host smart-4859af01-2951-4981-9430-08584a2da7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160114570 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.3160114570
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.1400886904
Short name T363
Test name
Test status
Simulation time 48690470 ps
CPU time 1.27 seconds
Started Jul 13 06:41:14 PM PDT 24
Finished Jul 13 06:41:17 PM PDT 24
Peak memory 218728 kb
Host smart-390fc10b-9f86-4cfb-bdf4-501f5e677fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400886904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1400886904
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.3983110290
Short name T228
Test name
Test status
Simulation time 46536116 ps
CPU time 1.17 seconds
Started Jul 13 06:41:12 PM PDT 24
Finished Jul 13 06:41:14 PM PDT 24
Peak memory 216004 kb
Host smart-f407fc61-4f52-4522-9779-bcb33ccd5c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983110290 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.3983110290
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert.903310884
Short name T142
Test name
Test status
Simulation time 54180103 ps
CPU time 1.2 seconds
Started Jul 13 06:39:19 PM PDT 24
Finished Jul 13 06:39:22 PM PDT 24
Peak memory 219008 kb
Host smart-78bea07d-96f6-4cdf-9f6d-6bc774863b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903310884 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.903310884
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.2681040463
Short name T508
Test name
Test status
Simulation time 24229377 ps
CPU time 0.86 seconds
Started Jul 13 06:39:18 PM PDT 24
Finished Jul 13 06:39:20 PM PDT 24
Peak memory 215476 kb
Host smart-de2aa89b-0ee4-4a91-bde2-62b68173ffa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681040463 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2681040463
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.1533926132
Short name T454
Test name
Test status
Simulation time 12199745 ps
CPU time 0.9 seconds
Started Jul 13 06:39:17 PM PDT 24
Finished Jul 13 06:39:20 PM PDT 24
Peak memory 215900 kb
Host smart-2ea73afd-3f08-4933-a474-376a4be0d456
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533926132 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.1533926132
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.429466728
Short name T976
Test name
Test status
Simulation time 74830640 ps
CPU time 1.25 seconds
Started Jul 13 06:39:22 PM PDT 24
Finished Jul 13 06:39:25 PM PDT 24
Peak memory 219912 kb
Host smart-c8d70b0c-1076-4f5d-8838-9bf4b5bc42b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429466728 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_di
sable_auto_req_mode.429466728
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_genbits.2070316833
Short name T992
Test name
Test status
Simulation time 31671495 ps
CPU time 1.21 seconds
Started Jul 13 06:39:20 PM PDT 24
Finished Jul 13 06:39:24 PM PDT 24
Peak memory 217696 kb
Host smart-fad96bd7-ad24-4823-a9a3-fb74ecac75c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070316833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2070316833
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_smoke.2265176782
Short name T542
Test name
Test status
Simulation time 17894379 ps
CPU time 1 seconds
Started Jul 13 06:39:19 PM PDT 24
Finished Jul 13 06:39:22 PM PDT 24
Peak memory 215536 kb
Host smart-58efcd76-b173-48fa-86b1-963e74c28b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265176782 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2265176782
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.2235688820
Short name T727
Test name
Test status
Simulation time 57183879 ps
CPU time 1.75 seconds
Started Jul 13 06:39:21 PM PDT 24
Finished Jul 13 06:39:26 PM PDT 24
Peak memory 217460 kb
Host smart-c985adbb-8c1b-428d-bdb7-b60c425de30c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235688820 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2235688820
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/120.edn_genbits.423037884
Short name T589
Test name
Test status
Simulation time 90547249 ps
CPU time 1.51 seconds
Started Jul 13 06:41:15 PM PDT 24
Finished Jul 13 06:41:19 PM PDT 24
Peak memory 220296 kb
Host smart-6b5728d9-4ac2-4a5f-88e2-03a88c65a098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423037884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.423037884
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.3903270248
Short name T701
Test name
Test status
Simulation time 24417801 ps
CPU time 1.19 seconds
Started Jul 13 06:41:13 PM PDT 24
Finished Jul 13 06:41:15 PM PDT 24
Peak memory 219004 kb
Host smart-744f33ae-31cf-4432-9de0-a2a543d58675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903270248 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.3903270248
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.4114304310
Short name T774
Test name
Test status
Simulation time 114911994 ps
CPU time 1.16 seconds
Started Jul 13 06:41:13 PM PDT 24
Finished Jul 13 06:41:15 PM PDT 24
Peak memory 217552 kb
Host smart-2d61ae04-20c5-4fd4-9d50-e167ca3c9d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114304310 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.4114304310
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.2425586433
Short name T817
Test name
Test status
Simulation time 99699323 ps
CPU time 1.2 seconds
Started Jul 13 06:41:16 PM PDT 24
Finished Jul 13 06:41:19 PM PDT 24
Peak memory 219904 kb
Host smart-13c28a5c-3b70-40b1-97e0-02ec6f888d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425586433 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.2425586433
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.3267484322
Short name T418
Test name
Test status
Simulation time 304599571 ps
CPU time 3.38 seconds
Started Jul 13 06:41:16 PM PDT 24
Finished Jul 13 06:41:21 PM PDT 24
Peak memory 220676 kb
Host smart-6b3a7e28-4baa-43a3-9c9e-d7157123534b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267484322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.3267484322
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.2659932502
Short name T514
Test name
Test status
Simulation time 96664377 ps
CPU time 1.3 seconds
Started Jul 13 06:41:15 PM PDT 24
Finished Jul 13 06:41:18 PM PDT 24
Peak memory 219088 kb
Host smart-c8a166fc-d8e8-46e7-9874-34bf92715e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659932502 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.2659932502
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/124.edn_alert.3904791940
Short name T89
Test name
Test status
Simulation time 28867920 ps
CPU time 1.31 seconds
Started Jul 13 06:41:14 PM PDT 24
Finished Jul 13 06:41:18 PM PDT 24
Peak memory 219740 kb
Host smart-b851a7a3-59a1-4c32-bf57-9145c15374c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904791940 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.3904791940
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.1634430027
Short name T112
Test name
Test status
Simulation time 42088488 ps
CPU time 1.69 seconds
Started Jul 13 06:41:18 PM PDT 24
Finished Jul 13 06:41:21 PM PDT 24
Peak memory 219008 kb
Host smart-48aa7859-e6bd-4c62-b4fb-374a9f3c47e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634430027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1634430027
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.73660999
Short name T714
Test name
Test status
Simulation time 55040152 ps
CPU time 1.29 seconds
Started Jul 13 06:41:15 PM PDT 24
Finished Jul 13 06:41:18 PM PDT 24
Peak memory 215964 kb
Host smart-073b24d2-7820-46aa-8d65-ea03e2f4f21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73660999 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.73660999
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.2993365124
Short name T518
Test name
Test status
Simulation time 176831916 ps
CPU time 2.61 seconds
Started Jul 13 06:41:13 PM PDT 24
Finished Jul 13 06:41:17 PM PDT 24
Peak memory 217944 kb
Host smart-c6c77719-ec7b-4403-8458-bfcbd66ff007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993365124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2993365124
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.999644307
Short name T46
Test name
Test status
Simulation time 156771995 ps
CPU time 1.31 seconds
Started Jul 13 06:41:14 PM PDT 24
Finished Jul 13 06:41:18 PM PDT 24
Peak memory 218896 kb
Host smart-9d7e8438-ec8b-482c-ae87-8ef21facd145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999644307 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.999644307
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.3440809782
Short name T583
Test name
Test status
Simulation time 60800485 ps
CPU time 1.37 seconds
Started Jul 13 06:41:18 PM PDT 24
Finished Jul 13 06:41:21 PM PDT 24
Peak memory 219164 kb
Host smart-26ac901f-1218-48a4-9131-e66cc7587642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440809782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.3440809782
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.428683558
Short name T498
Test name
Test status
Simulation time 49232489 ps
CPU time 1.16 seconds
Started Jul 13 06:41:18 PM PDT 24
Finished Jul 13 06:41:21 PM PDT 24
Peak memory 219860 kb
Host smart-dc50ff24-2678-4656-879b-faf754fa55f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428683558 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.428683558
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.559203185
Short name T486
Test name
Test status
Simulation time 27433852 ps
CPU time 1.34 seconds
Started Jul 13 06:41:18 PM PDT 24
Finished Jul 13 06:41:21 PM PDT 24
Peak memory 220692 kb
Host smart-87e8f7d8-dd40-4fff-868b-4ba0cd702570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559203185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.559203185
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.3493461776
Short name T715
Test name
Test status
Simulation time 40459786 ps
CPU time 1.23 seconds
Started Jul 13 06:41:18 PM PDT 24
Finished Jul 13 06:41:21 PM PDT 24
Peak memory 218892 kb
Host smart-00805375-73e3-44cc-82d8-20cc5530c2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493461776 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.3493461776
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.2711911817
Short name T843
Test name
Test status
Simulation time 69076205 ps
CPU time 1.36 seconds
Started Jul 13 06:41:18 PM PDT 24
Finished Jul 13 06:41:21 PM PDT 24
Peak memory 218872 kb
Host smart-b876d83a-9a2c-44c0-a8a6-baea4af0346f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711911817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.2711911817
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.3120515016
Short name T196
Test name
Test status
Simulation time 27969858 ps
CPU time 1.28 seconds
Started Jul 13 06:41:16 PM PDT 24
Finished Jul 13 06:41:20 PM PDT 24
Peak memory 215980 kb
Host smart-7dff6c68-7ef2-4e92-b703-2f947bb7a8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120515016 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.3120515016
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.1587123422
Short name T839
Test name
Test status
Simulation time 44051335 ps
CPU time 1.5 seconds
Started Jul 13 06:41:15 PM PDT 24
Finished Jul 13 06:41:19 PM PDT 24
Peak memory 219008 kb
Host smart-544c7383-81d3-464c-ad58-3535be960904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587123422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.1587123422
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.3312139275
Short name T471
Test name
Test status
Simulation time 42282898 ps
CPU time 1.17 seconds
Started Jul 13 06:39:19 PM PDT 24
Finished Jul 13 06:39:22 PM PDT 24
Peak memory 219692 kb
Host smart-bbc27fe9-7293-4c36-9846-a89183a1110d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312139275 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.3312139275
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.202102621
Short name T502
Test name
Test status
Simulation time 15354884 ps
CPU time 0.96 seconds
Started Jul 13 06:39:17 PM PDT 24
Finished Jul 13 06:39:19 PM PDT 24
Peak memory 215204 kb
Host smart-8ffc57fc-46e7-4ae8-b654-623211db4cd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202102621 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.202102621
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.3156889038
Short name T181
Test name
Test status
Simulation time 13094396 ps
CPU time 0.91 seconds
Started Jul 13 06:39:20 PM PDT 24
Finished Jul 13 06:39:24 PM PDT 24
Peak memory 216740 kb
Host smart-86a1d237-8617-4a8c-9556-f40d48b97120
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156889038 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.3156889038
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.2781269072
Short name T935
Test name
Test status
Simulation time 353070439 ps
CPU time 1.11 seconds
Started Jul 13 06:39:21 PM PDT 24
Finished Jul 13 06:39:25 PM PDT 24
Peak memory 217540 kb
Host smart-7a01a537-8120-437e-ac0e-13510aafc1bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781269072 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.2781269072
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.2123058675
Short name T104
Test name
Test status
Simulation time 26302601 ps
CPU time 0.88 seconds
Started Jul 13 06:39:20 PM PDT 24
Finished Jul 13 06:39:24 PM PDT 24
Peak memory 218520 kb
Host smart-7b158461-29d5-4234-a5a9-682de34e577a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123058675 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2123058675
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.4056217096
Short name T813
Test name
Test status
Simulation time 48840074 ps
CPU time 1.31 seconds
Started Jul 13 06:39:22 PM PDT 24
Finished Jul 13 06:39:25 PM PDT 24
Peak memory 215592 kb
Host smart-e6cf1b3e-1c43-4196-b845-a19ea7beb8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056217096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.4056217096
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.1144898979
Short name T60
Test name
Test status
Simulation time 50134095 ps
CPU time 0.99 seconds
Started Jul 13 06:39:18 PM PDT 24
Finished Jul 13 06:39:20 PM PDT 24
Peak memory 224132 kb
Host smart-9f63e2a1-2e74-44a7-b02d-85e4922acb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144898979 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.1144898979
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.2809579137
Short name T26
Test name
Test status
Simulation time 15704941 ps
CPU time 0.96 seconds
Started Jul 13 06:39:17 PM PDT 24
Finished Jul 13 06:39:20 PM PDT 24
Peak memory 215568 kb
Host smart-41207547-814b-424c-bb76-ed343c3f51b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809579137 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.2809579137
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.704265137
Short name T239
Test name
Test status
Simulation time 18756080419 ps
CPU time 409.57 seconds
Started Jul 13 06:39:19 PM PDT 24
Finished Jul 13 06:46:11 PM PDT 24
Peak memory 218592 kb
Host smart-915f01db-0164-4a31-915a-92956da5eb12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704265137 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.704265137
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.3173625519
Short name T569
Test name
Test status
Simulation time 62991360 ps
CPU time 1.38 seconds
Started Jul 13 06:41:16 PM PDT 24
Finished Jul 13 06:41:20 PM PDT 24
Peak memory 219060 kb
Host smart-1f63cd27-0288-4312-b505-0f8638caf294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173625519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.3173625519
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.594876226
Short name T778
Test name
Test status
Simulation time 67981379 ps
CPU time 1.11 seconds
Started Jul 13 06:41:27 PM PDT 24
Finished Jul 13 06:41:31 PM PDT 24
Peak memory 219932 kb
Host smart-307e8468-dfe4-4fdc-af4a-9f3a6abd8977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594876226 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.594876226
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.3033783327
Short name T419
Test name
Test status
Simulation time 49110282 ps
CPU time 1.22 seconds
Started Jul 13 06:41:26 PM PDT 24
Finished Jul 13 06:41:28 PM PDT 24
Peak memory 219080 kb
Host smart-2643b8b2-9abb-4646-be8c-4bbe4a6415a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033783327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.3033783327
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.4284345430
Short name T291
Test name
Test status
Simulation time 40400673 ps
CPU time 1.11 seconds
Started Jul 13 06:41:24 PM PDT 24
Finished Jul 13 06:41:27 PM PDT 24
Peak memory 218912 kb
Host smart-54b3ed89-a379-456b-8a71-4ff53f025cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284345430 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.4284345430
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.3551146698
Short name T481
Test name
Test status
Simulation time 133508261 ps
CPU time 1.84 seconds
Started Jul 13 06:41:25 PM PDT 24
Finished Jul 13 06:41:28 PM PDT 24
Peak memory 220312 kb
Host smart-1304ccac-3413-40a7-be95-2a49a378d27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551146698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.3551146698
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.3614268601
Short name T716
Test name
Test status
Simulation time 87571217 ps
CPU time 1.15 seconds
Started Jul 13 06:41:23 PM PDT 24
Finished Jul 13 06:41:25 PM PDT 24
Peak memory 218852 kb
Host smart-251e0af6-7ad5-42ec-a2ec-d7bffdef8b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614268601 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.3614268601
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.490334694
Short name T943
Test name
Test status
Simulation time 29412281 ps
CPU time 1.38 seconds
Started Jul 13 06:41:25 PM PDT 24
Finished Jul 13 06:41:27 PM PDT 24
Peak memory 220216 kb
Host smart-62bcb116-7771-4027-b06a-8b87a1ea148c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490334694 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.490334694
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.2344867037
Short name T558
Test name
Test status
Simulation time 30306597 ps
CPU time 1.28 seconds
Started Jul 13 06:41:25 PM PDT 24
Finished Jul 13 06:41:27 PM PDT 24
Peak memory 220896 kb
Host smart-72c40113-f977-46ec-8a8c-ba25dec1be6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344867037 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.2344867037
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.3530848763
Short name T491
Test name
Test status
Simulation time 33544856 ps
CPU time 1.39 seconds
Started Jul 13 06:41:26 PM PDT 24
Finished Jul 13 06:41:30 PM PDT 24
Peak memory 220188 kb
Host smart-2210ba73-96b8-4c18-8da6-0e945fc6221d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530848763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3530848763
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.3300288469
Short name T313
Test name
Test status
Simulation time 27816977 ps
CPU time 1.3 seconds
Started Jul 13 06:41:26 PM PDT 24
Finished Jul 13 06:41:29 PM PDT 24
Peak memory 218960 kb
Host smart-9dddac51-1edc-4c46-883e-bcce9a610ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300288469 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.3300288469
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.3683521916
Short name T91
Test name
Test status
Simulation time 94741904 ps
CPU time 1.37 seconds
Started Jul 13 06:41:26 PM PDT 24
Finished Jul 13 06:41:31 PM PDT 24
Peak memory 219308 kb
Host smart-762b5279-97a8-4641-97a6-4f8ec5c73792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683521916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.3683521916
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.1707178577
Short name T314
Test name
Test status
Simulation time 27464839 ps
CPU time 1.32 seconds
Started Jul 13 06:41:26 PM PDT 24
Finished Jul 13 06:41:30 PM PDT 24
Peak memory 220824 kb
Host smart-22af4c73-98f4-4962-94bc-875c0d428eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707178577 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.1707178577
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.611571266
Short name T537
Test name
Test status
Simulation time 60025507 ps
CPU time 1.25 seconds
Started Jul 13 06:41:24 PM PDT 24
Finished Jul 13 06:41:26 PM PDT 24
Peak memory 219368 kb
Host smart-8bac6cf9-6e60-4c0c-be3d-0ab2c4b0c0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611571266 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.611571266
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.3220030956
Short name T594
Test name
Test status
Simulation time 58879774 ps
CPU time 1.14 seconds
Started Jul 13 06:41:26 PM PDT 24
Finished Jul 13 06:41:29 PM PDT 24
Peak memory 218932 kb
Host smart-a239bae2-c411-4ad6-8f78-2559fef4acfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220030956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.3220030956
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.1067288160
Short name T686
Test name
Test status
Simulation time 74013035 ps
CPU time 1.07 seconds
Started Jul 13 06:41:27 PM PDT 24
Finished Jul 13 06:41:31 PM PDT 24
Peak memory 218756 kb
Host smart-387f65e1-bd6c-4ed9-a2df-592a69209cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067288160 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.1067288160
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.4091935987
Short name T960
Test name
Test status
Simulation time 68430502 ps
CPU time 1.46 seconds
Started Jul 13 06:41:27 PM PDT 24
Finished Jul 13 06:41:31 PM PDT 24
Peak memory 220164 kb
Host smart-b56f013f-ad6c-4bb6-be74-c00259ea3efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091935987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.4091935987
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.2427310740
Short name T995
Test name
Test status
Simulation time 27421880 ps
CPU time 1.25 seconds
Started Jul 13 06:41:27 PM PDT 24
Finished Jul 13 06:41:31 PM PDT 24
Peak memory 219960 kb
Host smart-b269c8ed-d5ef-4733-894d-ed9c4479290b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427310740 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.2427310740
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.3196327030
Short name T700
Test name
Test status
Simulation time 87569301 ps
CPU time 1.43 seconds
Started Jul 13 06:41:26 PM PDT 24
Finished Jul 13 06:41:29 PM PDT 24
Peak memory 217728 kb
Host smart-81330569-8bf6-462b-849d-6aaeb1c1c408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196327030 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3196327030
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.1613128918
Short name T837
Test name
Test status
Simulation time 69837421 ps
CPU time 1.08 seconds
Started Jul 13 06:39:22 PM PDT 24
Finished Jul 13 06:39:25 PM PDT 24
Peak memory 219136 kb
Host smart-de11f0ac-88be-4620-b7c6-e5c4022ed8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613128918 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.1613128918
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.254098704
Short name T670
Test name
Test status
Simulation time 89130346 ps
CPU time 0.96 seconds
Started Jul 13 06:39:21 PM PDT 24
Finished Jul 13 06:39:24 PM PDT 24
Peak memory 215208 kb
Host smart-42d0b55a-541b-4220-a13c-68e5f9a06278
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254098704 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.254098704
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.959126871
Short name T929
Test name
Test status
Simulation time 13542739 ps
CPU time 0.94 seconds
Started Jul 13 06:39:19 PM PDT 24
Finished Jul 13 06:39:23 PM PDT 24
Peak memory 215884 kb
Host smart-a303ca8b-1326-410f-b055-7d1139e370f3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959126871 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.959126871
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.289322340
Short name T597
Test name
Test status
Simulation time 55287078 ps
CPU time 1.14 seconds
Started Jul 13 06:39:19 PM PDT 24
Finished Jul 13 06:39:23 PM PDT 24
Peak memory 218868 kb
Host smart-3d256b13-cae3-4de2-bd44-8a7fb02999f4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289322340 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_di
sable_auto_req_mode.289322340
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_genbits.3273131736
Short name T758
Test name
Test status
Simulation time 54727290 ps
CPU time 1.21 seconds
Started Jul 13 06:39:18 PM PDT 24
Finished Jul 13 06:39:21 PM PDT 24
Peak memory 217788 kb
Host smart-a58b18bd-d1f9-464b-b1cb-008bffa42427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273131736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3273131736
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_smoke.1350534750
Short name T742
Test name
Test status
Simulation time 29269602 ps
CPU time 1.03 seconds
Started Jul 13 06:39:20 PM PDT 24
Finished Jul 13 06:39:24 PM PDT 24
Peak memory 215636 kb
Host smart-3d57db9d-9965-482c-82d3-77d0d5e74b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350534750 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.1350534750
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.3797856907
Short name T782
Test name
Test status
Simulation time 177903188 ps
CPU time 1.64 seconds
Started Jul 13 06:39:20 PM PDT 24
Finished Jul 13 06:39:24 PM PDT 24
Peak memory 215608 kb
Host smart-e7e2933b-3696-4302-9f64-7f824384a657
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797856907 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3797856907
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.3565255949
Short name T113
Test name
Test status
Simulation time 72217197624 ps
CPU time 1661.57 seconds
Started Jul 13 06:39:18 PM PDT 24
Finished Jul 13 07:07:01 PM PDT 24
Peak memory 225136 kb
Host smart-1a0faecd-8fb2-47ee-b6e2-12394e2e1b54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565255949 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.3565255949
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.546569525
Short name T872
Test name
Test status
Simulation time 92597398 ps
CPU time 1.22 seconds
Started Jul 13 06:41:27 PM PDT 24
Finished Jul 13 06:41:31 PM PDT 24
Peak memory 218984 kb
Host smart-eadde95a-a3d0-422a-aa41-29af9d7cf706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546569525 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.546569525
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.2090389251
Short name T362
Test name
Test status
Simulation time 215139920 ps
CPU time 1.13 seconds
Started Jul 13 06:41:25 PM PDT 24
Finished Jul 13 06:41:28 PM PDT 24
Peak memory 215616 kb
Host smart-42a453ec-c32d-45fd-92c9-54de0425d8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090389251 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2090389251
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.1654833193
Short name T140
Test name
Test status
Simulation time 40971468 ps
CPU time 1.18 seconds
Started Jul 13 06:41:26 PM PDT 24
Finished Jul 13 06:41:30 PM PDT 24
Peak memory 218728 kb
Host smart-2c04aa3e-6a78-491d-bea4-9362e08b99bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654833193 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.1654833193
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.693931170
Short name T878
Test name
Test status
Simulation time 94278629 ps
CPU time 1.53 seconds
Started Jul 13 06:41:24 PM PDT 24
Finished Jul 13 06:41:27 PM PDT 24
Peak memory 219304 kb
Host smart-75b734fa-69d2-4dac-bd4e-05158ce66109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693931170 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.693931170
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.1446053509
Short name T203
Test name
Test status
Simulation time 55629213 ps
CPU time 1.24 seconds
Started Jul 13 06:41:26 PM PDT 24
Finished Jul 13 06:41:29 PM PDT 24
Peak memory 220128 kb
Host smart-b63f1e9c-5a04-43e2-a9bf-92b25c787364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446053509 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.1446053509
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.1079289021
Short name T425
Test name
Test status
Simulation time 62987945 ps
CPU time 1.08 seconds
Started Jul 13 06:41:28 PM PDT 24
Finished Jul 13 06:41:32 PM PDT 24
Peak memory 217708 kb
Host smart-2076466c-d74d-4afd-aa37-5b064febca07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079289021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.1079289021
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.2111214942
Short name T754
Test name
Test status
Simulation time 27622842 ps
CPU time 1.29 seconds
Started Jul 13 06:41:24 PM PDT 24
Finished Jul 13 06:41:27 PM PDT 24
Peak memory 219496 kb
Host smart-776ca940-2e8c-4046-bd12-cbcb4b2e6339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111214942 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.2111214942
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.4097095105
Short name T986
Test name
Test status
Simulation time 63468656 ps
CPU time 1.36 seconds
Started Jul 13 06:41:25 PM PDT 24
Finished Jul 13 06:41:27 PM PDT 24
Peak memory 218908 kb
Host smart-2a0de77f-e04f-441f-91e3-0070ebd812e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097095105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.4097095105
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.1265602327
Short name T566
Test name
Test status
Simulation time 62824936 ps
CPU time 1.11 seconds
Started Jul 13 06:41:26 PM PDT 24
Finished Jul 13 06:41:30 PM PDT 24
Peak memory 219892 kb
Host smart-677e1af7-1de2-44be-866c-846c3ed37b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265602327 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.1265602327
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.2717364306
Short name T541
Test name
Test status
Simulation time 67354184 ps
CPU time 1.1 seconds
Started Jul 13 06:41:26 PM PDT 24
Finished Jul 13 06:41:28 PM PDT 24
Peak memory 217448 kb
Host smart-bb0db24a-208d-4120-9142-5a177d5de7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717364306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.2717364306
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.2269884456
Short name T133
Test name
Test status
Simulation time 140599181 ps
CPU time 1.19 seconds
Started Jul 13 06:41:25 PM PDT 24
Finished Jul 13 06:41:27 PM PDT 24
Peak memory 218908 kb
Host smart-86e82f87-2bf1-4e8a-9e27-2b090d24989c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269884456 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.2269884456
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.4014274752
Short name T352
Test name
Test status
Simulation time 79581127 ps
CPU time 1.22 seconds
Started Jul 13 06:41:23 PM PDT 24
Finished Jul 13 06:41:25 PM PDT 24
Peak memory 219840 kb
Host smart-3b62fec2-b554-4f32-9863-26bf3d234633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014274752 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.4014274752
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.81975270
Short name T115
Test name
Test status
Simulation time 29892236 ps
CPU time 1.3 seconds
Started Jul 13 06:41:27 PM PDT 24
Finished Jul 13 06:41:31 PM PDT 24
Peak memory 216012 kb
Host smart-6387011a-457e-477e-af4b-855c6b3ede61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81975270 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.81975270
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.1114773293
Short name T842
Test name
Test status
Simulation time 260552736 ps
CPU time 1.44 seconds
Started Jul 13 06:41:26 PM PDT 24
Finished Jul 13 06:41:30 PM PDT 24
Peak memory 220236 kb
Host smart-9825e1ea-3800-4154-9ce0-9f57d39fe03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114773293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1114773293
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.4111908867
Short name T910
Test name
Test status
Simulation time 24244499 ps
CPU time 1.2 seconds
Started Jul 13 06:41:28 PM PDT 24
Finished Jul 13 06:41:32 PM PDT 24
Peak memory 219064 kb
Host smart-9f810ab6-14b7-4b93-a1b9-6f99af553c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111908867 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.4111908867
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.1085988954
Short name T539
Test name
Test status
Simulation time 82525908 ps
CPU time 1.34 seconds
Started Jul 13 06:41:27 PM PDT 24
Finished Jul 13 06:41:31 PM PDT 24
Peak memory 218932 kb
Host smart-064df406-477e-4ce1-845f-c71a618cb48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085988954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.1085988954
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.1939916527
Short name T99
Test name
Test status
Simulation time 22710984 ps
CPU time 1.24 seconds
Started Jul 13 06:41:26 PM PDT 24
Finished Jul 13 06:41:30 PM PDT 24
Peak memory 221076 kb
Host smart-b0e6fd9b-3ab5-4f24-8299-4ea0b197edde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939916527 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.1939916527
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.150108114
Short name T631
Test name
Test status
Simulation time 310427680 ps
CPU time 1.04 seconds
Started Jul 13 06:41:24 PM PDT 24
Finished Jul 13 06:41:27 PM PDT 24
Peak memory 217568 kb
Host smart-967d4774-c3fa-4448-ad80-565e30d499a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150108114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.150108114
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.4112204632
Short name T189
Test name
Test status
Simulation time 32934366 ps
CPU time 1.17 seconds
Started Jul 13 06:41:26 PM PDT 24
Finished Jul 13 06:41:29 PM PDT 24
Peak memory 219960 kb
Host smart-85084557-7b87-435f-b6cd-be382f2ec25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112204632 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.4112204632
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.2540816058
Short name T561
Test name
Test status
Simulation time 33813176 ps
CPU time 1.39 seconds
Started Jul 13 06:41:28 PM PDT 24
Finished Jul 13 06:41:32 PM PDT 24
Peak memory 220308 kb
Host smart-c17060d6-7d81-480c-b655-ec8ee3c6537d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540816058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2540816058
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.2311857552
Short name T735
Test name
Test status
Simulation time 43855688 ps
CPU time 1.22 seconds
Started Jul 13 06:39:18 PM PDT 24
Finished Jul 13 06:39:21 PM PDT 24
Peak memory 219692 kb
Host smart-33e24168-b495-4ffc-b41d-3d2a08fe8c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311857552 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.2311857552
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.1604515252
Short name T917
Test name
Test status
Simulation time 18187268 ps
CPU time 1.06 seconds
Started Jul 13 06:39:31 PM PDT 24
Finished Jul 13 06:39:33 PM PDT 24
Peak memory 207032 kb
Host smart-4ccfdb0c-0919-4fcc-89a3-12643b5933b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604515252 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.1604515252
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.3158751472
Short name T584
Test name
Test status
Simulation time 19096434 ps
CPU time 0.89 seconds
Started Jul 13 06:39:29 PM PDT 24
Finished Jul 13 06:39:31 PM PDT 24
Peak memory 216424 kb
Host smart-5d98ca3e-26e2-4af5-bca9-7db97c4bcf1a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158751472 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3158751472
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.1174161720
Short name T130
Test name
Test status
Simulation time 146352567 ps
CPU time 1.11 seconds
Started Jul 13 06:39:35 PM PDT 24
Finished Jul 13 06:39:37 PM PDT 24
Peak memory 217112 kb
Host smart-2d1f1d87-faf9-4d0c-9075-144dd3fc04b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174161720 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.1174161720
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.1415436612
Short name T555
Test name
Test status
Simulation time 21748382 ps
CPU time 0.98 seconds
Started Jul 13 06:39:32 PM PDT 24
Finished Jul 13 06:39:34 PM PDT 24
Peak memory 218788 kb
Host smart-e8fd05f2-8836-4142-a8fd-57369e637e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415436612 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.1415436612
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.3873117216
Short name T958
Test name
Test status
Simulation time 44554350 ps
CPU time 1.16 seconds
Started Jul 13 06:39:17 PM PDT 24
Finished Jul 13 06:39:20 PM PDT 24
Peak memory 218980 kb
Host smart-5054b688-3c17-4c38-95d5-23cc854e7993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873117216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.3873117216
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.1425615968
Short name T417
Test name
Test status
Simulation time 32892092 ps
CPU time 0.99 seconds
Started Jul 13 06:39:22 PM PDT 24
Finished Jul 13 06:39:25 PM PDT 24
Peak memory 224300 kb
Host smart-c3496184-9d15-439e-a3a5-1de846ed1713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425615968 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.1425615968
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.2102850375
Short name T358
Test name
Test status
Simulation time 49878598 ps
CPU time 0.91 seconds
Started Jul 13 06:39:16 PM PDT 24
Finished Jul 13 06:39:18 PM PDT 24
Peak memory 215612 kb
Host smart-825c0108-0071-42e3-9bc2-055814a4dfaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102850375 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2102850375
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.2486314272
Short name T375
Test name
Test status
Simulation time 413068569 ps
CPU time 4.6 seconds
Started Jul 13 06:39:21 PM PDT 24
Finished Jul 13 06:39:28 PM PDT 24
Peak memory 220752 kb
Host smart-912d657a-9dde-4065-9a67-970d53c3d532
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486314272 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.2486314272
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/150.edn_alert.233574195
Short name T487
Test name
Test status
Simulation time 169855657 ps
CPU time 1.15 seconds
Started Jul 13 06:41:25 PM PDT 24
Finished Jul 13 06:41:27 PM PDT 24
Peak memory 218912 kb
Host smart-c11c8a2a-df89-43aa-8692-42853b80a255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233574195 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.233574195
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.690317765
Short name T846
Test name
Test status
Simulation time 98477979 ps
CPU time 1.3 seconds
Started Jul 13 06:41:24 PM PDT 24
Finished Jul 13 06:41:27 PM PDT 24
Peak memory 218884 kb
Host smart-3b354d81-0ee1-46ef-80a0-0f2e8a99b4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690317765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.690317765
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.1532105559
Short name T475
Test name
Test status
Simulation time 34790978 ps
CPU time 1.36 seconds
Started Jul 13 06:41:26 PM PDT 24
Finished Jul 13 06:41:30 PM PDT 24
Peak memory 215512 kb
Host smart-3137e4b8-270f-47d8-bba6-f77e464fb7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532105559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.1532105559
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.448386873
Short name T699
Test name
Test status
Simulation time 88895965 ps
CPU time 1.21 seconds
Started Jul 13 06:41:25 PM PDT 24
Finished Jul 13 06:41:28 PM PDT 24
Peak memory 220848 kb
Host smart-27ea5e9e-bbff-4a28-b5c1-dd1f5d58dab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448386873 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.448386873
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.3092292743
Short name T864
Test name
Test status
Simulation time 99046332 ps
CPU time 1.09 seconds
Started Jul 13 06:41:27 PM PDT 24
Finished Jul 13 06:41:30 PM PDT 24
Peak memory 217636 kb
Host smart-0c8d50ce-6e9a-4170-8e7a-6fd5358f24be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092292743 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.3092292743
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.2716334873
Short name T823
Test name
Test status
Simulation time 25881033 ps
CPU time 1.22 seconds
Started Jul 13 06:41:28 PM PDT 24
Finished Jul 13 06:41:31 PM PDT 24
Peak memory 218784 kb
Host smart-dd4789f6-dda7-40ea-8650-bec6bd68923f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716334873 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.2716334873
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.3514460357
Short name T545
Test name
Test status
Simulation time 153428114 ps
CPU time 1.09 seconds
Started Jul 13 06:41:27 PM PDT 24
Finished Jul 13 06:41:31 PM PDT 24
Peak memory 217736 kb
Host smart-b2a09ea3-f25a-426e-9b06-4ca9f494ca1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514460357 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.3514460357
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.3307061236
Short name T484
Test name
Test status
Simulation time 310904218 ps
CPU time 1.15 seconds
Started Jul 13 06:41:26 PM PDT 24
Finished Jul 13 06:41:29 PM PDT 24
Peak memory 220068 kb
Host smart-b8542d89-3693-4ad7-8234-6b75ba65172d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307061236 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.3307061236
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.3409072528
Short name T624
Test name
Test status
Simulation time 132386846 ps
CPU time 1.21 seconds
Started Jul 13 06:41:26 PM PDT 24
Finished Jul 13 06:41:29 PM PDT 24
Peak memory 217708 kb
Host smart-a331ea5e-b59a-4ca7-b953-77c6b9b66f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409072528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.3409072528
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.2645020293
Short name T257
Test name
Test status
Simulation time 74671885 ps
CPU time 1.19 seconds
Started Jul 13 06:41:24 PM PDT 24
Finished Jul 13 06:41:25 PM PDT 24
Peak memory 220636 kb
Host smart-c00d7cac-dfe8-495f-863e-afa2a93d1eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645020293 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.2645020293
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.3676564758
Short name T254
Test name
Test status
Simulation time 28428121 ps
CPU time 1.3 seconds
Started Jul 13 06:41:28 PM PDT 24
Finished Jul 13 06:41:32 PM PDT 24
Peak memory 218600 kb
Host smart-12c0da39-776d-4969-a521-2fd991899d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676564758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3676564758
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.2634958963
Short name T643
Test name
Test status
Simulation time 21786737 ps
CPU time 1.14 seconds
Started Jul 13 06:41:29 PM PDT 24
Finished Jul 13 06:41:32 PM PDT 24
Peak memory 218732 kb
Host smart-16c70a0f-08fb-419e-b9a3-d9d58366d824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634958963 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.2634958963
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.3978303713
Short name T894
Test name
Test status
Simulation time 44778694 ps
CPU time 1.78 seconds
Started Jul 13 06:41:27 PM PDT 24
Finished Jul 13 06:41:32 PM PDT 24
Peak memory 218708 kb
Host smart-ec34bf5a-28a8-40e0-b110-4898775f2138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978303713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3978303713
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.3081383105
Short name T927
Test name
Test status
Simulation time 40227193 ps
CPU time 1.09 seconds
Started Jul 13 06:41:26 PM PDT 24
Finished Jul 13 06:41:29 PM PDT 24
Peak memory 219088 kb
Host smart-e63c33a3-4fd6-4cad-9fec-6605f2d36b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081383105 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.3081383105
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.258916679
Short name T870
Test name
Test status
Simulation time 117940470 ps
CPU time 1.41 seconds
Started Jul 13 06:41:26 PM PDT 24
Finished Jul 13 06:41:30 PM PDT 24
Peak memory 218840 kb
Host smart-3813ecd4-06d2-4a89-b5b1-e7d0fd31393a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258916679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.258916679
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.2051526499
Short name T810
Test name
Test status
Simulation time 33023736 ps
CPU time 1.42 seconds
Started Jul 13 06:41:28 PM PDT 24
Finished Jul 13 06:41:32 PM PDT 24
Peak memory 220408 kb
Host smart-e78847ac-108b-49c7-863a-44212c8f2081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051526499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2051526499
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.2055308013
Short name T973
Test name
Test status
Simulation time 78132339 ps
CPU time 1.21 seconds
Started Jul 13 06:41:27 PM PDT 24
Finished Jul 13 06:41:31 PM PDT 24
Peak memory 220104 kb
Host smart-d5e452b0-31a7-4ddb-8036-acad007b6929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055308013 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.2055308013
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.1900130450
Short name T359
Test name
Test status
Simulation time 74488509 ps
CPU time 1.23 seconds
Started Jul 13 06:41:28 PM PDT 24
Finished Jul 13 06:41:32 PM PDT 24
Peak memory 218892 kb
Host smart-4cc336ac-13bb-4465-b008-cb2b442166ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900130450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1900130450
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.821702496
Short name T944
Test name
Test status
Simulation time 72921058 ps
CPU time 1.08 seconds
Started Jul 13 06:39:34 PM PDT 24
Finished Jul 13 06:39:36 PM PDT 24
Peak memory 218696 kb
Host smart-c4a34d48-1bf3-430a-8303-fd4699025a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821702496 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.821702496
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.992062840
Short name T827
Test name
Test status
Simulation time 17810442 ps
CPU time 0.83 seconds
Started Jul 13 06:39:31 PM PDT 24
Finished Jul 13 06:39:33 PM PDT 24
Peak memory 207044 kb
Host smart-e297392e-22b4-4f31-93ba-38ad7a23029e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992062840 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.992062840
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.2028102013
Short name T390
Test name
Test status
Simulation time 11173763 ps
CPU time 0.98 seconds
Started Jul 13 06:39:32 PM PDT 24
Finished Jul 13 06:39:34 PM PDT 24
Peak memory 216164 kb
Host smart-242e5104-e6fb-4ef0-b121-e407cc39495d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028102013 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2028102013
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2699346380
Short name T357
Test name
Test status
Simulation time 27170997 ps
CPU time 1.19 seconds
Started Jul 13 06:39:40 PM PDT 24
Finished Jul 13 06:39:43 PM PDT 24
Peak memory 217080 kb
Host smart-5399ad83-3ef6-4927-a052-622174e0bc1f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699346380 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2699346380
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.4048578966
Short name T764
Test name
Test status
Simulation time 24952860 ps
CPU time 1.21 seconds
Started Jul 13 06:39:31 PM PDT 24
Finished Jul 13 06:39:33 PM PDT 24
Peak memory 220004 kb
Host smart-c71f955a-50de-4be2-830b-3ea588275f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048578966 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.4048578966
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.1876666829
Short name T446
Test name
Test status
Simulation time 48754289 ps
CPU time 2.04 seconds
Started Jul 13 06:39:32 PM PDT 24
Finished Jul 13 06:39:35 PM PDT 24
Peak memory 218808 kb
Host smart-66c37501-b301-4b58-8cd3-c7414f037a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876666829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.1876666829
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.221616431
Short name T641
Test name
Test status
Simulation time 20979959 ps
CPU time 1.03 seconds
Started Jul 13 06:39:31 PM PDT 24
Finished Jul 13 06:39:33 PM PDT 24
Peak memory 216228 kb
Host smart-8c709a3d-3492-4883-ad9b-db070ab5d9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221616431 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.221616431
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.1246038195
Short name T66
Test name
Test status
Simulation time 35701119 ps
CPU time 0.9 seconds
Started Jul 13 06:39:31 PM PDT 24
Finished Jul 13 06:39:33 PM PDT 24
Peak memory 215856 kb
Host smart-8fd1a790-31d5-4c47-8fdb-9ee374ed3e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246038195 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1246038195
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.4279950933
Short name T845
Test name
Test status
Simulation time 470747078 ps
CPU time 2.08 seconds
Started Jul 13 06:39:28 PM PDT 24
Finished Jul 13 06:39:31 PM PDT 24
Peak memory 220576 kb
Host smart-366e375c-9111-4036-aeec-36e13a878aed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279950933 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.4279950933
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.3592313102
Short name T464
Test name
Test status
Simulation time 52849740076 ps
CPU time 1329.19 seconds
Started Jul 13 06:39:33 PM PDT 24
Finished Jul 13 07:01:43 PM PDT 24
Peak memory 223492 kb
Host smart-0413356f-928a-4a8b-8fa9-559c94f9fc7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592313102 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.3592313102
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.1338498102
Short name T311
Test name
Test status
Simulation time 65160858 ps
CPU time 1.14 seconds
Started Jul 13 06:41:24 PM PDT 24
Finished Jul 13 06:41:27 PM PDT 24
Peak memory 219452 kb
Host smart-1eb56b7e-b62c-4016-9089-65ae8feaabf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338498102 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.1338498102
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.3936638662
Short name T609
Test name
Test status
Simulation time 176987535 ps
CPU time 3.17 seconds
Started Jul 13 06:41:29 PM PDT 24
Finished Jul 13 06:41:34 PM PDT 24
Peak memory 220280 kb
Host smart-eca76103-3627-4a4b-a282-fb270bb3d33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936638662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.3936638662
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.2706256442
Short name T123
Test name
Test status
Simulation time 40320055 ps
CPU time 1.23 seconds
Started Jul 13 06:41:35 PM PDT 24
Finished Jul 13 06:41:37 PM PDT 24
Peak memory 219064 kb
Host smart-da178adb-81dd-4bec-a902-5c6d6b1709f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706256442 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.2706256442
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.3061834224
Short name T374
Test name
Test status
Simulation time 44043858 ps
CPU time 1.89 seconds
Started Jul 13 06:41:36 PM PDT 24
Finished Jul 13 06:41:38 PM PDT 24
Peak memory 219284 kb
Host smart-42d68d29-f533-40a0-bd0b-ca8fa074ced3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061834224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.3061834224
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.2433515385
Short name T712
Test name
Test status
Simulation time 91814180 ps
CPU time 1.23 seconds
Started Jul 13 06:41:38 PM PDT 24
Finished Jul 13 06:41:40 PM PDT 24
Peak memory 216004 kb
Host smart-be29446b-41a1-4c55-9d77-6302c712b21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433515385 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.2433515385
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.1605903384
Short name T552
Test name
Test status
Simulation time 83971888 ps
CPU time 1.18 seconds
Started Jul 13 06:41:36 PM PDT 24
Finished Jul 13 06:41:38 PM PDT 24
Peak memory 219700 kb
Host smart-a990860b-37b9-430f-b7ba-85cde814b886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605903384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.1605903384
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.3052509566
Short name T258
Test name
Test status
Simulation time 29877202 ps
CPU time 1.37 seconds
Started Jul 13 06:41:33 PM PDT 24
Finished Jul 13 06:41:35 PM PDT 24
Peak memory 219652 kb
Host smart-ae61a8a9-d1a1-452d-9a3c-838e609d5a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052509566 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.3052509566
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.908612054
Short name T875
Test name
Test status
Simulation time 149154885 ps
CPU time 1.21 seconds
Started Jul 13 06:41:40 PM PDT 24
Finished Jul 13 06:41:42 PM PDT 24
Peak memory 218008 kb
Host smart-2b9ced19-78a3-43ab-9b8b-bb3a8ce76fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908612054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.908612054
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.3071788886
Short name T493
Test name
Test status
Simulation time 30403772 ps
CPU time 1.28 seconds
Started Jul 13 06:41:34 PM PDT 24
Finished Jul 13 06:41:36 PM PDT 24
Peak memory 219000 kb
Host smart-da68609d-75a8-4bda-94ae-0d6678c14359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071788886 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.3071788886
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.4166519429
Short name T984
Test name
Test status
Simulation time 61789567 ps
CPU time 1.38 seconds
Started Jul 13 06:41:33 PM PDT 24
Finished Jul 13 06:41:35 PM PDT 24
Peak memory 217552 kb
Host smart-73039e42-f963-4a2b-809b-e284d5e2f955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166519429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.4166519429
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.3331708892
Short name T913
Test name
Test status
Simulation time 62634803 ps
CPU time 1.6 seconds
Started Jul 13 06:41:36 PM PDT 24
Finished Jul 13 06:41:38 PM PDT 24
Peak memory 219040 kb
Host smart-80fa7256-1346-46c6-95d9-a55340989f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331708892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3331708892
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.2461388097
Short name T732
Test name
Test status
Simulation time 155141936 ps
CPU time 1.17 seconds
Started Jul 13 06:41:36 PM PDT 24
Finished Jul 13 06:41:38 PM PDT 24
Peak memory 218856 kb
Host smart-7c87ea53-5e93-436f-be80-7583fcde78c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461388097 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.2461388097
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.925771576
Short name T92
Test name
Test status
Simulation time 203912857 ps
CPU time 2.89 seconds
Started Jul 13 06:41:39 PM PDT 24
Finished Jul 13 06:41:44 PM PDT 24
Peak memory 218948 kb
Host smart-6c340036-17f0-4ffd-ba1c-c9d6cb176f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925771576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.925771576
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.2007871690
Short name T121
Test name
Test status
Simulation time 97417829 ps
CPU time 1.33 seconds
Started Jul 13 06:41:37 PM PDT 24
Finished Jul 13 06:41:40 PM PDT 24
Peak memory 218348 kb
Host smart-1cdcd011-6865-40e5-a993-8c808180a7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007871690 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.2007871690
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.2956179419
Short name T945
Test name
Test status
Simulation time 113229604 ps
CPU time 1.22 seconds
Started Jul 13 06:41:34 PM PDT 24
Finished Jul 13 06:41:36 PM PDT 24
Peak memory 217604 kb
Host smart-3a4edb44-9b24-42db-8c5a-0ceb85793ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956179419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.2956179419
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.2295014895
Short name T950
Test name
Test status
Simulation time 47962010 ps
CPU time 1.23 seconds
Started Jul 13 06:41:39 PM PDT 24
Finished Jul 13 06:41:42 PM PDT 24
Peak memory 220128 kb
Host smart-69ef7231-b361-4eb8-a70e-e766c4199ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295014895 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.2295014895
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.258252392
Short name T685
Test name
Test status
Simulation time 63344895 ps
CPU time 1.61 seconds
Started Jul 13 06:41:38 PM PDT 24
Finished Jul 13 06:41:41 PM PDT 24
Peak memory 217600 kb
Host smart-48ddfccf-044e-4680-be73-30ae48a9a327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258252392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.258252392
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.1191521665
Short name T125
Test name
Test status
Simulation time 66229416 ps
CPU time 1.09 seconds
Started Jul 13 06:41:35 PM PDT 24
Finished Jul 13 06:41:37 PM PDT 24
Peak memory 218864 kb
Host smart-18fdaf67-f66e-4d6a-ba4b-1cf129ff51a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191521665 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.1191521665
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.969542667
Short name T693
Test name
Test status
Simulation time 37639356 ps
CPU time 1.21 seconds
Started Jul 13 06:41:37 PM PDT 24
Finished Jul 13 06:41:39 PM PDT 24
Peak memory 217508 kb
Host smart-3f013859-8463-4add-b5a5-baa8ef2795d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969542667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.969542667
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.3138402044
Short name T317
Test name
Test status
Simulation time 73331242 ps
CPU time 1.2 seconds
Started Jul 13 06:39:34 PM PDT 24
Finished Jul 13 06:39:36 PM PDT 24
Peak memory 220076 kb
Host smart-b3ee62f2-30c8-4e94-9d4f-626a6a2841fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138402044 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.3138402044
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.817096152
Short name T369
Test name
Test status
Simulation time 30344121 ps
CPU time 0.92 seconds
Started Jul 13 06:39:34 PM PDT 24
Finished Jul 13 06:39:35 PM PDT 24
Peak memory 215220 kb
Host smart-bc44d775-136f-4f5f-b4c4-9675cbd9a434
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817096152 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.817096152
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.3406625795
Short name T459
Test name
Test status
Simulation time 31236483 ps
CPU time 0.83 seconds
Started Jul 13 06:39:29 PM PDT 24
Finished Jul 13 06:39:30 PM PDT 24
Peak memory 216292 kb
Host smart-8b1f3740-dd2e-4452-bd5b-ee968ed53502
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406625795 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3406625795
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.1224410534
Short name T682
Test name
Test status
Simulation time 49784508 ps
CPU time 1.08 seconds
Started Jul 13 06:39:39 PM PDT 24
Finished Jul 13 06:39:41 PM PDT 24
Peak memory 218676 kb
Host smart-08118290-bc27-4fef-ad42-0e94ea49189c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224410534 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.1224410534
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.235323584
Short name T173
Test name
Test status
Simulation time 19755238 ps
CPU time 1.1 seconds
Started Jul 13 06:39:31 PM PDT 24
Finished Jul 13 06:39:33 PM PDT 24
Peak memory 218812 kb
Host smart-0afc4747-6b8a-4641-be07-3cf87c83aa13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235323584 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.235323584
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_smoke.2845923553
Short name T461
Test name
Test status
Simulation time 15636835 ps
CPU time 1.01 seconds
Started Jul 13 06:39:34 PM PDT 24
Finished Jul 13 06:39:36 PM PDT 24
Peak memory 215808 kb
Host smart-c44d9b79-8593-4c5d-a9ad-419b935582db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845923553 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.2845923553
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.216016169
Short name T249
Test name
Test status
Simulation time 929206045 ps
CPU time 3.45 seconds
Started Jul 13 06:39:29 PM PDT 24
Finished Jul 13 06:39:33 PM PDT 24
Peak memory 215616 kb
Host smart-d6b762a2-e994-43cc-982d-f5129bf636e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216016169 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.216016169
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/170.edn_alert.1414667811
Short name T556
Test name
Test status
Simulation time 51408094 ps
CPU time 1.24 seconds
Started Jul 13 06:41:42 PM PDT 24
Finished Jul 13 06:41:44 PM PDT 24
Peak memory 220540 kb
Host smart-5018f848-6436-41aa-a966-eaa45e7521e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414667811 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.1414667811
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.3990013774
Short name T849
Test name
Test status
Simulation time 67470195 ps
CPU time 2.45 seconds
Started Jul 13 06:41:40 PM PDT 24
Finished Jul 13 06:41:43 PM PDT 24
Peak memory 218960 kb
Host smart-7f198f2e-d5e2-4675-9d02-af039ff3301a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990013774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.3990013774
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.177174754
Short name T767
Test name
Test status
Simulation time 98087144 ps
CPU time 1.32 seconds
Started Jul 13 06:41:36 PM PDT 24
Finished Jul 13 06:41:38 PM PDT 24
Peak memory 218848 kb
Host smart-b93637cb-e15a-4e02-b783-faef384dad41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177174754 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.177174754
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.1452846028
Short name T646
Test name
Test status
Simulation time 41258960 ps
CPU time 1.35 seconds
Started Jul 13 06:41:40 PM PDT 24
Finished Jul 13 06:41:42 PM PDT 24
Peak memory 217552 kb
Host smart-c695576b-27bc-411c-a832-c106226de858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452846028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1452846028
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.608662859
Short name T488
Test name
Test status
Simulation time 35132694 ps
CPU time 1.2 seconds
Started Jul 13 06:41:37 PM PDT 24
Finished Jul 13 06:41:40 PM PDT 24
Peak memory 218440 kb
Host smart-26db5419-7ffa-4019-8e47-0a794638870c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608662859 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.608662859
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.2501477319
Short name T923
Test name
Test status
Simulation time 44092021 ps
CPU time 1.03 seconds
Started Jul 13 06:41:34 PM PDT 24
Finished Jul 13 06:41:35 PM PDT 24
Peak memory 217660 kb
Host smart-12de9e20-1c79-4247-a0ee-74a6a6082b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501477319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.2501477319
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.1870112935
Short name T261
Test name
Test status
Simulation time 79348335 ps
CPU time 1.23 seconds
Started Jul 13 06:41:38 PM PDT 24
Finished Jul 13 06:41:40 PM PDT 24
Peak memory 219972 kb
Host smart-62992413-ffc1-4fb9-b16d-880e92d776ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870112935 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.1870112935
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.539995577
Short name T350
Test name
Test status
Simulation time 98942873 ps
CPU time 1.21 seconds
Started Jul 13 06:41:34 PM PDT 24
Finished Jul 13 06:41:36 PM PDT 24
Peak memory 218820 kb
Host smart-55ca2125-ffda-41ce-b7e3-80cb5aeb928a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539995577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.539995577
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.3917156229
Short name T183
Test name
Test status
Simulation time 25604025 ps
CPU time 1.2 seconds
Started Jul 13 06:41:34 PM PDT 24
Finished Jul 13 06:41:36 PM PDT 24
Peak memory 220108 kb
Host smart-4dff8c14-e888-4537-9596-32ae51ad245b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917156229 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.3917156229
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.754444629
Short name T678
Test name
Test status
Simulation time 97490834 ps
CPU time 1.23 seconds
Started Jul 13 06:41:36 PM PDT 24
Finished Jul 13 06:41:38 PM PDT 24
Peak memory 217564 kb
Host smart-4e346446-8a85-4af3-a945-0d806f66b7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754444629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.754444629
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.404358726
Short name T145
Test name
Test status
Simulation time 90339533 ps
CPU time 1.21 seconds
Started Jul 13 06:41:33 PM PDT 24
Finished Jul 13 06:41:35 PM PDT 24
Peak memory 218620 kb
Host smart-9b6128ee-df3a-4583-8ec8-dc23e25df474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404358726 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.404358726
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.988385995
Short name T629
Test name
Test status
Simulation time 37592719 ps
CPU time 1.45 seconds
Started Jul 13 06:41:38 PM PDT 24
Finished Jul 13 06:41:40 PM PDT 24
Peak memory 218832 kb
Host smart-2d6d751f-dd9c-4b47-9763-6a1ce33c3939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988385995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.988385995
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.2592394936
Short name T420
Test name
Test status
Simulation time 82331201 ps
CPU time 1.13 seconds
Started Jul 13 06:41:36 PM PDT 24
Finished Jul 13 06:41:38 PM PDT 24
Peak memory 219868 kb
Host smart-2c273166-3bff-4582-9863-f1f383da7e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592394936 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.2592394936
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.2754044594
Short name T57
Test name
Test status
Simulation time 85183203 ps
CPU time 1.01 seconds
Started Jul 13 06:41:37 PM PDT 24
Finished Jul 13 06:41:40 PM PDT 24
Peak memory 215604 kb
Host smart-9587f102-5f30-40b2-a4f4-1285ba0f2080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754044594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2754044594
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.1328024105
Short name T489
Test name
Test status
Simulation time 112282007 ps
CPU time 1.23 seconds
Started Jul 13 06:41:37 PM PDT 24
Finished Jul 13 06:41:39 PM PDT 24
Peak memory 221012 kb
Host smart-fb3b5df9-1817-46c3-887a-e931d74af362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328024105 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.1328024105
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.3182224272
Short name T389
Test name
Test status
Simulation time 47821510 ps
CPU time 1.59 seconds
Started Jul 13 06:41:35 PM PDT 24
Finished Jul 13 06:41:37 PM PDT 24
Peak memory 217712 kb
Host smart-d15365d6-8209-4f61-949f-45388b66190c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182224272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.3182224272
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.1484422119
Short name T85
Test name
Test status
Simulation time 27588362 ps
CPU time 1.33 seconds
Started Jul 13 06:41:39 PM PDT 24
Finished Jul 13 06:41:42 PM PDT 24
Peak memory 218896 kb
Host smart-b474c0b4-051a-4ba1-93e0-1d383a0221df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484422119 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.1484422119
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.3731644511
Short name T69
Test name
Test status
Simulation time 105922799 ps
CPU time 1.42 seconds
Started Jul 13 06:41:33 PM PDT 24
Finished Jul 13 06:41:35 PM PDT 24
Peak memory 219008 kb
Host smart-35fd2aa9-1b74-4639-9dc3-cbdaa8008e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731644511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3731644511
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.4174421474
Short name T586
Test name
Test status
Simulation time 76620918 ps
CPU time 1.1 seconds
Started Jul 13 06:41:40 PM PDT 24
Finished Jul 13 06:41:42 PM PDT 24
Peak memory 218708 kb
Host smart-b96694f8-5467-4946-85ce-be3df4e01ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174421474 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.4174421474
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.3477207691
Short name T395
Test name
Test status
Simulation time 52131838 ps
CPU time 1.08 seconds
Started Jul 13 06:41:37 PM PDT 24
Finished Jul 13 06:41:40 PM PDT 24
Peak memory 217760 kb
Host smart-491caea3-59e1-4dbd-b7ec-db95177f1fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477207691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3477207691
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.2419547401
Short name T938
Test name
Test status
Simulation time 135781341 ps
CPU time 1.22 seconds
Started Jul 13 06:39:29 PM PDT 24
Finished Jul 13 06:39:31 PM PDT 24
Peak memory 218664 kb
Host smart-af6ec850-83f8-426a-beb6-2aa322cad066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419547401 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.2419547401
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.3964886025
Short name T565
Test name
Test status
Simulation time 15227287 ps
CPU time 1.08 seconds
Started Jul 13 06:39:32 PM PDT 24
Finished Jul 13 06:39:34 PM PDT 24
Peak memory 215056 kb
Host smart-e8995617-afb2-4d4e-ba8e-905166c3be4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964886025 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.3964886025
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.2805027506
Short name T713
Test name
Test status
Simulation time 11312145 ps
CPU time 0.87 seconds
Started Jul 13 06:39:33 PM PDT 24
Finished Jul 13 06:39:35 PM PDT 24
Peak memory 216572 kb
Host smart-a43fa325-20d2-4908-8f4c-8a25b85bd83a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805027506 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2805027506
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.1896810514
Short name T427
Test name
Test status
Simulation time 30891729 ps
CPU time 1.09 seconds
Started Jul 13 06:39:34 PM PDT 24
Finished Jul 13 06:39:36 PM PDT 24
Peak memory 218616 kb
Host smart-4ebcbe86-ff14-4f6d-9987-ec7bfc0129de
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896810514 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.1896810514
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.1263330743
Short name T36
Test name
Test status
Simulation time 27251023 ps
CPU time 0.91 seconds
Started Jul 13 06:39:34 PM PDT 24
Finished Jul 13 06:39:35 PM PDT 24
Peak memory 218560 kb
Host smart-f15a48c2-da1f-4ca1-8408-4d5696ba4eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263330743 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.1263330743
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.4273079656
Short name T98
Test name
Test status
Simulation time 38205854 ps
CPU time 1.52 seconds
Started Jul 13 06:39:31 PM PDT 24
Finished Jul 13 06:39:33 PM PDT 24
Peak memory 218888 kb
Host smart-37b10426-8a9d-4cd5-9b3d-733eade9c861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273079656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.4273079656
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.1249625681
Short name T604
Test name
Test status
Simulation time 33017055 ps
CPU time 0.92 seconds
Started Jul 13 06:39:32 PM PDT 24
Finished Jul 13 06:39:34 PM PDT 24
Peak memory 215772 kb
Host smart-cb97b4eb-65de-4c09-8750-6263da1b5f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249625681 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1249625681
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.1119238451
Short name T625
Test name
Test status
Simulation time 18611470 ps
CPU time 1.05 seconds
Started Jul 13 06:39:32 PM PDT 24
Finished Jul 13 06:39:34 PM PDT 24
Peak memory 215588 kb
Host smart-98d7c6a7-86bd-49fd-835c-89b4152a2ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119238451 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.1119238451
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.2995036821
Short name T456
Test name
Test status
Simulation time 227193511 ps
CPU time 2.9 seconds
Started Jul 13 06:39:39 PM PDT 24
Finished Jul 13 06:39:43 PM PDT 24
Peak memory 217460 kb
Host smart-c283d497-17c3-4332-a428-2810db21ac49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995036821 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.2995036821
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.3396743151
Short name T576
Test name
Test status
Simulation time 173122684716 ps
CPU time 474.23 seconds
Started Jul 13 06:39:33 PM PDT 24
Finished Jul 13 06:47:28 PM PDT 24
Peak memory 219040 kb
Host smart-b5f69862-c310-4130-9c11-1a32f9da62ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396743151 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.3396743151
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.4106822376
Short name T476
Test name
Test status
Simulation time 124177401 ps
CPU time 1.18 seconds
Started Jul 13 06:41:39 PM PDT 24
Finished Jul 13 06:41:41 PM PDT 24
Peak memory 217564 kb
Host smart-be00fbae-c4ef-416a-84c6-8a7bbdfbf5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106822376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.4106822376
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.1554979085
Short name T295
Test name
Test status
Simulation time 25045274 ps
CPU time 1.23 seconds
Started Jul 13 06:41:42 PM PDT 24
Finished Jul 13 06:41:44 PM PDT 24
Peak memory 219064 kb
Host smart-6ec15ee9-7572-4f7d-b0d8-4ef0edd8e54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554979085 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.1554979085
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.3268540153
Short name T931
Test name
Test status
Simulation time 34451794 ps
CPU time 1.23 seconds
Started Jul 13 06:41:39 PM PDT 24
Finished Jul 13 06:41:42 PM PDT 24
Peak memory 217552 kb
Host smart-0a81d0f0-185f-4665-9b5c-9ef129de4f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268540153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3268540153
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.3790674194
Short name T146
Test name
Test status
Simulation time 30766913 ps
CPU time 1.36 seconds
Started Jul 13 06:41:39 PM PDT 24
Finished Jul 13 06:41:42 PM PDT 24
Peak memory 220576 kb
Host smart-d47216a1-6ea3-4d0b-b424-4cb2bcd07a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790674194 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.3790674194
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.3165805148
Short name T814
Test name
Test status
Simulation time 278367754 ps
CPU time 4.17 seconds
Started Jul 13 06:41:35 PM PDT 24
Finished Jul 13 06:41:39 PM PDT 24
Peak memory 220536 kb
Host smart-b4a56a58-f2de-4a53-9ddd-1330c8c45808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165805148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.3165805148
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.1153075337
Short name T293
Test name
Test status
Simulation time 85861002 ps
CPU time 1.11 seconds
Started Jul 13 06:41:37 PM PDT 24
Finished Jul 13 06:41:39 PM PDT 24
Peak memory 218888 kb
Host smart-d213ffc4-f85d-47da-be7a-3f25e1618ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153075337 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.1153075337
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.196792824
Short name T749
Test name
Test status
Simulation time 50643277 ps
CPU time 2.17 seconds
Started Jul 13 06:41:39 PM PDT 24
Finished Jul 13 06:41:43 PM PDT 24
Peak memory 217856 kb
Host smart-e4dec182-62ce-4c9a-aa7c-3054f584c32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196792824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.196792824
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.3742922789
Short name T618
Test name
Test status
Simulation time 36437007 ps
CPU time 1.17 seconds
Started Jul 13 06:41:39 PM PDT 24
Finished Jul 13 06:41:41 PM PDT 24
Peak memory 219420 kb
Host smart-5844fb78-8dec-46ab-9f0a-aab9e5934b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742922789 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.3742922789
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.1822217456
Short name T655
Test name
Test status
Simulation time 104350373 ps
CPU time 1.34 seconds
Started Jul 13 06:41:39 PM PDT 24
Finished Jul 13 06:41:42 PM PDT 24
Peak memory 219944 kb
Host smart-0b7c6250-66a5-4dfd-9d86-5a286b884719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822217456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.1822217456
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.437635295
Short name T802
Test name
Test status
Simulation time 77040230 ps
CPU time 1.25 seconds
Started Jul 13 06:41:37 PM PDT 24
Finished Jul 13 06:41:40 PM PDT 24
Peak memory 219192 kb
Host smart-7ae0a39e-64d6-4d37-a9ba-fc80dd97f354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437635295 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.437635295
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.1066483894
Short name T439
Test name
Test status
Simulation time 50612144 ps
CPU time 1.13 seconds
Started Jul 13 06:41:37 PM PDT 24
Finished Jul 13 06:41:39 PM PDT 24
Peak memory 218992 kb
Host smart-5eb9285c-c4a1-48b6-87f1-b2b6b57ab80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066483894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.1066483894
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.1273414518
Short name T256
Test name
Test status
Simulation time 73423883 ps
CPU time 1.14 seconds
Started Jul 13 06:41:37 PM PDT 24
Finished Jul 13 06:41:39 PM PDT 24
Peak memory 220128 kb
Host smart-7f3581c8-8dbd-42f9-86da-8bafb47b4e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273414518 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.1273414518
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.3279994363
Short name T349
Test name
Test status
Simulation time 125450914 ps
CPU time 1.08 seconds
Started Jul 13 06:41:37 PM PDT 24
Finished Jul 13 06:41:40 PM PDT 24
Peak memory 217524 kb
Host smart-3000e221-efae-4b9b-b1d4-a74edde62a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279994363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.3279994363
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.2707829673
Short name T951
Test name
Test status
Simulation time 44541977 ps
CPU time 1.28 seconds
Started Jul 13 06:41:39 PM PDT 24
Finished Jul 13 06:41:42 PM PDT 24
Peak memory 216012 kb
Host smart-706e0a37-0660-42c3-8c59-727aa3afb7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707829673 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.2707829673
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.3034573378
Short name T355
Test name
Test status
Simulation time 49161748 ps
CPU time 1.82 seconds
Started Jul 13 06:41:36 PM PDT 24
Finished Jul 13 06:41:39 PM PDT 24
Peak memory 217704 kb
Host smart-c6534feb-e25c-4eb3-aa7f-9ea0440111a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034573378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.3034573378
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.1465900017
Short name T160
Test name
Test status
Simulation time 74933330 ps
CPU time 1.18 seconds
Started Jul 13 06:41:37 PM PDT 24
Finished Jul 13 06:41:39 PM PDT 24
Peak memory 219080 kb
Host smart-a962f239-0cc1-455c-9d99-475c4917695c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465900017 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.1465900017
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.1489701478
Short name T580
Test name
Test status
Simulation time 74058448 ps
CPU time 1.07 seconds
Started Jul 13 06:41:38 PM PDT 24
Finished Jul 13 06:41:40 PM PDT 24
Peak memory 217512 kb
Host smart-81945625-8517-43d7-a1d2-542d822123bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489701478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.1489701478
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert_test.2073295185
Short name T877
Test name
Test status
Simulation time 32648734 ps
CPU time 0.84 seconds
Started Jul 13 06:39:40 PM PDT 24
Finished Jul 13 06:39:42 PM PDT 24
Peak memory 206820 kb
Host smart-b276a421-f0ef-4c10-af40-d8a103cc46ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073295185 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2073295185
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.987394554
Short name T760
Test name
Test status
Simulation time 38538995 ps
CPU time 0.82 seconds
Started Jul 13 06:39:28 PM PDT 24
Finished Jul 13 06:39:29 PM PDT 24
Peak memory 216248 kb
Host smart-98d605bf-d79a-4f39-bfb6-7f8516e6b93f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987394554 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.987394554
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_err.3211253029
Short name T221
Test name
Test status
Simulation time 23564072 ps
CPU time 1.1 seconds
Started Jul 13 06:39:40 PM PDT 24
Finished Jul 13 06:39:42 PM PDT 24
Peak memory 218824 kb
Host smart-3a743fe0-9e4b-44a8-8cc9-3b931351eb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211253029 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.3211253029
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.3672102259
Short name T798
Test name
Test status
Simulation time 84563901 ps
CPU time 1.25 seconds
Started Jul 13 06:39:29 PM PDT 24
Finished Jul 13 06:39:31 PM PDT 24
Peak memory 219376 kb
Host smart-b9e04966-6693-4e15-bc9d-0903405861c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672102259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3672102259
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_smoke.1644480441
Short name T859
Test name
Test status
Simulation time 47460550 ps
CPU time 0.98 seconds
Started Jul 13 06:39:30 PM PDT 24
Finished Jul 13 06:39:32 PM PDT 24
Peak memory 215632 kb
Host smart-69873063-81ef-4a5e-a439-e1a8870e58b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644480441 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.1644480441
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.347408993
Short name T250
Test name
Test status
Simulation time 69220613 ps
CPU time 1.93 seconds
Started Jul 13 06:39:28 PM PDT 24
Finished Jul 13 06:39:30 PM PDT 24
Peak memory 215616 kb
Host smart-782d8839-f2c8-409a-af52-da92fd173ca0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347408993 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.347408993
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.3807752625
Short name T234
Test name
Test status
Simulation time 558771846817 ps
CPU time 2208.87 seconds
Started Jul 13 06:39:29 PM PDT 24
Finished Jul 13 07:16:19 PM PDT 24
Peak memory 227072 kb
Host smart-22146ea5-97ec-42c4-a0df-caad5b21e4f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807752625 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.3807752625
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.457021650
Short name T818
Test name
Test status
Simulation time 24886633 ps
CPU time 1.16 seconds
Started Jul 13 06:41:44 PM PDT 24
Finished Jul 13 06:41:46 PM PDT 24
Peak memory 218800 kb
Host smart-78bc2487-8b9a-4b8f-b4e3-a7fb8cc99778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457021650 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.457021650
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/191.edn_alert.2951765361
Short name T119
Test name
Test status
Simulation time 44670140 ps
CPU time 1.23 seconds
Started Jul 13 06:41:44 PM PDT 24
Finished Jul 13 06:41:46 PM PDT 24
Peak memory 221900 kb
Host smart-0215f905-29cd-49d0-a8c6-0a4d06199114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951765361 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.2951765361
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.338310959
Short name T503
Test name
Test status
Simulation time 90548155 ps
CPU time 2.1 seconds
Started Jul 13 06:41:44 PM PDT 24
Finished Jul 13 06:41:47 PM PDT 24
Peak memory 220592 kb
Host smart-2c3b42ba-f3e9-445e-bfe1-a5e628e45ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338310959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.338310959
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.446022962
Short name T971
Test name
Test status
Simulation time 175863236 ps
CPU time 1.05 seconds
Started Jul 13 06:41:42 PM PDT 24
Finished Jul 13 06:41:44 PM PDT 24
Peak memory 219172 kb
Host smart-5d4981e1-df86-4627-8236-02a6c48ec9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446022962 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.446022962
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.1444801247
Short name T830
Test name
Test status
Simulation time 48296307 ps
CPU time 1.1 seconds
Started Jul 13 06:41:42 PM PDT 24
Finished Jul 13 06:41:44 PM PDT 24
Peak memory 219248 kb
Host smart-76b203c8-5ac7-4c8e-9f96-90131955e408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444801247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.1444801247
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.3852496220
Short name T856
Test name
Test status
Simulation time 85644859 ps
CPU time 1.21 seconds
Started Jul 13 06:41:43 PM PDT 24
Finished Jul 13 06:41:46 PM PDT 24
Peak memory 218756 kb
Host smart-584d2abf-da40-49ed-ba63-8e7d318f2179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852496220 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.3852496220
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.2933336747
Short name T97
Test name
Test status
Simulation time 124469847 ps
CPU time 3.17 seconds
Started Jul 13 06:41:44 PM PDT 24
Finished Jul 13 06:41:48 PM PDT 24
Peak memory 219416 kb
Host smart-b3c56ca1-548d-48d2-b79e-ddccd728c08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933336747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.2933336747
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.2300703457
Short name T930
Test name
Test status
Simulation time 47312312 ps
CPU time 1.23 seconds
Started Jul 13 06:41:44 PM PDT 24
Finished Jul 13 06:41:46 PM PDT 24
Peak memory 220140 kb
Host smart-c58527e3-0993-4283-b486-8d7f9fc6c99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300703457 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.2300703457
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.3107202383
Short name T343
Test name
Test status
Simulation time 78189833 ps
CPU time 1.1 seconds
Started Jul 13 06:41:41 PM PDT 24
Finished Jul 13 06:41:44 PM PDT 24
Peak memory 218912 kb
Host smart-6a634ae4-714f-4dbd-a418-221d8e181d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107202383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3107202383
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.3798800427
Short name T772
Test name
Test status
Simulation time 29120857 ps
CPU time 1.39 seconds
Started Jul 13 06:41:42 PM PDT 24
Finished Jul 13 06:41:44 PM PDT 24
Peak memory 221048 kb
Host smart-25fc960d-6a6d-46e8-b3c4-ce9b8f26fb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798800427 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.3798800427
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.1623336470
Short name T932
Test name
Test status
Simulation time 117968079 ps
CPU time 1.9 seconds
Started Jul 13 06:41:49 PM PDT 24
Finished Jul 13 06:41:51 PM PDT 24
Peak memory 220452 kb
Host smart-0f9e3a0b-a355-443b-b1b4-3ecf5279c2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623336470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.1623336470
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.1739163439
Short name T432
Test name
Test status
Simulation time 41829709 ps
CPU time 1.19 seconds
Started Jul 13 06:41:44 PM PDT 24
Finished Jul 13 06:41:47 PM PDT 24
Peak memory 219596 kb
Host smart-a8dad2a1-6f66-4ddd-9726-0e2e7e978310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739163439 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.1739163439
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.295169846
Short name T613
Test name
Test status
Simulation time 47519424 ps
CPU time 1.58 seconds
Started Jul 13 06:41:42 PM PDT 24
Finished Jul 13 06:41:44 PM PDT 24
Peak memory 220320 kb
Host smart-b8f24430-aef8-4740-8e67-cf5c5deffa9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295169846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.295169846
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.605094013
Short name T262
Test name
Test status
Simulation time 57091115 ps
CPU time 1.26 seconds
Started Jul 13 06:41:44 PM PDT 24
Finished Jul 13 06:41:47 PM PDT 24
Peak memory 215960 kb
Host smart-dccc08a2-5f53-466d-aa90-4244778bfdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605094013 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.605094013
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.3894798320
Short name T963
Test name
Test status
Simulation time 43668332 ps
CPU time 1.5 seconds
Started Jul 13 06:41:43 PM PDT 24
Finished Jul 13 06:41:45 PM PDT 24
Peak memory 219040 kb
Host smart-9f377c19-b40a-4b24-a0dc-0fbc0f8621e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894798320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3894798320
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.1138357367
Short name T803
Test name
Test status
Simulation time 24540494 ps
CPU time 1.29 seconds
Started Jul 13 06:41:42 PM PDT 24
Finished Jul 13 06:41:44 PM PDT 24
Peak memory 220820 kb
Host smart-66e49d49-9ab8-4405-bcce-adc8dc864d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138357367 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.1138357367
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.4265183590
Short name T54
Test name
Test status
Simulation time 31283215 ps
CPU time 1.34 seconds
Started Jul 13 06:41:43 PM PDT 24
Finished Jul 13 06:41:46 PM PDT 24
Peak memory 220344 kb
Host smart-41d64592-874a-4a91-925b-f0b837a4039b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265183590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.4265183590
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.1063836905
Short name T496
Test name
Test status
Simulation time 26929086 ps
CPU time 1.27 seconds
Started Jul 13 06:38:59 PM PDT 24
Finished Jul 13 06:39:02 PM PDT 24
Peak memory 219760 kb
Host smart-2bc241b4-f021-4465-b908-1c3c7492b2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063836905 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.1063836905
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.2548104211
Short name T987
Test name
Test status
Simulation time 14251611 ps
CPU time 0.94 seconds
Started Jul 13 06:39:00 PM PDT 24
Finished Jul 13 06:39:02 PM PDT 24
Peak memory 215472 kb
Host smart-b7e9a453-6561-4415-9cf5-449fdf8f1aeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548104211 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.2548104211
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.2460798116
Short name T368
Test name
Test status
Simulation time 12089704 ps
CPU time 0.91 seconds
Started Jul 13 06:39:00 PM PDT 24
Finished Jul 13 06:39:02 PM PDT 24
Peak memory 216532 kb
Host smart-de98fc42-881d-45b5-831e-aa0d10428660
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460798116 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2460798116
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.571580265
Short name T940
Test name
Test status
Simulation time 30453158 ps
CPU time 1.06 seconds
Started Jul 13 06:39:00 PM PDT 24
Finished Jul 13 06:39:03 PM PDT 24
Peak memory 217124 kb
Host smart-c5cfe6e5-0a5e-462d-ae3d-c9908514fe99
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571580265 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_dis
able_auto_req_mode.571580265
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.126216486
Short name T192
Test name
Test status
Simulation time 19188543 ps
CPU time 1.23 seconds
Started Jul 13 06:38:57 PM PDT 24
Finished Jul 13 06:38:58 PM PDT 24
Peak memory 224140 kb
Host smart-7be01cb6-8173-4d14-b4c8-83b7ef254287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126216486 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.126216486
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.615542698
Short name T323
Test name
Test status
Simulation time 39931943 ps
CPU time 1.16 seconds
Started Jul 13 06:38:49 PM PDT 24
Finished Jul 13 06:38:50 PM PDT 24
Peak memory 220240 kb
Host smart-1f5c1dd5-3dd7-46f1-8d4f-ec179ddfe886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615542698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.615542698
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.4235162696
Short name T836
Test name
Test status
Simulation time 33917392 ps
CPU time 0.9 seconds
Started Jul 13 06:38:49 PM PDT 24
Finished Jul 13 06:38:50 PM PDT 24
Peak memory 215924 kb
Host smart-d353be51-e7cd-43d2-950b-562cc8bbb30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235162696 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.4235162696
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.1164283931
Short name T29
Test name
Test status
Simulation time 43168564 ps
CPU time 0.9 seconds
Started Jul 13 06:38:48 PM PDT 24
Finished Jul 13 06:38:49 PM PDT 24
Peak memory 207432 kb
Host smart-b5268380-881d-4176-b5f4-bc4e9690b110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164283931 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.1164283931
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.4021388254
Short name T68
Test name
Test status
Simulation time 507522138 ps
CPU time 7.24 seconds
Started Jul 13 06:39:01 PM PDT 24
Finished Jul 13 06:39:10 PM PDT 24
Peak memory 236092 kb
Host smart-fcee1aa4-ae46-4cd2-9e14-535736806293
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021388254 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.4021388254
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.1121965955
Short name T853
Test name
Test status
Simulation time 50518870 ps
CPU time 0.99 seconds
Started Jul 13 06:38:48 PM PDT 24
Finished Jul 13 06:38:49 PM PDT 24
Peak memory 215600 kb
Host smart-1eb4f098-b14d-4af3-a8ff-ccabd2aabbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121965955 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.1121965955
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.2436004441
Short name T709
Test name
Test status
Simulation time 373216237 ps
CPU time 6.83 seconds
Started Jul 13 06:38:46 PM PDT 24
Finished Jul 13 06:38:54 PM PDT 24
Peak memory 217512 kb
Host smart-52e26b96-6fa5-4048-ad99-4246af422dc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436004441 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2436004441
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1751673691
Short name T42
Test name
Test status
Simulation time 304912053826 ps
CPU time 502.06 seconds
Started Jul 13 06:38:48 PM PDT 24
Finished Jul 13 06:47:10 PM PDT 24
Peak memory 228040 kb
Host smart-d99f71ce-efc4-41f2-82ae-072580274866
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751673691 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1751673691
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.2065972544
Short name T893
Test name
Test status
Simulation time 67318943 ps
CPU time 1.23 seconds
Started Jul 13 06:39:30 PM PDT 24
Finished Jul 13 06:39:32 PM PDT 24
Peak memory 222092 kb
Host smart-517498ba-e9a7-4b7b-a2a9-99d912a45827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065972544 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.2065972544
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.2363841136
Short name T78
Test name
Test status
Simulation time 14866443 ps
CPU time 0.93 seconds
Started Jul 13 06:39:30 PM PDT 24
Finished Jul 13 06:39:31 PM PDT 24
Peak memory 207060 kb
Host smart-e03fb374-e417-433d-9901-20d404c8a3b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363841136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2363841136
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.3083632442
Short name T636
Test name
Test status
Simulation time 17680634 ps
CPU time 0.89 seconds
Started Jul 13 06:39:29 PM PDT 24
Finished Jul 13 06:39:30 PM PDT 24
Peak memory 216344 kb
Host smart-03bf03a7-cfeb-4cc3-bf45-6f7ca0d636e6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083632442 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3083632442
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_err.2077783044
Short name T881
Test name
Test status
Simulation time 67347392 ps
CPU time 1.23 seconds
Started Jul 13 06:39:40 PM PDT 24
Finished Jul 13 06:39:42 PM PDT 24
Peak memory 219992 kb
Host smart-50e522b7-5a8f-4168-a027-932cdeaee677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077783044 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2077783044
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.265331921
Short name T329
Test name
Test status
Simulation time 169181913 ps
CPU time 1.26 seconds
Started Jul 13 06:39:39 PM PDT 24
Finished Jul 13 06:39:41 PM PDT 24
Peak memory 219068 kb
Host smart-208a94b0-e60f-455a-b2a3-6f4c925f080d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265331921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.265331921
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.536316973
Short name T401
Test name
Test status
Simulation time 32249672 ps
CPU time 0.88 seconds
Started Jul 13 06:39:30 PM PDT 24
Finished Jul 13 06:39:31 PM PDT 24
Peak memory 215884 kb
Host smart-61d0f2f7-00ce-4f2d-86b0-e159966fef90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536316973 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.536316973
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.547093699
Short name T679
Test name
Test status
Simulation time 17924228 ps
CPU time 0.95 seconds
Started Jul 13 06:39:33 PM PDT 24
Finished Jul 13 06:39:35 PM PDT 24
Peak memory 215636 kb
Host smart-f0c48cb5-f69e-478d-824b-a6ecb1bf9134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547093699 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.547093699
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.2387292582
Short name T918
Test name
Test status
Simulation time 768267416 ps
CPU time 4.29 seconds
Started Jul 13 06:39:33 PM PDT 24
Finished Jul 13 06:39:38 PM PDT 24
Peak memory 217640 kb
Host smart-9fd73e9c-88f9-4f6e-aaa4-8d2391eccce1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387292582 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2387292582
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.1533197357
Short name T466
Test name
Test status
Simulation time 166170396020 ps
CPU time 1788.5 seconds
Started Jul 13 06:39:34 PM PDT 24
Finished Jul 13 07:09:24 PM PDT 24
Peak memory 225888 kb
Host smart-e6bdb339-d9be-4cc9-b8a2-91fd8b7f7eb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533197357 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.1533197357
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.1416904769
Short name T116
Test name
Test status
Simulation time 44418237 ps
CPU time 1.11 seconds
Started Jul 13 06:41:43 PM PDT 24
Finished Jul 13 06:41:46 PM PDT 24
Peak memory 217808 kb
Host smart-3ce57e4b-7b2d-447a-8a91-c77ed29e9ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416904769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.1416904769
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.83092431
Short name T523
Test name
Test status
Simulation time 66858116 ps
CPU time 1.07 seconds
Started Jul 13 06:41:42 PM PDT 24
Finished Jul 13 06:41:44 PM PDT 24
Peak memory 217628 kb
Host smart-46971732-ec12-4c90-ae20-39ff4257d3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83092431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.83092431
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.275735023
Short name T619
Test name
Test status
Simulation time 97776802 ps
CPU time 0.95 seconds
Started Jul 13 06:41:44 PM PDT 24
Finished Jul 13 06:41:46 PM PDT 24
Peak memory 217596 kb
Host smart-4c737a70-8866-40b3-b896-523125fd1809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275735023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.275735023
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.170880345
Short name T808
Test name
Test status
Simulation time 92783308 ps
CPU time 1.43 seconds
Started Jul 13 06:41:42 PM PDT 24
Finished Jul 13 06:41:44 PM PDT 24
Peak memory 218964 kb
Host smart-2d39f25e-4ca0-4d7c-b9aa-1af567524da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170880345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.170880345
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.2702786098
Short name T20
Test name
Test status
Simulation time 99381454 ps
CPU time 3.19 seconds
Started Jul 13 06:41:49 PM PDT 24
Finished Jul 13 06:41:52 PM PDT 24
Peak memory 220528 kb
Host smart-1f4231c2-756a-412b-9c9d-9b26c15ceece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702786098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.2702786098
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3008731999
Short name T731
Test name
Test status
Simulation time 34010070 ps
CPU time 1.29 seconds
Started Jul 13 06:41:48 PM PDT 24
Finished Jul 13 06:41:50 PM PDT 24
Peak memory 217480 kb
Host smart-cfd04cb3-bfaa-4887-a803-a241b155463b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008731999 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3008731999
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.3347681138
Short name T728
Test name
Test status
Simulation time 42396877 ps
CPU time 1.51 seconds
Started Jul 13 06:41:43 PM PDT 24
Finished Jul 13 06:41:46 PM PDT 24
Peak memory 220472 kb
Host smart-5d3a402c-0100-486f-81aa-5cdab217efdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347681138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3347681138
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.3162532847
Short name T822
Test name
Test status
Simulation time 58735981 ps
CPU time 2.34 seconds
Started Jul 13 06:41:42 PM PDT 24
Finished Jul 13 06:41:45 PM PDT 24
Peak memory 220300 kb
Host smart-ef2796bc-4776-4f88-bba8-92a1ac66e64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162532847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.3162532847
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.3633187018
Short name T920
Test name
Test status
Simulation time 177914403 ps
CPU time 1.11 seconds
Started Jul 13 06:41:42 PM PDT 24
Finished Jul 13 06:41:44 PM PDT 24
Peak memory 220096 kb
Host smart-1122744f-6831-4856-a6be-1c3d3aadb25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633187018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.3633187018
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.1684893783
Short name T384
Test name
Test status
Simulation time 162282752 ps
CPU time 1.31 seconds
Started Jul 13 06:39:38 PM PDT 24
Finished Jul 13 06:39:41 PM PDT 24
Peak memory 219552 kb
Host smart-6d476f53-8698-454b-80ef-ae3dafb60a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684893783 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.1684893783
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.2871705801
Short name T527
Test name
Test status
Simulation time 34147878 ps
CPU time 0.91 seconds
Started Jul 13 06:39:38 PM PDT 24
Finished Jul 13 06:39:40 PM PDT 24
Peak memory 207044 kb
Host smart-d70f766d-51de-4955-be62-037a15029612
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871705801 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2871705801
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.4265112907
Short name T371
Test name
Test status
Simulation time 21545205 ps
CPU time 0.88 seconds
Started Jul 13 06:39:39 PM PDT 24
Finished Jul 13 06:39:40 PM PDT 24
Peak memory 216252 kb
Host smart-2a7d1c05-7c3b-42da-8aa6-4ea89c32cc55
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265112907 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.4265112907
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.1199679428
Short name T725
Test name
Test status
Simulation time 73877181 ps
CPU time 1.06 seconds
Started Jul 13 06:39:38 PM PDT 24
Finished Jul 13 06:39:40 PM PDT 24
Peak memory 217300 kb
Host smart-d22c7928-4c38-4e9b-8b13-6416eb7465c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199679428 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.1199679428
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.3443167278
Short name T127
Test name
Test status
Simulation time 31864212 ps
CPU time 1.01 seconds
Started Jul 13 06:39:36 PM PDT 24
Finished Jul 13 06:39:38 PM PDT 24
Peak memory 219984 kb
Host smart-7c048d03-b22e-4ad2-8b7e-3f83d1ca10e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443167278 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3443167278
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.2961264324
Short name T237
Test name
Test status
Simulation time 95599262 ps
CPU time 1.14 seconds
Started Jul 13 06:39:39 PM PDT 24
Finished Jul 13 06:39:41 PM PDT 24
Peak memory 217576 kb
Host smart-00c36e01-48e4-4569-a8e2-fa808313493b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961264324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2961264324
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.459290165
Short name T207
Test name
Test status
Simulation time 22547519 ps
CPU time 1.12 seconds
Started Jul 13 06:39:37 PM PDT 24
Finished Jul 13 06:39:38 PM PDT 24
Peak memory 215820 kb
Host smart-d6797d42-72ed-4075-a297-15fe021e0e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459290165 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.459290165
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.3588717852
Short name T426
Test name
Test status
Simulation time 133295379 ps
CPU time 1 seconds
Started Jul 13 06:39:36 PM PDT 24
Finished Jul 13 06:39:38 PM PDT 24
Peak memory 215608 kb
Host smart-0bebd445-071c-4267-9fe6-acb6c84aa4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588717852 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.3588717852
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.998230863
Short name T536
Test name
Test status
Simulation time 306853804 ps
CPU time 3.58 seconds
Started Jul 13 06:39:41 PM PDT 24
Finished Jul 13 06:39:45 PM PDT 24
Peak memory 217572 kb
Host smart-06e279e5-9e16-46f2-b0c5-8cb8d2a1159e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998230863 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.998230863
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.2443502019
Short name T610
Test name
Test status
Simulation time 366290112959 ps
CPU time 1356.53 seconds
Started Jul 13 06:39:38 PM PDT 24
Finished Jul 13 07:02:15 PM PDT 24
Peak memory 224264 kb
Host smart-ef3ad329-55d6-47dc-a14a-16e1943cbb0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443502019 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.2443502019
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.2633552668
Short name T73
Test name
Test status
Simulation time 120842532 ps
CPU time 2.71 seconds
Started Jul 13 06:41:45 PM PDT 24
Finished Jul 13 06:41:48 PM PDT 24
Peak memory 220536 kb
Host smart-4f8400f0-f343-4b50-be43-52a052686695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633552668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.2633552668
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.2680250534
Short name T904
Test name
Test status
Simulation time 44239127 ps
CPU time 1.4 seconds
Started Jul 13 06:41:43 PM PDT 24
Finished Jul 13 06:41:46 PM PDT 24
Peak memory 218972 kb
Host smart-cb98b505-c50f-43b9-9691-783c178f2d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680250534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.2680250534
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.2515682159
Short name T110
Test name
Test status
Simulation time 34664745 ps
CPU time 1.14 seconds
Started Jul 13 06:41:42 PM PDT 24
Finished Jul 13 06:41:44 PM PDT 24
Peak memory 217592 kb
Host smart-2d29ca19-ee14-4019-b57d-eb6496c3576f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515682159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.2515682159
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3449325243
Short name T622
Test name
Test status
Simulation time 44650611 ps
CPU time 1.6 seconds
Started Jul 13 06:41:44 PM PDT 24
Finished Jul 13 06:41:47 PM PDT 24
Peak memory 218784 kb
Host smart-584bd805-9ad8-45d1-8f0a-e9b70d3f0946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449325243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3449325243
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.1691361605
Short name T941
Test name
Test status
Simulation time 56223086 ps
CPU time 1.04 seconds
Started Jul 13 06:41:44 PM PDT 24
Finished Jul 13 06:41:46 PM PDT 24
Peak memory 219768 kb
Host smart-ffdc016b-82d2-4385-a5cc-9beff62bc71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691361605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.1691361605
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.4121247471
Short name T662
Test name
Test status
Simulation time 33597247 ps
CPU time 1.16 seconds
Started Jul 13 06:41:49 PM PDT 24
Finished Jul 13 06:41:50 PM PDT 24
Peak memory 220300 kb
Host smart-a3bc546a-4d53-4aee-91d3-35df7de1e1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121247471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.4121247471
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.1158062307
Short name T87
Test name
Test status
Simulation time 67336614 ps
CPU time 1.15 seconds
Started Jul 13 06:41:43 PM PDT 24
Finished Jul 13 06:41:46 PM PDT 24
Peak memory 217572 kb
Host smart-fb93b1e9-8f53-42f4-afe1-f0e029ba9cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158062307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1158062307
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.2996910902
Short name T482
Test name
Test status
Simulation time 64672861 ps
CPU time 1.1 seconds
Started Jul 13 06:41:53 PM PDT 24
Finished Jul 13 06:41:56 PM PDT 24
Peak memory 217668 kb
Host smart-f1e47ad1-b6a0-42ee-9a62-5f5e2546399d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996910902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.2996910902
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.2401564452
Short name T620
Test name
Test status
Simulation time 35940983 ps
CPU time 1.1 seconds
Started Jul 13 06:41:54 PM PDT 24
Finished Jul 13 06:41:56 PM PDT 24
Peak memory 217480 kb
Host smart-f97e6e1a-e9a4-4bad-98e0-be680e70919d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401564452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2401564452
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.793250328
Short name T687
Test name
Test status
Simulation time 59202553 ps
CPU time 1.61 seconds
Started Jul 13 06:41:52 PM PDT 24
Finished Jul 13 06:41:54 PM PDT 24
Peak memory 219132 kb
Host smart-2590f3c8-c0bb-4de3-bd45-872dadf08b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793250328 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.793250328
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.3713149800
Short name T444
Test name
Test status
Simulation time 23882939 ps
CPU time 1.22 seconds
Started Jul 13 06:39:39 PM PDT 24
Finished Jul 13 06:39:41 PM PDT 24
Peak memory 219932 kb
Host smart-59fc36ee-61bb-45f5-a81e-b8d1d9b2218c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713149800 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.3713149800
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.3591437368
Short name T896
Test name
Test status
Simulation time 31725949 ps
CPU time 0.98 seconds
Started Jul 13 06:39:38 PM PDT 24
Finished Jul 13 06:39:40 PM PDT 24
Peak memory 215312 kb
Host smart-cbf94da5-c996-47e8-acda-2e2dd37ef25a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591437368 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.3591437368
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.3603315547
Short name T167
Test name
Test status
Simulation time 17161520 ps
CPU time 0.9 seconds
Started Jul 13 06:39:37 PM PDT 24
Finished Jul 13 06:39:38 PM PDT 24
Peak memory 215884 kb
Host smart-a0fbe8e8-c1be-4d8a-8acd-fb85c817610a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603315547 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3603315547
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_err.3326199375
Short name T884
Test name
Test status
Simulation time 19287159 ps
CPU time 1.04 seconds
Started Jul 13 06:39:35 PM PDT 24
Finished Jul 13 06:39:37 PM PDT 24
Peak memory 218872 kb
Host smart-d0c59f93-0b66-4023-8da2-8548ae141c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326199375 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.3326199375
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.926877234
Short name T3
Test name
Test status
Simulation time 84384492 ps
CPU time 1.32 seconds
Started Jul 13 06:39:36 PM PDT 24
Finished Jul 13 06:39:38 PM PDT 24
Peak memory 219088 kb
Host smart-d0ec8b34-032c-45d8-84ce-d13f4d81205a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926877234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.926877234
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.374176217
Short name T6
Test name
Test status
Simulation time 31813386 ps
CPU time 0.88 seconds
Started Jul 13 06:39:41 PM PDT 24
Finished Jul 13 06:39:42 PM PDT 24
Peak memory 215864 kb
Host smart-d02539c9-8ef4-4d30-9180-cbf77be95d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374176217 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.374176217
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.3167943191
Short name T562
Test name
Test status
Simulation time 16300972 ps
CPU time 1.06 seconds
Started Jul 13 06:39:37 PM PDT 24
Finished Jul 13 06:39:39 PM PDT 24
Peak memory 215588 kb
Host smart-28b205a5-3dbf-4894-95ae-34cdba5c2760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167943191 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.3167943191
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.4082303080
Short name T784
Test name
Test status
Simulation time 153748519 ps
CPU time 2.13 seconds
Started Jul 13 06:39:41 PM PDT 24
Finished Jul 13 06:39:44 PM PDT 24
Peak memory 217492 kb
Host smart-e4caa1b4-2012-413e-adb2-97f177dbd889
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082303080 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.4082303080
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.343084321
Short name T708
Test name
Test status
Simulation time 34164561058 ps
CPU time 844.25 seconds
Started Jul 13 06:39:38 PM PDT 24
Finished Jul 13 06:53:44 PM PDT 24
Peak memory 221168 kb
Host smart-7544811c-8399-460f-b9bd-85387dd1c3f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343084321 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.343084321
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.3509308196
Short name T574
Test name
Test status
Simulation time 51128610 ps
CPU time 1.78 seconds
Started Jul 13 06:41:54 PM PDT 24
Finished Jul 13 06:41:57 PM PDT 24
Peak memory 218952 kb
Host smart-80935596-9a0d-4d2c-85e1-0e839020b906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509308196 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.3509308196
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.1690479931
Short name T962
Test name
Test status
Simulation time 245428712 ps
CPU time 1.4 seconds
Started Jul 13 06:41:56 PM PDT 24
Finished Jul 13 06:41:58 PM PDT 24
Peak memory 220736 kb
Host smart-7a3338f1-4951-4a68-9c80-cd73f2da7f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690479931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.1690479931
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.2652022283
Short name T857
Test name
Test status
Simulation time 264438832 ps
CPU time 3.24 seconds
Started Jul 13 06:41:53 PM PDT 24
Finished Jul 13 06:41:57 PM PDT 24
Peak memory 217840 kb
Host smart-ff1bc353-c122-45cf-a0ce-5536475de9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652022283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2652022283
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.3515653392
Short name T505
Test name
Test status
Simulation time 49368351 ps
CPU time 1.14 seconds
Started Jul 13 06:41:51 PM PDT 24
Finished Jul 13 06:41:53 PM PDT 24
Peak memory 218752 kb
Host smart-d1fe7d02-22d3-470f-8287-6ac832f49e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515653392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.3515653392
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.305209691
Short name T521
Test name
Test status
Simulation time 134805592 ps
CPU time 1.1 seconds
Started Jul 13 06:41:56 PM PDT 24
Finished Jul 13 06:41:58 PM PDT 24
Peak memory 217520 kb
Host smart-b21be9e1-bb9e-4452-89f1-d2505a1a726d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305209691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.305209691
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.817419371
Short name T616
Test name
Test status
Simulation time 44696966 ps
CPU time 1.57 seconds
Started Jul 13 06:41:55 PM PDT 24
Finished Jul 13 06:41:57 PM PDT 24
Peak memory 218832 kb
Host smart-594f3338-e3dc-4045-bb50-f56a3431e4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817419371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.817419371
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.1331232096
Short name T959
Test name
Test status
Simulation time 65692907 ps
CPU time 1.27 seconds
Started Jul 13 06:41:53 PM PDT 24
Finished Jul 13 06:41:55 PM PDT 24
Peak memory 217840 kb
Host smart-2459c361-5edf-4b67-990e-a982fe4fea84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331232096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.1331232096
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.3990811274
Short name T490
Test name
Test status
Simulation time 59706025 ps
CPU time 1.03 seconds
Started Jul 13 06:41:55 PM PDT 24
Finished Jul 13 06:41:57 PM PDT 24
Peak memory 217732 kb
Host smart-5a2300fd-a80f-45c6-a027-efe5b90694b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990811274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.3990811274
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.1481486260
Short name T407
Test name
Test status
Simulation time 52568974 ps
CPU time 1.63 seconds
Started Jul 13 06:41:51 PM PDT 24
Finished Jul 13 06:41:54 PM PDT 24
Peak memory 217708 kb
Host smart-a78b27db-a005-451a-b7a7-2e73d11ea6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481486260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1481486260
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.2684830334
Short name T812
Test name
Test status
Simulation time 29268215 ps
CPU time 1.29 seconds
Started Jul 13 06:39:38 PM PDT 24
Finished Jul 13 06:39:40 PM PDT 24
Peak memory 220032 kb
Host smart-ad6afe4b-4e86-4f68-9931-d91dca0a7d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684830334 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.2684830334
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.3610031766
Short name T559
Test name
Test status
Simulation time 40546395 ps
CPU time 0.85 seconds
Started Jul 13 06:39:48 PM PDT 24
Finished Jul 13 06:39:51 PM PDT 24
Peak memory 206956 kb
Host smart-4ece1bb6-4ce4-4263-8098-8c7448e8a040
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610031766 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.3610031766
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.951706786
Short name T180
Test name
Test status
Simulation time 13103397 ps
CPU time 0.88 seconds
Started Jul 13 06:39:46 PM PDT 24
Finished Jul 13 06:39:47 PM PDT 24
Peak memory 216740 kb
Host smart-fa62d64c-e486-448d-80f0-82054c3b7ff6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951706786 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.951706786
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.2843194970
Short name T436
Test name
Test status
Simulation time 48286844 ps
CPU time 1.44 seconds
Started Jul 13 06:39:48 PM PDT 24
Finished Jul 13 06:39:52 PM PDT 24
Peak memory 217296 kb
Host smart-efcaba4a-797d-4433-b03a-5efa3da0a742
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843194970 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.2843194970
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.2818013881
Short name T852
Test name
Test status
Simulation time 23614093 ps
CPU time 0.97 seconds
Started Jul 13 06:39:37 PM PDT 24
Finished Jul 13 06:39:38 PM PDT 24
Peak memory 218748 kb
Host smart-7a4eea7a-5fac-49f7-a99d-5487d3d40839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818013881 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.2818013881
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.1445285125
Short name T635
Test name
Test status
Simulation time 64049085 ps
CPU time 1.28 seconds
Started Jul 13 06:39:40 PM PDT 24
Finished Jul 13 06:39:42 PM PDT 24
Peak memory 218696 kb
Host smart-6585d628-ee25-4c1a-ac56-bd7ebdcffd1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445285125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.1445285125
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.3861423869
Short name T33
Test name
Test status
Simulation time 57147209 ps
CPU time 0.84 seconds
Started Jul 13 06:39:37 PM PDT 24
Finished Jul 13 06:39:39 PM PDT 24
Peak memory 215792 kb
Host smart-f2a8ad30-0167-41c7-a9d7-79506df289df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861423869 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3861423869
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.3783204325
Short name T711
Test name
Test status
Simulation time 18574564 ps
CPU time 1.04 seconds
Started Jul 13 06:39:40 PM PDT 24
Finished Jul 13 06:39:42 PM PDT 24
Peak memory 215460 kb
Host smart-11d39a39-33cd-45da-9c08-02a247b439fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783204325 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3783204325
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.1589454568
Short name T377
Test name
Test status
Simulation time 208500350 ps
CPU time 2.59 seconds
Started Jul 13 06:39:40 PM PDT 24
Finished Jul 13 06:39:44 PM PDT 24
Peak memory 219948 kb
Host smart-bf8e89e8-72ec-43e6-a58a-2d3cb8ad02a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589454568 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.1589454568
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2842765510
Short name T416
Test name
Test status
Simulation time 330647865253 ps
CPU time 904.46 seconds
Started Jul 13 06:39:37 PM PDT 24
Finished Jul 13 06:54:42 PM PDT 24
Peak memory 222148 kb
Host smart-164ea91b-12af-4f16-ae4d-e27b7f3cb142
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842765510 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2842765510
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.2031616879
Short name T364
Test name
Test status
Simulation time 56671737 ps
CPU time 1.11 seconds
Started Jul 13 06:41:53 PM PDT 24
Finished Jul 13 06:41:56 PM PDT 24
Peak memory 220232 kb
Host smart-fc501845-5dfb-485a-bbf5-421a045833c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031616879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2031616879
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.3902110033
Short name T696
Test name
Test status
Simulation time 72185881 ps
CPU time 1.54 seconds
Started Jul 13 06:41:51 PM PDT 24
Finished Jul 13 06:41:53 PM PDT 24
Peak memory 218928 kb
Host smart-44116e66-1b6c-4f14-8026-33a5ecf5f9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902110033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3902110033
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.2400366319
Short name T48
Test name
Test status
Simulation time 138729349 ps
CPU time 1.3 seconds
Started Jul 13 06:41:53 PM PDT 24
Finished Jul 13 06:41:55 PM PDT 24
Peak memory 219032 kb
Host smart-2117b6ab-b65c-40a9-a7fc-5c70ccef8c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400366319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.2400366319
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.2719838577
Short name T847
Test name
Test status
Simulation time 44319185 ps
CPU time 1.43 seconds
Started Jul 13 06:41:52 PM PDT 24
Finished Jul 13 06:41:54 PM PDT 24
Peak memory 218840 kb
Host smart-086fcdba-8941-42c4-8f5f-e7149eb6a8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719838577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.2719838577
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.3546588995
Short name T645
Test name
Test status
Simulation time 38043137 ps
CPU time 1.11 seconds
Started Jul 13 06:41:53 PM PDT 24
Finished Jul 13 06:41:55 PM PDT 24
Peak memory 217712 kb
Host smart-388e617f-d70d-4183-b29e-24849088b2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546588995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.3546588995
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.1322984350
Short name T333
Test name
Test status
Simulation time 35357832 ps
CPU time 1.49 seconds
Started Jul 13 06:41:51 PM PDT 24
Finished Jul 13 06:41:54 PM PDT 24
Peak memory 218836 kb
Host smart-4957d333-6564-44b6-a31e-48442cac69e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322984350 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.1322984350
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.2463361184
Short name T348
Test name
Test status
Simulation time 27736448 ps
CPU time 1.1 seconds
Started Jul 13 06:41:51 PM PDT 24
Finished Jul 13 06:41:52 PM PDT 24
Peak memory 217800 kb
Host smart-5c2d92c7-7900-4bf5-8769-6aa4dc2cfb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463361184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.2463361184
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.3540269697
Short name T49
Test name
Test status
Simulation time 65068984 ps
CPU time 1.31 seconds
Started Jul 13 06:41:54 PM PDT 24
Finished Jul 13 06:41:57 PM PDT 24
Peak memory 217508 kb
Host smart-0b1bd131-16d3-4ada-9131-525bfb999f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540269697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.3540269697
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.2012437338
Short name T354
Test name
Test status
Simulation time 40193193 ps
CPU time 1.2 seconds
Started Jul 13 06:41:51 PM PDT 24
Finished Jul 13 06:41:54 PM PDT 24
Peak memory 220220 kb
Host smart-8063d3b6-7c5c-470d-a3a9-ef6fd754b4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012437338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2012437338
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.1758823104
Short name T919
Test name
Test status
Simulation time 37243675 ps
CPU time 1.16 seconds
Started Jul 13 06:39:48 PM PDT 24
Finished Jul 13 06:39:51 PM PDT 24
Peak memory 220096 kb
Host smart-99cc4056-ca81-4522-b99d-31e96ce14c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758823104 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.1758823104
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.3719284110
Short name T551
Test name
Test status
Simulation time 20500156 ps
CPU time 0.93 seconds
Started Jul 13 06:39:48 PM PDT 24
Finished Jul 13 06:39:51 PM PDT 24
Peak memory 215244 kb
Host smart-17645174-43bc-4e82-acda-f5db2deb9df1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719284110 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.3719284110
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.1737345627
Short name T220
Test name
Test status
Simulation time 22423499 ps
CPU time 0.89 seconds
Started Jul 13 06:39:51 PM PDT 24
Finished Jul 13 06:39:53 PM PDT 24
Peak memory 216584 kb
Host smart-2d1ec78d-078a-4d9e-80e0-4245577901b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737345627 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1737345627
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.3664053573
Short name T138
Test name
Test status
Simulation time 43389093 ps
CPU time 1.4 seconds
Started Jul 13 06:39:51 PM PDT 24
Finished Jul 13 06:39:54 PM PDT 24
Peak memory 219396 kb
Host smart-9b68d161-3310-49c7-95d5-6b002a8efff6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664053573 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.3664053573
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.665095999
Short name T978
Test name
Test status
Simulation time 24069717 ps
CPU time 1.25 seconds
Started Jul 13 06:39:46 PM PDT 24
Finished Jul 13 06:39:47 PM PDT 24
Peak memory 220236 kb
Host smart-68d3fc5e-f3ae-409b-a354-1f6d47fd990c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665095999 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.665095999
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.1300721993
Short name T535
Test name
Test status
Simulation time 81416184 ps
CPU time 1.31 seconds
Started Jul 13 06:39:46 PM PDT 24
Finished Jul 13 06:39:48 PM PDT 24
Peak memory 220376 kb
Host smart-787ef25c-91f9-40ba-a657-c2815dfe0710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300721993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1300721993
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.4271756647
Short name T607
Test name
Test status
Simulation time 23604263 ps
CPU time 1.07 seconds
Started Jul 13 06:39:48 PM PDT 24
Finished Jul 13 06:39:51 PM PDT 24
Peak memory 224308 kb
Host smart-82ffadab-f75e-47e9-851d-88ad8b630da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271756647 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.4271756647
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.3522511776
Short name T351
Test name
Test status
Simulation time 16518471 ps
CPU time 0.98 seconds
Started Jul 13 06:39:47 PM PDT 24
Finished Jul 13 06:39:49 PM PDT 24
Peak memory 215596 kb
Host smart-79d65b54-d5fe-4f9c-ae79-c737f0e7fe42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522511776 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.3522511776
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.3557125878
Short name T832
Test name
Test status
Simulation time 101916478 ps
CPU time 1.62 seconds
Started Jul 13 06:39:50 PM PDT 24
Finished Jul 13 06:39:54 PM PDT 24
Peak memory 218632 kb
Host smart-d144abc4-de39-400a-bc86-bdf7ce9c56b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557125878 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.3557125878
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1298115381
Short name T970
Test name
Test status
Simulation time 87961971247 ps
CPU time 939.68 seconds
Started Jul 13 06:39:49 PM PDT 24
Finished Jul 13 06:55:31 PM PDT 24
Peak memory 223952 kb
Host smart-53ad6053-f1f6-4d97-9c5b-e0efa6314c23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298115381 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1298115381
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.988873541
Short name T819
Test name
Test status
Simulation time 37204224 ps
CPU time 1.45 seconds
Started Jul 13 06:41:54 PM PDT 24
Finished Jul 13 06:41:57 PM PDT 24
Peak memory 217556 kb
Host smart-08ce8d76-2981-4805-867f-9f8fc7fedf99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988873541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.988873541
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.2804818796
Short name T260
Test name
Test status
Simulation time 55886624 ps
CPU time 1.37 seconds
Started Jul 13 06:41:52 PM PDT 24
Finished Jul 13 06:41:54 PM PDT 24
Peak memory 220356 kb
Host smart-5b164b0a-0be9-4468-82e8-d16e5ed391f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804818796 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.2804818796
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.3797175706
Short name T347
Test name
Test status
Simulation time 45761116 ps
CPU time 1.28 seconds
Started Jul 13 06:41:57 PM PDT 24
Finished Jul 13 06:41:59 PM PDT 24
Peak memory 220204 kb
Host smart-12448c75-700f-426b-992d-f8bebe576e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797175706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.3797175706
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.2306223308
Short name T776
Test name
Test status
Simulation time 97206012 ps
CPU time 1.32 seconds
Started Jul 13 06:41:52 PM PDT 24
Finished Jul 13 06:41:54 PM PDT 24
Peak memory 217724 kb
Host smart-f94dc188-a5c2-4698-9adb-9fa0986d12f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306223308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.2306223308
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.2335151224
Short name T915
Test name
Test status
Simulation time 81334094 ps
CPU time 3 seconds
Started Jul 13 06:41:51 PM PDT 24
Finished Jul 13 06:41:55 PM PDT 24
Peak memory 220648 kb
Host smart-aaa49598-32e0-476a-8dbc-4d7d33ffa0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335151224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.2335151224
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.536649444
Short name T606
Test name
Test status
Simulation time 48294618 ps
CPU time 1.83 seconds
Started Jul 13 06:41:52 PM PDT 24
Finished Jul 13 06:41:55 PM PDT 24
Peak memory 217704 kb
Host smart-191c0328-a444-490f-a507-55bc0d79dab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536649444 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.536649444
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.45491631
Short name T522
Test name
Test status
Simulation time 53883291 ps
CPU time 2 seconds
Started Jul 13 06:41:54 PM PDT 24
Finished Jul 13 06:41:58 PM PDT 24
Peak memory 218812 kb
Host smart-984d69b4-23e6-4889-aafa-792fa5083487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45491631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.45491631
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.23688532
Short name T961
Test name
Test status
Simulation time 80535919 ps
CPU time 2.32 seconds
Started Jul 13 06:41:55 PM PDT 24
Finished Jul 13 06:41:58 PM PDT 24
Peak memory 219180 kb
Host smart-23280040-7bc5-4ddf-acb2-d11e930051ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23688532 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.23688532
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.2918668536
Short name T766
Test name
Test status
Simulation time 614620860 ps
CPU time 3.13 seconds
Started Jul 13 06:41:54 PM PDT 24
Finished Jul 13 06:41:59 PM PDT 24
Peak memory 219928 kb
Host smart-01250fb4-980b-4b29-8c28-87e00b81c0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918668536 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.2918668536
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.3370837255
Short name T598
Test name
Test status
Simulation time 38009454 ps
CPU time 1.92 seconds
Started Jul 13 06:41:53 PM PDT 24
Finished Jul 13 06:41:56 PM PDT 24
Peak memory 218788 kb
Host smart-cd15cdef-c5bc-4cb4-a8c0-8b23dff5194a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370837255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.3370837255
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.1560326994
Short name T170
Test name
Test status
Simulation time 88311047 ps
CPU time 1.22 seconds
Started Jul 13 06:39:50 PM PDT 24
Finished Jul 13 06:39:53 PM PDT 24
Peak memory 220900 kb
Host smart-7036e536-c592-4974-8147-b16b0be075c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560326994 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.1560326994
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.4027442774
Short name T723
Test name
Test status
Simulation time 42728444 ps
CPU time 0.91 seconds
Started Jul 13 06:39:50 PM PDT 24
Finished Jul 13 06:39:53 PM PDT 24
Peak memory 215484 kb
Host smart-eff31240-7446-492a-b8f9-696a32896ea2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027442774 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.4027442774
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.4225577677
Short name T406
Test name
Test status
Simulation time 35286668 ps
CPU time 1.36 seconds
Started Jul 13 06:39:49 PM PDT 24
Finished Jul 13 06:39:52 PM PDT 24
Peak memory 217288 kb
Host smart-5242dc7c-9faa-4e32-a2e0-644f34430a12
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225577677 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.4225577677
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.1801571467
Short name T105
Test name
Test status
Simulation time 20023216 ps
CPU time 1.04 seconds
Started Jul 13 06:39:49 PM PDT 24
Finished Jul 13 06:39:52 PM PDT 24
Peak memory 218676 kb
Host smart-d1541a97-421d-490e-9d56-ceaeb25fd9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801571467 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.1801571467
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.3146460079
Short name T779
Test name
Test status
Simulation time 67152282 ps
CPU time 1.27 seconds
Started Jul 13 06:39:49 PM PDT 24
Finished Jul 13 06:39:52 PM PDT 24
Peak memory 218648 kb
Host smart-fa31170d-4541-45df-9a98-6be9d549706a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146460079 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3146460079
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.2551947003
Short name T811
Test name
Test status
Simulation time 22731776 ps
CPU time 1.26 seconds
Started Jul 13 06:39:49 PM PDT 24
Finished Jul 13 06:39:52 PM PDT 24
Peak memory 224232 kb
Host smart-595769c7-9579-421a-ab55-c512a44b77c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551947003 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2551947003
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.1889583313
Short name T431
Test name
Test status
Simulation time 43793206 ps
CPU time 0.89 seconds
Started Jul 13 06:39:47 PM PDT 24
Finished Jul 13 06:39:49 PM PDT 24
Peak memory 215612 kb
Host smart-3ad45eb3-f878-4feb-9185-9cc59adb10d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889583313 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.1889583313
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2404654283
Short name T500
Test name
Test status
Simulation time 248064100 ps
CPU time 1.91 seconds
Started Jul 13 06:39:50 PM PDT 24
Finished Jul 13 06:39:54 PM PDT 24
Peak memory 215632 kb
Host smart-29e9f232-65f7-4942-b75f-359119132715
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404654283 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2404654283
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.3441689334
Short name T761
Test name
Test status
Simulation time 86064243868 ps
CPU time 437.35 seconds
Started Jul 13 06:39:49 PM PDT 24
Finished Jul 13 06:47:08 PM PDT 24
Peak memory 219640 kb
Host smart-712f4b77-015e-4f68-98f1-5b4486e230f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441689334 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.3441689334
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.3275437236
Short name T334
Test name
Test status
Simulation time 44520175 ps
CPU time 1.59 seconds
Started Jul 13 06:41:51 PM PDT 24
Finished Jul 13 06:41:53 PM PDT 24
Peak memory 217788 kb
Host smart-f68c339f-1546-4f7a-9774-786c6406832a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275437236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3275437236
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.1652145485
Short name T972
Test name
Test status
Simulation time 92035704 ps
CPU time 1.47 seconds
Started Jul 13 06:41:53 PM PDT 24
Finished Jul 13 06:41:55 PM PDT 24
Peak memory 219364 kb
Host smart-4fe0fff3-9a5d-4128-b159-c3572311c6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652145485 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.1652145485
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.1023716617
Short name T326
Test name
Test status
Simulation time 39477643 ps
CPU time 1.48 seconds
Started Jul 13 06:41:54 PM PDT 24
Finished Jul 13 06:41:57 PM PDT 24
Peak memory 220120 kb
Host smart-d21cdb97-a8ed-406c-9547-227807e00686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023716617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.1023716617
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.2365957874
Short name T753
Test name
Test status
Simulation time 242938247 ps
CPU time 3.13 seconds
Started Jul 13 06:41:52 PM PDT 24
Finished Jul 13 06:41:56 PM PDT 24
Peak memory 220260 kb
Host smart-6d6f8545-8533-421e-a0d1-a2318f26ab79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365957874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.2365957874
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.824275814
Short name T437
Test name
Test status
Simulation time 77133675 ps
CPU time 1.36 seconds
Started Jul 13 06:41:54 PM PDT 24
Finished Jul 13 06:41:57 PM PDT 24
Peak memory 219216 kb
Host smart-8fa57cc4-681d-436e-bc8d-b24204ca8bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824275814 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.824275814
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.2201174366
Short name T53
Test name
Test status
Simulation time 121225758 ps
CPU time 1.37 seconds
Started Jul 13 06:41:53 PM PDT 24
Finished Jul 13 06:41:55 PM PDT 24
Peak memory 217784 kb
Host smart-e4715ce4-b7d7-4efb-86f6-9080d4d0ef72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201174366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2201174366
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.2261118118
Short name T327
Test name
Test status
Simulation time 71888237 ps
CPU time 1.09 seconds
Started Jul 13 06:41:52 PM PDT 24
Finished Jul 13 06:41:54 PM PDT 24
Peak memory 220120 kb
Host smart-bff8e501-d19b-430f-bbc9-4af86ed73c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261118118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.2261118118
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.1285230222
Short name T665
Test name
Test status
Simulation time 26167549 ps
CPU time 1.23 seconds
Started Jul 13 06:41:51 PM PDT 24
Finished Jul 13 06:41:53 PM PDT 24
Peak memory 217804 kb
Host smart-eee58265-c808-485b-9d7a-37663d3f5963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285230222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1285230222
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.1942102133
Short name T70
Test name
Test status
Simulation time 123112976 ps
CPU time 2.84 seconds
Started Jul 13 06:41:54 PM PDT 24
Finished Jul 13 06:41:58 PM PDT 24
Peak memory 220540 kb
Host smart-eeeb9264-5f68-4e55-a78c-4e028ce3c472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942102133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1942102133
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.3444475310
Short name T800
Test name
Test status
Simulation time 55815514 ps
CPU time 1.3 seconds
Started Jul 13 06:42:04 PM PDT 24
Finished Jul 13 06:42:06 PM PDT 24
Peak memory 217464 kb
Host smart-ba8d2bea-5277-4f1f-9706-05e4741d7ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444475310 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.3444475310
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.1850228060
Short name T659
Test name
Test status
Simulation time 55879078 ps
CPU time 1.33 seconds
Started Jul 13 06:39:49 PM PDT 24
Finished Jul 13 06:39:53 PM PDT 24
Peak memory 215964 kb
Host smart-7f8a2bfa-c5ae-480c-a176-0fe678589100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850228060 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.1850228060
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.2763977976
Short name T365
Test name
Test status
Simulation time 52774328 ps
CPU time 0.91 seconds
Started Jul 13 06:39:51 PM PDT 24
Finished Jul 13 06:39:53 PM PDT 24
Peak memory 207016 kb
Host smart-a6d8c7b0-9b82-4067-88af-7486865cae29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763977976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2763977976
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.3975084355
Short name T166
Test name
Test status
Simulation time 10541985 ps
CPU time 0.87 seconds
Started Jul 13 06:39:45 PM PDT 24
Finished Jul 13 06:39:46 PM PDT 24
Peak memory 215716 kb
Host smart-5f90a49d-6fd5-405b-9846-10677a741680
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975084355 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.3975084355
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.2702091014
Short name T694
Test name
Test status
Simulation time 20274292 ps
CPU time 0.98 seconds
Started Jul 13 06:39:48 PM PDT 24
Finished Jul 13 06:39:51 PM PDT 24
Peak memory 218608 kb
Host smart-fdfb156b-b99b-4083-a8d2-39048ebabf6f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702091014 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.2702091014
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.3477216994
Short name T642
Test name
Test status
Simulation time 27745213 ps
CPU time 1.13 seconds
Started Jul 13 06:39:49 PM PDT 24
Finished Jul 13 06:39:52 PM PDT 24
Peak memory 220004 kb
Host smart-3c95adcf-54e3-4f02-bcd5-7e5c8c435691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477216994 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.3477216994
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.1726517601
Short name T553
Test name
Test status
Simulation time 75099771 ps
CPU time 1.44 seconds
Started Jul 13 06:39:47 PM PDT 24
Finished Jul 13 06:39:49 PM PDT 24
Peak memory 219180 kb
Host smart-626eebec-f019-4b7d-ba6b-e6a272d674fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726517601 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.1726517601
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.4110297549
Short name T897
Test name
Test status
Simulation time 19945806 ps
CPU time 1.08 seconds
Started Jul 13 06:39:50 PM PDT 24
Finished Jul 13 06:39:53 PM PDT 24
Peak memory 216020 kb
Host smart-612b4350-e7d5-4be8-8994-141ef6d290a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110297549 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.4110297549
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.320891546
Short name T835
Test name
Test status
Simulation time 35330663 ps
CPU time 0.93 seconds
Started Jul 13 06:39:49 PM PDT 24
Finished Jul 13 06:39:52 PM PDT 24
Peak memory 215612 kb
Host smart-519d3784-e978-4de4-a11e-ad04a4fc73c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320891546 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.320891546
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.628425689
Short name T366
Test name
Test status
Simulation time 257181766 ps
CPU time 5.19 seconds
Started Jul 13 06:39:48 PM PDT 24
Finished Jul 13 06:39:55 PM PDT 24
Peak memory 218804 kb
Host smart-2aa79bca-cb32-4fa1-ad85-6a875525c365
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628425689 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.628425689
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.144163472
Short name T233
Test name
Test status
Simulation time 39935718065 ps
CPU time 445.51 seconds
Started Jul 13 06:39:47 PM PDT 24
Finished Jul 13 06:47:13 PM PDT 24
Peak memory 221928 kb
Host smart-f72c03cb-aee2-4ac0-bc22-db61a4b176ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144163472 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.144163472
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.2212567542
Short name T47
Test name
Test status
Simulation time 37864603 ps
CPU time 1.17 seconds
Started Jul 13 06:42:04 PM PDT 24
Finished Jul 13 06:42:07 PM PDT 24
Peak memory 217608 kb
Host smart-c0f4083a-5bc3-4717-8b0e-6f090aba3426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212567542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.2212567542
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.4088217626
Short name T509
Test name
Test status
Simulation time 108096242 ps
CPU time 1.78 seconds
Started Jul 13 06:42:03 PM PDT 24
Finished Jul 13 06:42:05 PM PDT 24
Peak memory 219344 kb
Host smart-96f9b5db-cabb-4436-abf3-867e741994c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088217626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.4088217626
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.1360198871
Short name T430
Test name
Test status
Simulation time 115992715 ps
CPU time 2.55 seconds
Started Jul 13 06:42:03 PM PDT 24
Finished Jul 13 06:42:06 PM PDT 24
Peak memory 219208 kb
Host smart-408896e7-4f9e-479c-a32f-4de0bd24af4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360198871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.1360198871
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.1986399936
Short name T770
Test name
Test status
Simulation time 76435278 ps
CPU time 1.36 seconds
Started Jul 13 06:42:03 PM PDT 24
Finished Jul 13 06:42:05 PM PDT 24
Peak memory 218864 kb
Host smart-55c37385-10d2-4a8c-807f-ab1bca89e627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986399936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.1986399936
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.4277390057
Short name T623
Test name
Test status
Simulation time 38182387 ps
CPU time 1.61 seconds
Started Jul 13 06:42:08 PM PDT 24
Finished Jul 13 06:42:11 PM PDT 24
Peak memory 219056 kb
Host smart-aad74884-20b4-475a-a81a-fdeb8d374b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277390057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.4277390057
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.2047840820
Short name T336
Test name
Test status
Simulation time 150816517 ps
CPU time 1.53 seconds
Started Jul 13 06:42:06 PM PDT 24
Finished Jul 13 06:42:10 PM PDT 24
Peak memory 219256 kb
Host smart-17926318-9524-46ef-890a-551c0f6fbe2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047840820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2047840820
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.2023365672
Short name T908
Test name
Test status
Simulation time 49191613 ps
CPU time 1.26 seconds
Started Jul 13 06:42:05 PM PDT 24
Finished Jul 13 06:42:08 PM PDT 24
Peak memory 217600 kb
Host smart-1b37c250-efbf-47d6-869f-e266195ef55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023365672 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2023365672
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1195144269
Short name T400
Test name
Test status
Simulation time 96105210 ps
CPU time 3.18 seconds
Started Jul 13 06:42:03 PM PDT 24
Finished Jul 13 06:42:07 PM PDT 24
Peak memory 218960 kb
Host smart-3f1b9a3e-6a36-499b-9eb9-bc3640a2c858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195144269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1195144269
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.1957404289
Short name T259
Test name
Test status
Simulation time 20328609 ps
CPU time 1.15 seconds
Started Jul 13 06:42:07 PM PDT 24
Finished Jul 13 06:42:10 PM PDT 24
Peak memory 217700 kb
Host smart-83c7fdb6-968d-4c47-bf39-10afecf9ef41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957404289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.1957404289
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.3651891571
Short name T43
Test name
Test status
Simulation time 39425104 ps
CPU time 1.17 seconds
Started Jul 13 06:39:50 PM PDT 24
Finished Jul 13 06:39:53 PM PDT 24
Peak memory 219448 kb
Host smart-1f209fd1-432b-43ca-a007-4b2a9420bcef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651891571 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.3651891571
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1423783311
Short name T492
Test name
Test status
Simulation time 32160005 ps
CPU time 0.92 seconds
Started Jul 13 06:39:48 PM PDT 24
Finished Jul 13 06:39:51 PM PDT 24
Peak memory 206968 kb
Host smart-f3cf8c08-e7d6-4bcd-a449-b63794948cca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423783311 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1423783311
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.2155114326
Short name T928
Test name
Test status
Simulation time 37136759 ps
CPU time 0.85 seconds
Started Jul 13 06:39:48 PM PDT 24
Finished Jul 13 06:39:51 PM PDT 24
Peak memory 216576 kb
Host smart-a47954c2-301b-419c-a103-1fef33d16bb7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155114326 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.2155114326
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.1588125194
Short name T90
Test name
Test status
Simulation time 93492216 ps
CPU time 1.13 seconds
Started Jul 13 06:39:47 PM PDT 24
Finished Jul 13 06:39:49 PM PDT 24
Peak memory 217060 kb
Host smart-683fa447-35f1-496b-bff6-e9c64557df31
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588125194 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.1588125194
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.1413751414
Short name T726
Test name
Test status
Simulation time 40176479 ps
CPU time 0.81 seconds
Started Jul 13 06:39:47 PM PDT 24
Finished Jul 13 06:39:48 PM PDT 24
Peak memory 218636 kb
Host smart-9aec152d-d50c-4c4a-bb87-c55b21706c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413751414 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.1413751414
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.2245967961
Short name T746
Test name
Test status
Simulation time 115198959 ps
CPU time 1.21 seconds
Started Jul 13 06:39:50 PM PDT 24
Finished Jul 13 06:39:53 PM PDT 24
Peak memory 217484 kb
Host smart-b6c6556f-a405-43dc-bca4-551c995dfca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245967961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.2245967961
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.4112448029
Short name T605
Test name
Test status
Simulation time 42973733 ps
CPU time 0.92 seconds
Started Jul 13 06:39:48 PM PDT 24
Finished Jul 13 06:39:51 PM PDT 24
Peak memory 215744 kb
Host smart-da081559-74b3-482b-b34f-f90d00c0e6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112448029 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.4112448029
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.4186726640
Short name T704
Test name
Test status
Simulation time 45099318 ps
CPU time 0.98 seconds
Started Jul 13 06:39:49 PM PDT 24
Finished Jul 13 06:39:52 PM PDT 24
Peak memory 207352 kb
Host smart-74ff1b3c-e9ca-4279-a819-bef11e4c68e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186726640 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.4186726640
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.2503229330
Short name T247
Test name
Test status
Simulation time 137548340 ps
CPU time 1.34 seconds
Started Jul 13 06:39:46 PM PDT 24
Finished Jul 13 06:39:48 PM PDT 24
Peak memory 217524 kb
Host smart-6b590777-97ae-4286-849b-b2c1c855b681
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503229330 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2503229330
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.1514069955
Short name T866
Test name
Test status
Simulation time 362780993972 ps
CPU time 550.32 seconds
Started Jul 13 06:39:48 PM PDT 24
Finished Jul 13 06:49:00 PM PDT 24
Peak memory 219536 kb
Host smart-9db22070-953b-403e-86d4-75a8906eacbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514069955 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.1514069955
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.3261575986
Short name T829
Test name
Test status
Simulation time 33729744 ps
CPU time 1.17 seconds
Started Jul 13 06:42:04 PM PDT 24
Finished Jul 13 06:42:07 PM PDT 24
Peak memory 220148 kb
Host smart-9f558562-6782-4c9f-b5d1-a08c59575971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261575986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.3261575986
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.811592041
Short name T413
Test name
Test status
Simulation time 51882448 ps
CPU time 1.33 seconds
Started Jul 13 06:42:04 PM PDT 24
Finished Jul 13 06:42:07 PM PDT 24
Peak memory 217728 kb
Host smart-7a58a4db-c9b2-4875-b9e4-0bc127dc4e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811592041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.811592041
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1076450424
Short name T657
Test name
Test status
Simulation time 94457531 ps
CPU time 0.97 seconds
Started Jul 13 06:42:04 PM PDT 24
Finished Jul 13 06:42:05 PM PDT 24
Peak memory 217592 kb
Host smart-aa62a598-f416-4600-b63f-8cbdc9c00368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076450424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1076450424
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.859975716
Short name T322
Test name
Test status
Simulation time 61362537 ps
CPU time 1.49 seconds
Started Jul 13 06:42:07 PM PDT 24
Finished Jul 13 06:42:10 PM PDT 24
Peak memory 218848 kb
Host smart-704c12f9-5a1b-483f-9177-9aa6825c035f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859975716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.859975716
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.4011758434
Short name T328
Test name
Test status
Simulation time 48233766 ps
CPU time 1.25 seconds
Started Jul 13 06:42:05 PM PDT 24
Finished Jul 13 06:42:09 PM PDT 24
Peak memory 218792 kb
Host smart-6b24886e-da27-484f-b75d-f31db2854e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011758434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.4011758434
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2208066197
Short name T993
Test name
Test status
Simulation time 57061529 ps
CPU time 1.16 seconds
Started Jul 13 06:42:06 PM PDT 24
Finished Jul 13 06:42:09 PM PDT 24
Peak memory 217652 kb
Host smart-b5065a49-6de6-4c25-a4e6-76eac529a6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208066197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2208066197
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3142728540
Short name T681
Test name
Test status
Simulation time 65819347 ps
CPU time 2.19 seconds
Started Jul 13 06:42:05 PM PDT 24
Finished Jul 13 06:42:09 PM PDT 24
Peak memory 219984 kb
Host smart-09f21cad-e47d-4688-8528-522e8c67ada0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142728540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3142728540
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.2946619359
Short name T51
Test name
Test status
Simulation time 88474847 ps
CPU time 1.44 seconds
Started Jul 13 06:42:05 PM PDT 24
Finished Jul 13 06:42:09 PM PDT 24
Peak memory 219244 kb
Host smart-5343f6db-d12f-4ed7-a008-3d724cce52bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946619359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2946619359
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.1332842739
Short name T825
Test name
Test status
Simulation time 153716111 ps
CPU time 1.55 seconds
Started Jul 13 06:42:01 PM PDT 24
Finished Jul 13 06:42:03 PM PDT 24
Peak memory 219452 kb
Host smart-24d7f50f-8411-4639-852c-2c16e9aa4f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332842739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.1332842739
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.276855464
Short name T880
Test name
Test status
Simulation time 193800343 ps
CPU time 2.25 seconds
Started Jul 13 06:42:06 PM PDT 24
Finished Jul 13 06:42:10 PM PDT 24
Peak memory 220596 kb
Host smart-e842b046-5a1f-4f02-b363-e00083ec3b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276855464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.276855464
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert_test.1412933332
Short name T990
Test name
Test status
Simulation time 57020977 ps
CPU time 0.95 seconds
Started Jul 13 06:39:55 PM PDT 24
Finished Jul 13 06:39:57 PM PDT 24
Peak memory 215192 kb
Host smart-799fcdcd-ce5b-4442-b5d7-64ac9f973ce5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412933332 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.1412933332
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.1330470955
Short name T698
Test name
Test status
Simulation time 13222421 ps
CPU time 0.92 seconds
Started Jul 13 06:39:59 PM PDT 24
Finished Jul 13 06:40:02 PM PDT 24
Peak memory 216300 kb
Host smart-33df01bc-8533-4b79-bab9-efab740ee4b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330470955 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1330470955
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.1286883901
Short name T263
Test name
Test status
Simulation time 259203953 ps
CPU time 1.29 seconds
Started Jul 13 06:39:59 PM PDT 24
Finished Jul 13 06:40:03 PM PDT 24
Peak memory 218668 kb
Host smart-dd7dc384-7686-4a84-bdba-df7ed47320b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286883901 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.1286883901
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.1141682051
Short name T472
Test name
Test status
Simulation time 21692893 ps
CPU time 1.08 seconds
Started Jul 13 06:39:58 PM PDT 24
Finished Jul 13 06:40:00 PM PDT 24
Peak memory 224144 kb
Host smart-7eca3fda-9c30-4c49-83c2-6ceb11e74d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141682051 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.1141682051
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.703342756
Short name T785
Test name
Test status
Simulation time 41971015 ps
CPU time 1.37 seconds
Started Jul 13 06:39:49 PM PDT 24
Finished Jul 13 06:39:52 PM PDT 24
Peak memory 217696 kb
Host smart-bcb26c23-79b1-4a0a-9bda-1a78095811ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703342756 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.703342756
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.3881329758
Short name T34
Test name
Test status
Simulation time 46452616 ps
CPU time 0.82 seconds
Started Jul 13 06:39:55 PM PDT 24
Finished Jul 13 06:39:56 PM PDT 24
Peak memory 215888 kb
Host smart-54746301-522b-4ed9-83ac-02780d4c21f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881329758 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.3881329758
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.3118774224
Short name T236
Test name
Test status
Simulation time 16775713 ps
CPU time 1.03 seconds
Started Jul 13 06:39:49 PM PDT 24
Finished Jul 13 06:39:52 PM PDT 24
Peak memory 215624 kb
Host smart-78f80883-0e20-408b-9961-cb329787694c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118774224 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.3118774224
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.3753848911
Short name T108
Test name
Test status
Simulation time 279841056 ps
CPU time 1.7 seconds
Started Jul 13 06:39:59 PM PDT 24
Finished Jul 13 06:40:01 PM PDT 24
Peak memory 215500 kb
Host smart-688e7f5d-b436-4126-8288-b17386d34abb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753848911 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.3753848911
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.1583447320
Short name T656
Test name
Test status
Simulation time 258392291134 ps
CPU time 3086.12 seconds
Started Jul 13 06:40:01 PM PDT 24
Finished Jul 13 07:31:30 PM PDT 24
Peak memory 230416 kb
Host smart-c2d9afec-862d-45c5-8288-12d9ba978c19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583447320 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.1583447320
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.4174683999
Short name T319
Test name
Test status
Simulation time 28528628 ps
CPU time 1.2 seconds
Started Jul 13 06:42:03 PM PDT 24
Finished Jul 13 06:42:05 PM PDT 24
Peak memory 217664 kb
Host smart-fb7066ce-982c-4a71-8708-75a0b46bb9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174683999 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.4174683999
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.3184618720
Short name T321
Test name
Test status
Simulation time 47739068 ps
CPU time 1.91 seconds
Started Jul 13 06:42:01 PM PDT 24
Finished Jul 13 06:42:03 PM PDT 24
Peak memory 220504 kb
Host smart-45e97ff1-465a-49e1-8a33-cacba5095d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184618720 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.3184618720
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.2594699088
Short name T692
Test name
Test status
Simulation time 74731866 ps
CPU time 1.19 seconds
Started Jul 13 06:42:04 PM PDT 24
Finished Jul 13 06:42:06 PM PDT 24
Peak memory 215708 kb
Host smart-c43e9213-4d59-4d13-aad4-dd5ceaf8fc7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594699088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.2594699088
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.3435693963
Short name T571
Test name
Test status
Simulation time 100502496 ps
CPU time 2.48 seconds
Started Jul 13 06:42:04 PM PDT 24
Finished Jul 13 06:42:07 PM PDT 24
Peak memory 220288 kb
Host smart-0d684379-0685-4b12-989b-b03ea75ca008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435693963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3435693963
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.2465961220
Short name T387
Test name
Test status
Simulation time 57247876 ps
CPU time 2.12 seconds
Started Jul 13 06:42:03 PM PDT 24
Finished Jul 13 06:42:06 PM PDT 24
Peak memory 219040 kb
Host smart-2246d502-f6a1-47f6-b9d0-1e4fa5d086f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465961220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.2465961220
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.1365711655
Short name T730
Test name
Test status
Simulation time 38926051 ps
CPU time 1.69 seconds
Started Jul 13 06:42:02 PM PDT 24
Finished Jul 13 06:42:04 PM PDT 24
Peak memory 219168 kb
Host smart-0df85640-8098-40b6-9b4e-4d5a1e826e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365711655 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.1365711655
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.2127988487
Short name T408
Test name
Test status
Simulation time 94330346 ps
CPU time 1.37 seconds
Started Jul 13 06:42:03 PM PDT 24
Finished Jul 13 06:42:05 PM PDT 24
Peak memory 217608 kb
Host smart-0738e4f4-38b4-4abb-af2c-f94e95d303f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127988487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.2127988487
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.3624209097
Short name T640
Test name
Test status
Simulation time 39666922 ps
CPU time 1.7 seconds
Started Jul 13 06:42:06 PM PDT 24
Finished Jul 13 06:42:10 PM PDT 24
Peak memory 218756 kb
Host smart-12863811-6534-4a8a-8d67-3a399d621ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624209097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3624209097
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.3608614928
Short name T997
Test name
Test status
Simulation time 199746185 ps
CPU time 2.67 seconds
Started Jul 13 06:42:06 PM PDT 24
Finished Jul 13 06:42:11 PM PDT 24
Peak memory 220096 kb
Host smart-3b063e01-5c87-4c3d-91cf-2374516b2dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608614928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.3608614928
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.2971063166
Short name T860
Test name
Test status
Simulation time 35519489 ps
CPU time 1.07 seconds
Started Jul 13 06:39:58 PM PDT 24
Finished Jul 13 06:40:00 PM PDT 24
Peak memory 219792 kb
Host smart-f476c133-42e9-46fd-a9ba-a747000e7b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971063166 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.2971063166
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.3291232867
Short name T914
Test name
Test status
Simulation time 32317149 ps
CPU time 0.81 seconds
Started Jul 13 06:39:59 PM PDT 24
Finished Jul 13 06:40:02 PM PDT 24
Peak memory 206648 kb
Host smart-75ea27dc-2d97-4bfc-8363-e806212caceb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291232867 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3291232867
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.4045332770
Short name T199
Test name
Test status
Simulation time 17390693 ps
CPU time 0.88 seconds
Started Jul 13 06:40:01 PM PDT 24
Finished Jul 13 06:40:04 PM PDT 24
Peak memory 216560 kb
Host smart-4303180b-1f6d-4eec-8aa8-fe2d1ab1e00a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045332770 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.4045332770
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.1558101083
Short name T81
Test name
Test status
Simulation time 26403714 ps
CPU time 1.09 seconds
Started Jul 13 06:40:03 PM PDT 24
Finished Jul 13 06:40:05 PM PDT 24
Peak memory 217344 kb
Host smart-16b0a52e-a534-4d96-95ac-1d06c3c07e4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558101083 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.1558101083
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.3422886579
Short name T136
Test name
Test status
Simulation time 27716654 ps
CPU time 1.02 seconds
Started Jul 13 06:40:01 PM PDT 24
Finished Jul 13 06:40:04 PM PDT 24
Peak memory 220024 kb
Host smart-9b7ac791-6f4f-4984-b0c1-b9b0866533f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422886579 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.3422886579
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.1544882147
Short name T994
Test name
Test status
Simulation time 54766380 ps
CPU time 1.2 seconds
Started Jul 13 06:39:56 PM PDT 24
Finished Jul 13 06:39:58 PM PDT 24
Peak memory 218648 kb
Host smart-70c42f8d-04de-411f-8990-66707649114c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544882147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.1544882147
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.1647180696
Short name T30
Test name
Test status
Simulation time 23797760 ps
CPU time 1.11 seconds
Started Jul 13 06:39:57 PM PDT 24
Finished Jul 13 06:39:59 PM PDT 24
Peak memory 216132 kb
Host smart-7b7180df-6985-4263-aba0-de2209e9e0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647180696 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.1647180696
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.4205383720
Short name T603
Test name
Test status
Simulation time 37888614 ps
CPU time 1 seconds
Started Jul 13 06:39:59 PM PDT 24
Finished Jul 13 06:40:02 PM PDT 24
Peak memory 215640 kb
Host smart-309eee93-1c5f-4a57-801d-ddb3d7113115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205383720 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.4205383720
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.760774963
Short name T211
Test name
Test status
Simulation time 294143105 ps
CPU time 2.91 seconds
Started Jul 13 06:39:59 PM PDT 24
Finished Jul 13 06:40:03 PM PDT 24
Peak memory 217504 kb
Host smart-5d2309d9-c8ab-47c1-b483-12169e09ee02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760774963 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.760774963
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.2863172412
Short name T79
Test name
Test status
Simulation time 153174300414 ps
CPU time 843.17 seconds
Started Jul 13 06:39:59 PM PDT 24
Finished Jul 13 06:54:04 PM PDT 24
Peak memory 223268 kb
Host smart-9c9381d8-94fe-4ad2-977c-7490b45a5415
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863172412 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.2863172412
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.1349338481
Short name T392
Test name
Test status
Simulation time 44906486 ps
CPU time 1.4 seconds
Started Jul 13 06:42:03 PM PDT 24
Finished Jul 13 06:42:05 PM PDT 24
Peak memory 217680 kb
Host smart-5637f728-b782-4c5d-9f36-8bbc3ad8081f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349338481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1349338481
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.2235897766
Short name T967
Test name
Test status
Simulation time 58355392 ps
CPU time 1.76 seconds
Started Jul 13 06:42:05 PM PDT 24
Finished Jul 13 06:42:09 PM PDT 24
Peak memory 218812 kb
Host smart-f7825fc3-382a-4036-bbf2-4ae05fe2e49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235897766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2235897766
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.744379109
Short name T996
Test name
Test status
Simulation time 35228270 ps
CPU time 1.45 seconds
Started Jul 13 06:42:04 PM PDT 24
Finished Jul 13 06:42:06 PM PDT 24
Peak memory 220360 kb
Host smart-79264ad3-eee3-45c9-9dcf-21fef1a8537b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744379109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.744379109
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2794750019
Short name T906
Test name
Test status
Simulation time 58020646 ps
CPU time 1.28 seconds
Started Jul 13 06:42:05 PM PDT 24
Finished Jul 13 06:42:09 PM PDT 24
Peak memory 217772 kb
Host smart-1ccc4398-aabe-4339-a0f8-71a27f79da51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794750019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2794750019
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.1199131733
Short name T587
Test name
Test status
Simulation time 95138161 ps
CPU time 1.41 seconds
Started Jul 13 06:42:02 PM PDT 24
Finished Jul 13 06:42:03 PM PDT 24
Peak memory 217620 kb
Host smart-915192e8-b555-44ed-8aa4-58f297b8cfde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199131733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.1199131733
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.2661509920
Short name T44
Test name
Test status
Simulation time 64652892 ps
CPU time 2.15 seconds
Started Jul 13 06:42:05 PM PDT 24
Finished Jul 13 06:42:10 PM PDT 24
Peak memory 218892 kb
Host smart-d4f9f31f-e886-493b-b3fb-813819a5756c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661509920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.2661509920
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.2866942929
Short name T873
Test name
Test status
Simulation time 28099808 ps
CPU time 1.21 seconds
Started Jul 13 06:42:03 PM PDT 24
Finished Jul 13 06:42:05 PM PDT 24
Peak memory 217584 kb
Host smart-8260e38e-c5ac-436f-9f01-d479c14e6eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866942929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.2866942929
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.1096365927
Short name T838
Test name
Test status
Simulation time 34701844 ps
CPU time 1.24 seconds
Started Jul 13 06:42:05 PM PDT 24
Finished Jul 13 06:42:08 PM PDT 24
Peak memory 217988 kb
Host smart-aa9d9a71-f7e9-40f2-a0b9-f01e0334ffd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096365927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1096365927
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.1502411422
Short name T11
Test name
Test status
Simulation time 65780003 ps
CPU time 2.28 seconds
Started Jul 13 06:42:06 PM PDT 24
Finished Jul 13 06:42:10 PM PDT 24
Peak memory 219744 kb
Host smart-bcb4c07a-9abc-4532-b967-988e14444da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502411422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.1502411422
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.447886452
Short name T381
Test name
Test status
Simulation time 89563585 ps
CPU time 1.27 seconds
Started Jul 13 06:42:04 PM PDT 24
Finished Jul 13 06:42:08 PM PDT 24
Peak memory 220176 kb
Host smart-6014db14-7f9b-4254-8b8f-b107e1461ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447886452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.447886452
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.1900444228
Short name T985
Test name
Test status
Simulation time 75754417 ps
CPU time 1.16 seconds
Started Jul 13 06:39:01 PM PDT 24
Finished Jul 13 06:39:03 PM PDT 24
Peak memory 220900 kb
Host smart-b2a0e2a8-e611-4645-b1f1-f081c602c85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900444228 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.1900444228
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.2535257396
Short name T549
Test name
Test status
Simulation time 70693290 ps
CPU time 0.89 seconds
Started Jul 13 06:38:59 PM PDT 24
Finished Jul 13 06:39:01 PM PDT 24
Peak memory 207072 kb
Host smart-1fe74d1e-e297-40aa-84f6-88b4375dc9b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535257396 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2535257396
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.725609907
Short name T137
Test name
Test status
Simulation time 36644736 ps
CPU time 1.18 seconds
Started Jul 13 06:38:59 PM PDT 24
Finished Jul 13 06:39:01 PM PDT 24
Peak memory 218592 kb
Host smart-677e46ea-de49-421a-843d-816c4136c5b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725609907 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_dis
able_auto_req_mode.725609907
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.571649267
Short name T64
Test name
Test status
Simulation time 24563993 ps
CPU time 1.33 seconds
Started Jul 13 06:38:58 PM PDT 24
Finished Jul 13 06:39:00 PM PDT 24
Peak memory 229872 kb
Host smart-e1852d67-472f-4703-aa2c-403f8a6cb90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571649267 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.571649267
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.3188328783
Short name T324
Test name
Test status
Simulation time 49499800 ps
CPU time 1.42 seconds
Started Jul 13 06:38:57 PM PDT 24
Finished Jul 13 06:38:59 PM PDT 24
Peak memory 218704 kb
Host smart-e921b585-f721-4269-bfa9-c11bbf90ca30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188328783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.3188328783
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.3749508594
Short name T32
Test name
Test status
Simulation time 20249569 ps
CPU time 1.09 seconds
Started Jul 13 06:38:59 PM PDT 24
Finished Jul 13 06:39:01 PM PDT 24
Peak memory 216164 kb
Host smart-73e2c9e5-7745-4a25-9066-287d28f2f0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749508594 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.3749508594
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.3148976421
Short name T899
Test name
Test status
Simulation time 17910869 ps
CPU time 1.02 seconds
Started Jul 13 06:38:59 PM PDT 24
Finished Jul 13 06:39:02 PM PDT 24
Peak memory 207432 kb
Host smart-64cf65fa-5ef5-4bd9-a874-bf96e77eea79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148976421 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.3148976421
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.3757784089
Short name T19
Test name
Test status
Simulation time 260242305 ps
CPU time 4.46 seconds
Started Jul 13 06:38:58 PM PDT 24
Finished Jul 13 06:39:04 PM PDT 24
Peak memory 236948 kb
Host smart-cc1df897-c454-49df-be01-109c72f9daf1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757784089 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.3757784089
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.3671790574
Short name T871
Test name
Test status
Simulation time 25225894 ps
CPU time 0.92 seconds
Started Jul 13 06:38:58 PM PDT 24
Finished Jul 13 06:39:00 PM PDT 24
Peak memory 215488 kb
Host smart-3f3581ec-8d68-4b83-999b-a5b51004edaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671790574 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3671790574
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.3217035924
Short name T440
Test name
Test status
Simulation time 154885604 ps
CPU time 3.33 seconds
Started Jul 13 06:38:59 PM PDT 24
Finished Jul 13 06:39:03 PM PDT 24
Peak memory 215504 kb
Host smart-f78d9e26-2919-495d-b248-c8ba40a8226c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217035924 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3217035924
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2947456329
Short name T412
Test name
Test status
Simulation time 427042320872 ps
CPU time 1576.98 seconds
Started Jul 13 06:39:00 PM PDT 24
Finished Jul 13 07:05:18 PM PDT 24
Peak memory 227100 kb
Host smart-2e4ef75a-74d8-4d5d-b7c4-d90e156edb8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947456329 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.2947456329
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.3977222968
Short name T570
Test name
Test status
Simulation time 71424272 ps
CPU time 1.28 seconds
Started Jul 13 06:39:59 PM PDT 24
Finished Jul 13 06:40:02 PM PDT 24
Peak memory 218916 kb
Host smart-0527d6da-d937-4844-99f5-adcedbaf1f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977222968 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.3977222968
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.720695102
Short name T356
Test name
Test status
Simulation time 35852121 ps
CPU time 0.87 seconds
Started Jul 13 06:39:58 PM PDT 24
Finished Jul 13 06:39:59 PM PDT 24
Peak memory 207016 kb
Host smart-e6c2e1b5-0f8e-43ea-acd3-0da579014a71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720695102 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.720695102
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.3054096006
Short name T139
Test name
Test status
Simulation time 30158015 ps
CPU time 1.19 seconds
Started Jul 13 06:39:56 PM PDT 24
Finished Jul 13 06:39:58 PM PDT 24
Peak memory 217100 kb
Host smart-4b6fbf3a-1491-43aa-9748-ae8c2e3d7e5e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054096006 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.3054096006
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.4213413657
Short name T185
Test name
Test status
Simulation time 46152554 ps
CPU time 0.99 seconds
Started Jul 13 06:39:57 PM PDT 24
Finished Jul 13 06:39:58 PM PDT 24
Peak memory 224088 kb
Host smart-87b6695a-5e64-4b7e-9b60-ac41d6a9ff63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213413657 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.4213413657
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.1820843279
Short name T414
Test name
Test status
Simulation time 71582072 ps
CPU time 1.07 seconds
Started Jul 13 06:39:58 PM PDT 24
Finished Jul 13 06:40:00 PM PDT 24
Peak memory 217636 kb
Host smart-bd729a45-4650-4cc8-ae24-b40c08811756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820843279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1820843279
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.3024768214
Short name T786
Test name
Test status
Simulation time 27030645 ps
CPU time 0.96 seconds
Started Jul 13 06:39:55 PM PDT 24
Finished Jul 13 06:39:57 PM PDT 24
Peak memory 216332 kb
Host smart-b0d35925-f025-4f82-9620-3840f17aa6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024768214 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3024768214
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.1070361710
Short name T690
Test name
Test status
Simulation time 43311921 ps
CPU time 0.96 seconds
Started Jul 13 06:39:58 PM PDT 24
Finished Jul 13 06:40:00 PM PDT 24
Peak memory 215624 kb
Host smart-c24d7828-2e60-4aa9-b9d5-d8a1d69a40bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070361710 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.1070361710
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.1522655508
Short name T591
Test name
Test status
Simulation time 133109128 ps
CPU time 3.26 seconds
Started Jul 13 06:39:54 PM PDT 24
Finished Jul 13 06:39:58 PM PDT 24
Peak memory 217692 kb
Host smart-55243d3e-425d-4c54-8029-9e96c06491a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522655508 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.1522655508
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.1767327473
Short name T924
Test name
Test status
Simulation time 80593738383 ps
CPU time 904.29 seconds
Started Jul 13 06:39:59 PM PDT 24
Finished Jul 13 06:55:06 PM PDT 24
Peak memory 224028 kb
Host smart-415de989-03aa-418c-a33d-67be9401599d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767327473 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.1767327473
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert_test.1935033395
Short name T290
Test name
Test status
Simulation time 15232524 ps
CPU time 0.96 seconds
Started Jul 13 06:39:57 PM PDT 24
Finished Jul 13 06:39:59 PM PDT 24
Peak memory 215296 kb
Host smart-6ed62cba-5456-40fa-9636-6a6bfc1aa566
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935033395 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.1935033395
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.3505945726
Short name T787
Test name
Test status
Simulation time 56461450 ps
CPU time 1.84 seconds
Started Jul 13 06:40:00 PM PDT 24
Finished Jul 13 06:40:04 PM PDT 24
Peak memory 217248 kb
Host smart-8412ae5a-d0fb-4bdc-8639-174b95f4c9a3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505945726 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.3505945726
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.1243431891
Short name T152
Test name
Test status
Simulation time 106814000 ps
CPU time 1.3 seconds
Started Jul 13 06:40:03 PM PDT 24
Finished Jul 13 06:40:06 PM PDT 24
Peak memory 225852 kb
Host smart-90b6fb1a-ecb4-46fd-b3fb-c39c5a266cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243431891 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.1243431891
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.2101110418
Short name T771
Test name
Test status
Simulation time 90641118 ps
CPU time 1.23 seconds
Started Jul 13 06:39:59 PM PDT 24
Finished Jul 13 06:40:01 PM PDT 24
Peak memory 217504 kb
Host smart-2582bf1d-e826-48a8-9051-62f48e635283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101110418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.2101110418
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.2289425980
Short name T463
Test name
Test status
Simulation time 34002834 ps
CPU time 0.93 seconds
Started Jul 13 06:40:00 PM PDT 24
Finished Jul 13 06:40:03 PM PDT 24
Peak memory 215856 kb
Host smart-1b15ae1f-4bb7-4cd6-8131-b36708239ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289425980 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.2289425980
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.3449012246
Short name T94
Test name
Test status
Simulation time 29300906 ps
CPU time 0.94 seconds
Started Jul 13 06:39:59 PM PDT 24
Finished Jul 13 06:40:02 PM PDT 24
Peak memory 215628 kb
Host smart-74c93c06-4a70-4d43-b06f-70b5ce2310c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449012246 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.3449012246
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.26418503
Short name T339
Test name
Test status
Simulation time 805170733 ps
CPU time 2.11 seconds
Started Jul 13 06:40:01 PM PDT 24
Finished Jul 13 06:40:05 PM PDT 24
Peak memory 217716 kb
Host smart-1a675891-289c-4708-a87e-f23609939236
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26418503 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.26418503
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.1665612926
Short name T595
Test name
Test status
Simulation time 228472833535 ps
CPU time 1310.93 seconds
Started Jul 13 06:40:01 PM PDT 24
Finished Jul 13 07:01:54 PM PDT 24
Peak memory 224020 kb
Host smart-bae85a9b-0134-438d-a748-8ff9d642eaf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665612926 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.1665612926
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.2512004442
Short name T423
Test name
Test status
Simulation time 40867255 ps
CPU time 1.2 seconds
Started Jul 13 06:39:56 PM PDT 24
Finished Jul 13 06:39:58 PM PDT 24
Peak memory 218820 kb
Host smart-15e2ebf7-6745-4472-8da6-b9dc95e765b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512004442 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.2512004442
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.2393579458
Short name T816
Test name
Test status
Simulation time 18684824 ps
CPU time 1.05 seconds
Started Jul 13 06:39:59 PM PDT 24
Finished Jul 13 06:40:02 PM PDT 24
Peak memory 207076 kb
Host smart-e26549ac-6b3e-48e2-b85b-7bd6762d958b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393579458 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.2393579458
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.2232472608
Short name T844
Test name
Test status
Simulation time 10774399 ps
CPU time 0.91 seconds
Started Jul 13 06:40:01 PM PDT 24
Finished Jul 13 06:40:04 PM PDT 24
Peak memory 216356 kb
Host smart-982f231b-c507-4b78-b98e-60dff8409504
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232472608 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.2232472608
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.1336148815
Short name T579
Test name
Test status
Simulation time 59976038 ps
CPU time 1.12 seconds
Started Jul 13 06:40:01 PM PDT 24
Finished Jul 13 06:40:04 PM PDT 24
Peak memory 217212 kb
Host smart-cd1217ee-2a4f-4a80-a604-dfea10802a08
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336148815 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.1336148815
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.769884805
Short name T62
Test name
Test status
Simulation time 19424338 ps
CPU time 1.22 seconds
Started Jul 13 06:39:59 PM PDT 24
Finished Jul 13 06:40:01 PM PDT 24
Peak memory 224392 kb
Host smart-11c21be8-8467-44a7-9eb8-7f0151c71d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769884805 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.769884805
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.2016153512
Short name T441
Test name
Test status
Simulation time 37157943 ps
CPU time 1.38 seconds
Started Jul 13 06:40:00 PM PDT 24
Finished Jul 13 06:40:03 PM PDT 24
Peak memory 217540 kb
Host smart-ea432ca2-1092-4c9c-b5b9-c2ef689a3500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016153512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2016153512
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.3944406412
Short name T499
Test name
Test status
Simulation time 27532120 ps
CPU time 1.09 seconds
Started Jul 13 06:39:58 PM PDT 24
Finished Jul 13 06:39:59 PM PDT 24
Peak memory 224388 kb
Host smart-81cc92b5-ab54-496a-9c3e-2a3575211ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944406412 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3944406412
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.3330541379
Short name T905
Test name
Test status
Simulation time 18989449 ps
CPU time 1.01 seconds
Started Jul 13 06:39:59 PM PDT 24
Finished Jul 13 06:40:01 PM PDT 24
Peak memory 215500 kb
Host smart-a77ce532-56d8-4e17-aa12-9b281e71e48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330541379 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.3330541379
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.708184996
Short name T695
Test name
Test status
Simulation time 97832244 ps
CPU time 1.51 seconds
Started Jul 13 06:40:00 PM PDT 24
Finished Jul 13 06:40:04 PM PDT 24
Peak memory 217580 kb
Host smart-587d3afb-217f-4f18-a885-e7d3f3a28c6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708184996 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.708184996
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.778833293
Short name T854
Test name
Test status
Simulation time 75301927524 ps
CPU time 611.89 seconds
Started Jul 13 06:39:59 PM PDT 24
Finished Jul 13 06:50:13 PM PDT 24
Peak memory 219140 kb
Host smart-29e486c8-6a88-4f76-957b-7f60f86b2d6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778833293 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.778833293
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.4171728253
Short name T154
Test name
Test status
Simulation time 21121444 ps
CPU time 1.25 seconds
Started Jul 13 06:39:58 PM PDT 24
Finished Jul 13 06:40:00 PM PDT 24
Peak memory 219032 kb
Host smart-530b013a-f24d-4448-8fb8-26bb9e08f31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171728253 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.4171728253
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.2923031761
Short name T526
Test name
Test status
Simulation time 48707815 ps
CPU time 0.97 seconds
Started Jul 13 06:40:03 PM PDT 24
Finished Jul 13 06:40:05 PM PDT 24
Peak memory 207008 kb
Host smart-a35da946-ab3b-4877-905c-bb9885e44e8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923031761 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2923031761
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.1820710720
Short name T224
Test name
Test status
Simulation time 26901347 ps
CPU time 0.82 seconds
Started Jul 13 06:40:01 PM PDT 24
Finished Jul 13 06:40:04 PM PDT 24
Peak memory 216476 kb
Host smart-243267ed-2dc7-4591-beda-934f6fd7331f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820710720 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1820710720
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.1541238558
Short name T361
Test name
Test status
Simulation time 15068644 ps
CPU time 1.01 seconds
Started Jul 13 06:40:01 PM PDT 24
Finished Jul 13 06:40:04 PM PDT 24
Peak memory 217212 kb
Host smart-f431553a-4621-4df4-af58-fdeea29b4d8e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541238558 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.1541238558
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.253566188
Short name T907
Test name
Test status
Simulation time 27905060 ps
CPU time 0.99 seconds
Started Jul 13 06:40:01 PM PDT 24
Finished Jul 13 06:40:04 PM PDT 24
Peak memory 224088 kb
Host smart-3d07a39a-6b88-4ee5-a447-579223977db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253566188 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.253566188
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.137901794
Short name T341
Test name
Test status
Simulation time 29034102 ps
CPU time 1.28 seconds
Started Jul 13 06:40:01 PM PDT 24
Finished Jul 13 06:40:04 PM PDT 24
Peak memory 220200 kb
Host smart-8b53d30b-84d4-4ac8-8b73-c79f20040145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137901794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.137901794
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.96139762
Short name T861
Test name
Test status
Simulation time 37748339 ps
CPU time 0.83 seconds
Started Jul 13 06:39:56 PM PDT 24
Finished Jul 13 06:39:57 PM PDT 24
Peak memory 215868 kb
Host smart-0a5ea1b6-55f1-4197-b2c1-8ddaddfc432a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96139762 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.96139762
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.881205991
Short name T554
Test name
Test status
Simulation time 17040631 ps
CPU time 1.1 seconds
Started Jul 13 06:40:00 PM PDT 24
Finished Jul 13 06:40:03 PM PDT 24
Peak memory 215560 kb
Host smart-c248004b-6c4d-41d0-b110-3028e7174454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881205991 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.881205991
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.1875354333
Short name T5
Test name
Test status
Simulation time 209775305 ps
CPU time 3.11 seconds
Started Jul 13 06:40:01 PM PDT 24
Finished Jul 13 06:40:06 PM PDT 24
Peak memory 215576 kb
Host smart-7e330360-2496-46de-8c21-30c8594241b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875354333 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.1875354333
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.2046564857
Short name T244
Test name
Test status
Simulation time 52245071560 ps
CPU time 1133.61 seconds
Started Jul 13 06:40:03 PM PDT 24
Finished Jul 13 06:58:58 PM PDT 24
Peak memory 220944 kb
Host smart-fd232a62-9f86-4c88-92ca-72f4b0a44b8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046564857 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.2046564857
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.2499339234
Short name T455
Test name
Test status
Simulation time 72084078 ps
CPU time 1.14 seconds
Started Jul 13 06:40:19 PM PDT 24
Finished Jul 13 06:40:21 PM PDT 24
Peak memory 218480 kb
Host smart-68a553ee-dd61-4158-80f3-b10616a40abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499339234 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2499339234
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.1651060979
Short name T632
Test name
Test status
Simulation time 14275102 ps
CPU time 0.9 seconds
Started Jul 13 06:40:14 PM PDT 24
Finished Jul 13 06:40:15 PM PDT 24
Peak memory 206964 kb
Host smart-52327dee-4948-4735-bf70-c230f7163118
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651060979 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1651060979
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.3817346656
Short name T737
Test name
Test status
Simulation time 29474010 ps
CPU time 1.2 seconds
Started Jul 13 06:40:16 PM PDT 24
Finished Jul 13 06:40:19 PM PDT 24
Peak memory 217096 kb
Host smart-a725fffe-268e-4802-a92a-4b2919e1af30
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817346656 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.3817346656
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.566873270
Short name T175
Test name
Test status
Simulation time 19510796 ps
CPU time 1.07 seconds
Started Jul 13 06:40:12 PM PDT 24
Finished Jul 13 06:40:13 PM PDT 24
Peak memory 218904 kb
Host smart-2e6709dd-df9d-4b28-99b8-348282a0b507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566873270 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.566873270
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.3199315492
Short name T95
Test name
Test status
Simulation time 63273007 ps
CPU time 1.43 seconds
Started Jul 13 06:40:01 PM PDT 24
Finished Jul 13 06:40:04 PM PDT 24
Peak memory 219356 kb
Host smart-bdc766ae-ebbd-4a8f-a35b-067dadb035d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199315492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.3199315492
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.4270950978
Short name T901
Test name
Test status
Simulation time 22520406 ps
CPU time 1.11 seconds
Started Jul 13 06:40:14 PM PDT 24
Finished Jul 13 06:40:17 PM PDT 24
Peak memory 215824 kb
Host smart-1dc07f09-64c3-48a6-858d-a73a4bf6d2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270950978 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.4270950978
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.3134301725
Short name T898
Test name
Test status
Simulation time 51433165 ps
CPU time 0.92 seconds
Started Jul 13 06:39:58 PM PDT 24
Finished Jul 13 06:40:00 PM PDT 24
Peak memory 215504 kb
Host smart-33b9b3c1-e607-44d4-9d5e-1240d07282f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134301725 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.3134301725
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.1320689956
Short name T360
Test name
Test status
Simulation time 374354276 ps
CPU time 2.26 seconds
Started Jul 13 06:40:00 PM PDT 24
Finished Jul 13 06:40:04 PM PDT 24
Peak memory 217468 kb
Host smart-53670b9d-fd62-4d27-95eb-5936c446c2c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320689956 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1320689956
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.3949111699
Short name T232
Test name
Test status
Simulation time 351266990927 ps
CPU time 626.92 seconds
Started Jul 13 06:40:15 PM PDT 24
Finished Jul 13 06:50:44 PM PDT 24
Peak memory 219708 kb
Host smart-3e9ea011-f893-4cc5-939c-52b79964461a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949111699 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.3949111699
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.429978909
Short name T949
Test name
Test status
Simulation time 74155386 ps
CPU time 1.11 seconds
Started Jul 13 06:40:14 PM PDT 24
Finished Jul 13 06:40:16 PM PDT 24
Peak memory 220072 kb
Host smart-9d73b4e7-465c-4d1e-b90b-ddffea16da2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429978909 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.429978909
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.3809335411
Short name T752
Test name
Test status
Simulation time 14866994 ps
CPU time 0.99 seconds
Started Jul 13 06:40:12 PM PDT 24
Finished Jul 13 06:40:14 PM PDT 24
Peak memory 215276 kb
Host smart-7704e133-1bce-46a6-aa84-635b91207a69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809335411 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.3809335411
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.1592037129
Short name T230
Test name
Test status
Simulation time 42330097 ps
CPU time 0.93 seconds
Started Jul 13 06:40:13 PM PDT 24
Finished Jul 13 06:40:14 PM PDT 24
Peak memory 215712 kb
Host smart-cf041354-60b6-41df-bfce-c54fe04cd30b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592037129 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1592037129
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_err.87247566
Short name T909
Test name
Test status
Simulation time 19445172 ps
CPU time 1.15 seconds
Started Jul 13 06:40:16 PM PDT 24
Finished Jul 13 06:40:20 PM PDT 24
Peak memory 219020 kb
Host smart-1386762d-3412-4571-adb1-fc014bd6ee5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87247566 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.87247566
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.3174765276
Short name T660
Test name
Test status
Simulation time 29236822 ps
CPU time 1.15 seconds
Started Jul 13 06:40:13 PM PDT 24
Finished Jul 13 06:40:15 PM PDT 24
Peak memory 220100 kb
Host smart-bc655e83-ad64-4775-b631-8d675fec61d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174765276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3174765276
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.3237837026
Short name T912
Test name
Test status
Simulation time 44166545 ps
CPU time 0.91 seconds
Started Jul 13 06:40:15 PM PDT 24
Finished Jul 13 06:40:18 PM PDT 24
Peak memory 215644 kb
Host smart-ca065a40-5d75-4fa3-99eb-bec0383a5b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237837026 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.3237837026
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.4108970994
Short name T957
Test name
Test status
Simulation time 17655639 ps
CPU time 1.05 seconds
Started Jul 13 06:40:15 PM PDT 24
Finished Jul 13 06:40:18 PM PDT 24
Peak memory 215580 kb
Host smart-f2697dfc-8e8a-4390-857a-a0cfdab8dae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108970994 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.4108970994
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.2349897873
Short name T289
Test name
Test status
Simulation time 66338749 ps
CPU time 1.93 seconds
Started Jul 13 06:40:15 PM PDT 24
Finished Jul 13 06:40:19 PM PDT 24
Peak memory 217608 kb
Host smart-fddf118d-f981-44e2-995e-74229b67ee2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349897873 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2349897873
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.46015806
Short name T332
Test name
Test status
Simulation time 109079760296 ps
CPU time 1486.21 seconds
Started Jul 13 06:40:17 PM PDT 24
Finished Jul 13 07:05:05 PM PDT 24
Peak memory 226384 kb
Host smart-7c128319-7d48-4bf1-85b9-f3d7f4995d90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46015806 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.46015806
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.3528052613
Short name T724
Test name
Test status
Simulation time 48907821 ps
CPU time 1.15 seconds
Started Jul 13 06:40:15 PM PDT 24
Finished Jul 13 06:40:19 PM PDT 24
Peak memory 219080 kb
Host smart-6d675bce-22c4-4e20-9eb6-2c6a6afe0a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528052613 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3528052613
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.3680060240
Short name T421
Test name
Test status
Simulation time 29574936 ps
CPU time 0.92 seconds
Started Jul 13 06:40:14 PM PDT 24
Finished Jul 13 06:40:17 PM PDT 24
Peak memory 207048 kb
Host smart-aba373f3-a608-4867-8716-c668a19a0384
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680060240 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3680060240
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.28213249
Short name T149
Test name
Test status
Simulation time 41290279 ps
CPU time 1.33 seconds
Started Jul 13 06:40:15 PM PDT 24
Finished Jul 13 06:40:19 PM PDT 24
Peak memory 217228 kb
Host smart-93a9b0d5-751e-4e9c-9ecb-219c5535b667
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28213249 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_dis
able_auto_req_mode.28213249
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.4275026943
Short name T480
Test name
Test status
Simulation time 21107202 ps
CPU time 1.09 seconds
Started Jul 13 06:40:19 PM PDT 24
Finished Jul 13 06:40:21 PM PDT 24
Peak memory 219556 kb
Host smart-4f48c277-0d8c-4040-9156-5c19f1aff43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275026943 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.4275026943
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.3004472544
Short name T245
Test name
Test status
Simulation time 268967840 ps
CPU time 1.22 seconds
Started Jul 13 06:40:16 PM PDT 24
Finished Jul 13 06:40:19 PM PDT 24
Peak memory 219396 kb
Host smart-64af1682-a73c-4cd4-beb1-8a103e33f58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004472544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.3004472544
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_smoke.750744713
Short name T568
Test name
Test status
Simulation time 16482378 ps
CPU time 0.99 seconds
Started Jul 13 06:40:14 PM PDT 24
Finished Jul 13 06:40:16 PM PDT 24
Peak memory 215604 kb
Host smart-b42d7db6-9485-46a3-bbdb-337223d93244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750744713 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.750744713
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.4266763087
Short name T675
Test name
Test status
Simulation time 379914820 ps
CPU time 2.38 seconds
Started Jul 13 06:40:14 PM PDT 24
Finished Jul 13 06:40:18 PM PDT 24
Peak memory 217892 kb
Host smart-f1e5a48a-753d-4623-84fc-6af956d81a74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266763087 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.4266763087
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3652062823
Short name T634
Test name
Test status
Simulation time 553902282943 ps
CPU time 3107.23 seconds
Started Jul 13 06:40:18 PM PDT 24
Finished Jul 13 07:32:07 PM PDT 24
Peak memory 234664 kb
Host smart-6c9ee5eb-af37-4222-af96-4e7b4ea10078
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652062823 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.3652062823
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.3488926267
Short name T801
Test name
Test status
Simulation time 79943489 ps
CPU time 1.23 seconds
Started Jul 13 06:40:14 PM PDT 24
Finished Jul 13 06:40:16 PM PDT 24
Peak memory 218940 kb
Host smart-da9ebc21-3161-420b-9c3a-decfa07b4553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488926267 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3488926267
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.3220826276
Short name T791
Test name
Test status
Simulation time 20644635 ps
CPU time 1.06 seconds
Started Jul 13 06:40:16 PM PDT 24
Finished Jul 13 06:40:19 PM PDT 24
Peak memory 215236 kb
Host smart-06c41c1b-5b7d-4b71-b94f-29247da2cf4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220826276 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.3220826276
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.1859103642
Short name T946
Test name
Test status
Simulation time 15144200 ps
CPU time 0.94 seconds
Started Jul 13 06:40:16 PM PDT 24
Finished Jul 13 06:40:19 PM PDT 24
Peak memory 216748 kb
Host smart-1754b2ea-f411-4ffe-90e5-ba52f105f55f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859103642 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1859103642
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.1925670077
Short name T157
Test name
Test status
Simulation time 52299935 ps
CPU time 1.1 seconds
Started Jul 13 06:40:14 PM PDT 24
Finished Jul 13 06:40:16 PM PDT 24
Peak memory 217228 kb
Host smart-4f78bf06-4a72-4962-a9f3-31cf8fa6328b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925670077 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.1925670077
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.2135619627
Short name T684
Test name
Test status
Simulation time 27889565 ps
CPU time 0.87 seconds
Started Jul 13 06:40:14 PM PDT 24
Finished Jul 13 06:40:16 PM PDT 24
Peak memory 218604 kb
Host smart-15345ae5-24fc-4c55-8b0f-606e42ec489c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135619627 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2135619627
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.2498634987
Short name T388
Test name
Test status
Simulation time 70170445 ps
CPU time 1.37 seconds
Started Jul 13 06:40:16 PM PDT 24
Finished Jul 13 06:40:19 PM PDT 24
Peak memory 218976 kb
Host smart-70cdbab7-febd-46b7-b8cc-c53ece070ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498634987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.2498634987
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.3199896333
Short name T103
Test name
Test status
Simulation time 33604147 ps
CPU time 0.88 seconds
Started Jul 13 06:40:13 PM PDT 24
Finished Jul 13 06:40:15 PM PDT 24
Peak memory 215960 kb
Host smart-6465e29d-55d1-4e84-8a1a-ad2f84799239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199896333 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.3199896333
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.3199343749
Short name T376
Test name
Test status
Simulation time 53795488 ps
CPU time 0.93 seconds
Started Jul 13 06:40:17 PM PDT 24
Finished Jul 13 06:40:20 PM PDT 24
Peak memory 215572 kb
Host smart-b4a42210-d27c-4129-95e3-81d304f77377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199343749 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3199343749
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.3883229776
Short name T965
Test name
Test status
Simulation time 783019338 ps
CPU time 3.5 seconds
Started Jul 13 06:40:15 PM PDT 24
Finished Jul 13 06:40:21 PM PDT 24
Peak memory 217712 kb
Host smart-84258524-23c3-4161-9fbf-3bbf07208d3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883229776 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.3883229776
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.3865737768
Short name T238
Test name
Test status
Simulation time 497851828196 ps
CPU time 2967.31 seconds
Started Jul 13 06:40:14 PM PDT 24
Finished Jul 13 07:29:43 PM PDT 24
Peak memory 230776 kb
Host smart-20d02770-1454-4745-80d0-f8ecbcdc1c8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865737768 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.3865737768
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.139039946
Short name T403
Test name
Test status
Simulation time 26906342 ps
CPU time 1.28 seconds
Started Jul 13 06:40:13 PM PDT 24
Finished Jul 13 06:40:15 PM PDT 24
Peak memory 218852 kb
Host smart-6684ae7b-36ef-494c-8a6a-1bc000cbb02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139039946 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.139039946
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.97638956
Short name T22
Test name
Test status
Simulation time 20536130 ps
CPU time 0.86 seconds
Started Jul 13 06:40:14 PM PDT 24
Finished Jul 13 06:40:16 PM PDT 24
Peak memory 215240 kb
Host smart-cdc02870-3400-49ef-a29c-dd524b15f171
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97638956 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.97638956
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.1659990996
Short name T702
Test name
Test status
Simulation time 18282492 ps
CPU time 0.92 seconds
Started Jul 13 06:40:16 PM PDT 24
Finished Jul 13 06:40:19 PM PDT 24
Peak memory 216528 kb
Host smart-f2b1e62d-1434-4869-8576-e6a6f21d0bd3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659990996 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.1659990996
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_err.2142579062
Short name T888
Test name
Test status
Simulation time 34708368 ps
CPU time 0.96 seconds
Started Jul 13 06:40:16 PM PDT 24
Finished Jul 13 06:40:19 PM PDT 24
Peak memory 218800 kb
Host smart-fb4663c0-d1f3-4239-9b83-96005d28bb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142579062 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.2142579062
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.4158642301
Short name T393
Test name
Test status
Simulation time 72974846 ps
CPU time 1.43 seconds
Started Jul 13 06:40:13 PM PDT 24
Finished Jul 13 06:40:15 PM PDT 24
Peak memory 218840 kb
Host smart-f808034b-9a82-414f-aacd-112412ce0073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158642301 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.4158642301
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.515021135
Short name T102
Test name
Test status
Simulation time 27900503 ps
CPU time 0.95 seconds
Started Jul 13 06:40:17 PM PDT 24
Finished Jul 13 06:40:20 PM PDT 24
Peak memory 216132 kb
Host smart-54232757-817f-4a7d-96ab-95d50011c711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515021135 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.515021135
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.399291477
Short name T669
Test name
Test status
Simulation time 92445180 ps
CPU time 0.96 seconds
Started Jul 13 06:40:17 PM PDT 24
Finished Jul 13 06:40:20 PM PDT 24
Peak memory 215624 kb
Host smart-b4241cd0-f88a-4ecb-9429-62187f0d34e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399291477 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.399291477
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.2580839339
Short name T756
Test name
Test status
Simulation time 213504852 ps
CPU time 2.96 seconds
Started Jul 13 06:40:19 PM PDT 24
Finished Jul 13 06:40:23 PM PDT 24
Peak memory 217464 kb
Host smart-213d2458-e0e6-4f8b-b64a-7ef76a56cd70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580839339 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.2580839339
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.330415894
Short name T883
Test name
Test status
Simulation time 39854842267 ps
CPU time 447.33 seconds
Started Jul 13 06:40:16 PM PDT 24
Finished Jul 13 06:47:46 PM PDT 24
Peak memory 224020 kb
Host smart-84d80f78-9578-4da7-bee1-0714f714acfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330415894 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.330415894
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2915567285
Short name T666
Test name
Test status
Simulation time 27364869 ps
CPU time 1.21 seconds
Started Jul 13 06:40:19 PM PDT 24
Finished Jul 13 06:40:21 PM PDT 24
Peak memory 220036 kb
Host smart-c50ea476-3fd6-4d39-a99f-234860d6ec84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915567285 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2915567285
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.927336470
Short name T834
Test name
Test status
Simulation time 16245532 ps
CPU time 0.89 seconds
Started Jul 13 06:40:25 PM PDT 24
Finished Jul 13 06:40:26 PM PDT 24
Peak memory 206988 kb
Host smart-cba34b22-cc05-46f7-b46e-4bd76f9d7288
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927336470 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.927336470
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.298214557
Short name T828
Test name
Test status
Simulation time 31936756 ps
CPU time 1.14 seconds
Started Jul 13 06:40:25 PM PDT 24
Finished Jul 13 06:40:27 PM PDT 24
Peak memory 217240 kb
Host smart-884e3065-39dc-4308-9c58-ef49ddd978c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298214557 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_di
sable_auto_req_mode.298214557
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.2535390080
Short name T71
Test name
Test status
Simulation time 25760087 ps
CPU time 0.98 seconds
Started Jul 13 06:40:27 PM PDT 24
Finished Jul 13 06:40:29 PM PDT 24
Peak memory 220060 kb
Host smart-15041eab-e108-45c0-9e1d-dd7472f09ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535390080 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.2535390080
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.1528147873
Short name T84
Test name
Test status
Simulation time 98803259 ps
CPU time 1.03 seconds
Started Jul 13 06:40:15 PM PDT 24
Finished Jul 13 06:40:18 PM PDT 24
Peak memory 217880 kb
Host smart-9a5d1dad-e34d-45b1-b1dc-deb5eec9a109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528147873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1528147873
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.4006755999
Short name T977
Test name
Test status
Simulation time 23672137 ps
CPU time 1.27 seconds
Started Jul 13 06:40:15 PM PDT 24
Finished Jul 13 06:40:18 PM PDT 24
Peak memory 224352 kb
Host smart-9843ca36-b97c-4a9e-8f29-e4a5fc127de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006755999 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.4006755999
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.2966300541
Short name T649
Test name
Test status
Simulation time 57599277 ps
CPU time 0.92 seconds
Started Jul 13 06:40:15 PM PDT 24
Finished Jul 13 06:40:18 PM PDT 24
Peak memory 215584 kb
Host smart-6ff47c48-571c-43d9-a8ae-d587b2258851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966300541 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.2966300541
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.1146777497
Short name T210
Test name
Test status
Simulation time 173548398 ps
CPU time 1.91 seconds
Started Jul 13 06:40:14 PM PDT 24
Finished Jul 13 06:40:17 PM PDT 24
Peak memory 219824 kb
Host smart-b6ed01a7-39eb-4580-9fef-4029f6d2a2e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146777497 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.1146777497
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.1582609882
Short name T741
Test name
Test status
Simulation time 100826831920 ps
CPU time 365.88 seconds
Started Jul 13 06:40:16 PM PDT 24
Finished Jul 13 06:46:24 PM PDT 24
Peak memory 224072 kb
Host smart-0e9a840c-3106-4757-9f94-fbc9bce6cefd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582609882 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.1582609882
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.1699071381
Short name T661
Test name
Test status
Simulation time 24889686 ps
CPU time 1.19 seconds
Started Jul 13 06:39:00 PM PDT 24
Finished Jul 13 06:39:02 PM PDT 24
Peak memory 220048 kb
Host smart-d8221cfd-0b52-4303-ab57-db291bca882f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699071381 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.1699071381
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.2806568549
Short name T405
Test name
Test status
Simulation time 61797628 ps
CPU time 1.03 seconds
Started Jul 13 06:38:59 PM PDT 24
Finished Jul 13 06:39:01 PM PDT 24
Peak memory 215192 kb
Host smart-840fed13-7f69-4f9a-91db-02d18262d78d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806568549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2806568549
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.3057221074
Short name T186
Test name
Test status
Simulation time 16116117 ps
CPU time 0.85 seconds
Started Jul 13 06:38:59 PM PDT 24
Finished Jul 13 06:39:02 PM PDT 24
Peak memory 216556 kb
Host smart-7fa2b6d0-caec-441a-b7b4-aba01325794f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057221074 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.3057221074
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.1050675160
Short name T294
Test name
Test status
Simulation time 64899261 ps
CPU time 1.12 seconds
Started Jul 13 06:39:01 PM PDT 24
Finished Jul 13 06:39:03 PM PDT 24
Peak memory 217180 kb
Host smart-c1ff91d8-821c-49de-941a-7963d68207cb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050675160 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.1050675160
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.2885323362
Short name T124
Test name
Test status
Simulation time 24433222 ps
CPU time 1.24 seconds
Started Jul 13 06:39:01 PM PDT 24
Finished Jul 13 06:39:03 PM PDT 24
Peak memory 220744 kb
Host smart-b8fc745f-4711-42e3-bbd4-b6db1af133c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885323362 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.2885323362
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.3841859500
Short name T974
Test name
Test status
Simulation time 56098189 ps
CPU time 1.24 seconds
Started Jul 13 06:38:57 PM PDT 24
Finished Jul 13 06:38:59 PM PDT 24
Peak memory 220368 kb
Host smart-63cdd495-d8b9-405b-aea7-b0f8e13406c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841859500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.3841859500
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.416318357
Short name T107
Test name
Test status
Simulation time 22690380 ps
CPU time 0.94 seconds
Started Jul 13 06:39:03 PM PDT 24
Finished Jul 13 06:39:04 PM PDT 24
Peak memory 216108 kb
Host smart-c087d19c-3e31-4fe3-a5db-95043c1dfec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416318357 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.416318357
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.2619105382
Short name T27
Test name
Test status
Simulation time 44378127 ps
CPU time 0.91 seconds
Started Jul 13 06:38:58 PM PDT 24
Finished Jul 13 06:39:00 PM PDT 24
Peak memory 207412 kb
Host smart-fc0a677a-781d-47cc-b9cb-fdca139963d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619105382 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.2619105382
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.2274222594
Short name T18
Test name
Test status
Simulation time 468673949 ps
CPU time 4.17 seconds
Started Jul 13 06:39:01 PM PDT 24
Finished Jul 13 06:39:07 PM PDT 24
Peak memory 242952 kb
Host smart-1634b7e8-c4a6-4203-a506-668ae7119394
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274222594 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.2274222594
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.2826239903
Short name T578
Test name
Test status
Simulation time 15712509 ps
CPU time 0.93 seconds
Started Jul 13 06:38:56 PM PDT 24
Finished Jul 13 06:38:57 PM PDT 24
Peak memory 215600 kb
Host smart-02bdf36b-261b-4d9a-ae5b-7924c8dbe917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826239903 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.2826239903
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.4157647500
Short name T379
Test name
Test status
Simulation time 336704653 ps
CPU time 6.83 seconds
Started Jul 13 06:38:58 PM PDT 24
Finished Jul 13 06:39:06 PM PDT 24
Peak memory 217460 kb
Host smart-afdf4f54-917b-460e-97ea-f5b3a9ae97a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157647500 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.4157647500
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.3207714447
Short name T241
Test name
Test status
Simulation time 325691677743 ps
CPU time 1000.2 seconds
Started Jul 13 06:38:59 PM PDT 24
Finished Jul 13 06:55:41 PM PDT 24
Peak memory 221448 kb
Host smart-b2e8bf11-e209-4409-8be0-6e2262659f26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207714447 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.3207714447
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.1969268440
Short name T226
Test name
Test status
Simulation time 53716666 ps
CPU time 1.32 seconds
Started Jul 13 06:40:25 PM PDT 24
Finished Jul 13 06:40:27 PM PDT 24
Peak memory 215948 kb
Host smart-5aa54f84-4aa2-4222-8276-d725341656e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969268440 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.1969268440
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.3333447790
Short name T495
Test name
Test status
Simulation time 168359823 ps
CPU time 0.91 seconds
Started Jul 13 06:40:28 PM PDT 24
Finished Jul 13 06:40:31 PM PDT 24
Peak memory 215192 kb
Host smart-f9b2fc8f-9a27-448a-8e77-2fe33253c5e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333447790 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3333447790
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.2393807403
Short name T201
Test name
Test status
Simulation time 20382991 ps
CPU time 0.88 seconds
Started Jul 13 06:40:23 PM PDT 24
Finished Jul 13 06:40:24 PM PDT 24
Peak memory 216564 kb
Host smart-1fe7c349-7f2d-4ed0-8172-40b2c4e9fdda
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393807403 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.2393807403
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.228551151
Short name T435
Test name
Test status
Simulation time 31255960 ps
CPU time 1.13 seconds
Started Jul 13 06:40:28 PM PDT 24
Finished Jul 13 06:40:31 PM PDT 24
Peak memory 217052 kb
Host smart-1c7d664a-72f7-4f41-bdbc-306fad86220f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228551151 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_di
sable_auto_req_mode.228551151
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.3221401896
Short name T763
Test name
Test status
Simulation time 28167948 ps
CPU time 1 seconds
Started Jul 13 06:40:23 PM PDT 24
Finished Jul 13 06:40:25 PM PDT 24
Peak memory 224052 kb
Host smart-ff924bd1-85e3-41a1-8894-998c773487b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221401896 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.3221401896
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.2040822533
Short name T525
Test name
Test status
Simulation time 33692153 ps
CPU time 1.4 seconds
Started Jul 13 06:40:27 PM PDT 24
Finished Jul 13 06:40:29 PM PDT 24
Peak memory 218944 kb
Host smart-47e43b84-3fa0-4765-8985-9a8cd0c319ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040822533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.2040822533
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.3849715701
Short name T689
Test name
Test status
Simulation time 29572247 ps
CPU time 0.88 seconds
Started Jul 13 06:40:26 PM PDT 24
Finished Jul 13 06:40:28 PM PDT 24
Peak memory 216160 kb
Host smart-e578660b-3dee-44ff-bb19-aa47948993b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849715701 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.3849715701
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.1810479570
Short name T983
Test name
Test status
Simulation time 18064131 ps
CPU time 1.05 seconds
Started Jul 13 06:40:33 PM PDT 24
Finished Jul 13 06:40:36 PM PDT 24
Peak memory 215612 kb
Host smart-14d3fe96-12ba-4edd-b343-e38534c81d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810479570 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1810479570
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.3306475382
Short name T593
Test name
Test status
Simulation time 475349332 ps
CPU time 5.64 seconds
Started Jul 13 06:40:25 PM PDT 24
Finished Jul 13 06:40:31 PM PDT 24
Peak memory 215620 kb
Host smart-8871031b-8016-44bd-9679-b4d41fee8da9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306475382 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.3306475382
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.1167793779
Short name T442
Test name
Test status
Simulation time 53365190217 ps
CPU time 1353.58 seconds
Started Jul 13 06:40:25 PM PDT 24
Finished Jul 13 07:03:00 PM PDT 24
Peak memory 223920 kb
Host smart-d5d05a74-2ddf-4758-9e0c-865013341ab3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167793779 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.1167793779
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.2002058214
Short name T863
Test name
Test status
Simulation time 43917226 ps
CPU time 1.18 seconds
Started Jul 13 06:40:27 PM PDT 24
Finished Jul 13 06:40:29 PM PDT 24
Peak memory 220140 kb
Host smart-dd9d89b1-b6fb-4547-be08-4c9c497b5b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002058214 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.2002058214
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.1471313144
Short name T892
Test name
Test status
Simulation time 17397241 ps
CPU time 0.95 seconds
Started Jul 13 06:40:28 PM PDT 24
Finished Jul 13 06:40:31 PM PDT 24
Peak memory 215476 kb
Host smart-9630b9e3-3f58-4b63-9fb2-c89ca3c1136d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471313144 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1471313144
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.2079027618
Short name T213
Test name
Test status
Simulation time 45064268 ps
CPU time 0.89 seconds
Started Jul 13 06:40:25 PM PDT 24
Finished Jul 13 06:40:27 PM PDT 24
Peak memory 216488 kb
Host smart-4ed86e16-221d-4942-bece-76932584fcfe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079027618 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2079027618
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.2008939507
Short name T729
Test name
Test status
Simulation time 38430709 ps
CPU time 1.25 seconds
Started Jul 13 06:40:24 PM PDT 24
Finished Jul 13 06:40:26 PM PDT 24
Peak memory 217380 kb
Host smart-b58411bb-b945-4326-8290-4e44b903555c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008939507 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.2008939507
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_genbits.3859984761
Short name T45
Test name
Test status
Simulation time 55133182 ps
CPU time 1.91 seconds
Started Jul 13 06:40:24 PM PDT 24
Finished Jul 13 06:40:27 PM PDT 24
Peak memory 218908 kb
Host smart-62db5c78-5397-4825-9cbd-a72dd26f7b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859984761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.3859984761
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.3146403493
Short name T38
Test name
Test status
Simulation time 27856939 ps
CPU time 0.92 seconds
Started Jul 13 06:40:28 PM PDT 24
Finished Jul 13 06:40:31 PM PDT 24
Peak memory 216176 kb
Host smart-5d6627ae-c22e-4d3e-9d41-235d8b7a86f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146403493 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.3146403493
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.4078903829
Short name T396
Test name
Test status
Simulation time 16876030 ps
CPU time 1.04 seconds
Started Jul 13 06:40:27 PM PDT 24
Finished Jul 13 06:40:29 PM PDT 24
Peak memory 215592 kb
Host smart-0a01d0b4-0551-49c3-97ad-ce0465f129cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078903829 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.4078903829
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.2553103548
Short name T248
Test name
Test status
Simulation time 655038026 ps
CPU time 3.88 seconds
Started Jul 13 06:40:24 PM PDT 24
Finished Jul 13 06:40:28 PM PDT 24
Peak memory 217512 kb
Host smart-2deb1bc6-aea4-4622-87b6-c975c375dc85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553103548 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.2553103548
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1009249735
Short name T592
Test name
Test status
Simulation time 353221509051 ps
CPU time 2021 seconds
Started Jul 13 06:40:27 PM PDT 24
Finished Jul 13 07:14:09 PM PDT 24
Peak memory 227844 kb
Host smart-0b440f6d-2331-4472-9c93-f683e91662d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009249735 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.1009249735
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.4110911892
Short name T862
Test name
Test status
Simulation time 34112057 ps
CPU time 1.14 seconds
Started Jul 13 06:40:34 PM PDT 24
Finished Jul 13 06:40:36 PM PDT 24
Peak memory 218660 kb
Host smart-dfe03b6c-65f1-4875-83b2-d713d243b844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110911892 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.4110911892
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.3665547412
Short name T422
Test name
Test status
Simulation time 19424055 ps
CPU time 1.04 seconds
Started Jul 13 06:40:26 PM PDT 24
Finished Jul 13 06:40:28 PM PDT 24
Peak memory 207036 kb
Host smart-ea223806-389b-4e0d-a2d4-046bd6472ee0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665547412 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.3665547412
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.2322375752
Short name T188
Test name
Test status
Simulation time 35194411 ps
CPU time 0.83 seconds
Started Jul 13 06:40:28 PM PDT 24
Finished Jul 13 06:40:31 PM PDT 24
Peak memory 216528 kb
Host smart-e319749c-d254-48d7-bb84-0e19aa35818f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322375752 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.2322375752
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.1588924342
Short name T215
Test name
Test status
Simulation time 101322516 ps
CPU time 1.11 seconds
Started Jul 13 06:40:23 PM PDT 24
Finished Jul 13 06:40:25 PM PDT 24
Peak memory 217244 kb
Host smart-18abd1b5-6cd1-4d78-a565-49ecd8c4610f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588924342 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.1588924342
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.2542159761
Short name T676
Test name
Test status
Simulation time 44398906 ps
CPU time 1.22 seconds
Started Jul 13 06:40:29 PM PDT 24
Finished Jul 13 06:40:32 PM PDT 24
Peak memory 225812 kb
Host smart-4871ce6e-784e-48dd-b330-666f16a98043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542159761 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.2542159761
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.2439361227
Short name T826
Test name
Test status
Simulation time 28402112 ps
CPU time 1.31 seconds
Started Jul 13 06:40:25 PM PDT 24
Finished Jul 13 06:40:27 PM PDT 24
Peak memory 220200 kb
Host smart-6aa77361-9364-40bb-958b-d37064c6e531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439361227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.2439361227
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.4071455805
Short name T513
Test name
Test status
Simulation time 38934605 ps
CPU time 0.91 seconds
Started Jul 13 06:40:28 PM PDT 24
Finished Jul 13 06:40:31 PM PDT 24
Peak memory 215832 kb
Host smart-b4cfef94-4b05-439b-97d6-07287afc0602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071455805 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.4071455805
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.3297781255
Short name T517
Test name
Test status
Simulation time 79121089 ps
CPU time 0.92 seconds
Started Jul 13 06:40:28 PM PDT 24
Finished Jul 13 06:40:30 PM PDT 24
Peak memory 215596 kb
Host smart-3f239682-6bf3-4492-9891-bdb072439050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297781255 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3297781255
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.3940569228
Short name T991
Test name
Test status
Simulation time 102157659 ps
CPU time 2.39 seconds
Started Jul 13 06:40:28 PM PDT 24
Finished Jul 13 06:40:32 PM PDT 24
Peak memory 217480 kb
Host smart-39b45657-b324-46c3-9409-41e9c8bf08c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940569228 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.3940569228
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.405669111
Short name T809
Test name
Test status
Simulation time 109039315345 ps
CPU time 575.63 seconds
Started Jul 13 06:40:29 PM PDT 24
Finished Jul 13 06:50:07 PM PDT 24
Peak memory 219756 kb
Host smart-451cef58-a3c1-4d27-b25d-bd214a61554d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405669111 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.405669111
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.442908181
Short name T585
Test name
Test status
Simulation time 93351503 ps
CPU time 1.23 seconds
Started Jul 13 06:40:28 PM PDT 24
Finished Jul 13 06:40:31 PM PDT 24
Peak memory 221164 kb
Host smart-71ec3010-6503-43ea-9954-773249d64a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442908181 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.442908181
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.2935314276
Short name T75
Test name
Test status
Simulation time 13301654 ps
CPU time 0.91 seconds
Started Jul 13 06:40:27 PM PDT 24
Finished Jul 13 06:40:29 PM PDT 24
Peak memory 207256 kb
Host smart-14d871cf-7d7d-4187-805e-ce89288c547a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935314276 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2935314276
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.752168083
Short name T50
Test name
Test status
Simulation time 37422820 ps
CPU time 0.87 seconds
Started Jul 13 06:40:25 PM PDT 24
Finished Jul 13 06:40:27 PM PDT 24
Peak memory 216332 kb
Host smart-6e087f83-964e-4c22-9367-e0a6d198a834
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752168083 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.752168083
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1316333097
Short name T824
Test name
Test status
Simulation time 76453205 ps
CPU time 1.15 seconds
Started Jul 13 06:40:27 PM PDT 24
Finished Jul 13 06:40:30 PM PDT 24
Peak memory 217532 kb
Host smart-2c3da932-bc63-4693-ab0e-cc854e3bd355
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316333097 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1316333097
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.1791049785
Short name T77
Test name
Test status
Simulation time 43924868 ps
CPU time 1.1 seconds
Started Jul 13 06:40:24 PM PDT 24
Finished Jul 13 06:40:27 PM PDT 24
Peak memory 219820 kb
Host smart-ea6da001-4b76-4f5d-a5d5-f39e42604510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791049785 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.1791049785
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.3870224160
Short name T668
Test name
Test status
Simulation time 141068160 ps
CPU time 1.13 seconds
Started Jul 13 06:40:25 PM PDT 24
Finished Jul 13 06:40:27 PM PDT 24
Peak memory 217704 kb
Host smart-d2831946-d201-4c00-a65d-90506f2b1bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870224160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.3870224160
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.360249724
Short name T528
Test name
Test status
Simulation time 58676664 ps
CPU time 0.85 seconds
Started Jul 13 06:40:34 PM PDT 24
Finished Jul 13 06:40:36 PM PDT 24
Peak memory 215732 kb
Host smart-c1c45436-1dea-459f-99c0-3ded0513cc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360249724 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.360249724
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.2926255094
Short name T543
Test name
Test status
Simulation time 18332172 ps
CPU time 0.97 seconds
Started Jul 13 06:40:28 PM PDT 24
Finished Jul 13 06:40:31 PM PDT 24
Peak memory 215828 kb
Host smart-e78f2625-d2d9-41d2-b302-6c27565c3723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926255094 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2926255094
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.3249570499
Short name T879
Test name
Test status
Simulation time 337064905 ps
CPU time 3.98 seconds
Started Jul 13 06:40:23 PM PDT 24
Finished Jul 13 06:40:27 PM PDT 24
Peak memory 215620 kb
Host smart-daa76b3e-b8da-4d24-aceb-8a07fe6406bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249570499 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3249570499
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.1862187496
Short name T529
Test name
Test status
Simulation time 117906671510 ps
CPU time 722.06 seconds
Started Jul 13 06:40:24 PM PDT 24
Finished Jul 13 06:52:28 PM PDT 24
Peak memory 221768 kb
Host smart-9d646282-b6dc-4255-8374-2df5631e51fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862187496 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.1862187496
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.3576217937
Short name T815
Test name
Test status
Simulation time 29779594 ps
CPU time 1.34 seconds
Started Jul 13 06:40:34 PM PDT 24
Finished Jul 13 06:40:37 PM PDT 24
Peak memory 220020 kb
Host smart-3b30716f-c847-4054-a606-7c6b73fcc75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576217937 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.3576217937
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.2614290624
Short name T916
Test name
Test status
Simulation time 87282235 ps
CPU time 0.97 seconds
Started Jul 13 06:40:29 PM PDT 24
Finished Jul 13 06:40:32 PM PDT 24
Peak memory 207128 kb
Host smart-5de85058-9e2a-4273-a9db-8a1013e24c8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614290624 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.2614290624
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.2917313241
Short name T214
Test name
Test status
Simulation time 15967541 ps
CPU time 0.88 seconds
Started Jul 13 06:40:28 PM PDT 24
Finished Jul 13 06:40:31 PM PDT 24
Peak memory 216816 kb
Host smart-f1d9d9c7-4b4a-452f-87c1-5fd36be006bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917313241 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2917313241
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.2213327600
Short name T155
Test name
Test status
Simulation time 75957646 ps
CPU time 1.15 seconds
Started Jul 13 06:40:27 PM PDT 24
Finished Jul 13 06:40:30 PM PDT 24
Peak memory 217084 kb
Host smart-c9c4e9cc-ac5e-4db5-b9c6-3f14399f03f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213327600 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.2213327600
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.1763467140
Short name T128
Test name
Test status
Simulation time 21423733 ps
CPU time 1.2 seconds
Started Jul 13 06:40:28 PM PDT 24
Finished Jul 13 06:40:31 PM PDT 24
Peak memory 229880 kb
Host smart-7cbf6b6f-c6af-44b9-8f60-86d6e6e7e4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763467140 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.1763467140
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.1728209907
Short name T56
Test name
Test status
Simulation time 44816137 ps
CPU time 1.41 seconds
Started Jul 13 06:40:26 PM PDT 24
Finished Jul 13 06:40:28 PM PDT 24
Peak memory 218964 kb
Host smart-2f4ee3f6-a0b4-44d4-b49b-18a8ba8a4858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728209907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.1728209907
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.3576726973
Short name T511
Test name
Test status
Simulation time 25827050 ps
CPU time 0.99 seconds
Started Jul 13 06:40:27 PM PDT 24
Finished Jul 13 06:40:29 PM PDT 24
Peak memory 216088 kb
Host smart-35263326-4e5d-4f77-af53-e33ac5a6bff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576726973 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.3576726973
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.2338524227
Short name T885
Test name
Test status
Simulation time 38329816 ps
CPU time 1.33 seconds
Started Jul 13 06:40:29 PM PDT 24
Finished Jul 13 06:40:32 PM PDT 24
Peak memory 215612 kb
Host smart-69551aad-3930-42d9-a9db-62cb31895f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338524227 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.2338524227
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.916301350
Short name T550
Test name
Test status
Simulation time 327741844 ps
CPU time 3.01 seconds
Started Jul 13 06:40:24 PM PDT 24
Finished Jul 13 06:40:28 PM PDT 24
Peak memory 215684 kb
Host smart-91162ee0-d2ad-4eee-90de-9c5bf265cb88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916301350 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.916301350
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.1043432569
Short name T691
Test name
Test status
Simulation time 84568199424 ps
CPU time 997.45 seconds
Started Jul 13 06:40:27 PM PDT 24
Finished Jul 13 06:57:05 PM PDT 24
Peak memory 223992 kb
Host smart-a878baaf-6425-40ed-971d-92329c4a2cfc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043432569 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.1043432569
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.3390219462
Short name T438
Test name
Test status
Simulation time 23747069 ps
CPU time 1.19 seconds
Started Jul 13 06:40:28 PM PDT 24
Finished Jul 13 06:40:32 PM PDT 24
Peak memory 219096 kb
Host smart-615095c6-faa5-46a6-bd50-7610703c7a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390219462 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.3390219462
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.743899445
Short name T747
Test name
Test status
Simulation time 18744786 ps
CPU time 1.08 seconds
Started Jul 13 06:40:29 PM PDT 24
Finished Jul 13 06:40:32 PM PDT 24
Peak memory 207076 kb
Host smart-49085aa9-7de5-4b54-8832-987a6932d587
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743899445 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.743899445
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.3922551023
Short name T759
Test name
Test status
Simulation time 89919605 ps
CPU time 1.15 seconds
Started Jul 13 06:40:30 PM PDT 24
Finished Jul 13 06:40:34 PM PDT 24
Peak memory 218532 kb
Host smart-b5e3e4b7-d05f-4552-ac46-25ccf719a7a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922551023 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.3922551023
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.3546301594
Short name T449
Test name
Test status
Simulation time 19174629 ps
CPU time 1.14 seconds
Started Jul 13 06:40:27 PM PDT 24
Finished Jul 13 06:40:29 PM PDT 24
Peak memory 218936 kb
Host smart-24260577-8743-4a34-b22c-e033d45c008e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546301594 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.3546301594
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.4134862493
Short name T733
Test name
Test status
Simulation time 53212526 ps
CPU time 1.55 seconds
Started Jul 13 06:40:28 PM PDT 24
Finished Jul 13 06:40:32 PM PDT 24
Peak memory 219148 kb
Host smart-4d761370-7b87-4338-aeb8-36dd78934ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134862493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.4134862493
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.3812102299
Short name T101
Test name
Test status
Simulation time 31305157 ps
CPU time 1.01 seconds
Started Jul 13 06:40:29 PM PDT 24
Finished Jul 13 06:40:32 PM PDT 24
Peak memory 216164 kb
Host smart-70bd66c4-6afc-46a1-84b9-374782ad22eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812102299 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.3812102299
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.2830565641
Short name T890
Test name
Test status
Simulation time 19254317 ps
CPU time 1 seconds
Started Jul 13 06:40:28 PM PDT 24
Finished Jul 13 06:40:31 PM PDT 24
Peak memory 215592 kb
Host smart-6236b868-4632-428c-b516-0b51340f9cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830565641 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.2830565641
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1713412229
Short name T494
Test name
Test status
Simulation time 188801381 ps
CPU time 1.61 seconds
Started Jul 13 06:40:29 PM PDT 24
Finished Jul 13 06:40:33 PM PDT 24
Peak memory 215532 kb
Host smart-f33fefad-8303-42a9-92c7-c52dae910df2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713412229 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1713412229
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.2498919423
Short name T743
Test name
Test status
Simulation time 52570781462 ps
CPU time 621.27 seconds
Started Jul 13 06:40:32 PM PDT 24
Finished Jul 13 06:50:54 PM PDT 24
Peak memory 218916 kb
Host smart-14ce6b71-0082-4ce6-8d4f-ac36ae5bed50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498919423 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.2498919423
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.835416913
Short name T925
Test name
Test status
Simulation time 26089264 ps
CPU time 1.33 seconds
Started Jul 13 06:40:31 PM PDT 24
Finished Jul 13 06:40:34 PM PDT 24
Peak memory 220204 kb
Host smart-e83e919b-c5af-4b3f-b3e5-86ef4772a5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835416913 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.835416913
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.3085121826
Short name T382
Test name
Test status
Simulation time 22832669 ps
CPU time 0.87 seconds
Started Jul 13 06:40:31 PM PDT 24
Finished Jul 13 06:40:34 PM PDT 24
Peak memory 206808 kb
Host smart-a1e0bac9-a778-4c55-bca8-47a87f7b6c44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085121826 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.3085121826
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.1651019331
Short name T168
Test name
Test status
Simulation time 12918446 ps
CPU time 0.91 seconds
Started Jul 13 06:40:28 PM PDT 24
Finished Jul 13 06:40:31 PM PDT 24
Peak memory 215736 kb
Host smart-2637c3cb-fbc3-469a-8771-21a3e62635ae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651019331 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.1651019331
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.2433532274
Short name T163
Test name
Test status
Simulation time 40975855 ps
CPU time 1.34 seconds
Started Jul 13 06:40:31 PM PDT 24
Finished Jul 13 06:40:34 PM PDT 24
Peak memory 217280 kb
Host smart-6d98b43d-eddc-44c8-b119-feb76033d429
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433532274 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.2433532274
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.2161569965
Short name T386
Test name
Test status
Simulation time 71491920 ps
CPU time 1.04 seconds
Started Jul 13 06:40:31 PM PDT 24
Finished Jul 13 06:40:34 PM PDT 24
Peak memory 219024 kb
Host smart-8272edd7-5dea-43ea-aa3c-24bbab42f74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161569965 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.2161569965
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1148983896
Short name T367
Test name
Test status
Simulation time 48359299 ps
CPU time 1.25 seconds
Started Jul 13 06:40:31 PM PDT 24
Finished Jul 13 06:40:34 PM PDT 24
Peak memory 217676 kb
Host smart-a2da558e-a2df-46e8-ab49-edf29f690027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148983896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1148983896
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.3196990607
Short name T61
Test name
Test status
Simulation time 36203929 ps
CPU time 1.01 seconds
Started Jul 13 06:40:31 PM PDT 24
Finished Jul 13 06:40:34 PM PDT 24
Peak memory 224176 kb
Host smart-1cbf1eb8-bcc6-4af5-988d-82c2570ae57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196990607 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3196990607
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.648599111
Short name T353
Test name
Test status
Simulation time 15428693 ps
CPU time 1.05 seconds
Started Jul 13 06:40:30 PM PDT 24
Finished Jul 13 06:40:33 PM PDT 24
Peak memory 215612 kb
Host smart-9ad63272-b528-4ea6-ae30-39a5b7326244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648599111 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.648599111
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.1906238628
Short name T344
Test name
Test status
Simulation time 397966840 ps
CPU time 4.73 seconds
Started Jul 13 06:40:41 PM PDT 24
Finished Jul 13 06:40:46 PM PDT 24
Peak memory 215668 kb
Host smart-aa111e79-09d8-444c-9b73-0df1ea416457
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906238628 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1906238628
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.3114444730
Short name T240
Test name
Test status
Simulation time 217949902112 ps
CPU time 1181.5 seconds
Started Jul 13 06:40:30 PM PDT 24
Finished Jul 13 07:00:14 PM PDT 24
Peak memory 223492 kb
Host smart-6a2bb396-c76a-4f96-8a23-ae9e69c47c7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114444730 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.3114444730
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.1127757673
Short name T588
Test name
Test status
Simulation time 127741035 ps
CPU time 1.38 seconds
Started Jul 13 06:40:30 PM PDT 24
Finished Jul 13 06:40:34 PM PDT 24
Peak memory 216012 kb
Host smart-d887c32d-cc3a-478d-959d-17fd8e6fdaa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127757673 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.1127757673
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.3127460176
Short name T485
Test name
Test status
Simulation time 14331113 ps
CPU time 0.95 seconds
Started Jul 13 06:40:34 PM PDT 24
Finished Jul 13 06:40:37 PM PDT 24
Peak memory 207044 kb
Host smart-20e12c9c-469c-45c2-93c2-692efa4920dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127460176 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.3127460176
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.490721219
Short name T874
Test name
Test status
Simulation time 21128804 ps
CPU time 1.12 seconds
Started Jul 13 06:40:35 PM PDT 24
Finished Jul 13 06:40:38 PM PDT 24
Peak memory 219940 kb
Host smart-d95a53b4-3f27-4053-860c-b29a4bcafd8c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490721219 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.490721219
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.2706040832
Short name T889
Test name
Test status
Simulation time 126753080 ps
CPU time 1.26 seconds
Started Jul 13 06:40:33 PM PDT 24
Finished Jul 13 06:40:36 PM PDT 24
Peak memory 217240 kb
Host smart-dac8a869-7cda-4164-b073-3a57a96676d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706040832 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.2706040832
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.3372764479
Short name T7
Test name
Test status
Simulation time 21111145 ps
CPU time 1.24 seconds
Started Jul 13 06:40:35 PM PDT 24
Finished Jul 13 06:40:38 PM PDT 24
Peak memory 229788 kb
Host smart-7f412b45-0e4e-4929-870a-d296a646dbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372764479 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3372764479
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.3913968505
Short name T515
Test name
Test status
Simulation time 83654375 ps
CPU time 1.57 seconds
Started Jul 13 06:40:26 PM PDT 24
Finished Jul 13 06:40:28 PM PDT 24
Peak memory 220260 kb
Host smart-da0675e7-c605-4bb5-8818-08b581846537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913968505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3913968505
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.2796859149
Short name T717
Test name
Test status
Simulation time 21674389 ps
CPU time 1.12 seconds
Started Jul 13 06:40:32 PM PDT 24
Finished Jul 13 06:40:35 PM PDT 24
Peak memory 215956 kb
Host smart-b38d25cf-7276-487f-9f7d-a56347663a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796859149 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.2796859149
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.3530748400
Short name T394
Test name
Test status
Simulation time 27942163 ps
CPU time 0.94 seconds
Started Jul 13 06:40:26 PM PDT 24
Finished Jul 13 06:40:27 PM PDT 24
Peak memory 215532 kb
Host smart-27a56925-2b4d-436c-8603-01a3f0c948d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530748400 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.3530748400
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.3946994524
Short name T936
Test name
Test status
Simulation time 244329384 ps
CPU time 1.98 seconds
Started Jul 13 06:40:30 PM PDT 24
Finished Jul 13 06:40:34 PM PDT 24
Peak memory 220184 kb
Host smart-eaffbca1-ab30-4299-91c4-911f294b74b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946994524 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.3946994524
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.4177500215
Short name T82
Test name
Test status
Simulation time 18889958423 ps
CPU time 464.33 seconds
Started Jul 13 06:40:28 PM PDT 24
Finished Jul 13 06:48:14 PM PDT 24
Peak memory 224028 kb
Host smart-628c9552-cf7b-4ff4-bc5d-a9361dde7e96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177500215 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.4177500215
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.3450439582
Short name T736
Test name
Test status
Simulation time 147796803 ps
CPU time 1.16 seconds
Started Jul 13 06:40:33 PM PDT 24
Finished Jul 13 06:40:36 PM PDT 24
Peak memory 220024 kb
Host smart-73311fdc-8084-4f66-afee-376d2fd52a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450439582 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.3450439582
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.1920175696
Short name T573
Test name
Test status
Simulation time 15252857 ps
CPU time 0.92 seconds
Started Jul 13 06:40:33 PM PDT 24
Finished Jul 13 06:40:36 PM PDT 24
Peak memory 207036 kb
Host smart-0959a3c1-32ce-4523-a72d-fc65cbb56178
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920175696 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1920175696
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.2555954423
Short name T531
Test name
Test status
Simulation time 10944067 ps
CPU time 0.86 seconds
Started Jul 13 06:40:33 PM PDT 24
Finished Jul 13 06:40:36 PM PDT 24
Peak memory 216508 kb
Host smart-101eebe5-33b2-4a76-8275-90b400a3cb86
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555954423 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.2555954423
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.2463778825
Short name T148
Test name
Test status
Simulation time 193634170 ps
CPU time 1.15 seconds
Started Jul 13 06:40:33 PM PDT 24
Finished Jul 13 06:40:36 PM PDT 24
Peak memory 217292 kb
Host smart-24050c33-e2ec-47d2-aab3-44f910baf48d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463778825 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.2463778825
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.3619340996
Short name T933
Test name
Test status
Simulation time 43750227 ps
CPU time 0.98 seconds
Started Jul 13 06:40:35 PM PDT 24
Finished Jul 13 06:40:38 PM PDT 24
Peak memory 218796 kb
Host smart-f199b07c-bb98-4d49-8211-7f34b76dc135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619340996 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3619340996
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.3717910498
Short name T667
Test name
Test status
Simulation time 93967596 ps
CPU time 2.24 seconds
Started Jul 13 06:40:33 PM PDT 24
Finished Jul 13 06:40:37 PM PDT 24
Peak memory 220684 kb
Host smart-869c4fe5-9394-4c68-8cb3-ee3bc64fc4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717910498 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3717910498
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.3474522496
Short name T532
Test name
Test status
Simulation time 35913972 ps
CPU time 0.91 seconds
Started Jul 13 06:40:37 PM PDT 24
Finished Jul 13 06:40:40 PM PDT 24
Peak memory 215744 kb
Host smart-963455ad-4be5-44e7-a5d4-019717f6de16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474522496 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3474522496
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.3930248505
Short name T868
Test name
Test status
Simulation time 23351954 ps
CPU time 0.95 seconds
Started Jul 13 06:40:37 PM PDT 24
Finished Jul 13 06:40:39 PM PDT 24
Peak memory 215644 kb
Host smart-ad99ba8d-6add-40b7-90eb-a2afb7ebd09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930248505 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.3930248505
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.2164929953
Short name T76
Test name
Test status
Simulation time 219521468 ps
CPU time 1.46 seconds
Started Jul 13 06:40:37 PM PDT 24
Finished Jul 13 06:40:40 PM PDT 24
Peak memory 215548 kb
Host smart-f117c416-974d-406e-893e-dee313b32a3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164929953 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.2164929953
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.3076091011
Short name T252
Test name
Test status
Simulation time 49288629974 ps
CPU time 669.41 seconds
Started Jul 13 06:40:35 PM PDT 24
Finished Jul 13 06:51:46 PM PDT 24
Peak memory 219708 kb
Host smart-888d2876-ba0b-42c4-98cc-a357b261dd0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076091011 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.3076091011
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.2556083135
Short name T563
Test name
Test status
Simulation time 65450020 ps
CPU time 1.13 seconds
Started Jul 13 06:40:35 PM PDT 24
Finished Jul 13 06:40:38 PM PDT 24
Peak memory 220000 kb
Host smart-5e3e8d3c-104b-48d2-9640-22c418d81184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556083135 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.2556083135
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.2345852239
Short name T467
Test name
Test status
Simulation time 55323832 ps
CPU time 0.85 seconds
Started Jul 13 06:40:36 PM PDT 24
Finished Jul 13 06:40:39 PM PDT 24
Peak memory 206864 kb
Host smart-e7c3d548-ac36-4659-bab5-f06146af434d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345852239 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.2345852239
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.2987588122
Short name T174
Test name
Test status
Simulation time 26572523 ps
CPU time 0.84 seconds
Started Jul 13 06:40:36 PM PDT 24
Finished Jul 13 06:40:38 PM PDT 24
Peak memory 216540 kb
Host smart-0faefca5-b813-49d0-a9e7-30e1bcfd7007
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987588122 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2987588122
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.407181521
Short name T162
Test name
Test status
Simulation time 26188116 ps
CPU time 1.07 seconds
Started Jul 13 06:40:36 PM PDT 24
Finished Jul 13 06:40:39 PM PDT 24
Peak memory 217320 kb
Host smart-cb8ad067-5e1a-4265-b91a-75bcbf9f3671
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407181521 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_di
sable_auto_req_mode.407181521
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.3052418062
Short name T143
Test name
Test status
Simulation time 24156016 ps
CPU time 1.12 seconds
Started Jul 13 06:40:36 PM PDT 24
Finished Jul 13 06:40:39 PM PDT 24
Peak memory 229884 kb
Host smart-b492fefe-34b6-4d61-b344-372edb01f2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052418062 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3052418062
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.516345400
Short name T411
Test name
Test status
Simulation time 190904760 ps
CPU time 1.41 seconds
Started Jul 13 06:40:35 PM PDT 24
Finished Jul 13 06:40:38 PM PDT 24
Peak memory 217556 kb
Host smart-435bbf2c-5378-4eac-b129-68dc658fabce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516345400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.516345400
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.1566571543
Short name T31
Test name
Test status
Simulation time 25922082 ps
CPU time 0.94 seconds
Started Jul 13 06:40:32 PM PDT 24
Finished Jul 13 06:40:34 PM PDT 24
Peak memory 216032 kb
Host smart-dd8bf35a-5270-4125-9c47-be80631ca371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566571543 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.1566571543
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.3009970296
Short name T789
Test name
Test status
Simulation time 79360720 ps
CPU time 0.97 seconds
Started Jul 13 06:40:37 PM PDT 24
Finished Jul 13 06:40:40 PM PDT 24
Peak memory 215600 kb
Host smart-1d6a4c39-9fb0-4013-b9f9-03245d59c980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009970296 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.3009970296
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.2063981484
Short name T460
Test name
Test status
Simulation time 586402449 ps
CPU time 1.76 seconds
Started Jul 13 06:40:38 PM PDT 24
Finished Jul 13 06:40:41 PM PDT 24
Peak memory 215616 kb
Host smart-c84c1977-3254-4b07-8fed-7b4fe8cf4b65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063981484 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2063981484
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1062369612
Short name T797
Test name
Test status
Simulation time 85086425627 ps
CPU time 848.04 seconds
Started Jul 13 06:40:38 PM PDT 24
Finished Jul 13 06:54:47 PM PDT 24
Peak memory 222364 kb
Host smart-f90688cc-609c-498a-b118-dcc2387557e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062369612 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1062369612
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.3871582885
Short name T911
Test name
Test status
Simulation time 89658132 ps
CPU time 1.21 seconds
Started Jul 13 06:38:57 PM PDT 24
Finished Jul 13 06:38:59 PM PDT 24
Peak memory 218880 kb
Host smart-4bfb07eb-937f-499e-ae8c-3828745f48c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871582885 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3871582885
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.29684379
Short name T663
Test name
Test status
Simulation time 18364824 ps
CPU time 0.95 seconds
Started Jul 13 06:38:58 PM PDT 24
Finished Jul 13 06:39:01 PM PDT 24
Peak memory 207052 kb
Host smart-54baa326-b7bd-439b-92d3-eed6added71e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29684379 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.29684379
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.225843098
Short name T434
Test name
Test status
Simulation time 20626685 ps
CPU time 0.87 seconds
Started Jul 13 06:39:00 PM PDT 24
Finished Jul 13 06:39:02 PM PDT 24
Peak memory 215744 kb
Host smart-455ce3c9-1d00-44f3-92af-0b011f602ac6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225843098 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.225843098
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.2637423386
Short name T415
Test name
Test status
Simulation time 38693647 ps
CPU time 1.32 seconds
Started Jul 13 06:38:58 PM PDT 24
Finished Jul 13 06:39:00 PM PDT 24
Peak memory 219968 kb
Host smart-0560516d-17b2-49e2-b558-70af37d847e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637423386 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.2637423386
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.1911836969
Short name T35
Test name
Test status
Simulation time 18371542 ps
CPU time 1.01 seconds
Started Jul 13 06:38:59 PM PDT 24
Finished Jul 13 06:39:02 PM PDT 24
Peak memory 218492 kb
Host smart-6dfe82ee-fbc5-473d-bd22-e988cb4626c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911836969 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.1911836969
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.3435346501
Short name T548
Test name
Test status
Simulation time 91973584 ps
CPU time 1.56 seconds
Started Jul 13 06:39:01 PM PDT 24
Finished Jul 13 06:39:04 PM PDT 24
Peak memory 219152 kb
Host smart-f04fcdb2-2b3a-46a0-a8fb-042b0458daaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435346501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.3435346501
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.1613909702
Short name T718
Test name
Test status
Simulation time 50112878 ps
CPU time 0.98 seconds
Started Jul 13 06:38:59 PM PDT 24
Finished Jul 13 06:39:02 PM PDT 24
Peak memory 224012 kb
Host smart-c2610daa-826d-482e-b245-2017ed827977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613909702 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1613909702
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.353930760
Short name T28
Test name
Test status
Simulation time 138751605 ps
CPU time 1.02 seconds
Started Jul 13 06:38:58 PM PDT 24
Finished Jul 13 06:39:01 PM PDT 24
Peak memory 207680 kb
Host smart-66e04178-79be-4cc7-be9e-6abc8efbc8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353930760 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.353930760
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.762609927
Short name T600
Test name
Test status
Simulation time 14672789 ps
CPU time 0.95 seconds
Started Jul 13 06:39:01 PM PDT 24
Finished Jul 13 06:39:03 PM PDT 24
Peak memory 215568 kb
Host smart-b7ec227e-195b-4265-a928-159b084a9939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762609927 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.762609927
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.161253629
Short name T858
Test name
Test status
Simulation time 726494442 ps
CPU time 2.96 seconds
Started Jul 13 06:38:59 PM PDT 24
Finished Jul 13 06:39:04 PM PDT 24
Peak memory 217656 kb
Host smart-f541f2f1-581c-4c55-a4c5-abdb54c7bb5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161253629 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.161253629
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.2165333171
Short name T465
Test name
Test status
Simulation time 43335366017 ps
CPU time 583.74 seconds
Started Jul 13 06:39:02 PM PDT 24
Finished Jul 13 06:48:46 PM PDT 24
Peak memory 218936 kb
Host smart-dbb59705-fcb1-426d-912b-be24249f0409
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165333171 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.2165333171
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.3370541180
Short name T159
Test name
Test status
Simulation time 29938351 ps
CPU time 1.36 seconds
Started Jul 13 06:40:36 PM PDT 24
Finished Jul 13 06:40:39 PM PDT 24
Peak memory 220880 kb
Host smart-fda54917-2ff3-497c-a954-0b249afc8ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370541180 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.3370541180
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.1172008293
Short name T205
Test name
Test status
Simulation time 19662774 ps
CPU time 1.18 seconds
Started Jul 13 06:40:38 PM PDT 24
Finished Jul 13 06:40:40 PM PDT 24
Peak memory 229852 kb
Host smart-f2188b4c-8c1f-4791-876e-bb756f463e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172008293 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.1172008293
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.3048045035
Short name T638
Test name
Test status
Simulation time 52778693 ps
CPU time 1.19 seconds
Started Jul 13 06:40:36 PM PDT 24
Finished Jul 13 06:40:38 PM PDT 24
Peak memory 217548 kb
Host smart-75cb30aa-8c2a-4c60-b4c0-ae15ce11f765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048045035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.3048045035
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.3033338822
Short name T637
Test name
Test status
Simulation time 28180240 ps
CPU time 1.24 seconds
Started Jul 13 06:40:33 PM PDT 24
Finished Jul 13 06:40:36 PM PDT 24
Peak memory 219940 kb
Host smart-f6046f5e-4852-4da6-93a8-a005db2d9cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033338822 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.3033338822
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.33333827
Short name T469
Test name
Test status
Simulation time 21788863 ps
CPU time 0.98 seconds
Started Jul 13 06:40:33 PM PDT 24
Finished Jul 13 06:40:35 PM PDT 24
Peak memory 218808 kb
Host smart-05a25d39-d8b3-41c9-a8ba-51249528fa06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33333827 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.33333827
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.1000490777
Short name T719
Test name
Test status
Simulation time 53002125 ps
CPU time 1.62 seconds
Started Jul 13 06:40:38 PM PDT 24
Finished Jul 13 06:40:41 PM PDT 24
Peak memory 218676 kb
Host smart-a4be412e-ffa2-416e-a32d-f76280aa24fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000490777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.1000490777
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.3289928511
Short name T506
Test name
Test status
Simulation time 33388863 ps
CPU time 1.39 seconds
Started Jul 13 06:40:34 PM PDT 24
Finished Jul 13 06:40:37 PM PDT 24
Peak memory 216020 kb
Host smart-f072f789-8704-4ca1-bf43-50f6a93d4112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289928511 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.3289928511
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.3231650032
Short name T848
Test name
Test status
Simulation time 31591274 ps
CPU time 1.02 seconds
Started Jul 13 06:40:35 PM PDT 24
Finished Jul 13 06:40:38 PM PDT 24
Peak memory 220004 kb
Host smart-7996a892-dac7-481a-adce-ed0ad9218c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231650032 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.3231650032
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.399686610
Short name T664
Test name
Test status
Simulation time 37863790 ps
CPU time 1.42 seconds
Started Jul 13 06:40:35 PM PDT 24
Finished Jul 13 06:40:38 PM PDT 24
Peak memory 218968 kb
Host smart-cfa2be37-5716-4db4-9661-4e18634b99d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399686610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.399686610
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.2877195708
Short name T966
Test name
Test status
Simulation time 28758808 ps
CPU time 1.32 seconds
Started Jul 13 06:40:33 PM PDT 24
Finished Jul 13 06:40:36 PM PDT 24
Peak memory 219436 kb
Host smart-0ec824a2-b00d-4ddf-8869-4e3836dfa4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877195708 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.2877195708
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.3894693968
Short name T831
Test name
Test status
Simulation time 19010755 ps
CPU time 1.19 seconds
Started Jul 13 06:40:32 PM PDT 24
Finished Jul 13 06:40:35 PM PDT 24
Peak memory 224232 kb
Host smart-1ef9149d-8923-4371-ba5d-89d794393f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894693968 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.3894693968
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/54.edn_err.3899278004
Short name T524
Test name
Test status
Simulation time 21407951 ps
CPU time 0.9 seconds
Started Jul 13 06:40:34 PM PDT 24
Finished Jul 13 06:40:37 PM PDT 24
Peak memory 218744 kb
Host smart-646efe12-1d6d-4dd7-a593-5e9b7ff2461e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899278004 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.3899278004
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.153493191
Short name T483
Test name
Test status
Simulation time 54120722 ps
CPU time 2.02 seconds
Started Jul 13 06:40:33 PM PDT 24
Finished Jul 13 06:40:37 PM PDT 24
Peak memory 218652 kb
Host smart-3dcfbd6e-74f2-47b2-b756-d590cfd670ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153493191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.153493191
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.4227571221
Short name T707
Test name
Test status
Simulation time 55905196 ps
CPU time 1.1 seconds
Started Jul 13 06:40:38 PM PDT 24
Finished Jul 13 06:40:40 PM PDT 24
Peak memory 218952 kb
Host smart-65ba1913-7da9-48a7-b88b-829d5ba3a1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227571221 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.4227571221
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.1094252176
Short name T979
Test name
Test status
Simulation time 28619134 ps
CPU time 1.27 seconds
Started Jul 13 06:40:37 PM PDT 24
Finished Jul 13 06:40:40 PM PDT 24
Peak memory 216008 kb
Host smart-2fca1dee-6f94-4bfc-9331-7848f485955a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094252176 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.1094252176
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.1542098794
Short name T117
Test name
Test status
Simulation time 42515473 ps
CPU time 1.26 seconds
Started Jul 13 06:40:35 PM PDT 24
Finished Jul 13 06:40:38 PM PDT 24
Peak memory 219080 kb
Host smart-b7f74b03-7771-43e2-8623-11d1245f490a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542098794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.1542098794
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.913038832
Short name T229
Test name
Test status
Simulation time 65303776 ps
CPU time 1.15 seconds
Started Jul 13 06:40:38 PM PDT 24
Finished Jul 13 06:40:40 PM PDT 24
Peak memory 218716 kb
Host smart-35a93058-ee28-497a-8677-a644c396fbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913038832 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.913038832
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.1221015367
Short name T601
Test name
Test status
Simulation time 28969142 ps
CPU time 1.27 seconds
Started Jul 13 06:40:37 PM PDT 24
Finished Jul 13 06:40:40 PM PDT 24
Peak memory 220876 kb
Host smart-33ed7147-0b34-4b7c-b2b8-c4450ff7b129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221015367 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.1221015367
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.1737187576
Short name T947
Test name
Test status
Simulation time 44371512 ps
CPU time 1.66 seconds
Started Jul 13 06:40:35 PM PDT 24
Finished Jul 13 06:40:38 PM PDT 24
Peak memory 218932 kb
Host smart-80e230f8-4e0f-4dce-a85a-3ff1df94fde3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737187576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.1737187576
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.1363307792
Short name T1
Test name
Test status
Simulation time 89469737 ps
CPU time 1.12 seconds
Started Jul 13 06:40:40 PM PDT 24
Finished Jul 13 06:40:42 PM PDT 24
Peak memory 219548 kb
Host smart-d8bf278c-6005-456d-857c-09ed50dd9e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363307792 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.1363307792
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.336832049
Short name T212
Test name
Test status
Simulation time 19879103 ps
CPU time 1.08 seconds
Started Jul 13 06:40:43 PM PDT 24
Finished Jul 13 06:40:45 PM PDT 24
Peak memory 218796 kb
Host smart-001208a9-a36e-4b91-b717-5f5414afe51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336832049 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.336832049
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.2070020303
Short name T452
Test name
Test status
Simulation time 63222821 ps
CPU time 1.3 seconds
Started Jul 13 06:40:38 PM PDT 24
Finished Jul 13 06:40:40 PM PDT 24
Peak memory 217816 kb
Host smart-682f3a86-76df-43a5-8682-b5e4093c5b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070020303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2070020303
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.3351251877
Short name T602
Test name
Test status
Simulation time 27278850 ps
CPU time 1.27 seconds
Started Jul 13 06:40:41 PM PDT 24
Finished Jul 13 06:40:43 PM PDT 24
Peak memory 220052 kb
Host smart-9077a841-8eaa-441d-9208-d7b0c50735f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351251877 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.3351251877
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.146530106
Short name T197
Test name
Test status
Simulation time 28233447 ps
CPU time 0.9 seconds
Started Jul 13 06:40:44 PM PDT 24
Finished Jul 13 06:40:47 PM PDT 24
Peak memory 218520 kb
Host smart-d27a2059-d659-421a-bec3-68a5c0b64933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146530106 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.146530106
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.2004112354
Short name T335
Test name
Test status
Simulation time 109325562 ps
CPU time 1.43 seconds
Started Jul 13 06:40:42 PM PDT 24
Finished Jul 13 06:40:44 PM PDT 24
Peak memory 220332 kb
Host smart-fa380ba3-bbf6-4aff-bf4a-9290710d5d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004112354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.2004112354
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.2596834904
Short name T74
Test name
Test status
Simulation time 71922191 ps
CPU time 1.06 seconds
Started Jul 13 06:40:45 PM PDT 24
Finished Jul 13 06:40:48 PM PDT 24
Peak memory 218956 kb
Host smart-b4849c38-799f-4bdf-b7bf-df0f48ed4c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596834904 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.2596834904
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.1108621278
Short name T184
Test name
Test status
Simulation time 70793201 ps
CPU time 0.94 seconds
Started Jul 13 06:40:48 PM PDT 24
Finished Jul 13 06:40:49 PM PDT 24
Peak memory 224116 kb
Host smart-8e67684e-1f6e-4cab-9050-5925493d63c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108621278 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.1108621278
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.4291677948
Short name T793
Test name
Test status
Simulation time 33908049 ps
CPU time 1.38 seconds
Started Jul 13 06:40:41 PM PDT 24
Finished Jul 13 06:40:43 PM PDT 24
Peak memory 217488 kb
Host smart-6197847d-6706-4384-8c28-d0af712f2128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291677948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.4291677948
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.3262616285
Short name T300
Test name
Test status
Simulation time 29520100 ps
CPU time 1.32 seconds
Started Jul 13 06:39:12 PM PDT 24
Finished Jul 13 06:39:15 PM PDT 24
Peak memory 219716 kb
Host smart-5ad5ac99-ff97-43db-b3df-1bf412526559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262616285 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.3262616285
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.2040492583
Short name T453
Test name
Test status
Simulation time 19270130 ps
CPU time 0.87 seconds
Started Jul 13 06:39:09 PM PDT 24
Finished Jul 13 06:39:11 PM PDT 24
Peak memory 206964 kb
Host smart-92784c5e-87ba-4585-a6c4-beed19b2f9b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040492583 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.2040492583
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.2188208300
Short name T567
Test name
Test status
Simulation time 13629966 ps
CPU time 0.89 seconds
Started Jul 13 06:39:09 PM PDT 24
Finished Jul 13 06:39:12 PM PDT 24
Peak memory 216524 kb
Host smart-d392692e-4273-418d-8cb9-194629206b24
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188208300 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.2188208300
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.1689595526
Short name T255
Test name
Test status
Simulation time 364457085 ps
CPU time 1.15 seconds
Started Jul 13 06:39:08 PM PDT 24
Finished Jul 13 06:39:11 PM PDT 24
Peak memory 217328 kb
Host smart-d256f12d-a38d-4abd-b7f3-6243c51fcaf6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689595526 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.1689595526
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.3028213522
Short name T507
Test name
Test status
Simulation time 36196653 ps
CPU time 0.88 seconds
Started Jul 13 06:39:09 PM PDT 24
Finished Jul 13 06:39:12 PM PDT 24
Peak memory 218768 kb
Host smart-58e08251-c36a-46c9-838d-f0a994c8746a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028213522 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.3028213522
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.51777230
Short name T470
Test name
Test status
Simulation time 66770951 ps
CPU time 1.02 seconds
Started Jul 13 06:39:09 PM PDT 24
Finished Jul 13 06:39:11 PM PDT 24
Peak memory 217760 kb
Host smart-ce338c89-3ee5-4d40-98d6-45077967bbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51777230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.51777230
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.3549266675
Short name T745
Test name
Test status
Simulation time 24039543 ps
CPU time 0.94 seconds
Started Jul 13 06:39:07 PM PDT 24
Finished Jul 13 06:39:08 PM PDT 24
Peak memory 216036 kb
Host smart-2c318389-13e9-4ab6-86c1-1152ce47a94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549266675 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.3549266675
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.388006072
Short name T886
Test name
Test status
Simulation time 51107072 ps
CPU time 0.94 seconds
Started Jul 13 06:39:10 PM PDT 24
Finished Jul 13 06:39:13 PM PDT 24
Peak memory 207352 kb
Host smart-c6e11ca8-2714-4c2b-b1dc-594f743add33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388006072 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.388006072
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.707985877
Short name T671
Test name
Test status
Simulation time 22792032 ps
CPU time 0.9 seconds
Started Jul 13 06:38:59 PM PDT 24
Finished Jul 13 06:39:01 PM PDT 24
Peak memory 215632 kb
Host smart-d269cc87-f9bc-4f20-ae34-7831a2deab60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707985877 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.707985877
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.3476434167
Short name T980
Test name
Test status
Simulation time 288475280 ps
CPU time 5.72 seconds
Started Jul 13 06:39:12 PM PDT 24
Finished Jul 13 06:39:19 PM PDT 24
Peak memory 215648 kb
Host smart-edc9029f-1876-4398-b378-97bd38e31531
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476434167 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.3476434167
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/60.edn_alert.1284593822
Short name T58
Test name
Test status
Simulation time 27985495 ps
CPU time 1.32 seconds
Started Jul 13 06:40:44 PM PDT 24
Finished Jul 13 06:40:46 PM PDT 24
Peak memory 219032 kb
Host smart-bf92ea25-804a-4b3c-af52-21feca94c896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284593822 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.1284593822
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.1731935198
Short name T135
Test name
Test status
Simulation time 24493573 ps
CPU time 1.36 seconds
Started Jul 13 06:40:43 PM PDT 24
Finished Jul 13 06:40:45 PM PDT 24
Peak memory 229956 kb
Host smart-64fac8d1-dac8-432c-b836-0aeac13bb2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731935198 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1731935198
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.288383792
Short name T887
Test name
Test status
Simulation time 88586871 ps
CPU time 1.2 seconds
Started Jul 13 06:40:43 PM PDT 24
Finished Jul 13 06:40:46 PM PDT 24
Peak memory 220480 kb
Host smart-290c3ee8-cab8-454f-96c2-643870a947b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288383792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.288383792
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.3394062637
Short name T869
Test name
Test status
Simulation time 30260894 ps
CPU time 1.34 seconds
Started Jul 13 06:40:44 PM PDT 24
Finished Jul 13 06:40:46 PM PDT 24
Peak memory 219012 kb
Host smart-742206ca-c218-4666-ad98-4f802a8ecd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394062637 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.3394062637
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.1326783348
Short name T171
Test name
Test status
Simulation time 24632654 ps
CPU time 1.01 seconds
Started Jul 13 06:40:42 PM PDT 24
Finished Jul 13 06:40:44 PM PDT 24
Peak memory 224240 kb
Host smart-d7c09abd-d0aa-4b6b-b36f-1b2fb3082b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326783348 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1326783348
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.1641776882
Short name T705
Test name
Test status
Simulation time 39789844 ps
CPU time 1.73 seconds
Started Jul 13 06:40:43 PM PDT 24
Finished Jul 13 06:40:45 PM PDT 24
Peak memory 217600 kb
Host smart-d34cf2a8-dafc-43f8-b0f5-409e784ff1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641776882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.1641776882
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.3670756706
Short name T144
Test name
Test status
Simulation time 32812622 ps
CPU time 1.32 seconds
Started Jul 13 06:40:43 PM PDT 24
Finished Jul 13 06:40:45 PM PDT 24
Peak memory 220212 kb
Host smart-af04d25a-50b7-450c-ae36-5166661f18e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670756706 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.3670756706
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.2903864623
Short name T773
Test name
Test status
Simulation time 41666243 ps
CPU time 1.32 seconds
Started Jul 13 06:40:42 PM PDT 24
Finished Jul 13 06:40:45 PM PDT 24
Peak memory 219860 kb
Host smart-81ac10c5-2229-4111-9346-d5af2637654c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903864623 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.2903864623
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.1931269910
Short name T533
Test name
Test status
Simulation time 261166096 ps
CPU time 1.87 seconds
Started Jul 13 06:40:41 PM PDT 24
Finished Jul 13 06:40:43 PM PDT 24
Peak memory 219096 kb
Host smart-3bc181f0-8ae2-4819-84b9-2591f76c3813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931269910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.1931269910
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.1135870155
Short name T683
Test name
Test status
Simulation time 110701799 ps
CPU time 1.19 seconds
Started Jul 13 06:40:42 PM PDT 24
Finished Jul 13 06:40:44 PM PDT 24
Peak memory 218964 kb
Host smart-4144c760-bd3c-472d-91d5-6d928ddb4fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135870155 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.1135870155
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.903826926
Short name T457
Test name
Test status
Simulation time 18909214 ps
CPU time 1 seconds
Started Jul 13 06:40:42 PM PDT 24
Finished Jul 13 06:40:44 PM PDT 24
Peak memory 218400 kb
Host smart-94b4a08a-f32d-442c-ac3d-cc34a9a5bed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903826926 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.903826926
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.1128952601
Short name T409
Test name
Test status
Simulation time 61936954 ps
CPU time 1.21 seconds
Started Jul 13 06:40:44 PM PDT 24
Finished Jul 13 06:40:47 PM PDT 24
Peak memory 217780 kb
Host smart-e9c5504d-a6f5-4146-b160-2033507a0c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128952601 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.1128952601
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.2756414428
Short name T820
Test name
Test status
Simulation time 327315958 ps
CPU time 1.36 seconds
Started Jul 13 06:40:44 PM PDT 24
Finished Jul 13 06:40:47 PM PDT 24
Peak memory 219712 kb
Host smart-e68aebd4-aba1-4adf-adc2-fcc6e37bd753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756414428 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.2756414428
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.272941978
Short name T850
Test name
Test status
Simulation time 18839364 ps
CPU time 1.11 seconds
Started Jul 13 06:40:44 PM PDT 24
Finished Jul 13 06:40:48 PM PDT 24
Peak memory 218892 kb
Host smart-9007f543-8e6c-4a38-8341-25cc2d65bfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272941978 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.272941978
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.2337302377
Short name T429
Test name
Test status
Simulation time 229781859 ps
CPU time 1.46 seconds
Started Jul 13 06:40:45 PM PDT 24
Finished Jul 13 06:40:49 PM PDT 24
Peak memory 218764 kb
Host smart-65704d5c-b491-46f7-b676-f2b17b0e64e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337302377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2337302377
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.4204826143
Short name T768
Test name
Test status
Simulation time 63730723 ps
CPU time 1.09 seconds
Started Jul 13 06:40:43 PM PDT 24
Finished Jul 13 06:40:45 PM PDT 24
Peak memory 219080 kb
Host smart-7b8318e7-dc82-4751-a73b-0c1cf28bd3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204826143 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.4204826143
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.2241842303
Short name T653
Test name
Test status
Simulation time 138338070 ps
CPU time 1.18 seconds
Started Jul 13 06:40:45 PM PDT 24
Finished Jul 13 06:40:48 PM PDT 24
Peak memory 225772 kb
Host smart-75debec3-4d85-4472-82fd-26fd8689cee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241842303 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.2241842303
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.120838007
Short name T516
Test name
Test status
Simulation time 58862917 ps
CPU time 1.37 seconds
Started Jul 13 06:40:45 PM PDT 24
Finished Jul 13 06:40:49 PM PDT 24
Peak memory 218664 kb
Host smart-ebb0bdf5-15c8-45f4-9024-0dbc18b65d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120838007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.120838007
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.1907633818
Short name T720
Test name
Test status
Simulation time 72640427 ps
CPU time 1.09 seconds
Started Jul 13 06:40:43 PM PDT 24
Finished Jul 13 06:40:45 PM PDT 24
Peak memory 219156 kb
Host smart-4cfd06c5-cc5a-4ffa-8df1-91283c954870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907633818 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.1907633818
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.1150296070
Short name T172
Test name
Test status
Simulation time 34894252 ps
CPU time 0.97 seconds
Started Jul 13 06:40:48 PM PDT 24
Finished Jul 13 06:40:50 PM PDT 24
Peak memory 224092 kb
Host smart-10ba38f4-46df-4e62-9a96-256ceec27643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150296070 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1150296070
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.372280457
Short name T581
Test name
Test status
Simulation time 85580538 ps
CPU time 1.54 seconds
Started Jul 13 06:40:46 PM PDT 24
Finished Jul 13 06:40:49 PM PDT 24
Peak memory 219368 kb
Host smart-76342c09-71ce-42c3-a861-3ad5264e8fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372280457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.372280457
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.2539214343
Short name T628
Test name
Test status
Simulation time 43883618 ps
CPU time 1.23 seconds
Started Jul 13 06:40:44 PM PDT 24
Finished Jul 13 06:40:48 PM PDT 24
Peak memory 221080 kb
Host smart-bf911881-a72c-4c9e-8436-58f5fa096c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539214343 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.2539214343
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.3362857042
Short name T805
Test name
Test status
Simulation time 19508391 ps
CPU time 1.12 seconds
Started Jul 13 06:40:44 PM PDT 24
Finished Jul 13 06:40:47 PM PDT 24
Peak memory 218836 kb
Host smart-dd3b4baf-43b2-4dd2-869a-c3a16471bc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362857042 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.3362857042
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.3712959338
Short name T639
Test name
Test status
Simulation time 49747058 ps
CPU time 1.8 seconds
Started Jul 13 06:40:43 PM PDT 24
Finished Jul 13 06:40:46 PM PDT 24
Peak memory 218788 kb
Host smart-82e9a0b9-000d-4ddd-9157-91e292c2b7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712959338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3712959338
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.2984224298
Short name T942
Test name
Test status
Simulation time 84849619 ps
CPU time 1.34 seconds
Started Jul 13 06:40:49 PM PDT 24
Finished Jul 13 06:40:50 PM PDT 24
Peak memory 216012 kb
Host smart-ed2834e3-f266-4583-a505-f552054b8c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984224298 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.2984224298
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.2493148205
Short name T83
Test name
Test status
Simulation time 55306269 ps
CPU time 0.84 seconds
Started Jul 13 06:40:43 PM PDT 24
Finished Jul 13 06:40:44 PM PDT 24
Peak memory 219628 kb
Host smart-b02bc6c9-e4d2-48a6-829d-5453d9ef4612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493148205 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.2493148205
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.2936561325
Short name T630
Test name
Test status
Simulation time 65905559 ps
CPU time 1.09 seconds
Started Jul 13 06:40:44 PM PDT 24
Finished Jul 13 06:40:47 PM PDT 24
Peak memory 218988 kb
Host smart-8c3d738a-e64c-4126-8827-d5d0db2ccdc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936561325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.2936561325
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.2194826688
Short name T141
Test name
Test status
Simulation time 294020487 ps
CPU time 1.28 seconds
Started Jul 13 06:40:42 PM PDT 24
Finished Jul 13 06:40:44 PM PDT 24
Peak memory 219232 kb
Host smart-fd3b812d-b404-400a-9697-edee4b2d7f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194826688 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.2194826688
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_genbits.3017565971
Short name T780
Test name
Test status
Simulation time 45882390 ps
CPU time 1.15 seconds
Started Jul 13 06:40:49 PM PDT 24
Finished Jul 13 06:40:50 PM PDT 24
Peak memory 220260 kb
Host smart-6aea80f2-6fed-43b7-8270-b1465fc9110b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017565971 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.3017565971
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.928610990
Short name T647
Test name
Test status
Simulation time 46259151 ps
CPU time 1.2 seconds
Started Jul 13 06:39:08 PM PDT 24
Finished Jul 13 06:39:09 PM PDT 24
Peak memory 218956 kb
Host smart-1c472441-73e7-484b-a6d3-6c2946120568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928610990 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.928610990
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.185543057
Short name T25
Test name
Test status
Simulation time 48740850 ps
CPU time 0.94 seconds
Started Jul 13 06:39:09 PM PDT 24
Finished Jul 13 06:39:12 PM PDT 24
Peak memory 215428 kb
Host smart-cc1f2c28-d023-4fe1-b120-86993e9d2a3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185543057 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.185543057
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.1713735284
Short name T851
Test name
Test status
Simulation time 30940462 ps
CPU time 0.85 seconds
Started Jul 13 06:39:12 PM PDT 24
Finished Jul 13 06:39:14 PM PDT 24
Peak memory 216480 kb
Host smart-fe36acfa-19fd-46da-baad-ea09ee782de6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713735284 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.1713735284
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.4040507230
Short name T424
Test name
Test status
Simulation time 270967419 ps
CPU time 1.12 seconds
Started Jul 13 06:39:08 PM PDT 24
Finished Jul 13 06:39:11 PM PDT 24
Peak memory 217280 kb
Host smart-562c3cdc-9916-468a-bfd2-8c0d0d22746a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040507230 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.4040507230
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.2359257585
Short name T217
Test name
Test status
Simulation time 69241723 ps
CPU time 1.07 seconds
Started Jul 13 06:39:10 PM PDT 24
Finished Jul 13 06:39:14 PM PDT 24
Peak memory 220100 kb
Host smart-626482de-3852-45ec-90fb-3c969527b0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359257585 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.2359257585
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.821862884
Short name T512
Test name
Test status
Simulation time 41760827 ps
CPU time 1.26 seconds
Started Jul 13 06:39:09 PM PDT 24
Finished Jul 13 06:39:13 PM PDT 24
Peak memory 218892 kb
Host smart-665d7827-7998-472f-95a1-a1373321bb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821862884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.821862884
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.703296411
Short name T397
Test name
Test status
Simulation time 20801308 ps
CPU time 1.26 seconds
Started Jul 13 06:39:10 PM PDT 24
Finished Jul 13 06:39:14 PM PDT 24
Peak memory 224420 kb
Host smart-6c3b885c-3a24-46ee-912f-b127af38376c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703296411 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.703296411
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.1336957214
Short name T777
Test name
Test status
Simulation time 43060811 ps
CPU time 0.95 seconds
Started Jul 13 06:39:08 PM PDT 24
Finished Jul 13 06:39:09 PM PDT 24
Peak memory 207352 kb
Host smart-8590e56b-c606-4241-aefc-bb11fe72082a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336957214 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.1336957214
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.1522297928
Short name T680
Test name
Test status
Simulation time 45087726 ps
CPU time 1.02 seconds
Started Jul 13 06:39:08 PM PDT 24
Finished Jul 13 06:39:10 PM PDT 24
Peak memory 215632 kb
Host smart-cad9e5e6-fd0d-481c-8a07-24b2cb65a52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522297928 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1522297928
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.169540148
Short name T477
Test name
Test status
Simulation time 235049127 ps
CPU time 5.04 seconds
Started Jul 13 06:39:12 PM PDT 24
Finished Jul 13 06:39:18 PM PDT 24
Peak memory 220464 kb
Host smart-d85bf192-0a5d-436b-a354-5ca3c8f9757d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169540148 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.169540148
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2658058314
Short name T739
Test name
Test status
Simulation time 207581895815 ps
CPU time 2523.62 seconds
Started Jul 13 06:39:08 PM PDT 24
Finished Jul 13 07:21:13 PM PDT 24
Peak memory 232552 kb
Host smart-3cbf835e-a6a3-40bf-ab4e-5ef34726e9d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658058314 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.2658058314
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.2981064762
Short name T688
Test name
Test status
Simulation time 39696925 ps
CPU time 1.36 seconds
Started Jul 13 06:40:44 PM PDT 24
Finished Jul 13 06:40:48 PM PDT 24
Peak memory 215992 kb
Host smart-00a4779f-80e3-49b8-804b-89e5488bf999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981064762 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.2981064762
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.1858455266
Short name T161
Test name
Test status
Simulation time 26081726 ps
CPU time 1.17 seconds
Started Jul 13 06:40:49 PM PDT 24
Finished Jul 13 06:40:50 PM PDT 24
Peak memory 220896 kb
Host smart-36abd58b-4608-4fd5-a03a-cd7aa925457d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858455266 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.1858455266
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.3405676521
Short name T473
Test name
Test status
Simulation time 38905734 ps
CPU time 1.64 seconds
Started Jul 13 06:40:45 PM PDT 24
Finished Jul 13 06:40:49 PM PDT 24
Peak memory 218752 kb
Host smart-7c1570f2-3c16-4149-ac18-d0f46c4aec0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405676521 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3405676521
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.4140723830
Short name T998
Test name
Test status
Simulation time 23938156 ps
CPU time 1.23 seconds
Started Jul 13 06:40:44 PM PDT 24
Finished Jul 13 06:40:46 PM PDT 24
Peak memory 220052 kb
Host smart-65f49628-e2a1-468c-8ec0-ba3436731a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140723830 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.4140723830
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.1019156985
Short name T8
Test name
Test status
Simulation time 24164717 ps
CPU time 1.31 seconds
Started Jul 13 06:40:42 PM PDT 24
Finished Jul 13 06:40:44 PM PDT 24
Peak memory 229924 kb
Host smart-c528f495-fa88-4082-af67-444df9acfce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019156985 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.1019156985
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.859134352
Short name T582
Test name
Test status
Simulation time 51270517 ps
CPU time 1.65 seconds
Started Jul 13 06:40:45 PM PDT 24
Finished Jul 13 06:40:48 PM PDT 24
Peak memory 218644 kb
Host smart-3781392e-79cd-45d4-b48b-ac2a0c52208c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859134352 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.859134352
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.3799497518
Short name T318
Test name
Test status
Simulation time 25345506 ps
CPU time 1.19 seconds
Started Jul 13 06:40:44 PM PDT 24
Finished Jul 13 06:40:47 PM PDT 24
Peak memory 220248 kb
Host smart-8bcdf1a7-5967-4485-bcfa-d16f15a76e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799497518 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.3799497518
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.337111177
Short name T16
Test name
Test status
Simulation time 41050644 ps
CPU time 1 seconds
Started Jul 13 06:40:44 PM PDT 24
Finished Jul 13 06:40:47 PM PDT 24
Peak memory 224088 kb
Host smart-796cdc8f-c321-4786-a1dd-99b2622a62cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337111177 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.337111177
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.1414563786
Short name T564
Test name
Test status
Simulation time 44085098 ps
CPU time 1.07 seconds
Started Jul 13 06:40:45 PM PDT 24
Finished Jul 13 06:40:48 PM PDT 24
Peak memory 218720 kb
Host smart-fdf12c50-64fb-40df-8406-477a44f77fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414563786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.1414563786
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.2488694615
Short name T346
Test name
Test status
Simulation time 75724141 ps
CPU time 1.17 seconds
Started Jul 13 06:40:44 PM PDT 24
Finished Jul 13 06:40:47 PM PDT 24
Peak memory 219060 kb
Host smart-4cf93c0a-0252-479e-a0dc-50c933585d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488694615 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.2488694615
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.2663151690
Short name T129
Test name
Test status
Simulation time 29627245 ps
CPU time 0.96 seconds
Started Jul 13 06:40:45 PM PDT 24
Finished Jul 13 06:40:48 PM PDT 24
Peak memory 219940 kb
Host smart-8de94354-16a4-4458-b4e0-9fca9af7b9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663151690 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.2663151690
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.184890037
Short name T546
Test name
Test status
Simulation time 61919207 ps
CPU time 1.07 seconds
Started Jul 13 06:40:43 PM PDT 24
Finished Jul 13 06:40:46 PM PDT 24
Peak memory 217580 kb
Host smart-c9be8d31-22c7-493c-8fb9-b35339bf640a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184890037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.184890037
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.2075559478
Short name T182
Test name
Test status
Simulation time 51760699 ps
CPU time 1.31 seconds
Started Jul 13 06:40:47 PM PDT 24
Finished Jul 13 06:40:49 PM PDT 24
Peak memory 216008 kb
Host smart-259b85e5-2211-4932-8b36-dfb48c40b8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075559478 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.2075559478
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.2014779016
Short name T134
Test name
Test status
Simulation time 58231100 ps
CPU time 1.13 seconds
Started Jul 13 06:40:42 PM PDT 24
Finished Jul 13 06:40:43 PM PDT 24
Peak memory 229576 kb
Host smart-07c07f6d-ba90-40e2-b649-028788ad8193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014779016 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.2014779016
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.452324418
Short name T722
Test name
Test status
Simulation time 179098000 ps
CPU time 2.36 seconds
Started Jul 13 06:40:45 PM PDT 24
Finished Jul 13 06:40:49 PM PDT 24
Peak memory 220136 kb
Host smart-385d789b-c146-4a60-b551-8c9436bd8bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452324418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.452324418
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.3635099682
Short name T372
Test name
Test status
Simulation time 66287034 ps
CPU time 1.25 seconds
Started Jul 13 06:40:47 PM PDT 24
Finished Jul 13 06:40:49 PM PDT 24
Peak memory 219892 kb
Host smart-bdea5346-a3d3-4693-a988-9e866e3affb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635099682 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.3635099682
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.2292021856
Short name T165
Test name
Test status
Simulation time 30062129 ps
CPU time 0.98 seconds
Started Jul 13 06:40:53 PM PDT 24
Finished Jul 13 06:40:54 PM PDT 24
Peak memory 218772 kb
Host smart-9b9056a4-59fd-46d4-a94e-f5f3b9107455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292021856 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.2292021856
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.4189107600
Short name T404
Test name
Test status
Simulation time 46387956 ps
CPU time 1.42 seconds
Started Jul 13 06:40:47 PM PDT 24
Finished Jul 13 06:40:49 PM PDT 24
Peak memory 220008 kb
Host smart-98246006-0cc9-41ec-a1a5-a580c115bebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189107600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.4189107600
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.872237905
Short name T65
Test name
Test status
Simulation time 25993807 ps
CPU time 1.15 seconds
Started Jul 13 06:40:55 PM PDT 24
Finished Jul 13 06:40:57 PM PDT 24
Peak memory 219020 kb
Host smart-ea8f0ca3-09c4-4ef5-af0c-8010041bc35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872237905 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.872237905
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.2865888556
Short name T710
Test name
Test status
Simulation time 36403563 ps
CPU time 1.09 seconds
Started Jul 13 06:40:56 PM PDT 24
Finished Jul 13 06:40:57 PM PDT 24
Peak memory 219056 kb
Host smart-58a5f1d2-4167-4a2d-80cf-270bca90aaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865888556 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.2865888556
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.481580016
Short name T608
Test name
Test status
Simulation time 58477270 ps
CPU time 1.35 seconds
Started Jul 13 06:40:56 PM PDT 24
Finished Jul 13 06:40:57 PM PDT 24
Peak memory 219120 kb
Host smart-bbb6a183-3dbf-4fe0-bdac-83c736e239a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481580016 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.481580016
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.2726754173
Short name T654
Test name
Test status
Simulation time 94454401 ps
CPU time 1.17 seconds
Started Jul 13 06:40:56 PM PDT 24
Finished Jul 13 06:40:58 PM PDT 24
Peak memory 218920 kb
Host smart-1d6143cd-9b1e-4b85-8555-7ae39200515a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726754173 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.2726754173
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.621514926
Short name T177
Test name
Test status
Simulation time 33432095 ps
CPU time 1.05 seconds
Started Jul 13 06:40:55 PM PDT 24
Finished Jul 13 06:40:56 PM PDT 24
Peak memory 224240 kb
Host smart-d51ee529-e3ec-480a-943e-5e412ef7bd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621514926 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.621514926
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.3656129538
Short name T621
Test name
Test status
Simulation time 47729290 ps
CPU time 1.24 seconds
Started Jul 13 06:40:57 PM PDT 24
Finished Jul 13 06:40:58 PM PDT 24
Peak memory 219028 kb
Host smart-dcd79ddb-c178-4b5a-9e34-b3a5a00fe14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656129538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.3656129538
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.2431722564
Short name T964
Test name
Test status
Simulation time 26523366 ps
CPU time 1.29 seconds
Started Jul 13 06:40:53 PM PDT 24
Finished Jul 13 06:40:55 PM PDT 24
Peak memory 221088 kb
Host smart-62dc90ed-76c2-473a-8aa0-0020db620cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431722564 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.2431722564
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.2315899937
Short name T445
Test name
Test status
Simulation time 17930053 ps
CPU time 1.06 seconds
Started Jul 13 06:40:53 PM PDT 24
Finished Jul 13 06:40:55 PM PDT 24
Peak memory 218924 kb
Host smart-e4690244-27dd-4f95-9020-91982677c72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315899937 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2315899937
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.2858199656
Short name T626
Test name
Test status
Simulation time 184299818 ps
CPU time 1.06 seconds
Started Jul 13 06:40:55 PM PDT 24
Finished Jul 13 06:40:56 PM PDT 24
Peak memory 217688 kb
Host smart-c47c01e8-5336-4961-bff4-25aa44407db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858199656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.2858199656
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.2925757004
Short name T373
Test name
Test status
Simulation time 28432196 ps
CPU time 1.26 seconds
Started Jul 13 06:40:54 PM PDT 24
Finished Jul 13 06:40:56 PM PDT 24
Peak memory 220876 kb
Host smart-7b77cb33-f3a4-439e-94e4-d9bcef3d0f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925757004 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.2925757004
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.67078347
Short name T577
Test name
Test status
Simulation time 21244667 ps
CPU time 0.9 seconds
Started Jul 13 06:40:54 PM PDT 24
Finished Jul 13 06:40:56 PM PDT 24
Peak memory 218732 kb
Host smart-3a0b8e11-45b1-4b97-89fe-d7bc435043b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67078347 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.67078347
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.1946676184
Short name T734
Test name
Test status
Simulation time 110792366 ps
CPU time 2.19 seconds
Started Jul 13 06:40:54 PM PDT 24
Finished Jul 13 06:40:56 PM PDT 24
Peak memory 220176 kb
Host smart-611e1acc-b530-47c6-bae9-2b3eda4e2472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946676184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.1946676184
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.751505216
Short name T596
Test name
Test status
Simulation time 36949067 ps
CPU time 1.16 seconds
Started Jul 13 06:39:09 PM PDT 24
Finished Jul 13 06:39:13 PM PDT 24
Peak memory 219028 kb
Host smart-98d8333f-c1d7-4ec3-bd28-2c2d1cc34211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751505216 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.751505216
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.161235720
Short name T788
Test name
Test status
Simulation time 18903266 ps
CPU time 0.98 seconds
Started Jul 13 06:39:10 PM PDT 24
Finished Jul 13 06:39:14 PM PDT 24
Peak memory 207076 kb
Host smart-35df06ca-25a1-4963-af5d-bef95b22a73d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161235720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.161235720
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.2542965063
Short name T218
Test name
Test status
Simulation time 13225779 ps
CPU time 0.92 seconds
Started Jul 13 06:39:10 PM PDT 24
Finished Jul 13 06:39:13 PM PDT 24
Peak memory 216604 kb
Host smart-3105c1ca-d8ad-4103-bcb0-96578c94f492
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542965063 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.2542965063
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.2392928868
Short name T792
Test name
Test status
Simulation time 116660472 ps
CPU time 1.16 seconds
Started Jul 13 06:39:09 PM PDT 24
Finished Jul 13 06:39:13 PM PDT 24
Peak memory 217188 kb
Host smart-e2397573-605a-45ac-9da7-f55a75b43502
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392928868 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.2392928868
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.1019098083
Short name T520
Test name
Test status
Simulation time 21032043 ps
CPU time 1.01 seconds
Started Jul 13 06:39:08 PM PDT 24
Finished Jul 13 06:39:10 PM PDT 24
Peak memory 224352 kb
Host smart-2879e46a-3f0a-4799-ad62-1067aab14af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019098083 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.1019098083
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.1292369038
Short name T544
Test name
Test status
Simulation time 40298073 ps
CPU time 1.38 seconds
Started Jul 13 06:39:09 PM PDT 24
Finished Jul 13 06:39:12 PM PDT 24
Peak memory 220088 kb
Host smart-7733f480-4ff8-4d06-a36d-a3b888f8c33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292369038 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1292369038
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.4138831399
Short name T939
Test name
Test status
Simulation time 25978076 ps
CPU time 1.27 seconds
Started Jul 13 06:39:11 PM PDT 24
Finished Jul 13 06:39:15 PM PDT 24
Peak memory 224228 kb
Host smart-5a74a63a-5ddf-4622-8541-40383aca3871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138831399 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.4138831399
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.708298138
Short name T769
Test name
Test status
Simulation time 51618696 ps
CPU time 1 seconds
Started Jul 13 06:39:06 PM PDT 24
Finished Jul 13 06:39:07 PM PDT 24
Peak memory 207320 kb
Host smart-19712f85-588a-4d35-aa59-f1288da065ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708298138 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.708298138
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.3487595108
Short name T450
Test name
Test status
Simulation time 16089567 ps
CPU time 0.96 seconds
Started Jul 13 06:39:09 PM PDT 24
Finished Jul 13 06:39:12 PM PDT 24
Peak memory 215580 kb
Host smart-bc3b1835-d0d7-4c91-9950-21ef67f52af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487595108 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.3487595108
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.2081313712
Short name T750
Test name
Test status
Simulation time 315811499 ps
CPU time 6.24 seconds
Started Jul 13 06:39:09 PM PDT 24
Finished Jul 13 06:39:17 PM PDT 24
Peak memory 217524 kb
Host smart-e8fef366-e4d1-4075-ab80-742cde781002
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081313712 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.2081313712
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.2602736203
Short name T840
Test name
Test status
Simulation time 64519655211 ps
CPU time 1645.59 seconds
Started Jul 13 06:39:08 PM PDT 24
Finished Jul 13 07:06:35 PM PDT 24
Peak memory 226716 kb
Host smart-a8e3238c-2427-423a-997f-12ff7b9be2a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602736203 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.2602736203
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.2368843823
Short name T118
Test name
Test status
Simulation time 33508012 ps
CPU time 1.34 seconds
Started Jul 13 06:40:57 PM PDT 24
Finished Jul 13 06:40:58 PM PDT 24
Peak memory 215952 kb
Host smart-30c8e3af-d320-49d8-aa15-8325058ca5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368843823 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.2368843823
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.1699049766
Short name T644
Test name
Test status
Simulation time 19983558 ps
CPU time 1.1 seconds
Started Jul 13 06:40:54 PM PDT 24
Finished Jul 13 06:40:56 PM PDT 24
Peak memory 218924 kb
Host smart-42d68baf-f453-4822-8613-7501fd26e089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699049766 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.1699049766
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.2529811200
Short name T320
Test name
Test status
Simulation time 111507832 ps
CPU time 1.55 seconds
Started Jul 13 06:40:56 PM PDT 24
Finished Jul 13 06:40:58 PM PDT 24
Peak memory 219080 kb
Host smart-95b10340-c791-411d-94f7-59cf064854ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529811200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.2529811200
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.2590431908
Short name T740
Test name
Test status
Simulation time 29784058 ps
CPU time 1.26 seconds
Started Jul 13 06:41:08 PM PDT 24
Finished Jul 13 06:41:10 PM PDT 24
Peak memory 215996 kb
Host smart-18d72e67-66d4-4e43-bf70-6bc019223722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590431908 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.2590431908
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.3922994009
Short name T510
Test name
Test status
Simulation time 37824414 ps
CPU time 1.22 seconds
Started Jul 13 06:41:02 PM PDT 24
Finished Jul 13 06:41:04 PM PDT 24
Peak memory 219844 kb
Host smart-884f7844-80a0-46e0-ba94-0b06ffb87ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922994009 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.3922994009
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.2666333875
Short name T253
Test name
Test status
Simulation time 89756394 ps
CPU time 1.16 seconds
Started Jul 13 06:41:03 PM PDT 24
Finished Jul 13 06:41:05 PM PDT 24
Peak memory 217476 kb
Host smart-0b6be720-da2c-4d05-8be5-420a92cbe70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666333875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.2666333875
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.4164137066
Short name T926
Test name
Test status
Simulation time 120607570 ps
CPU time 1.21 seconds
Started Jul 13 06:41:03 PM PDT 24
Finished Jul 13 06:41:05 PM PDT 24
Peak memory 219788 kb
Host smart-2ef24bcd-22a4-4544-b904-c8e039b66a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164137066 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.4164137066
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.611780760
Short name T538
Test name
Test status
Simulation time 19253025 ps
CPU time 1.08 seconds
Started Jul 13 06:41:01 PM PDT 24
Finished Jul 13 06:41:03 PM PDT 24
Peak memory 220000 kb
Host smart-cfdec099-35de-41f7-bd2f-5e3c63c768d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611780760 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.611780760
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.1700288970
Short name T301
Test name
Test status
Simulation time 66276751 ps
CPU time 1.26 seconds
Started Jul 13 06:41:03 PM PDT 24
Finished Jul 13 06:41:05 PM PDT 24
Peak memory 219120 kb
Host smart-caaeb50c-dcde-400b-b99b-d54ff3abdbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700288970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.1700288970
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.647100726
Short name T614
Test name
Test status
Simulation time 46141800 ps
CPU time 1.19 seconds
Started Jul 13 06:41:08 PM PDT 24
Finished Jul 13 06:41:10 PM PDT 24
Peak memory 220108 kb
Host smart-296be54b-ee22-4a8c-9fa6-11e12d256435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647100726 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.647100726
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.658291634
Short name T627
Test name
Test status
Simulation time 107740614 ps
CPU time 1.08 seconds
Started Jul 13 06:41:06 PM PDT 24
Finished Jul 13 06:41:08 PM PDT 24
Peak memory 219948 kb
Host smart-2cbd4588-6956-4293-8af1-933c69bde4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658291634 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.658291634
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.1259311708
Short name T674
Test name
Test status
Simulation time 109653672 ps
CPU time 1.17 seconds
Started Jul 13 06:41:04 PM PDT 24
Finished Jul 13 06:41:07 PM PDT 24
Peak memory 218944 kb
Host smart-b1244f56-b8de-4b2e-97bc-ad85ffa60703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259311708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.1259311708
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.3262962394
Short name T227
Test name
Test status
Simulation time 49504256 ps
CPU time 1.29 seconds
Started Jul 13 06:41:04 PM PDT 24
Finished Jul 13 06:41:07 PM PDT 24
Peak memory 219356 kb
Host smart-81348d6e-df55-4f37-a717-a1ffdf348d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262962394 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.3262962394
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.2524806534
Short name T479
Test name
Test status
Simulation time 21469920 ps
CPU time 0.92 seconds
Started Jul 13 06:41:05 PM PDT 24
Finished Jul 13 06:41:07 PM PDT 24
Peak memory 215808 kb
Host smart-8cfd6fb3-04e3-4e33-b59c-9657a7dc56dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524806534 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.2524806534
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.828032632
Short name T385
Test name
Test status
Simulation time 45896651 ps
CPU time 1.21 seconds
Started Jul 13 06:41:02 PM PDT 24
Finished Jul 13 06:41:03 PM PDT 24
Peak memory 218764 kb
Host smart-615a33c5-cc38-425c-8df3-bd9102fc9dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828032632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.828032632
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.3156062032
Short name T132
Test name
Test status
Simulation time 31200025 ps
CPU time 1.37 seconds
Started Jul 13 06:41:07 PM PDT 24
Finished Jul 13 06:41:09 PM PDT 24
Peak memory 220236 kb
Host smart-76ee4a45-f9ef-4d47-ba24-336c52595b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156062032 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.3156062032
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.150861667
Short name T178
Test name
Test status
Simulation time 23338773 ps
CPU time 0.97 seconds
Started Jul 13 06:41:03 PM PDT 24
Finished Jul 13 06:41:06 PM PDT 24
Peak memory 219076 kb
Host smart-f26b0002-102f-40be-a844-574e1182d07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150861667 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.150861667
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.1880141759
Short name T633
Test name
Test status
Simulation time 70355993 ps
CPU time 2.26 seconds
Started Jul 13 06:41:02 PM PDT 24
Finished Jul 13 06:41:04 PM PDT 24
Peak memory 220440 kb
Host smart-2c510e40-983b-4c47-8347-0c8672aedb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880141759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.1880141759
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.1516944350
Short name T153
Test name
Test status
Simulation time 28929288 ps
CPU time 1.29 seconds
Started Jul 13 06:41:05 PM PDT 24
Finished Jul 13 06:41:08 PM PDT 24
Peak memory 218724 kb
Host smart-8e6a8d44-743c-4d28-95a8-4dc23a48b07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516944350 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.1516944350
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.879465807
Short name T193
Test name
Test status
Simulation time 19635690 ps
CPU time 1.08 seconds
Started Jul 13 06:41:03 PM PDT 24
Finished Jul 13 06:41:06 PM PDT 24
Peak memory 218788 kb
Host smart-27c21d64-557b-4cd7-829c-62f951df81bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879465807 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.879465807
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.3883371127
Short name T648
Test name
Test status
Simulation time 92541751 ps
CPU time 1.53 seconds
Started Jul 13 06:41:03 PM PDT 24
Finished Jul 13 06:41:06 PM PDT 24
Peak memory 218988 kb
Host smart-cb6e9836-de88-4ff0-af66-fd03d158b727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883371127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3883371127
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.324060910
Short name T194
Test name
Test status
Simulation time 71240895 ps
CPU time 1.15 seconds
Started Jul 13 06:41:04 PM PDT 24
Finished Jul 13 06:41:06 PM PDT 24
Peak memory 220044 kb
Host smart-5702a6a0-4904-423f-989a-b7cd7a444476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324060910 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.324060910
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.1604405475
Short name T151
Test name
Test status
Simulation time 27164031 ps
CPU time 1.34 seconds
Started Jul 13 06:41:02 PM PDT 24
Finished Jul 13 06:41:04 PM PDT 24
Peak memory 232428 kb
Host smart-939796c4-dc07-4d5f-8640-3cbda612b509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604405475 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.1604405475
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/88.edn_alert.1614333313
Short name T534
Test name
Test status
Simulation time 40584041 ps
CPU time 1.42 seconds
Started Jul 13 06:41:07 PM PDT 24
Finished Jul 13 06:41:09 PM PDT 24
Peak memory 216084 kb
Host smart-396717f8-3490-48f7-a761-48cc84d6ca9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614333313 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.1614333313
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.2041868956
Short name T744
Test name
Test status
Simulation time 19915058 ps
CPU time 1.09 seconds
Started Jul 13 06:41:03 PM PDT 24
Finished Jul 13 06:41:05 PM PDT 24
Peak memory 218976 kb
Host smart-6f8f7b6c-5526-4493-8616-af6a220b895b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041868956 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.2041868956
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.3894539230
Short name T981
Test name
Test status
Simulation time 384564823 ps
CPU time 3.41 seconds
Started Jul 13 06:41:09 PM PDT 24
Finished Jul 13 06:41:13 PM PDT 24
Peak memory 218928 kb
Host smart-349c0941-5a54-4a4e-9c20-ebab22215720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894539230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.3894539230
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.3738992261
Short name T246
Test name
Test status
Simulation time 101699073 ps
CPU time 1.27 seconds
Started Jul 13 06:41:03 PM PDT 24
Finished Jul 13 06:41:06 PM PDT 24
Peak memory 220036 kb
Host smart-46602c50-9efe-44fe-b970-da60bad1ac8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738992261 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.3738992261
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.1340265261
Short name T378
Test name
Test status
Simulation time 30990762 ps
CPU time 1.04 seconds
Started Jul 13 06:41:05 PM PDT 24
Finished Jul 13 06:41:08 PM PDT 24
Peak memory 218816 kb
Host smart-66bad023-2118-4f5b-bfd9-67751d612a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340265261 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.1340265261
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.1456029447
Short name T590
Test name
Test status
Simulation time 265384458 ps
CPU time 1.12 seconds
Started Jul 13 06:41:06 PM PDT 24
Finished Jul 13 06:41:08 PM PDT 24
Peak memory 217672 kb
Host smart-8a43e3d9-02d2-48be-aa0f-be0aefa1deaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456029447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.1456029447
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.1273220880
Short name T895
Test name
Test status
Simulation time 24179615 ps
CPU time 1.19 seconds
Started Jul 13 06:39:08 PM PDT 24
Finished Jul 13 06:39:10 PM PDT 24
Peak memory 218836 kb
Host smart-36121b0e-3a4f-4e79-b515-90f9b4e35308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273220880 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1273220880
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.1040748731
Short name T806
Test name
Test status
Simulation time 22631236 ps
CPU time 0.84 seconds
Started Jul 13 06:39:08 PM PDT 24
Finished Jul 13 06:39:10 PM PDT 24
Peak memory 206760 kb
Host smart-22d29861-4bbc-425f-aaf9-04d315835a6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040748731 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1040748731
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.3714379059
Short name T209
Test name
Test status
Simulation time 14584927 ps
CPU time 0.93 seconds
Started Jul 13 06:39:09 PM PDT 24
Finished Jul 13 06:39:12 PM PDT 24
Peak memory 216760 kb
Host smart-fdbaae8e-d31f-42e1-b13b-cf7c58dae659
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714379059 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.3714379059
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.3699744340
Short name T147
Test name
Test status
Simulation time 71743892 ps
CPU time 1.07 seconds
Started Jul 13 06:39:10 PM PDT 24
Finished Jul 13 06:39:13 PM PDT 24
Peak memory 220100 kb
Host smart-430145fe-8bc3-43ec-afbd-fd487bc85609
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699744340 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.3699744340
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.1347023491
Short name T547
Test name
Test status
Simulation time 19784027 ps
CPU time 1.14 seconds
Started Jul 13 06:39:09 PM PDT 24
Finished Jul 13 06:39:12 PM PDT 24
Peak memory 218852 kb
Host smart-f2c07777-fef0-4f08-b31b-1156a667a815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347023491 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1347023491
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.2236787491
Short name T433
Test name
Test status
Simulation time 52103707 ps
CPU time 2.05 seconds
Started Jul 13 06:39:07 PM PDT 24
Finished Jul 13 06:39:09 PM PDT 24
Peak memory 217792 kb
Host smart-70c1e275-97c7-4978-9460-b27bfefe1039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236787491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.2236787491
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2163473822
Short name T922
Test name
Test status
Simulation time 21448005 ps
CPU time 1.08 seconds
Started Jul 13 06:39:12 PM PDT 24
Finished Jul 13 06:39:15 PM PDT 24
Peak memory 216120 kb
Host smart-1fad8b71-6ba8-4cbd-8734-d928a53e1b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163473822 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2163473822
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.877631377
Short name T799
Test name
Test status
Simulation time 18648103 ps
CPU time 1.04 seconds
Started Jul 13 06:39:10 PM PDT 24
Finished Jul 13 06:39:13 PM PDT 24
Peak memory 207512 kb
Host smart-01bdb4d1-3ac2-420b-8978-c84ed8eb2221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877631377 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.877631377
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.69234437
Short name T557
Test name
Test status
Simulation time 38055336 ps
CPU time 0.86 seconds
Started Jul 13 06:39:10 PM PDT 24
Finished Jul 13 06:39:13 PM PDT 24
Peak memory 215576 kb
Host smart-a0ef8c2e-00a8-4dc0-b123-7060a1384b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69234437 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.69234437
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.2125410971
Short name T673
Test name
Test status
Simulation time 368504226 ps
CPU time 3.8 seconds
Started Jul 13 06:39:09 PM PDT 24
Finished Jul 13 06:39:15 PM PDT 24
Peak memory 217616 kb
Host smart-d579993e-44cd-4004-9f31-da9df25d95c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125410971 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2125410971
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.2253213060
Short name T790
Test name
Test status
Simulation time 176928006427 ps
CPU time 1180.66 seconds
Started Jul 13 06:39:08 PM PDT 24
Finished Jul 13 06:58:50 PM PDT 24
Peak memory 224100 kb
Host smart-1322824b-5731-4ff6-94f4-67fda4c3982c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253213060 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.2253213060
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.4095775951
Short name T617
Test name
Test status
Simulation time 46376343 ps
CPU time 1.17 seconds
Started Jul 13 06:41:05 PM PDT 24
Finished Jul 13 06:41:07 PM PDT 24
Peak memory 219956 kb
Host smart-9292e611-3e95-4f12-9527-d605c2902e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095775951 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.4095775951
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.957558856
Short name T968
Test name
Test status
Simulation time 46056873 ps
CPU time 1.05 seconds
Started Jul 13 06:41:05 PM PDT 24
Finished Jul 13 06:41:08 PM PDT 24
Peak memory 218644 kb
Host smart-163edb35-f2d4-42a3-beba-ceb8a6ef7b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957558856 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.957558856
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.3873976434
Short name T865
Test name
Test status
Simulation time 63338825 ps
CPU time 2.2 seconds
Started Jul 13 06:41:05 PM PDT 24
Finished Jul 13 06:41:08 PM PDT 24
Peak memory 218952 kb
Host smart-b0f876f4-0ab7-4d3c-be12-47b5d42304ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873976434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3873976434
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.2916705011
Short name T969
Test name
Test status
Simulation time 227039952 ps
CPU time 1.25 seconds
Started Jul 13 06:41:06 PM PDT 24
Finished Jul 13 06:41:08 PM PDT 24
Peak memory 220000 kb
Host smart-f4998734-460d-48e2-8c65-5040f10872a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916705011 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.2916705011
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.2867849799
Short name T697
Test name
Test status
Simulation time 22117657 ps
CPU time 0.95 seconds
Started Jul 13 06:41:05 PM PDT 24
Finished Jul 13 06:41:07 PM PDT 24
Peak memory 219896 kb
Host smart-28797868-06d9-4257-85c2-ef10464419a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867849799 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.2867849799
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.3025688822
Short name T841
Test name
Test status
Simulation time 50638516 ps
CPU time 1.46 seconds
Started Jul 13 06:41:03 PM PDT 24
Finished Jul 13 06:41:06 PM PDT 24
Peak memory 218948 kb
Host smart-c30ebb98-60c5-4aa6-a52b-7417b9f99385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025688822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.3025688822
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.3177122060
Short name T316
Test name
Test status
Simulation time 30460789 ps
CPU time 1.17 seconds
Started Jul 13 06:41:02 PM PDT 24
Finished Jul 13 06:41:04 PM PDT 24
Peak memory 220208 kb
Host smart-abe1402d-c864-4885-9c84-09bc1cae608d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177122060 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.3177122060
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.2825752600
Short name T738
Test name
Test status
Simulation time 59527951 ps
CPU time 1.03 seconds
Started Jul 13 06:41:06 PM PDT 24
Finished Jul 13 06:41:08 PM PDT 24
Peak memory 221160 kb
Host smart-2ee1385e-106f-4a89-8633-372a8452bc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825752600 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.2825752600
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3316527489
Short name T398
Test name
Test status
Simulation time 224168781 ps
CPU time 3.2 seconds
Started Jul 13 06:41:02 PM PDT 24
Finished Jul 13 06:41:07 PM PDT 24
Peak memory 217932 kb
Host smart-bee7ad55-8438-43f3-be27-b6b617fa1e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316527489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3316527489
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.2315891893
Short name T292
Test name
Test status
Simulation time 91123319 ps
CPU time 1.18 seconds
Started Jul 13 06:41:00 PM PDT 24
Finished Jul 13 06:41:01 PM PDT 24
Peak memory 218712 kb
Host smart-3da53a76-7539-433a-97e8-eb130b231d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315891893 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.2315891893
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.3247965666
Short name T530
Test name
Test status
Simulation time 27983207 ps
CPU time 0.86 seconds
Started Jul 13 06:41:05 PM PDT 24
Finished Jul 13 06:41:07 PM PDT 24
Peak memory 218408 kb
Host smart-abeb0b27-e873-426e-bce2-a63caee8c129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247965666 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3247965666
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.1158666957
Short name T14
Test name
Test status
Simulation time 183704601 ps
CPU time 1.24 seconds
Started Jul 13 06:41:08 PM PDT 24
Finished Jul 13 06:41:10 PM PDT 24
Peak memory 218908 kb
Host smart-78ae4bcb-0e4b-44ed-b84f-976f7ac5a592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158666957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.1158666957
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.2171086965
Short name T952
Test name
Test status
Simulation time 33222470 ps
CPU time 1.22 seconds
Started Jul 13 06:41:04 PM PDT 24
Finished Jul 13 06:41:06 PM PDT 24
Peak memory 215992 kb
Host smart-4e0ba09c-c6c0-418b-a398-71d91c17bc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171086965 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.2171086965
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.2281362166
Short name T383
Test name
Test status
Simulation time 19823372 ps
CPU time 1.07 seconds
Started Jul 13 06:41:04 PM PDT 24
Finished Jul 13 06:41:07 PM PDT 24
Peak memory 220104 kb
Host smart-e34aeab4-bdc9-4fe0-918e-882b720c163d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281362166 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.2281362166
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.1737117847
Short name T795
Test name
Test status
Simulation time 69081036 ps
CPU time 1.32 seconds
Started Jul 13 06:41:04 PM PDT 24
Finished Jul 13 06:41:07 PM PDT 24
Peak memory 218824 kb
Host smart-d43de18f-3406-4af6-b32e-3aaad77712f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737117847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.1737117847
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.30024770
Short name T855
Test name
Test status
Simulation time 54137031 ps
CPU time 1.22 seconds
Started Jul 13 06:41:07 PM PDT 24
Finished Jul 13 06:41:09 PM PDT 24
Peak memory 220068 kb
Host smart-948f936c-08ab-42cd-8cc2-28aacd2015a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30024770 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.30024770
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.2516385080
Short name T198
Test name
Test status
Simulation time 19908930 ps
CPU time 1.08 seconds
Started Jul 13 06:41:03 PM PDT 24
Finished Jul 13 06:41:05 PM PDT 24
Peak memory 218664 kb
Host smart-7f3019d4-0266-492f-bdf5-697e3ec533da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516385080 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2516385080
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.882331925
Short name T954
Test name
Test status
Simulation time 44677576 ps
CPU time 1.52 seconds
Started Jul 13 06:41:08 PM PDT 24
Finished Jul 13 06:41:10 PM PDT 24
Peak memory 218980 kb
Host smart-53928cd1-403a-4284-8dbe-def13b94fb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882331925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.882331925
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.252822291
Short name T775
Test name
Test status
Simulation time 112221520 ps
CPU time 1.21 seconds
Started Jul 13 06:41:03 PM PDT 24
Finished Jul 13 06:41:05 PM PDT 24
Peak memory 219080 kb
Host smart-52697361-921e-486f-8d89-f0bda2afaa26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252822291 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.252822291
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.2263950766
Short name T222
Test name
Test status
Simulation time 30617791 ps
CPU time 1.05 seconds
Started Jul 13 06:41:02 PM PDT 24
Finished Jul 13 06:41:05 PM PDT 24
Peak memory 224392 kb
Host smart-e2c4a260-48d9-4b6a-be2d-874922fa223f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263950766 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.2263950766
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.708683730
Short name T783
Test name
Test status
Simulation time 46683614 ps
CPU time 1.28 seconds
Started Jul 13 06:41:05 PM PDT 24
Finished Jul 13 06:41:07 PM PDT 24
Peak memory 218812 kb
Host smart-17500e15-09b0-4f9c-b797-422a229a41b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708683730 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.708683730
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.1619077789
Short name T703
Test name
Test status
Simulation time 26549464 ps
CPU time 1.27 seconds
Started Jul 13 06:41:02 PM PDT 24
Finished Jul 13 06:41:04 PM PDT 24
Peak memory 219812 kb
Host smart-585de65e-e2bf-4d01-b9a5-ec0ed920f535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619077789 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.1619077789
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.186279702
Short name T59
Test name
Test status
Simulation time 20445354 ps
CPU time 1.13 seconds
Started Jul 13 06:41:02 PM PDT 24
Finished Jul 13 06:41:05 PM PDT 24
Peak memory 224380 kb
Host smart-8dfdd4e8-64c0-485d-a1e5-20ef0d552ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186279702 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.186279702
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.295101232
Short name T956
Test name
Test status
Simulation time 64249051 ps
CPU time 1.22 seconds
Started Jul 13 06:41:02 PM PDT 24
Finished Jul 13 06:41:04 PM PDT 24
Peak memory 218740 kb
Host smart-a773f6e2-e47a-44b1-b356-aef2a432bed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295101232 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.295101232
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.4077003820
Short name T900
Test name
Test status
Simulation time 121290154 ps
CPU time 1.25 seconds
Started Jul 13 06:41:18 PM PDT 24
Finished Jul 13 06:41:21 PM PDT 24
Peak memory 220052 kb
Host smart-54a66320-5af8-425d-8ffb-533b70512c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077003820 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.4077003820
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2049967966
Short name T891
Test name
Test status
Simulation time 52292831 ps
CPU time 1.32 seconds
Started Jul 13 06:41:13 PM PDT 24
Finished Jul 13 06:41:15 PM PDT 24
Peak memory 218956 kb
Host smart-cf9f19fd-5fac-4c2e-8ae9-9c2d65114964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049967966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2049967966
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.2128430971
Short name T867
Test name
Test status
Simulation time 25573429 ps
CPU time 1.18 seconds
Started Jul 13 06:41:13 PM PDT 24
Finished Jul 13 06:41:15 PM PDT 24
Peak memory 218820 kb
Host smart-d9428f23-4e55-4b41-a0bb-61fb565bcfb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128430971 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.2128430971
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.2555669627
Short name T975
Test name
Test status
Simulation time 28370863 ps
CPU time 0.9 seconds
Started Jul 13 06:41:14 PM PDT 24
Finished Jul 13 06:41:18 PM PDT 24
Peak memory 218988 kb
Host smart-61497f94-2bd1-4036-8c05-425a09f32194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555669627 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.2555669627
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.2493327654
Short name T989
Test name
Test status
Simulation time 69966605 ps
CPU time 1.37 seconds
Started Jul 13 06:41:13 PM PDT 24
Finished Jul 13 06:41:16 PM PDT 24
Peak memory 219140 kb
Host smart-3c50a619-3102-4299-a7b1-db4cc94c8587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493327654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.2493327654
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%