Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.73 98.25 93.97 97.02 92.44 96.37 99.77 92.28


Total test records in report: 1130
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T277 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1195234818 Jul 14 06:57:19 PM PDT 24 Jul 14 06:57:23 PM PDT 24 18810458 ps
T1016 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2392979760 Jul 14 06:57:24 PM PDT 24 Jul 14 06:57:28 PM PDT 24 67548920 ps
T278 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1094710828 Jul 14 06:57:15 PM PDT 24 Jul 14 06:57:18 PM PDT 24 120869139 ps
T265 /workspace/coverage/cover_reg_top/10.edn_csr_rw.316343728 Jul 14 06:57:07 PM PDT 24 Jul 14 06:57:09 PM PDT 24 13026256 ps
T1017 /workspace/coverage/cover_reg_top/6.edn_tl_errors.3403138213 Jul 14 06:56:59 PM PDT 24 Jul 14 06:57:04 PM PDT 24 185613311 ps
T1018 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3160663337 Jul 14 06:57:00 PM PDT 24 Jul 14 06:57:03 PM PDT 24 140640361 ps
T1019 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3986531505 Jul 14 06:57:07 PM PDT 24 Jul 14 06:57:08 PM PDT 24 94398332 ps
T1020 /workspace/coverage/cover_reg_top/37.edn_intr_test.1304643286 Jul 14 06:57:15 PM PDT 24 Jul 14 06:57:19 PM PDT 24 15415360 ps
T1021 /workspace/coverage/cover_reg_top/46.edn_intr_test.1251510741 Jul 14 06:57:33 PM PDT 24 Jul 14 06:57:35 PM PDT 24 124208510 ps
T1022 /workspace/coverage/cover_reg_top/34.edn_intr_test.721031159 Jul 14 06:57:38 PM PDT 24 Jul 14 06:57:40 PM PDT 24 24014469 ps
T1023 /workspace/coverage/cover_reg_top/14.edn_intr_test.1321635919 Jul 14 06:57:08 PM PDT 24 Jul 14 06:57:10 PM PDT 24 15284525 ps
T1024 /workspace/coverage/cover_reg_top/18.edn_tl_errors.4085777669 Jul 14 06:57:20 PM PDT 24 Jul 14 06:57:24 PM PDT 24 45934704 ps
T1025 /workspace/coverage/cover_reg_top/32.edn_intr_test.1676086027 Jul 14 06:57:33 PM PDT 24 Jul 14 06:57:35 PM PDT 24 41227196 ps
T295 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2592400749 Jul 14 06:57:11 PM PDT 24 Jul 14 06:57:14 PM PDT 24 131921172 ps
T292 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.378811252 Jul 14 06:57:09 PM PDT 24 Jul 14 06:57:13 PM PDT 24 99649528 ps
T1026 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2485885762 Jul 14 06:57:12 PM PDT 24 Jul 14 06:57:14 PM PDT 24 15951402 ps
T1027 /workspace/coverage/cover_reg_top/9.edn_csr_rw.2900659310 Jul 14 06:57:11 PM PDT 24 Jul 14 06:57:13 PM PDT 24 12406623 ps
T1028 /workspace/coverage/cover_reg_top/44.edn_intr_test.2198486676 Jul 14 06:57:34 PM PDT 24 Jul 14 06:57:35 PM PDT 24 12903140 ps
T1029 /workspace/coverage/cover_reg_top/0.edn_intr_test.2279746058 Jul 14 06:56:57 PM PDT 24 Jul 14 06:56:59 PM PDT 24 23293847 ps
T1030 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.516927295 Jul 14 06:57:16 PM PDT 24 Jul 14 06:57:22 PM PDT 24 50312592 ps
T296 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2600403776 Jul 14 06:57:08 PM PDT 24 Jul 14 06:57:11 PM PDT 24 826810740 ps
T1031 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3076271768 Jul 14 06:57:09 PM PDT 24 Jul 14 06:57:11 PM PDT 24 22801456 ps
T1032 /workspace/coverage/cover_reg_top/19.edn_tl_errors.1384607895 Jul 14 06:57:35 PM PDT 24 Jul 14 06:57:39 PM PDT 24 194017711 ps
T1033 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1687205549 Jul 14 06:57:19 PM PDT 24 Jul 14 06:57:24 PM PDT 24 140823797 ps
T1034 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1533948273 Jul 14 06:57:12 PM PDT 24 Jul 14 06:57:20 PM PDT 24 252686845 ps
T1035 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2931230573 Jul 14 06:57:15 PM PDT 24 Jul 14 06:57:19 PM PDT 24 47974736 ps
T1036 /workspace/coverage/cover_reg_top/10.edn_tl_errors.2227067711 Jul 14 06:57:09 PM PDT 24 Jul 14 06:57:13 PM PDT 24 94193289 ps
T1037 /workspace/coverage/cover_reg_top/8.edn_tl_errors.4018168077 Jul 14 06:57:10 PM PDT 24 Jul 14 06:57:14 PM PDT 24 122356660 ps
T1038 /workspace/coverage/cover_reg_top/11.edn_tl_errors.2387663522 Jul 14 06:57:08 PM PDT 24 Jul 14 06:57:11 PM PDT 24 464703592 ps
T1039 /workspace/coverage/cover_reg_top/2.edn_intr_test.3878946651 Jul 14 06:57:01 PM PDT 24 Jul 14 06:57:04 PM PDT 24 79190230 ps
T1040 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1096375671 Jul 14 06:57:19 PM PDT 24 Jul 14 06:57:27 PM PDT 24 158170776 ps
T1041 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2346682029 Jul 14 06:57:00 PM PDT 24 Jul 14 06:57:08 PM PDT 24 219562809 ps
T1042 /workspace/coverage/cover_reg_top/6.edn_csr_rw.1865354885 Jul 14 06:57:00 PM PDT 24 Jul 14 06:57:03 PM PDT 24 13102502 ps
T1043 /workspace/coverage/cover_reg_top/12.edn_tl_errors.3431614405 Jul 14 06:57:15 PM PDT 24 Jul 14 06:57:21 PM PDT 24 42964191 ps
T266 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1172894845 Jul 14 06:57:08 PM PDT 24 Jul 14 06:57:10 PM PDT 24 158516304 ps
T1044 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2249839630 Jul 14 06:56:54 PM PDT 24 Jul 14 06:56:58 PM PDT 24 20672344 ps
T1045 /workspace/coverage/cover_reg_top/7.edn_intr_test.3687845370 Jul 14 06:57:04 PM PDT 24 Jul 14 06:57:06 PM PDT 24 89948023 ps
T267 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.735857463 Jul 14 06:56:59 PM PDT 24 Jul 14 06:57:03 PM PDT 24 82723867 ps
T1046 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2209817457 Jul 14 06:57:15 PM PDT 24 Jul 14 06:57:19 PM PDT 24 40985156 ps
T1047 /workspace/coverage/cover_reg_top/21.edn_intr_test.2112918500 Jul 14 06:57:31 PM PDT 24 Jul 14 06:57:33 PM PDT 24 92927285 ps
T1048 /workspace/coverage/cover_reg_top/26.edn_intr_test.4098025526 Jul 14 06:57:24 PM PDT 24 Jul 14 06:57:27 PM PDT 24 15624496 ps
T1049 /workspace/coverage/cover_reg_top/1.edn_tl_errors.3654973270 Jul 14 06:56:59 PM PDT 24 Jul 14 06:57:04 PM PDT 24 43652883 ps
T1050 /workspace/coverage/cover_reg_top/42.edn_intr_test.1959741474 Jul 14 06:57:36 PM PDT 24 Jul 14 06:57:38 PM PDT 24 11955154 ps
T1051 /workspace/coverage/cover_reg_top/28.edn_intr_test.2037338278 Jul 14 06:57:13 PM PDT 24 Jul 14 06:57:17 PM PDT 24 41499842 ps
T297 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2012934764 Jul 14 06:56:57 PM PDT 24 Jul 14 06:57:02 PM PDT 24 1351862777 ps
T293 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2139484621 Jul 14 06:56:53 PM PDT 24 Jul 14 06:56:59 PM PDT 24 359611330 ps
T1052 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1378948804 Jul 14 06:56:53 PM PDT 24 Jul 14 06:56:58 PM PDT 24 91308457 ps
T1053 /workspace/coverage/cover_reg_top/16.edn_csr_rw.1826189548 Jul 14 06:57:17 PM PDT 24 Jul 14 06:57:21 PM PDT 24 48173751 ps
T1054 /workspace/coverage/cover_reg_top/15.edn_tl_errors.2702880334 Jul 14 06:57:16 PM PDT 24 Jul 14 06:57:21 PM PDT 24 54536250 ps
T1055 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.4092297785 Jul 14 06:57:09 PM PDT 24 Jul 14 06:57:11 PM PDT 24 59444832 ps
T1056 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1976500107 Jul 14 06:57:13 PM PDT 24 Jul 14 06:57:16 PM PDT 24 23191465 ps
T1057 /workspace/coverage/cover_reg_top/45.edn_intr_test.2695505433 Jul 14 06:57:23 PM PDT 24 Jul 14 06:57:26 PM PDT 24 56324794 ps
T1058 /workspace/coverage/cover_reg_top/9.edn_tl_errors.2060590192 Jul 14 06:57:12 PM PDT 24 Jul 14 06:57:16 PM PDT 24 61926641 ps
T1059 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2014819136 Jul 14 06:57:24 PM PDT 24 Jul 14 06:57:29 PM PDT 24 77725023 ps
T1060 /workspace/coverage/cover_reg_top/11.edn_intr_test.4090678281 Jul 14 06:57:14 PM PDT 24 Jul 14 06:57:18 PM PDT 24 66081978 ps
T1061 /workspace/coverage/cover_reg_top/39.edn_intr_test.3282732191 Jul 14 06:57:12 PM PDT 24 Jul 14 06:57:15 PM PDT 24 125198554 ps
T1062 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.263155853 Jul 14 06:57:11 PM PDT 24 Jul 14 06:57:14 PM PDT 24 98445400 ps
T1063 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.288064330 Jul 14 06:56:59 PM PDT 24 Jul 14 06:57:03 PM PDT 24 18973932 ps
T1064 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2102368352 Jul 14 06:56:58 PM PDT 24 Jul 14 06:57:02 PM PDT 24 53670209 ps
T1065 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2930478797 Jul 14 06:57:05 PM PDT 24 Jul 14 06:57:06 PM PDT 24 133388448 ps
T1066 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1921264321 Jul 14 06:57:14 PM PDT 24 Jul 14 06:57:18 PM PDT 24 35998520 ps
T1067 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3333146560 Jul 14 06:57:04 PM PDT 24 Jul 14 06:57:07 PM PDT 24 33936295 ps
T1068 /workspace/coverage/cover_reg_top/1.edn_intr_test.1959462059 Jul 14 06:56:50 PM PDT 24 Jul 14 06:56:56 PM PDT 24 14531771 ps
T1069 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2704852314 Jul 14 06:57:19 PM PDT 24 Jul 14 06:57:24 PM PDT 24 152968713 ps
T1070 /workspace/coverage/cover_reg_top/15.edn_intr_test.2830552787 Jul 14 06:57:11 PM PDT 24 Jul 14 06:57:13 PM PDT 24 28344109 ps
T1071 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.897050005 Jul 14 06:57:01 PM PDT 24 Jul 14 06:57:04 PM PDT 24 18859562 ps
T1072 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1885994071 Jul 14 06:56:58 PM PDT 24 Jul 14 06:57:02 PM PDT 24 81412434 ps
T1073 /workspace/coverage/cover_reg_top/1.edn_csr_rw.3994606790 Jul 14 06:56:54 PM PDT 24 Jul 14 06:56:58 PM PDT 24 32942426 ps
T1074 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3707087134 Jul 14 06:57:17 PM PDT 24 Jul 14 06:57:22 PM PDT 24 47303049 ps
T268 /workspace/coverage/cover_reg_top/8.edn_csr_rw.1226262214 Jul 14 06:57:17 PM PDT 24 Jul 14 06:57:22 PM PDT 24 37184063 ps
T1075 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.4081662204 Jul 14 06:57:24 PM PDT 24 Jul 14 06:57:28 PM PDT 24 48340367 ps
T1076 /workspace/coverage/cover_reg_top/2.edn_tl_errors.1575926675 Jul 14 06:57:00 PM PDT 24 Jul 14 06:57:05 PM PDT 24 46064068 ps
T1077 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.473112639 Jul 14 06:57:09 PM PDT 24 Jul 14 06:57:11 PM PDT 24 41453122 ps
T1078 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2538736407 Jul 14 06:57:12 PM PDT 24 Jul 14 06:57:14 PM PDT 24 23754424 ps
T1079 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2487212472 Jul 14 06:56:55 PM PDT 24 Jul 14 06:56:59 PM PDT 24 137280089 ps
T1080 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1871748676 Jul 14 06:57:06 PM PDT 24 Jul 14 06:57:10 PM PDT 24 169053354 ps
T1081 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3202479575 Jul 14 06:57:29 PM PDT 24 Jul 14 06:57:32 PM PDT 24 138404960 ps
T1082 /workspace/coverage/cover_reg_top/18.edn_intr_test.2803994674 Jul 14 06:57:30 PM PDT 24 Jul 14 06:57:32 PM PDT 24 14848730 ps
T1083 /workspace/coverage/cover_reg_top/14.edn_csr_rw.3357757084 Jul 14 06:57:15 PM PDT 24 Jul 14 06:57:19 PM PDT 24 32339067 ps
T1084 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2745765766 Jul 14 06:56:58 PM PDT 24 Jul 14 06:57:02 PM PDT 24 168544175 ps
T1085 /workspace/coverage/cover_reg_top/25.edn_intr_test.2051553274 Jul 14 06:57:14 PM PDT 24 Jul 14 06:57:17 PM PDT 24 41038569 ps
T270 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3112147986 Jul 14 06:57:05 PM PDT 24 Jul 14 06:57:09 PM PDT 24 272187301 ps
T269 /workspace/coverage/cover_reg_top/18.edn_csr_rw.3283589203 Jul 14 06:57:25 PM PDT 24 Jul 14 06:57:29 PM PDT 24 19967853 ps
T1086 /workspace/coverage/cover_reg_top/43.edn_intr_test.316144485 Jul 14 06:57:13 PM PDT 24 Jul 14 06:57:16 PM PDT 24 102805246 ps
T1087 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.351849288 Jul 14 06:57:00 PM PDT 24 Jul 14 06:57:03 PM PDT 24 52367732 ps
T1088 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.355329677 Jul 14 06:56:58 PM PDT 24 Jul 14 06:57:01 PM PDT 24 16662724 ps
T1089 /workspace/coverage/cover_reg_top/13.edn_intr_test.3268967822 Jul 14 06:57:13 PM PDT 24 Jul 14 06:57:16 PM PDT 24 12408609 ps
T1090 /workspace/coverage/cover_reg_top/12.edn_csr_rw.4083336929 Jul 14 06:57:19 PM PDT 24 Jul 14 06:57:23 PM PDT 24 30735656 ps
T1091 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1837475141 Jul 14 06:57:24 PM PDT 24 Jul 14 06:57:28 PM PDT 24 97024566 ps
T1092 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.4170075627 Jul 14 06:57:10 PM PDT 24 Jul 14 06:57:13 PM PDT 24 42345188 ps
T1093 /workspace/coverage/cover_reg_top/17.edn_tl_errors.3402540302 Jul 14 06:57:11 PM PDT 24 Jul 14 06:57:15 PM PDT 24 242362885 ps
T1094 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1085738828 Jul 14 06:57:13 PM PDT 24 Jul 14 06:57:17 PM PDT 24 85100584 ps
T1095 /workspace/coverage/cover_reg_top/16.edn_tl_errors.3178833125 Jul 14 06:57:18 PM PDT 24 Jul 14 06:57:25 PM PDT 24 197196228 ps
T1096 /workspace/coverage/cover_reg_top/15.edn_csr_rw.2685010449 Jul 14 06:57:08 PM PDT 24 Jul 14 06:57:09 PM PDT 24 11300060 ps
T294 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1278475111 Jul 14 06:57:05 PM PDT 24 Jul 14 06:57:08 PM PDT 24 60456135 ps
T1097 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1824435100 Jul 14 06:57:15 PM PDT 24 Jul 14 06:57:19 PM PDT 24 91771076 ps
T1098 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2161021803 Jul 14 06:57:10 PM PDT 24 Jul 14 06:57:13 PM PDT 24 129735157 ps
T1099 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.732189911 Jul 14 06:56:56 PM PDT 24 Jul 14 06:56:59 PM PDT 24 46777790 ps
T271 /workspace/coverage/cover_reg_top/11.edn_csr_rw.3004078958 Jul 14 06:57:15 PM PDT 24 Jul 14 06:57:18 PM PDT 24 25087064 ps
T1100 /workspace/coverage/cover_reg_top/23.edn_intr_test.2779581990 Jul 14 06:57:20 PM PDT 24 Jul 14 06:57:23 PM PDT 24 80855509 ps
T1101 /workspace/coverage/cover_reg_top/0.edn_tl_errors.2434962091 Jul 14 06:56:50 PM PDT 24 Jul 14 06:56:58 PM PDT 24 99934969 ps
T1102 /workspace/coverage/cover_reg_top/22.edn_intr_test.2057197815 Jul 14 06:57:15 PM PDT 24 Jul 14 06:57:18 PM PDT 24 12807091 ps
T1103 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2904540427 Jul 14 06:57:13 PM PDT 24 Jul 14 06:57:18 PM PDT 24 33247348 ps
T1104 /workspace/coverage/cover_reg_top/2.edn_csr_rw.3022929808 Jul 14 06:57:07 PM PDT 24 Jul 14 06:57:08 PM PDT 24 14479854 ps
T1105 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3821969283 Jul 14 06:57:09 PM PDT 24 Jul 14 06:57:11 PM PDT 24 83596568 ps
T1106 /workspace/coverage/cover_reg_top/48.edn_intr_test.985072577 Jul 14 06:57:14 PM PDT 24 Jul 14 06:57:18 PM PDT 24 77123353 ps
T1107 /workspace/coverage/cover_reg_top/20.edn_intr_test.73835953 Jul 14 06:57:12 PM PDT 24 Jul 14 06:57:15 PM PDT 24 44957480 ps
T1108 /workspace/coverage/cover_reg_top/9.edn_intr_test.487363889 Jul 14 06:57:03 PM PDT 24 Jul 14 06:57:06 PM PDT 24 55771942 ps
T1109 /workspace/coverage/cover_reg_top/33.edn_intr_test.490478494 Jul 14 06:57:18 PM PDT 24 Jul 14 06:57:23 PM PDT 24 13875121 ps
T1110 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2155293998 Jul 14 06:57:19 PM PDT 24 Jul 14 06:57:23 PM PDT 24 23185270 ps
T1111 /workspace/coverage/cover_reg_top/19.edn_csr_rw.1062863263 Jul 14 06:57:19 PM PDT 24 Jul 14 06:57:23 PM PDT 24 44646666 ps
T1112 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1991878051 Jul 14 06:57:03 PM PDT 24 Jul 14 06:57:04 PM PDT 24 29302964 ps
T1113 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2368420735 Jul 14 06:57:13 PM PDT 24 Jul 14 06:57:16 PM PDT 24 37512421 ps
T1114 /workspace/coverage/cover_reg_top/3.edn_tl_errors.14295156 Jul 14 06:57:10 PM PDT 24 Jul 14 06:57:13 PM PDT 24 199372913 ps
T1115 /workspace/coverage/cover_reg_top/47.edn_intr_test.512550894 Jul 14 06:57:11 PM PDT 24 Jul 14 06:57:13 PM PDT 24 19600669 ps
T1116 /workspace/coverage/cover_reg_top/0.edn_csr_rw.2985646121 Jul 14 06:56:57 PM PDT 24 Jul 14 06:57:00 PM PDT 24 41604492 ps
T1117 /workspace/coverage/cover_reg_top/24.edn_intr_test.3592599842 Jul 14 06:57:36 PM PDT 24 Jul 14 06:57:38 PM PDT 24 13305664 ps
T1118 /workspace/coverage/cover_reg_top/19.edn_intr_test.1371983056 Jul 14 06:57:10 PM PDT 24 Jul 14 06:57:12 PM PDT 24 22938131 ps
T1119 /workspace/coverage/cover_reg_top/4.edn_tl_errors.132779370 Jul 14 06:56:57 PM PDT 24 Jul 14 06:57:04 PM PDT 24 314729569 ps
T1120 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2132128311 Jul 14 06:57:09 PM PDT 24 Jul 14 06:57:11 PM PDT 24 47076428 ps
T1121 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1818205397 Jul 14 06:57:22 PM PDT 24 Jul 14 06:57:25 PM PDT 24 43731338 ps
T1122 /workspace/coverage/cover_reg_top/13.edn_tl_errors.3753240753 Jul 14 06:57:13 PM PDT 24 Jul 14 06:57:17 PM PDT 24 50171865 ps
T1123 /workspace/coverage/cover_reg_top/38.edn_intr_test.3448285923 Jul 14 06:57:14 PM PDT 24 Jul 14 06:57:17 PM PDT 24 18880187 ps
T1124 /workspace/coverage/cover_reg_top/17.edn_intr_test.2395279226 Jul 14 06:57:16 PM PDT 24 Jul 14 06:57:20 PM PDT 24 44592974 ps
T1125 /workspace/coverage/cover_reg_top/31.edn_intr_test.1211125207 Jul 14 06:57:22 PM PDT 24 Jul 14 06:57:25 PM PDT 24 94414435 ps
T1126 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2610529682 Jul 14 06:56:58 PM PDT 24 Jul 14 06:57:01 PM PDT 24 16994955 ps
T1127 /workspace/coverage/cover_reg_top/4.edn_intr_test.2919752307 Jul 14 06:57:02 PM PDT 24 Jul 14 06:57:04 PM PDT 24 41717952 ps
T1128 /workspace/coverage/cover_reg_top/49.edn_intr_test.3233261100 Jul 14 06:57:34 PM PDT 24 Jul 14 06:57:36 PM PDT 24 37123329 ps
T1129 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2897234525 Jul 14 06:57:06 PM PDT 24 Jul 14 06:57:09 PM PDT 24 83845176 ps
T1130 /workspace/coverage/cover_reg_top/14.edn_tl_errors.686984851 Jul 14 06:57:10 PM PDT 24 Jul 14 06:57:15 PM PDT 24 449930949 ps

Test location /workspace/coverage/default/185.edn_genbits.557026739
Short name T9
Test name
Test status
Simulation time 68819493 ps
CPU time 2.4 seconds
Started Jul 14 07:00:07 PM PDT 24
Finished Jul 14 07:00:16 PM PDT 24
Peak memory 220640 kb
Host smart-a7d44a5c-e49e-4d08-b086-e5fe7c455d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557026739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.557026739
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.3530474321
Short name T3
Test name
Test status
Simulation time 130333833602 ps
CPU time 796.71 seconds
Started Jul 14 06:58:18 PM PDT 24
Finished Jul 14 07:11:41 PM PDT 24
Peak memory 222280 kb
Host smart-18fb0398-27e0-4c36-b960-d71722dc4ba7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530474321 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.3530474321
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_err.3185883097
Short name T4
Test name
Test status
Simulation time 30450289 ps
CPU time 1.34 seconds
Started Jul 14 06:58:28 PM PDT 24
Finished Jul 14 06:58:30 PM PDT 24
Peak memory 226076 kb
Host smart-2ec995e5-99a4-4a81-bd57-0db6c09bb2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185883097 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.3185883097
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/126.edn_alert.740985574
Short name T44
Test name
Test status
Simulation time 28834848 ps
CPU time 1.25 seconds
Started Jul 14 06:59:36 PM PDT 24
Finished Jul 14 06:59:40 PM PDT 24
Peak memory 218960 kb
Host smart-657aaf80-3330-45dc-86e3-3b6f25c45d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740985574 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.740985574
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/2.edn_sec_cm.25193619
Short name T16
Test name
Test status
Simulation time 300060174 ps
CPU time 4.82 seconds
Started Jul 14 06:57:51 PM PDT 24
Finished Jul 14 06:57:57 PM PDT 24
Peak memory 235712 kb
Host smart-09f05522-eec3-4b36-8995-d73f5e3e87b4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25193619 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.25193619
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/192.edn_alert.2597520281
Short name T39
Test name
Test status
Simulation time 80952608 ps
CPU time 1.18 seconds
Started Jul 14 06:59:56 PM PDT 24
Finished Jul 14 07:00:04 PM PDT 24
Peak memory 220016 kb
Host smart-3c445977-b7e2-4e73-8a09-31928971324b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597520281 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.2597520281
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.3903776082
Short name T11
Test name
Test status
Simulation time 42179116 ps
CPU time 1.03 seconds
Started Jul 14 06:58:28 PM PDT 24
Finished Jul 14 06:58:30 PM PDT 24
Peak memory 218712 kb
Host smart-fcfec9d8-4a60-4807-b4db-7f05ad864865
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903776082 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.3903776082
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_sec_cm.4092524942
Short name T56
Test name
Test status
Simulation time 1898022731 ps
CPU time 8.49 seconds
Started Jul 14 06:57:57 PM PDT 24
Finished Jul 14 06:58:07 PM PDT 24
Peak memory 244264 kb
Host smart-305b628a-c963-444d-9114-a1de7dcfa1f8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092524942 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.4092524942
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/18.edn_genbits.1238987778
Short name T12
Test name
Test status
Simulation time 218398900 ps
CPU time 1.25 seconds
Started Jul 14 06:58:05 PM PDT 24
Finished Jul 14 06:58:10 PM PDT 24
Peak memory 220236 kb
Host smart-74a4bb2f-f458-4b36-bef7-4979542d804b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238987778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1238987778
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/70.edn_alert.1604553172
Short name T285
Test name
Test status
Simulation time 88246097 ps
CPU time 1.15 seconds
Started Jul 14 06:59:08 PM PDT 24
Finished Jul 14 06:59:15 PM PDT 24
Peak memory 218744 kb
Host smart-2deff7e4-1a34-423b-990c-6e28c32f14db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604553172 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.1604553172
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2133089729
Short name T222
Test name
Test status
Simulation time 202260703456 ps
CPU time 1622.55 seconds
Started Jul 14 06:58:12 PM PDT 24
Finished Jul 14 07:25:22 PM PDT 24
Peak memory 224380 kb
Host smart-014d20fe-0259-4ec6-b7f4-5cb5e6408871
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133089729 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2133089729
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.edn_regwen.4025860890
Short name T735
Test name
Test status
Simulation time 27627254 ps
CPU time 0.98 seconds
Started Jul 14 06:58:07 PM PDT 24
Finished Jul 14 06:58:13 PM PDT 24
Peak memory 207432 kb
Host smart-f445ca0a-c005-42be-8bfd-6480b25dd7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025860890 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.4025860890
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/33.edn_disable.531818593
Short name T22
Test name
Test status
Simulation time 40330530 ps
CPU time 0.86 seconds
Started Jul 14 06:58:41 PM PDT 24
Finished Jul 14 06:58:43 PM PDT 24
Peak memory 216424 kb
Host smart-8b4f2adf-3b21-45ad-958c-1935bcc691b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531818593 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.531818593
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/142.edn_alert.1118073612
Short name T247
Test name
Test status
Simulation time 42947933 ps
CPU time 1.17 seconds
Started Jul 14 06:59:59 PM PDT 24
Finished Jul 14 07:00:09 PM PDT 24
Peak memory 220676 kb
Host smart-3d1daf45-658d-4ec4-bdc4-8edb7274300b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118073612 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.1118073612
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.1562029652
Short name T647
Test name
Test status
Simulation time 62947186 ps
CPU time 1.25 seconds
Started Jul 14 06:58:11 PM PDT 24
Finished Jul 14 06:58:19 PM PDT 24
Peak memory 217252 kb
Host smart-12626d64-9a4e-46a7-87e2-f68b57e7007d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562029652 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.1562029652
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2600403776
Short name T296
Test name
Test status
Simulation time 826810740 ps
CPU time 2.44 seconds
Started Jul 14 06:57:08 PM PDT 24
Finished Jul 14 06:57:11 PM PDT 24
Peak memory 215412 kb
Host smart-64ac88cc-8e19-4fb8-be80-9048cd7bc3b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600403776 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.2600403776
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/default/60.edn_err.3530110249
Short name T30
Test name
Test status
Simulation time 32542658 ps
CPU time 0.89 seconds
Started Jul 14 06:59:02 PM PDT 24
Finished Jul 14 06:59:07 PM PDT 24
Peak memory 219508 kb
Host smart-7cf3e3d3-b405-4d5f-9f1a-cecd4a3577fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530110249 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.3530110249
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/96.edn_alert.1411279519
Short name T160
Test name
Test status
Simulation time 107877430 ps
CPU time 1.13 seconds
Started Jul 14 06:59:26 PM PDT 24
Finished Jul 14 06:59:30 PM PDT 24
Peak memory 218624 kb
Host smart-b299280f-7a65-4246-a894-1b303b9d8a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411279519 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.1411279519
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.2761808762
Short name T113
Test name
Test status
Simulation time 477177700 ps
CPU time 3.2 seconds
Started Jul 14 06:59:40 PM PDT 24
Finished Jul 14 06:59:47 PM PDT 24
Peak memory 218888 kb
Host smart-95fd8edc-2b4c-4ed9-bd58-df5d0a86d2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761808762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.2761808762
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.3706606931
Short name T1
Test name
Test status
Simulation time 82993795 ps
CPU time 1.16 seconds
Started Jul 14 06:59:42 PM PDT 24
Finished Jul 14 06:59:46 PM PDT 24
Peak memory 219296 kb
Host smart-c716a1c1-bccf-483a-b56f-83665ee10c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706606931 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.3706606931
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/0.edn_disable.1549290779
Short name T207
Test name
Test status
Simulation time 13638689 ps
CPU time 0.9 seconds
Started Jul 14 06:57:42 PM PDT 24
Finished Jul 14 06:57:46 PM PDT 24
Peak memory 216760 kb
Host smart-0367b3d1-ad08-4cf4-80b7-59076a050799
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549290779 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.1549290779
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.3243356783
Short name T154
Test name
Test status
Simulation time 306559811 ps
CPU time 1.1 seconds
Started Jul 14 06:58:33 PM PDT 24
Finished Jul 14 06:58:36 PM PDT 24
Peak memory 217400 kb
Host smart-1774f53e-71cc-42d2-82c7-70bd4b93b2ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243356783 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.3243356783
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_disable.3213255909
Short name T203
Test name
Test status
Simulation time 32610909 ps
CPU time 0.81 seconds
Started Jul 14 06:58:52 PM PDT 24
Finished Jul 14 06:58:56 PM PDT 24
Peak memory 216572 kb
Host smart-ae44fa48-e98a-47dd-b837-c40dc8e78675
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213255909 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3213255909
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.316343728
Short name T265
Test name
Test status
Simulation time 13026256 ps
CPU time 0.9 seconds
Started Jul 14 06:57:07 PM PDT 24
Finished Jul 14 06:57:09 PM PDT 24
Peak memory 206972 kb
Host smart-29d14f8f-2983-466c-9f61-5fab5421ad65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316343728 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.316343728
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/default/31.edn_genbits.1306117051
Short name T287
Test name
Test status
Simulation time 46869927 ps
CPU time 1.46 seconds
Started Jul 14 06:58:45 PM PDT 24
Finished Jul 14 06:58:48 PM PDT 24
Peak memory 219124 kb
Host smart-089083ff-2d2d-4b36-99fa-d37b3055988d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306117051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.1306117051
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.4266093301
Short name T110
Test name
Test status
Simulation time 30417366 ps
CPU time 1.27 seconds
Started Jul 14 06:59:54 PM PDT 24
Finished Jul 14 07:00:02 PM PDT 24
Peak memory 216004 kb
Host smart-b1ae210a-45bf-4b4b-a38c-67e4b2f4805a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266093301 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.4266093301
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert.3880873809
Short name T677
Test name
Test status
Simulation time 26115607 ps
CPU time 1.17 seconds
Started Jul 14 06:58:46 PM PDT 24
Finished Jul 14 06:58:48 PM PDT 24
Peak memory 220228 kb
Host smart-a15b0499-d2df-4e68-af0f-16a6ff31a105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880873809 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.3880873809
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/12.edn_intr.2481617354
Short name T26
Test name
Test status
Simulation time 19468452 ps
CPU time 1.06 seconds
Started Jul 14 06:58:07 PM PDT 24
Finished Jul 14 06:58:14 PM PDT 24
Peak memory 216092 kb
Host smart-818fd37c-f1b5-4dbd-bffd-edf3a926ad22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481617354 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.2481617354
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/1.edn_alert.483680255
Short name T61
Test name
Test status
Simulation time 27395878 ps
CPU time 1.3 seconds
Started Jul 14 06:58:03 PM PDT 24
Finished Jul 14 06:58:06 PM PDT 24
Peak memory 218868 kb
Host smart-4c89d24b-d9af-4ed9-ace1-7b5bfd862a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483680255 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.483680255
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/129.edn_alert.177305773
Short name T551
Test name
Test status
Simulation time 25504232 ps
CPU time 1.19 seconds
Started Jul 14 06:59:27 PM PDT 24
Finished Jul 14 06:59:32 PM PDT 24
Peak memory 218824 kb
Host smart-f5117e8b-3720-4770-bf64-bec95d13bb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177305773 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.177305773
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert.2543896578
Short name T143
Test name
Test status
Simulation time 22604097 ps
CPU time 1.17 seconds
Started Jul 14 06:58:30 PM PDT 24
Finished Jul 14 06:58:33 PM PDT 24
Peak memory 219876 kb
Host smart-fa6c2b9f-6ef1-4c37-8b1c-4b764b807aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543896578 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.2543896578
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/167.edn_alert.376990485
Short name T105
Test name
Test status
Simulation time 59651606 ps
CPU time 1.15 seconds
Started Jul 14 06:59:44 PM PDT 24
Finished Jul 14 06:59:47 PM PDT 24
Peak memory 219960 kb
Host smart-b699db6e-75d9-4a2b-a231-aece90e05614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376990485 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.376990485
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/50.edn_alert.555653290
Short name T525
Test name
Test status
Simulation time 44006964 ps
CPU time 1.16 seconds
Started Jul 14 06:59:00 PM PDT 24
Finished Jul 14 06:59:05 PM PDT 24
Peak memory 218616 kb
Host smart-19971819-484c-4a4b-a150-c5dc9aa6cbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555653290 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.555653290
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/79.edn_genbits.753792685
Short name T320
Test name
Test status
Simulation time 76668326 ps
CPU time 1.38 seconds
Started Jul 14 06:59:21 PM PDT 24
Finished Jul 14 06:59:24 PM PDT 24
Peak memory 220184 kb
Host smart-d7127739-ce92-4317-baa1-8e0cf3550dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753792685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.753792685
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3864514142
Short name T27
Test name
Test status
Simulation time 40468477 ps
CPU time 0.83 seconds
Started Jul 14 06:58:30 PM PDT 24
Finished Jul 14 06:58:33 PM PDT 24
Peak memory 215900 kb
Host smart-abacc10c-818b-4056-8910-c18199dae826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864514142 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3864514142
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/255.edn_genbits.3942382879
Short name T98
Test name
Test status
Simulation time 26133901 ps
CPU time 1.12 seconds
Started Jul 14 07:00:14 PM PDT 24
Finished Jul 14 07:00:19 PM PDT 24
Peak memory 217596 kb
Host smart-ab4595c7-0d6f-4b6a-8377-794b0a8fee50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942382879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.3942382879
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.2184652278
Short name T985
Test name
Test status
Simulation time 39048949 ps
CPU time 1.2 seconds
Started Jul 14 06:59:27 PM PDT 24
Finished Jul 14 06:59:32 PM PDT 24
Peak memory 218968 kb
Host smart-b58289d9-ab0f-4b61-8791-80b676a25a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184652278 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.2184652278
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/21.edn_disable.4182356804
Short name T162
Test name
Test status
Simulation time 90915997 ps
CPU time 0.84 seconds
Started Jul 14 06:58:33 PM PDT 24
Finished Jul 14 06:58:36 PM PDT 24
Peak memory 215744 kb
Host smart-60491fa7-29bf-4f18-ba68-bf7a17e79038
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182356804 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.4182356804
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/0.edn_alert.1337125371
Short name T112
Test name
Test status
Simulation time 69259950 ps
CPU time 1.07 seconds
Started Jul 14 06:58:02 PM PDT 24
Finished Jul 14 06:58:05 PM PDT 24
Peak memory 219808 kb
Host smart-b9910608-d46f-418a-9216-7fdc5a3a5909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337125371 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.1337125371
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.4157511858
Short name T127
Test name
Test status
Simulation time 78304789 ps
CPU time 1.22 seconds
Started Jul 14 06:58:06 PM PDT 24
Finished Jul 14 06:58:12 PM PDT 24
Peak memory 217068 kb
Host smart-b923bfc8-a89f-4b19-8bae-cccc5c4cef11
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157511858 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.4157511858
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_disable.3296295372
Short name T181
Test name
Test status
Simulation time 13788034 ps
CPU time 0.97 seconds
Started Jul 14 06:58:29 PM PDT 24
Finished Jul 14 06:58:32 PM PDT 24
Peak memory 216816 kb
Host smart-a3674c06-ab01-4a13-b85c-24b0b5da5fa1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296295372 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.3296295372
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2826796643
Short name T678
Test name
Test status
Simulation time 184418957 ps
CPU time 1.17 seconds
Started Jul 14 06:58:23 PM PDT 24
Finished Jul 14 06:58:27 PM PDT 24
Peak memory 217144 kb
Host smart-14d30df7-698a-4b2a-9228-93c1d474ecec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826796643 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2826796643
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.3070993513
Short name T185
Test name
Test status
Simulation time 19224230 ps
CPU time 1.04 seconds
Started Jul 14 06:58:08 PM PDT 24
Finished Jul 14 06:58:14 PM PDT 24
Peak memory 218924 kb
Host smart-536ee559-1247-4aaa-abec-b91dc8da7e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070993513 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.3070993513
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.2756783608
Short name T139
Test name
Test status
Simulation time 32413679 ps
CPU time 1.23 seconds
Started Jul 14 06:58:15 PM PDT 24
Finished Jul 14 06:58:23 PM PDT 24
Peak memory 219816 kb
Host smart-baf125c2-10de-4a9b-aad1-2170a73243a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756783608 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.2756783608
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_disable.373234769
Short name T199
Test name
Test status
Simulation time 46034776 ps
CPU time 0.84 seconds
Started Jul 14 06:58:38 PM PDT 24
Finished Jul 14 06:58:40 PM PDT 24
Peak memory 216628 kb
Host smart-ab26df22-0ddd-407e-92e6-4b19a38a4a7b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373234769 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.373234769
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable.2861671296
Short name T196
Test name
Test status
Simulation time 16283507 ps
CPU time 0.87 seconds
Started Jul 14 06:58:50 PM PDT 24
Finished Jul 14 06:58:54 PM PDT 24
Peak memory 216476 kb
Host smart-1170941a-6552-406c-a93a-e0680e70f8d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861671296 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.2861671296
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.2926911692
Short name T158
Test name
Test status
Simulation time 181058655 ps
CPU time 1.17 seconds
Started Jul 14 06:58:51 PM PDT 24
Finished Jul 14 06:58:55 PM PDT 24
Peak memory 217308 kb
Host smart-19dfeb0a-7909-42fc-a7ce-220b23adcf66
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926911692 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.2926911692
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.623534263
Short name T123
Test name
Test status
Simulation time 127493775 ps
CPU time 1.1 seconds
Started Jul 14 06:58:47 PM PDT 24
Finished Jul 14 06:58:50 PM PDT 24
Peak memory 217048 kb
Host smart-e5814d5b-9958-44de-bd43-b9a21c8f523b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623534263 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_di
sable_auto_req_mode.623534263
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_disable.1509090683
Short name T195
Test name
Test status
Simulation time 20904638 ps
CPU time 0.86 seconds
Started Jul 14 06:59:06 PM PDT 24
Finished Jul 14 06:59:12 PM PDT 24
Peak memory 216660 kb
Host smart-4f728a48-2644-465e-9d6e-c8409c434f92
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509090683 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.1509090683
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/54.edn_err.1672790381
Short name T191
Test name
Test status
Simulation time 42201145 ps
CPU time 0.86 seconds
Started Jul 14 06:59:00 PM PDT 24
Finished Jul 14 06:59:05 PM PDT 24
Peak memory 218596 kb
Host smart-c82f24b1-aa2c-4cb9-a72d-e4536f6c014f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672790381 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.1672790381
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/91.edn_alert.3122608125
Short name T187
Test name
Test status
Simulation time 65203557 ps
CPU time 1.04 seconds
Started Jul 14 06:59:29 PM PDT 24
Finished Jul 14 06:59:33 PM PDT 24
Peak memory 219404 kb
Host smart-56b26c5a-fd01-4575-8974-05787c56e2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122608125 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.3122608125
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.1059115820
Short name T81
Test name
Test status
Simulation time 49000730 ps
CPU time 1.16 seconds
Started Jul 14 06:59:58 PM PDT 24
Finished Jul 14 07:00:07 PM PDT 24
Peak memory 217704 kb
Host smart-b8859e8c-c2d5-4bbd-aa3e-89890dbc5032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059115820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.1059115820
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert_test.1861245351
Short name T250
Test name
Test status
Simulation time 44551585 ps
CPU time 0.82 seconds
Started Jul 14 06:58:06 PM PDT 24
Finished Jul 14 06:58:11 PM PDT 24
Peak memory 214944 kb
Host smart-113aa26b-115a-4e0f-9c4f-814373977a6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861245351 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.1861245351
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_stress_all.1556090218
Short name T73
Test name
Test status
Simulation time 319475391 ps
CPU time 5.22 seconds
Started Jul 14 06:58:09 PM PDT 24
Finished Jul 14 06:58:21 PM PDT 24
Peak memory 215464 kb
Host smart-f4045416-10a2-48fb-80f2-5a12d12a1ea4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556090218 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.1556090218
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/101.edn_genbits.2381071250
Short name T314
Test name
Test status
Simulation time 137249294 ps
CPU time 1.06 seconds
Started Jul 14 06:59:08 PM PDT 24
Finished Jul 14 06:59:14 PM PDT 24
Peak memory 217788 kb
Host smart-e78aa6b9-6849-450f-8ca4-9c70f12fc54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381071250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.2381071250
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.1588250542
Short name T326
Test name
Test status
Simulation time 61281505 ps
CPU time 1.35 seconds
Started Jul 14 06:59:43 PM PDT 24
Finished Jul 14 06:59:47 PM PDT 24
Peak memory 217600 kb
Host smart-9c9efe91-476f-4ebe-8807-d2b1b9877b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588250542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.1588250542
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_genbits.2693664236
Short name T341
Test name
Test status
Simulation time 134278802 ps
CPU time 2.41 seconds
Started Jul 14 06:59:28 PM PDT 24
Finished Jul 14 06:59:34 PM PDT 24
Peak memory 220424 kb
Host smart-fc461aec-5a41-4acb-bd17-3ec799a15f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693664236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.2693664236
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.2669448242
Short name T31
Test name
Test status
Simulation time 24494151 ps
CPU time 0.97 seconds
Started Jul 14 06:58:09 PM PDT 24
Finished Jul 14 06:58:16 PM PDT 24
Peak memory 216056 kb
Host smart-8d6d2c94-473f-48c9-abec-80dd2729e828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669448242 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.2669448242
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.343238978
Short name T259
Test name
Test status
Simulation time 27784065 ps
CPU time 1.15 seconds
Started Jul 14 06:56:58 PM PDT 24
Finished Jul 14 06:57:01 PM PDT 24
Peak memory 206884 kb
Host smart-57ee0245-d711-473a-907f-5d88e2a9bcc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343238978 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_out
standing.343238978
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2139484621
Short name T293
Test name
Test status
Simulation time 359611330 ps
CPU time 2.4 seconds
Started Jul 14 06:56:53 PM PDT 24
Finished Jul 14 06:56:59 PM PDT 24
Peak memory 215060 kb
Host smart-40ab6783-7af9-407f-8abe-600b16390123
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139484621 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.2139484621
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.261926717
Short name T321
Test name
Test status
Simulation time 31684765084 ps
CPU time 822.21 seconds
Started Jul 14 06:58:07 PM PDT 24
Finished Jul 14 07:11:53 PM PDT 24
Peak memory 224052 kb
Host smart-1a1e2c6a-3fa0-40f1-9aa5-aa9916505020
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261926717 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.261926717
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/105.edn_genbits.1318426322
Short name T950
Test name
Test status
Simulation time 59618890 ps
CPU time 1.35 seconds
Started Jul 14 06:59:27 PM PDT 24
Finished Jul 14 06:59:31 PM PDT 24
Peak memory 219028 kb
Host smart-bca449c9-e9ee-41f0-a722-5c3f16ec33b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318426322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1318426322
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.318087917
Short name T253
Test name
Test status
Simulation time 46582451 ps
CPU time 1.06 seconds
Started Jul 14 06:58:11 PM PDT 24
Finished Jul 14 06:58:19 PM PDT 24
Peak memory 217244 kb
Host smart-cc7dd6b5-4452-4542-a41f-73a8d3286a2b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318087917 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_di
sable_auto_req_mode.318087917
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/120.edn_alert.3169318305
Short name T878
Test name
Test status
Simulation time 43021046 ps
CPU time 1.17 seconds
Started Jul 14 06:59:20 PM PDT 24
Finished Jul 14 06:59:23 PM PDT 24
Peak memory 218904 kb
Host smart-c173749d-9435-48dd-9928-200e28a87ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169318305 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.3169318305
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.2103103157
Short name T336
Test name
Test status
Simulation time 70612915 ps
CPU time 1.25 seconds
Started Jul 14 06:59:28 PM PDT 24
Finished Jul 14 06:59:33 PM PDT 24
Peak memory 219228 kb
Host smart-9f5e0cc9-40db-45b4-a9fd-41e22daefc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103103157 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.2103103157
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.727850475
Short name T313
Test name
Test status
Simulation time 67411295 ps
CPU time 1.16 seconds
Started Jul 14 06:59:33 PM PDT 24
Finished Jul 14 06:59:37 PM PDT 24
Peak memory 219208 kb
Host smart-44223f49-df2b-446b-9fe1-6f1b47205cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727850475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.727850475
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.315615713
Short name T317
Test name
Test status
Simulation time 46890854 ps
CPU time 1.63 seconds
Started Jul 14 06:59:43 PM PDT 24
Finished Jul 14 06:59:47 PM PDT 24
Peak memory 218928 kb
Host smart-e1f44329-bd31-4fff-b29a-3e23058f7b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315615713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.315615713
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.2843427617
Short name T330
Test name
Test status
Simulation time 102353189 ps
CPU time 1.09 seconds
Started Jul 14 06:59:44 PM PDT 24
Finished Jul 14 06:59:47 PM PDT 24
Peak memory 215576 kb
Host smart-a1d205e9-10e6-4483-8c2b-80b65f636cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843427617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.2843427617
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/180.edn_genbits.3327701679
Short name T397
Test name
Test status
Simulation time 68509255 ps
CPU time 1.58 seconds
Started Jul 14 06:59:42 PM PDT 24
Finished Jul 14 06:59:47 PM PDT 24
Peak memory 219028 kb
Host smart-c564bc35-891d-4377-9894-1dd0003cc688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327701679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.3327701679
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.641459020
Short name T14
Test name
Test status
Simulation time 71822164 ps
CPU time 1.13 seconds
Started Jul 14 07:00:14 PM PDT 24
Finished Jul 14 07:00:20 PM PDT 24
Peak memory 219836 kb
Host smart-a4085120-144e-4c04-9fa9-5b448185f4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641459020 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.641459020
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.4056941887
Short name T94
Test name
Test status
Simulation time 20193294 ps
CPU time 1.15 seconds
Started Jul 14 06:58:21 PM PDT 24
Finished Jul 14 06:58:26 PM PDT 24
Peak memory 216316 kb
Host smart-a4035e44-67e7-4b8b-ae94-be3a5e5b6fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056941887 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.4056941887
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/195.edn_alert.4245127331
Short name T117
Test name
Test status
Simulation time 25299383 ps
CPU time 1.2 seconds
Started Jul 14 06:59:54 PM PDT 24
Finished Jul 14 07:00:02 PM PDT 24
Peak memory 218960 kb
Host smart-46c6fbad-8530-4db4-9b76-33a80d23aa81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245127331 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.4245127331
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/14.edn_err.3465541473
Short name T132
Test name
Test status
Simulation time 31055883 ps
CPU time 1.05 seconds
Started Jul 14 06:58:16 PM PDT 24
Finished Jul 14 06:58:24 PM PDT 24
Peak memory 219992 kb
Host smart-14c7652c-b8cf-4565-9b1c-53927fd3d73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465541473 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.3465541473
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/231.edn_genbits.1673155408
Short name T632
Test name
Test status
Simulation time 48640533 ps
CPU time 1.54 seconds
Started Jul 14 06:59:53 PM PDT 24
Finished Jul 14 06:59:58 PM PDT 24
Peak memory 220400 kb
Host smart-d00ee6ff-a3bf-4f89-afe1-22dfb794c128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673155408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1673155408
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2102368352
Short name T1064
Test name
Test status
Simulation time 53670209 ps
CPU time 1.26 seconds
Started Jul 14 06:56:58 PM PDT 24
Finished Jul 14 06:57:02 PM PDT 24
Peak memory 206928 kb
Host smart-cf511e7b-b3ad-4ec1-9a4f-f6524250b88b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102368352 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.2102368352
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2346682029
Short name T1041
Test name
Test status
Simulation time 219562809 ps
CPU time 5.71 seconds
Started Jul 14 06:57:00 PM PDT 24
Finished Jul 14 06:57:08 PM PDT 24
Peak memory 206884 kb
Host smart-69dcdf3e-36f4-4a21-8d7a-7d6cabef1e78
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346682029 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.2346682029
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.288064330
Short name T1063
Test name
Test status
Simulation time 18973932 ps
CPU time 1.02 seconds
Started Jul 14 06:56:59 PM PDT 24
Finished Jul 14 06:57:03 PM PDT 24
Peak memory 206884 kb
Host smart-4ba8ffd9-255d-4f67-aa71-df66819d4750
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288064330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.288064330
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1378948804
Short name T1052
Test name
Test status
Simulation time 91308457 ps
CPU time 1.3 seconds
Started Jul 14 06:56:53 PM PDT 24
Finished Jul 14 06:56:58 PM PDT 24
Peak memory 215236 kb
Host smart-03de9bad-2184-4e16-9d0f-f4bbdacd2e0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378948804 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.1378948804
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2985646121
Short name T1116
Test name
Test status
Simulation time 41604492 ps
CPU time 0.82 seconds
Started Jul 14 06:56:57 PM PDT 24
Finished Jul 14 06:57:00 PM PDT 24
Peak memory 206924 kb
Host smart-9656be8d-7a5d-4b94-beb2-d67bd7562e83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985646121 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2985646121
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.2279746058
Short name T1029
Test name
Test status
Simulation time 23293847 ps
CPU time 0.87 seconds
Started Jul 14 06:56:57 PM PDT 24
Finished Jul 14 06:56:59 PM PDT 24
Peak memory 206912 kb
Host smart-4c208252-459a-45f8-8736-5cb0f7c0b0d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279746058 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.2279746058
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.2434962091
Short name T1101
Test name
Test status
Simulation time 99934969 ps
CPU time 3.81 seconds
Started Jul 14 06:56:50 PM PDT 24
Finished Jul 14 06:56:58 PM PDT 24
Peak memory 215224 kb
Host smart-6e59d496-e7c4-4469-85d6-5a76ed0e2ba6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434962091 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.2434962091
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2610529682
Short name T1126
Test name
Test status
Simulation time 16994955 ps
CPU time 1.11 seconds
Started Jul 14 06:56:58 PM PDT 24
Finished Jul 14 06:57:01 PM PDT 24
Peak memory 206868 kb
Host smart-5dcd909f-993c-49b4-845d-e641d55ed261
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610529682 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.2610529682
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1533948273
Short name T1034
Test name
Test status
Simulation time 252686845 ps
CPU time 6.36 seconds
Started Jul 14 06:57:12 PM PDT 24
Finished Jul 14 06:57:20 PM PDT 24
Peak memory 206932 kb
Host smart-55a7aed4-9e62-405d-a06f-bd7cf83b4cfb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533948273 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.1533948273
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.732189911
Short name T1099
Test name
Test status
Simulation time 46777790 ps
CPU time 0.95 seconds
Started Jul 14 06:56:56 PM PDT 24
Finished Jul 14 06:56:59 PM PDT 24
Peak memory 206884 kb
Host smart-60470f2d-11e9-4ba6-a0e8-05d5167e81e1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732189911 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.732189911
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2249839630
Short name T1044
Test name
Test status
Simulation time 20672344 ps
CPU time 1.15 seconds
Started Jul 14 06:56:54 PM PDT 24
Finished Jul 14 06:56:58 PM PDT 24
Peak memory 215220 kb
Host smart-01945d2d-68da-4313-a073-382c2df7196b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249839630 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2249839630
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.3994606790
Short name T1073
Test name
Test status
Simulation time 32942426 ps
CPU time 0.9 seconds
Started Jul 14 06:56:54 PM PDT 24
Finished Jul 14 06:56:58 PM PDT 24
Peak memory 206912 kb
Host smart-e990ff3e-80fd-4c65-8869-a02508eaa6e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994606790 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3994606790
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.1959462059
Short name T1068
Test name
Test status
Simulation time 14531771 ps
CPU time 0.89 seconds
Started Jul 14 06:56:50 PM PDT 24
Finished Jul 14 06:56:56 PM PDT 24
Peak memory 206808 kb
Host smart-81a2585b-d2f3-4126-ac3d-c56dfab43dbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959462059 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.1959462059
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.351849288
Short name T1087
Test name
Test status
Simulation time 52367732 ps
CPU time 1.34 seconds
Started Jul 14 06:57:00 PM PDT 24
Finished Jul 14 06:57:03 PM PDT 24
Peak memory 206896 kb
Host smart-90822fa3-f680-45c3-b31a-2dd233fe958c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351849288 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_out
standing.351849288
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.3654973270
Short name T1049
Test name
Test status
Simulation time 43652883 ps
CPU time 1.92 seconds
Started Jul 14 06:56:59 PM PDT 24
Finished Jul 14 06:57:04 PM PDT 24
Peak memory 215192 kb
Host smart-45724b91-fa4d-4a96-afcf-3f6968dfcb9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654973270 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3654973270
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.53889926
Short name T283
Test name
Test status
Simulation time 59490166 ps
CPU time 1.89 seconds
Started Jul 14 06:57:00 PM PDT 24
Finished Jul 14 06:57:04 PM PDT 24
Peak memory 206940 kb
Host smart-66b1e52b-acc9-47e7-afc4-3c917524d920
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53889926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.53889926
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2161021803
Short name T1098
Test name
Test status
Simulation time 129735157 ps
CPU time 1.14 seconds
Started Jul 14 06:57:10 PM PDT 24
Finished Jul 14 06:57:13 PM PDT 24
Peak memory 223352 kb
Host smart-29749e04-adaa-4b61-89b4-b11b64ec2dbc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161021803 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.2161021803
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.1193486134
Short name T1015
Test name
Test status
Simulation time 19768376 ps
CPU time 0.82 seconds
Started Jul 14 06:57:09 PM PDT 24
Finished Jul 14 06:57:11 PM PDT 24
Peak memory 206872 kb
Host smart-b44a2f8d-74db-4c9c-a592-1c255467bb94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193486134 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.1193486134
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1381397619
Short name T272
Test name
Test status
Simulation time 78740466 ps
CPU time 1.06 seconds
Started Jul 14 06:57:13 PM PDT 24
Finished Jul 14 06:57:17 PM PDT 24
Peak memory 206956 kb
Host smart-d0a4652e-c1b0-4282-a8a4-97f855578dee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381397619 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.1381397619
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.2227067711
Short name T1036
Test name
Test status
Simulation time 94193289 ps
CPU time 2.02 seconds
Started Jul 14 06:57:09 PM PDT 24
Finished Jul 14 06:57:13 PM PDT 24
Peak memory 215140 kb
Host smart-4261849f-242a-4176-b049-7a53bf17a04a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227067711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2227067711
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.378811252
Short name T292
Test name
Test status
Simulation time 99649528 ps
CPU time 2.66 seconds
Started Jul 14 06:57:09 PM PDT 24
Finished Jul 14 06:57:13 PM PDT 24
Peak memory 206904 kb
Host smart-246bc3de-d4e1-45e9-a815-e136e5a621d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378811252 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.378811252
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2392979760
Short name T1016
Test name
Test status
Simulation time 67548920 ps
CPU time 1.09 seconds
Started Jul 14 06:57:24 PM PDT 24
Finished Jul 14 06:57:28 PM PDT 24
Peak memory 215172 kb
Host smart-7a4e65ad-babd-4a40-8c0d-c1ac7ad1280f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392979760 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.2392979760
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.3004078958
Short name T271
Test name
Test status
Simulation time 25087064 ps
CPU time 0.92 seconds
Started Jul 14 06:57:15 PM PDT 24
Finished Jul 14 06:57:18 PM PDT 24
Peak memory 206852 kb
Host smart-65ecfd70-ec71-41d6-88c2-a9fbb08a14a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004078958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3004078958
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.4090678281
Short name T1060
Test name
Test status
Simulation time 66081978 ps
CPU time 0.84 seconds
Started Jul 14 06:57:14 PM PDT 24
Finished Jul 14 06:57:18 PM PDT 24
Peak memory 206848 kb
Host smart-8ef27a1e-9f95-4145-b191-555635f547e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090678281 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.4090678281
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3076271768
Short name T1031
Test name
Test status
Simulation time 22801456 ps
CPU time 1.08 seconds
Started Jul 14 06:57:09 PM PDT 24
Finished Jul 14 06:57:11 PM PDT 24
Peak memory 206908 kb
Host smart-78121b06-c90f-42f7-8ac4-1fd55a6cc446
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076271768 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3076271768
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.2387663522
Short name T1038
Test name
Test status
Simulation time 464703592 ps
CPU time 2.86 seconds
Started Jul 14 06:57:08 PM PDT 24
Finished Jul 14 06:57:11 PM PDT 24
Peak memory 215060 kb
Host smart-51ed6eb1-1b6c-4a4c-a27b-4ee6a7adfde2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387663522 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2387663522
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2704852314
Short name T1069
Test name
Test status
Simulation time 152968713 ps
CPU time 1.79 seconds
Started Jul 14 06:57:19 PM PDT 24
Finished Jul 14 06:57:24 PM PDT 24
Peak memory 215052 kb
Host smart-f341079d-0604-44fb-8391-c2dc49fb70ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704852314 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.2704852314
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2485885762
Short name T1026
Test name
Test status
Simulation time 15951402 ps
CPU time 1.12 seconds
Started Jul 14 06:57:12 PM PDT 24
Finished Jul 14 06:57:14 PM PDT 24
Peak memory 215160 kb
Host smart-6ee7489b-b5ed-4891-bba0-9cc53b513058
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485885762 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.2485885762
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.4083336929
Short name T1090
Test name
Test status
Simulation time 30735656 ps
CPU time 0.79 seconds
Started Jul 14 06:57:19 PM PDT 24
Finished Jul 14 06:57:23 PM PDT 24
Peak memory 206752 kb
Host smart-df14927a-586d-4c45-ad3d-194e3f56caa8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083336929 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.4083336929
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.1258533569
Short name T1005
Test name
Test status
Simulation time 39254097 ps
CPU time 0.82 seconds
Started Jul 14 06:57:09 PM PDT 24
Finished Jul 14 06:57:11 PM PDT 24
Peak memory 206644 kb
Host smart-a74349af-ff42-492a-ba7a-639a9f66962b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258533569 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.1258533569
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1094710828
Short name T278
Test name
Test status
Simulation time 120869139 ps
CPU time 1.1 seconds
Started Jul 14 06:57:15 PM PDT 24
Finished Jul 14 06:57:18 PM PDT 24
Peak memory 206916 kb
Host smart-d5aab0fe-1eaf-454d-8e6b-25f781f530bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094710828 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.1094710828
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3431614405
Short name T1043
Test name
Test status
Simulation time 42964191 ps
CPU time 3.3 seconds
Started Jul 14 06:57:15 PM PDT 24
Finished Jul 14 06:57:21 PM PDT 24
Peak memory 215252 kb
Host smart-c186e2ee-7617-45cd-86a1-313092339cc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431614405 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3431614405
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3522490891
Short name T1004
Test name
Test status
Simulation time 23725040 ps
CPU time 1.21 seconds
Started Jul 14 06:57:12 PM PDT 24
Finished Jul 14 06:57:15 PM PDT 24
Peak memory 217584 kb
Host smart-f99dc8ff-b276-4005-a0ce-4a361a2e6172
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522490891 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.3522490891
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.2833871837
Short name T264
Test name
Test status
Simulation time 15553069 ps
CPU time 0.97 seconds
Started Jul 14 06:57:16 PM PDT 24
Finished Jul 14 06:57:19 PM PDT 24
Peak memory 206888 kb
Host smart-fd079072-c00b-4841-9921-e019dd28a7e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833871837 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.2833871837
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.3268967822
Short name T1089
Test name
Test status
Simulation time 12408609 ps
CPU time 0.85 seconds
Started Jul 14 06:57:13 PM PDT 24
Finished Jul 14 06:57:16 PM PDT 24
Peak memory 206848 kb
Host smart-23186484-cd89-44ce-b2ac-2523fb89c3c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268967822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.3268967822
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2538736407
Short name T1078
Test name
Test status
Simulation time 23754424 ps
CPU time 1.18 seconds
Started Jul 14 06:57:12 PM PDT 24
Finished Jul 14 06:57:14 PM PDT 24
Peak memory 206960 kb
Host smart-f0238cf0-a3ae-48d0-8804-329e0b3f6959
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538736407 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2538736407
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.3753240753
Short name T1122
Test name
Test status
Simulation time 50171865 ps
CPU time 2.02 seconds
Started Jul 14 06:57:13 PM PDT 24
Finished Jul 14 06:57:17 PM PDT 24
Peak memory 215344 kb
Host smart-94d55302-b088-4c41-af61-47d6f88365de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753240753 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.3753240753
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1824435100
Short name T1097
Test name
Test status
Simulation time 91771076 ps
CPU time 2.13 seconds
Started Jul 14 06:57:15 PM PDT 24
Finished Jul 14 06:57:19 PM PDT 24
Peak memory 206896 kb
Host smart-b4c8121d-79b2-44cd-a4a3-b126fe52c8e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824435100 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1824435100
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2904540427
Short name T1103
Test name
Test status
Simulation time 33247348 ps
CPU time 2.26 seconds
Started Jul 14 06:57:13 PM PDT 24
Finished Jul 14 06:57:18 PM PDT 24
Peak memory 215220 kb
Host smart-99e61c05-8450-4787-be6b-dfe45c88d771
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904540427 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2904540427
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.3357757084
Short name T1083
Test name
Test status
Simulation time 32339067 ps
CPU time 0.97 seconds
Started Jul 14 06:57:15 PM PDT 24
Finished Jul 14 06:57:19 PM PDT 24
Peak memory 206892 kb
Host smart-ab9d68f1-68f1-43bc-b9b1-a51ee6759206
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357757084 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.3357757084
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.1321635919
Short name T1023
Test name
Test status
Simulation time 15284525 ps
CPU time 0.86 seconds
Started Jul 14 06:57:08 PM PDT 24
Finished Jul 14 06:57:10 PM PDT 24
Peak memory 206852 kb
Host smart-f936ab63-8d1d-456d-bd7f-dbf60bfdd88b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321635919 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.1321635919
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3707087134
Short name T1074
Test name
Test status
Simulation time 47303049 ps
CPU time 0.97 seconds
Started Jul 14 06:57:17 PM PDT 24
Finished Jul 14 06:57:22 PM PDT 24
Peak memory 207024 kb
Host smart-6d55b5a5-eeae-4881-9d1a-4e343c5fe35d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707087134 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.3707087134
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.686984851
Short name T1130
Test name
Test status
Simulation time 449930949 ps
CPU time 4.41 seconds
Started Jul 14 06:57:10 PM PDT 24
Finished Jul 14 06:57:15 PM PDT 24
Peak memory 215180 kb
Host smart-966f2362-9bf9-4dd9-8cf4-09787789a9e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686984851 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.686984851
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1085738828
Short name T1094
Test name
Test status
Simulation time 85100584 ps
CPU time 1.62 seconds
Started Jul 14 06:57:13 PM PDT 24
Finished Jul 14 06:57:17 PM PDT 24
Peak memory 206884 kb
Host smart-06b7e665-c7e5-4b22-9e1f-14d9f0ff7dcf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085738828 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1085738828
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3202479575
Short name T1081
Test name
Test status
Simulation time 138404960 ps
CPU time 1.01 seconds
Started Jul 14 06:57:29 PM PDT 24
Finished Jul 14 06:57:32 PM PDT 24
Peak memory 216608 kb
Host smart-5d333c49-70ee-4844-acac-aef500c029c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202479575 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.3202479575
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.2685010449
Short name T1096
Test name
Test status
Simulation time 11300060 ps
CPU time 0.81 seconds
Started Jul 14 06:57:08 PM PDT 24
Finished Jul 14 06:57:09 PM PDT 24
Peak memory 206756 kb
Host smart-9a93a45f-8df2-4842-a92e-5c7ae33573c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685010449 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2685010449
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.2830552787
Short name T1070
Test name
Test status
Simulation time 28344109 ps
CPU time 0.87 seconds
Started Jul 14 06:57:11 PM PDT 24
Finished Jul 14 06:57:13 PM PDT 24
Peak memory 206892 kb
Host smart-ed5ac81d-980c-4271-b66b-bea47adac91c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830552787 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.2830552787
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1195234818
Short name T277
Test name
Test status
Simulation time 18810458 ps
CPU time 1.17 seconds
Started Jul 14 06:57:19 PM PDT 24
Finished Jul 14 06:57:23 PM PDT 24
Peak memory 206988 kb
Host smart-4adcfa96-52fe-4b16-a975-e879e3554740
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195234818 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.1195234818
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.2702880334
Short name T1054
Test name
Test status
Simulation time 54536250 ps
CPU time 2.17 seconds
Started Jul 14 06:57:16 PM PDT 24
Finished Jul 14 06:57:21 PM PDT 24
Peak memory 215148 kb
Host smart-ec1d9bef-b074-4c59-b515-ad9818f9e73d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702880334 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2702880334
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2592400749
Short name T295
Test name
Test status
Simulation time 131921172 ps
CPU time 1.46 seconds
Started Jul 14 06:57:11 PM PDT 24
Finished Jul 14 06:57:14 PM PDT 24
Peak memory 207088 kb
Host smart-3f0f1ab6-15c1-4543-a2f8-49cb48e90e40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592400749 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2592400749
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.4170075627
Short name T1092
Test name
Test status
Simulation time 42345188 ps
CPU time 1.24 seconds
Started Jul 14 06:57:10 PM PDT 24
Finished Jul 14 06:57:13 PM PDT 24
Peak memory 215236 kb
Host smart-1d8859f2-9799-4739-99dd-d37943516114
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170075627 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.4170075627
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.1826189548
Short name T1053
Test name
Test status
Simulation time 48173751 ps
CPU time 0.89 seconds
Started Jul 14 06:57:17 PM PDT 24
Finished Jul 14 06:57:21 PM PDT 24
Peak memory 206916 kb
Host smart-672cc4bb-f0c3-447a-be8a-1965cac4e714
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826189548 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1826189548
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.2670738991
Short name T1000
Test name
Test status
Simulation time 12884789 ps
CPU time 0.89 seconds
Started Jul 14 06:57:26 PM PDT 24
Finished Jul 14 06:57:29 PM PDT 24
Peak memory 206812 kb
Host smart-886df829-1c8a-41e7-91b9-79edb059a72b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670738991 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.2670738991
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2368420735
Short name T1113
Test name
Test status
Simulation time 37512421 ps
CPU time 1.47 seconds
Started Jul 14 06:57:13 PM PDT 24
Finished Jul 14 06:57:16 PM PDT 24
Peak memory 206876 kb
Host smart-e4913405-6a68-4383-812e-d4a5e7c56d16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368420735 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.2368420735
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.3178833125
Short name T1095
Test name
Test status
Simulation time 197196228 ps
CPU time 3.9 seconds
Started Jul 14 06:57:18 PM PDT 24
Finished Jul 14 06:57:25 PM PDT 24
Peak memory 215188 kb
Host smart-0b421e80-0d92-4d7b-9d1e-32b9ffcbf6a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178833125 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3178833125
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1687205549
Short name T1033
Test name
Test status
Simulation time 140823797 ps
CPU time 1.52 seconds
Started Jul 14 06:57:19 PM PDT 24
Finished Jul 14 06:57:24 PM PDT 24
Peak memory 207152 kb
Host smart-4a71c86a-21cf-4815-9916-c2205b4dd773
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687205549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.1687205549
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2209817457
Short name T1046
Test name
Test status
Simulation time 40985156 ps
CPU time 0.98 seconds
Started Jul 14 06:57:15 PM PDT 24
Finished Jul 14 06:57:19 PM PDT 24
Peak memory 206948 kb
Host smart-4cac1488-a4dd-467b-a78f-8a4884596e5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209817457 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2209817457
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.4075781769
Short name T261
Test name
Test status
Simulation time 14733706 ps
CPU time 0.91 seconds
Started Jul 14 06:57:13 PM PDT 24
Finished Jul 14 06:57:16 PM PDT 24
Peak memory 206884 kb
Host smart-88ef36f0-e6ac-491e-b68e-f20c216c1125
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075781769 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.4075781769
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.2395279226
Short name T1124
Test name
Test status
Simulation time 44592974 ps
CPU time 0.93 seconds
Started Jul 14 06:57:16 PM PDT 24
Finished Jul 14 06:57:20 PM PDT 24
Peak memory 206828 kb
Host smart-d2b0acde-d914-4100-a241-ffe004628333
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395279226 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.2395279226
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2155293998
Short name T1110
Test name
Test status
Simulation time 23185270 ps
CPU time 1.15 seconds
Started Jul 14 06:57:19 PM PDT 24
Finished Jul 14 06:57:23 PM PDT 24
Peak memory 206996 kb
Host smart-d8307843-4dae-4121-ac90-f2178455def7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155293998 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.2155293998
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.3402540302
Short name T1093
Test name
Test status
Simulation time 242362885 ps
CPU time 2.66 seconds
Started Jul 14 06:57:11 PM PDT 24
Finished Jul 14 06:57:15 PM PDT 24
Peak memory 223556 kb
Host smart-c2c411b6-056d-4ed2-aa76-3c4c4dd23578
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402540302 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3402540302
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2897234525
Short name T1129
Test name
Test status
Simulation time 83845176 ps
CPU time 2.34 seconds
Started Jul 14 06:57:06 PM PDT 24
Finished Jul 14 06:57:09 PM PDT 24
Peak memory 206928 kb
Host smart-2b33cd00-9de7-4c93-a658-db66ebc0b157
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897234525 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.2897234525
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.516927295
Short name T1030
Test name
Test status
Simulation time 50312592 ps
CPU time 1.8 seconds
Started Jul 14 06:57:16 PM PDT 24
Finished Jul 14 06:57:22 PM PDT 24
Peak memory 220184 kb
Host smart-8c7bbb83-7901-44ac-a804-2e9c942c65c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516927295 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.516927295
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.3283589203
Short name T269
Test name
Test status
Simulation time 19967853 ps
CPU time 0.84 seconds
Started Jul 14 06:57:25 PM PDT 24
Finished Jul 14 06:57:29 PM PDT 24
Peak memory 206740 kb
Host smart-0fee75f6-a2e0-494b-9926-86cac94e8142
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283589203 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.3283589203
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2803994674
Short name T1082
Test name
Test status
Simulation time 14848730 ps
CPU time 0.92 seconds
Started Jul 14 06:57:30 PM PDT 24
Finished Jul 14 06:57:32 PM PDT 24
Peak memory 206800 kb
Host smart-81cf1b85-528a-4393-8d75-7b22a6fb73c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803994674 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2803994674
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.4081662204
Short name T1075
Test name
Test status
Simulation time 48340367 ps
CPU time 1 seconds
Started Jul 14 06:57:24 PM PDT 24
Finished Jul 14 06:57:28 PM PDT 24
Peak memory 207144 kb
Host smart-2c655bd7-e167-4247-9341-a4b21d245c07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081662204 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.4081662204
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.4085777669
Short name T1024
Test name
Test status
Simulation time 45934704 ps
CPU time 1.88 seconds
Started Jul 14 06:57:20 PM PDT 24
Finished Jul 14 06:57:24 PM PDT 24
Peak memory 215096 kb
Host smart-d6019db0-b040-49bd-a83c-1875b26c155a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085777669 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.4085777669
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1096375671
Short name T1040
Test name
Test status
Simulation time 158170776 ps
CPU time 1.5 seconds
Started Jul 14 06:57:19 PM PDT 24
Finished Jul 14 06:57:27 PM PDT 24
Peak memory 206992 kb
Host smart-6a352cea-faae-4b1a-a817-6bac1b3e6dd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096375671 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1096375671
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1837475141
Short name T1091
Test name
Test status
Simulation time 97024566 ps
CPU time 1.22 seconds
Started Jul 14 06:57:24 PM PDT 24
Finished Jul 14 06:57:28 PM PDT 24
Peak memory 207048 kb
Host smart-95767639-3140-4bb5-b092-a7c4a0b384c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837475141 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.1837475141
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.1062863263
Short name T1111
Test name
Test status
Simulation time 44646666 ps
CPU time 0.9 seconds
Started Jul 14 06:57:19 PM PDT 24
Finished Jul 14 06:57:23 PM PDT 24
Peak memory 206916 kb
Host smart-ff39d127-14a9-4f81-8512-a5d3ed1ffe21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062863263 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.1062863263
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.1371983056
Short name T1118
Test name
Test status
Simulation time 22938131 ps
CPU time 0.86 seconds
Started Jul 14 06:57:10 PM PDT 24
Finished Jul 14 06:57:12 PM PDT 24
Peak memory 206816 kb
Host smart-8f1dc229-a004-47e7-8cbd-1d9c5aac6582
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371983056 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.1371983056
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.709586872
Short name T275
Test name
Test status
Simulation time 18634690 ps
CPU time 1.14 seconds
Started Jul 14 06:57:17 PM PDT 24
Finished Jul 14 06:57:21 PM PDT 24
Peak memory 206900 kb
Host smart-359832e0-b0ba-4f44-9853-4671ed20a0ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709586872 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_ou
tstanding.709586872
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1384607895
Short name T1032
Test name
Test status
Simulation time 194017711 ps
CPU time 2.68 seconds
Started Jul 14 06:57:35 PM PDT 24
Finished Jul 14 06:57:39 PM PDT 24
Peak memory 215244 kb
Host smart-ecad39f6-ad6e-4c71-8f1c-9489cb0a0199
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384607895 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1384607895
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2014819136
Short name T1059
Test name
Test status
Simulation time 77725023 ps
CPU time 2.34 seconds
Started Jul 14 06:57:24 PM PDT 24
Finished Jul 14 06:57:29 PM PDT 24
Peak memory 206896 kb
Host smart-93d7aea7-598e-4d25-af9d-c16a75f09cfe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014819136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.2014819136
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.4282673880
Short name T260
Test name
Test status
Simulation time 64028175 ps
CPU time 1.58 seconds
Started Jul 14 06:57:04 PM PDT 24
Finished Jul 14 06:57:07 PM PDT 24
Peak memory 207032 kb
Host smart-a1f2cd19-4cb6-4b78-909e-dffbeedcd669
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282673880 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.4282673880
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1921264321
Short name T1066
Test name
Test status
Simulation time 35998520 ps
CPU time 2.07 seconds
Started Jul 14 06:57:14 PM PDT 24
Finished Jul 14 06:57:18 PM PDT 24
Peak memory 206888 kb
Host smart-ac0b48d4-4f06-44dc-95dc-5137472c6438
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921264321 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1921264321
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1991878051
Short name T1112
Test name
Test status
Simulation time 29302964 ps
CPU time 0.94 seconds
Started Jul 14 06:57:03 PM PDT 24
Finished Jul 14 06:57:04 PM PDT 24
Peak memory 206848 kb
Host smart-d843ec09-a9c3-432b-9137-f40d0c9d93ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991878051 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1991878051
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.15599159
Short name T997
Test name
Test status
Simulation time 28798240 ps
CPU time 0.97 seconds
Started Jul 14 06:57:19 PM PDT 24
Finished Jul 14 06:57:24 PM PDT 24
Peak memory 206964 kb
Host smart-43b4f2ab-f2b2-426f-aada-548d19a2f24c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15599159 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.15599159
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.3022929808
Short name T1104
Test name
Test status
Simulation time 14479854 ps
CPU time 0.95 seconds
Started Jul 14 06:57:07 PM PDT 24
Finished Jul 14 06:57:08 PM PDT 24
Peak memory 206796 kb
Host smart-0f3c6b62-aeb4-440c-8ecb-0f7b60d4aa85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022929808 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3022929808
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.3878946651
Short name T1039
Test name
Test status
Simulation time 79190230 ps
CPU time 0.91 seconds
Started Jul 14 06:57:01 PM PDT 24
Finished Jul 14 06:57:04 PM PDT 24
Peak memory 206916 kb
Host smart-cea958d0-92c5-47af-a481-a708a9bef18b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878946651 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.3878946651
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.4092297785
Short name T1055
Test name
Test status
Simulation time 59444832 ps
CPU time 1.18 seconds
Started Jul 14 06:57:09 PM PDT 24
Finished Jul 14 06:57:11 PM PDT 24
Peak memory 206976 kb
Host smart-1f8ccc60-0163-4f01-acec-18f8ebd1d880
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092297785 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.4092297785
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.1575926675
Short name T1076
Test name
Test status
Simulation time 46064068 ps
CPU time 2.44 seconds
Started Jul 14 06:57:00 PM PDT 24
Finished Jul 14 06:57:05 PM PDT 24
Peak memory 215320 kb
Host smart-cf25d985-ef2e-488d-8740-c58883f4d09c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575926675 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1575926675
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1204763818
Short name T291
Test name
Test status
Simulation time 119707142 ps
CPU time 1.8 seconds
Started Jul 14 06:56:52 PM PDT 24
Finished Jul 14 06:56:58 PM PDT 24
Peak memory 206936 kb
Host smart-d04f6f43-5dc7-42d4-b038-27f76abeb355
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204763818 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1204763818
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.73835953
Short name T1107
Test name
Test status
Simulation time 44957480 ps
CPU time 0.84 seconds
Started Jul 14 06:57:12 PM PDT 24
Finished Jul 14 06:57:15 PM PDT 24
Peak memory 206816 kb
Host smart-f70f7bf7-9e52-4594-b223-da4c72d61c22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73835953 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.73835953
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.2112918500
Short name T1047
Test name
Test status
Simulation time 92927285 ps
CPU time 0.87 seconds
Started Jul 14 06:57:31 PM PDT 24
Finished Jul 14 06:57:33 PM PDT 24
Peak memory 206876 kb
Host smart-901da8b7-5845-4eae-baa5-156d33bae0d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112918500 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.2112918500
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.2057197815
Short name T1102
Test name
Test status
Simulation time 12807091 ps
CPU time 0.93 seconds
Started Jul 14 06:57:15 PM PDT 24
Finished Jul 14 06:57:18 PM PDT 24
Peak memory 206792 kb
Host smart-c571022c-d08a-4b7a-893e-6dc1833e20d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057197815 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2057197815
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.2779581990
Short name T1100
Test name
Test status
Simulation time 80855509 ps
CPU time 0.83 seconds
Started Jul 14 06:57:20 PM PDT 24
Finished Jul 14 06:57:23 PM PDT 24
Peak memory 206760 kb
Host smart-f97c7d05-3d34-4d11-a746-33829f1017d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779581990 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2779581990
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.3592599842
Short name T1117
Test name
Test status
Simulation time 13305664 ps
CPU time 0.88 seconds
Started Jul 14 06:57:36 PM PDT 24
Finished Jul 14 06:57:38 PM PDT 24
Peak memory 206864 kb
Host smart-510f330e-9744-43dc-beaf-251b75b25f9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592599842 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3592599842
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.2051553274
Short name T1085
Test name
Test status
Simulation time 41038569 ps
CPU time 0.81 seconds
Started Jul 14 06:57:14 PM PDT 24
Finished Jul 14 06:57:17 PM PDT 24
Peak memory 206616 kb
Host smart-7283d6e3-aac5-4d0a-bd43-3f68bacef1a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051553274 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.2051553274
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.4098025526
Short name T1048
Test name
Test status
Simulation time 15624496 ps
CPU time 0.91 seconds
Started Jul 14 06:57:24 PM PDT 24
Finished Jul 14 06:57:27 PM PDT 24
Peak memory 206864 kb
Host smart-53b1b8e0-0429-41e9-a911-71a5027b0053
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098025526 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.4098025526
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.281109586
Short name T1008
Test name
Test status
Simulation time 14261052 ps
CPU time 0.86 seconds
Started Jul 14 06:57:19 PM PDT 24
Finished Jul 14 06:57:23 PM PDT 24
Peak memory 206844 kb
Host smart-ad2e08eb-dc32-4980-a05e-de3ffb6ffb53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281109586 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.281109586
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2037338278
Short name T1051
Test name
Test status
Simulation time 41499842 ps
CPU time 0.8 seconds
Started Jul 14 06:57:13 PM PDT 24
Finished Jul 14 06:57:17 PM PDT 24
Peak memory 206644 kb
Host smart-fafd77af-58b3-4192-a140-995bc5f1dcbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037338278 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2037338278
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.4220849141
Short name T1014
Test name
Test status
Simulation time 12913847 ps
CPU time 0.86 seconds
Started Jul 14 06:57:21 PM PDT 24
Finished Jul 14 06:57:24 PM PDT 24
Peak memory 206864 kb
Host smart-511e1667-1cfc-4738-b2c7-eecdcbb34612
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220849141 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.4220849141
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.735857463
Short name T267
Test name
Test status
Simulation time 82723867 ps
CPU time 1.58 seconds
Started Jul 14 06:56:59 PM PDT 24
Finished Jul 14 06:57:03 PM PDT 24
Peak memory 206912 kb
Host smart-372615fe-3157-4ef0-93a2-2c5c691afd62
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735857463 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.735857463
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3112147986
Short name T270
Test name
Test status
Simulation time 272187301 ps
CPU time 3.48 seconds
Started Jul 14 06:57:05 PM PDT 24
Finished Jul 14 06:57:09 PM PDT 24
Peak memory 206864 kb
Host smart-ab3a6209-fdfe-4150-9bd7-3a993172544a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112147986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3112147986
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.296355038
Short name T262
Test name
Test status
Simulation time 46618992 ps
CPU time 0.91 seconds
Started Jul 14 06:57:01 PM PDT 24
Finished Jul 14 06:57:03 PM PDT 24
Peak memory 206916 kb
Host smart-a7a5d11f-db49-4df0-8fb8-402c76d838c3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296355038 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.296355038
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2487212472
Short name T1079
Test name
Test status
Simulation time 137280089 ps
CPU time 1.55 seconds
Started Jul 14 06:56:55 PM PDT 24
Finished Jul 14 06:56:59 PM PDT 24
Peak memory 215124 kb
Host smart-00a678d2-be63-44bb-9571-f3c78fb2d2a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487212472 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2487212472
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1610302403
Short name T263
Test name
Test status
Simulation time 91482074 ps
CPU time 0.84 seconds
Started Jul 14 06:57:05 PM PDT 24
Finished Jul 14 06:57:07 PM PDT 24
Peak memory 206728 kb
Host smart-dde84404-11b5-4888-9411-96dd5bbd1ecd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610302403 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1610302403
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.326054439
Short name T1013
Test name
Test status
Simulation time 17905272 ps
CPU time 0.81 seconds
Started Jul 14 06:57:15 PM PDT 24
Finished Jul 14 06:57:18 PM PDT 24
Peak memory 206820 kb
Host smart-5bd44208-7029-4f2e-9319-b466c0f33def
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326054439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.326054439
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3986531505
Short name T1019
Test name
Test status
Simulation time 94398332 ps
CPU time 1.27 seconds
Started Jul 14 06:57:07 PM PDT 24
Finished Jul 14 06:57:08 PM PDT 24
Peak memory 206820 kb
Host smart-e7c0b47d-18cc-49a2-b1b2-76106a409bc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986531505 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.3986531505
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.14295156
Short name T1114
Test name
Test status
Simulation time 199372913 ps
CPU time 2.1 seconds
Started Jul 14 06:57:10 PM PDT 24
Finished Jul 14 06:57:13 PM PDT 24
Peak memory 215324 kb
Host smart-b3bb3ecf-8fca-46cf-ae46-9bf3f5e6d5d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14295156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.14295156
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.263155853
Short name T1062
Test name
Test status
Simulation time 98445400 ps
CPU time 2.49 seconds
Started Jul 14 06:57:11 PM PDT 24
Finished Jul 14 06:57:14 PM PDT 24
Peak memory 206908 kb
Host smart-ee1b503f-9ab4-4d81-84a9-51a2a69151c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263155853 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.263155853
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.393689686
Short name T998
Test name
Test status
Simulation time 36619303 ps
CPU time 0.86 seconds
Started Jul 14 06:57:36 PM PDT 24
Finished Jul 14 06:57:38 PM PDT 24
Peak memory 206856 kb
Host smart-4d46f7fd-68f4-477d-8064-c1f313901d44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393689686 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.393689686
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.1211125207
Short name T1125
Test name
Test status
Simulation time 94414435 ps
CPU time 0.87 seconds
Started Jul 14 06:57:22 PM PDT 24
Finished Jul 14 06:57:25 PM PDT 24
Peak memory 206688 kb
Host smart-bee49a89-f0b8-4d9a-826b-700695897d22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211125207 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.1211125207
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.1676086027
Short name T1025
Test name
Test status
Simulation time 41227196 ps
CPU time 0.77 seconds
Started Jul 14 06:57:33 PM PDT 24
Finished Jul 14 06:57:35 PM PDT 24
Peak memory 206624 kb
Host smart-13ce665a-968b-4b94-89c7-8cfc4b8304db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676086027 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.1676086027
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.490478494
Short name T1109
Test name
Test status
Simulation time 13875121 ps
CPU time 0.88 seconds
Started Jul 14 06:57:18 PM PDT 24
Finished Jul 14 06:57:23 PM PDT 24
Peak memory 206828 kb
Host smart-4e0b3eb9-e0a7-4dd3-99e7-10699b160dbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490478494 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.490478494
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.721031159
Short name T1022
Test name
Test status
Simulation time 24014469 ps
CPU time 0.84 seconds
Started Jul 14 06:57:38 PM PDT 24
Finished Jul 14 06:57:40 PM PDT 24
Peak memory 206836 kb
Host smart-6b53fc34-153a-4d33-9f01-95b3cb43d661
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721031159 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.721031159
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.3038697405
Short name T1006
Test name
Test status
Simulation time 15313550 ps
CPU time 0.91 seconds
Started Jul 14 06:57:38 PM PDT 24
Finished Jul 14 06:57:41 PM PDT 24
Peak memory 206876 kb
Host smart-e259d235-2728-4fa9-90ae-9b8aa2d4295c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038697405 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3038697405
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.2283296166
Short name T1009
Test name
Test status
Simulation time 35207740 ps
CPU time 0.82 seconds
Started Jul 14 06:57:38 PM PDT 24
Finished Jul 14 06:57:41 PM PDT 24
Peak memory 206880 kb
Host smart-f0a8f733-2b68-41a0-9d8e-117e84ef9113
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283296166 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.2283296166
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.1304643286
Short name T1020
Test name
Test status
Simulation time 15415360 ps
CPU time 0.83 seconds
Started Jul 14 06:57:15 PM PDT 24
Finished Jul 14 06:57:19 PM PDT 24
Peak memory 206648 kb
Host smart-990e6194-143f-4ce7-9594-f098ebeabf70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304643286 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1304643286
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.3448285923
Short name T1123
Test name
Test status
Simulation time 18880187 ps
CPU time 0.84 seconds
Started Jul 14 06:57:14 PM PDT 24
Finished Jul 14 06:57:17 PM PDT 24
Peak memory 206832 kb
Host smart-b7fd6258-bab3-4457-985d-f58d747e306f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448285923 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3448285923
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.3282732191
Short name T1061
Test name
Test status
Simulation time 125198554 ps
CPU time 0.91 seconds
Started Jul 14 06:57:12 PM PDT 24
Finished Jul 14 06:57:15 PM PDT 24
Peak memory 206844 kb
Host smart-78671fa6-86db-425d-9cc4-90df6e70d66d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282732191 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3282732191
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1172894845
Short name T266
Test name
Test status
Simulation time 158516304 ps
CPU time 1.58 seconds
Started Jul 14 06:57:08 PM PDT 24
Finished Jul 14 06:57:10 PM PDT 24
Peak memory 206900 kb
Host smart-345d0985-41f3-4162-873c-80c0ff3b8fcd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172894845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.1172894845
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1885994071
Short name T1072
Test name
Test status
Simulation time 81412434 ps
CPU time 2.12 seconds
Started Jul 14 06:56:58 PM PDT 24
Finished Jul 14 06:57:02 PM PDT 24
Peak memory 206980 kb
Host smart-10f9dc3a-653d-4da3-9f02-1af23afc7052
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885994071 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.1885994071
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.355329677
Short name T1088
Test name
Test status
Simulation time 16662724 ps
CPU time 0.93 seconds
Started Jul 14 06:56:58 PM PDT 24
Finished Jul 14 06:57:01 PM PDT 24
Peak memory 206912 kb
Host smart-4fb2b1f7-6efe-4bc6-93a8-d4199ebcc850
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355329677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.355329677
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2132128311
Short name T1120
Test name
Test status
Simulation time 47076428 ps
CPU time 0.93 seconds
Started Jul 14 06:57:09 PM PDT 24
Finished Jul 14 06:57:11 PM PDT 24
Peak memory 206968 kb
Host smart-01d47244-4408-489a-a48a-7444ee68a4a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132128311 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.2132128311
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.999533695
Short name T274
Test name
Test status
Simulation time 50975247 ps
CPU time 0.92 seconds
Started Jul 14 06:57:08 PM PDT 24
Finished Jul 14 06:57:10 PM PDT 24
Peak memory 206900 kb
Host smart-2b1dca1f-06d6-47e5-9cde-3b354794e9bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999533695 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.999533695
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.2919752307
Short name T1127
Test name
Test status
Simulation time 41717952 ps
CPU time 0.85 seconds
Started Jul 14 06:57:02 PM PDT 24
Finished Jul 14 06:57:04 PM PDT 24
Peak memory 206828 kb
Host smart-7cc02c8a-2c1e-415a-ad1b-9c255f457046
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919752307 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2919752307
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1172831695
Short name T276
Test name
Test status
Simulation time 428007613 ps
CPU time 1.47 seconds
Started Jul 14 06:57:15 PM PDT 24
Finished Jul 14 06:57:19 PM PDT 24
Peak memory 206924 kb
Host smart-53f4733e-7983-4f9b-b184-47e7ca268da7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172831695 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.1172831695
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.132779370
Short name T1119
Test name
Test status
Simulation time 314729569 ps
CPU time 5.08 seconds
Started Jul 14 06:56:57 PM PDT 24
Finished Jul 14 06:57:04 PM PDT 24
Peak memory 215248 kb
Host smart-1d10cc20-4c92-41f8-a849-53a5cedf4b66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132779370 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.132779370
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2745765766
Short name T1084
Test name
Test status
Simulation time 168544175 ps
CPU time 2.37 seconds
Started Jul 14 06:56:58 PM PDT 24
Finished Jul 14 06:57:02 PM PDT 24
Peak memory 215116 kb
Host smart-e7758710-3855-46ba-9cbd-3eb575ea6f68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745765766 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.2745765766
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.2669107209
Short name T1010
Test name
Test status
Simulation time 12020587 ps
CPU time 0.85 seconds
Started Jul 14 06:57:35 PM PDT 24
Finished Jul 14 06:57:36 PM PDT 24
Peak memory 206856 kb
Host smart-2e1e3730-67a5-4873-bbeb-263462973f65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669107209 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.2669107209
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.1309071631
Short name T1003
Test name
Test status
Simulation time 93769000 ps
CPU time 0.78 seconds
Started Jul 14 06:57:17 PM PDT 24
Finished Jul 14 06:57:21 PM PDT 24
Peak memory 206648 kb
Host smart-4b3f4c35-f71d-4e91-843b-64905ea5781b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309071631 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1309071631
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.1959741474
Short name T1050
Test name
Test status
Simulation time 11955154 ps
CPU time 0.93 seconds
Started Jul 14 06:57:36 PM PDT 24
Finished Jul 14 06:57:38 PM PDT 24
Peak memory 206864 kb
Host smart-4c07c15f-ea27-4354-bb34-7159ca7b98a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959741474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.1959741474
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.316144485
Short name T1086
Test name
Test status
Simulation time 102805246 ps
CPU time 0.83 seconds
Started Jul 14 06:57:13 PM PDT 24
Finished Jul 14 06:57:16 PM PDT 24
Peak memory 206884 kb
Host smart-2a277b12-d608-4297-8799-af0a70625ef8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316144485 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.316144485
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.2198486676
Short name T1028
Test name
Test status
Simulation time 12903140 ps
CPU time 0.79 seconds
Started Jul 14 06:57:34 PM PDT 24
Finished Jul 14 06:57:35 PM PDT 24
Peak memory 206876 kb
Host smart-bb69f59a-e18e-4540-b70a-c0dbbdc12ad9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198486676 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2198486676
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.2695505433
Short name T1057
Test name
Test status
Simulation time 56324794 ps
CPU time 0.93 seconds
Started Jul 14 06:57:23 PM PDT 24
Finished Jul 14 06:57:26 PM PDT 24
Peak memory 206828 kb
Host smart-3a56e04d-9911-4e27-810a-9f6b959d6f64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695505433 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.2695505433
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1251510741
Short name T1021
Test name
Test status
Simulation time 124208510 ps
CPU time 0.83 seconds
Started Jul 14 06:57:33 PM PDT 24
Finished Jul 14 06:57:35 PM PDT 24
Peak memory 206688 kb
Host smart-1793c5d5-df34-4b50-a776-67b0085bb782
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251510741 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1251510741
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.512550894
Short name T1115
Test name
Test status
Simulation time 19600669 ps
CPU time 0.89 seconds
Started Jul 14 06:57:11 PM PDT 24
Finished Jul 14 06:57:13 PM PDT 24
Peak memory 206868 kb
Host smart-0aa6782d-647b-4ad2-b9a3-e2a2446c0b12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512550894 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.512550894
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.985072577
Short name T1106
Test name
Test status
Simulation time 77123353 ps
CPU time 0.78 seconds
Started Jul 14 06:57:14 PM PDT 24
Finished Jul 14 06:57:18 PM PDT 24
Peak memory 206648 kb
Host smart-343d3f69-7eeb-45ad-a257-3caa82e629f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985072577 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.985072577
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.3233261100
Short name T1128
Test name
Test status
Simulation time 37123329 ps
CPU time 0.85 seconds
Started Jul 14 06:57:34 PM PDT 24
Finished Jul 14 06:57:36 PM PDT 24
Peak memory 206756 kb
Host smart-4c442891-5501-4bcc-b277-392acba77298
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233261100 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.3233261100
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3160663337
Short name T1018
Test name
Test status
Simulation time 140640361 ps
CPU time 1.27 seconds
Started Jul 14 06:57:00 PM PDT 24
Finished Jul 14 06:57:03 PM PDT 24
Peak memory 215296 kb
Host smart-e3001bdc-fd2b-49e6-b4c9-72b5d75546fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160663337 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.3160663337
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.905869018
Short name T1001
Test name
Test status
Simulation time 21151795 ps
CPU time 0.94 seconds
Started Jul 14 06:57:09 PM PDT 24
Finished Jul 14 06:57:11 PM PDT 24
Peak memory 206908 kb
Host smart-5f3da0d3-bb39-4683-8f63-37f7e8f01981
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905869018 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.905869018
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.3191642775
Short name T1002
Test name
Test status
Simulation time 18492786 ps
CPU time 0.81 seconds
Started Jul 14 06:56:57 PM PDT 24
Finished Jul 14 06:57:00 PM PDT 24
Peak memory 206864 kb
Host smart-85a98b03-863c-404b-b9d2-f6ff1cb72c41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191642775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.3191642775
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2931230573
Short name T1035
Test name
Test status
Simulation time 47974736 ps
CPU time 1.16 seconds
Started Jul 14 06:57:15 PM PDT 24
Finished Jul 14 06:57:19 PM PDT 24
Peak memory 206936 kb
Host smart-a5fc426c-e57c-4128-820f-e4ed775c27c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931230573 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.2931230573
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.2013259600
Short name T999
Test name
Test status
Simulation time 390353089 ps
CPU time 3.84 seconds
Started Jul 14 06:57:03 PM PDT 24
Finished Jul 14 06:57:08 PM PDT 24
Peak memory 223404 kb
Host smart-c57ed456-5901-4999-8a01-f14d3f5df962
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013259600 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2013259600
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1278475111
Short name T294
Test name
Test status
Simulation time 60456135 ps
CPU time 1.9 seconds
Started Jul 14 06:57:05 PM PDT 24
Finished Jul 14 06:57:08 PM PDT 24
Peak memory 206992 kb
Host smart-dc877eec-584c-40a4-b143-9b0bd26aa7cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278475111 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1278475111
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3333146560
Short name T1067
Test name
Test status
Simulation time 33936295 ps
CPU time 1.46 seconds
Started Jul 14 06:57:04 PM PDT 24
Finished Jul 14 06:57:07 PM PDT 24
Peak memory 215168 kb
Host smart-63241afe-5e0e-4e87-9f4f-c2bb30d5f55f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333146560 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3333146560
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.1865354885
Short name T1042
Test name
Test status
Simulation time 13102502 ps
CPU time 0.87 seconds
Started Jul 14 06:57:00 PM PDT 24
Finished Jul 14 06:57:03 PM PDT 24
Peak memory 206924 kb
Host smart-b974cb93-e6fd-4d18-b878-23b64df23613
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865354885 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1865354885
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.1648997744
Short name T1012
Test name
Test status
Simulation time 37872026 ps
CPU time 0.83 seconds
Started Jul 14 06:57:00 PM PDT 24
Finished Jul 14 06:57:03 PM PDT 24
Peak memory 206692 kb
Host smart-4c706c8d-40a8-4044-9717-b4a78390abf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648997744 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.1648997744
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.897050005
Short name T1071
Test name
Test status
Simulation time 18859562 ps
CPU time 1.17 seconds
Started Jul 14 06:57:01 PM PDT 24
Finished Jul 14 06:57:04 PM PDT 24
Peak memory 206920 kb
Host smart-09aeee30-c7f9-41a4-8404-ab3cfdc8814b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897050005 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_out
standing.897050005
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3403138213
Short name T1017
Test name
Test status
Simulation time 185613311 ps
CPU time 2.14 seconds
Started Jul 14 06:56:59 PM PDT 24
Finished Jul 14 06:57:04 PM PDT 24
Peak memory 215228 kb
Host smart-484c3b09-faa0-4499-8bc8-36a71cd2971f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403138213 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3403138213
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3917835332
Short name T282
Test name
Test status
Simulation time 136319123 ps
CPU time 1.6 seconds
Started Jul 14 06:56:58 PM PDT 24
Finished Jul 14 06:57:01 PM PDT 24
Peak memory 215136 kb
Host smart-77a3a88a-8d75-4cc9-8c8e-07477642f926
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917835332 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.3917835332
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3821969283
Short name T1105
Test name
Test status
Simulation time 83596568 ps
CPU time 1.34 seconds
Started Jul 14 06:57:09 PM PDT 24
Finished Jul 14 06:57:11 PM PDT 24
Peak memory 215200 kb
Host smart-2a85eae2-4591-400c-9557-27def2b6a288
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821969283 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.3821969283
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1222558681
Short name T996
Test name
Test status
Simulation time 22320398 ps
CPU time 0.86 seconds
Started Jul 14 06:56:59 PM PDT 24
Finished Jul 14 06:57:01 PM PDT 24
Peak memory 206792 kb
Host smart-906dec1b-7185-40a0-984e-7d53b9427fb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222558681 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1222558681
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.3687845370
Short name T1045
Test name
Test status
Simulation time 89948023 ps
CPU time 0.84 seconds
Started Jul 14 06:57:04 PM PDT 24
Finished Jul 14 06:57:06 PM PDT 24
Peak memory 206736 kb
Host smart-f2fc583a-5ba3-45b3-9f1b-80e6a9ccdd45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687845370 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.3687845370
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1142543411
Short name T273
Test name
Test status
Simulation time 15002256 ps
CPU time 1.08 seconds
Started Jul 14 06:57:00 PM PDT 24
Finished Jul 14 06:57:03 PM PDT 24
Peak memory 206864 kb
Host smart-cd16db91-e030-46a0-919e-5b49b9fab76b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142543411 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.1142543411
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2160270545
Short name T1007
Test name
Test status
Simulation time 47300133 ps
CPU time 1.97 seconds
Started Jul 14 06:57:00 PM PDT 24
Finished Jul 14 06:57:04 PM PDT 24
Peak memory 215164 kb
Host smart-2c4ef45d-44eb-4467-b1f8-3c299f860f40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160270545 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2160270545
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1871748676
Short name T1080
Test name
Test status
Simulation time 169053354 ps
CPU time 3.54 seconds
Started Jul 14 06:57:06 PM PDT 24
Finished Jul 14 06:57:10 PM PDT 24
Peak memory 206968 kb
Host smart-fb4689f5-322a-47a1-aef5-f8c2f122aa85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871748676 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.1871748676
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1976500107
Short name T1056
Test name
Test status
Simulation time 23191465 ps
CPU time 1.17 seconds
Started Jul 14 06:57:13 PM PDT 24
Finished Jul 14 06:57:16 PM PDT 24
Peak memory 215168 kb
Host smart-753440b1-86d7-43fe-b279-d2cc4dd09b40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976500107 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1976500107
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.1226262214
Short name T268
Test name
Test status
Simulation time 37184063 ps
CPU time 0.81 seconds
Started Jul 14 06:57:17 PM PDT 24
Finished Jul 14 06:57:22 PM PDT 24
Peak memory 206900 kb
Host smart-92883855-73da-4ec1-83d0-a5fdf6acb9ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226262214 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1226262214
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.2385887815
Short name T1011
Test name
Test status
Simulation time 37339832 ps
CPU time 0.82 seconds
Started Jul 14 06:56:56 PM PDT 24
Finished Jul 14 06:56:59 PM PDT 24
Peak memory 206816 kb
Host smart-e02fe88a-f0f6-46d4-a54e-8675fde74032
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385887815 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.2385887815
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2930478797
Short name T1065
Test name
Test status
Simulation time 133388448 ps
CPU time 0.99 seconds
Started Jul 14 06:57:05 PM PDT 24
Finished Jul 14 06:57:06 PM PDT 24
Peak memory 206964 kb
Host smart-a951bdb6-4297-4f1a-921e-0e1083fe7d45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930478797 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.2930478797
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.4018168077
Short name T1037
Test name
Test status
Simulation time 122356660 ps
CPU time 2.23 seconds
Started Jul 14 06:57:10 PM PDT 24
Finished Jul 14 06:57:14 PM PDT 24
Peak memory 215124 kb
Host smart-7c03759b-7f80-405b-9bcf-aaf809d889d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018168077 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.4018168077
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2012934764
Short name T297
Test name
Test status
Simulation time 1351862777 ps
CPU time 2.74 seconds
Started Jul 14 06:56:57 PM PDT 24
Finished Jul 14 06:57:02 PM PDT 24
Peak memory 206936 kb
Host smart-09d0823c-0b0b-4576-8f7f-32740d13441c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012934764 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2012934764
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.473112639
Short name T1077
Test name
Test status
Simulation time 41453122 ps
CPU time 1.13 seconds
Started Jul 14 06:57:09 PM PDT 24
Finished Jul 14 06:57:11 PM PDT 24
Peak memory 216988 kb
Host smart-0163d0d9-2ef0-43b1-aff9-355fcf1ed29a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473112639 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.473112639
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2900659310
Short name T1027
Test name
Test status
Simulation time 12406623 ps
CPU time 0.87 seconds
Started Jul 14 06:57:11 PM PDT 24
Finished Jul 14 06:57:13 PM PDT 24
Peak memory 206884 kb
Host smart-b76703f6-8f1d-4abd-aee6-d4f2bf81def9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900659310 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2900659310
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.487363889
Short name T1108
Test name
Test status
Simulation time 55771942 ps
CPU time 0.89 seconds
Started Jul 14 06:57:03 PM PDT 24
Finished Jul 14 06:57:06 PM PDT 24
Peak memory 206832 kb
Host smart-adecb928-7c75-4cf2-952f-2a36e9ffaeab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487363889 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.487363889
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1818205397
Short name T1121
Test name
Test status
Simulation time 43731338 ps
CPU time 1.09 seconds
Started Jul 14 06:57:22 PM PDT 24
Finished Jul 14 06:57:25 PM PDT 24
Peak memory 206940 kb
Host smart-279b6191-66e9-422e-a0f5-2b90d4a88901
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818205397 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1818205397
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.2060590192
Short name T1058
Test name
Test status
Simulation time 61926641 ps
CPU time 2.13 seconds
Started Jul 14 06:57:12 PM PDT 24
Finished Jul 14 06:57:16 PM PDT 24
Peak memory 215272 kb
Host smart-26909215-6909-4934-8eba-15a1edcd6ffa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060590192 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.2060590192
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3838551260
Short name T284
Test name
Test status
Simulation time 101285410 ps
CPU time 1.65 seconds
Started Jul 14 06:57:21 PM PDT 24
Finished Jul 14 06:57:28 PM PDT 24
Peak memory 206936 kb
Host smart-d14decde-4b34-4eb5-bb72-d7743b04bd22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838551260 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3838551260
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert_test.2121678323
Short name T555
Test name
Test status
Simulation time 69747412 ps
CPU time 1.03 seconds
Started Jul 14 06:57:53 PM PDT 24
Finished Jul 14 06:57:55 PM PDT 24
Peak memory 207052 kb
Host smart-c42f1082-51df-489d-a401-034639691e9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121678323 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2121678323
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.1318889247
Short name T952
Test name
Test status
Simulation time 47931797 ps
CPU time 1.07 seconds
Started Jul 14 06:57:43 PM PDT 24
Finished Jul 14 06:57:46 PM PDT 24
Peak memory 219960 kb
Host smart-a0932e80-75b3-47be-a654-1441b9c90d08
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318889247 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.1318889247
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.1020951116
Short name T572
Test name
Test status
Simulation time 76725808 ps
CPU time 0.83 seconds
Started Jul 14 06:58:17 PM PDT 24
Finished Jul 14 06:58:24 PM PDT 24
Peak memory 218456 kb
Host smart-ca8ead1b-787c-4f30-a1e3-bc22bfb51dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020951116 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1020951116
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.2039207854
Short name T412
Test name
Test status
Simulation time 125238628 ps
CPU time 1.36 seconds
Started Jul 14 06:57:55 PM PDT 24
Finished Jul 14 06:57:58 PM PDT 24
Peak memory 217572 kb
Host smart-69013121-0318-40a9-944c-2efb7c59241a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039207854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2039207854
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.1767818969
Short name T782
Test name
Test status
Simulation time 23724942 ps
CPU time 1.1 seconds
Started Jul 14 06:57:50 PM PDT 24
Finished Jul 14 06:57:52 PM PDT 24
Peak memory 215900 kb
Host smart-6d66e4d9-e30a-4fd9-99d0-9dedd9056522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767818969 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1767818969
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.2826281998
Short name T887
Test name
Test status
Simulation time 28223838 ps
CPU time 0.96 seconds
Started Jul 14 06:57:59 PM PDT 24
Finished Jul 14 06:58:01 PM PDT 24
Peak memory 207412 kb
Host smart-2217da7a-191f-4164-bec2-5c25cab51999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826281998 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.2826281998
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_smoke.992067951
Short name T688
Test name
Test status
Simulation time 19927883 ps
CPU time 1.01 seconds
Started Jul 14 06:57:49 PM PDT 24
Finished Jul 14 06:57:51 PM PDT 24
Peak memory 215576 kb
Host smart-757eab6e-29c7-4749-8e19-e2c15264f71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992067951 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.992067951
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.2132426091
Short name T528
Test name
Test status
Simulation time 395999004 ps
CPU time 1.84 seconds
Started Jul 14 06:58:07 PM PDT 24
Finished Jul 14 06:58:14 PM PDT 24
Peak memory 217716 kb
Host smart-3c317013-a790-4be3-ab4f-a7857dd4c82f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132426091 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.2132426091
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_alert_test.1688948689
Short name T980
Test name
Test status
Simulation time 33829839 ps
CPU time 0.94 seconds
Started Jul 14 06:58:00 PM PDT 24
Finished Jul 14 06:58:02 PM PDT 24
Peak memory 207120 kb
Host smart-b2023dda-323e-45cc-84dd-ea3e87347fa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688948689 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1688948689
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.2569813756
Short name T206
Test name
Test status
Simulation time 69472267 ps
CPU time 0.87 seconds
Started Jul 14 06:58:02 PM PDT 24
Finished Jul 14 06:58:04 PM PDT 24
Peak memory 216548 kb
Host smart-5e47cb66-caea-4f66-bf3c-3f824e321faf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569813756 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.2569813756
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_err.3389507315
Short name T491
Test name
Test status
Simulation time 21575887 ps
CPU time 0.89 seconds
Started Jul 14 06:57:59 PM PDT 24
Finished Jul 14 06:58:01 PM PDT 24
Peak memory 218468 kb
Host smart-f3ec4a5f-1298-4887-a3b8-c27a7e1dfb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389507315 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.3389507315
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.2289641480
Short name T348
Test name
Test status
Simulation time 96443185 ps
CPU time 1.38 seconds
Started Jul 14 06:58:00 PM PDT 24
Finished Jul 14 06:58:02 PM PDT 24
Peak memory 219548 kb
Host smart-ea98d68b-695b-4ab6-b929-019336fb73c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289641480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2289641480
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.310229735
Short name T634
Test name
Test status
Simulation time 24113734 ps
CPU time 0.89 seconds
Started Jul 14 06:57:52 PM PDT 24
Finished Jul 14 06:57:55 PM PDT 24
Peak memory 216036 kb
Host smart-f1aea585-4201-467f-ae6f-6a7bde3967b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310229735 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.310229735
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.1216423150
Short name T989
Test name
Test status
Simulation time 61488421 ps
CPU time 1 seconds
Started Jul 14 06:57:52 PM PDT 24
Finished Jul 14 06:57:54 PM PDT 24
Peak memory 207412 kb
Host smart-3864270c-6536-4ec3-baf6-13e341370f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216423150 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.1216423150
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.3876003216
Short name T18
Test name
Test status
Simulation time 915678629 ps
CPU time 7.73 seconds
Started Jul 14 06:58:08 PM PDT 24
Finished Jul 14 06:58:22 PM PDT 24
Peak memory 238088 kb
Host smart-43e008fb-e179-475c-ba0f-3a6cac674314
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876003216 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.3876003216
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.2940313957
Short name T363
Test name
Test status
Simulation time 31619406 ps
CPU time 0.97 seconds
Started Jul 14 06:57:56 PM PDT 24
Finished Jul 14 06:57:58 PM PDT 24
Peak memory 215572 kb
Host smart-5b2bf3cc-cbef-4261-b2bd-c6185708f014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940313957 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.2940313957
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.503762001
Short name T981
Test name
Test status
Simulation time 693068384 ps
CPU time 4.17 seconds
Started Jul 14 06:58:20 PM PDT 24
Finished Jul 14 06:58:29 PM PDT 24
Peak memory 217468 kb
Host smart-101ad641-a6ca-49cc-99ea-cd3d32d6b1fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503762001 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.503762001
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_alert.946194817
Short name T700
Test name
Test status
Simulation time 30167843 ps
CPU time 1.19 seconds
Started Jul 14 06:58:11 PM PDT 24
Finished Jul 14 06:58:19 PM PDT 24
Peak memory 220260 kb
Host smart-a453d6c7-60fd-4cf0-96de-6a265675af58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946194817 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.946194817
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.1793616413
Short name T795
Test name
Test status
Simulation time 19244714 ps
CPU time 0.99 seconds
Started Jul 14 06:58:18 PM PDT 24
Finished Jul 14 06:58:25 PM PDT 24
Peak memory 215120 kb
Host smart-e883a151-6342-4a9d-8a12-a08de73bb188
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793616413 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.1793616413
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.1639274090
Short name T635
Test name
Test status
Simulation time 13134378 ps
CPU time 0.91 seconds
Started Jul 14 06:58:29 PM PDT 24
Finished Jul 14 06:58:31 PM PDT 24
Peak memory 215888 kb
Host smart-f535d90f-9b72-4f2a-9d3e-5f61ad48ab3e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639274090 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.1639274090
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.4003303176
Short name T446
Test name
Test status
Simulation time 88843673 ps
CPU time 1.13 seconds
Started Jul 14 06:58:11 PM PDT 24
Finished Jul 14 06:58:19 PM PDT 24
Peak memory 217148 kb
Host smart-b5a7d4e6-c6ea-445e-92ad-34cab6a89c7d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003303176 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.4003303176
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.1509007821
Short name T157
Test name
Test status
Simulation time 34452403 ps
CPU time 0.9 seconds
Started Jul 14 06:58:29 PM PDT 24
Finished Jul 14 06:58:32 PM PDT 24
Peak memory 220164 kb
Host smart-066f7a28-7c2d-40cb-9a97-92203537e504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509007821 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1509007821
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.714415634
Short name T744
Test name
Test status
Simulation time 57725851 ps
CPU time 1.25 seconds
Started Jul 14 06:58:21 PM PDT 24
Finished Jul 14 06:58:26 PM PDT 24
Peak memory 218836 kb
Host smart-8ec7a12e-2250-47f4-b7eb-c0afd561a25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714415634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.714415634
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.3874072647
Short name T649
Test name
Test status
Simulation time 33688592 ps
CPU time 1.02 seconds
Started Jul 14 06:58:31 PM PDT 24
Finished Jul 14 06:58:33 PM PDT 24
Peak memory 224260 kb
Host smart-bd2ac103-cdb2-4269-9be5-dddb1604e44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874072647 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3874072647
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.82416368
Short name T964
Test name
Test status
Simulation time 52704058 ps
CPU time 0.9 seconds
Started Jul 14 06:58:30 PM PDT 24
Finished Jul 14 06:58:33 PM PDT 24
Peak memory 215556 kb
Host smart-2a27e8ba-6660-43dc-b933-b1e50b296063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82416368 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.82416368
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.3249849895
Short name T726
Test name
Test status
Simulation time 403367347 ps
CPU time 7.43 seconds
Started Jul 14 06:58:03 PM PDT 24
Finished Jul 14 06:58:14 PM PDT 24
Peak memory 217392 kb
Host smart-ce90295f-bd33-4faf-be2b-5755a2265e82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249849895 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.3249849895
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.4203223161
Short name T231
Test name
Test status
Simulation time 274214339455 ps
CPU time 2230.29 seconds
Started Jul 14 06:58:30 PM PDT 24
Finished Jul 14 07:35:42 PM PDT 24
Peak memory 227492 kb
Host smart-9e657b58-cabc-40d8-b693-7f40259a796f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203223161 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.4203223161
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.1441702921
Short name T594
Test name
Test status
Simulation time 349023093 ps
CPU time 1.24 seconds
Started Jul 14 06:59:36 PM PDT 24
Finished Jul 14 06:59:40 PM PDT 24
Peak memory 218740 kb
Host smart-f261d337-0c08-4546-8c0f-daeab2fb982a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441702921 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.1441702921
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.3976883067
Short name T520
Test name
Test status
Simulation time 96224912 ps
CPU time 1.21 seconds
Started Jul 14 06:59:08 PM PDT 24
Finished Jul 14 06:59:14 PM PDT 24
Peak memory 220424 kb
Host smart-1e0b18df-da22-4cb4-bd54-03d3f36d3d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976883067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.3976883067
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.2340994611
Short name T106
Test name
Test status
Simulation time 30923218 ps
CPU time 1.3 seconds
Started Jul 14 06:59:23 PM PDT 24
Finished Jul 14 06:59:26 PM PDT 24
Peak memory 219688 kb
Host smart-dfa6c338-d667-4e5d-a1d9-0bd5cbb09125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340994611 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.2340994611
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/102.edn_alert.1763213634
Short name T959
Test name
Test status
Simulation time 23192783 ps
CPU time 1.13 seconds
Started Jul 14 06:59:25 PM PDT 24
Finished Jul 14 06:59:28 PM PDT 24
Peak memory 219056 kb
Host smart-40c10dfe-72de-4d13-96d3-54af4ae78f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763213634 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.1763213634
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.3855009881
Short name T657
Test name
Test status
Simulation time 70184052 ps
CPU time 1.06 seconds
Started Jul 14 06:59:23 PM PDT 24
Finished Jul 14 06:59:26 PM PDT 24
Peak memory 217696 kb
Host smart-9831b7c2-21fe-4c99-9f38-e6947455e4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855009881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.3855009881
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.2317843771
Short name T871
Test name
Test status
Simulation time 57217748 ps
CPU time 1.19 seconds
Started Jul 14 06:59:34 PM PDT 24
Finished Jul 14 06:59:37 PM PDT 24
Peak memory 216056 kb
Host smart-eafac0db-10c0-4e15-879b-3fad620666f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317843771 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.2317843771
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.2102472543
Short name T374
Test name
Test status
Simulation time 41442344 ps
CPU time 1.36 seconds
Started Jul 14 06:59:29 PM PDT 24
Finished Jul 14 06:59:34 PM PDT 24
Peak memory 217724 kb
Host smart-991376a7-3004-4150-9d71-a0e57b627183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102472543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.2102472543
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.2675510765
Short name T298
Test name
Test status
Simulation time 36377521 ps
CPU time 1.07 seconds
Started Jul 14 06:59:20 PM PDT 24
Finished Jul 14 06:59:23 PM PDT 24
Peak memory 220420 kb
Host smart-8c5d5a05-a45a-4ac9-bec0-7ff4dcb5b4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675510765 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.2675510765
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.3438205951
Short name T778
Test name
Test status
Simulation time 53342525 ps
CPU time 1.63 seconds
Started Jul 14 06:59:27 PM PDT 24
Finished Jul 14 06:59:31 PM PDT 24
Peak memory 219056 kb
Host smart-1cf2d1ba-677d-4c45-af4f-63d5ce2d00c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438205951 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.3438205951
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.3601518394
Short name T307
Test name
Test status
Simulation time 23665451 ps
CPU time 1.23 seconds
Started Jul 14 06:59:13 PM PDT 24
Finished Jul 14 06:59:19 PM PDT 24
Peak memory 218860 kb
Host smart-d6c1ae83-9139-4893-bf82-7cc5b6eec49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601518394 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.3601518394
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/106.edn_alert.2680300513
Short name T812
Test name
Test status
Simulation time 39244487 ps
CPU time 1.19 seconds
Started Jul 14 06:59:30 PM PDT 24
Finished Jul 14 06:59:35 PM PDT 24
Peak memory 219012 kb
Host smart-9765e521-8b9b-445c-8aef-4dced04a558b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680300513 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.2680300513
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.700096277
Short name T234
Test name
Test status
Simulation time 89568160 ps
CPU time 1.39 seconds
Started Jul 14 06:59:48 PM PDT 24
Finished Jul 14 06:59:51 PM PDT 24
Peak memory 219180 kb
Host smart-815dba3b-2903-4967-84fb-e9cde215ece1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700096277 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.700096277
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.643661379
Short name T216
Test name
Test status
Simulation time 24573855 ps
CPU time 1.23 seconds
Started Jul 14 06:59:21 PM PDT 24
Finished Jul 14 06:59:24 PM PDT 24
Peak memory 219120 kb
Host smart-73d071a8-e7c0-40dd-b2b0-57c1a2a47672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643661379 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.643661379
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.2352023839
Short name T493
Test name
Test status
Simulation time 60214181 ps
CPU time 1.41 seconds
Started Jul 14 06:59:24 PM PDT 24
Finished Jul 14 06:59:28 PM PDT 24
Peak memory 219116 kb
Host smart-95c9dcd2-77de-42b0-988f-d4be2da6913d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352023839 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2352023839
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.2674197928
Short name T874
Test name
Test status
Simulation time 82871324 ps
CPU time 1.12 seconds
Started Jul 14 06:59:18 PM PDT 24
Finished Jul 14 06:59:21 PM PDT 24
Peak memory 220992 kb
Host smart-94cec6a8-3bfa-479e-bb5a-2353abd82d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674197928 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.2674197928
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.1229569374
Short name T646
Test name
Test status
Simulation time 104899008 ps
CPU time 1.48 seconds
Started Jul 14 06:59:26 PM PDT 24
Finished Jul 14 06:59:30 PM PDT 24
Peak memory 219988 kb
Host smart-b7699773-a5b9-498e-8b38-cab05079084b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229569374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.1229569374
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.2731073268
Short name T480
Test name
Test status
Simulation time 62549566 ps
CPU time 1.15 seconds
Started Jul 14 06:59:31 PM PDT 24
Finished Jul 14 06:59:35 PM PDT 24
Peak memory 219020 kb
Host smart-6b082891-d2ba-4304-8c12-23303e30eafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731073268 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.2731073268
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.1883540229
Short name T476
Test name
Test status
Simulation time 32605270 ps
CPU time 1.34 seconds
Started Jul 14 06:59:11 PM PDT 24
Finished Jul 14 06:59:18 PM PDT 24
Peak memory 220360 kb
Host smart-f2c89050-6407-480e-b99d-affeec7594bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883540229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.1883540229
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.3083129604
Short name T450
Test name
Test status
Simulation time 199606382 ps
CPU time 1.17 seconds
Started Jul 14 06:58:51 PM PDT 24
Finished Jul 14 06:58:54 PM PDT 24
Peak memory 219460 kb
Host smart-b333f362-e988-4604-97d3-0967dd283e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083129604 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.3083129604
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.3865794705
Short name T413
Test name
Test status
Simulation time 12795498 ps
CPU time 0.89 seconds
Started Jul 14 06:58:07 PM PDT 24
Finished Jul 14 06:58:12 PM PDT 24
Peak memory 215128 kb
Host smart-51fd2557-a020-4026-8cc3-a07a1c0aa06c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865794705 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.3865794705
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.1039310667
Short name T828
Test name
Test status
Simulation time 12295785 ps
CPU time 0.9 seconds
Started Jul 14 06:58:07 PM PDT 24
Finished Jul 14 06:58:12 PM PDT 24
Peak memory 216812 kb
Host smart-b3e5a8bd-2e40-454f-a8a1-bc936c2ba361
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039310667 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.1039310667
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_err.3717508252
Short name T830
Test name
Test status
Simulation time 22969355 ps
CPU time 1.09 seconds
Started Jul 14 06:58:07 PM PDT 24
Finished Jul 14 06:58:13 PM PDT 24
Peak memory 218640 kb
Host smart-ca87a78c-14f5-4a0b-8a18-0ae230d9485c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717508252 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.3717508252
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.20454205
Short name T674
Test name
Test status
Simulation time 47872364 ps
CPU time 1.18 seconds
Started Jul 14 06:58:04 PM PDT 24
Finished Jul 14 06:58:09 PM PDT 24
Peak memory 217628 kb
Host smart-ad08e99e-d994-4ee4-9320-2a7c841a942a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20454205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.20454205
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.2454009680
Short name T914
Test name
Test status
Simulation time 74604421 ps
CPU time 0.87 seconds
Started Jul 14 06:58:10 PM PDT 24
Finished Jul 14 06:58:18 PM PDT 24
Peak memory 215740 kb
Host smart-11b65580-b21a-46c6-a7f5-ae83593735df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454009680 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.2454009680
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.3634847890
Short name T472
Test name
Test status
Simulation time 60047102 ps
CPU time 0.96 seconds
Started Jul 14 06:58:15 PM PDT 24
Finished Jul 14 06:58:23 PM PDT 24
Peak memory 215608 kb
Host smart-274fb615-828f-4769-8153-ef863c2fe01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634847890 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.3634847890
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.57931429
Short name T343
Test name
Test status
Simulation time 492521175 ps
CPU time 2.76 seconds
Started Jul 14 06:58:03 PM PDT 24
Finished Jul 14 06:58:08 PM PDT 24
Peak memory 217792 kb
Host smart-a29e30a6-3721-46ea-97b2-e5aeafc1be66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57931429 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.57931429
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/110.edn_alert.4019656987
Short name T977
Test name
Test status
Simulation time 83771257 ps
CPU time 1.2 seconds
Started Jul 14 06:59:33 PM PDT 24
Finished Jul 14 06:59:37 PM PDT 24
Peak memory 221252 kb
Host smart-6f22cde2-ccf2-43ec-ae83-fd3ed88a075b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019656987 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.4019656987
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.2487771685
Short name T699
Test name
Test status
Simulation time 142339104 ps
CPU time 1.21 seconds
Started Jul 14 06:59:12 PM PDT 24
Finished Jul 14 06:59:18 PM PDT 24
Peak memory 220140 kb
Host smart-6f8bc652-f0ce-4d02-841a-9a4dce3db342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487771685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2487771685
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.1462654475
Short name T281
Test name
Test status
Simulation time 84425284 ps
CPU time 1.24 seconds
Started Jul 14 06:59:47 PM PDT 24
Finished Jul 14 06:59:49 PM PDT 24
Peak memory 218756 kb
Host smart-b7b4357e-a9da-4159-8bd1-abe48bc8429b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462654475 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.1462654475
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.385847247
Short name T727
Test name
Test status
Simulation time 36925078 ps
CPU time 1.32 seconds
Started Jul 14 06:59:27 PM PDT 24
Finished Jul 14 06:59:31 PM PDT 24
Peak memory 217668 kb
Host smart-2c442b8c-b957-4386-b1ce-c28dc995fc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385847247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.385847247
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.1835268590
Short name T411
Test name
Test status
Simulation time 166975025 ps
CPU time 1.16 seconds
Started Jul 14 06:59:34 PM PDT 24
Finished Jul 14 06:59:38 PM PDT 24
Peak memory 219072 kb
Host smart-1c1ad91b-643e-4b2c-b7b6-dc40158162c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835268590 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.1835268590
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.3914213902
Short name T41
Test name
Test status
Simulation time 109782593 ps
CPU time 1.56 seconds
Started Jul 14 06:59:29 PM PDT 24
Finished Jul 14 06:59:35 PM PDT 24
Peak memory 219540 kb
Host smart-7f912dbf-96f7-4407-82de-1bda18777b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914213902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.3914213902
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.2346836550
Short name T835
Test name
Test status
Simulation time 63581447 ps
CPU time 1.16 seconds
Started Jul 14 06:59:26 PM PDT 24
Finished Jul 14 06:59:29 PM PDT 24
Peak memory 220056 kb
Host smart-503d8713-bbe6-44a7-8966-930668574c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346836550 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.2346836550
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.3563844157
Short name T911
Test name
Test status
Simulation time 50017752 ps
CPU time 1.51 seconds
Started Jul 14 07:00:07 PM PDT 24
Finished Jul 14 07:00:16 PM PDT 24
Peak memory 218640 kb
Host smart-7b486a18-664d-4e50-a11a-7a48b694c8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563844157 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.3563844157
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.2413628148
Short name T460
Test name
Test status
Simulation time 42474060 ps
CPU time 1.14 seconds
Started Jul 14 06:59:33 PM PDT 24
Finished Jul 14 06:59:36 PM PDT 24
Peak memory 220224 kb
Host smart-819610f9-d81d-4a9f-ad1c-d7b04c759144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413628148 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.2413628148
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.4030542810
Short name T60
Test name
Test status
Simulation time 35995057 ps
CPU time 1.25 seconds
Started Jul 14 06:59:52 PM PDT 24
Finished Jul 14 06:59:55 PM PDT 24
Peak memory 218868 kb
Host smart-1ad7e75c-9bbb-40a9-8f9d-aebdb3cd74c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030542810 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.4030542810
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.1509687779
Short name T236
Test name
Test status
Simulation time 25679927 ps
CPU time 1.14 seconds
Started Jul 14 06:59:42 PM PDT 24
Finished Jul 14 06:59:46 PM PDT 24
Peak memory 218860 kb
Host smart-a1a6d6f5-31f5-4868-a244-321f0472ee12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509687779 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.1509687779
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.2009736171
Short name T365
Test name
Test status
Simulation time 57966534 ps
CPU time 1.25 seconds
Started Jul 14 06:59:31 PM PDT 24
Finished Jul 14 06:59:35 PM PDT 24
Peak memory 217584 kb
Host smart-fa7bc1b5-9949-48eb-b3a4-5021b1a852d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009736171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.2009736171
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.3648729041
Short name T611
Test name
Test status
Simulation time 51021746 ps
CPU time 1.15 seconds
Started Jul 14 06:59:24 PM PDT 24
Finished Jul 14 06:59:27 PM PDT 24
Peak memory 220216 kb
Host smart-43101f37-842e-4d8a-80fb-efa57e8e5cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648729041 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.3648729041
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.1229972358
Short name T696
Test name
Test status
Simulation time 53941261 ps
CPU time 1.25 seconds
Started Jul 14 06:59:28 PM PDT 24
Finished Jul 14 06:59:33 PM PDT 24
Peak memory 218772 kb
Host smart-0f9a358e-32a1-4022-9493-73842776a9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229972358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1229972358
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.3269527393
Short name T104
Test name
Test status
Simulation time 36060239 ps
CPU time 1.31 seconds
Started Jul 14 06:59:36 PM PDT 24
Finished Jul 14 06:59:40 PM PDT 24
Peak memory 220252 kb
Host smart-5adf7ce4-e3d6-4d0c-a346-fdc3ae58da5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269527393 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.3269527393
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.1789088622
Short name T500
Test name
Test status
Simulation time 79054089 ps
CPU time 1.19 seconds
Started Jul 14 06:59:33 PM PDT 24
Finished Jul 14 06:59:36 PM PDT 24
Peak memory 220348 kb
Host smart-f37f6e37-0dcf-41da-9b9f-50cbdce00377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789088622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.1789088622
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.2285428824
Short name T164
Test name
Test status
Simulation time 54725993 ps
CPU time 1.07 seconds
Started Jul 14 06:59:35 PM PDT 24
Finished Jul 14 06:59:39 PM PDT 24
Peak memory 219944 kb
Host smart-ea278a36-f410-4531-adbd-391dacf438e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285428824 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.2285428824
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.2200971713
Short name T662
Test name
Test status
Simulation time 88727621 ps
CPU time 1.12 seconds
Started Jul 14 06:59:47 PM PDT 24
Finished Jul 14 06:59:50 PM PDT 24
Peak memory 219116 kb
Host smart-052429fe-9141-4ab2-911b-3ee5e7edde59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200971713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.2200971713
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.31970523
Short name T779
Test name
Test status
Simulation time 72124836 ps
CPU time 1.06 seconds
Started Jul 14 06:59:24 PM PDT 24
Finished Jul 14 06:59:27 PM PDT 24
Peak memory 217504 kb
Host smart-27755b19-82e5-47a7-91b2-8a9dd90abc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31970523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.31970523
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.1431349543
Short name T303
Test name
Test status
Simulation time 27661200 ps
CPU time 1.21 seconds
Started Jul 14 06:58:18 PM PDT 24
Finished Jul 14 06:58:25 PM PDT 24
Peak memory 220076 kb
Host smart-1711580e-21d2-47da-8742-3ccfa1d5d7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431349543 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.1431349543
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.1367894403
Short name T781
Test name
Test status
Simulation time 11269723 ps
CPU time 0.8 seconds
Started Jul 14 06:58:23 PM PDT 24
Finished Jul 14 06:58:27 PM PDT 24
Peak memory 207052 kb
Host smart-e5bbf492-3ffd-447e-8b49-87dca088e90a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367894403 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.1367894403
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_err.2520814187
Short name T614
Test name
Test status
Simulation time 34497352 ps
CPU time 0.86 seconds
Started Jul 14 06:58:25 PM PDT 24
Finished Jul 14 06:58:28 PM PDT 24
Peak memory 218692 kb
Host smart-06a53ee3-5aa6-4cde-99b5-1586c1a06934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520814187 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.2520814187
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.659853325
Short name T436
Test name
Test status
Simulation time 430946825 ps
CPU time 4.63 seconds
Started Jul 14 06:58:09 PM PDT 24
Finished Jul 14 06:58:20 PM PDT 24
Peak memory 218792 kb
Host smart-bd081c26-660a-4179-be53-462b41717ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659853325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.659853325
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_smoke.2850691444
Short name T443
Test name
Test status
Simulation time 28641302 ps
CPU time 0.91 seconds
Started Jul 14 06:58:30 PM PDT 24
Finished Jul 14 06:58:32 PM PDT 24
Peak memory 215600 kb
Host smart-f21cb466-6167-4b20-9b6a-811e9910d006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850691444 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2850691444
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.3887404032
Short name T494
Test name
Test status
Simulation time 130500242 ps
CPU time 2.78 seconds
Started Jul 14 06:58:49 PM PDT 24
Finished Jul 14 06:58:54 PM PDT 24
Peak memory 215752 kb
Host smart-6d1372af-103a-4223-8de9-ef19a34196bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887404032 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.3887404032
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.3116518327
Short name T232
Test name
Test status
Simulation time 303515501543 ps
CPU time 1525.57 seconds
Started Jul 14 06:58:31 PM PDT 24
Finished Jul 14 07:24:00 PM PDT 24
Peak memory 224920 kb
Host smart-638e1051-21ea-49dd-a15e-e581481399e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116518327 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.3116518327
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.894876619
Short name T863
Test name
Test status
Simulation time 43185260 ps
CPU time 1.57 seconds
Started Jul 14 06:59:27 PM PDT 24
Finished Jul 14 06:59:32 PM PDT 24
Peak memory 218988 kb
Host smart-d536ce3b-4965-4d10-ada1-2ed6d673500f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894876619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.894876619
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.3201365488
Short name T793
Test name
Test status
Simulation time 34651833 ps
CPU time 1.05 seconds
Started Jul 14 06:59:28 PM PDT 24
Finished Jul 14 06:59:33 PM PDT 24
Peak memory 219064 kb
Host smart-690a14d3-9ed1-495b-8cd9-9269a8077656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201365488 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.3201365488
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/122.edn_alert.325856983
Short name T82
Test name
Test status
Simulation time 47168141 ps
CPU time 1.16 seconds
Started Jul 14 06:59:30 PM PDT 24
Finished Jul 14 06:59:35 PM PDT 24
Peak memory 220264 kb
Host smart-1f40c92a-614a-4d3e-be95-ed467d2c6a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325856983 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.325856983
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.2335395397
Short name T523
Test name
Test status
Simulation time 38376873 ps
CPU time 1.39 seconds
Started Jul 14 06:59:47 PM PDT 24
Finished Jul 14 06:59:49 PM PDT 24
Peak memory 218600 kb
Host smart-9e758dbe-8c86-4f2e-9449-c05120bc2ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335395397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.2335395397
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.165321890
Short name T74
Test name
Test status
Simulation time 32044092 ps
CPU time 1.16 seconds
Started Jul 14 06:59:30 PM PDT 24
Finished Jul 14 06:59:35 PM PDT 24
Peak memory 221464 kb
Host smart-57b58600-f319-4099-b6f9-ec8450600579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165321890 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.165321890
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.672961266
Short name T636
Test name
Test status
Simulation time 52425324 ps
CPU time 1.27 seconds
Started Jul 14 06:59:35 PM PDT 24
Finished Jul 14 06:59:38 PM PDT 24
Peak memory 219084 kb
Host smart-3451faf4-94b9-4a0d-bbc1-2bffdadac873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672961266 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.672961266
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.1662349989
Short name T917
Test name
Test status
Simulation time 27148293 ps
CPU time 1.21 seconds
Started Jul 14 06:59:39 PM PDT 24
Finished Jul 14 06:59:44 PM PDT 24
Peak memory 219992 kb
Host smart-edc25d63-9285-4b08-859c-a2a4faa64d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662349989 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.1662349989
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.2977247326
Short name T623
Test name
Test status
Simulation time 116357328 ps
CPU time 2.13 seconds
Started Jul 14 06:59:58 PM PDT 24
Finished Jul 14 07:00:07 PM PDT 24
Peak memory 220004 kb
Host smart-daa04ab7-2a42-4a5b-8c08-04d2f941eb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977247326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.2977247326
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.1802394582
Short name T258
Test name
Test status
Simulation time 93889535 ps
CPU time 1.28 seconds
Started Jul 14 06:59:38 PM PDT 24
Finished Jul 14 06:59:42 PM PDT 24
Peak memory 219536 kb
Host smart-09d0bf15-477a-4995-90f5-55b8fe8c7eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802394582 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.1802394582
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.699326743
Short name T578
Test name
Test status
Simulation time 39697562 ps
CPU time 1.43 seconds
Started Jul 14 06:59:24 PM PDT 24
Finished Jul 14 06:59:27 PM PDT 24
Peak memory 218660 kb
Host smart-b412de71-1063-4052-8995-396a30f92fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699326743 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.699326743
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.1416652112
Short name T613
Test name
Test status
Simulation time 77441803 ps
CPU time 1.18 seconds
Started Jul 14 06:59:12 PM PDT 24
Finished Jul 14 06:59:18 PM PDT 24
Peak memory 217592 kb
Host smart-86e0b145-b6f4-4cea-a537-d7a5d4a242b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416652112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.1416652112
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.3810946668
Short name T38
Test name
Test status
Simulation time 30438952 ps
CPU time 1.27 seconds
Started Jul 14 06:59:33 PM PDT 24
Finished Jul 14 06:59:37 PM PDT 24
Peak memory 221212 kb
Host smart-1bcea2b8-4f43-4382-83ea-b1962d669c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810946668 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.3810946668
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.1318951572
Short name T59
Test name
Test status
Simulation time 132320688 ps
CPU time 1.2 seconds
Started Jul 14 06:59:24 PM PDT 24
Finished Jul 14 06:59:27 PM PDT 24
Peak memory 220216 kb
Host smart-7c60cd88-f30f-4008-bd8a-1221dd2dca42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318951572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.1318951572
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.2228191262
Short name T728
Test name
Test status
Simulation time 86802519 ps
CPU time 1.19 seconds
Started Jul 14 06:59:36 PM PDT 24
Finished Jul 14 06:59:40 PM PDT 24
Peak memory 218772 kb
Host smart-616a5880-f962-4310-93d8-599c07663c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228191262 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.2228191262
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.3592909694
Short name T40
Test name
Test status
Simulation time 54600184 ps
CPU time 1.28 seconds
Started Jul 14 06:59:35 PM PDT 24
Finished Jul 14 06:59:39 PM PDT 24
Peak memory 219036 kb
Host smart-87ede901-d145-457b-9818-0b6f05a2e66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592909694 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.3592909694
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.3949549010
Short name T940
Test name
Test status
Simulation time 55316285 ps
CPU time 1.29 seconds
Started Jul 14 06:59:34 PM PDT 24
Finished Jul 14 06:59:38 PM PDT 24
Peak memory 218856 kb
Host smart-99829838-5082-4f4d-ac98-4b556b79e0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949549010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.3949549010
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.1683857407
Short name T254
Test name
Test status
Simulation time 137611856 ps
CPU time 1.22 seconds
Started Jul 14 06:58:05 PM PDT 24
Finished Jul 14 06:58:11 PM PDT 24
Peak memory 219820 kb
Host smart-a52cf3b9-761c-4bd7-afe7-d5635db441aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683857407 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.1683857407
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.3820664021
Short name T463
Test name
Test status
Simulation time 65468594 ps
CPU time 0.81 seconds
Started Jul 14 06:58:07 PM PDT 24
Finished Jul 14 06:58:13 PM PDT 24
Peak memory 206824 kb
Host smart-475d40a6-0060-4b98-b4df-1f9d8fee8053
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820664021 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3820664021
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.1896229181
Short name T567
Test name
Test status
Simulation time 12896242 ps
CPU time 1 seconds
Started Jul 14 06:58:02 PM PDT 24
Finished Jul 14 06:58:05 PM PDT 24
Peak memory 215900 kb
Host smart-b1023628-e038-4549-a1ac-573898455c7e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896229181 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1896229181
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.1322694333
Short name T153
Test name
Test status
Simulation time 36733375 ps
CPU time 1.02 seconds
Started Jul 14 06:58:31 PM PDT 24
Finished Jul 14 06:58:33 PM PDT 24
Peak memory 217032 kb
Host smart-772702b0-1b48-4e51-8dba-0415844871bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322694333 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.1322694333
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.2297018096
Short name T133
Test name
Test status
Simulation time 47250174 ps
CPU time 0.98 seconds
Started Jul 14 06:58:12 PM PDT 24
Finished Jul 14 06:58:20 PM PDT 24
Peak memory 219836 kb
Host smart-1593fbc4-05fa-4acd-b26a-ff7301aa2d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297018096 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2297018096
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.2578268719
Short name T769
Test name
Test status
Simulation time 48987085 ps
CPU time 1.26 seconds
Started Jul 14 06:58:21 PM PDT 24
Finished Jul 14 06:58:26 PM PDT 24
Peak memory 217788 kb
Host smart-9c0b0f29-efaf-44b9-b276-cb2c269bf8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578268719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2578268719
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.4001722012
Short name T616
Test name
Test status
Simulation time 33734880 ps
CPU time 0.98 seconds
Started Jul 14 06:58:18 PM PDT 24
Finished Jul 14 06:58:25 PM PDT 24
Peak memory 224180 kb
Host smart-41ea7147-6433-4c84-9305-955e27c94ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001722012 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.4001722012
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.2911677220
Short name T595
Test name
Test status
Simulation time 62197946 ps
CPU time 0.94 seconds
Started Jul 14 06:58:09 PM PDT 24
Finished Jul 14 06:58:16 PM PDT 24
Peak memory 215804 kb
Host smart-1f563901-1e21-4cc7-8f06-4b516d4fe915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911677220 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.2911677220
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.3890827269
Short name T376
Test name
Test status
Simulation time 402796962 ps
CPU time 2.77 seconds
Started Jul 14 06:58:11 PM PDT 24
Finished Jul 14 06:58:21 PM PDT 24
Peak memory 217452 kb
Host smart-2fcd8840-aec4-44a7-a155-7e2e3554ef5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890827269 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3890827269
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2792622818
Short name T34
Test name
Test status
Simulation time 35098158224 ps
CPU time 403.55 seconds
Started Jul 14 06:58:03 PM PDT 24
Finished Jul 14 07:04:50 PM PDT 24
Peak memory 222168 kb
Host smart-03fcecdc-064e-472a-8b95-c71ddcd7d1aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792622818 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.2792622818
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.2831594600
Short name T142
Test name
Test status
Simulation time 338947035 ps
CPU time 1.19 seconds
Started Jul 14 06:59:40 PM PDT 24
Finished Jul 14 06:59:44 PM PDT 24
Peak memory 219224 kb
Host smart-6722ccad-cb14-4101-bfcc-8af77cec9e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831594600 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.2831594600
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.2031533294
Short name T898
Test name
Test status
Simulation time 83741691 ps
CPU time 1.55 seconds
Started Jul 14 06:59:42 PM PDT 24
Finished Jul 14 06:59:46 PM PDT 24
Peak memory 218024 kb
Host smart-f89ba719-e466-4b34-83b5-7de187e34afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031533294 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2031533294
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.1842890331
Short name T302
Test name
Test status
Simulation time 243361800 ps
CPU time 1.17 seconds
Started Jul 14 06:59:13 PM PDT 24
Finished Jul 14 06:59:21 PM PDT 24
Peak memory 218752 kb
Host smart-29efdb83-8cc2-4738-8a87-e583823f6dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842890331 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.1842890331
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.3173506710
Short name T592
Test name
Test status
Simulation time 67205299 ps
CPU time 1.58 seconds
Started Jul 14 06:59:14 PM PDT 24
Finished Jul 14 06:59:20 PM PDT 24
Peak memory 218940 kb
Host smart-1e260fc6-60f5-48e5-8568-6124aad2e3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173506710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.3173506710
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.4123964756
Short name T252
Test name
Test status
Simulation time 50377103 ps
CPU time 1.23 seconds
Started Jul 14 06:59:34 PM PDT 24
Finished Jul 14 06:59:37 PM PDT 24
Peak memory 219024 kb
Host smart-6854d839-d8bd-4dfa-a022-ad06efcbb9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123964756 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.4123964756
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/133.edn_alert.2077631861
Short name T751
Test name
Test status
Simulation time 63215811 ps
CPU time 1.23 seconds
Started Jul 14 06:59:48 PM PDT 24
Finished Jul 14 06:59:51 PM PDT 24
Peak memory 219872 kb
Host smart-8fa6ef07-fd36-4856-9f8b-4243a2f95219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077631861 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.2077631861
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.1739150125
Short name T637
Test name
Test status
Simulation time 40803727 ps
CPU time 1.42 seconds
Started Jul 14 06:59:49 PM PDT 24
Finished Jul 14 06:59:52 PM PDT 24
Peak memory 219892 kb
Host smart-4827af03-6308-441b-ba6b-d36e549a0c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739150125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1739150125
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.4180035849
Short name T603
Test name
Test status
Simulation time 27162384 ps
CPU time 1.21 seconds
Started Jul 14 06:59:39 PM PDT 24
Finished Jul 14 06:59:44 PM PDT 24
Peak memory 219952 kb
Host smart-b36dc079-9cc8-4b25-a8c9-c1669d84dbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180035849 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.4180035849
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.909426419
Short name T712
Test name
Test status
Simulation time 94088901 ps
CPU time 1.15 seconds
Started Jul 14 07:00:00 PM PDT 24
Finished Jul 14 07:00:09 PM PDT 24
Peak memory 217680 kb
Host smart-96374438-9a44-4afb-8c64-d1f26f911295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909426419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.909426419
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.865656663
Short name T566
Test name
Test status
Simulation time 38337230 ps
CPU time 1.29 seconds
Started Jul 14 06:59:43 PM PDT 24
Finished Jul 14 06:59:47 PM PDT 24
Peak memory 219900 kb
Host smart-29d1cc90-7d94-4b9a-80f7-e36eb117c842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865656663 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.865656663
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.914931688
Short name T405
Test name
Test status
Simulation time 90602392 ps
CPU time 1.36 seconds
Started Jul 14 06:59:48 PM PDT 24
Finished Jul 14 06:59:50 PM PDT 24
Peak memory 218896 kb
Host smart-f1c2f689-cbd6-4309-95ea-c9161b3b2808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914931688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.914931688
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.3749019010
Short name T849
Test name
Test status
Simulation time 91927031 ps
CPU time 1.22 seconds
Started Jul 14 06:59:45 PM PDT 24
Finished Jul 14 06:59:48 PM PDT 24
Peak memory 220180 kb
Host smart-f0c82f4d-43f2-4828-bef1-979800ea53b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749019010 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.3749019010
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.597886142
Short name T910
Test name
Test status
Simulation time 97115456 ps
CPU time 1.28 seconds
Started Jul 14 06:59:35 PM PDT 24
Finished Jul 14 06:59:39 PM PDT 24
Peak memory 217744 kb
Host smart-441c68e1-2e47-4223-ac57-eda1a4439ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597886142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.597886142
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.3963512091
Short name T136
Test name
Test status
Simulation time 30353755 ps
CPU time 1.22 seconds
Started Jul 14 06:59:43 PM PDT 24
Finished Jul 14 06:59:47 PM PDT 24
Peak memory 220108 kb
Host smart-8ebc503f-fbb4-45a2-8853-5106a775e194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963512091 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.3963512091
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.500516156
Short name T775
Test name
Test status
Simulation time 155026478 ps
CPU time 2.5 seconds
Started Jul 14 06:59:39 PM PDT 24
Finished Jul 14 06:59:45 PM PDT 24
Peak memory 220500 kb
Host smart-f53ae1ba-eefc-4f78-8fbb-405d3cbfb25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500516156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.500516156
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.2160673422
Short name T907
Test name
Test status
Simulation time 26499019 ps
CPU time 1.19 seconds
Started Jul 14 06:59:23 PM PDT 24
Finished Jul 14 06:59:26 PM PDT 24
Peak memory 219908 kb
Host smart-df4400bd-8f2c-4bee-92fd-0ec3b57ec264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160673422 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.2160673422
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.1973703839
Short name T641
Test name
Test status
Simulation time 99546868 ps
CPU time 1.3 seconds
Started Jul 14 06:59:37 PM PDT 24
Finished Jul 14 06:59:42 PM PDT 24
Peak memory 217692 kb
Host smart-462d05c6-1138-4f95-adb8-a92558c50472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973703839 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1973703839
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.2120322017
Short name T841
Test name
Test status
Simulation time 89769492 ps
CPU time 1.23 seconds
Started Jul 14 06:59:40 PM PDT 24
Finished Jul 14 06:59:45 PM PDT 24
Peak memory 221180 kb
Host smart-ed6b0d02-ce7c-4634-b2ba-f59d66666bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120322017 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.2120322017
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.3331135119
Short name T355
Test name
Test status
Simulation time 33094939 ps
CPU time 1.26 seconds
Started Jul 14 06:59:25 PM PDT 24
Finished Jul 14 06:59:29 PM PDT 24
Peak memory 220160 kb
Host smart-064a3fd2-3df0-4279-99f6-a70ca8dc29fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331135119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3331135119
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert_test.3776306511
Short name T925
Test name
Test status
Simulation time 114097945 ps
CPU time 0.78 seconds
Started Jul 14 06:58:32 PM PDT 24
Finished Jul 14 06:58:35 PM PDT 24
Peak memory 206636 kb
Host smart-baf1b7c3-613c-439c-b037-ab0486bd387a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776306511 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3776306511
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.455746892
Short name T962
Test name
Test status
Simulation time 49452998 ps
CPU time 0.86 seconds
Started Jul 14 06:58:31 PM PDT 24
Finished Jul 14 06:58:33 PM PDT 24
Peak memory 216252 kb
Host smart-88b39d0b-23fa-4d03-b4df-242df5a1b279
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455746892 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.455746892
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.2096336754
Short name T91
Test name
Test status
Simulation time 58962330 ps
CPU time 1.23 seconds
Started Jul 14 06:58:16 PM PDT 24
Finished Jul 14 06:58:24 PM PDT 24
Peak memory 217448 kb
Host smart-bb8643ed-6de6-4043-a8e8-e0ea46efe94c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096336754 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.2096336754
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_genbits.607411282
Short name T346
Test name
Test status
Simulation time 37508816 ps
CPU time 1.12 seconds
Started Jul 14 06:58:10 PM PDT 24
Finished Jul 14 06:58:18 PM PDT 24
Peak memory 220036 kb
Host smart-00dbada3-8a00-4d1b-a3ca-ffd19d63c144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607411282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.607411282
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.3217313480
Short name T584
Test name
Test status
Simulation time 41025371 ps
CPU time 1.02 seconds
Started Jul 14 06:58:09 PM PDT 24
Finished Jul 14 06:58:16 PM PDT 24
Peak memory 224516 kb
Host smart-d9de4ced-d038-4c5b-bb3e-d5478f239336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217313480 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3217313480
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.2949065967
Short name T414
Test name
Test status
Simulation time 80109026 ps
CPU time 0.94 seconds
Started Jul 14 06:58:07 PM PDT 24
Finished Jul 14 06:58:13 PM PDT 24
Peak memory 215560 kb
Host smart-00ef4d88-eaab-4dbd-935d-95a3063ac8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949065967 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2949065967
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.1640863767
Short name T387
Test name
Test status
Simulation time 221382241 ps
CPU time 2.9 seconds
Started Jul 14 06:58:05 PM PDT 24
Finished Jul 14 06:58:11 PM PDT 24
Peak memory 217352 kb
Host smart-6f60685a-78bb-44c7-9f85-094321ad718a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640863767 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1640863767
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.4099265618
Short name T224
Test name
Test status
Simulation time 211229293649 ps
CPU time 2643.64 seconds
Started Jul 14 06:58:06 PM PDT 24
Finished Jul 14 07:42:14 PM PDT 24
Peak memory 233992 kb
Host smart-3ca6f371-e918-4dd3-9fa1-d5ae6f891927
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099265618 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.4099265618
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.3823263479
Short name T600
Test name
Test status
Simulation time 44877421 ps
CPU time 1.16 seconds
Started Jul 14 06:59:34 PM PDT 24
Finished Jul 14 06:59:38 PM PDT 24
Peak memory 215932 kb
Host smart-1d895dbc-94b6-42be-9f07-c1aba23f8819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823263479 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.3823263479
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.174247828
Short name T840
Test name
Test status
Simulation time 53121551 ps
CPU time 2.11 seconds
Started Jul 14 06:59:40 PM PDT 24
Finished Jul 14 06:59:45 PM PDT 24
Peak memory 217872 kb
Host smart-2c0134aa-0219-475c-9329-b7d841e14513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174247828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.174247828
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.4140855318
Short name T256
Test name
Test status
Simulation time 26381261 ps
CPU time 1.15 seconds
Started Jul 14 06:59:36 PM PDT 24
Finished Jul 14 06:59:40 PM PDT 24
Peak memory 221032 kb
Host smart-9ad2efbc-c360-49bf-beb9-327ce5d02dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140855318 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.4140855318
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.3292309744
Short name T410
Test name
Test status
Simulation time 82332874 ps
CPU time 1.09 seconds
Started Jul 14 06:59:37 PM PDT 24
Finished Jul 14 06:59:41 PM PDT 24
Peak memory 217520 kb
Host smart-d80ca206-d30a-4407-937b-7764c1f34707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292309744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3292309744
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.1864988103
Short name T385
Test name
Test status
Simulation time 72972245 ps
CPU time 1.04 seconds
Started Jul 14 06:59:52 PM PDT 24
Finished Jul 14 06:59:57 PM PDT 24
Peak memory 217504 kb
Host smart-bfe99c4e-c91b-4a75-8fef-50daa7f88560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864988103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.1864988103
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.1050382274
Short name T752
Test name
Test status
Simulation time 83074889 ps
CPU time 1.39 seconds
Started Jul 14 06:59:35 PM PDT 24
Finished Jul 14 06:59:39 PM PDT 24
Peak memory 218904 kb
Host smart-5a45b2bd-5d1c-4d31-858a-54c0561a6743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050382274 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.1050382274
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.3568479321
Short name T802
Test name
Test status
Simulation time 60503335 ps
CPU time 1.29 seconds
Started Jul 14 06:59:33 PM PDT 24
Finished Jul 14 06:59:37 PM PDT 24
Peak memory 219748 kb
Host smart-1fdda0fc-c213-4d20-a050-a3a93a73ccc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568479321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.3568479321
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.1899246248
Short name T960
Test name
Test status
Simulation time 85764556 ps
CPU time 1.23 seconds
Started Jul 14 06:59:48 PM PDT 24
Finished Jul 14 06:59:51 PM PDT 24
Peak memory 219040 kb
Host smart-9a3d57ca-4169-4933-9e66-b62d1c444121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899246248 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.1899246248
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.4129540452
Short name T604
Test name
Test status
Simulation time 55699619 ps
CPU time 1.54 seconds
Started Jul 14 06:59:40 PM PDT 24
Finished Jul 14 06:59:45 PM PDT 24
Peak memory 219324 kb
Host smart-8ab6c6d8-154b-47ea-9729-9d7eb9884f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129540452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.4129540452
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.765224134
Short name T444
Test name
Test status
Simulation time 171972964 ps
CPU time 1.16 seconds
Started Jul 14 06:59:35 PM PDT 24
Finished Jul 14 06:59:39 PM PDT 24
Peak memory 220980 kb
Host smart-820581ac-abb9-4b15-8829-352c3ac8a697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765224134 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.765224134
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.4293927309
Short name T338
Test name
Test status
Simulation time 71417163 ps
CPU time 1.26 seconds
Started Jul 14 06:59:34 PM PDT 24
Finished Jul 14 06:59:37 PM PDT 24
Peak memory 219012 kb
Host smart-67dd1de8-fbc2-46fe-ab56-b8c195ac882c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293927309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.4293927309
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.1442652153
Short name T763
Test name
Test status
Simulation time 28639866 ps
CPU time 1.17 seconds
Started Jul 14 06:59:54 PM PDT 24
Finished Jul 14 07:00:02 PM PDT 24
Peak memory 218864 kb
Host smart-5699ce69-1531-4470-a338-17aef29ee07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442652153 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.1442652153
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.2575428412
Short name T328
Test name
Test status
Simulation time 258765768 ps
CPU time 1.1 seconds
Started Jul 14 06:59:42 PM PDT 24
Finished Jul 14 06:59:46 PM PDT 24
Peak memory 217628 kb
Host smart-7a68bc80-6d8e-480e-8879-b3da114c745f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575428412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2575428412
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.315544529
Short name T383
Test name
Test status
Simulation time 28872185 ps
CPU time 1.32 seconds
Started Jul 14 06:59:38 PM PDT 24
Finished Jul 14 06:59:43 PM PDT 24
Peak memory 218912 kb
Host smart-5db306e3-bc0d-44da-816e-59dc536d4121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315544529 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.315544529
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.3436300529
Short name T736
Test name
Test status
Simulation time 234230658 ps
CPU time 1.2 seconds
Started Jul 14 06:59:36 PM PDT 24
Finished Jul 14 06:59:40 PM PDT 24
Peak memory 218068 kb
Host smart-fb33bda2-c555-4769-921c-c27e663853db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436300529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3436300529
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.2241195812
Short name T927
Test name
Test status
Simulation time 29837838 ps
CPU time 1.22 seconds
Started Jul 14 06:59:35 PM PDT 24
Finished Jul 14 06:59:39 PM PDT 24
Peak memory 219824 kb
Host smart-09ec330b-3731-49a1-bdb3-45598f91d4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241195812 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.2241195812
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/149.edn_alert.1860550649
Short name T991
Test name
Test status
Simulation time 22384629 ps
CPU time 1.36 seconds
Started Jul 14 06:59:52 PM PDT 24
Finished Jul 14 06:59:56 PM PDT 24
Peak memory 218920 kb
Host smart-851a2dc3-9409-44ae-adfa-7534b6cb6072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860550649 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.1860550649
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert.1700733133
Short name T257
Test name
Test status
Simulation time 98630515 ps
CPU time 1.19 seconds
Started Jul 14 06:58:03 PM PDT 24
Finished Jul 14 06:58:07 PM PDT 24
Peak memory 220928 kb
Host smart-9ad2317d-d256-4248-b381-7640ccf254c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700733133 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.1700733133
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_disable.3374217340
Short name T2
Test name
Test status
Simulation time 14146711 ps
CPU time 0.92 seconds
Started Jul 14 06:58:28 PM PDT 24
Finished Jul 14 06:58:30 PM PDT 24
Peak memory 216696 kb
Host smart-ed843ac5-7e15-431a-8f84-2fcfec54c341
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374217340 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3374217340
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.600637697
Short name T456
Test name
Test status
Simulation time 45503791 ps
CPU time 0.96 seconds
Started Jul 14 06:58:05 PM PDT 24
Finished Jul 14 06:58:11 PM PDT 24
Peak memory 217156 kb
Host smart-19b5d9f1-775b-470e-af3a-d097f2d43bd1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600637697 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_di
sable_auto_req_mode.600637697
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.1901988283
Short name T924
Test name
Test status
Simulation time 30054815 ps
CPU time 0.84 seconds
Started Jul 14 06:58:28 PM PDT 24
Finished Jul 14 06:58:29 PM PDT 24
Peak memory 219524 kb
Host smart-52fbbcad-e035-4cb6-9ef5-707f1758e780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901988283 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.1901988283
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.430846333
Short name T10
Test name
Test status
Simulation time 63070884 ps
CPU time 2.37 seconds
Started Jul 14 06:58:19 PM PDT 24
Finished Jul 14 06:58:27 PM PDT 24
Peak memory 218840 kb
Host smart-9549afcf-d9f8-4c92-84b9-86e593a8877b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430846333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.430846333
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.1309353195
Short name T116
Test name
Test status
Simulation time 34819725 ps
CPU time 0.85 seconds
Started Jul 14 06:58:07 PM PDT 24
Finished Jul 14 06:58:13 PM PDT 24
Peak memory 215844 kb
Host smart-742f6ee9-b53b-4a61-a9a9-7be1b9e23b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309353195 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.1309353195
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.1887289373
Short name T492
Test name
Test status
Simulation time 18833490 ps
CPU time 0.99 seconds
Started Jul 14 06:58:28 PM PDT 24
Finished Jul 14 06:58:30 PM PDT 24
Peak memory 215596 kb
Host smart-2a839d16-a686-42cb-8373-f6c3fcb15b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887289373 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.1887289373
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.944234647
Short name T784
Test name
Test status
Simulation time 218151485 ps
CPU time 4.34 seconds
Started Jul 14 06:58:02 PM PDT 24
Finished Jul 14 06:58:08 PM PDT 24
Peak memory 217360 kb
Host smart-49933688-5ee4-4140-ba14-fb098d4d358c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944234647 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.944234647
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2284334539
Short name T944
Test name
Test status
Simulation time 27124476043 ps
CPU time 652.39 seconds
Started Jul 14 06:58:04 PM PDT 24
Finished Jul 14 07:09:00 PM PDT 24
Peak memory 217944 kb
Host smart-d1ac84ce-dc20-408d-844a-97e9c2a7c7f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284334539 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.2284334539
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.2741003570
Short name T760
Test name
Test status
Simulation time 44510001 ps
CPU time 1.13 seconds
Started Jul 14 06:59:44 PM PDT 24
Finished Jul 14 06:59:47 PM PDT 24
Peak memory 218784 kb
Host smart-68789e62-c6e2-4ee5-afae-46772ea01f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741003570 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.2741003570
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.3368544676
Short name T813
Test name
Test status
Simulation time 251083439 ps
CPU time 1.23 seconds
Started Jul 14 06:59:37 PM PDT 24
Finished Jul 14 06:59:41 PM PDT 24
Peak memory 217600 kb
Host smart-40e6bac0-8201-4a1d-8db0-5f385abcd765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368544676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3368544676
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.3044310308
Short name T141
Test name
Test status
Simulation time 64559126 ps
CPU time 1.09 seconds
Started Jul 14 06:59:53 PM PDT 24
Finished Jul 14 06:59:59 PM PDT 24
Peak memory 218928 kb
Host smart-30661158-b0fd-44ae-9c24-217290a5cb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044310308 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.3044310308
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.60383716
Short name T457
Test name
Test status
Simulation time 47685035 ps
CPU time 1.23 seconds
Started Jul 14 06:59:38 PM PDT 24
Finished Jul 14 06:59:42 PM PDT 24
Peak memory 217536 kb
Host smart-15b0fb88-beed-403d-bb72-af144be7120d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60383716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.60383716
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.1053869322
Short name T900
Test name
Test status
Simulation time 81071620 ps
CPU time 1.16 seconds
Started Jul 14 06:59:40 PM PDT 24
Finished Jul 14 06:59:45 PM PDT 24
Peak memory 218824 kb
Host smart-f5a98fe0-8b64-427c-a665-4e1578bc8a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053869322 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.1053869322
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.1169599488
Short name T877
Test name
Test status
Simulation time 66769793 ps
CPU time 1.1 seconds
Started Jul 14 06:59:38 PM PDT 24
Finished Jul 14 06:59:42 PM PDT 24
Peak memory 217744 kb
Host smart-00351211-8517-4a02-9db9-49a17285fe0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169599488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.1169599488
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.4254968770
Short name T792
Test name
Test status
Simulation time 29240335 ps
CPU time 1.29 seconds
Started Jul 14 06:59:45 PM PDT 24
Finished Jul 14 06:59:48 PM PDT 24
Peak memory 219764 kb
Host smart-bcb2fcca-20b9-46fe-aa09-ff5d0a7f5909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254968770 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.4254968770
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.298281197
Short name T84
Test name
Test status
Simulation time 53592341 ps
CPU time 1.37 seconds
Started Jul 14 06:59:41 PM PDT 24
Finished Jul 14 06:59:46 PM PDT 24
Peak memory 219024 kb
Host smart-6dba8477-4a75-437f-9a9a-c9dd84e4b8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298281197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.298281197
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.1973567605
Short name T631
Test name
Test status
Simulation time 29700091 ps
CPU time 1.3 seconds
Started Jul 14 06:59:42 PM PDT 24
Finished Jul 14 06:59:47 PM PDT 24
Peak memory 220932 kb
Host smart-89f4535e-fa0b-4808-9bef-ce9a8f82dac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973567605 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.1973567605
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.4153991868
Short name T451
Test name
Test status
Simulation time 32801471 ps
CPU time 1.22 seconds
Started Jul 14 07:00:06 PM PDT 24
Finished Jul 14 07:00:14 PM PDT 24
Peak memory 218892 kb
Host smart-f3cf73b9-ea65-48b1-876e-61b56b321a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153991868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.4153991868
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.2904070052
Short name T467
Test name
Test status
Simulation time 125190247 ps
CPU time 1.24 seconds
Started Jul 14 06:59:39 PM PDT 24
Finished Jul 14 06:59:44 PM PDT 24
Peak memory 220800 kb
Host smart-7eae28a6-568d-4ca4-a5c3-608fdcf77ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904070052 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.2904070052
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.1734712819
Short name T743
Test name
Test status
Simulation time 51100287 ps
CPU time 1.66 seconds
Started Jul 14 06:59:39 PM PDT 24
Finished Jul 14 06:59:44 PM PDT 24
Peak memory 218788 kb
Host smart-f0fefd25-0b74-4722-94d8-9720d4a55945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734712819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1734712819
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.1812741308
Short name T220
Test name
Test status
Simulation time 68495693 ps
CPU time 1.14 seconds
Started Jul 14 06:59:49 PM PDT 24
Finished Jul 14 06:59:51 PM PDT 24
Peak memory 219600 kb
Host smart-4f04e178-5eb0-4a6e-ae84-f14e76c639e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812741308 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.1812741308
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/157.edn_alert.540187469
Short name T130
Test name
Test status
Simulation time 24005137 ps
CPU time 1.17 seconds
Started Jul 14 06:59:31 PM PDT 24
Finished Jul 14 06:59:36 PM PDT 24
Peak memory 220612 kb
Host smart-e5eead2e-08ed-40d8-8120-b44d4ff15a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540187469 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.540187469
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.1761510845
Short name T761
Test name
Test status
Simulation time 53991247 ps
CPU time 1.4 seconds
Started Jul 14 06:59:49 PM PDT 24
Finished Jul 14 06:59:52 PM PDT 24
Peak memory 217744 kb
Host smart-2c62313a-c3aa-4268-9866-d5c40eb023f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761510845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.1761510845
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.4187210401
Short name T280
Test name
Test status
Simulation time 45528435 ps
CPU time 1.14 seconds
Started Jul 14 06:59:58 PM PDT 24
Finished Jul 14 07:00:07 PM PDT 24
Peak memory 218824 kb
Host smart-3dea03d8-6059-4936-8f22-b624814fe270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187210401 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.4187210401
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/159.edn_alert.2036067365
Short name T710
Test name
Test status
Simulation time 56646470 ps
CPU time 1.17 seconds
Started Jul 14 06:59:53 PM PDT 24
Finished Jul 14 06:59:59 PM PDT 24
Peak memory 220156 kb
Host smart-3ef3d72f-3cdd-46ee-934d-053ae586045b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036067365 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.2036067365
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.3832932505
Short name T934
Test name
Test status
Simulation time 53865228 ps
CPU time 1.36 seconds
Started Jul 14 06:59:40 PM PDT 24
Finished Jul 14 06:59:45 PM PDT 24
Peak memory 217460 kb
Host smart-75726dbf-34f1-452f-9d1b-53c74a5973af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832932505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.3832932505
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.3681072726
Short name T929
Test name
Test status
Simulation time 53668530 ps
CPU time 1.26 seconds
Started Jul 14 06:58:13 PM PDT 24
Finished Jul 14 06:58:21 PM PDT 24
Peak memory 220036 kb
Host smart-5cf13dd0-f840-4d52-9cea-18aaa3151afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681072726 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3681072726
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.2754542355
Short name T705
Test name
Test status
Simulation time 54865411 ps
CPU time 0.84 seconds
Started Jul 14 06:58:08 PM PDT 24
Finished Jul 14 06:58:15 PM PDT 24
Peak memory 214984 kb
Host smart-9840f487-c6b6-4ce0-a1ad-3005453e2135
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754542355 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.2754542355
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.2845115488
Short name T402
Test name
Test status
Simulation time 51951761 ps
CPU time 0.82 seconds
Started Jul 14 06:58:10 PM PDT 24
Finished Jul 14 06:58:18 PM PDT 24
Peak memory 216304 kb
Host smart-e8e5417d-9460-4a52-acf0-9a33282da677
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845115488 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2845115488
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_genbits.2152438162
Short name T540
Test name
Test status
Simulation time 32548948 ps
CPU time 1.26 seconds
Started Jul 14 06:58:14 PM PDT 24
Finished Jul 14 06:58:22 PM PDT 24
Peak memory 218752 kb
Host smart-b7df2fa5-db9c-4c82-865c-96a561f32e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152438162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2152438162
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.2773169635
Short name T961
Test name
Test status
Simulation time 28523949 ps
CPU time 1.04 seconds
Started Jul 14 06:58:14 PM PDT 24
Finished Jul 14 06:58:22 PM PDT 24
Peak memory 224336 kb
Host smart-9785f0bb-b8cd-458a-8583-a611e6af96f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773169635 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.2773169635
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.616863158
Short name T554
Test name
Test status
Simulation time 16394705 ps
CPU time 0.98 seconds
Started Jul 14 06:58:29 PM PDT 24
Finished Jul 14 06:58:31 PM PDT 24
Peak memory 215612 kb
Host smart-c710e5a9-d5c2-46fb-a9c5-1e14e47da4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616863158 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.616863158
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.4262270640
Short name T844
Test name
Test status
Simulation time 899459003 ps
CPU time 5.17 seconds
Started Jul 14 06:58:12 PM PDT 24
Finished Jul 14 06:58:24 PM PDT 24
Peak memory 215524 kb
Host smart-bdc4add8-0af6-46d5-9c95-032aa3b1dd02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262270640 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.4262270640
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2494076918
Short name T538
Test name
Test status
Simulation time 92195892203 ps
CPU time 1226.81 seconds
Started Jul 14 06:58:03 PM PDT 24
Finished Jul 14 07:18:33 PM PDT 24
Peak memory 225136 kb
Host smart-bf477fba-44fe-437c-a385-122cc98ba735
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494076918 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2494076918
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.3298744031
Short name T834
Test name
Test status
Simulation time 27444326 ps
CPU time 1.22 seconds
Started Jul 14 06:59:43 PM PDT 24
Finished Jul 14 06:59:47 PM PDT 24
Peak memory 220936 kb
Host smart-498a2af3-52ce-4487-b474-739cd4466564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298744031 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.3298744031
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.1820043784
Short name T347
Test name
Test status
Simulation time 100300199 ps
CPU time 1.49 seconds
Started Jul 14 06:59:42 PM PDT 24
Finished Jul 14 06:59:46 PM PDT 24
Peak memory 220520 kb
Host smart-16a03c92-fbed-4e07-8f67-eb9d09c81707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820043784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1820043784
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.4026902473
Short name T103
Test name
Test status
Simulation time 98598007 ps
CPU time 1.23 seconds
Started Jul 14 06:59:52 PM PDT 24
Finished Jul 14 06:59:57 PM PDT 24
Peak memory 219892 kb
Host smart-9b290e19-4270-4c40-9de4-717eeb42aa11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026902473 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.4026902473
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.92889918
Short name T342
Test name
Test status
Simulation time 127112534 ps
CPU time 2.92 seconds
Started Jul 14 06:59:49 PM PDT 24
Finished Jul 14 06:59:53 PM PDT 24
Peak memory 217844 kb
Host smart-37048f4f-9639-4efb-8541-cee74816cc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92889918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.92889918
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.1067063819
Short name T245
Test name
Test status
Simulation time 48827255 ps
CPU time 1.19 seconds
Started Jul 14 06:59:59 PM PDT 24
Finished Jul 14 07:00:09 PM PDT 24
Peak memory 221124 kb
Host smart-a3afe4bf-f434-4c9b-80bb-295f6fde4978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067063819 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.1067063819
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.2892565076
Short name T512
Test name
Test status
Simulation time 98797138 ps
CPU time 1.48 seconds
Started Jul 14 07:00:03 PM PDT 24
Finished Jul 14 07:00:12 PM PDT 24
Peak memory 219192 kb
Host smart-c3289c4c-e8f0-4047-94d2-f6c4c1245229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892565076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.2892565076
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.323657756
Short name T148
Test name
Test status
Simulation time 29857228 ps
CPU time 1.27 seconds
Started Jul 14 07:00:09 PM PDT 24
Finished Jul 14 07:00:17 PM PDT 24
Peak memory 219860 kb
Host smart-1ad918d5-0954-4468-982a-d98532052776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323657756 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.323657756
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.1586569470
Short name T289
Test name
Test status
Simulation time 87308392 ps
CPU time 1.37 seconds
Started Jul 14 06:59:54 PM PDT 24
Finished Jul 14 07:00:01 PM PDT 24
Peak memory 218920 kb
Host smart-ad19e168-6ab7-46f2-aa19-0aca96dc4562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586569470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.1586569470
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.2727999069
Short name T780
Test name
Test status
Simulation time 45462715 ps
CPU time 1.2 seconds
Started Jul 14 06:59:48 PM PDT 24
Finished Jul 14 06:59:50 PM PDT 24
Peak memory 219564 kb
Host smart-4528f3e2-c04d-4257-a39a-e7e03b03fc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727999069 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.2727999069
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.4104725385
Short name T945
Test name
Test status
Simulation time 41915634 ps
CPU time 1.61 seconds
Started Jul 14 06:59:42 PM PDT 24
Finished Jul 14 06:59:46 PM PDT 24
Peak memory 218764 kb
Host smart-806545a1-d19d-4913-8f53-fb51226601d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104725385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.4104725385
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.92104720
Short name T15
Test name
Test status
Simulation time 91268731 ps
CPU time 1.18 seconds
Started Jul 14 06:59:53 PM PDT 24
Finished Jul 14 06:59:57 PM PDT 24
Peak memory 216008 kb
Host smart-fe554591-3964-417b-9c05-5a1007b3ca99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92104720 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.92104720
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.985363033
Short name T970
Test name
Test status
Simulation time 138998649 ps
CPU time 1.62 seconds
Started Jul 14 06:59:37 PM PDT 24
Finished Jul 14 06:59:42 PM PDT 24
Peak memory 219124 kb
Host smart-272d2bac-1d37-4c89-88f8-ef0ca4a942dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985363033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.985363033
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.3747738574
Short name T455
Test name
Test status
Simulation time 41850539 ps
CPU time 1.54 seconds
Started Jul 14 06:59:36 PM PDT 24
Finished Jul 14 06:59:41 PM PDT 24
Peak memory 217784 kb
Host smart-bc245a9b-2678-4006-bf08-fbc24502ec88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747738574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.3747738574
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.823566223
Short name T729
Test name
Test status
Simulation time 88336537 ps
CPU time 1.15 seconds
Started Jul 14 06:59:55 PM PDT 24
Finished Jul 14 07:00:04 PM PDT 24
Peak memory 221212 kb
Host smart-12d33742-666a-446e-b960-5723bf0b58a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823566223 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.823566223
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.1502572205
Short name T811
Test name
Test status
Simulation time 95706732 ps
CPU time 1.75 seconds
Started Jul 14 06:59:40 PM PDT 24
Finished Jul 14 06:59:45 PM PDT 24
Peak memory 219332 kb
Host smart-8bf4a163-80de-4f90-b990-c594923b0ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502572205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1502572205
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.3419374915
Short name T628
Test name
Test status
Simulation time 72144004 ps
CPU time 1.09 seconds
Started Jul 14 06:59:39 PM PDT 24
Finished Jul 14 06:59:43 PM PDT 24
Peak memory 219004 kb
Host smart-67608bd5-5c24-412c-bcf7-e9c2d05d244e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419374915 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.3419374915
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.2283830626
Short name T318
Test name
Test status
Simulation time 35271301 ps
CPU time 1.58 seconds
Started Jul 14 06:59:39 PM PDT 24
Finished Jul 14 06:59:44 PM PDT 24
Peak memory 218808 kb
Host smart-02f30e3d-8253-4374-9040-63ee0f267c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283830626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.2283830626
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.2012788259
Short name T819
Test name
Test status
Simulation time 38163747 ps
CPU time 1.3 seconds
Started Jul 14 06:58:23 PM PDT 24
Finished Jul 14 06:58:27 PM PDT 24
Peak memory 215988 kb
Host smart-f5c651cf-89f6-46d7-ac98-98c2b2a99cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012788259 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.2012788259
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.2964153742
Short name T846
Test name
Test status
Simulation time 15472200 ps
CPU time 0.9 seconds
Started Jul 14 06:58:10 PM PDT 24
Finished Jul 14 06:58:18 PM PDT 24
Peak memory 207032 kb
Host smart-e8a16464-4d2f-4024-afd8-60dcb10479fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964153742 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2964153742
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.3907845012
Short name T189
Test name
Test status
Simulation time 28586653 ps
CPU time 0.86 seconds
Started Jul 14 06:58:18 PM PDT 24
Finished Jul 14 06:58:25 PM PDT 24
Peak memory 216640 kb
Host smart-68488cff-04e5-4877-a9fc-9475c280b114
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907845012 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3907845012
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_err.502509395
Short name T881
Test name
Test status
Simulation time 48698094 ps
CPU time 0.87 seconds
Started Jul 14 06:58:20 PM PDT 24
Finished Jul 14 06:58:26 PM PDT 24
Peak memory 218264 kb
Host smart-7e2da3d5-26c2-47e8-8378-119d6a0a4ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502509395 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.502509395
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.1477821763
Short name T323
Test name
Test status
Simulation time 245559094 ps
CPU time 1.66 seconds
Started Jul 14 06:58:07 PM PDT 24
Finished Jul 14 06:58:14 PM PDT 24
Peak memory 219488 kb
Host smart-8e61e7d7-21cb-4d20-861b-421559242cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477821763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1477821763
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.4020642134
Short name T66
Test name
Test status
Simulation time 23164442 ps
CPU time 1.15 seconds
Started Jul 14 06:58:13 PM PDT 24
Finished Jul 14 06:58:21 PM PDT 24
Peak memory 215712 kb
Host smart-d8418014-3cf0-4cce-bba5-a0cd3a686e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020642134 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.4020642134
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.3109698463
Short name T808
Test name
Test status
Simulation time 16944160 ps
CPU time 1.01 seconds
Started Jul 14 06:58:31 PM PDT 24
Finished Jul 14 06:58:34 PM PDT 24
Peak memory 215672 kb
Host smart-2160d642-9352-4765-8a10-e4cfc96985d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109698463 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.3109698463
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.2796857434
Short name T495
Test name
Test status
Simulation time 628032867 ps
CPU time 4.28 seconds
Started Jul 14 06:58:19 PM PDT 24
Finished Jul 14 06:58:29 PM PDT 24
Peak memory 215552 kb
Host smart-d5e50615-0e85-4fb6-9fc0-0a2b453e158e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796857434 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.2796857434
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.588973308
Short name T767
Test name
Test status
Simulation time 105541398408 ps
CPU time 2435.87 seconds
Started Jul 14 06:58:32 PM PDT 24
Finished Jul 14 07:39:11 PM PDT 24
Peak memory 229516 kb
Host smart-12444d22-6f97-4d6b-b242-f02de63ffe31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588973308 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.588973308
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.2923235051
Short name T748
Test name
Test status
Simulation time 39391233 ps
CPU time 1.08 seconds
Started Jul 14 06:59:41 PM PDT 24
Finished Jul 14 06:59:45 PM PDT 24
Peak memory 219016 kb
Host smart-a469557e-16ff-4a6b-a4c7-c93c030f77dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923235051 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.2923235051
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.1442514166
Short name T880
Test name
Test status
Simulation time 104066881 ps
CPU time 1.14 seconds
Started Jul 14 06:59:48 PM PDT 24
Finished Jul 14 06:59:50 PM PDT 24
Peak memory 217848 kb
Host smart-adf8616b-5fba-415c-ba08-b5e9ad712035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442514166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1442514166
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.1686004211
Short name T306
Test name
Test status
Simulation time 154922621 ps
CPU time 1.21 seconds
Started Jul 14 06:59:51 PM PDT 24
Finished Jul 14 06:59:55 PM PDT 24
Peak memory 218788 kb
Host smart-41a460b7-6395-47aa-b9bb-6336dfc40e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686004211 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.1686004211
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.246937885
Short name T663
Test name
Test status
Simulation time 465387763 ps
CPU time 2.36 seconds
Started Jul 14 06:59:59 PM PDT 24
Finished Jul 14 07:00:10 PM PDT 24
Peak memory 219380 kb
Host smart-df8103ef-02a8-408e-8e20-64d46d7365b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246937885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.246937885
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.2452016342
Short name T108
Test name
Test status
Simulation time 45902546 ps
CPU time 1.22 seconds
Started Jul 14 06:59:54 PM PDT 24
Finished Jul 14 07:00:00 PM PDT 24
Peak memory 218760 kb
Host smart-78f63ce4-9df5-4d56-9cc2-f700b468c665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452016342 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.2452016342
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.448004688
Short name T893
Test name
Test status
Simulation time 176742496 ps
CPU time 1.31 seconds
Started Jul 14 07:00:03 PM PDT 24
Finished Jul 14 07:00:13 PM PDT 24
Peak memory 218964 kb
Host smart-7a60e265-c843-425b-ab39-f51431838081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448004688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.448004688
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.3597210739
Short name T546
Test name
Test status
Simulation time 28564639 ps
CPU time 1.24 seconds
Started Jul 14 06:59:56 PM PDT 24
Finished Jul 14 07:00:04 PM PDT 24
Peak memory 215932 kb
Host smart-db72024f-1ace-4a96-aebb-e0de8d2e1003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597210739 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.3597210739
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.3422720732
Short name T982
Test name
Test status
Simulation time 24119722 ps
CPU time 1.13 seconds
Started Jul 14 06:59:56 PM PDT 24
Finished Jul 14 07:00:03 PM PDT 24
Peak memory 217496 kb
Host smart-492ce8b8-59db-40ab-87cf-75925bd20944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422720732 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.3422720732
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.3989822022
Short name T620
Test name
Test status
Simulation time 49885362 ps
CPU time 1.22 seconds
Started Jul 14 07:00:03 PM PDT 24
Finished Jul 14 07:00:12 PM PDT 24
Peak memory 218824 kb
Host smart-6efa3e6c-c62c-47d7-82c4-e74ee39f4c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989822022 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.3989822022
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.2515520290
Short name T946
Test name
Test status
Simulation time 81095409 ps
CPU time 1.54 seconds
Started Jul 14 07:00:01 PM PDT 24
Finished Jul 14 07:00:10 PM PDT 24
Peak memory 219128 kb
Host smart-a04d5bc4-382c-4d7c-a950-f8e70e402055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515520290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.2515520290
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.1044913492
Short name T659
Test name
Test status
Simulation time 326391057 ps
CPU time 1.39 seconds
Started Jul 14 06:59:56 PM PDT 24
Finished Jul 14 07:00:04 PM PDT 24
Peak memory 219980 kb
Host smart-ba327a60-1ddf-41ae-8c2d-3869c0b7fd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044913492 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.1044913492
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.2197772782
Short name T549
Test name
Test status
Simulation time 112058021 ps
CPU time 1.71 seconds
Started Jul 14 06:59:48 PM PDT 24
Finished Jul 14 06:59:51 PM PDT 24
Peak memory 219216 kb
Host smart-e8bd6aa0-52ea-4e06-b271-91c4df7613b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197772782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.2197772782
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.37022464
Short name T462
Test name
Test status
Simulation time 22028451 ps
CPU time 1.1 seconds
Started Jul 14 06:59:55 PM PDT 24
Finished Jul 14 07:00:02 PM PDT 24
Peak memory 219948 kb
Host smart-6fce1468-9a13-473f-a7ae-05a3b62d7b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37022464 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.37022464
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.3554702822
Short name T461
Test name
Test status
Simulation time 29729575 ps
CPU time 1.26 seconds
Started Jul 14 06:59:57 PM PDT 24
Finished Jul 14 07:00:05 PM PDT 24
Peak memory 220148 kb
Host smart-0cbd6f0b-0b89-4a5d-8d09-ed2f238af399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554702822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.3554702822
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.2031492424
Short name T690
Test name
Test status
Simulation time 29539272 ps
CPU time 1.25 seconds
Started Jul 14 06:59:55 PM PDT 24
Finished Jul 14 07:00:02 PM PDT 24
Peak memory 218956 kb
Host smart-4ff7c673-fef0-4976-9906-0e8fb9f848ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031492424 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.2031492424
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.2390214749
Short name T747
Test name
Test status
Simulation time 42785485 ps
CPU time 1.58 seconds
Started Jul 14 06:59:43 PM PDT 24
Finished Jul 14 06:59:47 PM PDT 24
Peak memory 220372 kb
Host smart-2d8777f5-fd27-45c8-91a4-c8cadc90cdbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390214749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2390214749
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.3457170967
Short name T974
Test name
Test status
Simulation time 28391141 ps
CPU time 1.28 seconds
Started Jul 14 06:59:54 PM PDT 24
Finished Jul 14 07:00:01 PM PDT 24
Peak memory 218900 kb
Host smart-d6820d3a-c96f-4d0d-a272-b513c8b873e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457170967 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.3457170967
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.3656212114
Short name T759
Test name
Test status
Simulation time 89569789 ps
CPU time 1.39 seconds
Started Jul 14 06:59:52 PM PDT 24
Finished Jul 14 06:59:56 PM PDT 24
Peak memory 217720 kb
Host smart-3eee7f88-9064-4377-9b47-482d09c35633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656212114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3656212114
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.2649440395
Short name T820
Test name
Test status
Simulation time 33743640 ps
CPU time 1.21 seconds
Started Jul 14 07:00:07 PM PDT 24
Finished Jul 14 07:00:16 PM PDT 24
Peak memory 218756 kb
Host smart-6baf0a01-ac77-4005-8818-1c0c4e38f3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649440395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.2649440395
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.3014170546
Short name T862
Test name
Test status
Simulation time 70526874 ps
CPU time 1.1 seconds
Started Jul 14 06:58:13 PM PDT 24
Finished Jul 14 06:58:21 PM PDT 24
Peak memory 221408 kb
Host smart-76497d33-3a12-4d62-ab4f-a142aa9e8d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014170546 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.3014170546
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.874081238
Short name T605
Test name
Test status
Simulation time 62826904 ps
CPU time 0.92 seconds
Started Jul 14 06:58:30 PM PDT 24
Finished Jul 14 06:58:32 PM PDT 24
Peak memory 215460 kb
Host smart-aac56390-8bc2-406e-b2c3-83ed9aa59f59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874081238 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.874081238
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.3951570289
Short name T238
Test name
Test status
Simulation time 15117462 ps
CPU time 0.9 seconds
Started Jul 14 06:58:28 PM PDT 24
Finished Jul 14 06:58:31 PM PDT 24
Peak memory 216676 kb
Host smart-dd8a750c-9580-4e34-a5a7-04062eb4a7ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951570289 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.3951570289
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_err.2552069883
Short name T703
Test name
Test status
Simulation time 29867897 ps
CPU time 0.91 seconds
Started Jul 14 06:58:44 PM PDT 24
Finished Jul 14 06:58:47 PM PDT 24
Peak memory 219428 kb
Host smart-b91ada1e-cb80-443b-b4df-97bcd10a11ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552069883 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.2552069883
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_intr.1677978584
Short name T833
Test name
Test status
Simulation time 40508167 ps
CPU time 0.95 seconds
Started Jul 14 06:58:20 PM PDT 24
Finished Jul 14 06:58:26 PM PDT 24
Peak memory 224256 kb
Host smart-aa482a65-ef9d-492f-865e-96ce8ccb4b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677978584 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1677978584
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.321373723
Short name T694
Test name
Test status
Simulation time 37456095 ps
CPU time 0.91 seconds
Started Jul 14 06:58:09 PM PDT 24
Finished Jul 14 06:58:16 PM PDT 24
Peak memory 215584 kb
Host smart-0f16c5ce-5652-476c-9545-624c66fa12b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321373723 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.321373723
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.341880140
Short name T503
Test name
Test status
Simulation time 382812784 ps
CPU time 3.66 seconds
Started Jul 14 06:58:05 PM PDT 24
Finished Jul 14 06:58:12 PM PDT 24
Peak memory 217600 kb
Host smart-773b2483-ea07-4e31-a7e5-bcf8b675acf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341880140 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.341880140
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.688248656
Short name T35
Test name
Test status
Simulation time 165112247336 ps
CPU time 1090.89 seconds
Started Jul 14 06:58:10 PM PDT 24
Finished Jul 14 07:16:28 PM PDT 24
Peak memory 224224 kb
Host smart-dd3aeeea-9427-4936-b38c-0b1101c3290c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688248656 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.688248656
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.4022469417
Short name T889
Test name
Test status
Simulation time 44816037 ps
CPU time 1.16 seconds
Started Jul 14 06:59:59 PM PDT 24
Finished Jul 14 07:00:09 PM PDT 24
Peak memory 221084 kb
Host smart-ab9587de-7d49-49f3-a63a-426e0e02ac75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022469417 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.4022469417
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/181.edn_alert.3111481802
Short name T639
Test name
Test status
Simulation time 126979145 ps
CPU time 1.13 seconds
Started Jul 14 06:59:58 PM PDT 24
Finished Jul 14 07:00:07 PM PDT 24
Peak memory 218756 kb
Host smart-408f7fcb-a7fb-480f-8c05-9dc5257dc99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111481802 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.3111481802
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.3187164523
Short name T574
Test name
Test status
Simulation time 51562444 ps
CPU time 1.43 seconds
Started Jul 14 06:59:54 PM PDT 24
Finished Jul 14 07:00:02 PM PDT 24
Peak memory 218952 kb
Host smart-b12a17c4-da8c-4d6d-9140-f1def97ac16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187164523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3187164523
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.334696564
Short name T175
Test name
Test status
Simulation time 66063337 ps
CPU time 1.18 seconds
Started Jul 14 06:59:50 PM PDT 24
Finished Jul 14 06:59:52 PM PDT 24
Peak memory 219984 kb
Host smart-11b30956-a3b3-4f69-9784-cb76ef28a70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334696564 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.334696564
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.3444322122
Short name T923
Test name
Test status
Simulation time 51831855 ps
CPU time 1.42 seconds
Started Jul 14 06:59:54 PM PDT 24
Finished Jul 14 07:00:01 PM PDT 24
Peak memory 219044 kb
Host smart-dd9e5690-dd2c-4d96-87cc-ffdc7af134ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444322122 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.3444322122
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.1146061427
Short name T111
Test name
Test status
Simulation time 28082321 ps
CPU time 1.17 seconds
Started Jul 14 06:59:51 PM PDT 24
Finished Jul 14 06:59:54 PM PDT 24
Peak memory 219992 kb
Host smart-0366861f-370c-4b32-a669-be9fa894198b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146061427 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.1146061427
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.2822070204
Short name T606
Test name
Test status
Simulation time 42424590 ps
CPU time 1.83 seconds
Started Jul 14 06:59:51 PM PDT 24
Finished Jul 14 06:59:54 PM PDT 24
Peak memory 218960 kb
Host smart-4128c11b-1b92-46fc-ae48-1dc7338e3d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822070204 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.2822070204
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.1224289109
Short name T715
Test name
Test status
Simulation time 39136195 ps
CPU time 1.13 seconds
Started Jul 14 06:59:57 PM PDT 24
Finished Jul 14 07:00:05 PM PDT 24
Peak memory 218932 kb
Host smart-0a3dd893-b055-4158-9e33-d0f4d1e76003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224289109 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.1224289109
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.2710753682
Short name T329
Test name
Test status
Simulation time 47933429 ps
CPU time 1.58 seconds
Started Jul 14 06:59:46 PM PDT 24
Finished Jul 14 06:59:49 PM PDT 24
Peak memory 218696 kb
Host smart-d638f7df-a95c-4bcb-93c5-6e8181517912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710753682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.2710753682
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.1826779681
Short name T488
Test name
Test status
Simulation time 68677591 ps
CPU time 1.09 seconds
Started Jul 14 07:00:04 PM PDT 24
Finished Jul 14 07:00:12 PM PDT 24
Peak memory 219084 kb
Host smart-64e25efe-8c5d-4783-9d81-b2a79c79106e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826779681 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.1826779681
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/186.edn_alert.328733608
Short name T714
Test name
Test status
Simulation time 68818204 ps
CPU time 1.09 seconds
Started Jul 14 07:00:06 PM PDT 24
Finished Jul 14 07:00:14 PM PDT 24
Peak memory 219016 kb
Host smart-524515b6-37b9-42d6-8921-be055a3b4cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328733608 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.328733608
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.284294776
Short name T356
Test name
Test status
Simulation time 117578532 ps
CPU time 1.04 seconds
Started Jul 14 07:00:11 PM PDT 24
Finished Jul 14 07:00:17 PM PDT 24
Peak memory 217600 kb
Host smart-a1bc1db2-5f50-4b5b-aa05-47e980e2c757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284294776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.284294776
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.4015577623
Short name T892
Test name
Test status
Simulation time 110628228 ps
CPU time 1.31 seconds
Started Jul 14 06:59:50 PM PDT 24
Finished Jul 14 06:59:53 PM PDT 24
Peak memory 215960 kb
Host smart-1045c462-e3a4-4cff-acdc-85431a5cabf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015577623 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.4015577623
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.3746144094
Short name T809
Test name
Test status
Simulation time 53483407 ps
CPU time 1.15 seconds
Started Jul 14 06:59:50 PM PDT 24
Finished Jul 14 06:59:52 PM PDT 24
Peak memory 217616 kb
Host smart-3d62ee7c-c0b9-43df-9b4f-01c5de8b0bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746144094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.3746144094
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.3429087307
Short name T821
Test name
Test status
Simulation time 23465580 ps
CPU time 1.22 seconds
Started Jul 14 06:59:59 PM PDT 24
Finished Jul 14 07:00:08 PM PDT 24
Peak memory 219036 kb
Host smart-047b426b-cf78-4ba4-b2b2-de64fd28cff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429087307 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.3429087307
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.3268601739
Short name T806
Test name
Test status
Simulation time 36814449 ps
CPU time 1.51 seconds
Started Jul 14 07:00:00 PM PDT 24
Finished Jul 14 07:00:10 PM PDT 24
Peak memory 220220 kb
Host smart-c86ee368-a184-4fd0-8ed7-27e79199ccdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268601739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3268601739
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.2214209170
Short name T539
Test name
Test status
Simulation time 38969950 ps
CPU time 1.06 seconds
Started Jul 14 07:00:19 PM PDT 24
Finished Jul 14 07:00:30 PM PDT 24
Peak memory 219068 kb
Host smart-30e059a7-3706-45cf-9d7b-7a78c4feb828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214209170 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.2214209170
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.1131058638
Short name T438
Test name
Test status
Simulation time 60216024 ps
CPU time 1.18 seconds
Started Jul 14 06:59:59 PM PDT 24
Finished Jul 14 07:00:09 PM PDT 24
Peak memory 218692 kb
Host smart-ed1626a9-9e31-493e-b4f1-0ebd5acb1749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131058638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.1131058638
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.3964791268
Short name T99
Test name
Test status
Simulation time 27386175 ps
CPU time 1.22 seconds
Started Jul 14 06:58:44 PM PDT 24
Finished Jul 14 06:58:47 PM PDT 24
Peak memory 219524 kb
Host smart-2a174c2a-53a2-45d0-ba3c-356f63afc603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964791268 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.3964791268
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.4141295685
Short name T69
Test name
Test status
Simulation time 27134985 ps
CPU time 1.02 seconds
Started Jul 14 06:58:12 PM PDT 24
Finished Jul 14 06:58:20 PM PDT 24
Peak memory 207088 kb
Host smart-f0d9a1ec-3d08-4d69-9895-c8557ef34af5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141295685 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.4141295685
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.873136413
Short name T85
Test name
Test status
Simulation time 31030733 ps
CPU time 0.89 seconds
Started Jul 14 06:58:30 PM PDT 24
Finished Jul 14 06:58:33 PM PDT 24
Peak memory 215708 kb
Host smart-64cd5abc-89ec-43cb-8018-2192fe9f6e74
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873136413 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.873136413
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.1435921327
Short name T684
Test name
Test status
Simulation time 30728122 ps
CPU time 1.01 seconds
Started Jul 14 06:58:09 PM PDT 24
Finished Jul 14 06:58:16 PM PDT 24
Peak memory 218540 kb
Host smart-6f4d9cd3-411a-435c-a745-87596f3eec07
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435921327 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.1435921327
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.3889428364
Short name T138
Test name
Test status
Simulation time 24037511 ps
CPU time 1.22 seconds
Started Jul 14 06:58:32 PM PDT 24
Finished Jul 14 06:58:36 PM PDT 24
Peak memory 219900 kb
Host smart-0dae196c-918b-47e2-bc16-5a3646255839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889428364 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.3889428364
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.1492441792
Short name T818
Test name
Test status
Simulation time 43260485 ps
CPU time 1.45 seconds
Started Jul 14 06:58:08 PM PDT 24
Finished Jul 14 06:58:15 PM PDT 24
Peak memory 218760 kb
Host smart-7d83ac77-f18b-41d5-9c43-7ebc2f53f195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492441792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.1492441792
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_smoke.4052794599
Short name T471
Test name
Test status
Simulation time 18202056 ps
CPU time 0.96 seconds
Started Jul 14 06:58:06 PM PDT 24
Finished Jul 14 06:58:11 PM PDT 24
Peak memory 215488 kb
Host smart-7a9de3d3-8100-4971-941e-d854af523a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052794599 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.4052794599
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.3004893373
Short name T829
Test name
Test status
Simulation time 35098854700 ps
CPU time 389.83 seconds
Started Jul 14 06:58:12 PM PDT 24
Finished Jul 14 07:04:49 PM PDT 24
Peak memory 221204 kb
Host smart-65e7e865-9b01-45bb-92a9-db1f139c0efa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004893373 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.3004893373
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.1574310446
Short name T810
Test name
Test status
Simulation time 82922050 ps
CPU time 1.13 seconds
Started Jul 14 06:59:57 PM PDT 24
Finished Jul 14 07:00:05 PM PDT 24
Peak memory 220088 kb
Host smart-86eca83b-8890-479c-99c4-a3a842a4005a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574310446 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.1574310446
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.3818138518
Short name T345
Test name
Test status
Simulation time 38085015 ps
CPU time 1.32 seconds
Started Jul 14 06:59:58 PM PDT 24
Finished Jul 14 07:00:08 PM PDT 24
Peak memory 217488 kb
Host smart-1d660543-5fb7-4667-92db-56279eafc582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818138518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3818138518
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.528415663
Short name T21
Test name
Test status
Simulation time 24944192 ps
CPU time 1.23 seconds
Started Jul 14 06:59:52 PM PDT 24
Finished Jul 14 06:59:57 PM PDT 24
Peak memory 218916 kb
Host smart-65a70670-f1cc-42b4-b414-ed60b6249b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528415663 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.528415663
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.2069015374
Short name T337
Test name
Test status
Simulation time 98620805 ps
CPU time 1.28 seconds
Started Jul 14 06:59:50 PM PDT 24
Finished Jul 14 06:59:53 PM PDT 24
Peak memory 217656 kb
Host smart-cec8b0a5-c5a5-4ce5-8f8b-3eeede9edf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069015374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2069015374
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.1746092813
Short name T805
Test name
Test status
Simulation time 51433742 ps
CPU time 2.04 seconds
Started Jul 14 06:59:55 PM PDT 24
Finished Jul 14 07:00:03 PM PDT 24
Peak memory 219108 kb
Host smart-961917e3-b046-4924-a1f2-3f2f04c989aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746092813 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.1746092813
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.66031300
Short name T305
Test name
Test status
Simulation time 68329788 ps
CPU time 1.22 seconds
Started Jul 14 06:59:54 PM PDT 24
Finished Jul 14 07:00:02 PM PDT 24
Peak memory 215996 kb
Host smart-34b9b72a-e2b3-4b06-b714-2ad0110c1faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66031300 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.66031300
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.2684792509
Short name T496
Test name
Test status
Simulation time 39840109 ps
CPU time 1.55 seconds
Started Jul 14 07:00:07 PM PDT 24
Finished Jul 14 07:00:15 PM PDT 24
Peak memory 217640 kb
Host smart-47a27a67-895c-481c-a2e9-a916a726ef81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684792509 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.2684792509
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.333638400
Short name T838
Test name
Test status
Simulation time 41141452 ps
CPU time 1.22 seconds
Started Jul 14 06:59:49 PM PDT 24
Finished Jul 14 06:59:51 PM PDT 24
Peak memory 219816 kb
Host smart-feb0222a-b474-4940-a6cb-c7f572516952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333638400 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.333638400
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.681622826
Short name T557
Test name
Test status
Simulation time 150217145 ps
CPU time 1.23 seconds
Started Jul 14 06:59:58 PM PDT 24
Finished Jul 14 07:00:08 PM PDT 24
Peak memory 217336 kb
Host smart-1899087d-2896-446a-93ce-719b25b64d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681622826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.681622826
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.1360093817
Short name T399
Test name
Test status
Simulation time 124387440 ps
CPU time 1.44 seconds
Started Jul 14 06:59:56 PM PDT 24
Finished Jul 14 07:00:04 PM PDT 24
Peak memory 218936 kb
Host smart-eab52d62-e54b-4097-93dc-95fbebcb4b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360093817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.1360093817
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.3285800858
Short name T75
Test name
Test status
Simulation time 89188065 ps
CPU time 1.25 seconds
Started Jul 14 07:00:00 PM PDT 24
Finished Jul 14 07:00:10 PM PDT 24
Peak memory 219880 kb
Host smart-9a92b0ac-afbc-47c2-89c6-a650dc9d8f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285800858 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.3285800858
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.3015192863
Short name T685
Test name
Test status
Simulation time 58483321 ps
CPU time 1.28 seconds
Started Jul 14 06:59:54 PM PDT 24
Finished Jul 14 07:00:02 PM PDT 24
Peak memory 217572 kb
Host smart-74ff6b4e-b4a0-4825-bd1d-c3e2de69c091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015192863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3015192863
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.2205286302
Short name T163
Test name
Test status
Simulation time 41571743 ps
CPU time 1.15 seconds
Started Jul 14 06:59:59 PM PDT 24
Finished Jul 14 07:00:09 PM PDT 24
Peak memory 219300 kb
Host smart-8e22b39b-7a11-461a-a38f-7d158053ec34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205286302 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.2205286302
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.3504974290
Short name T596
Test name
Test status
Simulation time 48938153 ps
CPU time 1.08 seconds
Started Jul 14 06:59:54 PM PDT 24
Finished Jul 14 07:00:00 PM PDT 24
Peak memory 217632 kb
Host smart-a8798ee7-94df-4019-b31f-888580cd67a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504974290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3504974290
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.3583118841
Short name T131
Test name
Test status
Simulation time 138965588 ps
CPU time 1.28 seconds
Started Jul 14 06:59:58 PM PDT 24
Finished Jul 14 07:00:08 PM PDT 24
Peak memory 218584 kb
Host smart-dcd3a174-b948-4467-bcf4-933dffaa3b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583118841 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.3583118841
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.1296686869
Short name T973
Test name
Test status
Simulation time 36756716 ps
CPU time 1.35 seconds
Started Jul 14 06:59:59 PM PDT 24
Finished Jul 14 07:00:09 PM PDT 24
Peak memory 219624 kb
Host smart-0bc32014-f58f-49e8-993a-6d5cb71be4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296686869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.1296686869
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.2803978025
Short name T537
Test name
Test status
Simulation time 97035235 ps
CPU time 1.02 seconds
Started Jul 14 06:59:49 PM PDT 24
Finished Jul 14 06:59:51 PM PDT 24
Peak memory 218952 kb
Host smart-4b8b9942-deb3-460f-acd5-622a686d2c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803978025 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.2803978025
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.206080320
Short name T770
Test name
Test status
Simulation time 49436754 ps
CPU time 1.2 seconds
Started Jul 14 06:59:51 PM PDT 24
Finished Jul 14 06:59:54 PM PDT 24
Peak memory 215572 kb
Host smart-f3247aff-cc83-49de-abaf-31e7ea264b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206080320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.206080320
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.3814054914
Short name T176
Test name
Test status
Simulation time 24847093 ps
CPU time 1.26 seconds
Started Jul 14 06:58:01 PM PDT 24
Finished Jul 14 06:58:03 PM PDT 24
Peak memory 220044 kb
Host smart-8ef343df-8618-4286-ab68-b65ab941ded9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814054914 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.3814054914
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.3871998853
Short name T351
Test name
Test status
Simulation time 23098859 ps
CPU time 0.9 seconds
Started Jul 14 06:58:07 PM PDT 24
Finished Jul 14 06:58:12 PM PDT 24
Peak memory 207080 kb
Host smart-2e9c394d-c873-4476-b013-66de79a72733
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871998853 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3871998853
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.3458857822
Short name T368
Test name
Test status
Simulation time 14833381 ps
CPU time 0.87 seconds
Started Jul 14 06:57:52 PM PDT 24
Finished Jul 14 06:57:54 PM PDT 24
Peak memory 216664 kb
Host smart-165264c8-def5-42ae-9a78-cb1c435fe52d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458857822 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.3458857822
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.2413454846
Short name T152
Test name
Test status
Simulation time 49415363 ps
CPU time 1.5 seconds
Started Jul 14 06:58:25 PM PDT 24
Finished Jul 14 06:58:28 PM PDT 24
Peak memory 217108 kb
Host smart-608dfac1-2169-45bb-b62d-75ed0d809c87
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413454846 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.2413454846
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.672340692
Short name T52
Test name
Test status
Simulation time 30776927 ps
CPU time 0.99 seconds
Started Jul 14 06:57:58 PM PDT 24
Finished Jul 14 06:58:00 PM PDT 24
Peak memory 224032 kb
Host smart-6822c75b-1621-4eb5-8630-1d960d3f4e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672340692 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.672340692
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.1889238973
Short name T482
Test name
Test status
Simulation time 134053212 ps
CPU time 1.4 seconds
Started Jul 14 06:58:02 PM PDT 24
Finished Jul 14 06:58:04 PM PDT 24
Peak memory 218952 kb
Host smart-f4e85309-a017-4f34-9e0e-dd078b67f445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889238973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1889238973
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_regwen.527581528
Short name T516
Test name
Test status
Simulation time 30528651 ps
CPU time 0.98 seconds
Started Jul 14 06:58:10 PM PDT 24
Finished Jul 14 06:58:18 PM PDT 24
Peak memory 207400 kb
Host smart-c4c69d0f-bd33-46fc-b3cf-45aef37fb506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527581528 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.527581528
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_smoke.2928657592
Short name T458
Test name
Test status
Simulation time 18324908 ps
CPU time 0.98 seconds
Started Jul 14 06:58:00 PM PDT 24
Finished Jul 14 06:58:02 PM PDT 24
Peak memory 215592 kb
Host smart-c79431dc-345d-477e-a1f4-8fd04c40b181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928657592 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.2928657592
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.517512114
Short name T378
Test name
Test status
Simulation time 750336455 ps
CPU time 2.44 seconds
Started Jul 14 06:57:58 PM PDT 24
Finished Jul 14 06:58:02 PM PDT 24
Peak memory 217712 kb
Host smart-b73e3699-b1b2-407f-b019-837d36f03a49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517512114 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.517512114
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.288889870
Short name T229
Test name
Test status
Simulation time 100741862823 ps
CPU time 559.4 seconds
Started Jul 14 06:58:09 PM PDT 24
Finished Jul 14 07:07:35 PM PDT 24
Peak memory 219760 kb
Host smart-4e08a3a7-c16b-4c07-bc26-60dae3f3c9a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288889870 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.288889870
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.4051267226
Short name T109
Test name
Test status
Simulation time 50897285 ps
CPU time 1.27 seconds
Started Jul 14 06:58:38 PM PDT 24
Finished Jul 14 06:58:41 PM PDT 24
Peak memory 220256 kb
Host smart-b7892367-e319-4142-b375-8ecde39eb908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051267226 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.4051267226
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.2972211274
Short name T514
Test name
Test status
Simulation time 18394555 ps
CPU time 0.92 seconds
Started Jul 14 06:58:32 PM PDT 24
Finished Jul 14 06:58:35 PM PDT 24
Peak memory 206976 kb
Host smart-66c03c58-c3cc-42a4-a4ca-4745125faab9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972211274 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2972211274
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.3279407921
Short name T36
Test name
Test status
Simulation time 29358800 ps
CPU time 0.84 seconds
Started Jul 14 06:58:26 PM PDT 24
Finished Jul 14 06:58:28 PM PDT 24
Peak memory 215644 kb
Host smart-d73b75e1-ce25-404c-91c1-ca8407e0664a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279407921 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3279407921
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.1735415232
Short name T122
Test name
Test status
Simulation time 29632452 ps
CPU time 1.16 seconds
Started Jul 14 06:58:10 PM PDT 24
Finished Jul 14 06:58:18 PM PDT 24
Peak memory 217064 kb
Host smart-fbab4214-2619-41cb-a164-33eb2d6ad1e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735415232 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.1735415232
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.1983958933
Short name T137
Test name
Test status
Simulation time 65284167 ps
CPU time 0.99 seconds
Started Jul 14 06:58:40 PM PDT 24
Finished Jul 14 06:58:43 PM PDT 24
Peak memory 229716 kb
Host smart-2ea2fad2-3450-460b-a32f-6ae4606628af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983958933 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.1983958933
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.3102224581
Short name T316
Test name
Test status
Simulation time 176011531 ps
CPU time 2.49 seconds
Started Jul 14 06:58:10 PM PDT 24
Finished Jul 14 06:58:19 PM PDT 24
Peak memory 217660 kb
Host smart-4dbab2a6-b572-47b6-844b-9368a397aee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102224581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3102224581
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.2061456594
Short name T653
Test name
Test status
Simulation time 20941333 ps
CPU time 1.09 seconds
Started Jul 14 06:58:10 PM PDT 24
Finished Jul 14 06:58:19 PM PDT 24
Peak memory 215708 kb
Host smart-7e434550-dc44-4f11-b32b-3dd4bd3b9bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061456594 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.2061456594
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.2192135490
Short name T453
Test name
Test status
Simulation time 26045925 ps
CPU time 0.92 seconds
Started Jul 14 06:58:32 PM PDT 24
Finished Jul 14 06:58:35 PM PDT 24
Peak memory 215568 kb
Host smart-5a7beaa5-e6d0-4240-9746-b13a952919a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192135490 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.2192135490
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.2434009567
Short name T702
Test name
Test status
Simulation time 440879457 ps
CPU time 1.31 seconds
Started Jul 14 06:58:07 PM PDT 24
Finished Jul 14 06:58:14 PM PDT 24
Peak memory 215508 kb
Host smart-b42da104-ad1f-467a-970c-66f7157bf755
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434009567 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2434009567
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.3499746382
Short name T386
Test name
Test status
Simulation time 29212018086 ps
CPU time 749.38 seconds
Started Jul 14 06:58:29 PM PDT 24
Finished Jul 14 07:10:59 PM PDT 24
Peak memory 221404 kb
Host smart-373fe31c-1782-4649-9e52-e542ed1953a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499746382 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.3499746382
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.3117791681
Short name T873
Test name
Test status
Simulation time 139037252 ps
CPU time 2.99 seconds
Started Jul 14 06:59:57 PM PDT 24
Finished Jul 14 07:00:07 PM PDT 24
Peak memory 220376 kb
Host smart-1ea1d691-d9ad-4a8c-a3ff-37e502cb932e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117791681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3117791681
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.3649845193
Short name T658
Test name
Test status
Simulation time 261750263 ps
CPU time 3.04 seconds
Started Jul 14 06:59:51 PM PDT 24
Finished Jul 14 06:59:56 PM PDT 24
Peak memory 220092 kb
Host smart-5c3862c5-9538-49be-95f6-1ce821e0acd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649845193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.3649845193
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.1816812242
Short name T904
Test name
Test status
Simulation time 112338767 ps
CPU time 1.31 seconds
Started Jul 14 06:59:53 PM PDT 24
Finished Jul 14 06:59:59 PM PDT 24
Peak memory 220244 kb
Host smart-e0579f20-f22c-4f35-ba8f-7343f1a671c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816812242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.1816812242
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.178910415
Short name T765
Test name
Test status
Simulation time 31182624 ps
CPU time 1.28 seconds
Started Jul 14 06:59:49 PM PDT 24
Finished Jul 14 06:59:52 PM PDT 24
Peak memory 220248 kb
Host smart-1ed760d0-5829-4309-aa64-7db695098667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178910415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.178910415
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.1646980901
Short name T689
Test name
Test status
Simulation time 57426865 ps
CPU time 1.23 seconds
Started Jul 14 07:00:02 PM PDT 24
Finished Jul 14 07:00:12 PM PDT 24
Peak memory 220064 kb
Host smart-0e719e7c-bf87-48eb-8db0-e58d99836791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646980901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.1646980901
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.1398005454
Short name T909
Test name
Test status
Simulation time 77059922 ps
CPU time 1.09 seconds
Started Jul 14 07:00:10 PM PDT 24
Finished Jul 14 07:00:17 PM PDT 24
Peak memory 217460 kb
Host smart-38296068-8377-4865-bfd3-6499af1691e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398005454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1398005454
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.766696827
Short name T601
Test name
Test status
Simulation time 70629940 ps
CPU time 1.08 seconds
Started Jul 14 06:59:50 PM PDT 24
Finished Jul 14 06:59:52 PM PDT 24
Peak memory 217776 kb
Host smart-c836c5db-d66a-484f-8c4f-7797873a9961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766696827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.766696827
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.875097714
Short name T807
Test name
Test status
Simulation time 162986195 ps
CPU time 1.68 seconds
Started Jul 14 06:59:54 PM PDT 24
Finished Jul 14 07:00:00 PM PDT 24
Peak memory 219180 kb
Host smart-aa3094b2-280a-4361-8ed5-83dcb0d024ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875097714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.875097714
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.2696398736
Short name T325
Test name
Test status
Simulation time 132678989 ps
CPU time 2.54 seconds
Started Jul 14 06:59:58 PM PDT 24
Finished Jul 14 07:00:08 PM PDT 24
Peak memory 220488 kb
Host smart-e1916e75-b246-4873-8b62-75c00d780955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696398736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.2696398736
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.1806914890
Short name T404
Test name
Test status
Simulation time 52859909 ps
CPU time 1.15 seconds
Started Jul 14 07:00:01 PM PDT 24
Finished Jul 14 07:00:11 PM PDT 24
Peak memory 217640 kb
Host smart-78efa261-0bff-4520-86b6-9ee3aee2fb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806914890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.1806914890
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.2297101516
Short name T519
Test name
Test status
Simulation time 68968158 ps
CPU time 1.02 seconds
Started Jul 14 06:58:30 PM PDT 24
Finished Jul 14 06:58:38 PM PDT 24
Peak memory 218732 kb
Host smart-03993da8-f842-4f46-b492-35c9da434e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297101516 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.2297101516
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.2423588478
Short name T246
Test name
Test status
Simulation time 20877575 ps
CPU time 0.81 seconds
Started Jul 14 06:58:30 PM PDT 24
Finished Jul 14 06:58:33 PM PDT 24
Peak memory 207060 kb
Host smart-260aeefe-854d-4eb5-80cc-a5efec6c1dcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423588478 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2423588478
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.581461055
Short name T668
Test name
Test status
Simulation time 58675818 ps
CPU time 0.99 seconds
Started Jul 14 06:58:11 PM PDT 24
Finished Jul 14 06:58:20 PM PDT 24
Peak memory 215932 kb
Host smart-3337daad-b7e8-4873-9b33-b245c7074b82
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581461055 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_di
sable_auto_req_mode.581461055
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.1690813142
Short name T579
Test name
Test status
Simulation time 28175483 ps
CPU time 0.87 seconds
Started Jul 14 06:58:41 PM PDT 24
Finished Jul 14 06:58:43 PM PDT 24
Peak memory 218496 kb
Host smart-8c0ca0e9-d1fb-4f36-956a-7c2364fc2abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690813142 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.1690813142
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.1987968690
Short name T19
Test name
Test status
Simulation time 80741072 ps
CPU time 1.24 seconds
Started Jul 14 06:58:11 PM PDT 24
Finished Jul 14 06:58:20 PM PDT 24
Peak memory 219864 kb
Host smart-f6c5d2b0-cf71-4f36-9226-f4195153f91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987968690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.1987968690
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.3220869899
Short name T680
Test name
Test status
Simulation time 23986890 ps
CPU time 1.08 seconds
Started Jul 14 06:58:10 PM PDT 24
Finished Jul 14 06:58:19 PM PDT 24
Peak memory 224184 kb
Host smart-7335b5d2-7de2-47bc-959e-e145d833b9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220869899 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3220869899
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.3232403274
Short name T995
Test name
Test status
Simulation time 35544652 ps
CPU time 0.87 seconds
Started Jul 14 06:58:31 PM PDT 24
Finished Jul 14 06:58:34 PM PDT 24
Peak memory 215568 kb
Host smart-60bfcc23-add7-4ade-a92e-2e3205fb9143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232403274 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.3232403274
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.339961783
Short name T72
Test name
Test status
Simulation time 82677379 ps
CPU time 1.5 seconds
Started Jul 14 06:58:31 PM PDT 24
Finished Jul 14 06:58:35 PM PDT 24
Peak memory 215640 kb
Host smart-b5dff0c2-cd61-4f26-8cee-71de342b58b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339961783 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.339961783
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.475166463
Short name T526
Test name
Test status
Simulation time 215357475360 ps
CPU time 1349.6 seconds
Started Jul 14 06:58:42 PM PDT 24
Finished Jul 14 07:21:12 PM PDT 24
Peak memory 226196 kb
Host smart-5c8b4f46-ea04-47d2-84ab-db05ea031eeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475166463 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.475166463
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.916782713
Short name T975
Test name
Test status
Simulation time 91388676 ps
CPU time 1.22 seconds
Started Jul 14 06:59:56 PM PDT 24
Finished Jul 14 07:00:03 PM PDT 24
Peak memory 217564 kb
Host smart-9f0ec56f-6529-4d5e-acf8-3529115a635f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916782713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.916782713
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.4247827454
Short name T241
Test name
Test status
Simulation time 49564988 ps
CPU time 1.17 seconds
Started Jul 14 06:59:56 PM PDT 24
Finished Jul 14 07:00:03 PM PDT 24
Peak memory 215524 kb
Host smart-6bb74a61-9405-42c7-aa4e-1d04bcb6242d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247827454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.4247827454
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.1399901557
Short name T83
Test name
Test status
Simulation time 31684985 ps
CPU time 1.11 seconds
Started Jul 14 07:00:07 PM PDT 24
Finished Jul 14 07:00:15 PM PDT 24
Peak memory 217724 kb
Host smart-545011f7-c501-456b-8148-854d233ae031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399901557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.1399901557
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.2034355685
Short name T755
Test name
Test status
Simulation time 36011534 ps
CPU time 1.25 seconds
Started Jul 14 07:00:08 PM PDT 24
Finished Jul 14 07:00:16 PM PDT 24
Peak memory 218608 kb
Host smart-eb354ffe-5e01-4093-85fc-6b4cb84168a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034355685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.2034355685
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.3666412169
Short name T788
Test name
Test status
Simulation time 46817792 ps
CPU time 1.34 seconds
Started Jul 14 06:59:55 PM PDT 24
Finished Jul 14 07:00:02 PM PDT 24
Peak memory 218768 kb
Host smart-587a5b96-dd2f-4bf0-ab1c-13c2c3506c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666412169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.3666412169
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.3823991453
Short name T691
Test name
Test status
Simulation time 47335526 ps
CPU time 1.2 seconds
Started Jul 14 06:59:55 PM PDT 24
Finished Jul 14 07:00:04 PM PDT 24
Peak memory 220168 kb
Host smart-32414596-81af-49b5-a715-35c9de792a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823991453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.3823991453
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.2058893625
Short name T638
Test name
Test status
Simulation time 84979280 ps
CPU time 1.17 seconds
Started Jul 14 06:59:53 PM PDT 24
Finished Jul 14 06:59:56 PM PDT 24
Peak memory 217544 kb
Host smart-d042e664-dc9d-43ba-bee3-8f353b3eac8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058893625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2058893625
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.3893996047
Short name T859
Test name
Test status
Simulation time 80003339 ps
CPU time 1.12 seconds
Started Jul 14 07:00:20 PM PDT 24
Finished Jul 14 07:00:26 PM PDT 24
Peak memory 217604 kb
Host smart-a0f4b16b-bf17-426b-b3b3-9b463c7fe1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893996047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.3893996047
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.1906411291
Short name T571
Test name
Test status
Simulation time 113692915 ps
CPU time 2.2 seconds
Started Jul 14 07:00:02 PM PDT 24
Finished Jul 14 07:00:13 PM PDT 24
Peak memory 220020 kb
Host smart-5c5ab7c3-29b5-4970-bc9c-62f76ebf7524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906411291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.1906411291
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.324524250
Short name T290
Test name
Test status
Simulation time 210763217 ps
CPU time 2.93 seconds
Started Jul 14 06:59:56 PM PDT 24
Finished Jul 14 07:00:05 PM PDT 24
Peak memory 218184 kb
Host smart-225c56ee-0cba-45d9-bf1c-f03afc98c807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324524250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.324524250
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.3131686039
Short name T739
Test name
Test status
Simulation time 29989353 ps
CPU time 1.2 seconds
Started Jul 14 06:58:12 PM PDT 24
Finished Jul 14 06:58:20 PM PDT 24
Peak memory 220148 kb
Host smart-147a69e0-d5d8-4476-8898-7714bcbd99b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131686039 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.3131686039
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.2848489128
Short name T447
Test name
Test status
Simulation time 19204939 ps
CPU time 0.82 seconds
Started Jul 14 06:58:32 PM PDT 24
Finished Jul 14 06:58:35 PM PDT 24
Peak memory 206992 kb
Host smart-d4bbc933-8e76-4a8f-b2e2-a25d946797b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848489128 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.2848489128
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.2347488252
Short name T217
Test name
Test status
Simulation time 38262009 ps
CPU time 0.86 seconds
Started Jul 14 06:58:10 PM PDT 24
Finished Jul 14 06:58:17 PM PDT 24
Peak memory 216460 kb
Host smart-49a5348c-5065-4682-b7cc-a614f3198441
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347488252 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2347488252
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.3873013430
Short name T473
Test name
Test status
Simulation time 39014283 ps
CPU time 1.02 seconds
Started Jul 14 06:58:34 PM PDT 24
Finished Jul 14 06:58:38 PM PDT 24
Peak memory 218820 kb
Host smart-ce134adf-0568-4173-aba6-11b24e70267e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873013430 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.3873013430
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.2797077987
Short name T179
Test name
Test status
Simulation time 24151117 ps
CPU time 1.03 seconds
Started Jul 14 06:58:09 PM PDT 24
Finished Jul 14 06:58:17 PM PDT 24
Peak memory 224448 kb
Host smart-62c06e52-4c7f-429f-b60c-d601db4c7ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797077987 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.2797077987
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.270892554
Short name T353
Test name
Test status
Simulation time 39690427 ps
CPU time 1.31 seconds
Started Jul 14 06:58:14 PM PDT 24
Finished Jul 14 06:58:22 PM PDT 24
Peak memory 217648 kb
Host smart-35ab8a45-b3c1-4a5d-a37e-79947ab79604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270892554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.270892554
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.845812890
Short name T478
Test name
Test status
Simulation time 22900947 ps
CPU time 1.09 seconds
Started Jul 14 06:58:32 PM PDT 24
Finished Jul 14 06:58:36 PM PDT 24
Peak memory 215904 kb
Host smart-491901b6-8e5e-4c1d-9d46-b1d638243bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845812890 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.845812890
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.2523742055
Short name T240
Test name
Test status
Simulation time 60829557 ps
CPU time 0.89 seconds
Started Jul 14 06:58:10 PM PDT 24
Finished Jul 14 06:58:17 PM PDT 24
Peak memory 215560 kb
Host smart-ff849a61-83de-4453-a639-548d02c5e075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523742055 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2523742055
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.3786921251
Short name T5
Test name
Test status
Simulation time 491454540 ps
CPU time 1.72 seconds
Started Jul 14 06:58:22 PM PDT 24
Finished Jul 14 06:58:27 PM PDT 24
Peak memory 215608 kb
Host smart-f60a4bbb-2659-4dc9-b27d-1a4ca9c8f17d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786921251 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.3786921251
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.4176673639
Short name T371
Test name
Test status
Simulation time 181879867342 ps
CPU time 1186.25 seconds
Started Jul 14 06:58:11 PM PDT 24
Finished Jul 14 07:18:05 PM PDT 24
Peak memory 225388 kb
Host smart-8d58da05-d0e5-4158-9977-6761f944a00b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176673639 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.4176673639
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.1328982345
Short name T708
Test name
Test status
Simulation time 109553994 ps
CPU time 1.08 seconds
Started Jul 14 06:59:55 PM PDT 24
Finished Jul 14 07:00:02 PM PDT 24
Peak memory 217508 kb
Host smart-dc8d63d4-81bf-4882-b60c-79520ec715c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328982345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.1328982345
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.3971040646
Short name T938
Test name
Test status
Simulation time 48574296 ps
CPU time 1.49 seconds
Started Jul 14 07:00:01 PM PDT 24
Finished Jul 14 07:00:11 PM PDT 24
Peak memory 215608 kb
Host smart-4775c06a-d795-4475-acb0-bbcd23d79dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971040646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3971040646
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.1015985122
Short name T868
Test name
Test status
Simulation time 30870306 ps
CPU time 1.53 seconds
Started Jul 14 06:59:53 PM PDT 24
Finished Jul 14 06:59:59 PM PDT 24
Peak memory 218824 kb
Host smart-5054efe1-8e0c-4e5f-a991-3a1c01618a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015985122 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.1015985122
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.2646752717
Short name T581
Test name
Test status
Simulation time 77240229 ps
CPU time 2.49 seconds
Started Jul 14 06:59:57 PM PDT 24
Finished Jul 14 07:00:07 PM PDT 24
Peak memory 215568 kb
Host smart-84276a6a-734b-489c-a519-cc7fc5fe771c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646752717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2646752717
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.1305725963
Short name T908
Test name
Test status
Simulation time 76222882 ps
CPU time 1.04 seconds
Started Jul 14 07:00:04 PM PDT 24
Finished Jul 14 07:00:13 PM PDT 24
Peak memory 217480 kb
Host smart-c99622b0-cd3b-47f6-92ad-965f539ec3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305725963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.1305725963
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.3251828088
Short name T527
Test name
Test status
Simulation time 90081004 ps
CPU time 1.31 seconds
Started Jul 14 06:59:50 PM PDT 24
Finished Jul 14 06:59:53 PM PDT 24
Peak memory 220224 kb
Host smart-f389d318-fca2-4518-a0aa-a84a9264b26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251828088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.3251828088
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.3394688455
Short name T866
Test name
Test status
Simulation time 51631138 ps
CPU time 1.66 seconds
Started Jul 14 06:59:57 PM PDT 24
Finished Jul 14 07:00:07 PM PDT 24
Peak memory 218820 kb
Host smart-bdf38889-eeee-4272-b392-1753ccdc35a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394688455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3394688455
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.2079290922
Short name T532
Test name
Test status
Simulation time 103835349 ps
CPU time 1.55 seconds
Started Jul 14 06:59:54 PM PDT 24
Finished Jul 14 07:00:02 PM PDT 24
Peak memory 219164 kb
Host smart-0c04b974-f571-4795-9d95-47ea7e7eb52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079290922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.2079290922
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.1540834572
Short name T235
Test name
Test status
Simulation time 143793695 ps
CPU time 1.2 seconds
Started Jul 14 07:00:16 PM PDT 24
Finished Jul 14 07:00:22 PM PDT 24
Peak memory 220308 kb
Host smart-002e03b4-a72a-48c0-8c4f-d477fc956a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540834572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.1540834572
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.1049999408
Short name T764
Test name
Test status
Simulation time 324025929 ps
CPU time 1.18 seconds
Started Jul 14 07:00:08 PM PDT 24
Finished Jul 14 07:00:16 PM PDT 24
Peak memory 217632 kb
Host smart-60fadb81-3191-4842-b4fb-2fc809d11ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049999408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1049999408
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.1674371656
Short name T730
Test name
Test status
Simulation time 23971672 ps
CPU time 1.18 seconds
Started Jul 14 06:58:18 PM PDT 24
Finished Jul 14 06:58:25 PM PDT 24
Peak memory 220260 kb
Host smart-28e78978-da3d-41c9-9fde-93410affb644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674371656 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.1674371656
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.3591622242
Short name T731
Test name
Test status
Simulation time 31294393 ps
CPU time 0.96 seconds
Started Jul 14 06:58:11 PM PDT 24
Finished Jul 14 06:58:19 PM PDT 24
Peak memory 215184 kb
Host smart-aa3f4344-b72f-4d67-bc00-f612e6583514
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591622242 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.3591622242
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.3699735351
Short name T609
Test name
Test status
Simulation time 21518796 ps
CPU time 0.83 seconds
Started Jul 14 06:58:10 PM PDT 24
Finished Jul 14 06:58:18 PM PDT 24
Peak memory 216416 kb
Host smart-2fe08d9d-1dfd-4017-a47d-29bf9c16ad6f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699735351 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3699735351
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3195057197
Short name T126
Test name
Test status
Simulation time 25688905 ps
CPU time 1.02 seconds
Started Jul 14 06:58:13 PM PDT 24
Finished Jul 14 06:58:21 PM PDT 24
Peak memory 217176 kb
Host smart-4c43c9ae-b04c-41dd-bd47-e9182bcfdd96
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195057197 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3195057197
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.373995581
Short name T354
Test name
Test status
Simulation time 46203739 ps
CPU time 0.83 seconds
Started Jul 14 06:58:14 PM PDT 24
Finished Jul 14 06:58:25 PM PDT 24
Peak memory 218424 kb
Host smart-bff7224c-3b55-4df7-aaea-e492e0843594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373995581 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.373995581
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.265379462
Short name T334
Test name
Test status
Simulation time 31856739 ps
CPU time 1.33 seconds
Started Jul 14 06:58:13 PM PDT 24
Finished Jul 14 06:58:21 PM PDT 24
Peak memory 219164 kb
Host smart-3b65998e-c5fa-4b63-9c53-e51eadfc8513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265379462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.265379462
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.3491205035
Short name T93
Test name
Test status
Simulation time 26283692 ps
CPU time 0.87 seconds
Started Jul 14 06:58:47 PM PDT 24
Finished Jul 14 06:58:51 PM PDT 24
Peak memory 216056 kb
Host smart-c5ffa583-48c7-48b3-9e86-bd533919f113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491205035 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3491205035
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.3784790059
Short name T454
Test name
Test status
Simulation time 19827415 ps
CPU time 1.02 seconds
Started Jul 14 06:58:31 PM PDT 24
Finished Jul 14 06:58:35 PM PDT 24
Peak memory 215608 kb
Host smart-d5a69be5-d8aa-4d98-9b11-57663e64d805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784790059 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3784790059
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.2250034615
Short name T524
Test name
Test status
Simulation time 290760459 ps
CPU time 2.52 seconds
Started Jul 14 06:58:13 PM PDT 24
Finished Jul 14 06:58:23 PM PDT 24
Peak memory 217820 kb
Host smart-c126a500-8ad3-4474-aa8e-57484d94e04e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250034615 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.2250034615
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.3436979100
Short name T655
Test name
Test status
Simulation time 19178391980 ps
CPU time 114.16 seconds
Started Jul 14 06:58:36 PM PDT 24
Finished Jul 14 07:00:32 PM PDT 24
Peak memory 218960 kb
Host smart-74f3cec6-0e98-44f4-b225-1f117b00171a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436979100 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.3436979100
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.2084200665
Short name T580
Test name
Test status
Simulation time 32634299 ps
CPU time 1.44 seconds
Started Jul 14 07:00:01 PM PDT 24
Finished Jul 14 07:00:10 PM PDT 24
Peak memory 217552 kb
Host smart-b7ff1a97-d344-40bb-84f3-765223f2cc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084200665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2084200665
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.1119614820
Short name T58
Test name
Test status
Simulation time 54502864 ps
CPU time 1.19 seconds
Started Jul 14 07:00:04 PM PDT 24
Finished Jul 14 07:00:13 PM PDT 24
Peak memory 218840 kb
Host smart-78d2851b-e7f9-480e-9ec4-491d02161f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119614820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.1119614820
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.380645384
Short name T957
Test name
Test status
Simulation time 56341912 ps
CPU time 1.41 seconds
Started Jul 14 06:59:55 PM PDT 24
Finished Jul 14 07:00:04 PM PDT 24
Peak memory 217644 kb
Host smart-9053d508-175e-4f14-a60b-d5e521fee437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380645384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.380645384
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.2242573912
Short name T560
Test name
Test status
Simulation time 74606947 ps
CPU time 1.57 seconds
Started Jul 14 06:59:51 PM PDT 24
Finished Jul 14 06:59:55 PM PDT 24
Peak memory 220284 kb
Host smart-45ca7d31-2220-49c7-a5da-5e22d221634e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242573912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2242573912
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.2777925792
Short name T427
Test name
Test status
Simulation time 115409030 ps
CPU time 2.58 seconds
Started Jul 14 06:59:52 PM PDT 24
Finished Jul 14 06:59:57 PM PDT 24
Peak memory 220564 kb
Host smart-e83ee2a3-d1f7-4d68-824e-e94f010e55a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777925792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2777925792
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.1138858802
Short name T388
Test name
Test status
Simulation time 54399467 ps
CPU time 1.26 seconds
Started Jul 14 07:00:15 PM PDT 24
Finished Jul 14 07:00:21 PM PDT 24
Peak memory 217932 kb
Host smart-1aaad979-bcb7-4c3c-b647-c4e71c04f572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138858802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.1138858802
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.727619211
Short name T971
Test name
Test status
Simulation time 67832733 ps
CPU time 1.24 seconds
Started Jul 14 07:00:13 PM PDT 24
Finished Jul 14 07:00:19 PM PDT 24
Peak memory 219112 kb
Host smart-25ec3e86-a42a-41e2-b7c8-64ff6a170d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727619211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.727619211
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.3072090852
Short name T850
Test name
Test status
Simulation time 61639886 ps
CPU time 1.74 seconds
Started Jul 14 06:59:55 PM PDT 24
Finished Jul 14 07:00:03 PM PDT 24
Peak memory 218856 kb
Host smart-c4426a3f-ce04-49b5-a870-9a582fee7642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072090852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.3072090852
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.259232495
Short name T568
Test name
Test status
Simulation time 269958953 ps
CPU time 1.18 seconds
Started Jul 14 06:59:56 PM PDT 24
Finished Jul 14 07:00:03 PM PDT 24
Peak memory 217672 kb
Host smart-b4a9d29c-7e38-462e-b047-52f0e9e2b7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259232495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.259232495
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.2917154926
Short name T301
Test name
Test status
Simulation time 46460122 ps
CPU time 1.23 seconds
Started Jul 14 06:58:57 PM PDT 24
Finished Jul 14 06:59:00 PM PDT 24
Peak memory 219452 kb
Host smart-6c8903d2-367f-4bdb-a796-aabe67c54b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917154926 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.2917154926
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.3155894832
Short name T484
Test name
Test status
Simulation time 25015202 ps
CPU time 0.91 seconds
Started Jul 14 06:58:15 PM PDT 24
Finished Jul 14 06:58:23 PM PDT 24
Peak memory 206996 kb
Host smart-69bb6577-6f07-4647-97af-abc04644ec3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155894832 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.3155894832
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.3223022825
Short name T188
Test name
Test status
Simulation time 42902110 ps
CPU time 0.85 seconds
Started Jul 14 06:58:23 PM PDT 24
Finished Jul 14 06:58:27 PM PDT 24
Peak memory 216496 kb
Host smart-6c96e577-eafa-46b5-9937-07f7179ade01
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223022825 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.3223022825
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_err.2487170933
Short name T167
Test name
Test status
Simulation time 311988618 ps
CPU time 1.11 seconds
Started Jul 14 06:58:17 PM PDT 24
Finished Jul 14 06:58:25 PM PDT 24
Peak memory 225896 kb
Host smart-3355c680-b4da-4211-84a7-6f36a1d3925a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487170933 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.2487170933
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.540226746
Short name T801
Test name
Test status
Simulation time 37456597 ps
CPU time 1.18 seconds
Started Jul 14 06:58:33 PM PDT 24
Finished Jul 14 06:58:37 PM PDT 24
Peak memory 220256 kb
Host smart-979b823f-2e20-4a60-b578-ea43907755be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540226746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.540226746
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.2912467999
Short name T786
Test name
Test status
Simulation time 23452758 ps
CPU time 1.09 seconds
Started Jul 14 06:58:11 PM PDT 24
Finished Jul 14 06:58:20 PM PDT 24
Peak memory 215684 kb
Host smart-ac6c33db-7b2f-45e6-94fb-26e079251fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912467999 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.2912467999
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.331925179
Short name T771
Test name
Test status
Simulation time 43396757 ps
CPU time 0.88 seconds
Started Jul 14 06:58:33 PM PDT 24
Finished Jul 14 06:58:36 PM PDT 24
Peak memory 215632 kb
Host smart-64140bfc-d76f-4e38-93e2-b9870cfcc590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331925179 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.331925179
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.15797972
Short name T322
Test name
Test status
Simulation time 154494877 ps
CPU time 3.52 seconds
Started Jul 14 06:58:11 PM PDT 24
Finished Jul 14 06:58:22 PM PDT 24
Peak memory 217712 kb
Host smart-a2ad26b6-0d60-4574-9b3a-784419b88c4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15797972 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.15797972
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.2260065979
Short name T223
Test name
Test status
Simulation time 113208900508 ps
CPU time 754.64 seconds
Started Jul 14 06:58:35 PM PDT 24
Finished Jul 14 07:11:12 PM PDT 24
Peak memory 221648 kb
Host smart-a6292eb5-3c5d-420e-a96e-d26d5b14fbd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260065979 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.2260065979
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.3296787785
Short name T43
Test name
Test status
Simulation time 47649777 ps
CPU time 1.19 seconds
Started Jul 14 06:59:59 PM PDT 24
Finished Jul 14 07:00:09 PM PDT 24
Peak memory 220056 kb
Host smart-62b68630-e750-4aec-88ff-ccd61ea3da15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296787785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.3296787785
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.779967822
Short name T552
Test name
Test status
Simulation time 37532044 ps
CPU time 1.13 seconds
Started Jul 14 07:00:14 PM PDT 24
Finished Jul 14 07:00:20 PM PDT 24
Peak memory 215608 kb
Host smart-2488910c-3e38-4112-b57b-e8b26eb369e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779967822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.779967822
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.4231795779
Short name T435
Test name
Test status
Simulation time 63330410 ps
CPU time 1.12 seconds
Started Jul 14 06:59:54 PM PDT 24
Finished Jul 14 07:00:02 PM PDT 24
Peak memory 217516 kb
Host smart-7a323e79-50ad-4cf3-aa14-d7a41c6acf38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231795779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.4231795779
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.752116225
Short name T682
Test name
Test status
Simulation time 86806431 ps
CPU time 1.1 seconds
Started Jul 14 06:59:54 PM PDT 24
Finished Jul 14 07:00:02 PM PDT 24
Peak memory 217580 kb
Host smart-64e154de-82fc-4d82-b342-c95e4ea13eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752116225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.752116225
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.3683626320
Short name T687
Test name
Test status
Simulation time 60171729 ps
CPU time 1.02 seconds
Started Jul 14 07:00:11 PM PDT 24
Finished Jul 14 07:00:17 PM PDT 24
Peak memory 217736 kb
Host smart-f8bbce39-36c1-4f2e-afd6-06b90a5d7e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683626320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.3683626320
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.2470189917
Short name T64
Test name
Test status
Simulation time 45576037 ps
CPU time 1.96 seconds
Started Jul 14 07:00:12 PM PDT 24
Finished Jul 14 07:00:19 PM PDT 24
Peak memory 218924 kb
Host smart-81583fc5-740b-43ab-b2db-9949c3704525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470189917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.2470189917
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.2226440314
Short name T344
Test name
Test status
Simulation time 42805664 ps
CPU time 1.51 seconds
Started Jul 14 07:00:12 PM PDT 24
Finished Jul 14 07:00:23 PM PDT 24
Peak memory 217436 kb
Host smart-a584aae6-e197-472a-b88f-c03f2024c673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226440314 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.2226440314
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.2509655624
Short name T826
Test name
Test status
Simulation time 41114273 ps
CPU time 1.46 seconds
Started Jul 14 06:59:54 PM PDT 24
Finished Jul 14 07:00:00 PM PDT 24
Peak memory 218848 kb
Host smart-6c5cda50-a00a-4942-9436-53b862131ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509655624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.2509655624
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.465508571
Short name T706
Test name
Test status
Simulation time 63116930 ps
CPU time 1.44 seconds
Started Jul 14 07:00:10 PM PDT 24
Finished Jul 14 07:00:17 PM PDT 24
Peak memory 220072 kb
Host smart-1bd339ce-faab-44b0-86a1-76a6fe22f8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465508571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.465508571
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1517963796
Short name T42
Test name
Test status
Simulation time 49139231 ps
CPU time 1.4 seconds
Started Jul 14 07:00:18 PM PDT 24
Finished Jul 14 07:00:25 PM PDT 24
Peak memory 217600 kb
Host smart-de65569e-1f30-4e28-9433-376cacefb3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517963796 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1517963796
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.3054141948
Short name T588
Test name
Test status
Simulation time 41134751 ps
CPU time 1.15 seconds
Started Jul 14 06:58:29 PM PDT 24
Finished Jul 14 06:58:31 PM PDT 24
Peak memory 220156 kb
Host smart-d80762a1-d9a3-47aa-8216-22691e0f0972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054141948 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.3054141948
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.2157963035
Short name T948
Test name
Test status
Simulation time 14475621 ps
CPU time 0.9 seconds
Started Jul 14 06:58:46 PM PDT 24
Finished Jul 14 06:58:49 PM PDT 24
Peak memory 207044 kb
Host smart-fb9e771e-155b-452d-899a-6301b4519d66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157963035 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2157963035
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.2199052820
Short name T205
Test name
Test status
Simulation time 19261684 ps
CPU time 0.86 seconds
Started Jul 14 06:58:16 PM PDT 24
Finished Jul 14 06:58:24 PM PDT 24
Peak memory 216500 kb
Host smart-4c58c498-d11a-4621-bb2a-0c1d4429a9c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199052820 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2199052820
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.1308809741
Short name T741
Test name
Test status
Simulation time 48649902 ps
CPU time 1.11 seconds
Started Jul 14 06:58:17 PM PDT 24
Finished Jul 14 06:58:25 PM PDT 24
Peak memory 218800 kb
Host smart-56e76a29-0ef7-4463-8958-7788b8745670
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308809741 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.1308809741
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.2033221609
Short name T831
Test name
Test status
Simulation time 49847897 ps
CPU time 1 seconds
Started Jul 14 06:58:17 PM PDT 24
Finished Jul 14 06:58:24 PM PDT 24
Peak memory 220888 kb
Host smart-4d533b1a-40a2-466c-9971-680ddfe23b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033221609 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.2033221609
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.1507223778
Short name T947
Test name
Test status
Simulation time 57985306 ps
CPU time 1.08 seconds
Started Jul 14 06:58:36 PM PDT 24
Finished Jul 14 06:58:38 PM PDT 24
Peak memory 219200 kb
Host smart-e366cb88-aeb1-42f1-93da-64b862400356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507223778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1507223778
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.2972882847
Short name T888
Test name
Test status
Simulation time 32743263 ps
CPU time 0.83 seconds
Started Jul 14 06:58:31 PM PDT 24
Finished Jul 14 06:58:43 PM PDT 24
Peak memory 215516 kb
Host smart-cb8061fb-bb59-437f-a01b-d6f7280343c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972882847 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2972882847
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.2325463946
Short name T827
Test name
Test status
Simulation time 36758062 ps
CPU time 0.89 seconds
Started Jul 14 06:58:33 PM PDT 24
Finished Jul 14 06:58:36 PM PDT 24
Peak memory 215600 kb
Host smart-b2f7897c-db3d-4525-9ca0-bfcd105185e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325463946 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.2325463946
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2081543475
Short name T428
Test name
Test status
Simulation time 43771544 ps
CPU time 1.11 seconds
Started Jul 14 06:58:38 PM PDT 24
Finished Jul 14 06:58:40 PM PDT 24
Peak memory 207468 kb
Host smart-a96f32a3-c0bb-4443-8b51-a2451bdfd2d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081543475 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2081543475
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.1460961202
Short name T673
Test name
Test status
Simulation time 30346093978 ps
CPU time 691.09 seconds
Started Jul 14 06:59:05 PM PDT 24
Finished Jul 14 07:10:41 PM PDT 24
Peak memory 218108 kb
Host smart-794c484d-3799-4c0e-b8a8-57521fbdb737
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460961202 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.1460961202
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.50547611
Short name T842
Test name
Test status
Simulation time 61465323 ps
CPU time 1.49 seconds
Started Jul 14 07:00:02 PM PDT 24
Finished Jul 14 07:00:12 PM PDT 24
Peak memory 218768 kb
Host smart-28acb86d-69ed-4e15-bc93-9923843ec8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50547611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.50547611
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2303768299
Short name T508
Test name
Test status
Simulation time 76997580 ps
CPU time 1.15 seconds
Started Jul 14 06:59:54 PM PDT 24
Finished Jul 14 07:00:00 PM PDT 24
Peak memory 218944 kb
Host smart-b3d81cd8-fada-46ee-ad4b-50276d2787d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303768299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2303768299
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.4095483570
Short name T988
Test name
Test status
Simulation time 101753614 ps
CPU time 1.6 seconds
Started Jul 14 06:59:54 PM PDT 24
Finished Jul 14 07:00:00 PM PDT 24
Peak memory 219236 kb
Host smart-e640c39e-bfa4-4917-a81a-8550c0a1049d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095483570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.4095483570
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.3141451837
Short name T670
Test name
Test status
Simulation time 151141796 ps
CPU time 1.71 seconds
Started Jul 14 06:59:58 PM PDT 24
Finished Jul 14 07:00:07 PM PDT 24
Peak memory 219024 kb
Host smart-5b240bd5-005a-4117-8fcb-b973402e6257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141451837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.3141451837
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.2392960552
Short name T251
Test name
Test status
Simulation time 32995583 ps
CPU time 1.38 seconds
Started Jul 14 07:00:09 PM PDT 24
Finished Jul 14 07:00:17 PM PDT 24
Peak memory 218852 kb
Host smart-cb069105-fe7e-471e-977c-56a7f74d3bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392960552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2392960552
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.3273921387
Short name T804
Test name
Test status
Simulation time 98346554 ps
CPU time 1.18 seconds
Started Jul 14 06:59:56 PM PDT 24
Finished Jul 14 07:00:04 PM PDT 24
Peak memory 217808 kb
Host smart-38f8107a-e25b-4bfc-b080-5f134f291713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273921387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.3273921387
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.1404336859
Short name T382
Test name
Test status
Simulation time 28498711 ps
CPU time 1.37 seconds
Started Jul 14 07:00:06 PM PDT 24
Finished Jul 14 07:00:15 PM PDT 24
Peak memory 218820 kb
Host smart-df08f129-b125-4859-b13d-de88debeb28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404336859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1404336859
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.979985628
Short name T429
Test name
Test status
Simulation time 40446242 ps
CPU time 1.51 seconds
Started Jul 14 07:00:18 PM PDT 24
Finished Jul 14 07:00:24 PM PDT 24
Peak memory 218988 kb
Host smart-eb4a83d2-c5f6-4db4-af9b-aaa5b9904f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979985628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.979985628
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.2914272089
Short name T993
Test name
Test status
Simulation time 51530660 ps
CPU time 1.24 seconds
Started Jul 14 06:59:53 PM PDT 24
Finished Jul 14 06:59:59 PM PDT 24
Peak memory 219060 kb
Host smart-a1c1c8c7-b107-4d09-a88a-7b41edc81f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914272089 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.2914272089
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.81526942
Short name T941
Test name
Test status
Simulation time 77108680 ps
CPU time 1.08 seconds
Started Jul 14 06:58:40 PM PDT 24
Finished Jul 14 06:58:42 PM PDT 24
Peak memory 219868 kb
Host smart-fa610989-183e-41d6-815c-b891563b4777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81526942 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.81526942
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.48721114
Short name T719
Test name
Test status
Simulation time 32572669 ps
CPU time 1.02 seconds
Started Jul 14 06:58:59 PM PDT 24
Finished Jul 14 06:59:04 PM PDT 24
Peak memory 215220 kb
Host smart-ff84b6e6-fafb-467f-9840-9fbe1e226e35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48721114 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.48721114
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.2556734685
Short name T899
Test name
Test status
Simulation time 12615993 ps
CPU time 0.88 seconds
Started Jul 14 06:58:15 PM PDT 24
Finished Jul 14 06:58:23 PM PDT 24
Peak memory 216664 kb
Host smart-b6a43a10-c4dc-415f-b673-9039815a51e5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556734685 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.2556734685
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.4227919817
Short name T823
Test name
Test status
Simulation time 118437788 ps
CPU time 1.2 seconds
Started Jul 14 06:58:33 PM PDT 24
Finished Jul 14 06:58:37 PM PDT 24
Peak memory 217244 kb
Host smart-f93bade8-9f37-4330-8892-68d1919dadcc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227919817 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.4227919817
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.200726762
Short name T150
Test name
Test status
Simulation time 86545537 ps
CPU time 0.99 seconds
Started Jul 14 06:58:15 PM PDT 24
Finished Jul 14 06:58:23 PM PDT 24
Peak memory 229880 kb
Host smart-c21ad212-b1aa-4eb7-be39-52e756627e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200726762 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.200726762
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.180834443
Short name T671
Test name
Test status
Simulation time 48963900 ps
CPU time 1.59 seconds
Started Jul 14 06:58:15 PM PDT 24
Finished Jul 14 06:58:27 PM PDT 24
Peak memory 217736 kb
Host smart-f0d88703-5624-41d1-acda-d786c862a7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180834443 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.180834443
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.1268665962
Short name T32
Test name
Test status
Simulation time 24219944 ps
CPU time 0.95 seconds
Started Jul 14 06:58:33 PM PDT 24
Finished Jul 14 06:58:36 PM PDT 24
Peak memory 216252 kb
Host smart-bc084ef4-28c8-4129-8641-4010175ce22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268665962 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.1268665962
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.1382185946
Short name T350
Test name
Test status
Simulation time 33305454 ps
CPU time 0.91 seconds
Started Jul 14 06:58:32 PM PDT 24
Finished Jul 14 06:58:35 PM PDT 24
Peak memory 215600 kb
Host smart-813b18c0-9246-4f5a-8735-3512ccb69ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382185946 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.1382185946
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.2851539741
Short name T869
Test name
Test status
Simulation time 771525927 ps
CPU time 4.06 seconds
Started Jul 14 06:59:10 PM PDT 24
Finished Jul 14 06:59:20 PM PDT 24
Peak memory 217804 kb
Host smart-bf0d53a1-0d9f-4792-88a2-b68a60d14d21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851539741 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.2851539741
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1235196113
Short name T968
Test name
Test status
Simulation time 42994230400 ps
CPU time 934.63 seconds
Started Jul 14 06:58:17 PM PDT 24
Finished Jul 14 07:14:00 PM PDT 24
Peak memory 219728 kb
Host smart-d90fd48b-15b1-463b-9eab-89b44a7b60eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235196113 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1235196113
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.607990850
Short name T746
Test name
Test status
Simulation time 50213638 ps
CPU time 1.18 seconds
Started Jul 14 07:00:13 PM PDT 24
Finished Jul 14 07:00:19 PM PDT 24
Peak memory 219012 kb
Host smart-15f20e28-381e-4b39-a1fa-fb90ff2dd408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607990850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.607990850
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.3925230289
Short name T754
Test name
Test status
Simulation time 38372931 ps
CPU time 1.2 seconds
Started Jul 14 07:00:19 PM PDT 24
Finished Jul 14 07:00:26 PM PDT 24
Peak memory 219052 kb
Host smart-6f8c2b32-048d-4221-a50e-738e96753613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925230289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3925230289
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.454557621
Short name T46
Test name
Test status
Simulation time 209354143 ps
CPU time 1.44 seconds
Started Jul 14 07:00:18 PM PDT 24
Finished Jul 14 07:00:25 PM PDT 24
Peak memory 219592 kb
Host smart-7dd738ac-6f19-49d9-bdb9-e2da654ceecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454557621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.454557621
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.2913482559
Short name T582
Test name
Test status
Simulation time 87249032 ps
CPU time 1.33 seconds
Started Jul 14 06:59:57 PM PDT 24
Finished Jul 14 07:00:05 PM PDT 24
Peak memory 219236 kb
Host smart-00670d05-d7f8-40f3-b96a-914e41a74e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913482559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.2913482559
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.1860325916
Short name T379
Test name
Test status
Simulation time 56457757 ps
CPU time 1.48 seconds
Started Jul 14 06:59:53 PM PDT 24
Finished Jul 14 06:59:57 PM PDT 24
Peak memory 218620 kb
Host smart-853e4cf0-f59d-4313-a5be-7eb64bbdac1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860325916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.1860325916
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.2254909021
Short name T916
Test name
Test status
Simulation time 40827539 ps
CPU time 1.51 seconds
Started Jul 14 07:00:00 PM PDT 24
Finished Jul 14 07:00:10 PM PDT 24
Peak memory 220220 kb
Host smart-10ee17f3-882c-491b-ad90-d86434192231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254909021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2254909021
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.3611987662
Short name T315
Test name
Test status
Simulation time 38065542 ps
CPU time 1.71 seconds
Started Jul 14 06:59:51 PM PDT 24
Finished Jul 14 06:59:55 PM PDT 24
Peak memory 218832 kb
Host smart-460ceb9a-3f89-49bf-89a7-1f81c2d6e149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611987662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.3611987662
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1774433293
Short name T389
Test name
Test status
Simulation time 144180064 ps
CPU time 2.1 seconds
Started Jul 14 07:00:18 PM PDT 24
Finished Jul 14 07:00:24 PM PDT 24
Peak memory 220472 kb
Host smart-931f314b-83ff-487c-bd45-ab4f8741f757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774433293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1774433293
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.2247601733
Short name T372
Test name
Test status
Simulation time 45547523 ps
CPU time 1.19 seconds
Started Jul 14 06:59:53 PM PDT 24
Finished Jul 14 06:59:59 PM PDT 24
Peak memory 218860 kb
Host smart-c600785c-ac0c-45d1-8663-155de33b37e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247601733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.2247601733
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.3408177920
Short name T856
Test name
Test status
Simulation time 203288742 ps
CPU time 1.14 seconds
Started Jul 14 06:58:16 PM PDT 24
Finished Jul 14 06:58:23 PM PDT 24
Peak memory 221624 kb
Host smart-1ba81521-884c-47c9-9727-01947ff62229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408177920 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.3408177920
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.528539521
Short name T737
Test name
Test status
Simulation time 18103348 ps
CPU time 1 seconds
Started Jul 14 06:58:18 PM PDT 24
Finished Jul 14 06:58:25 PM PDT 24
Peak memory 207040 kb
Host smart-dcc435e9-9a18-4403-834b-dc9a17b6976c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528539521 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.528539521
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.1500481291
Short name T202
Test name
Test status
Simulation time 100251636 ps
CPU time 1.16 seconds
Started Jul 14 06:58:16 PM PDT 24
Finished Jul 14 06:58:24 PM PDT 24
Peak memory 217332 kb
Host smart-7f718d2e-beb9-4db9-9040-602fed8145cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500481291 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.1500481291
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.2610400727
Short name T789
Test name
Test status
Simulation time 29916588 ps
CPU time 0.96 seconds
Started Jul 14 06:58:42 PM PDT 24
Finished Jul 14 06:58:45 PM PDT 24
Peak memory 229632 kb
Host smart-0bc76cc5-2a39-44a4-a79e-c1a8ba41489a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610400727 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2610400727
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.3182447935
Short name T358
Test name
Test status
Simulation time 33828847 ps
CPU time 1.27 seconds
Started Jul 14 06:58:15 PM PDT 24
Finished Jul 14 06:58:23 PM PDT 24
Peak memory 217748 kb
Host smart-a2e0288a-3020-4783-a3c4-9e544e4b1789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182447935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.3182447935
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.544146139
Short name T851
Test name
Test status
Simulation time 22077505 ps
CPU time 1.08 seconds
Started Jul 14 06:58:26 PM PDT 24
Finished Jul 14 06:58:29 PM PDT 24
Peak memory 215812 kb
Host smart-9f48c935-b531-413b-b618-16f6f0eacd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544146139 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.544146139
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.2657443584
Short name T723
Test name
Test status
Simulation time 50279270 ps
CPU time 0.84 seconds
Started Jul 14 06:58:15 PM PDT 24
Finished Jul 14 06:58:23 PM PDT 24
Peak memory 215488 kb
Host smart-af23fb68-f1d3-4326-9873-c75651cefdad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657443584 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.2657443584
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.1870136531
Short name T485
Test name
Test status
Simulation time 165481304 ps
CPU time 2.21 seconds
Started Jul 14 06:58:19 PM PDT 24
Finished Jul 14 06:58:27 PM PDT 24
Peak memory 217532 kb
Host smart-18f89efc-b2f5-445c-90ce-033758171f31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870136531 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1870136531
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.408068861
Short name T953
Test name
Test status
Simulation time 12954646690 ps
CPU time 321.7 seconds
Started Jul 14 06:58:52 PM PDT 24
Finished Jul 14 07:04:17 PM PDT 24
Peak memory 218704 kb
Host smart-ab35ab56-b0a3-42ec-af2e-5a18afeecbc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408068861 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.408068861
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.2367331697
Short name T956
Test name
Test status
Simulation time 35228821 ps
CPU time 1.42 seconds
Started Jul 14 06:59:53 PM PDT 24
Finished Jul 14 06:59:59 PM PDT 24
Peak memory 218748 kb
Host smart-3205a0e2-5f3c-4a45-80f0-3981788762b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367331697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2367331697
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.1517072012
Short name T440
Test name
Test status
Simulation time 171987797 ps
CPU time 2.29 seconds
Started Jul 14 07:00:17 PM PDT 24
Finished Jul 14 07:00:24 PM PDT 24
Peak memory 220608 kb
Host smart-81461f9e-c404-4007-aacb-225c83f75864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517072012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.1517072012
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1123398093
Short name T855
Test name
Test status
Simulation time 32868814 ps
CPU time 1.38 seconds
Started Jul 14 07:00:12 PM PDT 24
Finished Jul 14 07:00:19 PM PDT 24
Peak memory 220252 kb
Host smart-5ea82a21-7083-40d8-9f4d-9bda48c09415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123398093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1123398093
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.1177510526
Short name T521
Test name
Test status
Simulation time 72884493 ps
CPU time 2 seconds
Started Jul 14 07:00:02 PM PDT 24
Finished Jul 14 07:00:12 PM PDT 24
Peak memory 218980 kb
Host smart-378d8ed4-7e99-4c5d-86e7-6dbd12ac44de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177510526 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.1177510526
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.1636000713
Short name T586
Test name
Test status
Simulation time 75804000 ps
CPU time 1.18 seconds
Started Jul 14 07:00:17 PM PDT 24
Finished Jul 14 07:00:22 PM PDT 24
Peak memory 218840 kb
Host smart-9523aa73-61d3-433c-99f1-83b1cbcf0c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636000713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.1636000713
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2974739650
Short name T373
Test name
Test status
Simulation time 32094363 ps
CPU time 1.32 seconds
Started Jul 14 07:00:03 PM PDT 24
Finished Jul 14 07:00:12 PM PDT 24
Peak memory 218884 kb
Host smart-e37bfd0d-6d59-4ef7-a2a7-3b03907ef568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974739650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2974739650
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.1999644243
Short name T966
Test name
Test status
Simulation time 84431557 ps
CPU time 1.18 seconds
Started Jul 14 06:59:58 PM PDT 24
Finished Jul 14 07:00:07 PM PDT 24
Peak memory 220496 kb
Host smart-60f502a4-791c-4856-bad4-82b7b913026c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999644243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.1999644243
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.584415343
Short name T498
Test name
Test status
Simulation time 60736710 ps
CPU time 1.56 seconds
Started Jul 14 07:00:02 PM PDT 24
Finished Jul 14 07:00:12 PM PDT 24
Peak memory 218816 kb
Host smart-1415bdf2-c3ba-4cd6-9221-43230feaca58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584415343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.584415343
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.2236900718
Short name T400
Test name
Test status
Simulation time 80008611 ps
CPU time 1.13 seconds
Started Jul 14 07:00:05 PM PDT 24
Finished Jul 14 07:00:14 PM PDT 24
Peak memory 215580 kb
Host smart-4e538075-9b1b-4def-965d-de0549713f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236900718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.2236900718
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.1978204825
Short name T602
Test name
Test status
Simulation time 57092901 ps
CPU time 1.33 seconds
Started Jul 14 07:00:11 PM PDT 24
Finished Jul 14 07:00:18 PM PDT 24
Peak memory 220188 kb
Host smart-250bca2f-f149-4c03-b62b-4ccbbf8683c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978204825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.1978204825
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.1773231793
Short name T972
Test name
Test status
Simulation time 41823733 ps
CPU time 1.2 seconds
Started Jul 14 06:58:25 PM PDT 24
Finished Jul 14 06:58:28 PM PDT 24
Peak memory 220944 kb
Host smart-931a9ed8-e00d-4474-9545-f08f4999af6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773231793 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.1773231793
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.2662798405
Short name T68
Test name
Test status
Simulation time 15221253 ps
CPU time 0.91 seconds
Started Jul 14 06:58:34 PM PDT 24
Finished Jul 14 06:58:37 PM PDT 24
Peak memory 206972 kb
Host smart-6a2abd68-2e92-4b1a-9d90-a568e1065725
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662798405 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2662798405
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.1875794730
Short name T173
Test name
Test status
Simulation time 17851127 ps
CPU time 0.88 seconds
Started Jul 14 06:58:45 PM PDT 24
Finished Jul 14 06:58:48 PM PDT 24
Peak memory 216728 kb
Host smart-363d36a7-e3db-4c34-8e33-f3a9ecde55b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875794730 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1875794730
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.1571005895
Short name T513
Test name
Test status
Simulation time 34762651 ps
CPU time 1.1 seconds
Started Jul 14 06:58:30 PM PDT 24
Finished Jul 14 06:58:32 PM PDT 24
Peak memory 217184 kb
Host smart-11b80e3c-cd8c-41e2-92f3-b4ca25ee557b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571005895 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.1571005895
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.2488649146
Short name T49
Test name
Test status
Simulation time 39953811 ps
CPU time 0.94 seconds
Started Jul 14 06:58:18 PM PDT 24
Finished Jul 14 06:58:25 PM PDT 24
Peak memory 224020 kb
Host smart-35c05e4d-3728-4e12-a0b4-fd3246b843f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488649146 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2488649146
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.1348067869
Short name T481
Test name
Test status
Simulation time 27869970 ps
CPU time 1.31 seconds
Started Jul 14 06:58:46 PM PDT 24
Finished Jul 14 06:58:49 PM PDT 24
Peak memory 218644 kb
Host smart-94464f0b-c681-4cc0-a613-3faf011ae835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348067869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.1348067869
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.3674108319
Short name T466
Test name
Test status
Simulation time 21704091 ps
CPU time 1.08 seconds
Started Jul 14 06:58:42 PM PDT 24
Finished Jul 14 06:58:44 PM PDT 24
Peak memory 215752 kb
Host smart-fe9ff64c-7d64-454d-8402-01128513a9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674108319 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.3674108319
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.3955862691
Short name T740
Test name
Test status
Simulation time 16854248 ps
CPU time 1.04 seconds
Started Jul 14 06:58:16 PM PDT 24
Finished Jul 14 06:58:24 PM PDT 24
Peak memory 215624 kb
Host smart-b4cceb20-465f-4bf5-8f8a-d732337027f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955862691 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.3955862691
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.4245244297
Short name T879
Test name
Test status
Simulation time 54122046 ps
CPU time 1.12 seconds
Started Jul 14 06:58:38 PM PDT 24
Finished Jul 14 06:58:41 PM PDT 24
Peak memory 219776 kb
Host smart-3c04e2e7-a607-4caa-9110-dc4f3411fd89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245244297 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.4245244297
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.3601014295
Short name T449
Test name
Test status
Simulation time 54050613484 ps
CPU time 1342.03 seconds
Started Jul 14 06:58:49 PM PDT 24
Finished Jul 14 07:21:14 PM PDT 24
Peak memory 224360 kb
Host smart-f808e55d-1eb2-4908-99a4-467cd2b032aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601014295 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.3601014295
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.218021954
Short name T420
Test name
Test status
Simulation time 65511699 ps
CPU time 2.2 seconds
Started Jul 14 06:59:55 PM PDT 24
Finished Jul 14 07:00:04 PM PDT 24
Peak memory 215576 kb
Host smart-fcda7a67-04cd-4aa1-955e-f3352bb47306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218021954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.218021954
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.1081271482
Short name T872
Test name
Test status
Simulation time 60220290 ps
CPU time 1.58 seconds
Started Jul 14 07:00:07 PM PDT 24
Finished Jul 14 07:00:15 PM PDT 24
Peak memory 217708 kb
Host smart-86cda563-e316-4eab-bf8d-95c3a9da89cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081271482 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.1081271482
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.1443957784
Short name T434
Test name
Test status
Simulation time 28041583 ps
CPU time 0.98 seconds
Started Jul 14 06:59:57 PM PDT 24
Finished Jul 14 07:00:05 PM PDT 24
Peak memory 218924 kb
Host smart-7dc381b6-d13f-40df-9837-61bd36e437b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443957784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.1443957784
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.1026201705
Short name T101
Test name
Test status
Simulation time 70203231 ps
CPU time 2.53 seconds
Started Jul 14 07:00:07 PM PDT 24
Finished Jul 14 07:00:17 PM PDT 24
Peak memory 220164 kb
Host smart-5597950f-3015-4978-b2d2-7061332ecb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026201705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.1026201705
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.1250557561
Short name T922
Test name
Test status
Simulation time 66414016 ps
CPU time 2.28 seconds
Started Jul 14 06:59:53 PM PDT 24
Finished Jul 14 07:00:00 PM PDT 24
Peak memory 220316 kb
Host smart-0aae42a7-6c17-434b-ab9c-9ec3fb1d6912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250557561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.1250557561
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.3453104395
Short name T644
Test name
Test status
Simulation time 55514537 ps
CPU time 1.1 seconds
Started Jul 14 06:59:55 PM PDT 24
Finished Jul 14 07:00:02 PM PDT 24
Peak memory 219052 kb
Host smart-4c8c7b31-91bc-4755-8749-deb70893abbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453104395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3453104395
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.2138695410
Short name T550
Test name
Test status
Simulation time 48038300 ps
CPU time 1.71 seconds
Started Jul 14 06:59:55 PM PDT 24
Finished Jul 14 07:00:03 PM PDT 24
Peak memory 218936 kb
Host smart-909ef89d-d144-4977-a816-ce0848d4bb2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138695410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2138695410
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.1044210783
Short name T359
Test name
Test status
Simulation time 54094474 ps
CPU time 0.94 seconds
Started Jul 14 07:00:12 PM PDT 24
Finished Jul 14 07:00:18 PM PDT 24
Peak memory 217428 kb
Host smart-524963dc-01db-4e8c-8fad-f8f98480b4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044210783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.1044210783
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.4134462077
Short name T661
Test name
Test status
Simulation time 44230391 ps
CPU time 1.5 seconds
Started Jul 14 07:00:18 PM PDT 24
Finished Jul 14 07:00:24 PM PDT 24
Peak memory 218756 kb
Host smart-4910ca5d-df9f-4164-a3fb-a3df551e924c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134462077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.4134462077
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.3767477119
Short name T852
Test name
Test status
Simulation time 36753626 ps
CPU time 1.33 seconds
Started Jul 14 07:00:08 PM PDT 24
Finished Jul 14 07:00:16 PM PDT 24
Peak memory 217608 kb
Host smart-cdba5bba-b9de-41b1-ae98-e1278ff2b55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767477119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.3767477119
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.1389492333
Short name T124
Test name
Test status
Simulation time 100029656 ps
CPU time 1.2 seconds
Started Jul 14 06:58:40 PM PDT 24
Finished Jul 14 06:58:42 PM PDT 24
Peak memory 218860 kb
Host smart-2dce1742-7350-4915-8e51-2f528ceb63e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389492333 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1389492333
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.3185486000
Short name T352
Test name
Test status
Simulation time 35659181 ps
CPU time 0.97 seconds
Started Jul 14 06:58:34 PM PDT 24
Finished Jul 14 06:58:37 PM PDT 24
Peak memory 207044 kb
Host smart-ee920621-c6be-4c69-92ab-3bff281d4bf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185486000 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3185486000
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.1933072494
Short name T174
Test name
Test status
Simulation time 35345148 ps
CPU time 0.87 seconds
Started Jul 14 06:58:35 PM PDT 24
Finished Jul 14 06:58:38 PM PDT 24
Peak memory 216552 kb
Host smart-ff2f4023-a346-4525-98c4-74476a004b11
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933072494 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1933072494
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.222595518
Short name T848
Test name
Test status
Simulation time 33547185 ps
CPU time 1.17 seconds
Started Jul 14 06:58:39 PM PDT 24
Finished Jul 14 06:58:42 PM PDT 24
Peak memory 217068 kb
Host smart-19080c17-16e4-462d-8cd2-cb56d2aa9bdb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222595518 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_di
sable_auto_req_mode.222595518
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.655833286
Short name T753
Test name
Test status
Simulation time 30701539 ps
CPU time 0.89 seconds
Started Jul 14 06:58:44 PM PDT 24
Finished Jul 14 06:58:47 PM PDT 24
Peak memory 218680 kb
Host smart-08dfc8c3-cd7a-4f32-b671-467792d49a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655833286 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.655833286
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.3844895268
Short name T448
Test name
Test status
Simulation time 96148714 ps
CPU time 1.33 seconds
Started Jul 14 06:59:05 PM PDT 24
Finished Jul 14 06:59:12 PM PDT 24
Peak memory 219284 kb
Host smart-b196c7ed-2f2f-4bec-a696-d2ded0059f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844895268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3844895268
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.2816450721
Short name T624
Test name
Test status
Simulation time 24169631 ps
CPU time 1.09 seconds
Started Jul 14 06:58:43 PM PDT 24
Finished Jul 14 06:58:46 PM PDT 24
Peak memory 215684 kb
Host smart-b49e5cb6-688c-44b9-9a80-964c2ea4eac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816450721 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2816450721
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.1005690904
Short name T433
Test name
Test status
Simulation time 76954330 ps
CPU time 0.93 seconds
Started Jul 14 06:58:25 PM PDT 24
Finished Jul 14 06:58:27 PM PDT 24
Peak memory 207188 kb
Host smart-3ee663a7-e6f6-4ad8-ad86-79c6951cdb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005690904 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.1005690904
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.1610264433
Short name T627
Test name
Test status
Simulation time 343807895 ps
CPU time 6.82 seconds
Started Jul 14 06:58:43 PM PDT 24
Finished Jul 14 06:58:51 PM PDT 24
Peak memory 215580 kb
Host smart-2a25eed7-36eb-44e6-a376-6eb77f376d0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610264433 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1610264433
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.2604106629
Short name T865
Test name
Test status
Simulation time 127681142292 ps
CPU time 1486.38 seconds
Started Jul 14 06:58:49 PM PDT 24
Finished Jul 14 07:23:38 PM PDT 24
Peak memory 226432 kb
Host smart-6311f31c-15e4-48f4-8b81-ba824b78f846
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604106629 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.2604106629
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.3793077904
Short name T331
Test name
Test status
Simulation time 339775848 ps
CPU time 3.2 seconds
Started Jul 14 07:00:18 PM PDT 24
Finished Jul 14 07:00:25 PM PDT 24
Peak memory 220612 kb
Host smart-7a296e73-b475-4a6a-b7b3-7f93f4c37016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793077904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.3793077904
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.188481301
Short name T97
Test name
Test status
Simulation time 40099835 ps
CPU time 1.07 seconds
Started Jul 14 06:59:52 PM PDT 24
Finished Jul 14 06:59:55 PM PDT 24
Peak memory 217664 kb
Host smart-44426070-72f5-43da-a855-acb7067d267b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188481301 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.188481301
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.827760168
Short name T854
Test name
Test status
Simulation time 57689830 ps
CPU time 1.75 seconds
Started Jul 14 07:00:09 PM PDT 24
Finished Jul 14 07:00:17 PM PDT 24
Peak memory 217676 kb
Host smart-e0fa451c-2723-4abe-acf5-26534213472d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827760168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.827760168
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.1698572074
Short name T652
Test name
Test status
Simulation time 63078893 ps
CPU time 1.37 seconds
Started Jul 14 07:00:13 PM PDT 24
Finished Jul 14 07:00:24 PM PDT 24
Peak memory 218816 kb
Host smart-95e0c959-3df9-4a23-93f6-0eeed788ed2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698572074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.1698572074
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.366294953
Short name T569
Test name
Test status
Simulation time 42572333 ps
CPU time 1.13 seconds
Started Jul 14 06:59:55 PM PDT 24
Finished Jul 14 07:00:02 PM PDT 24
Peak memory 217696 kb
Host smart-3a55c4c4-8c91-4ac3-89ed-379c65943a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366294953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.366294953
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.4292529387
Short name T619
Test name
Test status
Simulation time 51765848 ps
CPU time 1.59 seconds
Started Jul 14 07:00:18 PM PDT 24
Finished Jul 14 07:00:24 PM PDT 24
Peak memory 218776 kb
Host smart-9a630b72-6654-47d1-89d6-7a204dbe45ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292529387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.4292529387
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3163446288
Short name T324
Test name
Test status
Simulation time 267185493 ps
CPU time 3.21 seconds
Started Jul 14 06:59:55 PM PDT 24
Finished Jul 14 07:00:04 PM PDT 24
Peak memory 220076 kb
Host smart-bc1c44e1-506c-447e-8df8-023313323095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163446288 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3163446288
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.4126433227
Short name T361
Test name
Test status
Simulation time 52732868 ps
CPU time 1.73 seconds
Started Jul 14 07:00:08 PM PDT 24
Finished Jul 14 07:00:16 PM PDT 24
Peak memory 218668 kb
Host smart-40440053-b5cd-47cf-a2ea-e3aff4b10ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126433227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.4126433227
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.89515731
Short name T796
Test name
Test status
Simulation time 35765200 ps
CPU time 1.19 seconds
Started Jul 14 06:59:55 PM PDT 24
Finished Jul 14 07:00:02 PM PDT 24
Peak memory 220176 kb
Host smart-4581728c-38c5-46bd-b1d1-795f0b661601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89515731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.89515731
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.1187504553
Short name T419
Test name
Test status
Simulation time 41653561 ps
CPU time 1.11 seconds
Started Jul 14 06:59:52 PM PDT 24
Finished Jul 14 06:59:57 PM PDT 24
Peak memory 217700 kb
Host smart-1c29b50c-4b61-4be9-937b-69de23eb1d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187504553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1187504553
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.3748167466
Short name T156
Test name
Test status
Simulation time 28051123 ps
CPU time 1.32 seconds
Started Jul 14 06:57:55 PM PDT 24
Finished Jul 14 06:57:57 PM PDT 24
Peak memory 219804 kb
Host smart-9a48ffac-3055-40fc-aacc-ab4aac699600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748167466 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.3748167466
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.2605032444
Short name T790
Test name
Test status
Simulation time 58593314 ps
CPU time 0.92 seconds
Started Jul 14 06:58:07 PM PDT 24
Finished Jul 14 06:58:13 PM PDT 24
Peak memory 215476 kb
Host smart-75a41986-dcf1-4bb5-9337-9fd64d0758e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605032444 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2605032444
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.2067428687
Short name T724
Test name
Test status
Simulation time 13934290 ps
CPU time 1.03 seconds
Started Jul 14 06:58:15 PM PDT 24
Finished Jul 14 06:58:23 PM PDT 24
Peak memory 216724 kb
Host smart-8f1b7ea9-d6e5-46b9-a7fa-c3b35533ed25
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067428687 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.2067428687
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.3835801538
Short name T773
Test name
Test status
Simulation time 195290056 ps
CPU time 1.03 seconds
Started Jul 14 06:57:56 PM PDT 24
Finished Jul 14 06:57:58 PM PDT 24
Peak memory 220036 kb
Host smart-ea08f3db-b096-4178-82dd-df330ac86735
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835801538 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.3835801538
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.20888941
Short name T184
Test name
Test status
Simulation time 32216213 ps
CPU time 0.95 seconds
Started Jul 14 06:58:08 PM PDT 24
Finished Jul 14 06:58:15 PM PDT 24
Peak memory 224068 kb
Host smart-f7c9fc05-8cd3-412f-ad85-4f72d18cb419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20888941 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.20888941
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.131308499
Short name T507
Test name
Test status
Simulation time 157580514 ps
CPU time 3.31 seconds
Started Jul 14 06:57:53 PM PDT 24
Finished Jul 14 06:57:57 PM PDT 24
Peak memory 220752 kb
Host smart-2aac4f12-c1a5-4905-b67f-6eba3e38e645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131308499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.131308499
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.4132568145
Short name T667
Test name
Test status
Simulation time 42590119 ps
CPU time 0.9 seconds
Started Jul 14 06:58:14 PM PDT 24
Finished Jul 14 06:58:22 PM PDT 24
Peak memory 215532 kb
Host smart-a6d60c78-3c1f-4b42-a2bb-c983585b7b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132568145 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.4132568145
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.4288730691
Short name T25
Test name
Test status
Simulation time 30774700 ps
CPU time 0.95 seconds
Started Jul 14 06:58:15 PM PDT 24
Finished Jul 14 06:58:23 PM PDT 24
Peak memory 207356 kb
Host smart-05626034-735b-4b70-aaae-e5a5685f84f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288730691 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.4288730691
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.277054294
Short name T17
Test name
Test status
Simulation time 967063895 ps
CPU time 8.73 seconds
Started Jul 14 06:57:56 PM PDT 24
Finished Jul 14 06:58:06 PM PDT 24
Peak memory 237372 kb
Host smart-a956d0a3-07ae-4f0e-87a6-9a9caa8d3bf6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277054294 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.277054294
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.3395794211
Short name T749
Test name
Test status
Simulation time 46291758 ps
CPU time 0.89 seconds
Started Jul 14 06:58:09 PM PDT 24
Finished Jul 14 06:58:16 PM PDT 24
Peak memory 215612 kb
Host smart-6be4350d-193f-423d-94c5-8bad75fb3273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395794211 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3395794211
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.2320609142
Short name T48
Test name
Test status
Simulation time 196466310 ps
CPU time 1.69 seconds
Started Jul 14 06:58:11 PM PDT 24
Finished Jul 14 06:58:19 PM PDT 24
Peak memory 218716 kb
Host smart-e2ea7a2d-d1ea-4f9a-95ac-b68768b84968
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320609142 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2320609142
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2088286061
Short name T62
Test name
Test status
Simulation time 127015541407 ps
CPU time 1612.88 seconds
Started Jul 14 06:58:08 PM PDT 24
Finished Jul 14 07:25:08 PM PDT 24
Peak memory 227540 kb
Host smart-8e7b0e10-f975-4fee-8c2e-b6ad4f8fc66c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088286061 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.2088286061
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.1375086584
Short name T839
Test name
Test status
Simulation time 38194380 ps
CPU time 1.09 seconds
Started Jul 14 06:58:37 PM PDT 24
Finished Jul 14 06:58:39 PM PDT 24
Peak memory 219004 kb
Host smart-291a7ee6-111b-4d1b-8fb2-278ec536db79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375086584 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1375086584
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.1866539477
Short name T734
Test name
Test status
Simulation time 81542065 ps
CPU time 0.95 seconds
Started Jul 14 06:58:39 PM PDT 24
Finished Jul 14 06:58:41 PM PDT 24
Peak memory 215424 kb
Host smart-aafb0c79-40e8-48dc-8d47-edb1b3086b71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866539477 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.1866539477
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.3955302822
Short name T529
Test name
Test status
Simulation time 14096050 ps
CPU time 0.93 seconds
Started Jul 14 06:58:38 PM PDT 24
Finished Jul 14 06:58:40 PM PDT 24
Peak memory 216376 kb
Host smart-00d6e85c-09a9-402d-a0ae-ac199c8f8f85
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955302822 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.3955302822
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.2113922233
Short name T860
Test name
Test status
Simulation time 83365167 ps
CPU time 1.13 seconds
Started Jul 14 06:58:46 PM PDT 24
Finished Jul 14 06:58:49 PM PDT 24
Peak memory 219832 kb
Host smart-519c433e-731f-4d77-a2fc-704b9d33ac26
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113922233 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.2113922233
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.2873564035
Short name T718
Test name
Test status
Simulation time 18672894 ps
CPU time 1.05 seconds
Started Jul 14 06:58:47 PM PDT 24
Finished Jul 14 06:58:51 PM PDT 24
Peak memory 218676 kb
Host smart-846e9fe1-a17b-421d-ac62-2fbab6bbdc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873564035 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.2873564035
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.1795802287
Short name T814
Test name
Test status
Simulation time 135847242 ps
CPU time 1.29 seconds
Started Jul 14 06:58:52 PM PDT 24
Finished Jul 14 06:58:56 PM PDT 24
Peak memory 219280 kb
Host smart-bbac8019-26d7-42f7-aa2a-bea6732ced6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795802287 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1795802287
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.1879197783
Short name T920
Test name
Test status
Simulation time 31847616 ps
CPU time 0.83 seconds
Started Jul 14 06:58:35 PM PDT 24
Finished Jul 14 06:58:38 PM PDT 24
Peak memory 215556 kb
Host smart-e8eed515-286f-4bab-a249-c38cad16a5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879197783 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.1879197783
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.1000933209
Short name T612
Test name
Test status
Simulation time 40015809 ps
CPU time 0.87 seconds
Started Jul 14 06:58:24 PM PDT 24
Finished Jul 14 06:58:27 PM PDT 24
Peak memory 215560 kb
Host smart-5f20497e-d729-4620-b49b-378ac4521be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000933209 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.1000933209
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.1740321419
Short name T825
Test name
Test status
Simulation time 475303380 ps
CPU time 4.4 seconds
Started Jul 14 06:58:38 PM PDT 24
Finished Jul 14 06:58:43 PM PDT 24
Peak memory 217344 kb
Host smart-e707bdc2-bec4-42a7-8c76-ff38aaadf6af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740321419 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.1740321419
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.750303211
Short name T226
Test name
Test status
Simulation time 188310512685 ps
CPU time 1514.5 seconds
Started Jul 14 06:58:41 PM PDT 24
Finished Jul 14 07:23:57 PM PDT 24
Peak memory 224672 kb
Host smart-1d8a54e3-b453-4ab4-80dd-88d857200bee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750303211 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.750303211
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.4142734331
Short name T963
Test name
Test status
Simulation time 42616972 ps
CPU time 1.12 seconds
Started Jul 14 06:58:22 PM PDT 24
Finished Jul 14 06:58:27 PM PDT 24
Peak memory 218904 kb
Host smart-3b0617dc-635b-4ec2-932e-5019e65d493c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142734331 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.4142734331
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.1854907961
Short name T439
Test name
Test status
Simulation time 44755949 ps
CPU time 0.89 seconds
Started Jul 14 06:58:54 PM PDT 24
Finished Jul 14 06:58:58 PM PDT 24
Peak memory 207052 kb
Host smart-fab25518-58e0-47cf-8b50-73cc8c6036f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854907961 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.1854907961
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.140772413
Short name T675
Test name
Test status
Simulation time 21257554 ps
CPU time 0.87 seconds
Started Jul 14 06:58:26 PM PDT 24
Finished Jul 14 06:58:29 PM PDT 24
Peak memory 216308 kb
Host smart-8996ea3e-d0eb-48f4-8173-2a4c13c4ec5e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140772413 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.140772413
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.1161179201
Short name T477
Test name
Test status
Simulation time 85827574 ps
CPU time 1.08 seconds
Started Jul 14 06:58:40 PM PDT 24
Finished Jul 14 06:58:42 PM PDT 24
Peak memory 218400 kb
Host smart-d43c2bdc-614a-45bc-9c2e-6ab70f482565
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161179201 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.1161179201
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_intr.1369699339
Short name T585
Test name
Test status
Simulation time 20844372 ps
CPU time 1.1 seconds
Started Jul 14 06:58:41 PM PDT 24
Finished Jul 14 06:58:43 PM PDT 24
Peak memory 215792 kb
Host smart-0fc4aa03-5992-4eb4-bccb-32e2871a3201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369699339 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.1369699339
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.1522574372
Short name T847
Test name
Test status
Simulation time 90770447 ps
CPU time 0.86 seconds
Started Jul 14 06:58:34 PM PDT 24
Finished Jul 14 06:58:38 PM PDT 24
Peak memory 215460 kb
Host smart-2762edf0-ebe1-4b51-b7d6-0880ce94d9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522574372 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.1522574372
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.1120371154
Short name T394
Test name
Test status
Simulation time 214736478 ps
CPU time 4.36 seconds
Started Jul 14 06:58:37 PM PDT 24
Finished Jul 14 06:58:43 PM PDT 24
Peak memory 217524 kb
Host smart-d021b423-06d1-4083-8a6b-132f17fc6e82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120371154 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1120371154
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.880378737
Short name T853
Test name
Test status
Simulation time 205776952906 ps
CPU time 934.4 seconds
Started Jul 14 06:58:43 PM PDT 24
Finished Jul 14 07:14:19 PM PDT 24
Peak memory 221840 kb
Host smart-1d6d4d63-8b72-40ca-be2e-97b5926edb7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880378737 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.880378737
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.3004713394
Short name T417
Test name
Test status
Simulation time 29690958 ps
CPU time 1.26 seconds
Started Jul 14 06:58:53 PM PDT 24
Finished Jul 14 06:58:57 PM PDT 24
Peak memory 220056 kb
Host smart-cb71b588-86d4-4542-801a-998fa7cd310f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004713394 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.3004713394
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.337470015
Short name T610
Test name
Test status
Simulation time 23195351 ps
CPU time 0.86 seconds
Started Jul 14 06:58:28 PM PDT 24
Finished Jul 14 06:58:30 PM PDT 24
Peak memory 206984 kb
Host smart-a9b0f3f6-6746-4115-ae58-4cff9371f4de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337470015 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.337470015
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.1214320472
Short name T501
Test name
Test status
Simulation time 26150356 ps
CPU time 1.13 seconds
Started Jul 14 06:59:05 PM PDT 24
Finished Jul 14 06:59:11 PM PDT 24
Peak memory 217180 kb
Host smart-16e692e3-043a-4ffc-ab09-0105fafc1150
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214320472 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.1214320472
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.457992837
Short name T643
Test name
Test status
Simulation time 31276811 ps
CPU time 1.19 seconds
Started Jul 14 06:58:51 PM PDT 24
Finished Jul 14 06:58:54 PM PDT 24
Peak memory 220864 kb
Host smart-37ec10b0-862b-4aea-bd39-ed2961d5854c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457992837 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.457992837
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.2105228075
Short name T288
Test name
Test status
Simulation time 35284031 ps
CPU time 1.42 seconds
Started Jul 14 06:58:53 PM PDT 24
Finished Jul 14 06:58:57 PM PDT 24
Peak memory 218908 kb
Host smart-ec26fa9a-6d1f-455e-953f-ae21d3734772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105228075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2105228075
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.1174419670
Short name T95
Test name
Test status
Simulation time 28945882 ps
CPU time 0.96 seconds
Started Jul 14 06:58:51 PM PDT 24
Finished Jul 14 06:58:55 PM PDT 24
Peak memory 215844 kb
Host smart-ae1d0a4b-312f-468b-b6e3-f98cab48a6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174419670 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.1174419670
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.1266266069
Short name T375
Test name
Test status
Simulation time 17358976 ps
CPU time 0.96 seconds
Started Jul 14 06:58:39 PM PDT 24
Finished Jul 14 06:58:41 PM PDT 24
Peak memory 215624 kb
Host smart-aa1c0064-d644-4419-be91-840a9b43d4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266266069 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.1266266069
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.3134816698
Short name T432
Test name
Test status
Simulation time 133347135 ps
CPU time 2.98 seconds
Started Jul 14 06:58:49 PM PDT 24
Finished Jul 14 06:58:55 PM PDT 24
Peak memory 215636 kb
Host smart-f492a48f-8fa2-4bfd-b5b2-7926b5df977a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134816698 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.3134816698
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.77422996
Short name T221
Test name
Test status
Simulation time 46641421895 ps
CPU time 438.74 seconds
Started Jul 14 06:58:51 PM PDT 24
Finished Jul 14 07:06:13 PM PDT 24
Peak memory 219248 kb
Host smart-ff66bf3c-5db1-4089-8ced-c395e1bbcec2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77422996 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.77422996
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.693844615
Short name T45
Test name
Test status
Simulation time 85805769 ps
CPU time 1.19 seconds
Started Jul 14 06:58:26 PM PDT 24
Finished Jul 14 06:58:29 PM PDT 24
Peak memory 219016 kb
Host smart-23f8de08-a108-46fa-891b-103876dd445a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693844615 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.693844615
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.2248249911
Short name T564
Test name
Test status
Simulation time 21999036 ps
CPU time 1 seconds
Started Jul 14 06:58:59 PM PDT 24
Finished Jul 14 06:59:03 PM PDT 24
Peak memory 215484 kb
Host smart-d860a2d4-094f-44dd-83e6-e8d946190553
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248249911 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2248249911
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.3815024971
Short name T518
Test name
Test status
Simulation time 189049083 ps
CPU time 1.09 seconds
Started Jul 14 06:58:47 PM PDT 24
Finished Jul 14 06:58:50 PM PDT 24
Peak memory 217192 kb
Host smart-53285411-aa99-4bbb-a17b-d39db6682b6e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815024971 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.3815024971
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.362558464
Short name T178
Test name
Test status
Simulation time 18994964 ps
CPU time 1.14 seconds
Started Jul 14 06:59:00 PM PDT 24
Finished Jul 14 06:59:05 PM PDT 24
Peak memory 224260 kb
Host smart-23911d08-7dea-48d3-b975-4ab29dfdf5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362558464 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.362558464
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.3910795865
Short name T248
Test name
Test status
Simulation time 315005592 ps
CPU time 4.1 seconds
Started Jul 14 06:58:51 PM PDT 24
Finished Jul 14 06:58:58 PM PDT 24
Peak memory 218956 kb
Host smart-ab9a4391-9e75-403c-a388-f27c60cb697e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910795865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.3910795865
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.2200434461
Short name T487
Test name
Test status
Simulation time 23478428 ps
CPU time 0.96 seconds
Started Jul 14 06:58:52 PM PDT 24
Finished Jul 14 06:58:56 PM PDT 24
Peak memory 215780 kb
Host smart-ec06153d-0972-4b78-a7b3-dfddd70327bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200434461 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.2200434461
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.2163909175
Short name T986
Test name
Test status
Simulation time 33022906 ps
CPU time 1.01 seconds
Started Jul 14 06:58:52 PM PDT 24
Finished Jul 14 06:58:56 PM PDT 24
Peak memory 215548 kb
Host smart-251a82c2-4080-4e88-9de0-1636074aa1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163909175 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.2163909175
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3985445770
Short name T732
Test name
Test status
Simulation time 712242322 ps
CPU time 4.84 seconds
Started Jul 14 06:58:30 PM PDT 24
Finished Jul 14 06:58:37 PM PDT 24
Peak memory 217448 kb
Host smart-d66cbad0-42d1-4596-ae6f-7fd49a58858f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985445770 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3985445770
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.1298778489
Short name T230
Test name
Test status
Simulation time 90754412733 ps
CPU time 1927.32 seconds
Started Jul 14 06:58:47 PM PDT 24
Finished Jul 14 07:30:57 PM PDT 24
Peak memory 226836 kb
Host smart-254084a0-3f2b-491b-bab6-d42694471a2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298778489 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.1298778489
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert_test.2850388720
Short name T556
Test name
Test status
Simulation time 31824799 ps
CPU time 0.95 seconds
Started Jul 14 06:58:36 PM PDT 24
Finished Jul 14 06:58:38 PM PDT 24
Peak memory 207000 kb
Host smart-d70fc18f-7ddc-4a92-b85a-4c903765ddde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850388720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.2850388720
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.2117595231
Short name T180
Test name
Test status
Simulation time 12134946 ps
CPU time 1.01 seconds
Started Jul 14 06:58:45 PM PDT 24
Finished Jul 14 06:58:48 PM PDT 24
Peak memory 216632 kb
Host smart-dc97603c-ef6c-41c6-b95f-e23fbf6f9c99
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117595231 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.2117595231
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.1376800306
Short name T90
Test name
Test status
Simulation time 32859863 ps
CPU time 1.3 seconds
Started Jul 14 06:58:36 PM PDT 24
Finished Jul 14 06:58:39 PM PDT 24
Peak memory 217196 kb
Host smart-6cc51409-6813-456f-8707-8416df2a9bf5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376800306 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.1376800306
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.527605933
Short name T591
Test name
Test status
Simulation time 196893290 ps
CPU time 1.1 seconds
Started Jul 14 06:58:34 PM PDT 24
Finished Jul 14 06:58:38 PM PDT 24
Peak memory 224112 kb
Host smart-eb96137a-c8ad-4cad-8e2f-9a422c07e594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527605933 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.527605933
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.435009210
Short name T912
Test name
Test status
Simulation time 39210237 ps
CPU time 1.09 seconds
Started Jul 14 06:58:47 PM PDT 24
Finished Jul 14 06:58:50 PM PDT 24
Peak memory 220104 kb
Host smart-cc8450cd-d604-4ec1-9fef-f24741d234b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435009210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.435009210
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.2016562704
Short name T50
Test name
Test status
Simulation time 26462223 ps
CPU time 1.1 seconds
Started Jul 14 06:58:45 PM PDT 24
Finished Jul 14 06:58:54 PM PDT 24
Peak memory 224320 kb
Host smart-1fc83141-f18d-4eee-91b2-6063c7c1f8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016562704 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.2016562704
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.1779064491
Short name T642
Test name
Test status
Simulation time 22546361 ps
CPU time 0.91 seconds
Started Jul 14 06:58:41 PM PDT 24
Finished Jul 14 06:58:43 PM PDT 24
Peak memory 215608 kb
Host smart-c798680f-7b68-4b5f-82d4-c4a67eb4dd7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779064491 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.1779064491
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.303960639
Short name T311
Test name
Test status
Simulation time 351009131 ps
CPU time 3.85 seconds
Started Jul 14 06:58:31 PM PDT 24
Finished Jul 14 06:58:36 PM PDT 24
Peak memory 217636 kb
Host smart-38be1853-8d3e-41ef-8828-7958f4ff375c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303960639 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.303960639
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.330238258
Short name T738
Test name
Test status
Simulation time 27898221227 ps
CPU time 585.67 seconds
Started Jul 14 06:58:47 PM PDT 24
Finished Jul 14 07:08:35 PM PDT 24
Peak memory 218308 kb
Host smart-1a7af985-255c-4223-9138-c935af5b3b18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330238258 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.330238258
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.2396019724
Short name T381
Test name
Test status
Simulation time 30132377 ps
CPU time 1.25 seconds
Started Jul 14 06:58:52 PM PDT 24
Finished Jul 14 06:58:57 PM PDT 24
Peak memory 221240 kb
Host smart-9b7a88ed-2e79-40e8-b06b-f6d913ff4fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396019724 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.2396019724
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.1141845041
Short name T362
Test name
Test status
Simulation time 34446019 ps
CPU time 0.82 seconds
Started Jul 14 06:58:57 PM PDT 24
Finished Jul 14 06:59:00 PM PDT 24
Peak memory 206756 kb
Host smart-3aa7e1b3-9cf0-4e49-ae88-6d40e17c3a58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141845041 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1141845041
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.1934598883
Short name T762
Test name
Test status
Simulation time 38093579 ps
CPU time 0.85 seconds
Started Jul 14 06:58:52 PM PDT 24
Finished Jul 14 06:58:56 PM PDT 24
Peak memory 216156 kb
Host smart-1efd273c-c276-491f-a4de-754fb0bec0c3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934598883 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1934598883
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.918146147
Short name T121
Test name
Test status
Simulation time 63138342 ps
CPU time 1.17 seconds
Started Jul 14 06:58:50 PM PDT 24
Finished Jul 14 06:58:54 PM PDT 24
Peak memory 217140 kb
Host smart-51a04851-62b9-40f9-9cca-a33ae6a04deb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918146147 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_di
sable_auto_req_mode.918146147
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.4213923962
Short name T409
Test name
Test status
Simulation time 79419883 ps
CPU time 1.2 seconds
Started Jul 14 06:58:43 PM PDT 24
Finished Jul 14 06:58:45 PM PDT 24
Peak memory 219920 kb
Host smart-0efb3def-73f4-48f0-a8af-8a0f42f338a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213923962 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.4213923962
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.3705804884
Short name T464
Test name
Test status
Simulation time 44745860 ps
CPU time 1.43 seconds
Started Jul 14 06:58:51 PM PDT 24
Finished Jul 14 06:58:55 PM PDT 24
Peak memory 218944 kb
Host smart-053fb6a7-86ab-4108-88e1-acbb9b0172a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705804884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3705804884
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.4191327888
Short name T33
Test name
Test status
Simulation time 21069242 ps
CPU time 1.09 seconds
Started Jul 14 06:58:51 PM PDT 24
Finished Jul 14 06:58:54 PM PDT 24
Peak memory 216160 kb
Host smart-4e214739-ce42-476d-a8db-313aff953904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191327888 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.4191327888
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.3261395398
Short name T906
Test name
Test status
Simulation time 17124704 ps
CPU time 0.97 seconds
Started Jul 14 06:58:40 PM PDT 24
Finished Jul 14 06:58:42 PM PDT 24
Peak memory 215608 kb
Host smart-d4cffede-e9d5-482b-b209-75768062b204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261395398 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.3261395398
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.1749508987
Short name T465
Test name
Test status
Simulation time 134177219 ps
CPU time 1.76 seconds
Started Jul 14 06:58:35 PM PDT 24
Finished Jul 14 06:58:39 PM PDT 24
Peak memory 215608 kb
Host smart-cf5e44e0-4d1f-4a77-a5fd-96bc82477a04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749508987 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.1749508987
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1396620315
Short name T225
Test name
Test status
Simulation time 25731522503 ps
CPU time 562.49 seconds
Started Jul 14 06:58:45 PM PDT 24
Finished Jul 14 07:08:09 PM PDT 24
Peak memory 218452 kb
Host smart-289980b7-d05c-49cb-8177-79ff8c6467b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396620315 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1396620315
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.3197874446
Short name T858
Test name
Test status
Simulation time 45695525 ps
CPU time 1.11 seconds
Started Jul 14 06:58:48 PM PDT 24
Finished Jul 14 06:58:51 PM PDT 24
Peak memory 220144 kb
Host smart-171cdca0-4837-4d7f-a70f-10fd4c2727e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197874446 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3197874446
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.4059852261
Short name T47
Test name
Test status
Simulation time 51608139 ps
CPU time 0.88 seconds
Started Jul 14 06:58:49 PM PDT 24
Finished Jul 14 06:58:52 PM PDT 24
Peak memory 207040 kb
Host smart-d2ae5d72-932b-44a6-a7c3-c93b91f3afca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059852261 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.4059852261
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.1320454742
Short name T626
Test name
Test status
Simulation time 14479918 ps
CPU time 0.95 seconds
Started Jul 14 06:58:54 PM PDT 24
Finished Jul 14 06:58:58 PM PDT 24
Peak memory 216736 kb
Host smart-d04d39ca-15ef-4433-bf14-c7db35d577f3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320454742 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1320454742
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.2312886220
Short name T919
Test name
Test status
Simulation time 41045297 ps
CPU time 1.56 seconds
Started Jul 14 06:58:41 PM PDT 24
Finished Jul 14 06:58:44 PM PDT 24
Peak memory 217192 kb
Host smart-1efa2dfe-4e59-4a6d-80c0-a3e2a9f3defe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312886220 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.2312886220
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.1477179932
Short name T80
Test name
Test status
Simulation time 35404895 ps
CPU time 0.88 seconds
Started Jul 14 06:58:47 PM PDT 24
Finished Jul 14 06:58:50 PM PDT 24
Peak memory 218608 kb
Host smart-921fcc48-6bd0-463f-b196-73db4fe21ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477179932 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1477179932
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.1767872868
Short name T468
Test name
Test status
Simulation time 56289778 ps
CPU time 1.42 seconds
Started Jul 14 06:58:40 PM PDT 24
Finished Jul 14 06:58:43 PM PDT 24
Peak memory 218824 kb
Host smart-7a747689-07ae-417b-affd-bbeb9b594fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767872868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1767872868
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.983386773
Short name T431
Test name
Test status
Simulation time 30351484 ps
CPU time 0.98 seconds
Started Jul 14 06:58:33 PM PDT 24
Finished Jul 14 06:58:36 PM PDT 24
Peak memory 215868 kb
Host smart-e9424f4c-5ef0-43c0-bb6c-bdb5cade3baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983386773 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.983386773
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.154442286
Short name T951
Test name
Test status
Simulation time 25962197 ps
CPU time 0.92 seconds
Started Jul 14 06:58:51 PM PDT 24
Finished Jul 14 06:58:54 PM PDT 24
Peak memory 215548 kb
Host smart-e2c6c0d6-a6ae-4ad0-8a88-326c2c0070cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154442286 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.154442286
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.2918846636
Short name T711
Test name
Test status
Simulation time 629294237 ps
CPU time 3.99 seconds
Started Jul 14 06:58:53 PM PDT 24
Finished Jul 14 06:59:00 PM PDT 24
Peak memory 217660 kb
Host smart-df5d6bc7-5a49-47a2-8b0d-b76ac5b45368
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918846636 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.2918846636
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3588058014
Short name T406
Test name
Test status
Simulation time 132126898514 ps
CPU time 1614.27 seconds
Started Jul 14 06:58:47 PM PDT 24
Finished Jul 14 07:25:44 PM PDT 24
Peak memory 228164 kb
Host smart-18732fdc-a775-4f7a-92c3-10df9d3b5a50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588058014 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.3588058014
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.611815587
Short name T901
Test name
Test status
Simulation time 93470529 ps
CPU time 1.05 seconds
Started Jul 14 06:58:34 PM PDT 24
Finished Jul 14 06:58:38 PM PDT 24
Peak memory 218836 kb
Host smart-f0ad5489-e6a1-4469-8a78-eb5a1d768549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611815587 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.611815587
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.1256728762
Short name T937
Test name
Test status
Simulation time 33320221 ps
CPU time 0.91 seconds
Started Jul 14 06:59:13 PM PDT 24
Finished Jul 14 06:59:19 PM PDT 24
Peak memory 206968 kb
Host smart-1d8e31c3-0cce-4e77-9d0f-9f81d2737d2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256728762 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.1256728762
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.725871546
Short name T182
Test name
Test status
Simulation time 12709735 ps
CPU time 0.91 seconds
Started Jul 14 06:58:54 PM PDT 24
Finished Jul 14 06:58:58 PM PDT 24
Peak memory 216784 kb
Host smart-596a1773-be23-4a94-a893-cff706fd18ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725871546 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.725871546
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.3143246487
Short name T128
Test name
Test status
Simulation time 62273485 ps
CPU time 1.29 seconds
Started Jul 14 06:58:45 PM PDT 24
Finished Jul 14 06:58:48 PM PDT 24
Peak memory 217292 kb
Host smart-e604b185-d1f5-444d-a885-e33e14acf692
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143246487 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.3143246487
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.3250524790
Short name T118
Test name
Test status
Simulation time 45689858 ps
CPU time 0.98 seconds
Started Jul 14 06:58:44 PM PDT 24
Finished Jul 14 06:58:47 PM PDT 24
Peak memory 219828 kb
Host smart-473639b6-a134-45ba-b713-a8b649d7212a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250524790 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.3250524790
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.1715105654
Short name T936
Test name
Test status
Simulation time 80030331 ps
CPU time 1.1 seconds
Started Jul 14 06:58:50 PM PDT 24
Finished Jul 14 06:58:53 PM PDT 24
Peak memory 217684 kb
Host smart-3d57b030-dd88-4e21-972e-8027c391a3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715105654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1715105654
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.785973574
Short name T921
Test name
Test status
Simulation time 21017230 ps
CPU time 1.13 seconds
Started Jul 14 06:58:48 PM PDT 24
Finished Jul 14 06:58:51 PM PDT 24
Peak memory 215796 kb
Host smart-6c4cb771-b024-418b-b01a-daec2305e8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785973574 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.785973574
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.3301529083
Short name T797
Test name
Test status
Simulation time 18152716 ps
CPU time 1.03 seconds
Started Jul 14 06:58:39 PM PDT 24
Finished Jul 14 06:58:41 PM PDT 24
Peak memory 215600 kb
Host smart-32f32e17-3b30-4227-970d-c9d69a48c49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301529083 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3301529083
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.2615565623
Short name T954
Test name
Test status
Simulation time 266701349 ps
CPU time 2.41 seconds
Started Jul 14 06:58:52 PM PDT 24
Finished Jul 14 06:58:56 PM PDT 24
Peak memory 218792 kb
Host smart-06ede42f-a292-4519-9da0-5c701b6764fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615565623 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2615565623
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.68473454
Short name T233
Test name
Test status
Simulation time 77864131958 ps
CPU time 435.99 seconds
Started Jul 14 06:58:56 PM PDT 24
Finished Jul 14 07:06:15 PM PDT 24
Peak memory 223964 kb
Host smart-d6516f93-26ce-4032-a98d-922118e5b30a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68473454 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.68473454
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.1528260016
Short name T666
Test name
Test status
Simulation time 28556074 ps
CPU time 1.3 seconds
Started Jul 14 06:58:54 PM PDT 24
Finished Jul 14 06:58:58 PM PDT 24
Peak memory 221284 kb
Host smart-e8b04e6c-bede-4f49-a759-3fa38d7d1e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528260016 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.1528260016
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.4018357340
Short name T470
Test name
Test status
Simulation time 90046629 ps
CPU time 0.79 seconds
Started Jul 14 06:58:56 PM PDT 24
Finished Jul 14 06:59:00 PM PDT 24
Peak memory 206684 kb
Host smart-97e17dab-cc02-4fb1-b3a9-821c5e848e51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018357340 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.4018357340
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_err.1961283412
Short name T119
Test name
Test status
Simulation time 157215861 ps
CPU time 1.09 seconds
Started Jul 14 06:58:32 PM PDT 24
Finished Jul 14 06:58:35 PM PDT 24
Peak memory 217752 kb
Host smart-369da0db-8dd4-491a-afcc-db575270b3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961283412 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.1961283412
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.167137229
Short name T86
Test name
Test status
Simulation time 45952101 ps
CPU time 1.42 seconds
Started Jul 14 06:58:38 PM PDT 24
Finished Jul 14 06:58:41 PM PDT 24
Peak memory 218792 kb
Host smart-6bd3cab9-7c4d-4a2b-9a07-37b69ead0dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167137229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.167137229
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.1703033592
Short name T758
Test name
Test status
Simulation time 22852295 ps
CPU time 0.97 seconds
Started Jul 14 06:59:12 PM PDT 24
Finished Jul 14 06:59:18 PM PDT 24
Peak memory 216148 kb
Host smart-3f80494d-be41-4d76-8a21-831d9ad1a01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703033592 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1703033592
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.346874512
Short name T506
Test name
Test status
Simulation time 26932059 ps
CPU time 0.9 seconds
Started Jul 14 06:58:50 PM PDT 24
Finished Jul 14 06:58:54 PM PDT 24
Peak memory 215600 kb
Host smart-eb40aeb4-d696-42ff-b115-5c1d6a0fb619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346874512 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.346874512
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.3904074954
Short name T629
Test name
Test status
Simulation time 45960385 ps
CPU time 1.15 seconds
Started Jul 14 06:59:13 PM PDT 24
Finished Jul 14 06:59:19 PM PDT 24
Peak memory 207048 kb
Host smart-b687a027-97c7-4a90-a373-57d32d48811d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904074954 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3904074954
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.3993239591
Short name T630
Test name
Test status
Simulation time 539466113512 ps
CPU time 2063.67 seconds
Started Jul 14 06:59:01 PM PDT 24
Finished Jul 14 07:33:29 PM PDT 24
Peak memory 227900 kb
Host smart-76a77ae6-1efd-46ad-b1c6-57eb759cc245
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993239591 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.3993239591
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.3282011777
Short name T589
Test name
Test status
Simulation time 23959074 ps
CPU time 1.2 seconds
Started Jul 14 06:58:45 PM PDT 24
Finished Jul 14 06:58:48 PM PDT 24
Peak memory 219804 kb
Host smart-22907e22-f1c6-4edd-9c18-074ef715f71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282011777 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.3282011777
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.578892790
Short name T884
Test name
Test status
Simulation time 38284419 ps
CPU time 0.85 seconds
Started Jul 14 06:58:54 PM PDT 24
Finished Jul 14 06:58:58 PM PDT 24
Peak memory 215180 kb
Host smart-861f596b-26d7-4e12-ad63-3c7f1171f06a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578892790 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.578892790
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.1812943850
Short name T489
Test name
Test status
Simulation time 26952001 ps
CPU time 0.87 seconds
Started Jul 14 06:59:12 PM PDT 24
Finished Jul 14 06:59:18 PM PDT 24
Peak memory 216248 kb
Host smart-c8af945b-c77b-4d76-865e-c8ff2f441c6f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812943850 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1812943850
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.4098095548
Short name T750
Test name
Test status
Simulation time 45024319 ps
CPU time 1.15 seconds
Started Jul 14 06:58:56 PM PDT 24
Finished Jul 14 06:58:59 PM PDT 24
Peak memory 220292 kb
Host smart-9e83e7cc-49e5-436f-bd07-78310c0c3548
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098095548 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.4098095548
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.71536367
Short name T120
Test name
Test status
Simulation time 91982538 ps
CPU time 0.91 seconds
Started Jul 14 06:58:40 PM PDT 24
Finished Jul 14 06:58:42 PM PDT 24
Peak memory 219928 kb
Host smart-2d0a1db0-cc3f-48a6-b6d8-0eeba681928f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71536367 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.71536367
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.320499616
Short name T542
Test name
Test status
Simulation time 209102614 ps
CPU time 1.15 seconds
Started Jul 14 06:58:58 PM PDT 24
Finished Jul 14 06:59:01 PM PDT 24
Peak memory 220456 kb
Host smart-126847b2-8fba-4331-bf2a-8a75c02aaaa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320499616 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.320499616
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.3871754690
Short name T897
Test name
Test status
Simulation time 40449953 ps
CPU time 0.93 seconds
Started Jul 14 06:58:33 PM PDT 24
Finished Jul 14 06:58:37 PM PDT 24
Peak memory 224120 kb
Host smart-5900aaa0-4b8d-482f-a6ef-f4f0d358c81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871754690 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.3871754690
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.3690777435
Short name T933
Test name
Test status
Simulation time 46001515 ps
CPU time 0.92 seconds
Started Jul 14 06:58:43 PM PDT 24
Finished Jul 14 06:58:45 PM PDT 24
Peak memory 215604 kb
Host smart-e9f32d57-d438-4bd9-8177-9fd6b27e8673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690777435 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.3690777435
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.2928516294
Short name T570
Test name
Test status
Simulation time 928302253 ps
CPU time 4.9 seconds
Started Jul 14 06:59:14 PM PDT 24
Finished Jul 14 06:59:23 PM PDT 24
Peak memory 217652 kb
Host smart-96084877-0b44-4ae1-b657-197d7f875c3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928516294 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2928516294
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.410982053
Short name T890
Test name
Test status
Simulation time 64917044918 ps
CPU time 438.29 seconds
Started Jul 14 06:58:55 PM PDT 24
Finished Jul 14 07:06:16 PM PDT 24
Peak memory 224284 kb
Host smart-944be3e7-5e51-4850-8568-729c9bcf1a97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410982053 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.410982053
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.3469132572
Short name T183
Test name
Test status
Simulation time 26795831 ps
CPU time 1.25 seconds
Started Jul 14 06:57:59 PM PDT 24
Finished Jul 14 06:58:01 PM PDT 24
Peak memory 219860 kb
Host smart-7315ba52-5e1f-4e32-b9de-305ada58a589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469132572 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3469132572
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.4176405309
Short name T392
Test name
Test status
Simulation time 74428672 ps
CPU time 0.99 seconds
Started Jul 14 06:58:02 PM PDT 24
Finished Jul 14 06:58:05 PM PDT 24
Peak memory 206984 kb
Host smart-97d676f8-149b-4f62-8c02-15aeb40a14eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176405309 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.4176405309
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.881468886
Short name T172
Test name
Test status
Simulation time 40453157 ps
CPU time 0.91 seconds
Started Jul 14 06:57:58 PM PDT 24
Finished Jul 14 06:58:00 PM PDT 24
Peak memory 216496 kb
Host smart-2337c5ac-9057-4d86-8ec3-61a937cc3df7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881468886 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.881468886
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.132679112
Short name T515
Test name
Test status
Simulation time 58981547 ps
CPU time 1.04 seconds
Started Jul 14 06:58:02 PM PDT 24
Finished Jul 14 06:58:05 PM PDT 24
Peak memory 217140 kb
Host smart-87d2a61d-6994-428a-9109-729db0c72bf0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132679112 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_dis
able_auto_req_mode.132679112
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.2280326483
Short name T77
Test name
Test status
Simulation time 22742492 ps
CPU time 0.96 seconds
Started Jul 14 06:57:51 PM PDT 24
Finished Jul 14 06:57:53 PM PDT 24
Peak memory 218708 kb
Host smart-ad0e94f5-7b61-43da-bc37-159ab6d108a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280326483 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.2280326483
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.3674575786
Short name T55
Test name
Test status
Simulation time 125768081 ps
CPU time 1.41 seconds
Started Jul 14 06:57:55 PM PDT 24
Finished Jul 14 06:57:58 PM PDT 24
Peak memory 219520 kb
Host smart-0413a682-f82e-47bc-a92a-4372928e423f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674575786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.3674575786
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.1257122536
Short name T967
Test name
Test status
Simulation time 32400599 ps
CPU time 0.89 seconds
Started Jul 14 06:57:51 PM PDT 24
Finished Jul 14 06:57:53 PM PDT 24
Peak memory 215928 kb
Host smart-fc8d692c-4b43-48b9-af2c-acfbcb1aef9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257122536 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.1257122536
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.2541571871
Short name T942
Test name
Test status
Simulation time 23375775 ps
CPU time 0.91 seconds
Started Jul 14 06:57:57 PM PDT 24
Finished Jul 14 06:57:59 PM PDT 24
Peak memory 207448 kb
Host smart-46619b05-3591-4059-a2bc-140aa79b3824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541571871 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.2541571871
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.1484061947
Short name T57
Test name
Test status
Simulation time 516842395 ps
CPU time 4.48 seconds
Started Jul 14 06:58:20 PM PDT 24
Finished Jul 14 06:58:29 PM PDT 24
Peak memory 235512 kb
Host smart-136df649-bfc3-4977-b33e-d74fc8eac322
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484061947 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.1484061947
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.2137213260
Short name T408
Test name
Test status
Simulation time 16423121 ps
CPU time 0.99 seconds
Started Jul 14 06:58:05 PM PDT 24
Finished Jul 14 06:58:10 PM PDT 24
Peak memory 215588 kb
Host smart-7f1fb576-0663-4d0a-898a-5aebbb710043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137213260 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.2137213260
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.4190794486
Short name T983
Test name
Test status
Simulation time 463248961 ps
CPU time 4.93 seconds
Started Jul 14 06:57:55 PM PDT 24
Finished Jul 14 06:58:01 PM PDT 24
Peak memory 215544 kb
Host smart-833e2630-30fd-436e-85aa-1f5500b6c1b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190794486 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.4190794486
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2317729102
Short name T227
Test name
Test status
Simulation time 43285503001 ps
CPU time 499.16 seconds
Started Jul 14 06:58:12 PM PDT 24
Finished Jul 14 07:06:38 PM PDT 24
Peak memory 219468 kb
Host smart-1669c4f2-80cf-4c6f-9539-8d65e7288a91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317729102 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.2317729102
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.3523882173
Short name T561
Test name
Test status
Simulation time 32266444 ps
CPU time 1.46 seconds
Started Jul 14 06:59:09 PM PDT 24
Finished Jul 14 06:59:16 PM PDT 24
Peak memory 220512 kb
Host smart-a452a13b-de95-4c39-8887-bcb1a5b172cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523882173 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.3523882173
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.2585037878
Short name T990
Test name
Test status
Simulation time 19148031 ps
CPU time 0.83 seconds
Started Jul 14 06:59:00 PM PDT 24
Finished Jul 14 06:59:05 PM PDT 24
Peak memory 207084 kb
Host smart-27f9b0c9-90e2-4a63-8c45-c1e9f25ef39d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585037878 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.2585037878
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.334486710
Short name T625
Test name
Test status
Simulation time 14142873 ps
CPU time 0.89 seconds
Started Jul 14 06:59:03 PM PDT 24
Finished Jul 14 06:59:08 PM PDT 24
Peak memory 215700 kb
Host smart-ef27a181-93e5-480b-8de9-9e0a6af70cee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334486710 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.334486710
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.1104887653
Short name T490
Test name
Test status
Simulation time 36445492 ps
CPU time 1.18 seconds
Started Jul 14 06:58:48 PM PDT 24
Finished Jul 14 06:58:52 PM PDT 24
Peak memory 217080 kb
Host smart-8f0e4b06-7cee-48cf-945d-a2bd9c8decbf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104887653 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.1104887653
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.2808744178
Short name T955
Test name
Test status
Simulation time 45161726 ps
CPU time 1.2 seconds
Started Jul 14 06:58:47 PM PDT 24
Finished Jul 14 06:58:51 PM PDT 24
Peak memory 224276 kb
Host smart-f0d6c918-a97d-4598-a781-82f9de1567ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808744178 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.2808744178
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.941149209
Short name T509
Test name
Test status
Simulation time 58667266 ps
CPU time 1.15 seconds
Started Jul 14 06:58:45 PM PDT 24
Finished Jul 14 06:58:48 PM PDT 24
Peak memory 217744 kb
Host smart-6fd4a63a-9d4b-415c-aa6c-caf822f77f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941149209 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.941149209
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.2921234989
Short name T870
Test name
Test status
Simulation time 22678949 ps
CPU time 1.14 seconds
Started Jul 14 06:58:54 PM PDT 24
Finished Jul 14 06:58:59 PM PDT 24
Peak memory 215736 kb
Host smart-af911185-c313-45ad-8daf-de3f90c8faca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921234989 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.2921234989
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.1587143954
Short name T864
Test name
Test status
Simulation time 26153048 ps
CPU time 0.94 seconds
Started Jul 14 06:58:58 PM PDT 24
Finished Jul 14 06:59:01 PM PDT 24
Peak memory 207388 kb
Host smart-c0bb5953-fad0-43a7-abda-aa985f13260b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587143954 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1587143954
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.1276682317
Short name T994
Test name
Test status
Simulation time 296184139 ps
CPU time 3.55 seconds
Started Jul 14 06:59:05 PM PDT 24
Finished Jul 14 06:59:14 PM PDT 24
Peak memory 217460 kb
Host smart-b3239f06-b898-492c-b6bd-19ee8703fd18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276682317 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.1276682317
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.3857848844
Short name T395
Test name
Test status
Simulation time 54150664191 ps
CPU time 1384.69 seconds
Started Jul 14 06:58:43 PM PDT 24
Finished Jul 14 07:21:49 PM PDT 24
Peak memory 224188 kb
Host smart-58760190-a7aa-444b-9326-c21f9d70c94d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857848844 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.3857848844
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.2985906187
Short name T279
Test name
Test status
Simulation time 30435207 ps
CPU time 1.3 seconds
Started Jul 14 06:58:48 PM PDT 24
Finished Jul 14 06:58:52 PM PDT 24
Peak memory 220800 kb
Host smart-911c1b66-96a4-4843-9a49-d5c66f06a708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985906187 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.2985906187
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.4260526009
Short name T931
Test name
Test status
Simulation time 20921878 ps
CPU time 1.04 seconds
Started Jul 14 06:59:06 PM PDT 24
Finished Jul 14 06:59:12 PM PDT 24
Peak memory 207108 kb
Host smart-6fc78323-c6b9-49c3-bc73-869e78763ad8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260526009 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.4260526009
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.191241927
Short name T486
Test name
Test status
Simulation time 11532153 ps
CPU time 0.9 seconds
Started Jul 14 06:59:08 PM PDT 24
Finished Jul 14 06:59:14 PM PDT 24
Peak memory 216576 kb
Host smart-502404b2-cc51-4451-9e0e-9abe780c0f90
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191241927 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.191241927
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.1930128118
Short name T425
Test name
Test status
Simulation time 49164830 ps
CPU time 1.45 seconds
Started Jul 14 06:58:47 PM PDT 24
Finished Jul 14 06:58:51 PM PDT 24
Peak memory 217192 kb
Host smart-e7741fcc-90b8-48ad-bd75-28f4760d4ffe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930128118 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.1930128118
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.2338697210
Short name T987
Test name
Test status
Simulation time 25948135 ps
CPU time 1.2 seconds
Started Jul 14 06:58:56 PM PDT 24
Finished Jul 14 06:58:59 PM PDT 24
Peak memory 221108 kb
Host smart-f4ff3b81-2668-4035-8765-edb4b74a0f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338697210 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2338697210
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.2726619779
Short name T497
Test name
Test status
Simulation time 164563484 ps
CPU time 2.13 seconds
Started Jul 14 06:59:03 PM PDT 24
Finished Jul 14 06:59:10 PM PDT 24
Peak memory 220432 kb
Host smart-7e14b9ac-c4b6-400f-b949-b6408c8356d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726619779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.2726619779
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.1714694241
Short name T553
Test name
Test status
Simulation time 20894006 ps
CPU time 1.13 seconds
Started Jul 14 06:58:54 PM PDT 24
Finished Jul 14 06:58:58 PM PDT 24
Peak memory 215696 kb
Host smart-595ee205-a7fd-48c0-a97b-e237842ab12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714694241 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.1714694241
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.789876705
Short name T349
Test name
Test status
Simulation time 41241429 ps
CPU time 0.86 seconds
Started Jul 14 06:58:50 PM PDT 24
Finished Jul 14 06:58:54 PM PDT 24
Peak memory 215420 kb
Host smart-7a2b3752-9ebc-4bed-8e00-8ba304ac7248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789876705 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.789876705
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.3442401366
Short name T237
Test name
Test status
Simulation time 337063611 ps
CPU time 2.99 seconds
Started Jul 14 06:58:52 PM PDT 24
Finished Jul 14 06:58:57 PM PDT 24
Peak memory 217488 kb
Host smart-295de009-e210-4983-bfde-fafbcb3dbee2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442401366 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3442401366
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1076229699
Short name T407
Test name
Test status
Simulation time 33072748215 ps
CPU time 365.56 seconds
Started Jul 14 06:59:16 PM PDT 24
Finished Jul 14 07:05:25 PM PDT 24
Peak memory 219568 kb
Host smart-078e9838-bb5b-45d6-a145-30c46b553742
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076229699 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.1076229699
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.2920853225
Short name T891
Test name
Test status
Simulation time 29299165 ps
CPU time 1.25 seconds
Started Jul 14 06:58:45 PM PDT 24
Finished Jul 14 06:58:48 PM PDT 24
Peak memory 219024 kb
Host smart-5e6eed5d-d4b0-4aa8-a514-097880c2aa51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920853225 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.2920853225
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.2879730
Short name T930
Test name
Test status
Simulation time 32270165 ps
CPU time 0.91 seconds
Started Jul 14 06:59:00 PM PDT 24
Finished Jul 14 06:59:05 PM PDT 24
Peak memory 206964 kb
Host smart-3e596d01-33e4-497e-b0bc-a40e283cdf2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879730 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2879730
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.2963563632
Short name T391
Test name
Test status
Simulation time 37085721 ps
CPU time 0.87 seconds
Started Jul 14 06:58:55 PM PDT 24
Finished Jul 14 06:58:58 PM PDT 24
Peak memory 216224 kb
Host smart-f4f143ec-5f64-4a2c-8c4d-f0e8223a387d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963563632 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.2963563632
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_err.4284143372
Short name T8
Test name
Test status
Simulation time 86339591 ps
CPU time 1.02 seconds
Started Jul 14 06:58:57 PM PDT 24
Finished Jul 14 06:59:00 PM PDT 24
Peak memory 219860 kb
Host smart-b62189a8-15b6-486c-8675-d46613e2a396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284143372 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.4284143372
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.3509484458
Short name T242
Test name
Test status
Simulation time 43150038 ps
CPU time 1.6 seconds
Started Jul 14 06:59:18 PM PDT 24
Finished Jul 14 06:59:21 PM PDT 24
Peak memory 215620 kb
Host smart-3b46aed2-6d3a-4e2e-88a7-e8d9414d4c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509484458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.3509484458
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.2846602731
Short name T575
Test name
Test status
Simulation time 20976834 ps
CPU time 1.25 seconds
Started Jul 14 06:59:03 PM PDT 24
Finished Jul 14 06:59:09 PM PDT 24
Peak memory 224288 kb
Host smart-00aaa925-9890-4701-b256-9f556f927acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846602731 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.2846602731
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.2740197779
Short name T757
Test name
Test status
Simulation time 16992984 ps
CPU time 0.97 seconds
Started Jul 14 06:59:04 PM PDT 24
Finished Jul 14 06:59:10 PM PDT 24
Peak memory 215524 kb
Host smart-b5150be4-2de6-4eba-b7b2-d59d5489cce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740197779 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.2740197779
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.3577444817
Short name T366
Test name
Test status
Simulation time 84893016 ps
CPU time 1.46 seconds
Started Jul 14 06:58:56 PM PDT 24
Finished Jul 14 06:58:59 PM PDT 24
Peak memory 215560 kb
Host smart-609f89bc-a075-42b3-9200-7d9a8bca8cd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577444817 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.3577444817
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.2819437041
Short name T543
Test name
Test status
Simulation time 76282968715 ps
CPU time 960.94 seconds
Started Jul 14 06:59:00 PM PDT 24
Finished Jul 14 07:15:04 PM PDT 24
Peak memory 222544 kb
Host smart-b23ff6da-ddfb-46bb-8839-67c6a882c94c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819437041 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.2819437041
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.4057590850
Short name T843
Test name
Test status
Simulation time 80138548 ps
CPU time 1.21 seconds
Started Jul 14 06:58:53 PM PDT 24
Finished Jul 14 06:58:57 PM PDT 24
Peak memory 219492 kb
Host smart-01bd181c-f1e2-4ded-8a4d-ed92236be6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057590850 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.4057590850
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.2658314860
Short name T563
Test name
Test status
Simulation time 30137128 ps
CPU time 1.11 seconds
Started Jul 14 06:59:01 PM PDT 24
Finished Jul 14 06:59:06 PM PDT 24
Peak memory 207020 kb
Host smart-62814096-364f-4114-ac5e-cbd2b9b35e0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658314860 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2658314860
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.337516655
Short name T905
Test name
Test status
Simulation time 28455027 ps
CPU time 1.1 seconds
Started Jul 14 06:58:47 PM PDT 24
Finished Jul 14 06:58:51 PM PDT 24
Peak memory 217184 kb
Host smart-739aed3f-6830-463f-9ff3-d356e43a1591
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337516655 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_di
sable_auto_req_mode.337516655
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.2410627347
Short name T656
Test name
Test status
Simulation time 26352574 ps
CPU time 0.98 seconds
Started Jul 14 06:58:58 PM PDT 24
Finished Jul 14 06:59:01 PM PDT 24
Peak memory 229708 kb
Host smart-756d1f8f-5611-4bfc-a8a9-df290947a3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410627347 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.2410627347
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.3437865392
Short name T479
Test name
Test status
Simulation time 57964109 ps
CPU time 1.02 seconds
Started Jul 14 06:59:00 PM PDT 24
Finished Jul 14 06:59:05 PM PDT 24
Peak memory 217788 kb
Host smart-95421f20-7a30-4abf-93b9-dc565b50a6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437865392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.3437865392
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.382085222
Short name T28
Test name
Test status
Simulation time 22413722 ps
CPU time 1.01 seconds
Started Jul 14 06:58:54 PM PDT 24
Finished Jul 14 06:58:58 PM PDT 24
Peak memory 216036 kb
Host smart-5addf551-6d16-4a93-8234-b62b738d6beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382085222 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.382085222
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.4057433505
Short name T720
Test name
Test status
Simulation time 86066742 ps
CPU time 0.88 seconds
Started Jul 14 06:59:08 PM PDT 24
Finished Jul 14 06:59:22 PM PDT 24
Peak memory 207472 kb
Host smart-c7913543-eef8-4d10-874f-ad6b2e0627a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057433505 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.4057433505
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.3913188193
Short name T244
Test name
Test status
Simulation time 517384851 ps
CPU time 2.97 seconds
Started Jul 14 06:58:49 PM PDT 24
Finished Jul 14 06:58:55 PM PDT 24
Peak memory 217704 kb
Host smart-9b2851c6-5f8a-4040-8480-12214102778c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913188193 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3913188193
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.424743047
Short name T913
Test name
Test status
Simulation time 89622808601 ps
CPU time 820.67 seconds
Started Jul 14 06:59:01 PM PDT 24
Finished Jul 14 07:12:46 PM PDT 24
Peak memory 221272 kb
Host smart-551df64d-f650-41f0-ba43-3ebf20fb1ff9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424743047 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.424743047
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.4175859138
Short name T304
Test name
Test status
Simulation time 26890673 ps
CPU time 1.17 seconds
Started Jul 14 06:59:18 PM PDT 24
Finished Jul 14 06:59:21 PM PDT 24
Peak memory 219040 kb
Host smart-c0fdf2af-f8e8-4a62-8c46-30d0112f00d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175859138 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.4175859138
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.385646794
Short name T645
Test name
Test status
Simulation time 34615468 ps
CPU time 0.9 seconds
Started Jul 14 06:59:06 PM PDT 24
Finished Jul 14 06:59:13 PM PDT 24
Peak memory 215428 kb
Host smart-ab27e862-bbf5-4dbd-9dd8-17211986caed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385646794 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.385646794
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.3246649778
Short name T799
Test name
Test status
Simulation time 18826978 ps
CPU time 0.83 seconds
Started Jul 14 06:59:05 PM PDT 24
Finished Jul 14 06:59:10 PM PDT 24
Peak memory 215672 kb
Host smart-2d077c84-4600-479c-bbf8-736a7043dfc2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246649778 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.3246649778
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.2019582411
Short name T798
Test name
Test status
Simulation time 49623328 ps
CPU time 1.02 seconds
Started Jul 14 06:58:57 PM PDT 24
Finished Jul 14 06:59:00 PM PDT 24
Peak memory 217204 kb
Host smart-aee5c2bc-39c4-4809-afab-4c981d42d09e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019582411 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.2019582411
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.3490577302
Short name T992
Test name
Test status
Simulation time 22857370 ps
CPU time 1.03 seconds
Started Jul 14 06:59:01 PM PDT 24
Finished Jul 14 06:59:06 PM PDT 24
Peak memory 224192 kb
Host smart-8f08fa99-07f6-45f9-88ab-0cba250b0fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490577302 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.3490577302
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.2085202052
Short name T424
Test name
Test status
Simulation time 28879318 ps
CPU time 1.3 seconds
Started Jul 14 06:59:03 PM PDT 24
Finished Jul 14 06:59:09 PM PDT 24
Peak memory 218884 kb
Host smart-aa1fe533-6d0e-4638-9f36-dc2771cd3b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085202052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.2085202052
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.2148070822
Short name T926
Test name
Test status
Simulation time 37445219 ps
CPU time 0.89 seconds
Started Jul 14 06:58:58 PM PDT 24
Finished Jul 14 06:59:01 PM PDT 24
Peak memory 215776 kb
Host smart-2f03b1d0-fca1-4cbd-8703-550c8dc194ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148070822 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.2148070822
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.156177024
Short name T704
Test name
Test status
Simulation time 58137056 ps
CPU time 0.92 seconds
Started Jul 14 06:58:55 PM PDT 24
Finished Jul 14 06:58:59 PM PDT 24
Peak memory 215532 kb
Host smart-61979d59-eec6-4bc4-8a1f-94b32952c283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156177024 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.156177024
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.3954363530
Short name T709
Test name
Test status
Simulation time 377407343 ps
CPU time 2.46 seconds
Started Jul 14 06:58:52 PM PDT 24
Finished Jul 14 06:58:58 PM PDT 24
Peak memory 217812 kb
Host smart-7b0d4102-6337-4194-9e76-9d5b44b3677f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954363530 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3954363530
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.29073615
Short name T228
Test name
Test status
Simulation time 506522190459 ps
CPU time 1243.01 seconds
Started Jul 14 06:59:01 PM PDT 24
Finished Jul 14 07:19:48 PM PDT 24
Peak memory 222776 kb
Host smart-7079def1-e4c4-4a2a-8749-d962cad26855
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29073615 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.29073615
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.808495573
Short name T147
Test name
Test status
Simulation time 54863539 ps
CPU time 1.19 seconds
Started Jul 14 06:59:14 PM PDT 24
Finished Jul 14 06:59:19 PM PDT 24
Peak memory 216008 kb
Host smart-358fd329-945c-4fae-ae64-d30d45bfff05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808495573 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.808495573
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.3578214733
Short name T239
Test name
Test status
Simulation time 16660558 ps
CPU time 0.96 seconds
Started Jul 14 06:59:00 PM PDT 24
Finished Jul 14 06:59:05 PM PDT 24
Peak memory 215480 kb
Host smart-5761869e-0006-46b2-8bb4-28c15d3e73a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578214733 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3578214733
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.2364341324
Short name T87
Test name
Test status
Simulation time 11183300 ps
CPU time 0.87 seconds
Started Jul 14 06:59:00 PM PDT 24
Finished Jul 14 06:59:04 PM PDT 24
Peak memory 216272 kb
Host smart-a33ac98c-2755-4598-8060-bfaa2e9523fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364341324 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2364341324
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.1334289565
Short name T510
Test name
Test status
Simulation time 124234070 ps
CPU time 1.32 seconds
Started Jul 14 06:58:59 PM PDT 24
Finished Jul 14 06:59:05 PM PDT 24
Peak memory 217240 kb
Host smart-b1f43a51-8f5d-4afe-be30-a31546c47660
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334289565 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.1334289565
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.806125818
Short name T733
Test name
Test status
Simulation time 42207607 ps
CPU time 1.1 seconds
Started Jul 14 06:59:01 PM PDT 24
Finished Jul 14 06:59:07 PM PDT 24
Peak memory 224172 kb
Host smart-259c2ff4-3974-4002-8f42-9743ecbcf289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806125818 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.806125818
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.3413633935
Short name T935
Test name
Test status
Simulation time 50386998 ps
CPU time 1.41 seconds
Started Jul 14 06:59:08 PM PDT 24
Finished Jul 14 06:59:15 PM PDT 24
Peak memory 218928 kb
Host smart-31f71f19-a495-43f4-bd5c-9dc703808a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413633935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.3413633935
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.3723295826
Short name T803
Test name
Test status
Simulation time 44590389 ps
CPU time 0.86 seconds
Started Jul 14 06:59:22 PM PDT 24
Finished Jul 14 06:59:24 PM PDT 24
Peak memory 215664 kb
Host smart-3ff081f3-7f3f-4a74-9f93-520d46b409b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723295826 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.3723295826
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.3677538445
Short name T369
Test name
Test status
Simulation time 22171693 ps
CPU time 0.95 seconds
Started Jul 14 06:58:58 PM PDT 24
Finished Jul 14 06:59:01 PM PDT 24
Peak memory 215620 kb
Host smart-6a44dcd0-7f82-40e3-942e-2d9ef6d83881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677538445 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.3677538445
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.2179160446
Short name T100
Test name
Test status
Simulation time 1036990146 ps
CPU time 5.74 seconds
Started Jul 14 06:58:52 PM PDT 24
Finished Jul 14 06:59:00 PM PDT 24
Peak memory 219944 kb
Host smart-dd5cca47-6075-4e11-a0f9-1211522e0f7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179160446 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.2179160446
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.67251360
Short name T70
Test name
Test status
Simulation time 21741454072 ps
CPU time 559.41 seconds
Started Jul 14 06:59:01 PM PDT 24
Finished Jul 14 07:08:31 PM PDT 24
Peak memory 218284 kb
Host smart-d78ddcdc-d7d8-4acb-94b2-fc05652af3e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67251360 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.67251360
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.964967114
Short name T396
Test name
Test status
Simulation time 50750671 ps
CPU time 1.33 seconds
Started Jul 14 06:59:07 PM PDT 24
Finished Jul 14 06:59:14 PM PDT 24
Peak memory 220008 kb
Host smart-64ce3eed-737d-4d57-96c6-8aa4426b19e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964967114 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.964967114
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.4074800017
Short name T648
Test name
Test status
Simulation time 35953162 ps
CPU time 0.81 seconds
Started Jul 14 06:59:06 PM PDT 24
Finished Jul 14 06:59:12 PM PDT 24
Peak memory 206912 kb
Host smart-6d5d0ef3-f770-453d-bb7f-2902f08bbfc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074800017 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.4074800017
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.1166613667
Short name T633
Test name
Test status
Simulation time 50721055 ps
CPU time 0.86 seconds
Started Jul 14 06:58:59 PM PDT 24
Finished Jul 14 06:59:03 PM PDT 24
Peak memory 216236 kb
Host smart-aac3defe-7ef4-4696-9f36-6b2daf654854
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166613667 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.1166613667
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.4175131469
Short name T214
Test name
Test status
Simulation time 37097799 ps
CPU time 1.25 seconds
Started Jul 14 06:59:00 PM PDT 24
Finished Jul 14 06:59:05 PM PDT 24
Peak memory 217024 kb
Host smart-14e7ff8d-860c-4bb8-8705-d27099142671
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175131469 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.4175131469
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.1434468428
Short name T976
Test name
Test status
Simulation time 26681704 ps
CPU time 0.93 seconds
Started Jul 14 06:58:59 PM PDT 24
Finished Jul 14 06:59:04 PM PDT 24
Peak memory 224060 kb
Host smart-c4a7ac5e-995c-44ec-a19e-7713a630a737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434468428 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1434468428
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.703884726
Short name T442
Test name
Test status
Simulation time 24221860 ps
CPU time 1.15 seconds
Started Jul 14 06:59:02 PM PDT 24
Finished Jul 14 06:59:08 PM PDT 24
Peak memory 220244 kb
Host smart-cd44e796-2cb2-4ebf-a6a9-d7fdcd3931d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703884726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.703884726
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.3742827893
Short name T54
Test name
Test status
Simulation time 31391187 ps
CPU time 0.95 seconds
Started Jul 14 06:59:00 PM PDT 24
Finished Jul 14 06:59:04 PM PDT 24
Peak memory 224340 kb
Host smart-796a5d87-632a-4dc2-a2d0-d3ef81502225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742827893 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3742827893
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.952207271
Short name T686
Test name
Test status
Simulation time 17206558 ps
CPU time 0.99 seconds
Started Jul 14 06:58:59 PM PDT 24
Finished Jul 14 06:59:04 PM PDT 24
Peak memory 215604 kb
Host smart-7ea0b6cc-a770-4470-9bd0-f6f2fcf496d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952207271 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.952207271
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.1851693099
Short name T836
Test name
Test status
Simulation time 415228988 ps
CPU time 4.62 seconds
Started Jul 14 06:59:00 PM PDT 24
Finished Jul 14 06:59:09 PM PDT 24
Peak memory 217488 kb
Host smart-0eaf8c91-a6f7-4e70-82b6-aecf7db0c0d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851693099 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1851693099
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.3568776684
Short name T96
Test name
Test status
Simulation time 41478993356 ps
CPU time 957.7 seconds
Started Jul 14 06:59:04 PM PDT 24
Finished Jul 14 07:15:06 PM PDT 24
Peak memory 223960 kb
Host smart-982a25b1-ff20-4a75-b063-f5f70e46a72f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568776684 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.3568776684
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.2591702875
Short name T255
Test name
Test status
Simulation time 56093582 ps
CPU time 1.08 seconds
Started Jul 14 06:59:10 PM PDT 24
Finished Jul 14 06:59:17 PM PDT 24
Peak memory 220956 kb
Host smart-2c6df712-8eca-4914-af17-e73a16f44d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591702875 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2591702875
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.3921038519
Short name T766
Test name
Test status
Simulation time 63089798 ps
CPU time 0.87 seconds
Started Jul 14 06:59:14 PM PDT 24
Finished Jul 14 06:59:19 PM PDT 24
Peak memory 207028 kb
Host smart-4fb09aaa-faa5-4b11-9e8e-93499dd0b412
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921038519 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.3921038519
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.4210730008
Short name T502
Test name
Test status
Simulation time 23126456 ps
CPU time 0.89 seconds
Started Jul 14 06:59:02 PM PDT 24
Finished Jul 14 06:59:07 PM PDT 24
Peak memory 216576 kb
Host smart-2d3cffa5-840c-47b2-93c1-9ba4c49bb81f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210730008 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.4210730008
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1140305593
Short name T71
Test name
Test status
Simulation time 64229629 ps
CPU time 1.14 seconds
Started Jul 14 06:58:58 PM PDT 24
Finished Jul 14 06:59:02 PM PDT 24
Peak memory 217564 kb
Host smart-4c1f57d7-c905-4ad4-a85f-3aeb6f8a4803
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140305593 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1140305593
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.3432864117
Short name T791
Test name
Test status
Simulation time 63863280 ps
CPU time 1.22 seconds
Started Jul 14 06:59:10 PM PDT 24
Finished Jul 14 06:59:17 PM PDT 24
Peak memory 230008 kb
Host smart-7bde9a08-4802-4b2f-b327-d6e7d0fafc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432864117 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3432864117
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.4258832924
Short name T332
Test name
Test status
Simulation time 46912966 ps
CPU time 1.26 seconds
Started Jul 14 06:58:58 PM PDT 24
Finished Jul 14 06:59:01 PM PDT 24
Peak memory 217512 kb
Host smart-1be0f37d-fd2f-4efd-af56-72c8fb79e539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258832924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.4258832924
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.61410140
Short name T29
Test name
Test status
Simulation time 43747732 ps
CPU time 0.8 seconds
Started Jul 14 06:59:04 PM PDT 24
Finished Jul 14 06:59:09 PM PDT 24
Peak memory 215832 kb
Host smart-e0d324f4-a97a-4254-8992-0d8e07cf2935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61410140 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.61410140
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.3088369267
Short name T965
Test name
Test status
Simulation time 19000176 ps
CPU time 1.02 seconds
Started Jul 14 06:59:11 PM PDT 24
Finished Jul 14 06:59:17 PM PDT 24
Peak memory 215448 kb
Host smart-5b448cd0-8728-4d07-9b39-4797e0d6a4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088369267 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.3088369267
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.1722039980
Short name T698
Test name
Test status
Simulation time 146249596 ps
CPU time 3.14 seconds
Started Jul 14 06:58:52 PM PDT 24
Finished Jul 14 06:58:58 PM PDT 24
Peak memory 217472 kb
Host smart-41b59e86-983e-4d23-a138-1e599855971a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722039980 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1722039980
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2806353002
Short name T511
Test name
Test status
Simulation time 26099545544 ps
CPU time 635.2 seconds
Started Jul 14 06:59:00 PM PDT 24
Finished Jul 14 07:09:40 PM PDT 24
Peak memory 223992 kb
Host smart-c792aff9-4a9e-4334-91c5-381a149b2257
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806353002 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.2806353002
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.3718734945
Short name T107
Test name
Test status
Simulation time 37071740 ps
CPU time 1.1 seconds
Started Jul 14 06:59:17 PM PDT 24
Finished Jul 14 06:59:21 PM PDT 24
Peak memory 219860 kb
Host smart-95c3241f-37f4-4fb6-9f6b-160f0591a269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718734945 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.3718734945
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.4207060229
Short name T783
Test name
Test status
Simulation time 26281371 ps
CPU time 0.94 seconds
Started Jul 14 06:58:56 PM PDT 24
Finished Jul 14 06:58:59 PM PDT 24
Peak memory 207000 kb
Host smart-559ad4c1-2a7a-4cf6-8ffc-8c3f31c431cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207060229 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.4207060229
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.26052480
Short name T212
Test name
Test status
Simulation time 28076023 ps
CPU time 0.85 seconds
Started Jul 14 06:59:04 PM PDT 24
Finished Jul 14 06:59:10 PM PDT 24
Peak memory 216488 kb
Host smart-7fc81744-cacc-400f-a865-646a4a90c7a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26052480 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.26052480
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.3657195781
Short name T683
Test name
Test status
Simulation time 86083448 ps
CPU time 0.98 seconds
Started Jul 14 06:59:05 PM PDT 24
Finished Jul 14 06:59:10 PM PDT 24
Peak memory 218624 kb
Host smart-9cd357b0-3143-4495-bd2e-47c75a39adde
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657195781 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.3657195781
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.929586773
Short name T210
Test name
Test status
Simulation time 25031553 ps
CPU time 0.93 seconds
Started Jul 14 06:58:56 PM PDT 24
Finished Jul 14 06:59:00 PM PDT 24
Peak memory 218956 kb
Host smart-a30d00bf-6b43-4db8-9574-f0e09b13c6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929586773 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.929586773
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.3608748911
Short name T340
Test name
Test status
Simulation time 160252164 ps
CPU time 1.47 seconds
Started Jul 14 06:59:32 PM PDT 24
Finished Jul 14 06:59:36 PM PDT 24
Peak memory 219388 kb
Host smart-6ac0ece2-ab1d-4bb7-90e7-82ae5ccadce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608748911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3608748911
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.1813966520
Short name T76
Test name
Test status
Simulation time 20907566 ps
CPU time 1.12 seconds
Started Jul 14 06:59:13 PM PDT 24
Finished Jul 14 06:59:19 PM PDT 24
Peak memory 215692 kb
Host smart-60851776-8748-40bc-87cd-58575f587da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813966520 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.1813966520
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.787778006
Short name T505
Test name
Test status
Simulation time 36753096 ps
CPU time 0.88 seconds
Started Jul 14 06:59:09 PM PDT 24
Finished Jul 14 06:59:16 PM PDT 24
Peak memory 215556 kb
Host smart-c50b6442-04b7-44f4-9824-ecf1e2556c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787778006 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.787778006
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.1980521907
Short name T676
Test name
Test status
Simulation time 1719667846 ps
CPU time 4 seconds
Started Jul 14 06:59:20 PM PDT 24
Finished Jul 14 06:59:26 PM PDT 24
Peak memory 217484 kb
Host smart-ff312af7-9bbe-4c01-988c-79881b21a310
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980521907 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1980521907
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.2894616693
Short name T573
Test name
Test status
Simulation time 29793512665 ps
CPU time 724.41 seconds
Started Jul 14 06:59:09 PM PDT 24
Finished Jul 14 07:11:19 PM PDT 24
Peak memory 224060 kb
Host smart-0e8ad0f4-dd6c-4b43-a2cc-92ba6fd0773f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894616693 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.2894616693
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.1889403227
Short name T190
Test name
Test status
Simulation time 89172384 ps
CPU time 1.2 seconds
Started Jul 14 06:59:11 PM PDT 24
Finished Jul 14 06:59:17 PM PDT 24
Peak memory 220436 kb
Host smart-aaf799d0-593a-4a09-8047-fc75cf718744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889403227 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.1889403227
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.1332955198
Short name T949
Test name
Test status
Simulation time 21529738 ps
CPU time 0.93 seconds
Started Jul 14 06:59:04 PM PDT 24
Finished Jul 14 06:59:10 PM PDT 24
Peak memory 215140 kb
Host smart-193bbac1-eb95-4cae-8de2-2409a074dd4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332955198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.1332955198
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.3082760024
Short name T249
Test name
Test status
Simulation time 23037845 ps
CPU time 0.85 seconds
Started Jul 14 06:59:25 PM PDT 24
Finished Jul 14 06:59:28 PM PDT 24
Peak memory 216352 kb
Host smart-af7a40c5-2936-4383-a5b0-36a594ad7cb0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082760024 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.3082760024
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.4256563535
Short name T201
Test name
Test status
Simulation time 63305044 ps
CPU time 1.2 seconds
Started Jul 14 06:59:01 PM PDT 24
Finished Jul 14 06:59:06 PM PDT 24
Peak memory 217268 kb
Host smart-1b0d0640-3426-4ff2-8540-6ba94462e63f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256563535 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.4256563535
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.3641403755
Short name T430
Test name
Test status
Simulation time 26553632 ps
CPU time 0.96 seconds
Started Jul 14 06:59:02 PM PDT 24
Finished Jul 14 06:59:07 PM PDT 24
Peak memory 219864 kb
Host smart-cff062d3-2d84-4ad3-8d95-e6425fd2f13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641403755 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3641403755
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.3154736909
Short name T894
Test name
Test status
Simulation time 42111809 ps
CPU time 1.34 seconds
Started Jul 14 06:59:28 PM PDT 24
Finished Jul 14 06:59:33 PM PDT 24
Peak memory 219156 kb
Host smart-0dad6bab-306d-4fc7-9d53-060cd9b6daa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154736909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3154736909
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.4007218758
Short name T115
Test name
Test status
Simulation time 42119776 ps
CPU time 0.88 seconds
Started Jul 14 06:59:01 PM PDT 24
Finished Jul 14 06:59:06 PM PDT 24
Peak memory 215996 kb
Host smart-1fa284bc-85a6-4a16-b877-85f06adcfe50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007218758 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.4007218758
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.924691338
Short name T717
Test name
Test status
Simulation time 15491474 ps
CPU time 0.98 seconds
Started Jul 14 06:59:04 PM PDT 24
Finished Jul 14 06:59:10 PM PDT 24
Peak memory 215572 kb
Host smart-72e38c17-dcd8-4435-8ec7-92b3b0e21633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924691338 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.924691338
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.705220258
Short name T243
Test name
Test status
Simulation time 210993595 ps
CPU time 4.18 seconds
Started Jul 14 06:59:01 PM PDT 24
Finished Jul 14 06:59:09 PM PDT 24
Peak memory 217560 kb
Host smart-04761124-282d-4e59-866f-e11a2f22b7f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705220258 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.705220258
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.159039855
Short name T664
Test name
Test status
Simulation time 124183942781 ps
CPU time 552.79 seconds
Started Jul 14 06:59:23 PM PDT 24
Finished Jul 14 07:08:37 PM PDT 24
Peak memory 221820 kb
Host smart-fb8e3db2-66f3-425c-8f87-f81b4c0f4ba4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159039855 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.159039855
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.1980617952
Short name T360
Test name
Test status
Simulation time 22654196 ps
CPU time 1.16 seconds
Started Jul 14 06:58:08 PM PDT 24
Finished Jul 14 06:58:16 PM PDT 24
Peak memory 221040 kb
Host smart-16d60efa-7fa3-4936-bdea-568df26af001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980617952 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.1980617952
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.866601106
Short name T547
Test name
Test status
Simulation time 14353671 ps
CPU time 0.98 seconds
Started Jul 14 06:58:07 PM PDT 24
Finished Jul 14 06:58:13 PM PDT 24
Peak memory 206988 kb
Host smart-b6d4371b-0a01-4328-9233-26501bdd5490
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866601106 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.866601106
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.4068968789
Short name T800
Test name
Test status
Simulation time 18910426 ps
CPU time 0.87 seconds
Started Jul 14 06:58:20 PM PDT 24
Finished Jul 14 06:58:26 PM PDT 24
Peak memory 216456 kb
Host smart-2067c17e-2a32-437e-8be7-d42eafaafea8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068968789 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.4068968789
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.880832388
Short name T541
Test name
Test status
Simulation time 50717511 ps
CPU time 1.15 seconds
Started Jul 14 06:58:03 PM PDT 24
Finished Jul 14 06:58:12 PM PDT 24
Peak memory 217256 kb
Host smart-c2c43038-8b78-42aa-9272-96de98cc7861
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880832388 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_dis
able_auto_req_mode.880832388
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.61448750
Short name T170
Test name
Test status
Simulation time 43840367 ps
CPU time 0.95 seconds
Started Jul 14 06:58:09 PM PDT 24
Finished Jul 14 06:58:16 PM PDT 24
Peak memory 224072 kb
Host smart-b42f1b46-3024-4545-888f-89d476b2e476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61448750 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.61448750
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.221367066
Short name T745
Test name
Test status
Simulation time 46716937 ps
CPU time 1.6 seconds
Started Jul 14 06:58:01 PM PDT 24
Finished Jul 14 06:58:03 PM PDT 24
Peak memory 220200 kb
Host smart-a0fb7e0d-12bb-4e90-b97f-d03c673b7b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221367066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.221367066
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.2048295208
Short name T459
Test name
Test status
Simulation time 22113040 ps
CPU time 1.06 seconds
Started Jul 14 06:58:14 PM PDT 24
Finished Jul 14 06:58:22 PM PDT 24
Peak memory 215856 kb
Host smart-1dd5f382-268e-4bf3-b0b6-3944b9497059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048295208 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.2048295208
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.2584861575
Short name T23
Test name
Test status
Simulation time 21181394 ps
CPU time 0.9 seconds
Started Jul 14 06:58:01 PM PDT 24
Finished Jul 14 06:58:03 PM PDT 24
Peak memory 207384 kb
Host smart-cde40007-e606-455d-bd21-da7a9b93049b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584861575 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2584861575
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.2408067982
Short name T885
Test name
Test status
Simulation time 63674393 ps
CPU time 0.98 seconds
Started Jul 14 06:58:03 PM PDT 24
Finished Jul 14 06:58:07 PM PDT 24
Peak memory 215620 kb
Host smart-aa14fa31-0a56-4554-854d-fbfc98437d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408067982 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.2408067982
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.496701417
Short name T545
Test name
Test status
Simulation time 485797629 ps
CPU time 3.1 seconds
Started Jul 14 06:57:58 PM PDT 24
Finished Jul 14 06:58:02 PM PDT 24
Peak memory 217384 kb
Host smart-91e785a5-039c-4204-bab2-e4555dcfac84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496701417 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.496701417
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.3756252276
Short name T785
Test name
Test status
Simulation time 50106426831 ps
CPU time 1081.85 seconds
Started Jul 14 06:58:00 PM PDT 24
Finished Jul 14 07:16:03 PM PDT 24
Peak memory 221132 kb
Host smart-9dda9434-fcb6-43f8-848f-3c2b487a6b2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756252276 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.3756252276
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.2078480848
Short name T79
Test name
Test status
Simulation time 30834104 ps
CPU time 0.85 seconds
Started Jul 14 06:59:04 PM PDT 24
Finished Jul 14 06:59:10 PM PDT 24
Peak memory 218632 kb
Host smart-fb92a38c-b3ff-4178-a4cd-23dbf823c6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078480848 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.2078480848
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.577101300
Short name T377
Test name
Test status
Simulation time 95650130 ps
CPU time 1.31 seconds
Started Jul 14 06:59:10 PM PDT 24
Finished Jul 14 06:59:17 PM PDT 24
Peak memory 219332 kb
Host smart-406adb6b-b833-46d6-b2f4-ce1baad87f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577101300 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.577101300
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.1872631902
Short name T882
Test name
Test status
Simulation time 128215066 ps
CPU time 1.2 seconds
Started Jul 14 06:59:00 PM PDT 24
Finished Jul 14 06:59:05 PM PDT 24
Peak memory 221644 kb
Host smart-0ef5e903-750b-44fd-a2ac-55119802391e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872631902 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.1872631902
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.2014128495
Short name T958
Test name
Test status
Simulation time 52096064 ps
CPU time 1.07 seconds
Started Jul 14 06:59:21 PM PDT 24
Finished Jul 14 06:59:24 PM PDT 24
Peak memory 224204 kb
Host smart-be2af0cd-cd36-4973-98c0-e92ace940027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014128495 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.2014128495
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.2158553190
Short name T370
Test name
Test status
Simulation time 49896702 ps
CPU time 1.55 seconds
Started Jul 14 06:59:20 PM PDT 24
Finished Jul 14 06:59:23 PM PDT 24
Peak memory 219876 kb
Host smart-12c82820-c40e-4c47-b2f0-870ad09a9d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158553190 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.2158553190
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.10573841
Short name T310
Test name
Test status
Simulation time 62736936 ps
CPU time 1.1 seconds
Started Jul 14 06:59:04 PM PDT 24
Finished Jul 14 06:59:10 PM PDT 24
Peak memory 219988 kb
Host smart-8cb12986-6202-4b94-9d85-6e53313b243d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10573841 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.10573841
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.3577567846
Short name T902
Test name
Test status
Simulation time 86720155 ps
CPU time 0.93 seconds
Started Jul 14 06:59:16 PM PDT 24
Finished Jul 14 06:59:20 PM PDT 24
Peak memory 219892 kb
Host smart-e28ea15e-83bd-4943-8c9d-784d02f29391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577567846 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.3577567846
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.2762165490
Short name T562
Test name
Test status
Simulation time 169590095 ps
CPU time 1.43 seconds
Started Jul 14 06:59:12 PM PDT 24
Finished Jul 14 06:59:18 PM PDT 24
Peak memory 219468 kb
Host smart-b6033e3c-9238-49e0-9f96-1872dc900186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762165490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.2762165490
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.2417413158
Short name T218
Test name
Test status
Simulation time 105719794 ps
CPU time 1.4 seconds
Started Jul 14 06:59:00 PM PDT 24
Finished Jul 14 06:59:05 PM PDT 24
Peak memory 220956 kb
Host smart-85898682-5ce0-4f64-9e3f-3a6871034586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417413158 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.2417413158
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.644004650
Short name T531
Test name
Test status
Simulation time 58905303 ps
CPU time 1.39 seconds
Started Jul 14 06:58:59 PM PDT 24
Finished Jul 14 06:59:03 PM PDT 24
Peak memory 225808 kb
Host smart-c745fc00-05a3-4b07-b7c3-46ee2f7601f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644004650 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.644004650
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.3575633483
Short name T660
Test name
Test status
Simulation time 45311422 ps
CPU time 1.4 seconds
Started Jul 14 06:59:28 PM PDT 24
Finished Jul 14 06:59:34 PM PDT 24
Peak memory 220220 kb
Host smart-5a944f4b-625f-4a6a-bc84-68fbc0ac3483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575633483 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.3575633483
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.2692360249
Short name T437
Test name
Test status
Simulation time 79429901 ps
CPU time 1.12 seconds
Started Jul 14 06:59:22 PM PDT 24
Finished Jul 14 06:59:25 PM PDT 24
Peak memory 220140 kb
Host smart-912f0e39-3fe2-4ef6-b168-977a44dd0ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692360249 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.2692360249
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_genbits.3994001688
Short name T939
Test name
Test status
Simulation time 54335678 ps
CPU time 1.08 seconds
Started Jul 14 06:59:00 PM PDT 24
Finished Jul 14 06:59:05 PM PDT 24
Peak memory 217732 kb
Host smart-9f976707-f5ae-4f87-9a82-92ea97f676e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994001688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.3994001688
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.574301509
Short name T149
Test name
Test status
Simulation time 115528511 ps
CPU time 1.06 seconds
Started Jul 14 06:59:00 PM PDT 24
Finished Jul 14 06:59:10 PM PDT 24
Peak memory 220812 kb
Host smart-3470f30c-7771-4622-9a6f-211782c07725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574301509 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.574301509
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.3244839894
Short name T63
Test name
Test status
Simulation time 48658547 ps
CPU time 0.81 seconds
Started Jul 14 06:59:13 PM PDT 24
Finished Jul 14 06:59:18 PM PDT 24
Peak memory 218308 kb
Host smart-a189c453-73be-4739-9095-2502363edeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244839894 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.3244839894
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.169940745
Short name T357
Test name
Test status
Simulation time 59943833 ps
CPU time 2.48 seconds
Started Jul 14 06:59:12 PM PDT 24
Finished Jul 14 06:59:20 PM PDT 24
Peak memory 220280 kb
Host smart-55c3260b-3d73-4ba2-bf62-2c516beb74c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169940745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.169940745
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.3943472848
Short name T308
Test name
Test status
Simulation time 47017008 ps
CPU time 1.22 seconds
Started Jul 14 06:59:02 PM PDT 24
Finished Jul 14 06:59:08 PM PDT 24
Peak memory 218912 kb
Host smart-1b43996a-469c-4bcc-9a61-0768056c06d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943472848 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.3943472848
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.4286426434
Short name T6
Test name
Test status
Simulation time 34767519 ps
CPU time 1.07 seconds
Started Jul 14 06:59:22 PM PDT 24
Finished Jul 14 06:59:24 PM PDT 24
Peak memory 229864 kb
Host smart-c4923e5f-f0f6-479f-952d-d2049726504b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286426434 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.4286426434
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.3351184447
Short name T697
Test name
Test status
Simulation time 31792490 ps
CPU time 0.97 seconds
Started Jul 14 06:59:39 PM PDT 24
Finished Jul 14 06:59:43 PM PDT 24
Peak memory 217668 kb
Host smart-147d75c0-adfb-46da-b59a-5a409084b355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351184447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.3351184447
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.2791276900
Short name T598
Test name
Test status
Simulation time 168364108 ps
CPU time 1.17 seconds
Started Jul 14 06:59:23 PM PDT 24
Finished Jul 14 06:59:25 PM PDT 24
Peak memory 218620 kb
Host smart-754ccbd1-7504-41e9-ad71-64d7f0cfd386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791276900 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.2791276900
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.83898101
Short name T772
Test name
Test status
Simulation time 20483768 ps
CPU time 1.12 seconds
Started Jul 14 06:59:05 PM PDT 24
Finished Jul 14 06:59:11 PM PDT 24
Peak memory 218764 kb
Host smart-a0dc1152-152b-467e-bc73-7f702dac676c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83898101 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.83898101
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.2908613289
Short name T621
Test name
Test status
Simulation time 46680840 ps
CPU time 1.52 seconds
Started Jul 14 06:59:00 PM PDT 24
Finished Jul 14 06:59:05 PM PDT 24
Peak memory 218812 kb
Host smart-6ce2f1e2-80ec-4f83-9401-fe7a3ded46b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908613289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2908613289
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.1736322022
Short name T499
Test name
Test status
Simulation time 25907378 ps
CPU time 1.22 seconds
Started Jul 14 06:59:02 PM PDT 24
Finished Jul 14 06:59:08 PM PDT 24
Peak memory 219928 kb
Host smart-cdf00ac8-7740-4f52-8b00-660ea26bbabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736322022 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.1736322022
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.1015351036
Short name T213
Test name
Test status
Simulation time 24114580 ps
CPU time 0.91 seconds
Started Jul 14 06:59:38 PM PDT 24
Finished Jul 14 06:59:42 PM PDT 24
Peak memory 218848 kb
Host smart-fc690f95-ab2d-40d7-893f-ce5635caf245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015351036 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.1015351036
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.3934785031
Short name T65
Test name
Test status
Simulation time 42606765 ps
CPU time 1.36 seconds
Started Jul 14 06:58:59 PM PDT 24
Finished Jul 14 06:59:03 PM PDT 24
Peak memory 217552 kb
Host smart-860a5bcf-8a16-4960-8ba3-937a74e90f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934785031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.3934785031
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.754417942
Short name T815
Test name
Test status
Simulation time 74811905 ps
CPU time 1.17 seconds
Started Jul 14 06:59:00 PM PDT 24
Finished Jul 14 06:59:05 PM PDT 24
Peak memory 218744 kb
Host smart-0693a02d-ab06-4856-a9ce-6314152c3019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754417942 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.754417942
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.2334708894
Short name T932
Test name
Test status
Simulation time 19624435 ps
CPU time 0.97 seconds
Started Jul 14 06:58:59 PM PDT 24
Finished Jul 14 06:59:03 PM PDT 24
Peak memory 218884 kb
Host smart-f54f3146-4190-4db4-8bae-e5fb08554724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334708894 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.2334708894
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.2321018004
Short name T37
Test name
Test status
Simulation time 30283001 ps
CPU time 1.29 seconds
Started Jul 14 06:59:25 PM PDT 24
Finished Jul 14 06:59:29 PM PDT 24
Peak memory 217772 kb
Host smart-f31672fe-f7ed-4464-ba97-7ef4bebd4e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321018004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.2321018004
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.839745304
Short name T617
Test name
Test status
Simulation time 30766782 ps
CPU time 1.34 seconds
Started Jul 14 06:58:03 PM PDT 24
Finished Jul 14 06:58:07 PM PDT 24
Peak memory 215960 kb
Host smart-91e2ebc9-8621-43d0-abb7-dadee167d579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839745304 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.839745304
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.1082961168
Short name T832
Test name
Test status
Simulation time 67159953 ps
CPU time 1.06 seconds
Started Jul 14 06:57:56 PM PDT 24
Finished Jul 14 06:57:59 PM PDT 24
Peak memory 215260 kb
Host smart-8f055fc6-9893-4d0f-ba26-ba8561b34b05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082961168 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.1082961168
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.1311637787
Short name T474
Test name
Test status
Simulation time 22923328 ps
CPU time 0.89 seconds
Started Jul 14 06:58:14 PM PDT 24
Finished Jul 14 06:58:22 PM PDT 24
Peak memory 216224 kb
Host smart-884b14c2-f60c-44b1-a3d5-d83ffa3febd3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311637787 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.1311637787
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.3974351186
Short name T140
Test name
Test status
Simulation time 24537781 ps
CPU time 1.12 seconds
Started Jul 14 06:58:01 PM PDT 24
Finished Jul 14 06:58:04 PM PDT 24
Peak memory 218832 kb
Host smart-d386a4a1-69a7-434e-9bf0-95556c613014
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974351186 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.3974351186
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.1875693682
Short name T166
Test name
Test status
Simulation time 37760091 ps
CPU time 0.96 seconds
Started Jul 14 06:58:00 PM PDT 24
Finished Jul 14 06:58:02 PM PDT 24
Peak memory 218588 kb
Host smart-4e4221a0-e6eb-45db-81a1-3f472e4a9e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875693682 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.1875693682
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.808856313
Short name T817
Test name
Test status
Simulation time 167601336 ps
CPU time 2.85 seconds
Started Jul 14 06:57:59 PM PDT 24
Finished Jul 14 06:58:03 PM PDT 24
Peak memory 220344 kb
Host smart-154a2243-e947-4688-b78c-a2294e1193f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808856313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.808856313
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.1972852979
Short name T380
Test name
Test status
Simulation time 33380437 ps
CPU time 0.88 seconds
Started Jul 14 06:58:08 PM PDT 24
Finished Jul 14 06:58:15 PM PDT 24
Peak memory 215608 kb
Host smart-bd393684-4a36-482a-930c-2a092b34cc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972852979 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.1972852979
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.80762514
Short name T622
Test name
Test status
Simulation time 16449142 ps
CPU time 1.03 seconds
Started Jul 14 06:58:02 PM PDT 24
Finished Jul 14 06:58:05 PM PDT 24
Peak memory 207348 kb
Host smart-8914ebee-e206-4c74-8978-b59ac752c8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80762514 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.80762514
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.2104080904
Short name T867
Test name
Test status
Simulation time 30284452 ps
CPU time 0.9 seconds
Started Jul 14 06:58:11 PM PDT 24
Finished Jul 14 06:58:19 PM PDT 24
Peak memory 215428 kb
Host smart-da1db259-360b-4f88-869f-631277930c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104080904 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.2104080904
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.1166203088
Short name T445
Test name
Test status
Simulation time 335156852 ps
CPU time 3.91 seconds
Started Jul 14 06:58:15 PM PDT 24
Finished Jul 14 06:58:26 PM PDT 24
Peak memory 218704 kb
Host smart-7250cfbc-1d3d-4f54-b8d1-8609272b6a52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166203088 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.1166203088
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.3328975641
Short name T640
Test name
Test status
Simulation time 230386653878 ps
CPU time 1045.98 seconds
Started Jul 14 06:57:59 PM PDT 24
Finished Jul 14 07:15:26 PM PDT 24
Peak memory 222852 kb
Host smart-eb59fe12-0cef-47cb-a09d-5eab9255099c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328975641 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.3328975641
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.2226081782
Short name T883
Test name
Test status
Simulation time 28900082 ps
CPU time 1.2 seconds
Started Jul 14 06:59:21 PM PDT 24
Finished Jul 14 06:59:23 PM PDT 24
Peak memory 221076 kb
Host smart-3e1d08f4-f762-4265-a02b-adfde9b2e13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226081782 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.2226081782
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_genbits.3446057805
Short name T89
Test name
Test status
Simulation time 109889843 ps
CPU time 1.5 seconds
Started Jul 14 06:59:09 PM PDT 24
Finished Jul 14 06:59:16 PM PDT 24
Peak memory 217572 kb
Host smart-0c715747-0bbb-4672-9af8-be14d6cf0df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446057805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3446057805
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.1099926602
Short name T722
Test name
Test status
Simulation time 27327975 ps
CPU time 1.17 seconds
Started Jul 14 06:58:59 PM PDT 24
Finished Jul 14 06:59:04 PM PDT 24
Peak memory 219872 kb
Host smart-072314cd-a91b-4819-b17a-058dd6b7d023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099926602 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.1099926602
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.1315614101
Short name T168
Test name
Test status
Simulation time 19827320 ps
CPU time 1.03 seconds
Started Jul 14 06:59:01 PM PDT 24
Finished Jul 14 06:59:06 PM PDT 24
Peak memory 224232 kb
Host smart-34f9cfb4-9fce-4e0a-939d-40eb038cb579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315614101 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1315614101
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.1200651914
Short name T13
Test name
Test status
Simulation time 55222679 ps
CPU time 1.19 seconds
Started Jul 14 06:58:59 PM PDT 24
Finished Jul 14 06:59:04 PM PDT 24
Peak memory 220296 kb
Host smart-6c178298-1ce0-40f8-970f-cdf3915003f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200651914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.1200651914
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.1680476478
Short name T403
Test name
Test status
Simulation time 25392051 ps
CPU time 1.22 seconds
Started Jul 14 06:59:12 PM PDT 24
Finished Jul 14 06:59:19 PM PDT 24
Peak memory 220300 kb
Host smart-f06bd425-2d50-4ae5-9e9d-3b1e8e291884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680476478 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.1680476478
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.4059219519
Short name T576
Test name
Test status
Simulation time 33044940 ps
CPU time 0.99 seconds
Started Jul 14 06:59:05 PM PDT 24
Finished Jul 14 06:59:11 PM PDT 24
Peak memory 224256 kb
Host smart-796aa40a-ddfd-4a58-9c12-a13407f6f957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059219519 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.4059219519
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.1095351245
Short name T319
Test name
Test status
Simulation time 84055575 ps
CPU time 1.4 seconds
Started Jul 14 06:59:23 PM PDT 24
Finished Jul 14 06:59:26 PM PDT 24
Peak memory 219408 kb
Host smart-34a5c817-e7e4-4686-9c23-119ca34b96d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095351245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.1095351245
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.3423940357
Short name T577
Test name
Test status
Simulation time 106519603 ps
CPU time 1.1 seconds
Started Jul 14 06:59:37 PM PDT 24
Finished Jul 14 06:59:41 PM PDT 24
Peak memory 215996 kb
Host smart-3d4d728d-a032-4c12-bd6a-8a6e09c252be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423940357 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.3423940357
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.1032878947
Short name T144
Test name
Test status
Simulation time 31154978 ps
CPU time 1.02 seconds
Started Jul 14 06:59:09 PM PDT 24
Finished Jul 14 06:59:19 PM PDT 24
Peak memory 218712 kb
Host smart-d836a443-b7f7-4e6c-9766-1581e979d839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032878947 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1032878947
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.2216132142
Short name T681
Test name
Test status
Simulation time 112857753 ps
CPU time 1.33 seconds
Started Jul 14 06:59:05 PM PDT 24
Finished Jul 14 06:59:12 PM PDT 24
Peak memory 219332 kb
Host smart-7e8865e9-4dc6-4051-b447-12ec127dcf9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216132142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.2216132142
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.1609877565
Short name T861
Test name
Test status
Simulation time 36154949 ps
CPU time 1.09 seconds
Started Jul 14 06:58:59 PM PDT 24
Finished Jul 14 06:59:03 PM PDT 24
Peak memory 220156 kb
Host smart-e6f791c0-22ad-4e6c-a078-20afcbe24e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609877565 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.1609877565
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.2280320162
Short name T7
Test name
Test status
Simulation time 46994631 ps
CPU time 1.08 seconds
Started Jul 14 06:59:19 PM PDT 24
Finished Jul 14 06:59:22 PM PDT 24
Peak memory 229836 kb
Host smart-abf6e5e5-8286-4eb8-a4a4-e6230f8183cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280320162 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.2280320162
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.2671428081
Short name T20
Test name
Test status
Simulation time 38575133 ps
CPU time 1.61 seconds
Started Jul 14 06:59:27 PM PDT 24
Finished Jul 14 06:59:32 PM PDT 24
Peak memory 218880 kb
Host smart-7360226c-0ca1-4daa-bc0a-a20f84e99802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671428081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2671428081
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.2187542791
Short name T794
Test name
Test status
Simulation time 48003832 ps
CPU time 1.09 seconds
Started Jul 14 06:59:26 PM PDT 24
Finished Jul 14 06:59:29 PM PDT 24
Peak memory 220308 kb
Host smart-7c683234-5773-4421-a6f9-b9c4d92d6665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187542791 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.2187542791
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.2845003159
Short name T151
Test name
Test status
Simulation time 29229495 ps
CPU time 1.12 seconds
Started Jul 14 06:59:06 PM PDT 24
Finished Jul 14 06:59:12 PM PDT 24
Peak memory 220012 kb
Host smart-00dd7cc1-bd6d-48f0-9520-14d3873a14de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845003159 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.2845003159
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.3138333714
Short name T339
Test name
Test status
Simulation time 50885054 ps
CPU time 1.77 seconds
Started Jul 14 06:58:57 PM PDT 24
Finished Jul 14 06:59:01 PM PDT 24
Peak memory 218804 kb
Host smart-5e2e1549-ee6e-4cc0-b61b-bc59c523b840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138333714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.3138333714
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.3040399772
Short name T390
Test name
Test status
Simulation time 23177115 ps
CPU time 1.17 seconds
Started Jul 14 06:58:57 PM PDT 24
Finished Jul 14 06:59:00 PM PDT 24
Peak memory 220748 kb
Host smart-263578ec-4547-4e14-9500-20f86f11d9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040399772 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.3040399772
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.553284689
Short name T53
Test name
Test status
Simulation time 29714173 ps
CPU time 0.96 seconds
Started Jul 14 06:59:22 PM PDT 24
Finished Jul 14 06:59:24 PM PDT 24
Peak memory 224048 kb
Host smart-22eebc6f-4a59-48a3-a201-9a25c30599e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553284689 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.553284689
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/67.edn_alert.1932848165
Short name T615
Test name
Test status
Simulation time 73105342 ps
CPU time 1.16 seconds
Started Jul 14 06:59:02 PM PDT 24
Finished Jul 14 06:59:07 PM PDT 24
Peak memory 218804 kb
Host smart-977199be-ffa5-42cc-bc4b-8754ac350a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932848165 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.1932848165
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.3029399368
Short name T504
Test name
Test status
Simulation time 28548829 ps
CPU time 0.85 seconds
Started Jul 14 06:59:23 PM PDT 24
Finished Jul 14 06:59:25 PM PDT 24
Peak memory 218904 kb
Host smart-49ae17de-4634-4d6c-ac2e-6dcfda98495c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029399368 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.3029399368
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.3777623399
Short name T536
Test name
Test status
Simulation time 144807050 ps
CPU time 1.27 seconds
Started Jul 14 06:59:25 PM PDT 24
Finished Jul 14 06:59:29 PM PDT 24
Peak memory 219060 kb
Host smart-663aa9a6-5c4a-4ad4-b533-5a24f71d3242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777623399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3777623399
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.3064282399
Short name T824
Test name
Test status
Simulation time 69940212 ps
CPU time 1.11 seconds
Started Jul 14 06:59:27 PM PDT 24
Finished Jul 14 06:59:31 PM PDT 24
Peak memory 218888 kb
Host smart-6e3ca699-4828-4e66-814c-4839b0724d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064282399 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.3064282399
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.3446381968
Short name T145
Test name
Test status
Simulation time 33989402 ps
CPU time 1.34 seconds
Started Jul 14 06:59:05 PM PDT 24
Finished Jul 14 06:59:11 PM PDT 24
Peak memory 225776 kb
Host smart-f4117d17-cfdb-48b9-b257-2f00cb1209ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446381968 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.3446381968
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.182125422
Short name T327
Test name
Test status
Simulation time 58014909 ps
CPU time 1.1 seconds
Started Jul 14 06:59:06 PM PDT 24
Finished Jul 14 06:59:13 PM PDT 24
Peak memory 217588 kb
Host smart-b51207df-36f6-41ff-8098-b6171993bfce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182125422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.182125422
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.3405085728
Short name T774
Test name
Test status
Simulation time 25823227 ps
CPU time 1.21 seconds
Started Jul 14 06:59:00 PM PDT 24
Finished Jul 14 06:59:06 PM PDT 24
Peak memory 219952 kb
Host smart-c7b95968-dcc0-493d-b84a-de1c485f46ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405085728 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.3405085728
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.1357983498
Short name T171
Test name
Test status
Simulation time 27851724 ps
CPU time 1 seconds
Started Jul 14 06:59:02 PM PDT 24
Finished Jul 14 06:59:08 PM PDT 24
Peak memory 218464 kb
Host smart-53163247-4d36-423a-9566-776ef1c61dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357983498 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.1357983498
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.444849261
Short name T522
Test name
Test status
Simulation time 51162084 ps
CPU time 1.42 seconds
Started Jul 14 06:59:27 PM PDT 24
Finished Jul 14 06:59:32 PM PDT 24
Peak memory 217744 kb
Host smart-5179e05e-f9c1-48b6-9439-43f98948e49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444849261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.444849261
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.950590367
Short name T597
Test name
Test status
Simulation time 46097762 ps
CPU time 1.13 seconds
Started Jul 14 06:58:08 PM PDT 24
Finished Jul 14 06:58:14 PM PDT 24
Peak memory 220180 kb
Host smart-d2f35363-fbfb-4f70-b4a4-7e145327b3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950590367 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.950590367
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.3565319775
Short name T418
Test name
Test status
Simulation time 40891467 ps
CPU time 0.9 seconds
Started Jul 14 06:58:06 PM PDT 24
Finished Jul 14 06:58:11 PM PDT 24
Peak memory 215160 kb
Host smart-6200fc14-c909-414f-b11e-3e876523f3a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565319775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.3565319775
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.4259263249
Short name T88
Test name
Test status
Simulation time 17667512 ps
CPU time 0.93 seconds
Started Jul 14 06:58:12 PM PDT 24
Finished Jul 14 06:58:20 PM PDT 24
Peak memory 215924 kb
Host smart-18b89bc7-0951-4eab-9a1c-a1f5692ccbbc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259263249 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.4259263249
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.3914817861
Short name T67
Test name
Test status
Simulation time 102199292 ps
CPU time 0.98 seconds
Started Jul 14 06:58:08 PM PDT 24
Finished Jul 14 06:58:14 PM PDT 24
Peak memory 217120 kb
Host smart-7725af29-4c34-4011-bcd7-5caeb24f73e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914817861 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.3914817861
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.1574863273
Short name T125
Test name
Test status
Simulation time 25494332 ps
CPU time 1.01 seconds
Started Jul 14 06:58:11 PM PDT 24
Finished Jul 14 06:58:19 PM PDT 24
Peak memory 219900 kb
Host smart-17857283-b681-4417-be76-d2b4673295ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574863273 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.1574863273
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.1881876610
Short name T475
Test name
Test status
Simulation time 46069993 ps
CPU time 1.11 seconds
Started Jul 14 06:58:02 PM PDT 24
Finished Jul 14 06:58:05 PM PDT 24
Peak memory 217584 kb
Host smart-bb33f560-033e-4132-a9fd-6256b0b6c4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881876610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1881876610
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_smoke.1623385812
Short name T837
Test name
Test status
Simulation time 65874623 ps
CPU time 0.9 seconds
Started Jul 14 06:58:30 PM PDT 24
Finished Jul 14 06:58:32 PM PDT 24
Peak memory 215536 kb
Host smart-5f9643dd-b322-4180-a3fc-a85a93071476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623385812 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1623385812
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.66298589
Short name T979
Test name
Test status
Simulation time 50220902 ps
CPU time 1.16 seconds
Started Jul 14 06:58:10 PM PDT 24
Finished Jul 14 06:58:18 PM PDT 24
Peak memory 215612 kb
Host smart-98795192-911d-4651-bd79-09136ad25faf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66298589 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.66298589
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.4230407678
Short name T593
Test name
Test status
Simulation time 373814657839 ps
CPU time 907.96 seconds
Started Jul 14 06:58:16 PM PDT 24
Finished Jul 14 07:13:31 PM PDT 24
Peak memory 223224 kb
Host smart-aa0a806d-6338-42e1-9069-c1f9e7989692
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230407678 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.4230407678
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.2366511434
Short name T134
Test name
Test status
Simulation time 20064921 ps
CPU time 1.24 seconds
Started Jul 14 06:59:03 PM PDT 24
Finished Jul 14 06:59:09 PM PDT 24
Peak memory 229944 kb
Host smart-834309d3-e472-435d-bbe7-705491b7bc9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366511434 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.2366511434
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.3560001999
Short name T721
Test name
Test status
Simulation time 135080395 ps
CPU time 1.23 seconds
Started Jul 14 06:59:17 PM PDT 24
Finished Jul 14 06:59:21 PM PDT 24
Peak memory 220404 kb
Host smart-e92e400b-5583-4f0e-baf9-23dcea98a89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560001999 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3560001999
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.4288780180
Short name T695
Test name
Test status
Simulation time 27343606 ps
CPU time 1.25 seconds
Started Jul 14 06:59:47 PM PDT 24
Finished Jul 14 06:59:50 PM PDT 24
Peak memory 218944 kb
Host smart-1b91378a-e3ce-4b3c-bd70-84ebe8aad1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288780180 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.4288780180
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.69815095
Short name T469
Test name
Test status
Simulation time 45343070 ps
CPU time 0.81 seconds
Started Jul 14 06:59:19 PM PDT 24
Finished Jul 14 06:59:21 PM PDT 24
Peak memory 218368 kb
Host smart-caa35bd1-c3de-48e4-ac37-16475ee42fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69815095 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.69815095
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.3492183585
Short name T978
Test name
Test status
Simulation time 45950384 ps
CPU time 1.64 seconds
Started Jul 14 06:59:00 PM PDT 24
Finished Jul 14 06:59:06 PM PDT 24
Peak memory 217688 kb
Host smart-ae11b2b4-33ac-4eb9-b2e1-4e5f94219fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492183585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.3492183585
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.3180647143
Short name T822
Test name
Test status
Simulation time 24195237 ps
CPU time 1.16 seconds
Started Jul 14 06:59:29 PM PDT 24
Finished Jul 14 06:59:34 PM PDT 24
Peak memory 219180 kb
Host smart-79e381b5-0c2b-4d19-9c56-a8717125a9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180647143 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.3180647143
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.1151020305
Short name T587
Test name
Test status
Simulation time 209996080 ps
CPU time 1.04 seconds
Started Jul 14 06:59:23 PM PDT 24
Finished Jul 14 06:59:26 PM PDT 24
Peak memory 219892 kb
Host smart-21097df4-76c0-4af1-96f8-b0a29a098bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151020305 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.1151020305
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.3829153973
Short name T423
Test name
Test status
Simulation time 46315758 ps
CPU time 1.24 seconds
Started Jul 14 06:59:09 PM PDT 24
Finished Jul 14 06:59:15 PM PDT 24
Peak memory 218864 kb
Host smart-10d34562-be1f-4e69-9414-43f4f9b32d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829153973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.3829153973
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.2769014002
Short name T716
Test name
Test status
Simulation time 22612939 ps
CPU time 1.16 seconds
Started Jul 14 06:59:23 PM PDT 24
Finished Jul 14 06:59:26 PM PDT 24
Peak memory 218716 kb
Host smart-3e3a86ec-0b2c-427c-9d9d-dc99d88fcf73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769014002 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.2769014002
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.207171692
Short name T192
Test name
Test status
Simulation time 19175558 ps
CPU time 1.15 seconds
Started Jul 14 06:59:59 PM PDT 24
Finished Jul 14 07:00:09 PM PDT 24
Peak memory 224172 kb
Host smart-a6bea0de-9d84-4702-bb09-88ecedbf07a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207171692 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.207171692
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.4228967827
Short name T713
Test name
Test status
Simulation time 50544154 ps
CPU time 1.17 seconds
Started Jul 14 06:59:23 PM PDT 24
Finished Jul 14 06:59:26 PM PDT 24
Peak memory 217560 kb
Host smart-d5c5503d-41da-423c-bdff-b1695d169324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228967827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.4228967827
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.2751862156
Short name T483
Test name
Test status
Simulation time 85278282 ps
CPU time 1.15 seconds
Started Jul 14 06:59:08 PM PDT 24
Finished Jul 14 06:59:15 PM PDT 24
Peak memory 219316 kb
Host smart-840ff8f0-a729-4ca7-bb39-7101be38335c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751862156 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.2751862156
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.3802933941
Short name T918
Test name
Test status
Simulation time 22105348 ps
CPU time 0.92 seconds
Started Jul 14 06:59:25 PM PDT 24
Finished Jul 14 06:59:28 PM PDT 24
Peak memory 218540 kb
Host smart-420a6def-02c2-4b1f-841b-e2479d3b69b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802933941 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.3802933941
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.682421420
Short name T421
Test name
Test status
Simulation time 56580123 ps
CPU time 1.87 seconds
Started Jul 14 06:59:14 PM PDT 24
Finished Jul 14 06:59:20 PM PDT 24
Peak memory 217884 kb
Host smart-cdb86aa4-ccb0-427c-8364-921ccc368ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682421420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.682421420
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.2281877933
Short name T384
Test name
Test status
Simulation time 23342801 ps
CPU time 1.16 seconds
Started Jul 14 06:59:04 PM PDT 24
Finished Jul 14 06:59:10 PM PDT 24
Peak memory 220000 kb
Host smart-2ffdeb67-0ee5-49bb-97eb-a31f459fe2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281877933 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.2281877933
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.1939827608
Short name T665
Test name
Test status
Simulation time 20907748 ps
CPU time 0.96 seconds
Started Jul 14 06:59:36 PM PDT 24
Finished Jul 14 06:59:39 PM PDT 24
Peak memory 219892 kb
Host smart-a47ed6b6-a65e-475f-a7f5-281e48d66035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939827608 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.1939827608
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.1542773294
Short name T903
Test name
Test status
Simulation time 116179601 ps
CPU time 1.43 seconds
Started Jul 14 06:59:02 PM PDT 24
Finished Jul 14 06:59:08 PM PDT 24
Peak memory 219496 kb
Host smart-4920a8d0-6266-4650-aaac-8b9f2d4d4f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542773294 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.1542773294
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.3265270245
Short name T309
Test name
Test status
Simulation time 81154285 ps
CPU time 1.1 seconds
Started Jul 14 06:59:24 PM PDT 24
Finished Jul 14 06:59:27 PM PDT 24
Peak memory 220144 kb
Host smart-884015af-02eb-4f1c-ad52-929a17b970f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265270245 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.3265270245
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.2487890515
Short name T565
Test name
Test status
Simulation time 32123665 ps
CPU time 1.04 seconds
Started Jul 14 06:59:02 PM PDT 24
Finished Jul 14 06:59:13 PM PDT 24
Peak memory 218996 kb
Host smart-4dc4fae8-5ae1-4024-ac9a-0927d1f200f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487890515 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.2487890515
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.1067939570
Short name T300
Test name
Test status
Simulation time 42948340 ps
CPU time 1.25 seconds
Started Jul 14 06:59:06 PM PDT 24
Finished Jul 14 06:59:12 PM PDT 24
Peak memory 219052 kb
Host smart-10361568-2f70-4f7f-b7c3-d1e2955ba901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067939570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.1067939570
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.240977936
Short name T169
Test name
Test status
Simulation time 171675620 ps
CPU time 1.21 seconds
Started Jul 14 06:59:02 PM PDT 24
Finished Jul 14 06:59:08 PM PDT 24
Peak memory 218872 kb
Host smart-3157986d-1b10-45a6-a0de-ab81b5982bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240977936 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.240977936
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.2059632353
Short name T165
Test name
Test status
Simulation time 25216471 ps
CPU time 0.96 seconds
Started Jul 14 06:59:27 PM PDT 24
Finished Jul 14 06:59:32 PM PDT 24
Peak memory 219000 kb
Host smart-39216d44-548a-4982-ba41-d76f0518d776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059632353 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.2059632353
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.4169829025
Short name T679
Test name
Test status
Simulation time 43571295 ps
CPU time 1.46 seconds
Started Jul 14 06:59:23 PM PDT 24
Finished Jul 14 06:59:26 PM PDT 24
Peak memory 217716 kb
Host smart-c43111f5-50d8-4f2c-bc54-47895fa6dc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169829025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.4169829025
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.3972173419
Short name T177
Test name
Test status
Simulation time 27712781 ps
CPU time 1.21 seconds
Started Jul 14 06:59:06 PM PDT 24
Finished Jul 14 06:59:13 PM PDT 24
Peak memory 220044 kb
Host smart-42413a0c-b52b-413a-ac33-8cd15cca07b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972173419 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.3972173419
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.4139496648
Short name T51
Test name
Test status
Simulation time 26149910 ps
CPU time 1.2 seconds
Started Jul 14 06:59:04 PM PDT 24
Finished Jul 14 06:59:10 PM PDT 24
Peak memory 229860 kb
Host smart-0ebf5841-a355-478f-96b1-ee6a90afc5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139496648 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.4139496648
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.3206955045
Short name T875
Test name
Test status
Simulation time 147606984 ps
CPU time 3.08 seconds
Started Jul 14 06:59:23 PM PDT 24
Finished Jul 14 06:59:28 PM PDT 24
Peak memory 219556 kb
Host smart-929e70a3-4214-4504-8332-7e8f5ad2d750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206955045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.3206955045
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.1390458356
Short name T129
Test name
Test status
Simulation time 26882263 ps
CPU time 1.26 seconds
Started Jul 14 06:59:04 PM PDT 24
Finished Jul 14 06:59:11 PM PDT 24
Peak memory 218724 kb
Host smart-d9188b6d-639a-43ab-bdab-3d68b584003e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390458356 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.1390458356
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.2056176764
Short name T209
Test name
Test status
Simulation time 19777442 ps
CPU time 1.06 seconds
Started Jul 14 06:59:21 PM PDT 24
Finished Jul 14 06:59:23 PM PDT 24
Peak memory 218856 kb
Host smart-d3bcb13f-e04f-46f6-ad30-5c7f9a3be156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056176764 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.2056176764
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/8.edn_alert.1620379316
Short name T533
Test name
Test status
Simulation time 81198420 ps
CPU time 1.18 seconds
Started Jul 14 06:58:03 PM PDT 24
Finished Jul 14 06:58:15 PM PDT 24
Peak memory 218752 kb
Host smart-87036c66-bf5f-4630-a0c4-500030629724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620379316 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.1620379316
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.835584649
Short name T367
Test name
Test status
Simulation time 15118067 ps
CPU time 0.92 seconds
Started Jul 14 06:58:04 PM PDT 24
Finished Jul 14 06:58:08 PM PDT 24
Peak memory 207004 kb
Host smart-1d3f4f15-3aed-4392-abac-e082e602a114
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835584649 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.835584649
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.4222981615
Short name T857
Test name
Test status
Simulation time 14054016 ps
CPU time 0.92 seconds
Started Jul 14 06:58:05 PM PDT 24
Finished Jul 14 06:58:11 PM PDT 24
Peak memory 216684 kb
Host smart-e7c1fc99-ee5d-4586-aa0c-e8d1b3b9fad8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222981615 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.4222981615
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.4187783428
Short name T159
Test name
Test status
Simulation time 43234785 ps
CPU time 1.54 seconds
Started Jul 14 06:58:01 PM PDT 24
Finished Jul 14 06:58:04 PM PDT 24
Peak memory 217052 kb
Host smart-87b884ff-7b8d-43df-b322-295f649115ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187783428 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.4187783428
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.1651654578
Short name T208
Test name
Test status
Simulation time 77175714 ps
CPU time 1.18 seconds
Started Jul 14 06:58:04 PM PDT 24
Finished Jul 14 06:58:09 PM PDT 24
Peak memory 225204 kb
Host smart-2f3a1d2e-3bd8-4b21-8a28-e088e9217880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651654578 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.1651654578
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.3038313822
Short name T335
Test name
Test status
Simulation time 126929252 ps
CPU time 1.4 seconds
Started Jul 14 06:58:04 PM PDT 24
Finished Jul 14 06:58:09 PM PDT 24
Peak memory 218936 kb
Host smart-2cfd8b28-a85b-474b-a4f4-a2ad904633ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038313822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3038313822
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.1557945926
Short name T114
Test name
Test status
Simulation time 32951570 ps
CPU time 0.9 seconds
Started Jul 14 06:58:02 PM PDT 24
Finished Jul 14 06:58:06 PM PDT 24
Peak memory 216012 kb
Host smart-ac49da05-f7d2-4a23-b70f-22a0cef2593f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557945926 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.1557945926
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.4262723372
Short name T24
Test name
Test status
Simulation time 40014224 ps
CPU time 0.92 seconds
Started Jul 14 06:58:11 PM PDT 24
Finished Jul 14 06:58:19 PM PDT 24
Peak memory 207452 kb
Host smart-1e933b89-99e0-4b88-83f6-048f069f0f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262723372 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.4262723372
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.2874396437
Short name T599
Test name
Test status
Simulation time 24776666 ps
CPU time 0.91 seconds
Started Jul 14 06:58:03 PM PDT 24
Finished Jul 14 06:58:07 PM PDT 24
Peak memory 215580 kb
Host smart-ba130a40-941b-46cd-a012-1b3297ac1301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874396437 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.2874396437
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.3845246676
Short name T333
Test name
Test status
Simulation time 344241287 ps
CPU time 4.49 seconds
Started Jul 14 06:58:08 PM PDT 24
Finished Jul 14 06:58:18 PM PDT 24
Peak memory 220908 kb
Host smart-8f0d61f1-2626-4505-a6c7-61e340db8e77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845246676 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.3845246676
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.3089709179
Short name T441
Test name
Test status
Simulation time 63426171772 ps
CPU time 1429.03 seconds
Started Jul 14 06:58:03 PM PDT 24
Finished Jul 14 07:21:54 PM PDT 24
Peak memory 223444 kb
Host smart-6fe183c6-1374-4326-93de-1c686d44ea2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089709179 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3089709179
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.2332718997
Short name T286
Test name
Test status
Simulation time 34050068 ps
CPU time 1.31 seconds
Started Jul 14 06:59:08 PM PDT 24
Finished Jul 14 06:59:15 PM PDT 24
Peak memory 220676 kb
Host smart-bba6faf9-2aab-4aca-bc02-bb8cdd05defe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332718997 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.2332718997
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.3437165702
Short name T393
Test name
Test status
Simulation time 24520998 ps
CPU time 0.87 seconds
Started Jul 14 06:58:59 PM PDT 24
Finished Jul 14 06:59:04 PM PDT 24
Peak memory 218516 kb
Host smart-5c078780-5d9f-4e70-8bbf-f685758c4afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437165702 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.3437165702
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.2728121316
Short name T608
Test name
Test status
Simulation time 64676640 ps
CPU time 2.49 seconds
Started Jul 14 06:59:28 PM PDT 24
Finished Jul 14 06:59:34 PM PDT 24
Peak memory 219196 kb
Host smart-5d818839-bcaa-4ee2-8fb1-8373b65318af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728121316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.2728121316
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.4036553732
Short name T559
Test name
Test status
Simulation time 49412128 ps
CPU time 1.15 seconds
Started Jul 14 06:59:06 PM PDT 24
Finished Jul 14 06:59:12 PM PDT 24
Peak memory 220084 kb
Host smart-fa35a513-61de-4951-9578-11e0fb739403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036553732 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.4036553732
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.2626147291
Short name T742
Test name
Test status
Simulation time 31063110 ps
CPU time 0.9 seconds
Started Jul 14 06:59:06 PM PDT 24
Finished Jul 14 06:59:12 PM PDT 24
Peak memory 218900 kb
Host smart-9f4d3eab-040b-40a8-8a66-5ae756e0dda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626147291 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.2626147291
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.3062368910
Short name T928
Test name
Test status
Simulation time 24438164 ps
CPU time 1.17 seconds
Started Jul 14 06:59:18 PM PDT 24
Finished Jul 14 06:59:21 PM PDT 24
Peak memory 217784 kb
Host smart-08901358-096c-4bcd-a4f1-44aa2bb8eab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062368910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3062368910
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.2980829799
Short name T135
Test name
Test status
Simulation time 25909501 ps
CPU time 1.22 seconds
Started Jul 14 06:59:33 PM PDT 24
Finished Jul 14 06:59:37 PM PDT 24
Peak memory 218932 kb
Host smart-be3caed9-e63d-449b-b14d-988a44a3e83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980829799 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.2980829799
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.3109133920
Short name T215
Test name
Test status
Simulation time 24978528 ps
CPU time 1.14 seconds
Started Jul 14 06:59:06 PM PDT 24
Finished Jul 14 06:59:12 PM PDT 24
Peak memory 218868 kb
Host smart-34276f2c-2050-4994-9da9-7dcfd75a9e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109133920 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.3109133920
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.2783577594
Short name T768
Test name
Test status
Simulation time 92882116 ps
CPU time 1.11 seconds
Started Jul 14 06:59:09 PM PDT 24
Finished Jul 14 06:59:15 PM PDT 24
Peak memory 217376 kb
Host smart-e494a58f-e1a5-4a0f-8706-572bef182cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783577594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.2783577594
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.4125136513
Short name T155
Test name
Test status
Simulation time 29384566 ps
CPU time 1.26 seconds
Started Jul 14 06:59:38 PM PDT 24
Finished Jul 14 06:59:42 PM PDT 24
Peak memory 218948 kb
Host smart-d66e11d2-0a83-413b-8b2c-17baf1f0e2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125136513 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.4125136513
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.463868878
Short name T816
Test name
Test status
Simulation time 24038253 ps
CPU time 0.99 seconds
Started Jul 14 06:59:06 PM PDT 24
Finished Jul 14 06:59:13 PM PDT 24
Peak memory 219876 kb
Host smart-d9d62d17-bc96-440f-97fd-cb3a5e32d979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463868878 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.463868878
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.3113906744
Short name T693
Test name
Test status
Simulation time 57366663 ps
CPU time 1.04 seconds
Started Jul 14 06:59:09 PM PDT 24
Finished Jul 14 06:59:16 PM PDT 24
Peak memory 217616 kb
Host smart-fb9db9f9-39b8-494b-b797-8cc07ab3be84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113906744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3113906744
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.536008477
Short name T756
Test name
Test status
Simulation time 24890784 ps
CPU time 1.13 seconds
Started Jul 14 06:59:16 PM PDT 24
Finished Jul 14 06:59:20 PM PDT 24
Peak memory 220160 kb
Host smart-1c2c9762-dd20-4244-a2b7-27fb6fa22a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536008477 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.536008477
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.2468527250
Short name T534
Test name
Test status
Simulation time 27193315 ps
CPU time 1.14 seconds
Started Jul 14 06:59:04 PM PDT 24
Finished Jul 14 06:59:10 PM PDT 24
Peak memory 219072 kb
Host smart-bee61a13-1f5e-456a-8cb8-b87bbfe40195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468527250 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.2468527250
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.3669619510
Short name T452
Test name
Test status
Simulation time 59540679 ps
CPU time 1.53 seconds
Started Jul 14 06:59:25 PM PDT 24
Finished Jul 14 06:59:29 PM PDT 24
Peak memory 218936 kb
Host smart-4d9d0ead-85e9-475a-b02c-8b8ffaefe509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669619510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3669619510
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.543982779
Short name T607
Test name
Test status
Simulation time 41137453 ps
CPU time 1.05 seconds
Started Jul 14 06:59:11 PM PDT 24
Finished Jul 14 06:59:17 PM PDT 24
Peak memory 219020 kb
Host smart-b15a3146-2d3e-40cc-a557-21518181be35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543982779 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.543982779
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.4173033354
Short name T78
Test name
Test status
Simulation time 25788212 ps
CPU time 0.87 seconds
Started Jul 14 06:59:07 PM PDT 24
Finished Jul 14 06:59:13 PM PDT 24
Peak memory 218576 kb
Host smart-a9bc73d7-e83f-4dab-bd93-6ea970de992f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173033354 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.4173033354
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.2362125914
Short name T548
Test name
Test status
Simulation time 87498149 ps
CPU time 1.21 seconds
Started Jul 14 06:59:25 PM PDT 24
Finished Jul 14 06:59:28 PM PDT 24
Peak memory 218984 kb
Host smart-342aed7a-c657-4b3c-bdd6-be054f3f9b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362125914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.2362125914
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.259850149
Short name T895
Test name
Test status
Simulation time 93466772 ps
CPU time 1.14 seconds
Started Jul 14 06:59:29 PM PDT 24
Finished Jul 14 06:59:34 PM PDT 24
Peak memory 215976 kb
Host smart-609d4f22-83eb-4154-85b0-5df6f2e25a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259850149 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.259850149
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.4063772437
Short name T651
Test name
Test status
Simulation time 28905064 ps
CPU time 0.86 seconds
Started Jul 14 06:59:10 PM PDT 24
Finished Jul 14 06:59:16 PM PDT 24
Peak memory 218604 kb
Host smart-47224843-0782-4c59-9df5-4c134f77326a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063772437 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.4063772437
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.2595493956
Short name T299
Test name
Test status
Simulation time 62056973 ps
CPU time 1.11 seconds
Started Jul 14 06:59:34 PM PDT 24
Finished Jul 14 06:59:38 PM PDT 24
Peak memory 219372 kb
Host smart-4e07f05c-66ab-4ea9-b199-48ef31ba764b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595493956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.2595493956
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.565906811
Short name T102
Test name
Test status
Simulation time 81332482 ps
CPU time 1.22 seconds
Started Jul 14 06:59:45 PM PDT 24
Finished Jul 14 06:59:48 PM PDT 24
Peak memory 220044 kb
Host smart-35c1ec5f-f2d0-4213-9caf-3b26a8c1abe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565906811 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.565906811
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.2043892753
Short name T161
Test name
Test status
Simulation time 18731113 ps
CPU time 1 seconds
Started Jul 14 06:59:06 PM PDT 24
Finished Jul 14 06:59:12 PM PDT 24
Peak memory 218776 kb
Host smart-49c57d91-aa2c-431c-b390-c281e1fdcd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043892753 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.2043892753
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.2081407395
Short name T426
Test name
Test status
Simulation time 51154771 ps
CPU time 1.47 seconds
Started Jul 14 06:59:24 PM PDT 24
Finished Jul 14 06:59:28 PM PDT 24
Peak memory 218884 kb
Host smart-02d12e10-f5ca-4498-85ad-63d361134fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081407395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2081407395
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.2031640800
Short name T219
Test name
Test status
Simulation time 86283919 ps
CPU time 1.17 seconds
Started Jul 14 06:59:33 PM PDT 24
Finished Jul 14 06:59:36 PM PDT 24
Peak memory 220512 kb
Host smart-2e50e5a0-729e-46c4-afa1-304ba3774f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031640800 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.2031640800
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.2248251811
Short name T200
Test name
Test status
Simulation time 86885166 ps
CPU time 1.08 seconds
Started Jul 14 06:59:28 PM PDT 24
Finished Jul 14 06:59:32 PM PDT 24
Peak memory 219932 kb
Host smart-abe3722e-f4a5-4607-92f2-41a4c345f5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248251811 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.2248251811
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.566336659
Short name T398
Test name
Test status
Simulation time 118616415 ps
CPU time 2.57 seconds
Started Jul 14 06:59:23 PM PDT 24
Finished Jul 14 06:59:28 PM PDT 24
Peak memory 218932 kb
Host smart-f5af68f5-7908-4a5a-8eb6-65fff8aa27f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566336659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.566336659
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.382417245
Short name T583
Test name
Test status
Simulation time 232948969 ps
CPU time 1.14 seconds
Started Jul 14 06:59:09 PM PDT 24
Finished Jul 14 06:59:16 PM PDT 24
Peak memory 218956 kb
Host smart-440fd7ee-af7b-4832-a13f-bc4c7906c63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382417245 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.382417245
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.306508535
Short name T669
Test name
Test status
Simulation time 23829802 ps
CPU time 0.94 seconds
Started Jul 14 06:59:07 PM PDT 24
Finished Jul 14 06:59:18 PM PDT 24
Peak memory 218780 kb
Host smart-2273924d-0ffa-40c1-8e88-3247045df81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306508535 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.306508535
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.1455191735
Short name T969
Test name
Test status
Simulation time 71070838 ps
CPU time 1.41 seconds
Started Jul 14 06:59:43 PM PDT 24
Finished Jul 14 06:59:52 PM PDT 24
Peak memory 217668 kb
Host smart-d2fcc68f-2aac-48bc-a273-8589885b2a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455191735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.1455191735
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.2804288696
Short name T915
Test name
Test status
Simulation time 38003184 ps
CPU time 1.11 seconds
Started Jul 14 06:58:32 PM PDT 24
Finished Jul 14 06:58:35 PM PDT 24
Peak memory 218796 kb
Host smart-e2db0026-cc85-4cc1-8b57-b2f89f390038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804288696 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.2804288696
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.3061116252
Short name T776
Test name
Test status
Simulation time 15361269 ps
CPU time 0.92 seconds
Started Jul 14 06:58:06 PM PDT 24
Finished Jul 14 06:58:11 PM PDT 24
Peak memory 206960 kb
Host smart-429b5158-6e1c-4e2a-85be-b75403f0b7b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061116252 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.3061116252
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.2963646012
Short name T558
Test name
Test status
Simulation time 117901970 ps
CPU time 0.86 seconds
Started Jul 14 06:58:28 PM PDT 24
Finished Jul 14 06:58:30 PM PDT 24
Peak memory 216640 kb
Host smart-5df93961-5597-4779-bbf2-f3ac24ae93bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963646012 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.2963646012
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.3337922615
Short name T198
Test name
Test status
Simulation time 33232521 ps
CPU time 1.29 seconds
Started Jul 14 06:58:32 PM PDT 24
Finished Jul 14 06:58:36 PM PDT 24
Peak memory 217136 kb
Host smart-e617eb91-a666-4885-a86a-06823f9f9475
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337922615 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.3337922615
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.1744629124
Short name T416
Test name
Test status
Simulation time 62278424 ps
CPU time 1.13 seconds
Started Jul 14 06:58:18 PM PDT 24
Finished Jul 14 06:58:25 PM PDT 24
Peak memory 220040 kb
Host smart-84f8707f-aee8-45d9-9048-7de96cf7001d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744629124 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1744629124
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.1124922388
Short name T707
Test name
Test status
Simulation time 50502826 ps
CPU time 1.32 seconds
Started Jul 14 06:58:06 PM PDT 24
Finished Jul 14 06:58:11 PM PDT 24
Peak memory 220028 kb
Host smart-9246befb-08e4-4a60-b7d6-7b4a33ba6561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124922388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1124922388
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.1802088084
Short name T92
Test name
Test status
Simulation time 25498095 ps
CPU time 0.92 seconds
Started Jul 14 06:58:04 PM PDT 24
Finished Jul 14 06:58:08 PM PDT 24
Peak memory 216216 kb
Host smart-191f9baf-82c5-4eb0-b283-d61bd224cb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802088084 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.1802088084
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.3338670620
Short name T650
Test name
Test status
Simulation time 68577881 ps
CPU time 0.95 seconds
Started Jul 14 06:58:07 PM PDT 24
Finished Jul 14 06:58:13 PM PDT 24
Peak memory 207264 kb
Host smart-6fcf2277-fd25-4c25-a5b6-e07831bf2105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338670620 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.3338670620
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.2473160772
Short name T725
Test name
Test status
Simulation time 26765932 ps
CPU time 0.94 seconds
Started Jul 14 06:58:05 PM PDT 24
Finished Jul 14 06:58:11 PM PDT 24
Peak memory 215568 kb
Host smart-3a09aa7e-8bd1-47cd-a9c4-13769efc2022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473160772 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2473160772
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1009752447
Short name T530
Test name
Test status
Simulation time 352430888 ps
CPU time 4.12 seconds
Started Jul 14 06:58:07 PM PDT 24
Finished Jul 14 06:58:17 PM PDT 24
Peak memory 217632 kb
Host smart-dd7db966-6491-48fd-96cb-d6adea47b01f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009752447 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1009752447
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.1412812716
Short name T943
Test name
Test status
Simulation time 244581760103 ps
CPU time 1783.28 seconds
Started Jul 14 06:58:06 PM PDT 24
Finished Jul 14 07:27:53 PM PDT 24
Peak memory 226196 kb
Host smart-07c8506a-be22-4dca-8b88-9135573ce000
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412812716 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.1412812716
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.177815477
Short name T422
Test name
Test status
Simulation time 49521759 ps
CPU time 1.24 seconds
Started Jul 14 06:59:43 PM PDT 24
Finished Jul 14 06:59:47 PM PDT 24
Peak memory 218728 kb
Host smart-2e6bd5c2-ba2a-44de-83d2-e8e81988c9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177815477 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.177815477
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.419419720
Short name T194
Test name
Test status
Simulation time 20730701 ps
CPU time 1.19 seconds
Started Jul 14 06:59:17 PM PDT 24
Finished Jul 14 06:59:21 PM PDT 24
Peak memory 230076 kb
Host smart-36ab7b5f-a831-4999-8ab8-20b543666871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419419720 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.419419720
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.459060880
Short name T401
Test name
Test status
Simulation time 187899691 ps
CPU time 1.04 seconds
Started Jul 14 06:59:08 PM PDT 24
Finished Jul 14 06:59:13 PM PDT 24
Peak memory 217880 kb
Host smart-884ce106-29f8-4803-b7bd-6ba908983e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459060880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.459060880
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.2921785608
Short name T193
Test name
Test status
Simulation time 72358624 ps
CPU time 0.9 seconds
Started Jul 14 06:59:52 PM PDT 24
Finished Jul 14 06:59:55 PM PDT 24
Peak memory 229564 kb
Host smart-02348d6f-1713-45ac-bed5-c4d4f55806ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921785608 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.2921785608
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.3272463232
Short name T984
Test name
Test status
Simulation time 124610855 ps
CPU time 1.37 seconds
Started Jul 14 06:59:08 PM PDT 24
Finished Jul 14 06:59:14 PM PDT 24
Peak memory 220320 kb
Host smart-98e0763b-b617-4ed6-91a5-6f62e59af06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272463232 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.3272463232
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.3324641515
Short name T590
Test name
Test status
Simulation time 121201264 ps
CPU time 1.24 seconds
Started Jul 14 06:59:14 PM PDT 24
Finished Jul 14 06:59:19 PM PDT 24
Peak memory 220776 kb
Host smart-2bd88bbc-27dc-4dc5-a2b2-8d96cba2ffb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324641515 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.3324641515
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.3927215663
Short name T146
Test name
Test status
Simulation time 32600831 ps
CPU time 1.03 seconds
Started Jul 14 06:59:29 PM PDT 24
Finished Jul 14 06:59:34 PM PDT 24
Peak memory 218820 kb
Host smart-82aaf68f-c2cc-42d6-8f26-5bef283b1257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927215663 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3927215663
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.1597702363
Short name T845
Test name
Test status
Simulation time 28684170 ps
CPU time 1.2 seconds
Started Jul 14 06:59:52 PM PDT 24
Finished Jul 14 06:59:55 PM PDT 24
Peak memory 218968 kb
Host smart-1cd61a7b-cdfc-4ed1-b1a8-edea6d8ebc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597702363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1597702363
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.2362451625
Short name T415
Test name
Test status
Simulation time 42960450 ps
CPU time 1.15 seconds
Started Jul 14 06:59:22 PM PDT 24
Finished Jul 14 06:59:24 PM PDT 24
Peak memory 220156 kb
Host smart-1fcc5552-2d4a-41d1-b056-ff07f8c4d6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362451625 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.2362451625
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.812450204
Short name T701
Test name
Test status
Simulation time 23718813 ps
CPU time 0.89 seconds
Started Jul 14 06:59:10 PM PDT 24
Finished Jul 14 06:59:16 PM PDT 24
Peak memory 218452 kb
Host smart-4044c5d1-6ebd-45da-9008-a2142e68de51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812450204 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.812450204
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.4264915359
Short name T312
Test name
Test status
Simulation time 37034652 ps
CPU time 1.11 seconds
Started Jul 14 06:59:24 PM PDT 24
Finished Jul 14 06:59:27 PM PDT 24
Peak memory 220192 kb
Host smart-beabf743-4f46-4223-924f-28ea9acd9513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264915359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.4264915359
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.2410835583
Short name T186
Test name
Test status
Simulation time 40447800 ps
CPU time 1.19 seconds
Started Jul 14 06:59:26 PM PDT 24
Finished Jul 14 06:59:30 PM PDT 24
Peak memory 215972 kb
Host smart-7cd2e746-424d-4420-87d7-67af59f2a1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410835583 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.2410835583
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.813864329
Short name T211
Test name
Test status
Simulation time 18484104 ps
CPU time 1.05 seconds
Started Jul 14 06:59:20 PM PDT 24
Finished Jul 14 06:59:23 PM PDT 24
Peak memory 218920 kb
Host smart-a1c186d0-ab5a-45e9-a511-64f7bb725be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813864329 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.813864329
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.2089113685
Short name T364
Test name
Test status
Simulation time 42506956 ps
CPU time 1.42 seconds
Started Jul 14 06:59:07 PM PDT 24
Finished Jul 14 06:59:13 PM PDT 24
Peak memory 218792 kb
Host smart-6af93072-6a7e-446e-ae4d-bcb3c98497e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089113685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.2089113685
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.1352653345
Short name T886
Test name
Test status
Simulation time 23966387 ps
CPU time 1.14 seconds
Started Jul 14 06:59:39 PM PDT 24
Finished Jul 14 06:59:43 PM PDT 24
Peak memory 219948 kb
Host smart-50eea8b6-312a-496a-af01-f4fb201fd81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352653345 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.1352653345
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.1011341924
Short name T197
Test name
Test status
Simulation time 23773181 ps
CPU time 0.93 seconds
Started Jul 14 06:59:08 PM PDT 24
Finished Jul 14 06:59:14 PM PDT 24
Peak memory 218756 kb
Host smart-207fbff1-d513-4c88-b1ff-7ce3ec7990fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011341924 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.1011341924
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.796768156
Short name T876
Test name
Test status
Simulation time 22376286 ps
CPU time 1.14 seconds
Started Jul 14 06:59:10 PM PDT 24
Finished Jul 14 06:59:17 PM PDT 24
Peak memory 218728 kb
Host smart-7c2138e0-4d3c-4395-ad15-8ac49e63c592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796768156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.796768156
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.1500672642
Short name T204
Test name
Test status
Simulation time 50392741 ps
CPU time 0.92 seconds
Started Jul 14 06:59:10 PM PDT 24
Finished Jul 14 06:59:16 PM PDT 24
Peak memory 219996 kb
Host smart-e5c4b040-3cf0-4dc4-853f-10e00a63ea2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500672642 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.1500672642
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.1502710810
Short name T777
Test name
Test status
Simulation time 36437890 ps
CPU time 1.28 seconds
Started Jul 14 06:59:09 PM PDT 24
Finished Jul 14 06:59:15 PM PDT 24
Peak memory 218776 kb
Host smart-96d7199e-45fa-4880-ad31-d2b832db8418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502710810 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.1502710810
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.3549985479
Short name T517
Test name
Test status
Simulation time 64429956 ps
CPU time 1.08 seconds
Started Jul 14 06:59:39 PM PDT 24
Finished Jul 14 06:59:43 PM PDT 24
Peak memory 221232 kb
Host smart-83f67ce9-97c3-451e-be1e-37551c9d601e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549985479 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.3549985479
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.2397485040
Short name T544
Test name
Test status
Simulation time 22835930 ps
CPU time 0.98 seconds
Started Jul 14 06:59:35 PM PDT 24
Finished Jul 14 06:59:39 PM PDT 24
Peak memory 218892 kb
Host smart-40e5d9f3-0531-488d-b0f2-0dee9492508f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397485040 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.2397485040
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.537990851
Short name T896
Test name
Test status
Simulation time 52611379 ps
CPU time 0.91 seconds
Started Jul 14 06:59:11 PM PDT 24
Finished Jul 14 06:59:17 PM PDT 24
Peak memory 217624 kb
Host smart-af347b96-1396-4dc8-ac85-f3782b88049e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537990851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.537990851
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.2592410589
Short name T787
Test name
Test status
Simulation time 28794990 ps
CPU time 1.34 seconds
Started Jul 14 06:59:25 PM PDT 24
Finished Jul 14 06:59:29 PM PDT 24
Peak memory 219076 kb
Host smart-193f3d79-d8a1-4f07-9aa2-36c82d58758b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592410589 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.2592410589
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.1393407085
Short name T672
Test name
Test status
Simulation time 24459619 ps
CPU time 1 seconds
Started Jul 14 06:59:09 PM PDT 24
Finished Jul 14 06:59:15 PM PDT 24
Peak memory 218672 kb
Host smart-2e547f2c-b9ec-44bd-8635-c1f6babd7600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393407085 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1393407085
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.1916918367
Short name T654
Test name
Test status
Simulation time 60747329 ps
CPU time 1.29 seconds
Started Jul 14 06:59:26 PM PDT 24
Finished Jul 14 06:59:31 PM PDT 24
Peak memory 218352 kb
Host smart-906e299e-4fe1-44a0-a37d-e8f1bb91f069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916918367 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.1916918367
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.1418124719
Short name T692
Test name
Test status
Simulation time 26246356 ps
CPU time 1.15 seconds
Started Jul 14 06:59:26 PM PDT 24
Finished Jul 14 06:59:30 PM PDT 24
Peak memory 220936 kb
Host smart-4bd36095-3908-4559-a5a6-6f5719e67bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418124719 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.1418124719
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.553775371
Short name T618
Test name
Test status
Simulation time 24279853 ps
CPU time 0.92 seconds
Started Jul 14 06:59:26 PM PDT 24
Finished Jul 14 06:59:30 PM PDT 24
Peak memory 218768 kb
Host smart-d3ee8a4a-45b9-434a-ac3a-7e2603267fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553775371 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.553775371
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.3452640352
Short name T535
Test name
Test status
Simulation time 46995589 ps
CPU time 1.51 seconds
Started Jul 14 06:59:35 PM PDT 24
Finished Jul 14 06:59:39 PM PDT 24
Peak memory 218664 kb
Host smart-f7572e44-153e-4c56-8d9a-725c6240d1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452640352 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3452640352
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%