Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 12 0 12 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 2 0 2 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 12 0 12 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 7187 1 T6 26 T54 33 T40 66
all_values[1] 7187 1 T6 26 T54 33 T40 66


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7351 1 T6 20 T54 26 T40 67
auto[1] 7023 1 T6 32 T54 40 T40 65


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 5554 1 T6 18 T54 27 T40 47
auto[1] 8820 1 T6 34 T54 39 T40 85


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8531 1 T6 30 T54 39 T40 81
auto[1] 5843 1 T6 22 T54 27 T40 51


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 12 0 12 100.00
Automatically Generated Cross Bins 12 0 12 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 1390 1 T6 4 T54 6 T40 16
all_values[0] auto[0] auto[0] auto[1] 768 1 T6 4 T54 2 T40 4
all_values[0] auto[0] auto[1] auto[0] 1356 1 T6 7 T54 7 T40 15
all_values[0] auto[0] auto[1] auto[1] 766 1 T6 1 T54 5 T40 8
all_values[0] auto[1] auto[0] auto[1] 1487 1 T6 5 T54 4 T40 11
all_values[0] auto[1] auto[1] auto[1] 1420 1 T6 5 T54 9 T40 12
all_values[1] auto[0] auto[0] auto[0] 1455 1 T54 7 T40 10 T41 29
all_values[1] auto[0] auto[0] auto[1] 753 1 T6 3 T54 1 T40 10
all_values[1] auto[0] auto[1] auto[0] 1353 1 T6 7 T54 7 T40 6
all_values[1] auto[0] auto[1] auto[1] 690 1 T6 4 T54 4 T40 12
all_values[1] auto[1] auto[0] auto[1] 1498 1 T6 4 T54 6 T40 16
all_values[1] auto[1] auto[1] auto[1] 1438 1 T6 8 T54 8 T40 12


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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