Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.78 98.25 93.91 97.02 93.02 96.37 99.77 92.08


Total test records in report: 1130
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T1014 /workspace/coverage/cover_reg_top/21.edn_intr_test.3194079038 Jul 15 07:11:50 PM PDT 24 Jul 15 07:11:58 PM PDT 24 21005106 ps
T1015 /workspace/coverage/cover_reg_top/0.edn_intr_test.3935421978 Jul 15 07:11:41 PM PDT 24 Jul 15 07:11:43 PM PDT 24 15018932 ps
T1016 /workspace/coverage/cover_reg_top/44.edn_intr_test.1563900791 Jul 15 07:11:52 PM PDT 24 Jul 15 07:12:01 PM PDT 24 15982399 ps
T274 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.864184361 Jul 15 07:11:57 PM PDT 24 Jul 15 07:12:06 PM PDT 24 79707637 ps
T261 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3184563729 Jul 15 07:11:40 PM PDT 24 Jul 15 07:11:43 PM PDT 24 43536726 ps
T1017 /workspace/coverage/cover_reg_top/9.edn_tl_errors.1517188322 Jul 15 07:11:48 PM PDT 24 Jul 15 07:11:56 PM PDT 24 31218652 ps
T1018 /workspace/coverage/cover_reg_top/43.edn_intr_test.3472139600 Jul 15 07:11:53 PM PDT 24 Jul 15 07:12:02 PM PDT 24 21522933 ps
T1019 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.4207641102 Jul 15 07:11:43 PM PDT 24 Jul 15 07:11:48 PM PDT 24 58213186 ps
T1020 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.427770141 Jul 15 07:11:44 PM PDT 24 Jul 15 07:11:49 PM PDT 24 54224882 ps
T285 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3955013531 Jul 15 07:11:45 PM PDT 24 Jul 15 07:11:51 PM PDT 24 79551690 ps
T1021 /workspace/coverage/cover_reg_top/5.edn_tl_errors.1102678498 Jul 15 07:11:47 PM PDT 24 Jul 15 07:11:56 PM PDT 24 699468724 ps
T1022 /workspace/coverage/cover_reg_top/28.edn_intr_test.1664783202 Jul 15 07:11:56 PM PDT 24 Jul 15 07:12:06 PM PDT 24 13680134 ps
T1023 /workspace/coverage/cover_reg_top/19.edn_tl_errors.4190191105 Jul 15 07:11:53 PM PDT 24 Jul 15 07:12:02 PM PDT 24 51263840 ps
T286 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1013728584 Jul 15 07:11:52 PM PDT 24 Jul 15 07:12:02 PM PDT 24 177263606 ps
T287 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3252119255 Jul 15 07:11:49 PM PDT 24 Jul 15 07:11:58 PM PDT 24 88393933 ps
T1024 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.4160130648 Jul 15 07:11:54 PM PDT 24 Jul 15 07:12:05 PM PDT 24 132616414 ps
T1025 /workspace/coverage/cover_reg_top/49.edn_intr_test.1104824222 Jul 15 07:11:51 PM PDT 24 Jul 15 07:12:00 PM PDT 24 99800980 ps
T1026 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1326033463 Jul 15 07:11:51 PM PDT 24 Jul 15 07:12:01 PM PDT 24 109425248 ps
T1027 /workspace/coverage/cover_reg_top/15.edn_tl_errors.2433430468 Jul 15 07:11:50 PM PDT 24 Jul 15 07:12:00 PM PDT 24 39608506 ps
T1028 /workspace/coverage/cover_reg_top/8.edn_csr_rw.267133361 Jul 15 07:11:49 PM PDT 24 Jul 15 07:11:57 PM PDT 24 16963572 ps
T1029 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.761754786 Jul 15 07:11:49 PM PDT 24 Jul 15 07:11:57 PM PDT 24 37302593 ps
T1030 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3226357433 Jul 15 07:11:51 PM PDT 24 Jul 15 07:12:02 PM PDT 24 456554284 ps
T1031 /workspace/coverage/cover_reg_top/1.edn_tl_errors.541222310 Jul 15 07:11:42 PM PDT 24 Jul 15 07:11:46 PM PDT 24 54200714 ps
T1032 /workspace/coverage/cover_reg_top/7.edn_csr_rw.1840429035 Jul 15 07:11:47 PM PDT 24 Jul 15 07:11:54 PM PDT 24 19459901 ps
T1033 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.731427776 Jul 15 07:11:48 PM PDT 24 Jul 15 07:11:55 PM PDT 24 30497232 ps
T1034 /workspace/coverage/cover_reg_top/24.edn_intr_test.212081095 Jul 15 07:11:51 PM PDT 24 Jul 15 07:12:00 PM PDT 24 25445958 ps
T1035 /workspace/coverage/cover_reg_top/11.edn_csr_rw.1791652370 Jul 15 07:11:49 PM PDT 24 Jul 15 07:11:57 PM PDT 24 41629112 ps
T1036 /workspace/coverage/cover_reg_top/13.edn_csr_rw.2133241487 Jul 15 07:11:51 PM PDT 24 Jul 15 07:12:00 PM PDT 24 14084056 ps
T1037 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3787409704 Jul 15 07:11:47 PM PDT 24 Jul 15 07:11:54 PM PDT 24 30496426 ps
T1038 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3391326659 Jul 15 07:11:42 PM PDT 24 Jul 15 07:11:46 PM PDT 24 16643358 ps
T1039 /workspace/coverage/cover_reg_top/2.edn_tl_errors.497986979 Jul 15 07:11:44 PM PDT 24 Jul 15 07:11:51 PM PDT 24 156031744 ps
T1040 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2882406810 Jul 15 07:11:49 PM PDT 24 Jul 15 07:11:56 PM PDT 24 104541213 ps
T1041 /workspace/coverage/cover_reg_top/9.edn_intr_test.1251639881 Jul 15 07:11:47 PM PDT 24 Jul 15 07:11:54 PM PDT 24 20397796 ps
T1042 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2523684433 Jul 15 07:11:47 PM PDT 24 Jul 15 07:11:53 PM PDT 24 58340395 ps
T1043 /workspace/coverage/cover_reg_top/4.edn_tl_errors.2935804523 Jul 15 07:11:44 PM PDT 24 Jul 15 07:11:51 PM PDT 24 55614839 ps
T1044 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2414982896 Jul 15 07:11:42 PM PDT 24 Jul 15 07:11:46 PM PDT 24 101860511 ps
T1045 /workspace/coverage/cover_reg_top/12.edn_tl_errors.1930210060 Jul 15 07:11:50 PM PDT 24 Jul 15 07:11:59 PM PDT 24 113972608 ps
T1046 /workspace/coverage/cover_reg_top/7.edn_intr_test.4203191827 Jul 15 07:11:46 PM PDT 24 Jul 15 07:11:52 PM PDT 24 65138049 ps
T1047 /workspace/coverage/cover_reg_top/2.edn_intr_test.2847420649 Jul 15 07:11:42 PM PDT 24 Jul 15 07:11:47 PM PDT 24 15505736 ps
T1048 /workspace/coverage/cover_reg_top/11.edn_tl_errors.2220020991 Jul 15 07:11:47 PM PDT 24 Jul 15 07:11:57 PM PDT 24 290844722 ps
T1049 /workspace/coverage/cover_reg_top/8.edn_tl_errors.3506526 Jul 15 07:11:44 PM PDT 24 Jul 15 07:11:50 PM PDT 24 143278309 ps
T1050 /workspace/coverage/cover_reg_top/14.edn_intr_test.727411044 Jul 15 07:11:54 PM PDT 24 Jul 15 07:12:03 PM PDT 24 47164073 ps
T1051 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2647728838 Jul 15 07:11:42 PM PDT 24 Jul 15 07:11:47 PM PDT 24 88307848 ps
T1052 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3514576425 Jul 15 07:11:44 PM PDT 24 Jul 15 07:11:50 PM PDT 24 12203445 ps
T1053 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1241587606 Jul 15 07:11:47 PM PDT 24 Jul 15 07:11:55 PM PDT 24 90425977 ps
T1054 /workspace/coverage/cover_reg_top/27.edn_intr_test.1596038217 Jul 15 07:11:54 PM PDT 24 Jul 15 07:12:04 PM PDT 24 28794255 ps
T1055 /workspace/coverage/cover_reg_top/25.edn_intr_test.2966094463 Jul 15 07:11:52 PM PDT 24 Jul 15 07:12:01 PM PDT 24 14562441 ps
T1056 /workspace/coverage/cover_reg_top/0.edn_csr_rw.1072218645 Jul 15 07:11:41 PM PDT 24 Jul 15 07:11:44 PM PDT 24 17434601 ps
T1057 /workspace/coverage/cover_reg_top/12.edn_intr_test.4003911532 Jul 15 07:11:48 PM PDT 24 Jul 15 07:11:55 PM PDT 24 16243448 ps
T1058 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1306900899 Jul 15 07:11:44 PM PDT 24 Jul 15 07:11:49 PM PDT 24 25265278 ps
T1059 /workspace/coverage/cover_reg_top/15.edn_intr_test.2810292680 Jul 15 07:11:49 PM PDT 24 Jul 15 07:11:56 PM PDT 24 47031637 ps
T1060 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.4190482686 Jul 15 07:11:42 PM PDT 24 Jul 15 07:11:46 PM PDT 24 38871324 ps
T1061 /workspace/coverage/cover_reg_top/13.edn_intr_test.1804151409 Jul 15 07:11:49 PM PDT 24 Jul 15 07:11:57 PM PDT 24 16686134 ps
T1062 /workspace/coverage/cover_reg_top/13.edn_tl_errors.2537336487 Jul 15 07:11:47 PM PDT 24 Jul 15 07:11:54 PM PDT 24 119871082 ps
T1063 /workspace/coverage/cover_reg_top/36.edn_intr_test.999740816 Jul 15 07:11:55 PM PDT 24 Jul 15 07:12:04 PM PDT 24 30904901 ps
T262 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.4178348660 Jul 15 07:11:41 PM PDT 24 Jul 15 07:11:45 PM PDT 24 36849567 ps
T1064 /workspace/coverage/cover_reg_top/48.edn_intr_test.1835029197 Jul 15 07:11:51 PM PDT 24 Jul 15 07:12:00 PM PDT 24 19354530 ps
T1065 /workspace/coverage/cover_reg_top/16.edn_tl_errors.2024707148 Jul 15 07:11:50 PM PDT 24 Jul 15 07:11:58 PM PDT 24 82033124 ps
T263 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.319658724 Jul 15 07:11:41 PM PDT 24 Jul 15 07:11:44 PM PDT 24 24666006 ps
T1066 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3888277926 Jul 15 07:11:41 PM PDT 24 Jul 15 07:11:44 PM PDT 24 133709085 ps
T1067 /workspace/coverage/cover_reg_top/1.edn_csr_rw.179314428 Jul 15 07:11:44 PM PDT 24 Jul 15 07:11:49 PM PDT 24 24011045 ps
T1068 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2273009981 Jul 15 07:11:46 PM PDT 24 Jul 15 07:11:52 PM PDT 24 22052730 ps
T1069 /workspace/coverage/cover_reg_top/3.edn_tl_errors.432132798 Jul 15 07:11:39 PM PDT 24 Jul 15 07:11:44 PM PDT 24 201531945 ps
T1070 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3363615249 Jul 15 07:11:52 PM PDT 24 Jul 15 07:12:01 PM PDT 24 20822099 ps
T1071 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2983736885 Jul 15 07:11:47 PM PDT 24 Jul 15 07:11:54 PM PDT 24 49559855 ps
T289 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1624196324 Jul 15 07:11:46 PM PDT 24 Jul 15 07:11:54 PM PDT 24 193488446 ps
T1072 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.373927390 Jul 15 07:11:45 PM PDT 24 Jul 15 07:11:52 PM PDT 24 77303518 ps
T1073 /workspace/coverage/cover_reg_top/2.edn_csr_rw.1455397621 Jul 15 07:11:44 PM PDT 24 Jul 15 07:11:49 PM PDT 24 46487819 ps
T1074 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.700616017 Jul 15 07:11:42 PM PDT 24 Jul 15 07:11:47 PM PDT 24 87408358 ps
T1075 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2213568369 Jul 15 07:11:43 PM PDT 24 Jul 15 07:11:47 PM PDT 24 53306274 ps
T266 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.680504138 Jul 15 07:11:42 PM PDT 24 Jul 15 07:11:48 PM PDT 24 140384117 ps
T1076 /workspace/coverage/cover_reg_top/16.edn_intr_test.4233279043 Jul 15 07:11:50 PM PDT 24 Jul 15 07:11:58 PM PDT 24 41145017 ps
T1077 /workspace/coverage/cover_reg_top/14.edn_csr_rw.3294331395 Jul 15 07:11:54 PM PDT 24 Jul 15 07:12:04 PM PDT 24 18820429 ps
T1078 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3437063155 Jul 15 07:11:47 PM PDT 24 Jul 15 07:11:55 PM PDT 24 60420928 ps
T1079 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3195909755 Jul 15 07:11:48 PM PDT 24 Jul 15 07:11:55 PM PDT 24 38958137 ps
T1080 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1513661550 Jul 15 07:11:43 PM PDT 24 Jul 15 07:11:50 PM PDT 24 107208232 ps
T1081 /workspace/coverage/cover_reg_top/47.edn_intr_test.1193422050 Jul 15 07:11:57 PM PDT 24 Jul 15 07:12:06 PM PDT 24 12741903 ps
T1082 /workspace/coverage/cover_reg_top/11.edn_intr_test.1812600214 Jul 15 07:11:52 PM PDT 24 Jul 15 07:12:01 PM PDT 24 13520502 ps
T1083 /workspace/coverage/cover_reg_top/35.edn_intr_test.2297987798 Jul 15 07:11:50 PM PDT 24 Jul 15 07:11:58 PM PDT 24 76411167 ps
T288 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3162175762 Jul 15 07:11:45 PM PDT 24 Jul 15 07:11:53 PM PDT 24 1022472355 ps
T1084 /workspace/coverage/cover_reg_top/41.edn_intr_test.3809180771 Jul 15 07:11:54 PM PDT 24 Jul 15 07:12:03 PM PDT 24 13632758 ps
T1085 /workspace/coverage/cover_reg_top/37.edn_intr_test.1149402929 Jul 15 07:11:55 PM PDT 24 Jul 15 07:12:05 PM PDT 24 20724448 ps
T1086 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3180678002 Jul 15 07:11:54 PM PDT 24 Jul 15 07:12:03 PM PDT 24 32587166 ps
T1087 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2730760071 Jul 15 07:11:46 PM PDT 24 Jul 15 07:11:52 PM PDT 24 19108250 ps
T1088 /workspace/coverage/cover_reg_top/18.edn_csr_rw.761130796 Jul 15 07:11:49 PM PDT 24 Jul 15 07:11:57 PM PDT 24 12274280 ps
T1089 /workspace/coverage/cover_reg_top/14.edn_tl_errors.3917665906 Jul 15 07:11:51 PM PDT 24 Jul 15 07:12:00 PM PDT 24 107543582 ps
T267 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3801182102 Jul 15 07:11:44 PM PDT 24 Jul 15 07:11:54 PM PDT 24 182415971 ps
T1090 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1006594254 Jul 15 07:11:48 PM PDT 24 Jul 15 07:11:56 PM PDT 24 215047413 ps
T1091 /workspace/coverage/cover_reg_top/6.edn_tl_errors.2607477802 Jul 15 07:11:49 PM PDT 24 Jul 15 07:11:58 PM PDT 24 81805072 ps
T1092 /workspace/coverage/cover_reg_top/7.edn_tl_errors.3977488338 Jul 15 07:11:47 PM PDT 24 Jul 15 07:11:55 PM PDT 24 155707256 ps
T1093 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2745081682 Jul 15 07:11:48 PM PDT 24 Jul 15 07:11:56 PM PDT 24 30895680 ps
T1094 /workspace/coverage/cover_reg_top/17.edn_intr_test.1833957251 Jul 15 07:11:49 PM PDT 24 Jul 15 07:11:56 PM PDT 24 23738347 ps
T1095 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1160621088 Jul 15 07:11:47 PM PDT 24 Jul 15 07:11:55 PM PDT 24 102557164 ps
T1096 /workspace/coverage/cover_reg_top/0.edn_tl_errors.2566142868 Jul 15 07:11:43 PM PDT 24 Jul 15 07:11:49 PM PDT 24 66301125 ps
T1097 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1039523997 Jul 15 07:11:49 PM PDT 24 Jul 15 07:11:56 PM PDT 24 188833056 ps
T1098 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2034414930 Jul 15 07:11:46 PM PDT 24 Jul 15 07:11:55 PM PDT 24 1150632034 ps
T1099 /workspace/coverage/cover_reg_top/10.edn_intr_test.2844662043 Jul 15 07:11:49 PM PDT 24 Jul 15 07:11:56 PM PDT 24 40755368 ps
T1100 /workspace/coverage/cover_reg_top/6.edn_intr_test.4210584904 Jul 15 07:11:43 PM PDT 24 Jul 15 07:11:48 PM PDT 24 45636450 ps
T1101 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2466057427 Jul 15 07:11:54 PM PDT 24 Jul 15 07:12:04 PM PDT 24 36133807 ps
T1102 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.621467896 Jul 15 07:11:46 PM PDT 24 Jul 15 07:11:53 PM PDT 24 16893616 ps
T1103 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2769979718 Jul 15 07:11:50 PM PDT 24 Jul 15 07:11:58 PM PDT 24 16712128 ps
T1104 /workspace/coverage/cover_reg_top/5.edn_intr_test.3446606525 Jul 15 07:11:43 PM PDT 24 Jul 15 07:11:48 PM PDT 24 14955814 ps
T1105 /workspace/coverage/cover_reg_top/45.edn_intr_test.1803444311 Jul 15 07:11:52 PM PDT 24 Jul 15 07:12:00 PM PDT 24 38815814 ps
T264 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.459677044 Jul 15 07:11:45 PM PDT 24 Jul 15 07:11:52 PM PDT 24 70149394 ps
T1106 /workspace/coverage/cover_reg_top/38.edn_intr_test.3607985853 Jul 15 07:11:52 PM PDT 24 Jul 15 07:12:00 PM PDT 24 85267873 ps
T1107 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.442014120 Jul 15 07:11:42 PM PDT 24 Jul 15 07:11:46 PM PDT 24 63029216 ps
T1108 /workspace/coverage/cover_reg_top/8.edn_intr_test.2611349748 Jul 15 07:11:52 PM PDT 24 Jul 15 07:12:00 PM PDT 24 16173399 ps
T265 /workspace/coverage/cover_reg_top/5.edn_csr_rw.1888113737 Jul 15 07:11:47 PM PDT 24 Jul 15 07:11:53 PM PDT 24 15167241 ps
T1109 /workspace/coverage/cover_reg_top/34.edn_intr_test.1106879700 Jul 15 07:11:52 PM PDT 24 Jul 15 07:12:01 PM PDT 24 13636314 ps
T1110 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.142734385 Jul 15 07:11:43 PM PDT 24 Jul 15 07:11:48 PM PDT 24 58786549 ps
T1111 /workspace/coverage/cover_reg_top/6.edn_csr_rw.2695677212 Jul 15 07:11:45 PM PDT 24 Jul 15 07:11:51 PM PDT 24 16608533 ps
T1112 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1879609027 Jul 15 07:11:47 PM PDT 24 Jul 15 07:11:55 PM PDT 24 58726924 ps
T1113 /workspace/coverage/cover_reg_top/10.edn_csr_rw.935607074 Jul 15 07:11:49 PM PDT 24 Jul 15 07:11:57 PM PDT 24 41624190 ps
T1114 /workspace/coverage/cover_reg_top/23.edn_intr_test.2978831710 Jul 15 07:11:55 PM PDT 24 Jul 15 07:12:04 PM PDT 24 25279526 ps
T1115 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2979121434 Jul 15 07:11:49 PM PDT 24 Jul 15 07:11:56 PM PDT 24 46402421 ps
T1116 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.403062498 Jul 15 07:11:48 PM PDT 24 Jul 15 07:11:56 PM PDT 24 83675011 ps
T1117 /workspace/coverage/cover_reg_top/40.edn_intr_test.719696842 Jul 15 07:11:56 PM PDT 24 Jul 15 07:12:06 PM PDT 24 13149765 ps
T1118 /workspace/coverage/cover_reg_top/33.edn_intr_test.3742679304 Jul 15 07:11:54 PM PDT 24 Jul 15 07:12:03 PM PDT 24 18160764 ps
T1119 /workspace/coverage/cover_reg_top/31.edn_intr_test.3976633435 Jul 15 07:11:49 PM PDT 24 Jul 15 07:11:57 PM PDT 24 90139719 ps
T1120 /workspace/coverage/cover_reg_top/12.edn_csr_rw.3130502635 Jul 15 07:11:49 PM PDT 24 Jul 15 07:11:57 PM PDT 24 21680906 ps
T1121 /workspace/coverage/cover_reg_top/42.edn_intr_test.3241741982 Jul 15 07:11:51 PM PDT 24 Jul 15 07:12:00 PM PDT 24 20918287 ps
T1122 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.4040263029 Jul 15 07:11:51 PM PDT 24 Jul 15 07:12:01 PM PDT 24 302739927 ps
T1123 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1297630889 Jul 15 07:11:47 PM PDT 24 Jul 15 07:11:54 PM PDT 24 49252009 ps
T1124 /workspace/coverage/cover_reg_top/19.edn_csr_rw.2474882051 Jul 15 07:11:51 PM PDT 24 Jul 15 07:12:00 PM PDT 24 49038981 ps
T1125 /workspace/coverage/cover_reg_top/18.edn_tl_errors.2153933779 Jul 15 07:11:54 PM PDT 24 Jul 15 07:12:03 PM PDT 24 20427969 ps
T1126 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3252929631 Jul 15 07:11:46 PM PDT 24 Jul 15 07:11:53 PM PDT 24 654851277 ps
T1127 /workspace/coverage/cover_reg_top/3.edn_intr_test.2791847940 Jul 15 07:11:42 PM PDT 24 Jul 15 07:11:46 PM PDT 24 88527183 ps
T1128 /workspace/coverage/cover_reg_top/20.edn_intr_test.1785641661 Jul 15 07:11:48 PM PDT 24 Jul 15 07:11:55 PM PDT 24 43147171 ps
T1129 /workspace/coverage/cover_reg_top/19.edn_intr_test.3987885024 Jul 15 07:11:53 PM PDT 24 Jul 15 07:12:01 PM PDT 24 36245041 ps
T1130 /workspace/coverage/cover_reg_top/4.edn_intr_test.4221592212 Jul 15 07:11:43 PM PDT 24 Jul 15 07:11:48 PM PDT 24 23627142 ps

Test location /workspace/coverage/default/191.edn_genbits.947958389
Short name T3
Test name
Test status
Simulation time 279095124 ps
CPU time 3.91 seconds
Started Jul 15 07:16:52 PM PDT 24
Finished Jul 15 07:18:05 PM PDT 24
Peak memory 220484 kb
Host smart-6df3f92a-9e2a-478a-b844-b184fe30ad85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947958389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.947958389
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_alert.1527836054
Short name T48
Test name
Test status
Simulation time 24608849 ps
CPU time 1.22 seconds
Started Jul 15 07:14:10 PM PDT 24
Finished Jul 15 07:15:53 PM PDT 24
Peak memory 219116 kb
Host smart-dc0bd048-a1a2-44d4-ac57-f9c1e032b78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527836054 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.1527836054
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.2888518947
Short name T41
Test name
Test status
Simulation time 580023647895 ps
CPU time 1289.61 seconds
Started Jul 15 07:12:57 PM PDT 24
Finished Jul 15 07:35:22 PM PDT 24
Peak memory 234992 kb
Host smart-423b05e8-e301-40bc-9b7f-0946f4596cea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888518947 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.2888518947
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/187.edn_genbits.522458721
Short name T43
Test name
Test status
Simulation time 32639453 ps
CPU time 1.33 seconds
Started Jul 15 07:16:44 PM PDT 24
Finished Jul 15 07:17:44 PM PDT 24
Peak memory 217952 kb
Host smart-77613523-c2e9-4edd-86f8-bbce68145a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522458721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.522458721
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_sec_cm.2360052757
Short name T18
Test name
Test status
Simulation time 439759407 ps
CPU time 6.65 seconds
Started Jul 15 07:13:06 PM PDT 24
Finished Jul 15 07:14:31 PM PDT 24
Peak memory 236832 kb
Host smart-9cfb20bf-92e9-4e23-a6cd-0bf63f62eb3d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360052757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.2360052757
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/64.edn_err.2174679804
Short name T10
Test name
Test status
Simulation time 25500568 ps
CPU time 1 seconds
Started Jul 15 07:15:03 PM PDT 24
Finished Jul 15 07:16:22 PM PDT 24
Peak memory 220180 kb
Host smart-b550c502-4d6a-47c4-beba-001ee72742d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174679804 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.2174679804
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/17.edn_disable.2559714820
Short name T91
Test name
Test status
Simulation time 13694721 ps
CPU time 0.82 seconds
Started Jul 15 07:13:24 PM PDT 24
Finished Jul 15 07:14:55 PM PDT 24
Peak memory 216616 kb
Host smart-417ff892-5b86-4381-b5d4-08c477807b94
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559714820 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.2559714820
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/4.edn_regwen.2061330728
Short name T27
Test name
Test status
Simulation time 141145470 ps
CPU time 0.92 seconds
Started Jul 15 07:12:59 PM PDT 24
Finished Jul 15 07:14:06 PM PDT 24
Peak memory 207372 kb
Host smart-d17ab670-1adc-4ea1-89f0-b99cc3ae23db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061330728 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.2061330728
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/79.edn_alert.2616884654
Short name T107
Test name
Test status
Simulation time 79624676 ps
CPU time 1.17 seconds
Started Jul 15 07:15:15 PM PDT 24
Finished Jul 15 07:16:29 PM PDT 24
Peak memory 218716 kb
Host smart-a4353272-ccdf-4d3d-9344-b7cb0bfeee40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616884654 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.2616884654
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.4215283955
Short name T123
Test name
Test status
Simulation time 37190498 ps
CPU time 1.21 seconds
Started Jul 15 07:14:09 PM PDT 24
Finished Jul 15 07:15:53 PM PDT 24
Peak memory 217204 kb
Host smart-1ff72e1e-eec9-4ec7-8d60-01c935b14957
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215283955 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.4215283955
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_alert.3532976941
Short name T120
Test name
Test status
Simulation time 51948093 ps
CPU time 1.2 seconds
Started Jul 15 07:14:50 PM PDT 24
Finished Jul 15 07:16:19 PM PDT 24
Peak memory 216044 kb
Host smart-d4c782e8-312f-473e-9aaf-122dc55f3c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532976941 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.3532976941
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/158.edn_alert.600078322
Short name T104
Test name
Test status
Simulation time 27046909 ps
CPU time 1.2 seconds
Started Jul 15 07:16:39 PM PDT 24
Finished Jul 15 07:17:35 PM PDT 24
Peak memory 220064 kb
Host smart-410096bd-2945-40ab-86f0-fad1e9549445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600078322 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.600078322
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.2926245008
Short name T60
Test name
Test status
Simulation time 22389824 ps
CPU time 1.01 seconds
Started Jul 15 07:15:05 PM PDT 24
Finished Jul 15 07:16:24 PM PDT 24
Peak memory 224228 kb
Host smart-157663f7-7778-4486-87b6-0904892fb874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926245008 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.2926245008
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/219.edn_genbits.4122427298
Short name T85
Test name
Test status
Simulation time 79361462 ps
CPU time 2.08 seconds
Started Jul 15 07:17:00 PM PDT 24
Finished Jul 15 07:18:25 PM PDT 24
Peak memory 218016 kb
Host smart-5c7a9cd8-33a7-4dc4-892b-301f6ea31506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122427298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.4122427298
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.853220304
Short name T279
Test name
Test status
Simulation time 256589608 ps
CPU time 2.14 seconds
Started Jul 15 07:11:47 PM PDT 24
Finished Jul 15 07:11:56 PM PDT 24
Peak memory 206952 kb
Host smart-eb843d2a-e0a2-4d48-9213-feecd6ba603f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853220304 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.853220304
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3662716300
Short name T255
Test name
Test status
Simulation time 38164746 ps
CPU time 1.54 seconds
Started Jul 15 07:11:42 PM PDT 24
Finished Jul 15 07:11:46 PM PDT 24
Peak memory 206956 kb
Host smart-1b0f3128-c14d-4c62-b520-504e6c2def27
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662716300 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.3662716300
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.3824721865
Short name T118
Test name
Test status
Simulation time 106127753 ps
CPU time 1.13 seconds
Started Jul 15 07:14:21 PM PDT 24
Finished Jul 15 07:15:59 PM PDT 24
Peak memory 217092 kb
Host smart-375d0342-572b-4972-be31-4a63369efe44
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824721865 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.3824721865
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_disable.2589441166
Short name T225
Test name
Test status
Simulation time 32589516 ps
CPU time 0.81 seconds
Started Jul 15 07:12:49 PM PDT 24
Finished Jul 15 07:13:31 PM PDT 24
Peak memory 216532 kb
Host smart-779a00b4-999c-4cfc-b00d-7160b9c4ac10
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589441166 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.2589441166
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable.3417864286
Short name T204
Test name
Test status
Simulation time 27154532 ps
CPU time 0.82 seconds
Started Jul 15 07:13:03 PM PDT 24
Finished Jul 15 07:14:16 PM PDT 24
Peak memory 216504 kb
Host smart-2e617181-798b-4654-85f5-31f3d3c4befa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417864286 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3417864286
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable.1103909657
Short name T177
Test name
Test status
Simulation time 22226121 ps
CPU time 0.84 seconds
Started Jul 15 07:13:42 PM PDT 24
Finished Jul 15 07:15:21 PM PDT 24
Peak memory 216536 kb
Host smart-8b58ca80-b63d-43a1-80be-6e0239f94ea6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103909657 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1103909657
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/152.edn_alert.2714008541
Short name T112
Test name
Test status
Simulation time 116529403 ps
CPU time 1.07 seconds
Started Jul 15 07:16:32 PM PDT 24
Finished Jul 15 07:17:23 PM PDT 24
Peak memory 221160 kb
Host smart-c76196b4-9b2c-4ffe-a98f-f5db6ac640bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714008541 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.2714008541
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/156.edn_alert.615547853
Short name T234
Test name
Test status
Simulation time 39558212 ps
CPU time 1.2 seconds
Started Jul 15 07:16:30 PM PDT 24
Finished Jul 15 07:17:18 PM PDT 24
Peak memory 220088 kb
Host smart-c1fd7162-23b5-4d46-916d-04f8a9a08de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615547853 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.615547853
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.3966267708
Short name T76
Test name
Test status
Simulation time 248813196354 ps
CPU time 1504.14 seconds
Started Jul 15 07:13:50 PM PDT 24
Finished Jul 15 07:40:38 PM PDT 24
Peak memory 224584 kb
Host smart-7d1048b1-278e-4d01-b1de-48ef6c28abd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966267708 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.3966267708
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.edn_alert.661729443
Short name T125
Test name
Test status
Simulation time 86087278 ps
CPU time 1.3 seconds
Started Jul 15 07:13:25 PM PDT 24
Finished Jul 15 07:15:09 PM PDT 24
Peak memory 215912 kb
Host smart-ba8ecd1d-61a1-4472-b225-d2eba0a49be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661729443 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.661729443
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/168.edn_alert.2780072673
Short name T186
Test name
Test status
Simulation time 28830089 ps
CPU time 1.22 seconds
Started Jul 15 07:16:38 PM PDT 24
Finished Jul 15 07:17:35 PM PDT 24
Peak memory 220068 kb
Host smart-21c2fa5e-410c-435a-9fb4-a6eb9fb0ff31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780072673 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.2780072673
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/118.edn_alert.2232425966
Short name T491
Test name
Test status
Simulation time 39194152 ps
CPU time 1.12 seconds
Started Jul 15 07:16:09 PM PDT 24
Finished Jul 15 07:16:59 PM PDT 24
Peak memory 220164 kb
Host smart-88341fcb-aaa5-4534-b487-942bcb6d6619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232425966 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.2232425966
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/119.edn_alert.829690497
Short name T873
Test name
Test status
Simulation time 24236201 ps
CPU time 1.22 seconds
Started Jul 15 07:16:07 PM PDT 24
Finished Jul 15 07:16:58 PM PDT 24
Peak memory 220272 kb
Host smart-38645456-6c79-4f25-9877-1150bc09258e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829690497 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.829690497
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/12.edn_disable.4237500880
Short name T89
Test name
Test status
Simulation time 14585284 ps
CPU time 0.91 seconds
Started Jul 15 07:13:02 PM PDT 24
Finished Jul 15 07:14:15 PM PDT 24
Peak memory 216728 kb
Host smart-8c93f9fa-b2dd-4bc1-bba2-d4a7c45aae42
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237500880 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.4237500880
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/127.edn_alert.3331488631
Short name T138
Test name
Test status
Simulation time 80299207 ps
CPU time 1.2 seconds
Started Jul 15 07:16:05 PM PDT 24
Finished Jul 15 07:16:56 PM PDT 24
Peak memory 220336 kb
Host smart-ef678914-ba61-47f0-a1af-0e07d8d51e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331488631 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.3331488631
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert.890029297
Short name T100
Test name
Test status
Simulation time 25156028 ps
CPU time 1.25 seconds
Started Jul 15 07:13:10 PM PDT 24
Finished Jul 15 07:14:32 PM PDT 24
Peak memory 219840 kb
Host smart-b1a3c031-c336-45c5-9cbe-256de60c1399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890029297 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.890029297
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/149.edn_alert.89659161
Short name T181
Test name
Test status
Simulation time 73177429 ps
CPU time 1.07 seconds
Started Jul 15 07:16:25 PM PDT 24
Finished Jul 15 07:17:12 PM PDT 24
Peak memory 218820 kb
Host smart-cac95793-425b-4d41-a3ad-e24eeac03d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89659161 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.89659161
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/193.edn_alert.220047895
Short name T135
Test name
Test status
Simulation time 91071488 ps
CPU time 1.33 seconds
Started Jul 15 07:16:53 PM PDT 24
Finished Jul 15 07:18:03 PM PDT 24
Peak memory 220244 kb
Host smart-33b193e7-11d7-4458-b27e-9225071f6f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220047895 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.220047895
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/9.edn_intr.3078877893
Short name T36
Test name
Test status
Simulation time 26716657 ps
CPU time 0.91 seconds
Started Jul 15 07:12:59 PM PDT 24
Finished Jul 15 07:14:00 PM PDT 24
Peak memory 216040 kb
Host smart-aa5d0b14-74c6-453b-8d39-05c84dc12989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078877893 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.3078877893
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/16.edn_genbits.607010656
Short name T301
Test name
Test status
Simulation time 113651767 ps
CPU time 1.08 seconds
Started Jul 15 07:13:21 PM PDT 24
Finished Jul 15 07:14:54 PM PDT 24
Peak memory 220464 kb
Host smart-69abec89-229a-4063-9149-d4530f152001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607010656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.607010656
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_disable.1536686236
Short name T161
Test name
Test status
Simulation time 12352240 ps
CPU time 0.92 seconds
Started Jul 15 07:13:25 PM PDT 24
Finished Jul 15 07:15:00 PM PDT 24
Peak memory 215876 kb
Host smart-4f27b4c2-d81f-4e97-8965-207736635697
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536686236 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.1536686236
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable.746103440
Short name T190
Test name
Test status
Simulation time 40363259 ps
CPU time 0.85 seconds
Started Jul 15 07:14:03 PM PDT 24
Finished Jul 15 07:15:45 PM PDT 24
Peak memory 216628 kb
Host smart-df528bbc-220f-41f3-919e-fd464dda0a86
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746103440 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.746103440
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/58.edn_alert.1816643115
Short name T977
Test name
Test status
Simulation time 45165821 ps
CPU time 1.14 seconds
Started Jul 15 07:15:00 PM PDT 24
Finished Jul 15 07:16:23 PM PDT 24
Peak memory 218928 kb
Host smart-6c7d4b9b-10b2-4555-969a-e2ddfecee20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816643115 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.1816643115
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/0.edn_intr.893239767
Short name T99
Test name
Test status
Simulation time 21722796 ps
CPU time 0.9 seconds
Started Jul 15 07:12:46 PM PDT 24
Finished Jul 15 07:13:22 PM PDT 24
Peak memory 216016 kb
Host smart-7e7e922f-8a13-47d6-9b9f-c920531cc285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893239767 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.893239767
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.2849131348
Short name T950
Test name
Test status
Simulation time 50215998 ps
CPU time 1.53 seconds
Started Jul 15 07:12:46 PM PDT 24
Finished Jul 15 07:13:26 PM PDT 24
Peak memory 217132 kb
Host smart-8c6eb0d1-d57b-45eb-a4f7-b33f3b81b339
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849131348 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.2849131348
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2319516722
Short name T217
Test name
Test status
Simulation time 371716278 ps
CPU time 1.21 seconds
Started Jul 15 07:12:58 PM PDT 24
Finished Jul 15 07:13:59 PM PDT 24
Peak memory 217248 kb
Host smart-605fe08e-b385-44b1-8646-d4133299911d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319516722 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2319516722
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.1250087549
Short name T144
Test name
Test status
Simulation time 100834346 ps
CPU time 1.08 seconds
Started Jul 15 07:13:02 PM PDT 24
Finished Jul 15 07:14:16 PM PDT 24
Peak memory 217204 kb
Host smart-b1d67312-56b7-4946-b81a-512862ca011e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250087549 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.1250087549
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.3397368930
Short name T196
Test name
Test status
Simulation time 18856454 ps
CPU time 1.07 seconds
Started Jul 15 07:13:02 PM PDT 24
Finished Jul 15 07:14:17 PM PDT 24
Peak memory 218732 kb
Host smart-9dd40c6c-0b13-441e-9351-01170b9cceb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397368930 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3397368930
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/173.edn_alert.111627190
Short name T471
Test name
Test status
Simulation time 71895985 ps
CPU time 1.17 seconds
Started Jul 15 07:16:42 PM PDT 24
Finished Jul 15 07:17:38 PM PDT 24
Peak memory 219904 kb
Host smart-f82e28c3-0ad9-4f88-88d2-05dc96e57005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111627190 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.111627190
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/22.edn_disable.4116522342
Short name T208
Test name
Test status
Simulation time 57952965 ps
CPU time 0.88 seconds
Started Jul 15 07:13:39 PM PDT 24
Finished Jul 15 07:15:20 PM PDT 24
Peak memory 216532 kb
Host smart-407c6d56-a5fc-4e4a-bcb6-f86f7a25c35e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116522342 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.4116522342
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.743774518
Short name T133
Test name
Test status
Simulation time 45287763 ps
CPU time 1.32 seconds
Started Jul 15 07:13:43 PM PDT 24
Finished Jul 15 07:15:28 PM PDT 24
Peak memory 218504 kb
Host smart-95efceca-188a-47bd-93ed-874551e51646
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743774518 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_di
sable_auto_req_mode.743774518
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.3715958682
Short name T983
Test name
Test status
Simulation time 74575179 ps
CPU time 0.88 seconds
Started Jul 15 07:13:42 PM PDT 24
Finished Jul 15 07:15:21 PM PDT 24
Peak memory 229548 kb
Host smart-324f7561-b22c-4c2f-837b-2e49d348cef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715958682 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.3715958682
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/44.edn_disable.671814414
Short name T192
Test name
Test status
Simulation time 23919312 ps
CPU time 0.78 seconds
Started Jul 15 07:14:52 PM PDT 24
Finished Jul 15 07:16:17 PM PDT 24
Peak memory 216500 kb
Host smart-e171154b-fbc0-4a98-9bf8-b5ef4bdd1717
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671814414 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.671814414
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/53.edn_err.2999516953
Short name T185
Test name
Test status
Simulation time 35544606 ps
CPU time 0.89 seconds
Started Jul 15 07:15:00 PM PDT 24
Finished Jul 15 07:16:22 PM PDT 24
Peak memory 218628 kb
Host smart-196b3062-7514-4276-b601-d0e11def22b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999516953 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2999516953
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/9.edn_disable.3944634750
Short name T201
Test name
Test status
Simulation time 14777053 ps
CPU time 0.92 seconds
Started Jul 15 07:13:07 PM PDT 24
Finished Jul 15 07:14:25 PM PDT 24
Peak memory 216732 kb
Host smart-658592e6-2096-4dfa-81ee-3b1064ea5922
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944634750 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.3944634750
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/47.edn_genbits.3136695775
Short name T13
Test name
Test status
Simulation time 167799504 ps
CPU time 1.25 seconds
Started Jul 15 07:14:46 PM PDT 24
Finished Jul 15 07:16:12 PM PDT 24
Peak memory 220000 kb
Host smart-9b40cfed-96b3-4770-84ac-9abfd67c1f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136695775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3136695775
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_alert_test.4144005999
Short name T1
Test name
Test status
Simulation time 17270282 ps
CPU time 0.9 seconds
Started Jul 15 07:13:03 PM PDT 24
Finished Jul 15 07:14:17 PM PDT 24
Peak memory 215264 kb
Host smart-1786d301-9dfa-40ba-987b-b41fc42eb779
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144005999 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.4144005999
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/58.edn_genbits.232977702
Short name T26
Test name
Test status
Simulation time 32546160 ps
CPU time 1.57 seconds
Started Jul 15 07:15:03 PM PDT 24
Finished Jul 15 07:16:24 PM PDT 24
Peak memory 218816 kb
Host smart-dff5029b-aad5-411a-9213-3e0c7e5ac2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232977702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.232977702
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.2605581023
Short name T318
Test name
Test status
Simulation time 161966744858 ps
CPU time 837.44 seconds
Started Jul 15 07:12:52 PM PDT 24
Finished Jul 15 07:27:35 PM PDT 24
Peak memory 220952 kb
Host smart-8a9a96e8-f0bf-4c2b-84bc-f01c45d171cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605581023 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.2605581023
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/104.edn_genbits.2504096097
Short name T350
Test name
Test status
Simulation time 53206619 ps
CPU time 1.55 seconds
Started Jul 15 07:15:56 PM PDT 24
Finished Jul 15 07:16:50 PM PDT 24
Peak memory 218932 kb
Host smart-e7f1cc73-c951-4edf-82d4-95dccec84ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504096097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.2504096097
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.3076452479
Short name T306
Test name
Test status
Simulation time 28896308 ps
CPU time 1.22 seconds
Started Jul 15 07:16:00 PM PDT 24
Finished Jul 15 07:16:53 PM PDT 24
Peak memory 217500 kb
Host smart-85af119a-f4bd-454d-8e9e-382c0ae264a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076452479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3076452479
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.3495657967
Short name T972
Test name
Test status
Simulation time 29948947 ps
CPU time 1.19 seconds
Started Jul 15 07:13:03 PM PDT 24
Finished Jul 15 07:14:17 PM PDT 24
Peak memory 221464 kb
Host smart-0e967133-be2a-48c9-bd7f-1f61cd6cfc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495657967 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.3495657967
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/49.edn_intr.570530790
Short name T37
Test name
Test status
Simulation time 20829632 ps
CPU time 1.15 seconds
Started Jul 15 07:14:53 PM PDT 24
Finished Jul 15 07:16:18 PM PDT 24
Peak memory 217156 kb
Host smart-05d4a359-eaf3-4d37-b92b-7abfa813c6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570530790 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.570530790
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.258222182
Short name T273
Test name
Test status
Simulation time 16992973 ps
CPU time 1.03 seconds
Started Jul 15 07:11:43 PM PDT 24
Finished Jul 15 07:11:48 PM PDT 24
Peak memory 206900 kb
Host smart-ce8bae55-69cb-42fc-adc5-b1f3545d78e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258222182 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_out
standing.258222182
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/default/17.edn_err.4102366474
Short name T9
Test name
Test status
Simulation time 110843969 ps
CPU time 0.98 seconds
Started Jul 15 07:13:25 PM PDT 24
Finished Jul 15 07:15:09 PM PDT 24
Peak memory 220008 kb
Host smart-0685afaf-6198-4c07-a5d8-25db0f2d6ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102366474 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.4102366474
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3162175762
Short name T288
Test name
Test status
Simulation time 1022472355 ps
CPU time 2.35 seconds
Started Jul 15 07:11:45 PM PDT 24
Finished Jul 15 07:11:53 PM PDT 24
Peak memory 206928 kb
Host smart-98e7cc67-6ba7-4e48-9cab-9315f2d7485f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162175762 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.3162175762
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_genbits.3981731847
Short name T539
Test name
Test status
Simulation time 95728596 ps
CPU time 1.41 seconds
Started Jul 15 07:12:59 PM PDT 24
Finished Jul 15 07:14:00 PM PDT 24
Peak memory 217580 kb
Host smart-de3f6ad1-f183-41ef-9ad0-cd5a7c7cbd1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981731847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.3981731847
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.2206426828
Short name T421
Test name
Test status
Simulation time 78601958 ps
CPU time 1.21 seconds
Started Jul 15 07:15:53 PM PDT 24
Finished Jul 15 07:16:47 PM PDT 24
Peak memory 217656 kb
Host smart-5dd10f06-8c6d-4013-91d3-2cf5661f8c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206426828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.2206426828
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.423190786
Short name T315
Test name
Test status
Simulation time 241050097 ps
CPU time 3.05 seconds
Started Jul 15 07:15:55 PM PDT 24
Finished Jul 15 07:16:51 PM PDT 24
Peak memory 220400 kb
Host smart-e047fb7a-a965-4619-bee6-46f8be6a9102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423190786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.423190786
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.1900844901
Short name T309
Test name
Test status
Simulation time 36809445 ps
CPU time 1.11 seconds
Started Jul 15 07:15:53 PM PDT 24
Finished Jul 15 07:16:47 PM PDT 24
Peak memory 218952 kb
Host smart-a5d7f3fb-86a4-4a85-bbd4-39468137a662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900844901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1900844901
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_genbits.2368396818
Short name T84
Test name
Test status
Simulation time 93625135 ps
CPU time 1.47 seconds
Started Jul 15 07:13:01 PM PDT 24
Finished Jul 15 07:14:08 PM PDT 24
Peak memory 218948 kb
Host smart-e16cc54f-b38d-431d-81d6-682d33f7349e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368396818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2368396818
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_genbits.3735060607
Short name T326
Test name
Test status
Simulation time 153216165 ps
CPU time 1.76 seconds
Started Jul 15 07:13:12 PM PDT 24
Finished Jul 15 07:14:33 PM PDT 24
Peak memory 218996 kb
Host smart-cd7aa76a-3913-4270-8d02-2b9dc5f8391c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735060607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3735060607
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.2075340386
Short name T939
Test name
Test status
Simulation time 37061777 ps
CPU time 1.43 seconds
Started Jul 15 07:16:30 PM PDT 24
Finished Jul 15 07:17:18 PM PDT 24
Peak memory 220096 kb
Host smart-049125c1-ff77-49fb-a5d3-b27860b559c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075340386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.2075340386
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/160.edn_genbits.548927869
Short name T817
Test name
Test status
Simulation time 39880802 ps
CPU time 1.12 seconds
Started Jul 15 07:16:40 PM PDT 24
Finished Jul 15 07:17:35 PM PDT 24
Peak memory 220280 kb
Host smart-a2cf1006-e40c-4ae0-88ac-3384e1b15b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548927869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.548927869
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.3863550674
Short name T302
Test name
Test status
Simulation time 73876261 ps
CPU time 1.3 seconds
Started Jul 15 07:16:53 PM PDT 24
Finished Jul 15 07:18:03 PM PDT 24
Peak memory 219008 kb
Host smart-c8cd1a7b-5f00-4f6c-99de-709415863b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863550674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3863550674
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_genbits.2523226527
Short name T314
Test name
Test status
Simulation time 35343173 ps
CPU time 1.28 seconds
Started Jul 15 07:13:34 PM PDT 24
Finished Jul 15 07:15:12 PM PDT 24
Peak memory 219028 kb
Host smart-6ba1f4b1-b4d4-4c11-a863-2605b741090b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523226527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2523226527
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_alert.1303703274
Short name T158
Test name
Test status
Simulation time 52738524 ps
CPU time 1.18 seconds
Started Jul 15 07:14:17 PM PDT 24
Finished Jul 15 07:15:58 PM PDT 24
Peak memory 218756 kb
Host smart-bf683cf8-c05e-4f2a-aa27-2c0e0a81bb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303703274 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.1303703274
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/12.edn_intr.1156154851
Short name T38
Test name
Test status
Simulation time 110675868 ps
CPU time 0.79 seconds
Started Jul 15 07:13:02 PM PDT 24
Finished Jul 15 07:14:15 PM PDT 24
Peak memory 215764 kb
Host smart-3d24edb6-b24f-4592-a9da-21041e87824f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156154851 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.1156154851
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/45.edn_alert.234058336
Short name T114
Test name
Test status
Simulation time 29724566 ps
CPU time 1.1 seconds
Started Jul 15 07:14:44 PM PDT 24
Finished Jul 15 07:16:14 PM PDT 24
Peak memory 218920 kb
Host smart-fba7da56-3308-43c8-bc8a-52d33d74e46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234058336 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.234058336
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.3210924339
Short name T577
Test name
Test status
Simulation time 27149906 ps
CPU time 1.33 seconds
Started Jul 15 07:16:40 PM PDT 24
Finished Jul 15 07:17:36 PM PDT 24
Peak memory 217764 kb
Host smart-e1f8731a-5efa-4cee-bb13-d93c8d660707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210924339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.3210924339
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.4178348660
Short name T262
Test name
Test status
Simulation time 36849567 ps
CPU time 1.23 seconds
Started Jul 15 07:11:41 PM PDT 24
Finished Jul 15 07:11:45 PM PDT 24
Peak memory 207052 kb
Host smart-e6c61969-8a34-4117-be08-2ceb6abb65c5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178348660 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.4178348660
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.680504138
Short name T266
Test name
Test status
Simulation time 140384117 ps
CPU time 3.59 seconds
Started Jul 15 07:11:42 PM PDT 24
Finished Jul 15 07:11:48 PM PDT 24
Peak memory 206884 kb
Host smart-e8712d77-65f3-4886-9dec-6af2691740ac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680504138 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.680504138
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.4190482686
Short name T1060
Test name
Test status
Simulation time 38871324 ps
CPU time 0.9 seconds
Started Jul 15 07:11:42 PM PDT 24
Finished Jul 15 07:11:46 PM PDT 24
Peak memory 206880 kb
Host smart-3bb68913-2f65-4616-8b06-0383fbb10f5e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190482686 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.4190482686
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2467915145
Short name T1008
Test name
Test status
Simulation time 30804406 ps
CPU time 1.07 seconds
Started Jul 15 07:11:40 PM PDT 24
Finished Jul 15 07:11:42 PM PDT 24
Peak memory 215252 kb
Host smart-4e240d8d-faf2-4420-a088-ada54bb128a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467915145 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2467915145
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.1072218645
Short name T1056
Test name
Test status
Simulation time 17434601 ps
CPU time 0.85 seconds
Started Jul 15 07:11:41 PM PDT 24
Finished Jul 15 07:11:44 PM PDT 24
Peak memory 206908 kb
Host smart-7918147c-0003-49b8-9267-032e474307b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072218645 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.1072218645
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.3935421978
Short name T1015
Test name
Test status
Simulation time 15018932 ps
CPU time 0.8 seconds
Started Jul 15 07:11:41 PM PDT 24
Finished Jul 15 07:11:43 PM PDT 24
Peak memory 206664 kb
Host smart-49a94628-a749-4373-bd0c-b213a67a4404
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935421978 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.3935421978
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.2566142868
Short name T1096
Test name
Test status
Simulation time 66301125 ps
CPU time 2.01 seconds
Started Jul 15 07:11:43 PM PDT 24
Finished Jul 15 07:11:49 PM PDT 24
Peak memory 215156 kb
Host smart-1653b2b9-b3d4-433f-aa09-9ba029a2a923
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566142868 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.2566142868
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2630160192
Short name T278
Test name
Test status
Simulation time 552547435 ps
CPU time 2.52 seconds
Started Jul 15 07:11:47 PM PDT 24
Finished Jul 15 07:11:56 PM PDT 24
Peak memory 206980 kb
Host smart-686ba56a-51da-4b43-87fe-726d6e1fabe6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630160192 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.2630160192
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3184563729
Short name T261
Test name
Test status
Simulation time 43536726 ps
CPU time 1.57 seconds
Started Jul 15 07:11:40 PM PDT 24
Finished Jul 15 07:11:43 PM PDT 24
Peak memory 206960 kb
Host smart-b38bdb11-5d49-4e88-891a-03511c374564
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184563729 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.3184563729
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2598365911
Short name T257
Test name
Test status
Simulation time 59447915 ps
CPU time 3.24 seconds
Started Jul 15 07:11:43 PM PDT 24
Finished Jul 15 07:11:50 PM PDT 24
Peak memory 207012 kb
Host smart-6363cf99-2e3e-46d6-96a6-a660c8059562
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598365911 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2598365911
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.319658724
Short name T263
Test name
Test status
Simulation time 24666006 ps
CPU time 0.86 seconds
Started Jul 15 07:11:41 PM PDT 24
Finished Jul 15 07:11:44 PM PDT 24
Peak memory 206928 kb
Host smart-3e3f5121-5fd3-4fdc-91d8-71019e14fe11
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319658724 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.319658724
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.142734385
Short name T1110
Test name
Test status
Simulation time 58786549 ps
CPU time 1.36 seconds
Started Jul 15 07:11:43 PM PDT 24
Finished Jul 15 07:11:48 PM PDT 24
Peak memory 215144 kb
Host smart-f904377e-b385-4450-b032-ab3f1ab235dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142734385 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.142734385
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.179314428
Short name T1067
Test name
Test status
Simulation time 24011045 ps
CPU time 0.85 seconds
Started Jul 15 07:11:44 PM PDT 24
Finished Jul 15 07:11:49 PM PDT 24
Peak memory 206888 kb
Host smart-f05db439-aaa5-4781-8532-f46367a64c2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179314428 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.179314428
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.56891181
Short name T1001
Test name
Test status
Simulation time 54601425 ps
CPU time 0.87 seconds
Started Jul 15 07:11:42 PM PDT 24
Finished Jul 15 07:11:45 PM PDT 24
Peak memory 206816 kb
Host smart-3e8312f1-48f9-430e-ae88-3da7f5970283
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56891181 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.56891181
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.442014120
Short name T1107
Test name
Test status
Simulation time 63029216 ps
CPU time 1.43 seconds
Started Jul 15 07:11:42 PM PDT 24
Finished Jul 15 07:11:46 PM PDT 24
Peak memory 206936 kb
Host smart-a2c2522e-bb7f-4937-9287-52ee78b92fac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442014120 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_out
standing.442014120
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.541222310
Short name T1031
Test name
Test status
Simulation time 54200714 ps
CPU time 1.96 seconds
Started Jul 15 07:11:42 PM PDT 24
Finished Jul 15 07:11:46 PM PDT 24
Peak memory 223468 kb
Host smart-9400a79e-5ed7-4324-89b4-b0bddf9fe48c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541222310 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.541222310
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.700616017
Short name T1074
Test name
Test status
Simulation time 87408358 ps
CPU time 2.25 seconds
Started Jul 15 07:11:42 PM PDT 24
Finished Jul 15 07:11:47 PM PDT 24
Peak memory 206964 kb
Host smart-b66316c3-efb2-41da-84bb-760f9ff05147
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700616017 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.700616017
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.731427776
Short name T1033
Test name
Test status
Simulation time 30497232 ps
CPU time 1.37 seconds
Started Jul 15 07:11:48 PM PDT 24
Finished Jul 15 07:11:55 PM PDT 24
Peak memory 218520 kb
Host smart-50d12898-2dff-4e2c-a311-a620a04ca604
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731427776 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.731427776
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.935607074
Short name T1113
Test name
Test status
Simulation time 41624190 ps
CPU time 0.87 seconds
Started Jul 15 07:11:49 PM PDT 24
Finished Jul 15 07:11:57 PM PDT 24
Peak memory 206792 kb
Host smart-a033267d-c10a-4d2c-af4d-c5746849db3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935607074 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.935607074
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2844662043
Short name T1099
Test name
Test status
Simulation time 40755368 ps
CPU time 0.89 seconds
Started Jul 15 07:11:49 PM PDT 24
Finished Jul 15 07:11:56 PM PDT 24
Peak memory 206692 kb
Host smart-efd149b6-8d66-4751-9733-49685772c74f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844662043 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2844662043
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2979121434
Short name T1115
Test name
Test status
Simulation time 46402421 ps
CPU time 1 seconds
Started Jul 15 07:11:49 PM PDT 24
Finished Jul 15 07:11:56 PM PDT 24
Peak memory 206932 kb
Host smart-637711c8-7e08-4b2a-b74c-e713964d43ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979121434 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2979121434
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.355789632
Short name T997
Test name
Test status
Simulation time 22072531 ps
CPU time 1.57 seconds
Started Jul 15 07:11:49 PM PDT 24
Finished Jul 15 07:11:57 PM PDT 24
Peak memory 215120 kb
Host smart-57db0e62-9030-45ff-b4d0-0cc65df4ce93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355789632 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.355789632
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1160621088
Short name T1095
Test name
Test status
Simulation time 102557164 ps
CPU time 1.47 seconds
Started Jul 15 07:11:47 PM PDT 24
Finished Jul 15 07:11:55 PM PDT 24
Peak memory 206892 kb
Host smart-21881d8d-0765-473f-91d0-e984bf7e9542
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160621088 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1160621088
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1631068834
Short name T1002
Test name
Test status
Simulation time 41276705 ps
CPU time 1.21 seconds
Started Jul 15 07:11:46 PM PDT 24
Finished Jul 15 07:11:53 PM PDT 24
Peak memory 215120 kb
Host smart-236941cc-f0c3-4189-87f5-6495f261d2e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631068834 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.1631068834
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.1791652370
Short name T1035
Test name
Test status
Simulation time 41629112 ps
CPU time 0.9 seconds
Started Jul 15 07:11:49 PM PDT 24
Finished Jul 15 07:11:57 PM PDT 24
Peak memory 206852 kb
Host smart-8cab0194-68ea-4285-a811-3d705b733294
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791652370 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1791652370
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.1812600214
Short name T1082
Test name
Test status
Simulation time 13520502 ps
CPU time 0.86 seconds
Started Jul 15 07:11:52 PM PDT 24
Finished Jul 15 07:12:01 PM PDT 24
Peak memory 206852 kb
Host smart-c1f1e211-3cce-4d0a-a9d6-2db41540ef3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812600214 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1812600214
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1241587606
Short name T1053
Test name
Test status
Simulation time 90425977 ps
CPU time 1.19 seconds
Started Jul 15 07:11:47 PM PDT 24
Finished Jul 15 07:11:55 PM PDT 24
Peak memory 206928 kb
Host smart-c48659bf-556a-472a-a92d-aa28314d91c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241587606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.1241587606
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.2220020991
Short name T1048
Test name
Test status
Simulation time 290844722 ps
CPU time 4.23 seconds
Started Jul 15 07:11:47 PM PDT 24
Finished Jul 15 07:11:57 PM PDT 24
Peak memory 215188 kb
Host smart-f9197db9-79cb-4b12-8412-626282bf735b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220020991 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2220020991
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3787409704
Short name T1037
Test name
Test status
Simulation time 30496426 ps
CPU time 1.89 seconds
Started Jul 15 07:11:47 PM PDT 24
Finished Jul 15 07:11:54 PM PDT 24
Peak memory 215160 kb
Host smart-ea988c91-17e5-42b3-b2df-0b07fa122336
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787409704 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.3787409704
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.3130502635
Short name T1120
Test name
Test status
Simulation time 21680906 ps
CPU time 0.86 seconds
Started Jul 15 07:11:49 PM PDT 24
Finished Jul 15 07:11:57 PM PDT 24
Peak memory 206968 kb
Host smart-dd689a83-6d1b-4c88-93db-0c6a378a6fdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130502635 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.3130502635
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.4003911532
Short name T1057
Test name
Test status
Simulation time 16243448 ps
CPU time 0.99 seconds
Started Jul 15 07:11:48 PM PDT 24
Finished Jul 15 07:11:55 PM PDT 24
Peak memory 206876 kb
Host smart-3707113e-bb9e-4adf-8483-e6eeac949878
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003911532 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.4003911532
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.403062498
Short name T1116
Test name
Test status
Simulation time 83675011 ps
CPU time 1.39 seconds
Started Jul 15 07:11:48 PM PDT 24
Finished Jul 15 07:11:56 PM PDT 24
Peak memory 206932 kb
Host smart-8b2fcb80-3e37-4abc-bf9d-b19eec1c04db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403062498 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_ou
tstanding.403062498
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.1930210060
Short name T1045
Test name
Test status
Simulation time 113972608 ps
CPU time 2.19 seconds
Started Jul 15 07:11:50 PM PDT 24
Finished Jul 15 07:11:59 PM PDT 24
Peak memory 215228 kb
Host smart-974f1976-5592-470c-ad5b-e54446422855
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930210060 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1930210060
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2745081682
Short name T1093
Test name
Test status
Simulation time 30895680 ps
CPU time 1.46 seconds
Started Jul 15 07:11:48 PM PDT 24
Finished Jul 15 07:11:56 PM PDT 24
Peak memory 215324 kb
Host smart-e7f45258-bfd8-4c74-aecc-423b81728ae3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745081682 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2745081682
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.2133241487
Short name T1036
Test name
Test status
Simulation time 14084056 ps
CPU time 0.91 seconds
Started Jul 15 07:11:51 PM PDT 24
Finished Jul 15 07:12:00 PM PDT 24
Peak memory 206772 kb
Host smart-f773d4aa-e97b-4d36-bc03-695a5de17e4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133241487 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.2133241487
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.1804151409
Short name T1061
Test name
Test status
Simulation time 16686134 ps
CPU time 0.93 seconds
Started Jul 15 07:11:49 PM PDT 24
Finished Jul 15 07:11:57 PM PDT 24
Peak memory 206888 kb
Host smart-4ab28ef8-b951-4d6d-9ae3-3ebab7d3d478
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804151409 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.1804151409
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2882406810
Short name T1040
Test name
Test status
Simulation time 104541213 ps
CPU time 1.27 seconds
Started Jul 15 07:11:49 PM PDT 24
Finished Jul 15 07:11:56 PM PDT 24
Peak memory 206928 kb
Host smart-561b96b1-d1b6-44bf-986f-6a6db7d56883
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882406810 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2882406810
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.2537336487
Short name T1062
Test name
Test status
Simulation time 119871082 ps
CPU time 1.8 seconds
Started Jul 15 07:11:47 PM PDT 24
Finished Jul 15 07:11:54 PM PDT 24
Peak memory 215204 kb
Host smart-e48f8519-2f0b-4c8b-bbb9-dba07acfab64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537336487 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2537336487
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1879609027
Short name T1112
Test name
Test status
Simulation time 58726924 ps
CPU time 1.83 seconds
Started Jul 15 07:11:47 PM PDT 24
Finished Jul 15 07:11:55 PM PDT 24
Peak memory 206904 kb
Host smart-58d211fb-1ce4-40a1-b06a-0578aa5be509
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879609027 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1879609027
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3344939008
Short name T1000
Test name
Test status
Simulation time 60997867 ps
CPU time 1.15 seconds
Started Jul 15 07:11:54 PM PDT 24
Finished Jul 15 07:12:03 PM PDT 24
Peak memory 215180 kb
Host smart-06b6532f-4759-4873-b27e-be8b3b103db1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344939008 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.3344939008
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.3294331395
Short name T1077
Test name
Test status
Simulation time 18820429 ps
CPU time 0.86 seconds
Started Jul 15 07:11:54 PM PDT 24
Finished Jul 15 07:12:04 PM PDT 24
Peak memory 206920 kb
Host smart-380ae7f7-c108-4684-a9fa-2515fcf6a66d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294331395 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.3294331395
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.727411044
Short name T1050
Test name
Test status
Simulation time 47164073 ps
CPU time 0.86 seconds
Started Jul 15 07:11:54 PM PDT 24
Finished Jul 15 07:12:03 PM PDT 24
Peak memory 206856 kb
Host smart-2f4d7d5f-7735-4580-8df0-5cb022f6e181
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727411044 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.727411044
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.4152363829
Short name T256
Test name
Test status
Simulation time 39811003 ps
CPU time 1.47 seconds
Started Jul 15 07:11:50 PM PDT 24
Finished Jul 15 07:11:58 PM PDT 24
Peak memory 206904 kb
Host smart-8806aad2-31cf-4616-a1bb-81415e32354c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152363829 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.4152363829
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.3917665906
Short name T1089
Test name
Test status
Simulation time 107543582 ps
CPU time 2.08 seconds
Started Jul 15 07:11:51 PM PDT 24
Finished Jul 15 07:12:00 PM PDT 24
Peak memory 215172 kb
Host smart-8db5b209-415a-4f57-bd76-130868a97f17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917665906 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3917665906
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1624196324
Short name T289
Test name
Test status
Simulation time 193488446 ps
CPU time 1.6 seconds
Started Jul 15 07:11:46 PM PDT 24
Finished Jul 15 07:11:54 PM PDT 24
Peak memory 215244 kb
Host smart-67098780-ef4d-4ade-96bd-120b645d432f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624196324 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1624196324
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.761754786
Short name T1029
Test name
Test status
Simulation time 37302593 ps
CPU time 1.67 seconds
Started Jul 15 07:11:49 PM PDT 24
Finished Jul 15 07:11:57 PM PDT 24
Peak memory 218836 kb
Host smart-4f3dea96-ca4a-4e69-8439-d4c0e675b2bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761754786 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.761754786
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.1520139667
Short name T272
Test name
Test status
Simulation time 13759570 ps
CPU time 0.9 seconds
Started Jul 15 07:11:51 PM PDT 24
Finished Jul 15 07:11:58 PM PDT 24
Peak memory 206936 kb
Host smart-147c8728-c0bc-4a6c-bc65-e5f5e144f245
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520139667 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1520139667
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.2810292680
Short name T1059
Test name
Test status
Simulation time 47031637 ps
CPU time 0.9 seconds
Started Jul 15 07:11:49 PM PDT 24
Finished Jul 15 07:11:56 PM PDT 24
Peak memory 206876 kb
Host smart-10c39815-400c-4d27-a88d-50cb63980616
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810292680 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.2810292680
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1039523997
Short name T1097
Test name
Test status
Simulation time 188833056 ps
CPU time 1.26 seconds
Started Jul 15 07:11:49 PM PDT 24
Finished Jul 15 07:11:56 PM PDT 24
Peak memory 206928 kb
Host smart-54cec72f-e1b1-4b13-9a26-70c48238ef58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039523997 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.1039523997
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.2433430468
Short name T1027
Test name
Test status
Simulation time 39608506 ps
CPU time 2.82 seconds
Started Jul 15 07:11:50 PM PDT 24
Finished Jul 15 07:12:00 PM PDT 24
Peak memory 215216 kb
Host smart-7889e0c6-f22a-479e-ba61-8b1a1441dd94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433430468 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2433430468
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2034414930
Short name T1098
Test name
Test status
Simulation time 1150632034 ps
CPU time 2.64 seconds
Started Jul 15 07:11:46 PM PDT 24
Finished Jul 15 07:11:55 PM PDT 24
Peak memory 207040 kb
Host smart-5cd3a896-7844-494d-a9c5-81a7a668cf88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034414930 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2034414930
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.804699474
Short name T1004
Test name
Test status
Simulation time 26279594 ps
CPU time 1.32 seconds
Started Jul 15 07:11:51 PM PDT 24
Finished Jul 15 07:11:59 PM PDT 24
Peak memory 215272 kb
Host smart-156eba4e-533d-4a0d-9588-4498751820ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804699474 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.804699474
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.2732044869
Short name T270
Test name
Test status
Simulation time 50940888 ps
CPU time 0.93 seconds
Started Jul 15 07:11:54 PM PDT 24
Finished Jul 15 07:12:03 PM PDT 24
Peak memory 206920 kb
Host smart-f5e1bbb9-9abb-441f-bc2c-30c572cad3f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732044869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.2732044869
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.4233279043
Short name T1076
Test name
Test status
Simulation time 41145017 ps
CPU time 0.86 seconds
Started Jul 15 07:11:50 PM PDT 24
Finished Jul 15 07:11:58 PM PDT 24
Peak memory 206832 kb
Host smart-161ada2b-104b-42de-8b08-e4d6a61643c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233279043 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.4233279043
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3437063155
Short name T1078
Test name
Test status
Simulation time 60420928 ps
CPU time 1.35 seconds
Started Jul 15 07:11:47 PM PDT 24
Finished Jul 15 07:11:55 PM PDT 24
Peak memory 206888 kb
Host smart-3b38b181-a2aa-40ab-bd6b-973555ce2e67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437063155 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3437063155
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.2024707148
Short name T1065
Test name
Test status
Simulation time 82033124 ps
CPU time 2.47 seconds
Started Jul 15 07:11:50 PM PDT 24
Finished Jul 15 07:11:58 PM PDT 24
Peak memory 215148 kb
Host smart-6b4e12e6-0756-4a2e-bbe3-f32fb01d8f91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024707148 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.2024707148
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3226357433
Short name T1030
Test name
Test status
Simulation time 456554284 ps
CPU time 4.3 seconds
Started Jul 15 07:11:51 PM PDT 24
Finished Jul 15 07:12:02 PM PDT 24
Peak memory 215164 kb
Host smart-422ddc33-10bc-40dc-bcc4-926b946dc659
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226357433 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.3226357433
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2769979718
Short name T1103
Test name
Test status
Simulation time 16712128 ps
CPU time 1.11 seconds
Started Jul 15 07:11:50 PM PDT 24
Finished Jul 15 07:11:58 PM PDT 24
Peak memory 215256 kb
Host smart-f4977e07-e822-4775-a535-2f195d5f4c97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769979718 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2769979718
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.3022746174
Short name T268
Test name
Test status
Simulation time 13307463 ps
CPU time 0.93 seconds
Started Jul 15 07:11:51 PM PDT 24
Finished Jul 15 07:11:58 PM PDT 24
Peak memory 206876 kb
Host smart-0f3243ed-2a46-463b-a5ab-68cdbe3b7518
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022746174 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.3022746174
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.1833957251
Short name T1094
Test name
Test status
Simulation time 23738347 ps
CPU time 0.95 seconds
Started Jul 15 07:11:49 PM PDT 24
Finished Jul 15 07:11:56 PM PDT 24
Peak memory 206880 kb
Host smart-55f7ada3-4ad3-47e1-96ea-c0086614f311
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833957251 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1833957251
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3363615249
Short name T1070
Test name
Test status
Simulation time 20822099 ps
CPU time 1.26 seconds
Started Jul 15 07:11:52 PM PDT 24
Finished Jul 15 07:12:01 PM PDT 24
Peak memory 206976 kb
Host smart-a9f23fab-4102-4b9a-9b11-5fb9556ac223
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363615249 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.3363615249
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.562678555
Short name T999
Test name
Test status
Simulation time 136875861 ps
CPU time 2.53 seconds
Started Jul 15 07:11:53 PM PDT 24
Finished Jul 15 07:12:03 PM PDT 24
Peak memory 215120 kb
Host smart-281d0440-caee-4d3d-88fc-410f319edbf5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562678555 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.562678555
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3252119255
Short name T287
Test name
Test status
Simulation time 88393933 ps
CPU time 2.56 seconds
Started Jul 15 07:11:49 PM PDT 24
Finished Jul 15 07:11:58 PM PDT 24
Peak memory 206928 kb
Host smart-8f5cbb99-e6a9-4859-b16d-81a7d9d1ce9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252119255 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3252119255
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2466057427
Short name T1101
Test name
Test status
Simulation time 36133807 ps
CPU time 1.59 seconds
Started Jul 15 07:11:54 PM PDT 24
Finished Jul 15 07:12:04 PM PDT 24
Peak memory 215164 kb
Host smart-18b6dc54-1837-479a-9474-923ddf829036
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466057427 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.2466057427
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.761130796
Short name T1088
Test name
Test status
Simulation time 12274280 ps
CPU time 0.91 seconds
Started Jul 15 07:11:49 PM PDT 24
Finished Jul 15 07:11:57 PM PDT 24
Peak memory 206916 kb
Host smart-b9e6beb2-0abb-4f75-b069-ea335fb0f55e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761130796 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.761130796
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.3939805661
Short name T995
Test name
Test status
Simulation time 20235277 ps
CPU time 0.82 seconds
Started Jul 15 07:11:53 PM PDT 24
Finished Jul 15 07:12:02 PM PDT 24
Peak memory 206636 kb
Host smart-5b195b29-3f43-47f2-a878-64b282bf634f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939805661 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.3939805661
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3180678002
Short name T1086
Test name
Test status
Simulation time 32587166 ps
CPU time 1.02 seconds
Started Jul 15 07:11:54 PM PDT 24
Finished Jul 15 07:12:03 PM PDT 24
Peak memory 206916 kb
Host smart-b6fe69ec-c092-4a54-8521-2aa10e4d7811
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180678002 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.3180678002
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.2153933779
Short name T1125
Test name
Test status
Simulation time 20427969 ps
CPU time 1.52 seconds
Started Jul 15 07:11:54 PM PDT 24
Finished Jul 15 07:12:03 PM PDT 24
Peak memory 215256 kb
Host smart-60d18391-5ca2-4d07-ada5-b7c643ba2592
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153933779 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.2153933779
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.4040263029
Short name T1122
Test name
Test status
Simulation time 302739927 ps
CPU time 2.47 seconds
Started Jul 15 07:11:51 PM PDT 24
Finished Jul 15 07:12:01 PM PDT 24
Peak memory 206912 kb
Host smart-de646efa-7a5a-48ad-87ba-fb1368fc390b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040263029 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.4040263029
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1326033463
Short name T1026
Test name
Test status
Simulation time 109425248 ps
CPU time 1.98 seconds
Started Jul 15 07:11:51 PM PDT 24
Finished Jul 15 07:12:01 PM PDT 24
Peak memory 215212 kb
Host smart-137c1fab-ddcb-4cb8-b4d8-385da96d79c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326033463 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.1326033463
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2474882051
Short name T1124
Test name
Test status
Simulation time 49038981 ps
CPU time 0.92 seconds
Started Jul 15 07:11:51 PM PDT 24
Finished Jul 15 07:12:00 PM PDT 24
Peak memory 206836 kb
Host smart-3b89bb4d-7969-4fc2-b607-3dba1fd616f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474882051 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2474882051
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.3987885024
Short name T1129
Test name
Test status
Simulation time 36245041 ps
CPU time 0.86 seconds
Started Jul 15 07:11:53 PM PDT 24
Finished Jul 15 07:12:01 PM PDT 24
Peak memory 206580 kb
Host smart-45a2f970-9c0e-4248-8997-7fd3c011614d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987885024 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.3987885024
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.864184361
Short name T274
Test name
Test status
Simulation time 79707637 ps
CPU time 1.06 seconds
Started Jul 15 07:11:57 PM PDT 24
Finished Jul 15 07:12:06 PM PDT 24
Peak memory 206896 kb
Host smart-4de82f6c-0f22-4ade-95c2-e888a1ffe204
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864184361 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_ou
tstanding.864184361
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.4190191105
Short name T1023
Test name
Test status
Simulation time 51263840 ps
CPU time 1.85 seconds
Started Jul 15 07:11:53 PM PDT 24
Finished Jul 15 07:12:02 PM PDT 24
Peak memory 223328 kb
Host smart-326cc998-7060-496c-a3b5-c608ff8bf72e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190191105 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.4190191105
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.4160130648
Short name T1024
Test name
Test status
Simulation time 132616414 ps
CPU time 2.92 seconds
Started Jul 15 07:11:54 PM PDT 24
Finished Jul 15 07:12:05 PM PDT 24
Peak memory 206956 kb
Host smart-bce70661-4225-4c5d-9063-3751b96498d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160130648 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.4160130648
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3131004194
Short name T1006
Test name
Test status
Simulation time 1710462377 ps
CPU time 3.3 seconds
Started Jul 15 07:11:42 PM PDT 24
Finished Jul 15 07:11:48 PM PDT 24
Peak memory 206960 kb
Host smart-d56d85f1-5dbc-4f09-829c-282fb3b6ebcf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131004194 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.3131004194
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3888277926
Short name T1066
Test name
Test status
Simulation time 133709085 ps
CPU time 0.8 seconds
Started Jul 15 07:11:41 PM PDT 24
Finished Jul 15 07:11:44 PM PDT 24
Peak memory 206684 kb
Host smart-ae65bfff-bea5-4535-93fc-de4804788948
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888277926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3888277926
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3195909755
Short name T1079
Test name
Test status
Simulation time 38958137 ps
CPU time 1.11 seconds
Started Jul 15 07:11:48 PM PDT 24
Finished Jul 15 07:11:55 PM PDT 24
Peak memory 215168 kb
Host smart-ab1356dd-3c50-477c-9d94-f12063fc8d42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195909755 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3195909755
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.1455397621
Short name T1073
Test name
Test status
Simulation time 46487819 ps
CPU time 0.87 seconds
Started Jul 15 07:11:44 PM PDT 24
Finished Jul 15 07:11:49 PM PDT 24
Peak memory 206868 kb
Host smart-1255ac31-e07e-49a5-8243-8f8ef30aae14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455397621 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.1455397621
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.2847420649
Short name T1047
Test name
Test status
Simulation time 15505736 ps
CPU time 0.87 seconds
Started Jul 15 07:11:42 PM PDT 24
Finished Jul 15 07:11:47 PM PDT 24
Peak memory 206800 kb
Host smart-09dde6b8-2525-4f9f-a54d-46c8f7924c7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847420649 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.2847420649
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.427770141
Short name T1020
Test name
Test status
Simulation time 54224882 ps
CPU time 1.04 seconds
Started Jul 15 07:11:44 PM PDT 24
Finished Jul 15 07:11:49 PM PDT 24
Peak memory 206968 kb
Host smart-1bcbea0f-69b0-4ad2-9422-be5eab69c24a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427770141 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_out
standing.427770141
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.497986979
Short name T1039
Test name
Test status
Simulation time 156031744 ps
CPU time 2.64 seconds
Started Jul 15 07:11:44 PM PDT 24
Finished Jul 15 07:11:51 PM PDT 24
Peak memory 215152 kb
Host smart-f071e9fe-b505-490e-9847-ad8abb6d913e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497986979 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.497986979
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2213568369
Short name T1075
Test name
Test status
Simulation time 53306274 ps
CPU time 1.73 seconds
Started Jul 15 07:11:43 PM PDT 24
Finished Jul 15 07:11:47 PM PDT 24
Peak memory 207152 kb
Host smart-f4b53625-e132-48f2-b5ca-6385d4debb3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213568369 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.2213568369
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.1785641661
Short name T1128
Test name
Test status
Simulation time 43147171 ps
CPU time 0.83 seconds
Started Jul 15 07:11:48 PM PDT 24
Finished Jul 15 07:11:55 PM PDT 24
Peak memory 206860 kb
Host smart-2981db03-76db-4496-b2b2-fa57b90d95a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785641661 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.1785641661
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.3194079038
Short name T1014
Test name
Test status
Simulation time 21005106 ps
CPU time 0.82 seconds
Started Jul 15 07:11:50 PM PDT 24
Finished Jul 15 07:11:58 PM PDT 24
Peak memory 206864 kb
Host smart-97c97ebc-7439-42cd-a777-d2b87dff70f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194079038 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.3194079038
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.2868380214
Short name T1010
Test name
Test status
Simulation time 13132905 ps
CPU time 0.86 seconds
Started Jul 15 07:11:54 PM PDT 24
Finished Jul 15 07:12:03 PM PDT 24
Peak memory 206828 kb
Host smart-d9211dda-8e63-4fe3-9126-12010f01bb13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868380214 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2868380214
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.2978831710
Short name T1114
Test name
Test status
Simulation time 25279526 ps
CPU time 0.86 seconds
Started Jul 15 07:11:55 PM PDT 24
Finished Jul 15 07:12:04 PM PDT 24
Peak memory 206908 kb
Host smart-0d130c2e-8238-4719-876c-a81686a5f698
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978831710 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2978831710
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.212081095
Short name T1034
Test name
Test status
Simulation time 25445958 ps
CPU time 0.89 seconds
Started Jul 15 07:11:51 PM PDT 24
Finished Jul 15 07:12:00 PM PDT 24
Peak memory 206788 kb
Host smart-59680046-0852-438d-8ce3-48386c41f1ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212081095 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.212081095
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.2966094463
Short name T1055
Test name
Test status
Simulation time 14562441 ps
CPU time 0.89 seconds
Started Jul 15 07:11:52 PM PDT 24
Finished Jul 15 07:12:01 PM PDT 24
Peak memory 206996 kb
Host smart-b567db60-1ec3-4a07-8a73-53cfc55c2ff8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966094463 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.2966094463
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.2609551495
Short name T1003
Test name
Test status
Simulation time 52929938 ps
CPU time 0.92 seconds
Started Jul 15 07:11:53 PM PDT 24
Finished Jul 15 07:12:02 PM PDT 24
Peak memory 206828 kb
Host smart-86103c2a-47cc-4e3e-833c-e22227406b86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609551495 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2609551495
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.1596038217
Short name T1054
Test name
Test status
Simulation time 28794255 ps
CPU time 0.9 seconds
Started Jul 15 07:11:54 PM PDT 24
Finished Jul 15 07:12:04 PM PDT 24
Peak memory 206852 kb
Host smart-5b43d5b1-fc41-4d89-a720-d3800a3dcece
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596038217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1596038217
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.1664783202
Short name T1022
Test name
Test status
Simulation time 13680134 ps
CPU time 0.9 seconds
Started Jul 15 07:11:56 PM PDT 24
Finished Jul 15 07:12:06 PM PDT 24
Peak memory 206776 kb
Host smart-3a0e688a-9ffd-466a-9798-ef965f132c7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664783202 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.1664783202
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.3296226018
Short name T1011
Test name
Test status
Simulation time 72401174 ps
CPU time 0.9 seconds
Started Jul 15 07:11:53 PM PDT 24
Finished Jul 15 07:12:01 PM PDT 24
Peak memory 206752 kb
Host smart-78f8f852-402f-49cb-bfc8-d4ee672263de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296226018 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.3296226018
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.974406691
Short name T260
Test name
Test status
Simulation time 151604472 ps
CPU time 1.61 seconds
Started Jul 15 07:11:42 PM PDT 24
Finished Jul 15 07:11:46 PM PDT 24
Peak memory 206876 kb
Host smart-7c872b7b-7285-44e4-b65b-937d6b40841d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974406691 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.974406691
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2414982896
Short name T1044
Test name
Test status
Simulation time 101860511 ps
CPU time 1.98 seconds
Started Jul 15 07:11:42 PM PDT 24
Finished Jul 15 07:11:46 PM PDT 24
Peak memory 206996 kb
Host smart-24a623ba-2532-4d6b-9c94-59c22e65015e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414982896 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.2414982896
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3514576425
Short name T1052
Test name
Test status
Simulation time 12203445 ps
CPU time 0.92 seconds
Started Jul 15 07:11:44 PM PDT 24
Finished Jul 15 07:11:50 PM PDT 24
Peak memory 206876 kb
Host smart-5968e00e-1e7d-4721-b7b5-562b40dc0579
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514576425 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.3514576425
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2983736885
Short name T1071
Test name
Test status
Simulation time 49559855 ps
CPU time 1.8 seconds
Started Jul 15 07:11:47 PM PDT 24
Finished Jul 15 07:11:54 PM PDT 24
Peak memory 215196 kb
Host smart-22a0f7e8-93db-4791-afd9-9c26df1925c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983736885 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2983736885
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.3437734814
Short name T259
Test name
Test status
Simulation time 11805710 ps
CPU time 0.88 seconds
Started Jul 15 07:11:42 PM PDT 24
Finished Jul 15 07:11:45 PM PDT 24
Peak memory 206864 kb
Host smart-da2d0bbf-1d60-4f39-a013-869e2b5368fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437734814 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.3437734814
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.2791847940
Short name T1127
Test name
Test status
Simulation time 88527183 ps
CPU time 0.79 seconds
Started Jul 15 07:11:42 PM PDT 24
Finished Jul 15 07:11:46 PM PDT 24
Peak memory 206628 kb
Host smart-3f6f25c4-2c00-4db0-ba4e-27e5c5610c66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791847940 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.2791847940
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.130529254
Short name T258
Test name
Test status
Simulation time 16293588 ps
CPU time 1.01 seconds
Started Jul 15 07:11:43 PM PDT 24
Finished Jul 15 07:11:48 PM PDT 24
Peak memory 206908 kb
Host smart-652583b8-4db1-44a3-8721-568074cf895f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130529254 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_out
standing.130529254
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.432132798
Short name T1069
Test name
Test status
Simulation time 201531945 ps
CPU time 3.91 seconds
Started Jul 15 07:11:39 PM PDT 24
Finished Jul 15 07:11:44 PM PDT 24
Peak memory 215148 kb
Host smart-d0fa4820-fac9-4982-81a0-46bd2287293d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432132798 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.432132798
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2647728838
Short name T1051
Test name
Test status
Simulation time 88307848 ps
CPU time 1.78 seconds
Started Jul 15 07:11:42 PM PDT 24
Finished Jul 15 07:11:47 PM PDT 24
Peak memory 207060 kb
Host smart-2194ce12-f2af-4553-849b-e0a71bc5f23c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647728838 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.2647728838
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2153353218
Short name T1009
Test name
Test status
Simulation time 19264494 ps
CPU time 0.98 seconds
Started Jul 15 07:11:54 PM PDT 24
Finished Jul 15 07:12:04 PM PDT 24
Peak memory 206912 kb
Host smart-a65c8bc0-95c0-4d55-8e3c-55dab7c4c87d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153353218 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2153353218
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.3976633435
Short name T1119
Test name
Test status
Simulation time 90139719 ps
CPU time 0.86 seconds
Started Jul 15 07:11:49 PM PDT 24
Finished Jul 15 07:11:57 PM PDT 24
Peak memory 206692 kb
Host smart-ab95ed4f-0f5f-461f-96f7-1a50d34e0ba2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976633435 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.3976633435
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.501342164
Short name T1012
Test name
Test status
Simulation time 33762618 ps
CPU time 0.8 seconds
Started Jul 15 07:11:50 PM PDT 24
Finished Jul 15 07:11:57 PM PDT 24
Peak memory 206644 kb
Host smart-b66383c2-9f23-4672-aa62-0892171143a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501342164 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.501342164
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.3742679304
Short name T1118
Test name
Test status
Simulation time 18160764 ps
CPU time 0.97 seconds
Started Jul 15 07:11:54 PM PDT 24
Finished Jul 15 07:12:03 PM PDT 24
Peak memory 206824 kb
Host smart-5309517b-4d3a-4e40-82df-1c74fbb7f34e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742679304 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3742679304
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.1106879700
Short name T1109
Test name
Test status
Simulation time 13636314 ps
CPU time 0.88 seconds
Started Jul 15 07:11:52 PM PDT 24
Finished Jul 15 07:12:01 PM PDT 24
Peak memory 206844 kb
Host smart-d3c6ea74-9314-4b0c-ae9b-c1527fa76ff9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106879700 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1106879700
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.2297987798
Short name T1083
Test name
Test status
Simulation time 76411167 ps
CPU time 0.85 seconds
Started Jul 15 07:11:50 PM PDT 24
Finished Jul 15 07:11:58 PM PDT 24
Peak memory 206676 kb
Host smart-08c44b78-2ca2-4e05-a82e-546d0d8a226a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297987798 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.2297987798
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.999740816
Short name T1063
Test name
Test status
Simulation time 30904901 ps
CPU time 0.78 seconds
Started Jul 15 07:11:55 PM PDT 24
Finished Jul 15 07:12:04 PM PDT 24
Peak memory 206672 kb
Host smart-3382cac0-5555-4c04-bb3d-912af83393bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999740816 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.999740816
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.1149402929
Short name T1085
Test name
Test status
Simulation time 20724448 ps
CPU time 0.81 seconds
Started Jul 15 07:11:55 PM PDT 24
Finished Jul 15 07:12:05 PM PDT 24
Peak memory 206864 kb
Host smart-30fc7746-7534-48ba-9706-e4276f81f526
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149402929 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1149402929
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.3607985853
Short name T1106
Test name
Test status
Simulation time 85267873 ps
CPU time 0.84 seconds
Started Jul 15 07:11:52 PM PDT 24
Finished Jul 15 07:12:00 PM PDT 24
Peak memory 206892 kb
Host smart-7202dd8b-79dd-4c70-9881-2fbcfdaeb2c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607985853 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3607985853
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.1926609662
Short name T996
Test name
Test status
Simulation time 41321521 ps
CPU time 0.86 seconds
Started Jul 15 07:11:53 PM PDT 24
Finished Jul 15 07:12:02 PM PDT 24
Peak memory 206816 kb
Host smart-fc4ef29b-dd32-49bf-a1f0-738dff6a421c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926609662 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.1926609662
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.459677044
Short name T264
Test name
Test status
Simulation time 70149394 ps
CPU time 1.45 seconds
Started Jul 15 07:11:45 PM PDT 24
Finished Jul 15 07:11:52 PM PDT 24
Peak memory 206928 kb
Host smart-da3876f6-d25b-4acb-9649-ef331b169609
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459677044 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.459677044
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3801182102
Short name T267
Test name
Test status
Simulation time 182415971 ps
CPU time 5.22 seconds
Started Jul 15 07:11:44 PM PDT 24
Finished Jul 15 07:11:54 PM PDT 24
Peak memory 206920 kb
Host smart-64207292-b874-4bc9-bb0f-685dc4c3591e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801182102 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.3801182102
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3391326659
Short name T1038
Test name
Test status
Simulation time 16643358 ps
CPU time 0.88 seconds
Started Jul 15 07:11:42 PM PDT 24
Finished Jul 15 07:11:46 PM PDT 24
Peak memory 206912 kb
Host smart-f34e0223-8396-444e-ab60-4470b088b70e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391326659 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3391326659
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.707388973
Short name T1005
Test name
Test status
Simulation time 231063538 ps
CPU time 1.25 seconds
Started Jul 15 07:11:48 PM PDT 24
Finished Jul 15 07:11:55 PM PDT 24
Peak memory 215260 kb
Host smart-0b84f5f7-ff70-4065-a0e9-6feec9c78ed3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707388973 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.707388973
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.3474203034
Short name T998
Test name
Test status
Simulation time 67370598 ps
CPU time 0.84 seconds
Started Jul 15 07:11:45 PM PDT 24
Finished Jul 15 07:11:50 PM PDT 24
Peak memory 206984 kb
Host smart-5769c71e-51c8-4065-9ce6-f7cf0bb17075
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474203034 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.3474203034
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.4221592212
Short name T1130
Test name
Test status
Simulation time 23627142 ps
CPU time 0.86 seconds
Started Jul 15 07:11:43 PM PDT 24
Finished Jul 15 07:11:48 PM PDT 24
Peak memory 206996 kb
Host smart-31fb2ae6-a602-4fd5-8569-55f716af7325
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221592212 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.4221592212
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2730760071
Short name T1087
Test name
Test status
Simulation time 19108250 ps
CPU time 1.04 seconds
Started Jul 15 07:11:46 PM PDT 24
Finished Jul 15 07:11:52 PM PDT 24
Peak memory 206992 kb
Host smart-fc4a6fb1-6283-4523-a69c-e45fbd056984
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730760071 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.2730760071
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.2935804523
Short name T1043
Test name
Test status
Simulation time 55614839 ps
CPU time 2.27 seconds
Started Jul 15 07:11:44 PM PDT 24
Finished Jul 15 07:11:51 PM PDT 24
Peak memory 215252 kb
Host smart-8df18568-91ac-4541-bb9c-4cbaa3c1e0a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935804523 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2935804523
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3955013531
Short name T285
Test name
Test status
Simulation time 79551690 ps
CPU time 1.51 seconds
Started Jul 15 07:11:45 PM PDT 24
Finished Jul 15 07:11:51 PM PDT 24
Peak memory 206964 kb
Host smart-7900bed1-cc99-4919-9884-53a51d81523b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955013531 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.3955013531
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.719696842
Short name T1117
Test name
Test status
Simulation time 13149765 ps
CPU time 0.9 seconds
Started Jul 15 07:11:56 PM PDT 24
Finished Jul 15 07:12:06 PM PDT 24
Peak memory 206832 kb
Host smart-b66350b7-080d-4884-9e5d-e4e99a9f92d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719696842 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.719696842
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.3809180771
Short name T1084
Test name
Test status
Simulation time 13632758 ps
CPU time 0.95 seconds
Started Jul 15 07:11:54 PM PDT 24
Finished Jul 15 07:12:03 PM PDT 24
Peak memory 206872 kb
Host smart-3864c25e-cd8f-4bc9-83f7-3c6a15aa49a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809180771 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.3809180771
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.3241741982
Short name T1121
Test name
Test status
Simulation time 20918287 ps
CPU time 0.85 seconds
Started Jul 15 07:11:51 PM PDT 24
Finished Jul 15 07:12:00 PM PDT 24
Peak memory 206800 kb
Host smart-e855df51-fa34-46e4-8133-c3c1deb535be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241741982 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3241741982
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.3472139600
Short name T1018
Test name
Test status
Simulation time 21522933 ps
CPU time 0.85 seconds
Started Jul 15 07:11:53 PM PDT 24
Finished Jul 15 07:12:02 PM PDT 24
Peak memory 206812 kb
Host smart-5d11b901-280d-49e1-a7df-5cd969e92ed9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472139600 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.3472139600
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.1563900791
Short name T1016
Test name
Test status
Simulation time 15982399 ps
CPU time 0.94 seconds
Started Jul 15 07:11:52 PM PDT 24
Finished Jul 15 07:12:01 PM PDT 24
Peak memory 206996 kb
Host smart-218002d1-65e7-423e-bfcc-849cc81544e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563900791 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.1563900791
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.1803444311
Short name T1105
Test name
Test status
Simulation time 38815814 ps
CPU time 0.92 seconds
Started Jul 15 07:11:52 PM PDT 24
Finished Jul 15 07:12:00 PM PDT 24
Peak memory 206668 kb
Host smart-ffa27e99-9fac-47b5-a263-9edfdc31d193
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803444311 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1803444311
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1456121014
Short name T1013
Test name
Test status
Simulation time 27397165 ps
CPU time 0.86 seconds
Started Jul 15 07:11:51 PM PDT 24
Finished Jul 15 07:12:00 PM PDT 24
Peak memory 206760 kb
Host smart-e970fcdf-273c-4f56-92f7-2fc41c919b3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456121014 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1456121014
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.1193422050
Short name T1081
Test name
Test status
Simulation time 12741903 ps
CPU time 0.87 seconds
Started Jul 15 07:11:57 PM PDT 24
Finished Jul 15 07:12:06 PM PDT 24
Peak memory 206856 kb
Host smart-8abe17d9-9f0d-4a44-b97d-12066882f683
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193422050 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.1193422050
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.1835029197
Short name T1064
Test name
Test status
Simulation time 19354530 ps
CPU time 0.88 seconds
Started Jul 15 07:11:51 PM PDT 24
Finished Jul 15 07:12:00 PM PDT 24
Peak memory 206752 kb
Host smart-340c98b7-6325-4624-8037-8f68f5e160d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835029197 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.1835029197
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.1104824222
Short name T1025
Test name
Test status
Simulation time 99800980 ps
CPU time 0.88 seconds
Started Jul 15 07:11:51 PM PDT 24
Finished Jul 15 07:12:00 PM PDT 24
Peak memory 206672 kb
Host smart-84fbc75f-6446-41cb-917d-2c173973b624
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104824222 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.1104824222
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.235212057
Short name T994
Test name
Test status
Simulation time 88738921 ps
CPU time 1.55 seconds
Started Jul 15 07:11:44 PM PDT 24
Finished Jul 15 07:11:49 PM PDT 24
Peak memory 215116 kb
Host smart-248c2a4d-7026-4e77-8d21-7c670b656cae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235212057 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.235212057
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.1888113737
Short name T265
Test name
Test status
Simulation time 15167241 ps
CPU time 0.86 seconds
Started Jul 15 07:11:47 PM PDT 24
Finished Jul 15 07:11:53 PM PDT 24
Peak memory 206912 kb
Host smart-6483cd13-02e6-4cbc-a5c2-617f401a28ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888113737 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.1888113737
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.3446606525
Short name T1104
Test name
Test status
Simulation time 14955814 ps
CPU time 0.9 seconds
Started Jul 15 07:11:43 PM PDT 24
Finished Jul 15 07:11:48 PM PDT 24
Peak memory 206872 kb
Host smart-31b3a622-5f9f-40e6-995b-371be6f0b4ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446606525 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.3446606525
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2273009981
Short name T1068
Test name
Test status
Simulation time 22052730 ps
CPU time 1.09 seconds
Started Jul 15 07:11:46 PM PDT 24
Finished Jul 15 07:11:52 PM PDT 24
Peak memory 206912 kb
Host smart-478cc75e-82c9-4738-9f48-adea1b9c6f39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273009981 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.2273009981
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.1102678498
Short name T1021
Test name
Test status
Simulation time 699468724 ps
CPU time 2.97 seconds
Started Jul 15 07:11:47 PM PDT 24
Finished Jul 15 07:11:56 PM PDT 24
Peak memory 215188 kb
Host smart-fc766d93-a105-48e9-a264-429bb13c0e08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102678498 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.1102678498
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1006594254
Short name T1090
Test name
Test status
Simulation time 215047413 ps
CPU time 2.07 seconds
Started Jul 15 07:11:48 PM PDT 24
Finished Jul 15 07:11:56 PM PDT 24
Peak memory 207084 kb
Host smart-02397cce-fcd0-46ff-9f30-7754ffdb1cdd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006594254 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1006594254
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.373927390
Short name T1072
Test name
Test status
Simulation time 77303518 ps
CPU time 1.35 seconds
Started Jul 15 07:11:45 PM PDT 24
Finished Jul 15 07:11:52 PM PDT 24
Peak memory 223396 kb
Host smart-cd0287b3-61da-41e6-9631-c41bec113237
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373927390 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.373927390
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.2695677212
Short name T1111
Test name
Test status
Simulation time 16608533 ps
CPU time 0.95 seconds
Started Jul 15 07:11:45 PM PDT 24
Finished Jul 15 07:11:51 PM PDT 24
Peak memory 206984 kb
Host smart-2ad898de-7fd5-4227-94b5-238c9ee1a56d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695677212 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.2695677212
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.4210584904
Short name T1100
Test name
Test status
Simulation time 45636450 ps
CPU time 0.83 seconds
Started Jul 15 07:11:43 PM PDT 24
Finished Jul 15 07:11:48 PM PDT 24
Peak memory 206872 kb
Host smart-b1347e68-b3da-436d-a606-0e0f89fda604
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210584904 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.4210584904
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1306900899
Short name T1058
Test name
Test status
Simulation time 25265278 ps
CPU time 0.98 seconds
Started Jul 15 07:11:44 PM PDT 24
Finished Jul 15 07:11:49 PM PDT 24
Peak memory 206912 kb
Host smart-be5e374e-c1a0-44a3-bfc7-2ce3da598360
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306900899 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.1306900899
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.2607477802
Short name T1091
Test name
Test status
Simulation time 81805072 ps
CPU time 2.82 seconds
Started Jul 15 07:11:49 PM PDT 24
Finished Jul 15 07:11:58 PM PDT 24
Peak memory 215308 kb
Host smart-4f23bf13-f8d0-405d-97d4-36f1a8832caf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607477802 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2607477802
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1513661550
Short name T1080
Test name
Test status
Simulation time 107208232 ps
CPU time 2.75 seconds
Started Jul 15 07:11:43 PM PDT 24
Finished Jul 15 07:11:50 PM PDT 24
Peak memory 215120 kb
Host smart-3fd4415d-1db1-4c88-8a16-612566440139
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513661550 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.1513661550
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1297630889
Short name T1123
Test name
Test status
Simulation time 49252009 ps
CPU time 1.3 seconds
Started Jul 15 07:11:47 PM PDT 24
Finished Jul 15 07:11:54 PM PDT 24
Peak memory 218096 kb
Host smart-ce77c8e3-40ab-4fa3-87e2-e8f6c506ecc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297630889 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1297630889
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1840429035
Short name T1032
Test name
Test status
Simulation time 19459901 ps
CPU time 0.79 seconds
Started Jul 15 07:11:47 PM PDT 24
Finished Jul 15 07:11:54 PM PDT 24
Peak memory 206740 kb
Host smart-71632cb8-7809-4583-b80c-cf673a1999d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840429035 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1840429035
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.4203191827
Short name T1046
Test name
Test status
Simulation time 65138049 ps
CPU time 0.78 seconds
Started Jul 15 07:11:46 PM PDT 24
Finished Jul 15 07:11:52 PM PDT 24
Peak memory 206624 kb
Host smart-302179c6-59e4-424b-863d-f9f77d4f4c61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203191827 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.4203191827
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1722723465
Short name T269
Test name
Test status
Simulation time 20609493 ps
CPU time 1.15 seconds
Started Jul 15 07:11:49 PM PDT 24
Finished Jul 15 07:11:57 PM PDT 24
Peak memory 206956 kb
Host smart-494c06c5-b4d0-49cf-95ab-094c9caea03d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722723465 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.1722723465
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.3977488338
Short name T1092
Test name
Test status
Simulation time 155707256 ps
CPU time 1.98 seconds
Started Jul 15 07:11:47 PM PDT 24
Finished Jul 15 07:11:55 PM PDT 24
Peak memory 215168 kb
Host smart-ad86d1e7-d11b-4518-9509-9d3dc71884bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977488338 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.3977488338
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3252929631
Short name T1126
Test name
Test status
Simulation time 654851277 ps
CPU time 2.27 seconds
Started Jul 15 07:11:46 PM PDT 24
Finished Jul 15 07:11:53 PM PDT 24
Peak memory 206928 kb
Host smart-613619b0-e63b-47ea-aae0-e866ef4352e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252929631 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.3252929631
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.621467896
Short name T1102
Test name
Test status
Simulation time 16893616 ps
CPU time 1.16 seconds
Started Jul 15 07:11:46 PM PDT 24
Finished Jul 15 07:11:53 PM PDT 24
Peak memory 215232 kb
Host smart-d7887591-1a74-4b23-947c-2991f2c4d117
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621467896 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.621467896
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.267133361
Short name T1028
Test name
Test status
Simulation time 16963572 ps
CPU time 0.81 seconds
Started Jul 15 07:11:49 PM PDT 24
Finished Jul 15 07:11:57 PM PDT 24
Peak memory 206676 kb
Host smart-2b940bdd-6453-41b5-9924-f5d662cc3159
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267133361 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.267133361
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.2611349748
Short name T1108
Test name
Test status
Simulation time 16173399 ps
CPU time 0.93 seconds
Started Jul 15 07:11:52 PM PDT 24
Finished Jul 15 07:12:00 PM PDT 24
Peak memory 206824 kb
Host smart-daee283b-f68e-4adb-a1cf-734e1da4f8a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611349748 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.2611349748
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.4207641102
Short name T1019
Test name
Test status
Simulation time 58213186 ps
CPU time 1.07 seconds
Started Jul 15 07:11:43 PM PDT 24
Finished Jul 15 07:11:48 PM PDT 24
Peak memory 206876 kb
Host smart-01eb7706-f233-4a61-8ef9-ed51dd86e343
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207641102 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.4207641102
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.3506526
Short name T1049
Test name
Test status
Simulation time 143278309 ps
CPU time 2.32 seconds
Started Jul 15 07:11:44 PM PDT 24
Finished Jul 15 07:11:50 PM PDT 24
Peak memory 215220 kb
Host smart-01efcb4a-f91f-4c99-8c20-90550c7da4e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506526 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.3506526
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1974743053
Short name T280
Test name
Test status
Simulation time 93898150 ps
CPU time 1.77 seconds
Started Jul 15 07:11:48 PM PDT 24
Finished Jul 15 07:11:56 PM PDT 24
Peak memory 207076 kb
Host smart-4487800b-3e8d-4fc2-875c-fb35a4531b1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974743053 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1974743053
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1452752466
Short name T1007
Test name
Test status
Simulation time 36829059 ps
CPU time 1.41 seconds
Started Jul 15 07:11:51 PM PDT 24
Finished Jul 15 07:12:00 PM PDT 24
Peak memory 215128 kb
Host smart-4c471803-adc5-4414-8363-09a0009626c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452752466 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.1452752466
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.479475645
Short name T271
Test name
Test status
Simulation time 26812720 ps
CPU time 0.89 seconds
Started Jul 15 07:11:45 PM PDT 24
Finished Jul 15 07:11:51 PM PDT 24
Peak memory 206872 kb
Host smart-167e5091-c49c-4d0e-ae6b-e20a7555e14e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479475645 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.479475645
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.1251639881
Short name T1041
Test name
Test status
Simulation time 20397796 ps
CPU time 0.79 seconds
Started Jul 15 07:11:47 PM PDT 24
Finished Jul 15 07:11:54 PM PDT 24
Peak memory 206680 kb
Host smart-2de6a985-29d0-488f-960b-af71c6d7d2ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251639881 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.1251639881
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2523684433
Short name T1042
Test name
Test status
Simulation time 58340395 ps
CPU time 0.94 seconds
Started Jul 15 07:11:47 PM PDT 24
Finished Jul 15 07:11:53 PM PDT 24
Peak memory 206956 kb
Host smart-78899379-5df2-46b3-9bf6-66073772c333
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523684433 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.2523684433
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.1517188322
Short name T1017
Test name
Test status
Simulation time 31218652 ps
CPU time 2.12 seconds
Started Jul 15 07:11:48 PM PDT 24
Finished Jul 15 07:11:56 PM PDT 24
Peak memory 215140 kb
Host smart-73811be8-c275-4ca8-a628-20f5a93750cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517188322 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1517188322
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1013728584
Short name T286
Test name
Test status
Simulation time 177263606 ps
CPU time 1.54 seconds
Started Jul 15 07:11:52 PM PDT 24
Finished Jul 15 07:12:02 PM PDT 24
Peak memory 206932 kb
Host smart-4620439f-badf-42ae-96d2-89c199177f6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013728584 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.1013728584
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.3796960715
Short name T398
Test name
Test status
Simulation time 25068837 ps
CPU time 1.22 seconds
Started Jul 15 07:12:57 PM PDT 24
Finished Jul 15 07:13:54 PM PDT 24
Peak memory 221180 kb
Host smart-b1e563a7-9b1a-4f42-be2d-092dc27cb8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796960715 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3796960715
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.1249531343
Short name T832
Test name
Test status
Simulation time 32786749 ps
CPU time 0.79 seconds
Started Jul 15 07:13:03 PM PDT 24
Finished Jul 15 07:14:16 PM PDT 24
Peak memory 207136 kb
Host smart-87635466-0ea0-4527-9848-08ca1d64d284
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249531343 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.1249531343
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_err.1681095515
Short name T690
Test name
Test status
Simulation time 41674232 ps
CPU time 0.93 seconds
Started Jul 15 07:12:52 PM PDT 24
Finished Jul 15 07:13:38 PM PDT 24
Peak memory 224072 kb
Host smart-d60695ad-0cfa-4685-bbd5-ac63d67dd77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681095515 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1681095515
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_regwen.2141045060
Short name T917
Test name
Test status
Simulation time 29759287 ps
CPU time 1 seconds
Started Jul 15 07:12:54 PM PDT 24
Finished Jul 15 07:13:45 PM PDT 24
Peak memory 207408 kb
Host smart-cb0f51ff-c039-4810-a636-96b7c313f0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141045060 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.2141045060
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.3449089851
Short name T20
Test name
Test status
Simulation time 270464928 ps
CPU time 4.41 seconds
Started Jul 15 07:12:54 PM PDT 24
Finished Jul 15 07:13:48 PM PDT 24
Peak memory 236212 kb
Host smart-e528de82-87b7-4753-921f-79abe1681f08
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449089851 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.3449089851
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.2704637692
Short name T385
Test name
Test status
Simulation time 21792710 ps
CPU time 0.95 seconds
Started Jul 15 07:12:57 PM PDT 24
Finished Jul 15 07:13:53 PM PDT 24
Peak memory 215620 kb
Host smart-e181ae18-6919-4e73-a7b4-ae30a0c3c7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704637692 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2704637692
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.2609882039
Short name T847
Test name
Test status
Simulation time 489123625 ps
CPU time 4.74 seconds
Started Jul 15 07:13:05 PM PDT 24
Finished Jul 15 07:14:28 PM PDT 24
Peak memory 217692 kb
Host smart-67d94463-a824-4913-a1e1-daf1fad0e3b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609882039 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.2609882039
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.3161166330
Short name T236
Test name
Test status
Simulation time 87292683904 ps
CPU time 1145.01 seconds
Started Jul 15 07:12:56 PM PDT 24
Finished Jul 15 07:32:57 PM PDT 24
Peak memory 225024 kb
Host smart-d3dc47cb-a5de-4096-a324-7a769f28e92d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161166330 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.3161166330
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.1447027791
Short name T889
Test name
Test status
Simulation time 29817838 ps
CPU time 1.26 seconds
Started Jul 15 07:12:54 PM PDT 24
Finished Jul 15 07:13:45 PM PDT 24
Peak memory 219000 kb
Host smart-21bef41f-806f-4a1b-b172-923514782e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447027791 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1447027791
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_err.3654691069
Short name T117
Test name
Test status
Simulation time 22150115 ps
CPU time 1.13 seconds
Started Jul 15 07:13:06 PM PDT 24
Finished Jul 15 07:14:25 PM PDT 24
Peak memory 229932 kb
Host smart-5315d203-1a8e-4cfc-aa43-958acc797f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654691069 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.3654691069
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.2886783391
Short name T609
Test name
Test status
Simulation time 81879300 ps
CPU time 1.19 seconds
Started Jul 15 07:12:52 PM PDT 24
Finished Jul 15 07:13:38 PM PDT 24
Peak memory 220180 kb
Host smart-964d10a5-a1b5-4524-aee9-165f95227178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886783391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2886783391
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.935164099
Short name T676
Test name
Test status
Simulation time 31857971 ps
CPU time 0.94 seconds
Started Jul 15 07:12:53 PM PDT 24
Finished Jul 15 07:13:44 PM PDT 24
Peak memory 224120 kb
Host smart-421ad35e-d25e-457c-9bc7-4ab4d271a67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935164099 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.935164099
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.2187192560
Short name T660
Test name
Test status
Simulation time 18921191 ps
CPU time 1 seconds
Started Jul 15 07:12:58 PM PDT 24
Finished Jul 15 07:14:00 PM PDT 24
Peak memory 207424 kb
Host smart-8b75f76e-322b-4d88-907b-eb4e680769af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187192560 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.2187192560
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.3744125160
Short name T63
Test name
Test status
Simulation time 3632294212 ps
CPU time 4.2 seconds
Started Jul 15 07:12:57 PM PDT 24
Finished Jul 15 07:14:02 PM PDT 24
Peak memory 236068 kb
Host smart-7bd23448-7baa-4f73-8bfd-4939929930cc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744125160 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.3744125160
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.1850740221
Short name T65
Test name
Test status
Simulation time 19607598 ps
CPU time 1 seconds
Started Jul 15 07:13:02 PM PDT 24
Finished Jul 15 07:14:16 PM PDT 24
Peak memory 215604 kb
Host smart-bc93bcc7-a0b6-4a7b-a652-d9472bfab91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850740221 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1850740221
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.3262775768
Short name T462
Test name
Test status
Simulation time 143452479 ps
CPU time 3.08 seconds
Started Jul 15 07:12:54 PM PDT 24
Finished Jul 15 07:13:47 PM PDT 24
Peak memory 218784 kb
Host smart-384e9716-a48a-486c-9141-fdc95c9d81e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262775768 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.3262775768
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_alert.3379609761
Short name T277
Test name
Test status
Simulation time 82901529 ps
CPU time 1.13 seconds
Started Jul 15 07:13:09 PM PDT 24
Finished Jul 15 07:14:31 PM PDT 24
Peak memory 218732 kb
Host smart-107546d2-e2db-4184-9eba-328d89a4d177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379609761 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.3379609761
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.346082991
Short name T605
Test name
Test status
Simulation time 13924248 ps
CPU time 0.89 seconds
Started Jul 15 07:13:02 PM PDT 24
Finished Jul 15 07:14:16 PM PDT 24
Peak memory 215128 kb
Host smart-01a913f6-f1fc-426f-8458-1582d4e5d34f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346082991 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.346082991
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.2683463425
Short name T992
Test name
Test status
Simulation time 11431562 ps
CPU time 0.88 seconds
Started Jul 15 07:13:08 PM PDT 24
Finished Jul 15 07:14:25 PM PDT 24
Peak memory 216536 kb
Host smart-d0a50f86-c0c0-4662-9f3e-af5291e0afc9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683463425 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.2683463425
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_err.1909889193
Short name T215
Test name
Test status
Simulation time 19603802 ps
CPU time 1.04 seconds
Started Jul 15 07:13:07 PM PDT 24
Finished Jul 15 07:14:25 PM PDT 24
Peak memory 218956 kb
Host smart-efbe2281-0e9c-4047-bc74-32042dae9125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909889193 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1909889193
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.2805591923
Short name T896
Test name
Test status
Simulation time 174930625 ps
CPU time 2.54 seconds
Started Jul 15 07:13:04 PM PDT 24
Finished Jul 15 07:14:18 PM PDT 24
Peak memory 220500 kb
Host smart-bd530d59-ac47-4406-8179-fba6eab33a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805591923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.2805591923
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.1577959197
Short name T366
Test name
Test status
Simulation time 23465941 ps
CPU time 1.03 seconds
Started Jul 15 07:13:02 PM PDT 24
Finished Jul 15 07:14:15 PM PDT 24
Peak memory 215836 kb
Host smart-9b3ae4ae-342b-4dc4-9c0d-ed7b19effa22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577959197 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1577959197
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.2581417720
Short name T582
Test name
Test status
Simulation time 38285742 ps
CPU time 0.88 seconds
Started Jul 15 07:12:59 PM PDT 24
Finished Jul 15 07:14:00 PM PDT 24
Peak memory 215412 kb
Host smart-21f36d2b-f8d2-49b6-b9ae-2075bb7e97eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581417720 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.2581417720
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.662113044
Short name T612
Test name
Test status
Simulation time 104815762 ps
CPU time 2.39 seconds
Started Jul 15 07:13:03 PM PDT 24
Finished Jul 15 07:14:18 PM PDT 24
Peak memory 215608 kb
Host smart-ff3efcf4-866c-4c65-88c9-ef21a42644ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662113044 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.662113044
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.621193458
Short name T910
Test name
Test status
Simulation time 88566166358 ps
CPU time 770.56 seconds
Started Jul 15 07:12:58 PM PDT 24
Finished Jul 15 07:26:49 PM PDT 24
Peak memory 224008 kb
Host smart-bbe8ea85-7a5f-41ec-ab20-80c0fd349e6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621193458 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.621193458
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.619273100
Short name T778
Test name
Test status
Simulation time 45240818 ps
CPU time 1.21 seconds
Started Jul 15 07:15:55 PM PDT 24
Finished Jul 15 07:16:49 PM PDT 24
Peak memory 215964 kb
Host smart-a00c14f8-9bf1-4f57-920d-f99174ce4319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619273100 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.619273100
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.3720700338
Short name T356
Test name
Test status
Simulation time 59146246 ps
CPU time 1.34 seconds
Started Jul 15 07:15:59 PM PDT 24
Finished Jul 15 07:16:53 PM PDT 24
Peak memory 218912 kb
Host smart-d977bd8f-666b-47fd-b617-8f557301a8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720700338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.3720700338
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.1500405040
Short name T859
Test name
Test status
Simulation time 54141034 ps
CPU time 1.21 seconds
Started Jul 15 07:15:53 PM PDT 24
Finished Jul 15 07:16:48 PM PDT 24
Peak memory 220180 kb
Host smart-34d52af7-460e-4d49-8ca5-ea59b6d614b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500405040 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.1500405040
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/102.edn_alert.3501926660
Short name T590
Test name
Test status
Simulation time 154331421 ps
CPU time 1.21 seconds
Started Jul 15 07:15:56 PM PDT 24
Finished Jul 15 07:16:49 PM PDT 24
Peak memory 218916 kb
Host smart-3f20e566-fd45-41f9-a372-f66bcf3ff6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501926660 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.3501926660
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.635887978
Short name T484
Test name
Test status
Simulation time 106587483 ps
CPU time 2.33 seconds
Started Jul 15 07:15:54 PM PDT 24
Finished Jul 15 07:16:50 PM PDT 24
Peak memory 215648 kb
Host smart-34ac5cf7-f8e4-40e5-9b21-5540cf201040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635887978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.635887978
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.1392837142
Short name T474
Test name
Test status
Simulation time 34783301 ps
CPU time 1.18 seconds
Started Jul 15 07:16:01 PM PDT 24
Finished Jul 15 07:16:53 PM PDT 24
Peak memory 219024 kb
Host smart-a6213dc5-cb96-4e21-933a-504c08ec8a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392837142 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.1392837142
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/104.edn_alert.2664319904
Short name T250
Test name
Test status
Simulation time 250476837 ps
CPU time 1.12 seconds
Started Jul 15 07:15:55 PM PDT 24
Finished Jul 15 07:16:49 PM PDT 24
Peak memory 221028 kb
Host smart-604b1f5e-e442-4fe0-a6dd-346b99006223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664319904 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.2664319904
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/105.edn_alert.2272502799
Short name T409
Test name
Test status
Simulation time 35641040 ps
CPU time 1.09 seconds
Started Jul 15 07:15:53 PM PDT 24
Finished Jul 15 07:16:47 PM PDT 24
Peak memory 220580 kb
Host smart-02710402-92b4-4de3-9ab2-4a8804f0d870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272502799 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.2272502799
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/106.edn_alert.2163419703
Short name T291
Test name
Test status
Simulation time 62373274 ps
CPU time 1.05 seconds
Started Jul 15 07:16:03 PM PDT 24
Finished Jul 15 07:16:55 PM PDT 24
Peak memory 219376 kb
Host smart-642573f3-b6ac-4d4a-bee2-c40da2920c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163419703 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.2163419703
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.150017509
Short name T630
Test name
Test status
Simulation time 49103373 ps
CPU time 1.88 seconds
Started Jul 15 07:15:55 PM PDT 24
Finished Jul 15 07:16:49 PM PDT 24
Peak memory 218792 kb
Host smart-76bfec7c-2002-4ffb-bb44-c427df0dd1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150017509 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.150017509
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.3468177184
Short name T188
Test name
Test status
Simulation time 23175563 ps
CPU time 1.17 seconds
Started Jul 15 07:16:01 PM PDT 24
Finished Jul 15 07:16:53 PM PDT 24
Peak memory 221260 kb
Host smart-38ecd8d6-7ec0-46e7-b7a6-05edd0f652d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468177184 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.3468177184
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.3800847206
Short name T761
Test name
Test status
Simulation time 66682600 ps
CPU time 1.23 seconds
Started Jul 15 07:16:00 PM PDT 24
Finished Jul 15 07:16:53 PM PDT 24
Peak memory 217748 kb
Host smart-9c7049f9-0b50-419d-90af-9afce383a485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800847206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.3800847206
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.1125236353
Short name T753
Test name
Test status
Simulation time 93326855 ps
CPU time 1.2 seconds
Started Jul 15 07:16:05 PM PDT 24
Finished Jul 15 07:16:56 PM PDT 24
Peak memory 219540 kb
Host smart-b8e2472a-2c3f-49dc-a4a2-5f5eceddc45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125236353 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.1125236353
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.1457376159
Short name T659
Test name
Test status
Simulation time 314598932 ps
CPU time 3.19 seconds
Started Jul 15 07:16:01 PM PDT 24
Finished Jul 15 07:16:55 PM PDT 24
Peak memory 220628 kb
Host smart-21dc2523-b48e-4958-994a-20da4b7aa02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457376159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.1457376159
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.3181631833
Short name T853
Test name
Test status
Simulation time 104992960 ps
CPU time 1.12 seconds
Started Jul 15 07:15:59 PM PDT 24
Finished Jul 15 07:16:52 PM PDT 24
Peak memory 218840 kb
Host smart-f4b62d17-2cf4-43e4-84f3-f510f81b3397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181631833 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.3181631833
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.1143012897
Short name T53
Test name
Test status
Simulation time 111644591 ps
CPU time 2.39 seconds
Started Jul 15 07:16:05 PM PDT 24
Finished Jul 15 07:16:57 PM PDT 24
Peak memory 220496 kb
Host smart-27ef94c5-e51e-4602-a491-c94588711140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143012897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.1143012897
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.276179234
Short name T193
Test name
Test status
Simulation time 31136309 ps
CPU time 1.31 seconds
Started Jul 15 07:13:10 PM PDT 24
Finished Jul 15 07:14:31 PM PDT 24
Peak memory 215956 kb
Host smart-57d9deec-3656-4077-90da-7252965d9f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276179234 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.276179234
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.3584031530
Short name T77
Test name
Test status
Simulation time 53077047 ps
CPU time 0.83 seconds
Started Jul 15 07:12:58 PM PDT 24
Finished Jul 15 07:14:00 PM PDT 24
Peak memory 206532 kb
Host smart-46345e3e-25fe-4e87-af31-c9271b30add3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584031530 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.3584031530
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.2039340384
Short name T95
Test name
Test status
Simulation time 19532651 ps
CPU time 0.86 seconds
Started Jul 15 07:13:16 PM PDT 24
Finished Jul 15 07:14:40 PM PDT 24
Peak memory 216624 kb
Host smart-b134867a-3c3b-4cdf-b642-b4125b33b60a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039340384 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.2039340384
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.3199742561
Short name T919
Test name
Test status
Simulation time 292467643 ps
CPU time 0.95 seconds
Started Jul 15 07:13:07 PM PDT 24
Finished Jul 15 07:14:25 PM PDT 24
Peak memory 220000 kb
Host smart-c3f5c4b0-4534-4229-bd27-1fa85caee67a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199742561 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.3199742561
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.359070365
Short name T55
Test name
Test status
Simulation time 24755649 ps
CPU time 1.21 seconds
Started Jul 15 07:13:04 PM PDT 24
Finished Jul 15 07:14:17 PM PDT 24
Peak memory 230012 kb
Host smart-f4348bd3-5f00-40ed-945a-ab3c7e6674f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359070365 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.359070365
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_intr.137246002
Short name T478
Test name
Test status
Simulation time 28330987 ps
CPU time 0.94 seconds
Started Jul 15 07:13:06 PM PDT 24
Finished Jul 15 07:14:25 PM PDT 24
Peak memory 215848 kb
Host smart-f7705c2d-92cb-4538-a248-ee438e62ef08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137246002 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.137246002
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.150441629
Short name T360
Test name
Test status
Simulation time 19691102 ps
CPU time 1 seconds
Started Jul 15 07:13:00 PM PDT 24
Finished Jul 15 07:14:08 PM PDT 24
Peak memory 215628 kb
Host smart-8825465e-bddd-424f-bc8c-da928e9800a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150441629 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.150441629
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.3864912869
Short name T545
Test name
Test status
Simulation time 170630636 ps
CPU time 3.68 seconds
Started Jul 15 07:13:04 PM PDT 24
Finished Jul 15 07:14:20 PM PDT 24
Peak memory 220164 kb
Host smart-1ab12f2e-46e7-4633-9c90-7bee8d87ccd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864912869 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.3864912869
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.3485492993
Short name T103
Test name
Test status
Simulation time 26255624258 ps
CPU time 584.62 seconds
Started Jul 15 07:13:01 PM PDT 24
Finished Jul 15 07:23:52 PM PDT 24
Peak memory 218320 kb
Host smart-c051c719-b72e-4fff-bd40-e794e8a50939
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485492993 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.3485492993
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.3336243219
Short name T83
Test name
Test status
Simulation time 129489970 ps
CPU time 1.14 seconds
Started Jul 15 07:15:58 PM PDT 24
Finished Jul 15 07:16:52 PM PDT 24
Peak memory 219700 kb
Host smart-a2f40a15-3953-4d3f-9323-ed5dd4088b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336243219 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.3336243219
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.620379852
Short name T672
Test name
Test status
Simulation time 143110358 ps
CPU time 3.12 seconds
Started Jul 15 07:16:02 PM PDT 24
Finished Jul 15 07:16:57 PM PDT 24
Peak memory 220396 kb
Host smart-433fbfc4-c794-44df-9965-613af715c12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620379852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.620379852
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.1498157656
Short name T126
Test name
Test status
Simulation time 105096081 ps
CPU time 1.36 seconds
Started Jul 15 07:16:02 PM PDT 24
Finished Jul 15 07:16:53 PM PDT 24
Peak memory 215924 kb
Host smart-1f26bb74-9514-45e0-8da1-7130a17728dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498157656 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.1498157656
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.1982692086
Short name T357
Test name
Test status
Simulation time 451619853 ps
CPU time 1.38 seconds
Started Jul 15 07:16:00 PM PDT 24
Finished Jul 15 07:16:53 PM PDT 24
Peak memory 217576 kb
Host smart-7022de87-40cf-4287-8ef0-193697e04bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982692086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1982692086
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.2620426245
Short name T502
Test name
Test status
Simulation time 71190961 ps
CPU time 1.09 seconds
Started Jul 15 07:16:08 PM PDT 24
Finished Jul 15 07:17:00 PM PDT 24
Peak memory 220292 kb
Host smart-6d5dd183-8ad4-4ed0-ac32-83ca07ea816d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620426245 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.2620426245
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.3728460520
Short name T898
Test name
Test status
Simulation time 76570118 ps
CPU time 1.34 seconds
Started Jul 15 07:15:59 PM PDT 24
Finished Jul 15 07:16:53 PM PDT 24
Peak memory 219088 kb
Host smart-f8d576b4-3728-4e27-8693-ff310a1685c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728460520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.3728460520
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.2208477362
Short name T828
Test name
Test status
Simulation time 86899567 ps
CPU time 1.14 seconds
Started Jul 15 07:16:05 PM PDT 24
Finished Jul 15 07:16:56 PM PDT 24
Peak memory 219500 kb
Host smart-ea93a243-3225-450b-bfa3-ccfbf5750d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208477362 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.2208477362
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.2055513711
Short name T240
Test name
Test status
Simulation time 41887060 ps
CPU time 1.69 seconds
Started Jul 15 07:16:04 PM PDT 24
Finished Jul 15 07:16:56 PM PDT 24
Peak memory 218724 kb
Host smart-657d67de-519a-43ca-b717-ddd298f25785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055513711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.2055513711
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.130403631
Short name T92
Test name
Test status
Simulation time 24000841 ps
CPU time 1.18 seconds
Started Jul 15 07:16:07 PM PDT 24
Finished Jul 15 07:16:59 PM PDT 24
Peak memory 220196 kb
Host smart-1b0b191f-6396-4bbe-9e96-940a0545f154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130403631 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.130403631
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/115.edn_alert.617410052
Short name T505
Test name
Test status
Simulation time 88984241 ps
CPU time 1.25 seconds
Started Jul 15 07:16:06 PM PDT 24
Finished Jul 15 07:16:56 PM PDT 24
Peak memory 220516 kb
Host smart-1c3792b2-c8ef-4b27-8435-31b75f296ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617410052 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.617410052
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.3303630582
Short name T601
Test name
Test status
Simulation time 97339223 ps
CPU time 1.52 seconds
Started Jul 15 07:16:11 PM PDT 24
Finished Jul 15 07:17:04 PM PDT 24
Peak memory 217676 kb
Host smart-fe8edd6d-aaf2-4597-a44a-403b7dc5cc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303630582 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.3303630582
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.2076767882
Short name T764
Test name
Test status
Simulation time 65896585 ps
CPU time 1.08 seconds
Started Jul 15 07:16:09 PM PDT 24
Finished Jul 15 07:16:59 PM PDT 24
Peak memory 218964 kb
Host smart-b81a74ab-6be8-48f3-a3f5-e45628705226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076767882 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.2076767882
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.21804584
Short name T362
Test name
Test status
Simulation time 61495217 ps
CPU time 1.32 seconds
Started Jul 15 07:16:08 PM PDT 24
Finished Jul 15 07:16:59 PM PDT 24
Peak memory 219000 kb
Host smart-7cdd56e4-aed9-4348-bcfd-bc62cfd144db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21804584 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.21804584
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.1310061462
Short name T986
Test name
Test status
Simulation time 40810543 ps
CPU time 1.06 seconds
Started Jul 15 07:16:05 PM PDT 24
Finished Jul 15 07:16:56 PM PDT 24
Peak memory 220948 kb
Host smart-5f8bee9c-f6d8-4c79-81ed-b5bf8b1a5592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310061462 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.1310061462
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.1182725834
Short name T786
Test name
Test status
Simulation time 51451138 ps
CPU time 1.3 seconds
Started Jul 15 07:16:09 PM PDT 24
Finished Jul 15 07:16:59 PM PDT 24
Peak memory 219812 kb
Host smart-72929019-f21c-46ee-94c3-8b108283db97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182725834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.1182725834
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.1099213447
Short name T733
Test name
Test status
Simulation time 54580534 ps
CPU time 1.68 seconds
Started Jul 15 07:16:07 PM PDT 24
Finished Jul 15 07:17:00 PM PDT 24
Peak memory 218984 kb
Host smart-3d9ed193-4305-40bc-9667-0e8064da70f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099213447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1099213447
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.3874035277
Short name T624
Test name
Test status
Simulation time 36440115 ps
CPU time 1.48 seconds
Started Jul 15 07:16:08 PM PDT 24
Finished Jul 15 07:17:00 PM PDT 24
Peak memory 220424 kb
Host smart-911d3cee-859b-4c62-ac3b-257adc2d8637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874035277 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3874035277
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert_test.1392932386
Short name T728
Test name
Test status
Simulation time 26780008 ps
CPU time 0.88 seconds
Started Jul 15 07:13:06 PM PDT 24
Finished Jul 15 07:14:24 PM PDT 24
Peak memory 215192 kb
Host smart-aaae78d0-fcd5-40c5-9e3d-136a72c9e0f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392932386 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.1392932386
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3775122137
Short name T157
Test name
Test status
Simulation time 68999219 ps
CPU time 1.27 seconds
Started Jul 15 07:13:14 PM PDT 24
Finished Jul 15 07:14:40 PM PDT 24
Peak memory 217200 kb
Host smart-2a2d8e65-98ad-406f-8e97-8203a66e5c7d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775122137 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3775122137
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_genbits.3021896461
Short name T344
Test name
Test status
Simulation time 45114224 ps
CPU time 1.11 seconds
Started Jul 15 07:13:12 PM PDT 24
Finished Jul 15 07:14:32 PM PDT 24
Peak memory 220132 kb
Host smart-e859e4b9-03ae-46b7-a490-01e794fc8cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021896461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.3021896461
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_smoke.623060917
Short name T604
Test name
Test status
Simulation time 23628507 ps
CPU time 0.91 seconds
Started Jul 15 07:12:59 PM PDT 24
Finished Jul 15 07:14:00 PM PDT 24
Peak memory 215484 kb
Host smart-a80bdf0b-a5c3-4729-9d8b-2b67b9734e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623060917 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.623060917
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.909652274
Short name T807
Test name
Test status
Simulation time 785741470 ps
CPU time 3.88 seconds
Started Jul 15 07:13:21 PM PDT 24
Finished Jul 15 07:14:57 PM PDT 24
Peak memory 217588 kb
Host smart-757da233-b7d8-439c-82ee-9a06a8ce1f39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909652274 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.909652274
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.3919002716
Short name T716
Test name
Test status
Simulation time 137960023153 ps
CPU time 1709.6 seconds
Started Jul 15 07:13:06 PM PDT 24
Finished Jul 15 07:42:54 PM PDT 24
Peak memory 228276 kb
Host smart-b3b9b097-9093-4a5d-8f6b-e2b4add7d4ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919002716 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.3919002716
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.3575945587
Short name T524
Test name
Test status
Simulation time 29880601 ps
CPU time 1.3 seconds
Started Jul 15 07:16:11 PM PDT 24
Finished Jul 15 07:17:04 PM PDT 24
Peak memory 219688 kb
Host smart-ae0cb735-4051-46e1-afc7-5c66ad9ca856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575945587 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.3575945587
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.3858168613
Short name T493
Test name
Test status
Simulation time 44639656 ps
CPU time 1.21 seconds
Started Jul 15 07:16:08 PM PDT 24
Finished Jul 15 07:17:00 PM PDT 24
Peak memory 217548 kb
Host smart-93bf0bf8-ef95-43ec-b314-a7b4250fc6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858168613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3858168613
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.3121791546
Short name T153
Test name
Test status
Simulation time 36937042 ps
CPU time 1.15 seconds
Started Jul 15 07:16:10 PM PDT 24
Finished Jul 15 07:16:58 PM PDT 24
Peak memory 220556 kb
Host smart-9c4b9d69-8357-4ac8-b9e1-cfba6232a2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121791546 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.3121791546
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.1834912334
Short name T867
Test name
Test status
Simulation time 84449105 ps
CPU time 1.08 seconds
Started Jul 15 07:16:09 PM PDT 24
Finished Jul 15 07:16:59 PM PDT 24
Peak memory 219092 kb
Host smart-123013d0-7f94-4523-ad07-cd76265270bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834912334 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.1834912334
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.3039741176
Short name T167
Test name
Test status
Simulation time 55291625 ps
CPU time 1.24 seconds
Started Jul 15 07:16:09 PM PDT 24
Finished Jul 15 07:16:59 PM PDT 24
Peak memory 215980 kb
Host smart-08ac1ab0-8456-4260-8308-e1ef3e3838fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039741176 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.3039741176
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.1316216750
Short name T686
Test name
Test status
Simulation time 49653735 ps
CPU time 1.18 seconds
Started Jul 15 07:16:06 PM PDT 24
Finished Jul 15 07:16:56 PM PDT 24
Peak memory 217588 kb
Host smart-b9965fd4-7304-4a56-b66a-af16e9939748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316216750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.1316216750
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.686103028
Short name T596
Test name
Test status
Simulation time 36800286 ps
CPU time 1.19 seconds
Started Jul 15 07:16:06 PM PDT 24
Finished Jul 15 07:16:55 PM PDT 24
Peak memory 219040 kb
Host smart-89ba856f-55ad-4ca1-b01a-172193a9a20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686103028 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.686103028
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.1500928370
Short name T777
Test name
Test status
Simulation time 34667610 ps
CPU time 1.47 seconds
Started Jul 15 07:16:07 PM PDT 24
Finished Jul 15 07:16:59 PM PDT 24
Peak memory 217764 kb
Host smart-7e242c29-af7d-4f29-adcf-c8a7a1eafa8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500928370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.1500928370
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.312448168
Short name T942
Test name
Test status
Simulation time 223924085 ps
CPU time 1.11 seconds
Started Jul 15 07:16:09 PM PDT 24
Finished Jul 15 07:16:59 PM PDT 24
Peak memory 219956 kb
Host smart-7426c73f-fb4a-459c-9ca8-6e306abece7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312448168 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.312448168
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.115606621
Short name T903
Test name
Test status
Simulation time 32682680 ps
CPU time 1.28 seconds
Started Jul 15 07:16:10 PM PDT 24
Finished Jul 15 07:17:00 PM PDT 24
Peak memory 220256 kb
Host smart-a1cdaa75-f869-4805-9740-76af857f48d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115606621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.115606621
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.2246239504
Short name T463
Test name
Test status
Simulation time 196695996 ps
CPU time 1.25 seconds
Started Jul 15 07:16:09 PM PDT 24
Finished Jul 15 07:16:59 PM PDT 24
Peak memory 215952 kb
Host smart-ffcdfcef-f87e-4f92-a92e-e359384b327d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246239504 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.2246239504
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.3184598848
Short name T519
Test name
Test status
Simulation time 57510266 ps
CPU time 1.01 seconds
Started Jul 15 07:16:09 PM PDT 24
Finished Jul 15 07:16:59 PM PDT 24
Peak memory 217656 kb
Host smart-c0cd083e-5ca3-45a5-93f2-5b89bdca0c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184598848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.3184598848
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.778275300
Short name T93
Test name
Test status
Simulation time 42898434 ps
CPU time 1.13 seconds
Started Jul 15 07:16:10 PM PDT 24
Finished Jul 15 07:16:59 PM PDT 24
Peak memory 215984 kb
Host smart-73ad6b68-d8e4-4cf1-8d64-ccdc5d5778e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778275300 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.778275300
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.1892543564
Short name T663
Test name
Test status
Simulation time 35348915 ps
CPU time 1.37 seconds
Started Jul 15 07:16:08 PM PDT 24
Finished Jul 15 07:16:59 PM PDT 24
Peak memory 218716 kb
Host smart-177b393e-664d-4878-bd5d-6edddf08bea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892543564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.1892543564
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.2604874346
Short name T553
Test name
Test status
Simulation time 33789295 ps
CPU time 1.27 seconds
Started Jul 15 07:16:08 PM PDT 24
Finished Jul 15 07:17:00 PM PDT 24
Peak memory 219008 kb
Host smart-d57ac361-a5ef-4852-9646-dba75072a94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604874346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.2604874346
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.3856209303
Short name T178
Test name
Test status
Simulation time 23874824 ps
CPU time 1.16 seconds
Started Jul 15 07:16:15 PM PDT 24
Finished Jul 15 07:17:04 PM PDT 24
Peak memory 220228 kb
Host smart-92cca059-8f44-4fd1-86f1-c3ff1f8cbecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856209303 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.3856209303
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.1888140186
Short name T488
Test name
Test status
Simulation time 75494118 ps
CPU time 1.05 seconds
Started Jul 15 07:16:15 PM PDT 24
Finished Jul 15 07:17:04 PM PDT 24
Peak memory 217648 kb
Host smart-e6c998ef-fe0d-4c37-b725-2feba31fbac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888140186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.1888140186
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.139698631
Short name T527
Test name
Test status
Simulation time 169105145 ps
CPU time 1.3 seconds
Started Jul 15 07:16:14 PM PDT 24
Finished Jul 15 07:17:04 PM PDT 24
Peak memory 220080 kb
Host smart-f20c9071-8214-4ea0-ac38-59a7804e76b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139698631 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.139698631
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.4081377567
Short name T443
Test name
Test status
Simulation time 97351665 ps
CPU time 1.39 seconds
Started Jul 15 07:16:14 PM PDT 24
Finished Jul 15 07:17:04 PM PDT 24
Peak memory 218736 kb
Host smart-efe61a8f-8625-41a6-9673-00fb01fa1793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081377567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.4081377567
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert_test.2648884923
Short name T434
Test name
Test status
Simulation time 47099389 ps
CPU time 1.02 seconds
Started Jul 15 07:13:08 PM PDT 24
Finished Jul 15 07:14:26 PM PDT 24
Peak memory 207044 kb
Host smart-8617dfaf-ae83-45b7-ab6a-04227e5aa988
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648884923 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.2648884923
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.2172756599
Short name T166
Test name
Test status
Simulation time 16456212 ps
CPU time 0.87 seconds
Started Jul 15 07:13:07 PM PDT 24
Finished Jul 15 07:14:25 PM PDT 24
Peak memory 216552 kb
Host smart-c905d836-112d-4dc2-91c4-0d559dad5fa1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172756599 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.2172756599
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.595111630
Short name T833
Test name
Test status
Simulation time 72569278 ps
CPU time 1.12 seconds
Started Jul 15 07:13:12 PM PDT 24
Finished Jul 15 07:14:32 PM PDT 24
Peak memory 215932 kb
Host smart-8a4fadba-7baf-4384-b3fa-d5b3b2943360
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595111630 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_di
sable_auto_req_mode.595111630
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.3265424003
Short name T839
Test name
Test status
Simulation time 19603556 ps
CPU time 1.05 seconds
Started Jul 15 07:13:15 PM PDT 24
Finished Jul 15 07:14:40 PM PDT 24
Peak memory 218856 kb
Host smart-9eb93372-33dd-41b6-8ad0-951ab81ebd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265424003 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.3265424003
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.3565933233
Short name T68
Test name
Test status
Simulation time 42544246 ps
CPU time 1.4 seconds
Started Jul 15 07:13:09 PM PDT 24
Finished Jul 15 07:14:24 PM PDT 24
Peak memory 218824 kb
Host smart-f9106142-0415-4a92-bf01-ff041af0c383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565933233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.3565933233
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.2134173566
Short name T886
Test name
Test status
Simulation time 28462732 ps
CPU time 0.94 seconds
Started Jul 15 07:13:12 PM PDT 24
Finished Jul 15 07:14:32 PM PDT 24
Peak memory 215828 kb
Host smart-521bf3d7-0860-4ba9-b6fd-facff3c730b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134173566 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.2134173566
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.386365568
Short name T389
Test name
Test status
Simulation time 102586361 ps
CPU time 0.94 seconds
Started Jul 15 07:13:06 PM PDT 24
Finished Jul 15 07:14:25 PM PDT 24
Peak memory 215576 kb
Host smart-5e970d18-65ed-46b1-a180-88f4d65c8a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386365568 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.386365568
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.333540063
Short name T54
Test name
Test status
Simulation time 549763750 ps
CPU time 3.04 seconds
Started Jul 15 07:13:15 PM PDT 24
Finished Jul 15 07:14:41 PM PDT 24
Peak memory 215568 kb
Host smart-37782dc4-421a-483e-98b1-d535abf9901b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333540063 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.333540063
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2833641613
Short name T726
Test name
Test status
Simulation time 58279710613 ps
CPU time 765.86 seconds
Started Jul 15 07:13:13 PM PDT 24
Finished Jul 15 07:27:23 PM PDT 24
Peak memory 224076 kb
Host smart-f6f6494b-a27a-408b-a588-e483cfd82276
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833641613 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.2833641613
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.2790646474
Short name T550
Test name
Test status
Simulation time 58223596 ps
CPU time 1.11 seconds
Started Jul 15 07:16:17 PM PDT 24
Finished Jul 15 07:17:08 PM PDT 24
Peak memory 220656 kb
Host smart-9c1cd2ef-5c18-4d6e-a4df-84eced578663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790646474 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.2790646474
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.3021760882
Short name T586
Test name
Test status
Simulation time 182242611 ps
CPU time 2.29 seconds
Started Jul 15 07:16:14 PM PDT 24
Finished Jul 15 07:17:05 PM PDT 24
Peak memory 220232 kb
Host smart-18d370d5-4001-4761-9a66-b4333b6f317c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021760882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.3021760882
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.2593736639
Short name T616
Test name
Test status
Simulation time 192399250 ps
CPU time 1.41 seconds
Started Jul 15 07:16:14 PM PDT 24
Finished Jul 15 07:17:04 PM PDT 24
Peak memory 218896 kb
Host smart-b652c573-83f1-4802-a4dc-2df6a2632f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593736639 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.2593736639
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.2908026776
Short name T843
Test name
Test status
Simulation time 36085934 ps
CPU time 1.35 seconds
Started Jul 15 07:16:17 PM PDT 24
Finished Jul 15 07:17:08 PM PDT 24
Peak memory 218976 kb
Host smart-9337a3a5-bd34-4b98-bfe2-ebb7920e4cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908026776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2908026776
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.3475698498
Short name T661
Test name
Test status
Simulation time 32359658 ps
CPU time 1.19 seconds
Started Jul 15 07:16:17 PM PDT 24
Finished Jul 15 07:17:07 PM PDT 24
Peak memory 219776 kb
Host smart-316a686f-b980-47a0-af35-bf230fd60d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475698498 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.3475698498
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.2304008681
Short name T542
Test name
Test status
Simulation time 74819667 ps
CPU time 1.39 seconds
Started Jul 15 07:16:17 PM PDT 24
Finished Jul 15 07:17:07 PM PDT 24
Peak memory 218928 kb
Host smart-74c57c21-eaef-4949-a608-a4bcb14e75a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304008681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.2304008681
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.4227224811
Short name T671
Test name
Test status
Simulation time 45387536 ps
CPU time 1.18 seconds
Started Jul 15 07:16:16 PM PDT 24
Finished Jul 15 07:17:04 PM PDT 24
Peak memory 220272 kb
Host smart-42bce265-59dc-4e68-8aad-615868cce3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227224811 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.4227224811
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.2703128810
Short name T557
Test name
Test status
Simulation time 19701399 ps
CPU time 1.09 seconds
Started Jul 15 07:16:20 PM PDT 24
Finished Jul 15 07:17:07 PM PDT 24
Peak memory 218108 kb
Host smart-da42ad08-8ead-40c9-96cc-0e1764db9030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703128810 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.2703128810
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.1105396342
Short name T869
Test name
Test status
Simulation time 106574075 ps
CPU time 1.17 seconds
Started Jul 15 07:16:15 PM PDT 24
Finished Jul 15 07:17:04 PM PDT 24
Peak memory 219840 kb
Host smart-97d2fecd-4598-404f-a9e9-99d9796ed012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105396342 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.1105396342
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.673762734
Short name T394
Test name
Test status
Simulation time 53794077 ps
CPU time 1.67 seconds
Started Jul 15 07:16:16 PM PDT 24
Finished Jul 15 07:17:05 PM PDT 24
Peak memory 218960 kb
Host smart-d1f45f55-e638-4210-9a23-08f271fcf58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673762734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.673762734
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.1050131007
Short name T414
Test name
Test status
Simulation time 30754620 ps
CPU time 1.28 seconds
Started Jul 15 07:16:20 PM PDT 24
Finished Jul 15 07:17:08 PM PDT 24
Peak memory 219820 kb
Host smart-92d75341-0b8c-44e0-a32e-587068843434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050131007 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.1050131007
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.2867361774
Short name T473
Test name
Test status
Simulation time 81628435 ps
CPU time 1.17 seconds
Started Jul 15 07:16:15 PM PDT 24
Finished Jul 15 07:17:04 PM PDT 24
Peak memory 217612 kb
Host smart-5fff64a7-03fe-44bc-bee7-0414dce8b84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867361774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.2867361774
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.1334537289
Short name T8
Test name
Test status
Simulation time 28100385 ps
CPU time 1.16 seconds
Started Jul 15 07:16:13 PM PDT 24
Finished Jul 15 07:17:04 PM PDT 24
Peak memory 218852 kb
Host smart-b0e6a4da-351f-4308-919e-70c7103e310e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334537289 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.1334537289
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.1061455543
Short name T340
Test name
Test status
Simulation time 43853644 ps
CPU time 1.55 seconds
Started Jul 15 07:16:14 PM PDT 24
Finished Jul 15 07:17:04 PM PDT 24
Peak memory 218836 kb
Host smart-00bd557d-e9d2-4679-9841-66d3f2c98a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061455543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.1061455543
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.1271774168
Short name T673
Test name
Test status
Simulation time 30285120 ps
CPU time 1.11 seconds
Started Jul 15 07:16:18 PM PDT 24
Finished Jul 15 07:17:09 PM PDT 24
Peak memory 220104 kb
Host smart-ea05a534-ab6b-41d3-ab9a-9b913797cd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271774168 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.1271774168
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.1168081655
Short name T464
Test name
Test status
Simulation time 33997121 ps
CPU time 1.3 seconds
Started Jul 15 07:16:17 PM PDT 24
Finished Jul 15 07:17:09 PM PDT 24
Peak memory 218840 kb
Host smart-38b9e126-fbf2-4a81-b09a-4d9eb89ec83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168081655 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1168081655
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.4088337397
Short name T721
Test name
Test status
Simulation time 78810715 ps
CPU time 1.1 seconds
Started Jul 15 07:16:18 PM PDT 24
Finished Jul 15 07:17:09 PM PDT 24
Peak memory 219836 kb
Host smart-4e41c53d-e85d-4ecb-8828-a8bacc508867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088337397 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.4088337397
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.2001364032
Short name T704
Test name
Test status
Simulation time 35853065 ps
CPU time 1.05 seconds
Started Jul 15 07:16:18 PM PDT 24
Finished Jul 15 07:17:09 PM PDT 24
Peak memory 217520 kb
Host smart-7e0ff55c-3ce8-4f91-9f28-e31bc915592f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001364032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.2001364032
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.1198576520
Short name T449
Test name
Test status
Simulation time 46855831 ps
CPU time 1.21 seconds
Started Jul 15 07:16:23 PM PDT 24
Finished Jul 15 07:17:12 PM PDT 24
Peak memory 221232 kb
Host smart-34f7aad2-937d-460d-89e5-9a07ee78ae14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198576520 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.1198576520
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.2571598003
Short name T846
Test name
Test status
Simulation time 31100787 ps
CPU time 1.07 seconds
Started Jul 15 07:16:16 PM PDT 24
Finished Jul 15 07:17:07 PM PDT 24
Peak memory 220376 kb
Host smart-abd5fc43-fda4-4ee9-94da-c61155bf479e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571598003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.2571598003
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.1367176832
Short name T617
Test name
Test status
Simulation time 99113145 ps
CPU time 1.13 seconds
Started Jul 15 07:13:19 PM PDT 24
Finished Jul 15 07:14:48 PM PDT 24
Peak memory 218692 kb
Host smart-025e293e-46a2-4c7b-8762-ec8a0e0aefb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367176832 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.1367176832
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.4267243657
Short name T750
Test name
Test status
Simulation time 32504910 ps
CPU time 1.1 seconds
Started Jul 15 07:13:17 PM PDT 24
Finished Jul 15 07:14:47 PM PDT 24
Peak memory 207060 kb
Host smart-21f5bec1-43c3-4589-9b2b-7a442b2d2b1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267243657 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.4267243657
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.3068946236
Short name T655
Test name
Test status
Simulation time 26147287 ps
CPU time 0.85 seconds
Started Jul 15 07:13:18 PM PDT 24
Finished Jul 15 07:14:48 PM PDT 24
Peak memory 216540 kb
Host smart-b531b58a-bb77-441c-8907-c34a8805d1e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068946236 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3068946236
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.1136796158
Short name T522
Test name
Test status
Simulation time 54641384 ps
CPU time 1.18 seconds
Started Jul 15 07:13:11 PM PDT 24
Finished Jul 15 07:14:32 PM PDT 24
Peak memory 217204 kb
Host smart-0999c369-ee1c-4ef3-a1ee-72f7cd81a78c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136796158 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.1136796158
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.359384332
Short name T129
Test name
Test status
Simulation time 64241199 ps
CPU time 1.14 seconds
Started Jul 15 07:13:17 PM PDT 24
Finished Jul 15 07:14:47 PM PDT 24
Peak memory 229976 kb
Host smart-2565d162-a552-4a16-96db-3e439f759447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359384332 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.359384332
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_intr.124539064
Short name T532
Test name
Test status
Simulation time 21790244 ps
CPU time 1.16 seconds
Started Jul 15 07:13:11 PM PDT 24
Finished Jul 15 07:14:32 PM PDT 24
Peak memory 224296 kb
Host smart-bee88365-505c-4d00-968c-67d40f89ba23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124539064 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.124539064
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.3896085718
Short name T959
Test name
Test status
Simulation time 17200367 ps
CPU time 1 seconds
Started Jul 15 07:13:17 PM PDT 24
Finished Jul 15 07:14:48 PM PDT 24
Peak memory 215588 kb
Host smart-216e75d0-dfbe-4d4d-a737-8848c9363d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896085718 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.3896085718
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.2290957234
Short name T683
Test name
Test status
Simulation time 300371520 ps
CPU time 2.15 seconds
Started Jul 15 07:13:15 PM PDT 24
Finished Jul 15 07:14:41 PM PDT 24
Peak memory 215560 kb
Host smart-ed7ed677-1540-4c48-9ba2-1c7fd66a1610
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290957234 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.2290957234
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.509330244
Short name T241
Test name
Test status
Simulation time 79425942610 ps
CPU time 366.09 seconds
Started Jul 15 07:13:12 PM PDT 24
Finished Jul 15 07:20:37 PM PDT 24
Peak memory 219300 kb
Host smart-d5f9a466-778e-4032-8941-1057e9698c41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509330244 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.509330244
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.1242930128
Short name T82
Test name
Test status
Simulation time 43050100 ps
CPU time 1.23 seconds
Started Jul 15 07:16:23 PM PDT 24
Finished Jul 15 07:17:12 PM PDT 24
Peak memory 220392 kb
Host smart-39e5362d-613c-43f6-adec-2e4084c1912d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242930128 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.1242930128
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.3323733035
Short name T444
Test name
Test status
Simulation time 98630932 ps
CPU time 1.08 seconds
Started Jul 15 07:16:25 PM PDT 24
Finished Jul 15 07:17:12 PM PDT 24
Peak memory 217716 kb
Host smart-7ccc9bff-5f56-4f74-80c4-a67aa4ac1d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323733035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.3323733035
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.2959776557
Short name T182
Test name
Test status
Simulation time 67728800 ps
CPU time 1.07 seconds
Started Jul 15 07:16:22 PM PDT 24
Finished Jul 15 07:17:12 PM PDT 24
Peak memory 218928 kb
Host smart-123b1554-10c7-4577-bcf1-cf6d6b0d5426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959776557 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.2959776557
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.1575404846
Short name T982
Test name
Test status
Simulation time 182770434 ps
CPU time 2.35 seconds
Started Jul 15 07:16:21 PM PDT 24
Finished Jul 15 07:17:09 PM PDT 24
Peak memory 220304 kb
Host smart-d12235c3-0c38-4210-825d-2660d231fb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575404846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1575404846
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.354267078
Short name T51
Test name
Test status
Simulation time 70119382 ps
CPU time 1.19 seconds
Started Jul 15 07:16:24 PM PDT 24
Finished Jul 15 07:17:12 PM PDT 24
Peak memory 220088 kb
Host smart-61ec6691-50da-4e58-8898-87ec27d7d7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354267078 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.354267078
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.1772711709
Short name T975
Test name
Test status
Simulation time 67354010 ps
CPU time 1.67 seconds
Started Jul 15 07:16:22 PM PDT 24
Finished Jul 15 07:17:13 PM PDT 24
Peak memory 219152 kb
Host smart-74f3beb8-f1fd-4819-aeb8-c0a7f52ad27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772711709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.1772711709
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.16515443
Short name T757
Test name
Test status
Simulation time 100559747 ps
CPU time 1.25 seconds
Started Jul 15 07:16:23 PM PDT 24
Finished Jul 15 07:17:12 PM PDT 24
Peak memory 215980 kb
Host smart-41b3d59b-ed63-4091-b5ac-51565501ee54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16515443 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.16515443
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.299458823
Short name T46
Test name
Test status
Simulation time 31563825 ps
CPU time 1.34 seconds
Started Jul 15 07:16:23 PM PDT 24
Finished Jul 15 07:17:12 PM PDT 24
Peak memory 217728 kb
Host smart-058515ca-df99-4726-a377-75abff585489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299458823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.299458823
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.1804761915
Short name T512
Test name
Test status
Simulation time 45887890 ps
CPU time 1.25 seconds
Started Jul 15 07:16:23 PM PDT 24
Finished Jul 15 07:17:12 PM PDT 24
Peak memory 219156 kb
Host smart-9f38ffb1-1628-4e07-819e-c22d73dfb8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804761915 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.1804761915
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.4245410141
Short name T487
Test name
Test status
Simulation time 96198680 ps
CPU time 1.04 seconds
Started Jul 15 07:16:22 PM PDT 24
Finished Jul 15 07:17:13 PM PDT 24
Peak memory 219624 kb
Host smart-962b0538-ed1f-4823-b244-c78f8a58b4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245410141 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.4245410141
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.2775313068
Short name T964
Test name
Test status
Simulation time 26316412 ps
CPU time 1.18 seconds
Started Jul 15 07:16:23 PM PDT 24
Finished Jul 15 07:17:12 PM PDT 24
Peak memory 218944 kb
Host smart-203742d0-67f7-47b4-9539-845165b4ee3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775313068 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.2775313068
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.1827830666
Short name T299
Test name
Test status
Simulation time 27921050 ps
CPU time 1.17 seconds
Started Jul 15 07:16:22 PM PDT 24
Finished Jul 15 07:17:13 PM PDT 24
Peak memory 217728 kb
Host smart-8a4864a9-abc3-4bdc-9fd7-4f5d282076b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827830666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.1827830666
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.1022826712
Short name T924
Test name
Test status
Simulation time 26396271 ps
CPU time 1.22 seconds
Started Jul 15 07:16:23 PM PDT 24
Finished Jul 15 07:17:12 PM PDT 24
Peak memory 221088 kb
Host smart-b178dafa-4341-44c4-9b84-4c8e56622b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022826712 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.1022826712
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.1284787102
Short name T423
Test name
Test status
Simulation time 126664048 ps
CPU time 0.94 seconds
Started Jul 15 07:16:21 PM PDT 24
Finished Jul 15 07:17:12 PM PDT 24
Peak memory 217724 kb
Host smart-9bacca3e-5660-454a-b99b-3fe623234df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284787102 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1284787102
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.3409305024
Short name T860
Test name
Test status
Simulation time 89109932 ps
CPU time 1.15 seconds
Started Jul 15 07:16:22 PM PDT 24
Finished Jul 15 07:17:13 PM PDT 24
Peak memory 220032 kb
Host smart-0c35e6fc-9b41-4c6a-9138-c51c235ea5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409305024 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.3409305024
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.3135903702
Short name T882
Test name
Test status
Simulation time 523761565 ps
CPU time 2.94 seconds
Started Jul 15 07:16:25 PM PDT 24
Finished Jul 15 07:17:14 PM PDT 24
Peak memory 217880 kb
Host smart-d1cc3c14-249c-4c3b-a0f6-353f172d1463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135903702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3135903702
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.1472436663
Short name T906
Test name
Test status
Simulation time 64698804 ps
CPU time 1.17 seconds
Started Jul 15 07:16:32 PM PDT 24
Finished Jul 15 07:17:23 PM PDT 24
Peak memory 216000 kb
Host smart-5bd15458-a422-4ca2-9a50-bad5ef63e939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472436663 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.1472436663
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.2977372343
Short name T349
Test name
Test status
Simulation time 41790189 ps
CPU time 1.28 seconds
Started Jul 15 07:16:31 PM PDT 24
Finished Jul 15 07:17:22 PM PDT 24
Peak memory 218760 kb
Host smart-ff0716b4-9bb8-4b37-8714-e6153693157e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977372343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.2977372343
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.1240487532
Short name T993
Test name
Test status
Simulation time 41455430 ps
CPU time 1.36 seconds
Started Jul 15 07:16:26 PM PDT 24
Finished Jul 15 07:17:13 PM PDT 24
Peak memory 217608 kb
Host smart-34069a90-37fc-4e8e-9c5a-891baa22991e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240487532 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1240487532
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.3318823668
Short name T227
Test name
Test status
Simulation time 47030222 ps
CPU time 1.09 seconds
Started Jul 15 07:13:16 PM PDT 24
Finished Jul 15 07:14:40 PM PDT 24
Peak memory 220160 kb
Host smart-1a78d4fb-6048-4a14-8eb7-bfad1f1b2027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318823668 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3318823668
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.307918088
Short name T743
Test name
Test status
Simulation time 41011099 ps
CPU time 1.07 seconds
Started Jul 15 07:13:16 PM PDT 24
Finished Jul 15 07:14:46 PM PDT 24
Peak memory 215308 kb
Host smart-e5d26001-037f-4738-9f68-88942cbcde4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307918088 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.307918088
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.813273493
Short name T618
Test name
Test status
Simulation time 18907205 ps
CPU time 0.86 seconds
Started Jul 15 07:13:20 PM PDT 24
Finished Jul 15 07:14:48 PM PDT 24
Peak memory 216524 kb
Host smart-5b525265-4e9a-4453-a4f0-f9c85395ed5c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813273493 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.813273493
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.4126866474
Short name T122
Test name
Test status
Simulation time 61950003 ps
CPU time 1.19 seconds
Started Jul 15 07:13:17 PM PDT 24
Finished Jul 15 07:14:47 PM PDT 24
Peak memory 217136 kb
Host smart-9913d716-50d4-484a-af2f-335ffb749fc8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126866474 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.4126866474
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.1034209846
Short name T148
Test name
Test status
Simulation time 34801699 ps
CPU time 0.92 seconds
Started Jul 15 07:13:22 PM PDT 24
Finished Jul 15 07:14:55 PM PDT 24
Peak memory 220120 kb
Host smart-d4422bc2-ede4-4c61-baaa-c69416034344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034209846 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.1034209846
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.89739019
Short name T575
Test name
Test status
Simulation time 157645283 ps
CPU time 2.09 seconds
Started Jul 15 07:13:20 PM PDT 24
Finished Jul 15 07:14:50 PM PDT 24
Peak memory 219752 kb
Host smart-9bf9b448-5a59-42aa-a1d4-843132d7e4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89739019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.89739019
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.2779655954
Short name T773
Test name
Test status
Simulation time 20844413 ps
CPU time 1.09 seconds
Started Jul 15 07:13:17 PM PDT 24
Finished Jul 15 07:14:47 PM PDT 24
Peak memory 215788 kb
Host smart-ff8d29aa-6f92-4bea-993a-ab19f53d63e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779655954 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2779655954
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.1820021741
Short name T876
Test name
Test status
Simulation time 19295635 ps
CPU time 1 seconds
Started Jul 15 07:13:15 PM PDT 24
Finished Jul 15 07:14:40 PM PDT 24
Peak memory 215628 kb
Host smart-3ae5240b-828f-4abe-835d-0f0e68219015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820021741 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.1820021741
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.2943687095
Short name T247
Test name
Test status
Simulation time 145795183 ps
CPU time 2.47 seconds
Started Jul 15 07:13:19 PM PDT 24
Finished Jul 15 07:14:50 PM PDT 24
Peak memory 215588 kb
Host smart-32c5c725-5f31-401a-b31e-7648ceff1afb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943687095 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.2943687095
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2244665752
Short name T703
Test name
Test status
Simulation time 97326950364 ps
CPU time 1213.75 seconds
Started Jul 15 07:13:20 PM PDT 24
Finished Jul 15 07:35:01 PM PDT 24
Peak memory 225656 kb
Host smart-c4e51ef4-0c01-401b-abb4-b2764fc1bd23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244665752 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.2244665752
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.700689007
Short name T648
Test name
Test status
Simulation time 77908593 ps
CPU time 1.18 seconds
Started Jul 15 07:16:31 PM PDT 24
Finished Jul 15 07:17:22 PM PDT 24
Peak memory 219044 kb
Host smart-7750446a-b9d6-4f60-86a5-e9374161f57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700689007 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.700689007
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.2369992261
Short name T316
Test name
Test status
Simulation time 83034200 ps
CPU time 2.69 seconds
Started Jul 15 07:16:27 PM PDT 24
Finished Jul 15 07:17:19 PM PDT 24
Peak memory 219208 kb
Host smart-60b3db01-d628-4d9c-ab72-4c6814f0b205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369992261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.2369992261
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.1335022856
Short name T87
Test name
Test status
Simulation time 24813668 ps
CPU time 1.16 seconds
Started Jul 15 07:16:28 PM PDT 24
Finished Jul 15 07:17:18 PM PDT 24
Peak memory 220080 kb
Host smart-47b89161-cc7e-407a-9d2f-fd4eb8ab672f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335022856 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.1335022856
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.3658380291
Short name T814
Test name
Test status
Simulation time 101993251 ps
CPU time 1.63 seconds
Started Jul 15 07:16:31 PM PDT 24
Finished Jul 15 07:17:23 PM PDT 24
Peak memory 220588 kb
Host smart-1fcaa632-d640-4e65-abc9-c80e49ec3822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658380291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.3658380291
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.758514246
Short name T504
Test name
Test status
Simulation time 344577496 ps
CPU time 4.37 seconds
Started Jul 15 07:16:27 PM PDT 24
Finished Jul 15 07:17:20 PM PDT 24
Peak memory 218080 kb
Host smart-ff6492c3-4530-4fe9-bd2a-54d3812ecb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758514246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.758514246
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.3262504960
Short name T891
Test name
Test status
Simulation time 191807451 ps
CPU time 1.04 seconds
Started Jul 15 07:16:26 PM PDT 24
Finished Jul 15 07:17:13 PM PDT 24
Peak memory 219132 kb
Host smart-44d104fe-c247-4f18-9235-948325028462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262504960 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.3262504960
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.44594323
Short name T585
Test name
Test status
Simulation time 128058448 ps
CPU time 1.33 seconds
Started Jul 15 07:16:27 PM PDT 24
Finished Jul 15 07:17:17 PM PDT 24
Peak memory 217640 kb
Host smart-f6d6074f-9f3b-4d48-be66-a1a25cc51839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44594323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.44594323
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.3841456210
Short name T561
Test name
Test status
Simulation time 63130551 ps
CPU time 1.17 seconds
Started Jul 15 07:16:30 PM PDT 24
Finished Jul 15 07:17:18 PM PDT 24
Peak memory 216008 kb
Host smart-ac6ae4f4-fa50-49cc-bf13-e67482bf28ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841456210 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.3841456210
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.1007049342
Short name T375
Test name
Test status
Simulation time 30219542 ps
CPU time 1.07 seconds
Started Jul 15 07:16:26 PM PDT 24
Finished Jul 15 07:17:13 PM PDT 24
Peak memory 217524 kb
Host smart-a0c779d5-477c-40dc-92f9-9cb64fb45791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007049342 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1007049342
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.366101866
Short name T621
Test name
Test status
Simulation time 23127899 ps
CPU time 1.16 seconds
Started Jul 15 07:16:27 PM PDT 24
Finished Jul 15 07:17:17 PM PDT 24
Peak memory 219000 kb
Host smart-64c88e2c-62fc-4561-af6d-d3dfaaa2c7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366101866 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.366101866
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.1997935753
Short name T870
Test name
Test status
Simulation time 32079196 ps
CPU time 1.21 seconds
Started Jul 15 07:16:32 PM PDT 24
Finished Jul 15 07:17:23 PM PDT 24
Peak memory 217500 kb
Host smart-9ccc7106-fe30-450c-b082-6a0474444264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997935753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1997935753
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.3731959850
Short name T931
Test name
Test status
Simulation time 80995812 ps
CPU time 2.78 seconds
Started Jul 15 07:16:31 PM PDT 24
Finished Jul 15 07:17:24 PM PDT 24
Peak memory 220544 kb
Host smart-770f37b6-bb43-4e0e-b89d-be4b4794f8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731959850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3731959850
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.3633846640
Short name T765
Test name
Test status
Simulation time 82431872 ps
CPU time 1.31 seconds
Started Jul 15 07:16:30 PM PDT 24
Finished Jul 15 07:17:18 PM PDT 24
Peak memory 215992 kb
Host smart-bc19d350-7735-4744-96d8-bbc2caa46d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633846640 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.3633846640
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.1839136751
Short name T22
Test name
Test status
Simulation time 121553435 ps
CPU time 2.19 seconds
Started Jul 15 07:16:26 PM PDT 24
Finished Jul 15 07:17:18 PM PDT 24
Peak memory 220240 kb
Host smart-7f57d6fc-b659-423f-9eb4-64793ef09a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839136751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1839136751
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.3339147130
Short name T979
Test name
Test status
Simulation time 104593739 ps
CPU time 1.25 seconds
Started Jul 15 07:16:39 PM PDT 24
Finished Jul 15 07:17:36 PM PDT 24
Peak memory 216036 kb
Host smart-f3c56d0c-6371-451e-9c8c-58c18f9a7319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339147130 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.3339147130
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.1203930797
Short name T952
Test name
Test status
Simulation time 36154540 ps
CPU time 1.17 seconds
Started Jul 15 07:16:40 PM PDT 24
Finished Jul 15 07:17:35 PM PDT 24
Peak memory 218972 kb
Host smart-5ffcc6d4-4235-4864-a466-8e8fae0a770f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203930797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1203930797
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.2161761341
Short name T295
Test name
Test status
Simulation time 70601026 ps
CPU time 1.07 seconds
Started Jul 15 07:13:17 PM PDT 24
Finished Jul 15 07:14:48 PM PDT 24
Peak memory 219128 kb
Host smart-61a39fb6-9d32-4e9d-9028-6c1890593319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161761341 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.2161761341
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.1081858529
Short name T78
Test name
Test status
Simulation time 59982714 ps
CPU time 0.95 seconds
Started Jul 15 07:13:20 PM PDT 24
Finished Jul 15 07:14:49 PM PDT 24
Peak memory 207064 kb
Host smart-c2bfe46a-3e23-4011-b964-162cfbb17ecf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081858529 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1081858529
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.1574640011
Short name T218
Test name
Test status
Simulation time 37781822 ps
CPU time 0.86 seconds
Started Jul 15 07:13:15 PM PDT 24
Finished Jul 15 07:14:39 PM PDT 24
Peak memory 216520 kb
Host smart-91e44720-e9d3-44b0-b84d-a1e42529ae57
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574640011 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.1574640011
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2307440595
Short name T606
Test name
Test status
Simulation time 51071995 ps
CPU time 1.06 seconds
Started Jul 15 07:13:18 PM PDT 24
Finished Jul 15 07:14:48 PM PDT 24
Peak memory 217056 kb
Host smart-3e9c6434-7be6-4283-baf7-9a5a4b645aad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307440595 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2307440595
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.3564454930
Short name T692
Test name
Test status
Simulation time 23041641 ps
CPU time 0.99 seconds
Started Jul 15 07:13:17 PM PDT 24
Finished Jul 15 07:14:47 PM PDT 24
Peak memory 219108 kb
Host smart-9d8b2eb4-dc47-4ebc-9e42-5dbaa981e098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564454930 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.3564454930
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_intr.2850117867
Short name T35
Test name
Test status
Simulation time 25545737 ps
CPU time 0.85 seconds
Started Jul 15 07:13:15 PM PDT 24
Finished Jul 15 07:14:39 PM PDT 24
Peak memory 216000 kb
Host smart-0655cba5-4457-4844-b69b-5e5619cd9556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850117867 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.2850117867
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.1438037012
Short name T858
Test name
Test status
Simulation time 28008674 ps
CPU time 0.97 seconds
Started Jul 15 07:13:21 PM PDT 24
Finished Jul 15 07:14:54 PM PDT 24
Peak memory 215548 kb
Host smart-6c755abd-8e2d-43ed-aae2-5ef9054add1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438037012 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1438037012
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.3167378750
Short name T900
Test name
Test status
Simulation time 206644961 ps
CPU time 2.45 seconds
Started Jul 15 07:13:19 PM PDT 24
Finished Jul 15 07:14:50 PM PDT 24
Peak memory 218748 kb
Host smart-028b44d0-c60f-4865-a5cc-7b2c0eabe130
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167378750 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.3167378750
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.457207069
Short name T932
Test name
Test status
Simulation time 41286624645 ps
CPU time 236.91 seconds
Started Jul 15 07:13:20 PM PDT 24
Finished Jul 15 07:18:49 PM PDT 24
Peak memory 220156 kb
Host smart-7aef97b8-869c-4856-9b9f-bf29e0b2b978
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457207069 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.457207069
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.2652219382
Short name T134
Test name
Test status
Simulation time 65478199 ps
CPU time 1.1 seconds
Started Jul 15 07:16:41 PM PDT 24
Finished Jul 15 07:17:35 PM PDT 24
Peak memory 220472 kb
Host smart-182d63af-2154-472f-a902-cbcde0c4d964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652219382 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.2652219382
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/161.edn_alert.752334809
Short name T111
Test name
Test status
Simulation time 26858694 ps
CPU time 1.26 seconds
Started Jul 15 07:16:40 PM PDT 24
Finished Jul 15 07:17:36 PM PDT 24
Peak memory 220172 kb
Host smart-1d020d51-19a2-4e25-ada8-e90ced6c7d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752334809 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.752334809
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.3363309777
Short name T862
Test name
Test status
Simulation time 53755283 ps
CPU time 1.35 seconds
Started Jul 15 07:16:40 PM PDT 24
Finished Jul 15 07:17:36 PM PDT 24
Peak memory 219188 kb
Host smart-782a5469-8feb-44da-adfc-3e5862b2cd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363309777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.3363309777
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.222208300
Short name T47
Test name
Test status
Simulation time 44999335 ps
CPU time 1.19 seconds
Started Jul 15 07:16:42 PM PDT 24
Finished Jul 15 07:17:38 PM PDT 24
Peak memory 218884 kb
Host smart-2ba01667-cdbd-4787-a9b5-f153e23fc24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222208300 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.222208300
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.980041950
Short name T599
Test name
Test status
Simulation time 33810184 ps
CPU time 1.33 seconds
Started Jul 15 07:16:40 PM PDT 24
Finished Jul 15 07:17:36 PM PDT 24
Peak memory 220224 kb
Host smart-c96eaf13-737e-41b2-acbb-af017abfa73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980041950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.980041950
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.3316599548
Short name T674
Test name
Test status
Simulation time 24961332 ps
CPU time 1.15 seconds
Started Jul 15 07:16:42 PM PDT 24
Finished Jul 15 07:17:38 PM PDT 24
Peak memory 218824 kb
Host smart-d9dbaf43-6566-46fe-b737-275054a29601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316599548 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.3316599548
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.2821592925
Short name T567
Test name
Test status
Simulation time 37722742 ps
CPU time 1.46 seconds
Started Jul 15 07:16:41 PM PDT 24
Finished Jul 15 07:17:36 PM PDT 24
Peak memory 217576 kb
Host smart-8366648b-41f9-4cbe-9ea9-591de291a30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821592925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.2821592925
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.3087589790
Short name T796
Test name
Test status
Simulation time 182024847 ps
CPU time 1.19 seconds
Started Jul 15 07:16:41 PM PDT 24
Finished Jul 15 07:17:35 PM PDT 24
Peak memory 218692 kb
Host smart-569686e3-e7bd-424e-8266-7c31e05a7d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087589790 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.3087589790
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.198933261
Short name T52
Test name
Test status
Simulation time 44087397 ps
CPU time 1.42 seconds
Started Jul 15 07:16:43 PM PDT 24
Finished Jul 15 07:17:39 PM PDT 24
Peak memory 218776 kb
Host smart-6e279782-f209-4f3b-a2d8-55856f6b5b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198933261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.198933261
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.2128247537
Short name T988
Test name
Test status
Simulation time 30009773 ps
CPU time 1.15 seconds
Started Jul 15 07:16:39 PM PDT 24
Finished Jul 15 07:17:35 PM PDT 24
Peak memory 220312 kb
Host smart-5d253017-0aa8-43ae-b0c3-54077e80a74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128247537 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.2128247537
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.1993234584
Short name T477
Test name
Test status
Simulation time 95589408 ps
CPU time 1.26 seconds
Started Jul 15 07:16:39 PM PDT 24
Finished Jul 15 07:17:36 PM PDT 24
Peak memory 219040 kb
Host smart-29b6fe9f-8cd8-4c4c-b882-8e30d0ac2a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993234584 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.1993234584
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.3473148852
Short name T151
Test name
Test status
Simulation time 96848933 ps
CPU time 1.22 seconds
Started Jul 15 07:16:41 PM PDT 24
Finished Jul 15 07:17:36 PM PDT 24
Peak memory 219064 kb
Host smart-76706a8e-cc38-44cf-95b1-2aca3256f70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473148852 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.3473148852
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.3590695320
Short name T571
Test name
Test status
Simulation time 81154483 ps
CPU time 1.12 seconds
Started Jul 15 07:16:42 PM PDT 24
Finished Jul 15 07:17:38 PM PDT 24
Peak memory 217732 kb
Host smart-ee247bd2-8388-46dc-ad4d-0e25cc9b4ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590695320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.3590695320
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.2066222735
Short name T494
Test name
Test status
Simulation time 158865974 ps
CPU time 1.07 seconds
Started Jul 15 07:16:42 PM PDT 24
Finished Jul 15 07:17:38 PM PDT 24
Peak memory 219052 kb
Host smart-3ed840c5-1b0e-4d2f-8d9e-55213490e91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066222735 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.2066222735
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.3460668401
Short name T507
Test name
Test status
Simulation time 36485188 ps
CPU time 1.4 seconds
Started Jul 15 07:16:40 PM PDT 24
Finished Jul 15 07:17:36 PM PDT 24
Peak memory 217724 kb
Host smart-7a2c707a-8c31-476f-afba-b268aea01108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460668401 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.3460668401
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.3005955879
Short name T600
Test name
Test status
Simulation time 81348669 ps
CPU time 1.25 seconds
Started Jul 15 07:16:39 PM PDT 24
Finished Jul 15 07:17:35 PM PDT 24
Peak memory 219164 kb
Host smart-529ac69c-f61f-4c1f-b987-93e3bcf7e71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005955879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.3005955879
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.1041825350
Short name T762
Test name
Test status
Simulation time 26744234 ps
CPU time 1.19 seconds
Started Jul 15 07:16:39 PM PDT 24
Finished Jul 15 07:17:35 PM PDT 24
Peak memory 221140 kb
Host smart-61059c77-100c-4e4d-8ad0-5d0a7500106a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041825350 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.1041825350
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.3817366206
Short name T597
Test name
Test status
Simulation time 38967202 ps
CPU time 1.39 seconds
Started Jul 15 07:16:43 PM PDT 24
Finished Jul 15 07:17:39 PM PDT 24
Peak memory 218968 kb
Host smart-6085a21b-48ad-4fe4-988a-25e2ec5830af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817366206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.3817366206
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert_test.260446724
Short name T640
Test name
Test status
Simulation time 56596200 ps
CPU time 0.95 seconds
Started Jul 15 07:13:26 PM PDT 24
Finished Jul 15 07:15:02 PM PDT 24
Peak memory 207024 kb
Host smart-f13d93fe-9e57-4643-b087-8aaa2a3df3c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260446724 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.260446724
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.1713589742
Short name T974
Test name
Test status
Simulation time 37716050 ps
CPU time 1.29 seconds
Started Jul 15 07:13:24 PM PDT 24
Finished Jul 15 07:14:56 PM PDT 24
Peak memory 217092 kb
Host smart-711457c5-e85d-4c11-a7a2-da0ae60099b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713589742 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.1713589742
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_genbits.297605297
Short name T338
Test name
Test status
Simulation time 114749778 ps
CPU time 1.31 seconds
Started Jul 15 07:13:20 PM PDT 24
Finished Jul 15 07:14:49 PM PDT 24
Peak memory 218804 kb
Host smart-d4c42993-aa02-4739-9479-190be9a79e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297605297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.297605297
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3054529535
Short name T806
Test name
Test status
Simulation time 35623311 ps
CPU time 0.88 seconds
Started Jul 15 07:13:15 PM PDT 24
Finished Jul 15 07:14:39 PM PDT 24
Peak memory 215980 kb
Host smart-b27dae8d-5aa7-4f76-8953-d203f5039bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054529535 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3054529535
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.699511598
Short name T678
Test name
Test status
Simulation time 23301957 ps
CPU time 0.93 seconds
Started Jul 15 07:13:14 PM PDT 24
Finished Jul 15 07:14:39 PM PDT 24
Peak memory 215552 kb
Host smart-85fa09ee-e7fd-4e5f-9b97-7cdf458dc0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699511598 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.699511598
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.4199389639
Short name T800
Test name
Test status
Simulation time 217663126 ps
CPU time 2.46 seconds
Started Jul 15 07:13:17 PM PDT 24
Finished Jul 15 07:14:48 PM PDT 24
Peak memory 217492 kb
Host smart-904499b6-8911-4284-bb34-a6943444682a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199389639 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.4199389639
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.1739157708
Short name T967
Test name
Test status
Simulation time 9326605123 ps
CPU time 200.5 seconds
Started Jul 15 07:13:24 PM PDT 24
Finished Jul 15 07:18:15 PM PDT 24
Peak memory 222400 kb
Host smart-5a6167b4-f6b1-4fd7-970a-46010a58c972
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739157708 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.1739157708
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.1257927399
Short name T961
Test name
Test status
Simulation time 29137100 ps
CPU time 1.22 seconds
Started Jul 15 07:16:43 PM PDT 24
Finished Jul 15 07:17:38 PM PDT 24
Peak memory 220224 kb
Host smart-06ba8867-785c-4bef-997a-6eff7b8c58fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257927399 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.1257927399
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.1770244610
Short name T335
Test name
Test status
Simulation time 36831616 ps
CPU time 1.26 seconds
Started Jul 15 07:16:42 PM PDT 24
Finished Jul 15 07:17:38 PM PDT 24
Peak memory 219236 kb
Host smart-18478a38-3cd8-4229-b292-50ee51f67265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770244610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1770244610
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.992220079
Short name T275
Test name
Test status
Simulation time 104105349 ps
CPU time 1.33 seconds
Started Jul 15 07:16:41 PM PDT 24
Finished Jul 15 07:17:36 PM PDT 24
Peak memory 220080 kb
Host smart-431e565d-9534-4ddf-853a-924c38582cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992220079 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.992220079
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.3145180898
Short name T332
Test name
Test status
Simulation time 44798723 ps
CPU time 1.52 seconds
Started Jul 15 07:16:39 PM PDT 24
Finished Jul 15 07:17:36 PM PDT 24
Peak memory 218692 kb
Host smart-b19746e4-c031-48bb-bdd2-841b8e7baa89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145180898 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.3145180898
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.1124450154
Short name T579
Test name
Test status
Simulation time 25149397 ps
CPU time 1.2 seconds
Started Jul 15 07:16:38 PM PDT 24
Finished Jul 15 07:17:35 PM PDT 24
Peak memory 220880 kb
Host smart-4399610a-aa5f-440c-9567-dc57a1590549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124450154 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.1124450154
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.1988286780
Short name T72
Test name
Test status
Simulation time 36542223 ps
CPU time 1.36 seconds
Started Jul 15 07:16:41 PM PDT 24
Finished Jul 15 07:17:36 PM PDT 24
Peak memory 218728 kb
Host smart-10eae531-58cf-4674-9c2b-b4e5b2265401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988286780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.1988286780
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.4274467938
Short name T384
Test name
Test status
Simulation time 46491985 ps
CPU time 1.51 seconds
Started Jul 15 07:16:41 PM PDT 24
Finished Jul 15 07:17:36 PM PDT 24
Peak memory 217536 kb
Host smart-2f62476a-33c2-4278-9e21-1823597fa511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274467938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.4274467938
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.268232606
Short name T816
Test name
Test status
Simulation time 92572314 ps
CPU time 1.23 seconds
Started Jul 15 07:16:41 PM PDT 24
Finished Jul 15 07:17:38 PM PDT 24
Peak memory 219052 kb
Host smart-72054f3a-5bf9-4f18-aa42-da3a20d8ab8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268232606 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.268232606
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.172092687
Short name T448
Test name
Test status
Simulation time 41839939 ps
CPU time 1.38 seconds
Started Jul 15 07:16:40 PM PDT 24
Finished Jul 15 07:17:36 PM PDT 24
Peak memory 220352 kb
Host smart-9950dadf-f3a8-40e9-a7ea-a2a36b4eabfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172092687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.172092687
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.2447678686
Short name T956
Test name
Test status
Simulation time 39536524 ps
CPU time 1.15 seconds
Started Jul 15 07:16:42 PM PDT 24
Finished Jul 15 07:17:38 PM PDT 24
Peak memory 219980 kb
Host smart-fb4c2557-b455-456a-b25f-db06bdc4a8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447678686 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.2447678686
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/176.edn_alert.1643511624
Short name T854
Test name
Test status
Simulation time 28392613 ps
CPU time 1.2 seconds
Started Jul 15 07:16:43 PM PDT 24
Finished Jul 15 07:17:38 PM PDT 24
Peak memory 220252 kb
Host smart-7a493b94-254e-4f59-aec7-e7b7cd123924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643511624 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.1643511624
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.3274532944
Short name T496
Test name
Test status
Simulation time 30540480 ps
CPU time 1.25 seconds
Started Jul 15 07:16:40 PM PDT 24
Finished Jul 15 07:17:36 PM PDT 24
Peak memory 218724 kb
Host smart-fb46b690-96c2-4246-9d3e-dc0ffcf702cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274532944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.3274532944
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.1014426270
Short name T66
Test name
Test status
Simulation time 104983278 ps
CPU time 1.3 seconds
Started Jul 15 07:16:46 PM PDT 24
Finished Jul 15 07:17:47 PM PDT 24
Peak memory 220120 kb
Host smart-b39d4cc6-d714-448d-996c-1a51b23bf9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014426270 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.1014426270
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.243012351
Short name T594
Test name
Test status
Simulation time 66368714 ps
CPU time 1.21 seconds
Started Jul 15 07:16:43 PM PDT 24
Finished Jul 15 07:17:38 PM PDT 24
Peak memory 218752 kb
Host smart-0d4f708d-3763-4e63-a614-0d2ab6ae3cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243012351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.243012351
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.3743521711
Short name T343
Test name
Test status
Simulation time 28276317 ps
CPU time 1.17 seconds
Started Jul 15 07:16:45 PM PDT 24
Finished Jul 15 07:17:45 PM PDT 24
Peak memory 220116 kb
Host smart-3234d6b8-f31e-4af8-8178-f0d000aa2e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743521711 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.3743521711
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.1800980749
Short name T331
Test name
Test status
Simulation time 51365747 ps
CPU time 1.19 seconds
Started Jul 15 07:16:44 PM PDT 24
Finished Jul 15 07:17:44 PM PDT 24
Peak memory 220236 kb
Host smart-d7289614-7a3b-4b08-a6e6-636a27a2d059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800980749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1800980749
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.3343985545
Short name T121
Test name
Test status
Simulation time 127149705 ps
CPU time 1.23 seconds
Started Jul 15 07:16:43 PM PDT 24
Finished Jul 15 07:17:39 PM PDT 24
Peak memory 216000 kb
Host smart-0288add8-cd73-43fc-a740-1733a124cfcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343985545 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.3343985545
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.385862363
Short name T559
Test name
Test status
Simulation time 59256956 ps
CPU time 1.29 seconds
Started Jul 15 07:16:42 PM PDT 24
Finished Jul 15 07:17:38 PM PDT 24
Peak memory 217580 kb
Host smart-679b9dee-f94a-409e-9720-e605cb459911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385862363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.385862363
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.3883320625
Short name T856
Test name
Test status
Simulation time 43495445 ps
CPU time 1.16 seconds
Started Jul 15 07:13:26 PM PDT 24
Finished Jul 15 07:15:03 PM PDT 24
Peak memory 219796 kb
Host smart-cbf73ced-e0d9-42ec-b1b3-62998c939d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883320625 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.3883320625
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.1927821152
Short name T968
Test name
Test status
Simulation time 25615752 ps
CPU time 0.86 seconds
Started Jul 15 07:13:25 PM PDT 24
Finished Jul 15 07:15:00 PM PDT 24
Peak memory 207048 kb
Host smart-4f152813-0b14-4d9d-8d82-a56fb6ac8d82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927821152 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.1927821152
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.892219503
Short name T164
Test name
Test status
Simulation time 124221770 ps
CPU time 0.8 seconds
Started Jul 15 07:13:26 PM PDT 24
Finished Jul 15 07:15:02 PM PDT 24
Peak memory 216520 kb
Host smart-3572e47a-c76a-4e67-8e65-b718248a1d1e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892219503 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.892219503
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.9215657
Short name T719
Test name
Test status
Simulation time 68547226 ps
CPU time 1.22 seconds
Started Jul 15 07:13:24 PM PDT 24
Finished Jul 15 07:14:56 PM PDT 24
Peak memory 217092 kb
Host smart-4300246b-7e95-48f3-8b75-90cb558dd4c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9215657 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disab
le_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disa
ble_auto_req_mode.9215657
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.2577415467
Short name T128
Test name
Test status
Simulation time 26003125 ps
CPU time 1 seconds
Started Jul 15 07:13:24 PM PDT 24
Finished Jul 15 07:14:55 PM PDT 24
Peak memory 219836 kb
Host smart-d4638e11-c044-4024-84b5-fbc66b140df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577415467 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.2577415467
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.1975759264
Short name T818
Test name
Test status
Simulation time 139956628 ps
CPU time 3.35 seconds
Started Jul 15 07:13:26 PM PDT 24
Finished Jul 15 07:15:05 PM PDT 24
Peak memory 217876 kb
Host smart-afd3ef93-287f-4c13-b9ba-55c696f5582f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975759264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1975759264
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.1631876041
Short name T71
Test name
Test status
Simulation time 32528841 ps
CPU time 0.88 seconds
Started Jul 15 07:13:25 PM PDT 24
Finished Jul 15 07:15:00 PM PDT 24
Peak memory 215716 kb
Host smart-6f4dfad8-0b71-492f-a7cb-7dc4bae80d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631876041 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1631876041
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.331684848
Short name T407
Test name
Test status
Simulation time 17548551 ps
CPU time 1.04 seconds
Started Jul 15 07:13:23 PM PDT 24
Finished Jul 15 07:14:55 PM PDT 24
Peak memory 215484 kb
Host smart-3c69b8d6-c841-4ae8-b540-095763c24b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331684848 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.331684848
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.801868382
Short name T682
Test name
Test status
Simulation time 290023148 ps
CPU time 1.82 seconds
Started Jul 15 07:13:23 PM PDT 24
Finished Jul 15 07:14:56 PM PDT 24
Peak memory 215524 kb
Host smart-a8eedd58-42bb-45ec-945e-f4a62a3cd28f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801868382 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.801868382
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.3065775300
Short name T67
Test name
Test status
Simulation time 89448564546 ps
CPU time 660.5 seconds
Started Jul 15 07:13:26 PM PDT 24
Finished Jul 15 07:26:02 PM PDT 24
Peak memory 221208 kb
Host smart-4c117922-ae25-4b0f-bc47-70a5dc19c26d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065775300 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.3065775300
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.4200042376
Short name T501
Test name
Test status
Simulation time 76854157 ps
CPU time 1.07 seconds
Started Jul 15 07:16:44 PM PDT 24
Finished Jul 15 07:17:39 PM PDT 24
Peak memory 218840 kb
Host smart-a78fb346-37a5-4b27-956a-758aace78452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200042376 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.4200042376
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.3904840328
Short name T445
Test name
Test status
Simulation time 52213241 ps
CPU time 1.44 seconds
Started Jul 15 07:16:43 PM PDT 24
Finished Jul 15 07:17:39 PM PDT 24
Peak memory 218588 kb
Host smart-61040a89-8ed9-476b-bc8e-2c34f14aad2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904840328 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.3904840328
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.1865093371
Short name T565
Test name
Test status
Simulation time 107155338 ps
CPU time 1.32 seconds
Started Jul 15 07:16:46 PM PDT 24
Finished Jul 15 07:17:47 PM PDT 24
Peak memory 220824 kb
Host smart-be0d573f-93b8-42ff-aa56-327252977414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865093371 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.1865093371
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.3531006087
Short name T457
Test name
Test status
Simulation time 57967134 ps
CPU time 1.92 seconds
Started Jul 15 07:16:43 PM PDT 24
Finished Jul 15 07:17:39 PM PDT 24
Peak memory 218892 kb
Host smart-b1fd1fe3-4646-4b43-af1c-af1d0904cb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531006087 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3531006087
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.2383233359
Short name T835
Test name
Test status
Simulation time 21233187 ps
CPU time 1.11 seconds
Started Jul 15 07:16:46 PM PDT 24
Finished Jul 15 07:17:46 PM PDT 24
Peak memory 218804 kb
Host smart-5ddda8a2-6b7e-439f-9687-c494fb0fb980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383233359 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.2383233359
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.3246149188
Short name T985
Test name
Test status
Simulation time 31582166 ps
CPU time 1.28 seconds
Started Jul 15 07:16:46 PM PDT 24
Finished Jul 15 07:17:47 PM PDT 24
Peak memory 218812 kb
Host smart-ce717494-d7dd-4d62-b103-79ae55bb03de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246149188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.3246149188
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.2276253767
Short name T290
Test name
Test status
Simulation time 104431472 ps
CPU time 1.33 seconds
Started Jul 15 07:16:46 PM PDT 24
Finished Jul 15 07:17:47 PM PDT 24
Peak memory 219992 kb
Host smart-543b93bc-a96d-42be-bd6e-585d37501e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276253767 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.2276253767
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.1088282646
Short name T399
Test name
Test status
Simulation time 91274390 ps
CPU time 1.29 seconds
Started Jul 15 07:16:46 PM PDT 24
Finished Jul 15 07:17:46 PM PDT 24
Peak memory 217784 kb
Host smart-2723437b-2155-4bf6-9921-375bcfc4682b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088282646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.1088282646
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.733783243
Short name T108
Test name
Test status
Simulation time 40682821 ps
CPU time 1.26 seconds
Started Jul 15 07:16:46 PM PDT 24
Finished Jul 15 07:17:47 PM PDT 24
Peak memory 215972 kb
Host smart-d17af1b2-1c17-434f-8df8-425055603f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733783243 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.733783243
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.2093910990
Short name T282
Test name
Test status
Simulation time 48578013 ps
CPU time 1.35 seconds
Started Jul 15 07:16:50 PM PDT 24
Finished Jul 15 07:17:58 PM PDT 24
Peak memory 218952 kb
Host smart-fa14570f-c2dd-4a6d-9266-50b6bcae09eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093910990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.2093910990
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.1704379465
Short name T252
Test name
Test status
Simulation time 32632189 ps
CPU time 1.28 seconds
Started Jul 15 07:16:46 PM PDT 24
Finished Jul 15 07:17:47 PM PDT 24
Peak memory 216052 kb
Host smart-68b3826d-c498-4df4-8d93-3c6f69d69c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704379465 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.1704379465
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.1411747689
Short name T913
Test name
Test status
Simulation time 64715547 ps
CPU time 1.25 seconds
Started Jul 15 07:16:46 PM PDT 24
Finished Jul 15 07:17:46 PM PDT 24
Peak memory 217488 kb
Host smart-12a69444-d95a-4c2a-93aa-0eea12d65aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411747689 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.1411747689
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.3060541753
Short name T230
Test name
Test status
Simulation time 26745537 ps
CPU time 1.18 seconds
Started Jul 15 07:16:50 PM PDT 24
Finished Jul 15 07:17:58 PM PDT 24
Peak memory 219344 kb
Host smart-ebbdf725-c4f3-4c78-941c-1dd94bd29605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060541753 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.3060541753
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.1276005635
Short name T789
Test name
Test status
Simulation time 58578794 ps
CPU time 1.22 seconds
Started Jul 15 07:16:50 PM PDT 24
Finished Jul 15 07:17:58 PM PDT 24
Peak memory 219224 kb
Host smart-2fb836df-70ac-4e36-85d4-8b9aef72514b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276005635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.1276005635
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.1476908714
Short name T885
Test name
Test status
Simulation time 249758709 ps
CPU time 1.16 seconds
Started Jul 15 07:16:49 PM PDT 24
Finished Jul 15 07:17:57 PM PDT 24
Peak memory 216036 kb
Host smart-04a8ba2f-99db-48eb-a203-62b867e867e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476908714 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.1476908714
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/188.edn_alert.2445000159
Short name T852
Test name
Test status
Simulation time 25458658 ps
CPU time 1.24 seconds
Started Jul 15 07:16:49 PM PDT 24
Finished Jul 15 07:17:58 PM PDT 24
Peak memory 219540 kb
Host smart-c77340aa-7270-4287-97d7-b50ee6a17ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445000159 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.2445000159
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.995554374
Short name T377
Test name
Test status
Simulation time 74718357 ps
CPU time 1.09 seconds
Started Jul 15 07:16:49 PM PDT 24
Finished Jul 15 07:17:57 PM PDT 24
Peak memory 217424 kb
Host smart-a79f1f13-8d53-4124-9b59-e4f781b011e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995554374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.995554374
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.3811399879
Short name T591
Test name
Test status
Simulation time 43122726 ps
CPU time 1.19 seconds
Started Jul 15 07:16:51 PM PDT 24
Finished Jul 15 07:18:01 PM PDT 24
Peak memory 221240 kb
Host smart-3e6caa80-8eb5-440f-a838-56585c318196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811399879 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.3811399879
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.2719814636
Short name T509
Test name
Test status
Simulation time 50720547 ps
CPU time 1.51 seconds
Started Jul 15 07:16:49 PM PDT 24
Finished Jul 15 07:17:58 PM PDT 24
Peak memory 218716 kb
Host smart-28abace3-358b-4918-a2ec-8a1f145936c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719814636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.2719814636
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.546353874
Short name T228
Test name
Test status
Simulation time 29397410 ps
CPU time 1.22 seconds
Started Jul 15 07:13:26 PM PDT 24
Finished Jul 15 07:15:03 PM PDT 24
Peak memory 220196 kb
Host smart-1a4535e8-c69d-4ed4-920b-6f12367e0d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546353874 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.546353874
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.3460985560
Short name T456
Test name
Test status
Simulation time 45290786 ps
CPU time 0.85 seconds
Started Jul 15 07:13:38 PM PDT 24
Finished Jul 15 07:15:20 PM PDT 24
Peak memory 207016 kb
Host smart-d5316440-c6d4-4132-9451-f53c6f7d2385
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460985560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3460985560
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.29642756
Short name T510
Test name
Test status
Simulation time 83887423 ps
CPU time 0.93 seconds
Started Jul 15 07:13:27 PM PDT 24
Finished Jul 15 07:15:03 PM PDT 24
Peak memory 218500 kb
Host smart-9648585f-a786-4422-96ad-f8d52b5cb452
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29642756 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_dis
able_auto_req_mode.29642756
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.3727833239
Short name T165
Test name
Test status
Simulation time 23674082 ps
CPU time 1.06 seconds
Started Jul 15 07:13:25 PM PDT 24
Finished Jul 15 07:15:00 PM PDT 24
Peak memory 224280 kb
Host smart-6c63dd56-082e-4acd-b080-3817bea60fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727833239 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.3727833239
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.3932098391
Short name T540
Test name
Test status
Simulation time 128158525 ps
CPU time 1.97 seconds
Started Jul 15 07:13:26 PM PDT 24
Finished Jul 15 07:15:03 PM PDT 24
Peak memory 220472 kb
Host smart-2e187005-eb90-49d2-9629-8a9b3af87f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932098391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3932098391
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.2156311792
Short name T973
Test name
Test status
Simulation time 63441731 ps
CPU time 0.94 seconds
Started Jul 15 07:13:24 PM PDT 24
Finished Jul 15 07:14:55 PM PDT 24
Peak memory 224132 kb
Host smart-0b07f35c-324b-4a6e-98f7-a83116cf5ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156311792 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.2156311792
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.1087541453
Short name T701
Test name
Test status
Simulation time 22799408 ps
CPU time 0.98 seconds
Started Jul 15 07:13:24 PM PDT 24
Finished Jul 15 07:14:55 PM PDT 24
Peak memory 215608 kb
Host smart-a639b37f-c448-4c5e-8e9b-15fa0773fac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087541453 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.1087541453
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.1043417713
Short name T202
Test name
Test status
Simulation time 541556382 ps
CPU time 4.39 seconds
Started Jul 15 07:13:24 PM PDT 24
Finished Jul 15 07:14:57 PM PDT 24
Peak memory 217452 kb
Host smart-c5f8a4b5-8f2d-4840-9c4d-38c13e28be69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043417713 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.1043417713
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.3784225235
Short name T243
Test name
Test status
Simulation time 248409467030 ps
CPU time 1528.58 seconds
Started Jul 15 07:13:24 PM PDT 24
Finished Jul 15 07:40:23 PM PDT 24
Peak memory 224544 kb
Host smart-f7d9a817-4ba1-492c-81f2-6579ea8321dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784225235 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.3784225235
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.1722350671
Short name T152
Test name
Test status
Simulation time 25457083 ps
CPU time 1.15 seconds
Started Jul 15 07:16:54 PM PDT 24
Finished Jul 15 07:18:10 PM PDT 24
Peak memory 220948 kb
Host smart-f1c5cfc1-4423-48f1-8490-99d0c39345e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722350671 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.1722350671
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.1177085414
Short name T634
Test name
Test status
Simulation time 50326956 ps
CPU time 1.5 seconds
Started Jul 15 07:16:54 PM PDT 24
Finished Jul 15 07:18:10 PM PDT 24
Peak memory 218828 kb
Host smart-020c5413-62c0-4780-ba91-0b5ddc1417ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177085414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.1177085414
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.1420114283
Short name T756
Test name
Test status
Simulation time 212188860 ps
CPU time 1.23 seconds
Started Jul 15 07:16:50 PM PDT 24
Finished Jul 15 07:17:58 PM PDT 24
Peak memory 218804 kb
Host smart-b7b25db9-f560-448a-becc-b80189d55def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420114283 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.1420114283
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/192.edn_alert.51118094
Short name T233
Test name
Test status
Simulation time 48181197 ps
CPU time 1.2 seconds
Started Jul 15 07:16:59 PM PDT 24
Finished Jul 15 07:18:16 PM PDT 24
Peak memory 220620 kb
Host smart-c9312bba-74cc-444a-af79-8ce0c8d3a5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51118094 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.51118094
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.233596236
Short name T322
Test name
Test status
Simulation time 44680553 ps
CPU time 1.08 seconds
Started Jul 15 07:16:51 PM PDT 24
Finished Jul 15 07:18:01 PM PDT 24
Peak memory 217556 kb
Host smart-136bd54f-420c-4ce8-b3e3-f9008684a335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233596236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.233596236
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.3758899728
Short name T370
Test name
Test status
Simulation time 78529243 ps
CPU time 1.1 seconds
Started Jul 15 07:16:59 PM PDT 24
Finished Jul 15 07:18:16 PM PDT 24
Peak memory 220200 kb
Host smart-827b271e-c7ea-4377-89ab-368814f9fbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758899728 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3758899728
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.534074288
Short name T857
Test name
Test status
Simulation time 61494252 ps
CPU time 1.27 seconds
Started Jul 15 07:16:50 PM PDT 24
Finished Jul 15 07:17:58 PM PDT 24
Peak memory 220648 kb
Host smart-eb44d628-b8f5-4b19-bee9-e59ba6648af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534074288 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.534074288
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.3056986849
Short name T284
Test name
Test status
Simulation time 119848115 ps
CPU time 1.79 seconds
Started Jul 15 07:16:47 PM PDT 24
Finished Jul 15 07:17:56 PM PDT 24
Peak memory 218876 kb
Host smart-0fd2bea1-94d2-427d-85a5-8f1ef311be86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056986849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3056986849
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.1858822475
Short name T702
Test name
Test status
Simulation time 45733097 ps
CPU time 1.2 seconds
Started Jul 15 07:16:52 PM PDT 24
Finished Jul 15 07:18:02 PM PDT 24
Peak memory 218996 kb
Host smart-c76daf66-dc5a-482e-a99c-887ee288fac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858822475 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.1858822475
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.3816127981
Short name T770
Test name
Test status
Simulation time 25418278 ps
CPU time 1.24 seconds
Started Jul 15 07:16:54 PM PDT 24
Finished Jul 15 07:18:10 PM PDT 24
Peak memory 217488 kb
Host smart-b27ae81d-0274-4270-a808-8ca0ee6cdff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816127981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3816127981
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.3184757061
Short name T549
Test name
Test status
Simulation time 99216637 ps
CPU time 1.27 seconds
Started Jul 15 07:16:52 PM PDT 24
Finished Jul 15 07:18:02 PM PDT 24
Peak memory 220424 kb
Host smart-fa33ad01-ed78-42ec-8302-2db2a4d81add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184757061 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.3184757061
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.3562484865
Short name T439
Test name
Test status
Simulation time 42640943 ps
CPU time 1.2 seconds
Started Jul 15 07:16:50 PM PDT 24
Finished Jul 15 07:17:58 PM PDT 24
Peak memory 215748 kb
Host smart-143d2e88-ce78-4031-9656-5c977d412c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562484865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3562484865
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.2621772206
Short name T643
Test name
Test status
Simulation time 28699611 ps
CPU time 1.07 seconds
Started Jul 15 07:16:50 PM PDT 24
Finished Jul 15 07:17:57 PM PDT 24
Peak memory 220208 kb
Host smart-db8aa905-c0ef-4632-86bf-6aaecc48f541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621772206 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.2621772206
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/198.edn_alert.682417648
Short name T460
Test name
Test status
Simulation time 26713185 ps
CPU time 1.27 seconds
Started Jul 15 07:16:55 PM PDT 24
Finished Jul 15 07:18:11 PM PDT 24
Peak memory 220128 kb
Host smart-7f1fd604-e5d4-4093-9145-a299bf289ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682417648 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.682417648
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.1965135773
Short name T21
Test name
Test status
Simulation time 44020623 ps
CPU time 1.6 seconds
Started Jul 15 07:16:49 PM PDT 24
Finished Jul 15 07:17:58 PM PDT 24
Peak memory 220372 kb
Host smart-f0438d14-c6de-474d-b047-146b3e24e224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965135773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.1965135773
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.1120411312
Short name T292
Test name
Test status
Simulation time 111827680 ps
CPU time 1.11 seconds
Started Jul 15 07:16:47 PM PDT 24
Finished Jul 15 07:17:55 PM PDT 24
Peak memory 220068 kb
Host smart-afad1538-544d-4b3a-bd2e-afae764b5e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120411312 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.1120411312
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.3830673600
Short name T861
Test name
Test status
Simulation time 52888569 ps
CPU time 1.85 seconds
Started Jul 15 07:16:53 PM PDT 24
Finished Jul 15 07:18:04 PM PDT 24
Peak memory 218860 kb
Host smart-b6974ada-108a-48cd-83c0-3bfdf7def546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830673600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.3830673600
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.4048671143
Short name T713
Test name
Test status
Simulation time 26673223 ps
CPU time 1.2 seconds
Started Jul 15 07:12:58 PM PDT 24
Finished Jul 15 07:14:00 PM PDT 24
Peak memory 218856 kb
Host smart-c409cb39-654a-4b0b-80b2-4761cfb74784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048671143 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.4048671143
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.4122576184
Short name T675
Test name
Test status
Simulation time 16689501 ps
CPU time 0.95 seconds
Started Jul 15 07:13:02 PM PDT 24
Finished Jul 15 07:14:15 PM PDT 24
Peak memory 207060 kb
Host smart-e00d0521-5f15-49df-a8c2-709db0fa4ebb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122576184 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.4122576184
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.2469712858
Short name T747
Test name
Test status
Simulation time 20837610 ps
CPU time 0.85 seconds
Started Jul 15 07:12:57 PM PDT 24
Finished Jul 15 07:13:53 PM PDT 24
Peak memory 215712 kb
Host smart-72a5eb0e-36d4-49e2-916a-8f122db0e1d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469712858 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2469712858
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.2154406046
Short name T667
Test name
Test status
Simulation time 47863558 ps
CPU time 1.03 seconds
Started Jul 15 07:13:02 PM PDT 24
Finished Jul 15 07:14:16 PM PDT 24
Peak memory 219992 kb
Host smart-11d191f4-49e3-4d8a-b393-2b7e5798dff6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154406046 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.2154406046
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.941850128
Short name T216
Test name
Test status
Simulation time 28599958 ps
CPU time 1.21 seconds
Started Jul 15 07:12:59 PM PDT 24
Finished Jul 15 07:14:00 PM PDT 24
Peak memory 215772 kb
Host smart-2c2c977f-5d1e-4117-9976-aa72ad0cb5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941850128 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.941850128
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.3647646288
Short name T877
Test name
Test status
Simulation time 82497595 ps
CPU time 1.1 seconds
Started Jul 15 07:12:53 PM PDT 24
Finished Jul 15 07:13:44 PM PDT 24
Peak memory 217624 kb
Host smart-e58d59ad-4e0e-4b63-a81e-5e16c9b8f674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647646288 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3647646288
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.3069062355
Short name T614
Test name
Test status
Simulation time 22419037 ps
CPU time 1.2 seconds
Started Jul 15 07:13:00 PM PDT 24
Finished Jul 15 07:14:08 PM PDT 24
Peak memory 224336 kb
Host smart-40b597e3-933a-465a-8264-3f17b9cde3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069062355 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.3069062355
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.3513569560
Short name T936
Test name
Test status
Simulation time 42944554 ps
CPU time 0.93 seconds
Started Jul 15 07:13:02 PM PDT 24
Finished Jul 15 07:14:16 PM PDT 24
Peak memory 207436 kb
Host smart-f2cb558d-9674-47de-bf07-66b51f7ff0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513569560 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3513569560
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.3231458197
Short name T64
Test name
Test status
Simulation time 2962616276 ps
CPU time 8.14 seconds
Started Jul 15 07:13:06 PM PDT 24
Finished Jul 15 07:14:32 PM PDT 24
Peak memory 237276 kb
Host smart-c461aed5-bcea-48b4-9c4b-8bfe28b54184
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231458197 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.3231458197
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.1815523755
Short name T804
Test name
Test status
Simulation time 25335808 ps
CPU time 0.96 seconds
Started Jul 15 07:13:06 PM PDT 24
Finished Jul 15 07:14:25 PM PDT 24
Peak memory 215604 kb
Host smart-5a3528b9-aacc-4f7b-bee8-c146bfe1eefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815523755 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.1815523755
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.1648852305
Short name T408
Test name
Test status
Simulation time 119894008 ps
CPU time 1.75 seconds
Started Jul 15 07:13:02 PM PDT 24
Finished Jul 15 07:14:17 PM PDT 24
Peak memory 215612 kb
Host smart-8b1d56a0-deb1-41a0-809b-4e6755a67aec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648852305 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.1648852305
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1964563222
Short name T79
Test name
Test status
Simulation time 50663219893 ps
CPU time 569.42 seconds
Started Jul 15 07:12:53 PM PDT 24
Finished Jul 15 07:23:12 PM PDT 24
Peak memory 224092 kb
Host smart-8b6b6b04-200f-474f-8ff0-8abf63be7b03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964563222 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1964563222
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.3648817801
Short name T706
Test name
Test status
Simulation time 77688934 ps
CPU time 1.09 seconds
Started Jul 15 07:13:36 PM PDT 24
Finished Jul 15 07:15:12 PM PDT 24
Peak memory 218868 kb
Host smart-8f4edd82-ff01-4e36-96e8-93001a9a4208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648817801 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.3648817801
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.3231052702
Short name T583
Test name
Test status
Simulation time 34052435 ps
CPU time 1.2 seconds
Started Jul 15 07:13:33 PM PDT 24
Finished Jul 15 07:15:11 PM PDT 24
Peak memory 215272 kb
Host smart-f94ba6b7-df7e-4532-b379-6684ba89fed4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231052702 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.3231052702
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.3949794829
Short name T175
Test name
Test status
Simulation time 11126927 ps
CPU time 0.85 seconds
Started Jul 15 07:13:38 PM PDT 24
Finished Jul 15 07:15:20 PM PDT 24
Peak memory 216620 kb
Host smart-01dbe8b1-6f31-43b1-832b-0de206cb76c7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949794829 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3949794829
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.608861866
Short name T450
Test name
Test status
Simulation time 72494590 ps
CPU time 0.97 seconds
Started Jul 15 07:13:37 PM PDT 24
Finished Jul 15 07:15:17 PM PDT 24
Peak memory 217064 kb
Host smart-39230b9f-c0fa-4a61-827b-fd13e5045370
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608861866 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_di
sable_auto_req_mode.608861866
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.500621912
Short name T921
Test name
Test status
Simulation time 19677429 ps
CPU time 0.96 seconds
Started Jul 15 07:13:37 PM PDT 24
Finished Jul 15 07:15:18 PM PDT 24
Peak memory 218644 kb
Host smart-4f2bfe16-fec1-4c7c-bb64-1da8da3eeb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500621912 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.500621912
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.1469398082
Short name T694
Test name
Test status
Simulation time 116538872 ps
CPU time 1.63 seconds
Started Jul 15 07:13:33 PM PDT 24
Finished Jul 15 07:15:12 PM PDT 24
Peak memory 219256 kb
Host smart-b230e88a-92b5-4270-b480-9fe3ec7accd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469398082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1469398082
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.2904454146
Short name T645
Test name
Test status
Simulation time 21012623 ps
CPU time 1.03 seconds
Started Jul 15 07:13:34 PM PDT 24
Finished Jul 15 07:15:12 PM PDT 24
Peak memory 215668 kb
Host smart-02faf1c2-30cf-4ad1-b47d-4d2363faaa24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904454146 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.2904454146
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.3145192204
Short name T799
Test name
Test status
Simulation time 25778159 ps
CPU time 0.92 seconds
Started Jul 15 07:13:38 PM PDT 24
Finished Jul 15 07:15:20 PM PDT 24
Peak memory 215624 kb
Host smart-3b1342aa-4383-427c-bd5c-675994cdaec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145192204 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.3145192204
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.2898672060
Short name T307
Test name
Test status
Simulation time 123499464 ps
CPU time 1.88 seconds
Started Jul 15 07:13:37 PM PDT 24
Finished Jul 15 07:15:19 PM PDT 24
Peak memory 218980 kb
Host smart-634fb2ec-11f9-46f7-95a2-a969c2dd8e6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898672060 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2898672060
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.436926620
Short name T887
Test name
Test status
Simulation time 42972328672 ps
CPU time 1076.6 seconds
Started Jul 15 07:13:39 PM PDT 24
Finished Jul 15 07:33:16 PM PDT 24
Peak memory 224100 kb
Host smart-efa23939-7427-492e-921e-41ca0507c4fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436926620 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.436926620
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.1068104567
Short name T298
Test name
Test status
Simulation time 48982860 ps
CPU time 1.59 seconds
Started Jul 15 07:16:51 PM PDT 24
Finished Jul 15 07:18:02 PM PDT 24
Peak memory 218624 kb
Host smart-3c088cd7-3219-4072-8055-3188c0c6a004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068104567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.1068104567
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.224427646
Short name T406
Test name
Test status
Simulation time 44757021 ps
CPU time 1.2 seconds
Started Jul 15 07:16:53 PM PDT 24
Finished Jul 15 07:18:03 PM PDT 24
Peak memory 218824 kb
Host smart-24b9168c-615b-4988-9fe3-b88a743147b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224427646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.224427646
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.1830013213
Short name T631
Test name
Test status
Simulation time 39906900 ps
CPU time 1.27 seconds
Started Jul 15 07:16:52 PM PDT 24
Finished Jul 15 07:18:03 PM PDT 24
Peak memory 219684 kb
Host smart-e580da56-7ad9-4a6f-8215-cf0c4ab1fef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830013213 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.1830013213
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.1162378959
Short name T937
Test name
Test status
Simulation time 79413131 ps
CPU time 1.03 seconds
Started Jul 15 07:16:51 PM PDT 24
Finished Jul 15 07:18:01 PM PDT 24
Peak memory 217624 kb
Host smart-0c29a092-72f6-4fb7-a572-4c759b6f9969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162378959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.1162378959
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.3348644032
Short name T323
Test name
Test status
Simulation time 80195199 ps
CPU time 1.07 seconds
Started Jul 15 07:16:49 PM PDT 24
Finished Jul 15 07:17:56 PM PDT 24
Peak memory 217604 kb
Host smart-a28f79c5-58f1-47dd-89bc-42507ba580cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348644032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3348644032
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3611518032
Short name T736
Test name
Test status
Simulation time 45677465 ps
CPU time 1.25 seconds
Started Jul 15 07:16:50 PM PDT 24
Finished Jul 15 07:17:58 PM PDT 24
Peak memory 218820 kb
Host smart-89ea4aa0-feb4-4a1f-897d-55a4267a57e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611518032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3611518032
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2233451611
Short name T369
Test name
Test status
Simulation time 162534952 ps
CPU time 1.19 seconds
Started Jul 15 07:16:59 PM PDT 24
Finished Jul 15 07:18:17 PM PDT 24
Peak memory 217564 kb
Host smart-32185be1-1971-4b44-925e-d27af29b4180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233451611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2233451611
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.2063996027
Short name T826
Test name
Test status
Simulation time 51202832 ps
CPU time 1.44 seconds
Started Jul 15 07:16:53 PM PDT 24
Finished Jul 15 07:18:04 PM PDT 24
Peak memory 218756 kb
Host smart-0126c8da-9bb0-4764-a648-673f975af899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063996027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.2063996027
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.4123711001
Short name T312
Test name
Test status
Simulation time 40969952 ps
CPU time 1.42 seconds
Started Jul 15 07:16:51 PM PDT 24
Finished Jul 15 07:18:01 PM PDT 24
Peak memory 220300 kb
Host smart-b483c958-0217-4e30-aadc-c9130964df02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123711001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.4123711001
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.1116148532
Short name T912
Test name
Test status
Simulation time 174051827 ps
CPU time 2.48 seconds
Started Jul 15 07:16:59 PM PDT 24
Finished Jul 15 07:18:18 PM PDT 24
Peak memory 219024 kb
Host smart-83be8fe8-ac96-4568-b43b-128d3c20cec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116148532 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.1116148532
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.2662101305
Short name T404
Test name
Test status
Simulation time 55980322 ps
CPU time 1.22 seconds
Started Jul 15 07:13:37 PM PDT 24
Finished Jul 15 07:15:18 PM PDT 24
Peak memory 221292 kb
Host smart-73604df3-ff79-48d3-9129-441f6df06d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662101305 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.2662101305
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.363677780
Short name T74
Test name
Test status
Simulation time 14743479 ps
CPU time 0.88 seconds
Started Jul 15 07:13:38 PM PDT 24
Finished Jul 15 07:15:20 PM PDT 24
Peak memory 205588 kb
Host smart-605ffd11-a6fe-4c14-bc09-ecec5f92478f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363677780 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.363677780
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.1734054359
Short name T162
Test name
Test status
Simulation time 13848640 ps
CPU time 0.9 seconds
Started Jul 15 07:13:37 PM PDT 24
Finished Jul 15 07:15:18 PM PDT 24
Peak memory 215856 kb
Host smart-56517e1b-9ac0-4509-ab62-4e79609df52b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734054359 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1734054359
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.3855500338
Short name T69
Test name
Test status
Simulation time 28056290 ps
CPU time 1.1 seconds
Started Jul 15 07:13:38 PM PDT 24
Finished Jul 15 07:15:20 PM PDT 24
Peak memory 217372 kb
Host smart-53576d0f-9eb8-4086-8f91-14a7b16c134a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855500338 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.3855500338
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.377966575
Short name T646
Test name
Test status
Simulation time 56050706 ps
CPU time 1.04 seconds
Started Jul 15 07:13:39 PM PDT 24
Finished Jul 15 07:15:20 PM PDT 24
Peak memory 224116 kb
Host smart-1dcffb8e-3b36-43e2-9211-e9e2e80d5229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377966575 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.377966575
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_intr.4209273415
Short name T32
Test name
Test status
Simulation time 46269063 ps
CPU time 0.8 seconds
Started Jul 15 07:13:34 PM PDT 24
Finished Jul 15 07:15:12 PM PDT 24
Peak memory 215784 kb
Host smart-364cb096-6fb1-4f74-b8b2-c8ea64dfdc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209273415 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.4209273415
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.856870540
Short name T359
Test name
Test status
Simulation time 23005244 ps
CPU time 0.89 seconds
Started Jul 15 07:13:36 PM PDT 24
Finished Jul 15 07:15:17 PM PDT 24
Peak memory 215532 kb
Host smart-66de0a93-b525-4c29-988e-724b6323938e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856870540 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.856870540
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.1479554199
Short name T535
Test name
Test status
Simulation time 859721220 ps
CPU time 5.07 seconds
Started Jul 15 07:13:38 PM PDT 24
Finished Jul 15 07:15:24 PM PDT 24
Peak memory 215604 kb
Host smart-4db52d72-5d05-4df4-a1b2-f37da5141548
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479554199 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.1479554199
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.3824764298
Short name T436
Test name
Test status
Simulation time 197817625115 ps
CPU time 749.51 seconds
Started Jul 15 07:13:35 PM PDT 24
Finished Jul 15 07:27:41 PM PDT 24
Peak memory 221564 kb
Host smart-9ff6ce38-1b8e-4cc1-a2e2-c233a1a41148
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824764298 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.3824764298
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.2926981140
Short name T324
Test name
Test status
Simulation time 95635279 ps
CPU time 1.69 seconds
Started Jul 15 07:16:55 PM PDT 24
Finished Jul 15 07:18:12 PM PDT 24
Peak memory 218912 kb
Host smart-54317d18-09a0-438e-8283-f12672b6fb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926981140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.2926981140
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.1182963712
Short name T14
Test name
Test status
Simulation time 136183141 ps
CPU time 1.39 seconds
Started Jul 15 07:16:51 PM PDT 24
Finished Jul 15 07:18:02 PM PDT 24
Peak memory 220556 kb
Host smart-c30f2351-8fd7-48bb-a802-5290994d9bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182963712 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.1182963712
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.1874275692
Short name T940
Test name
Test status
Simulation time 68604212 ps
CPU time 1.56 seconds
Started Jul 15 07:16:51 PM PDT 24
Finished Jul 15 07:18:02 PM PDT 24
Peak memory 218940 kb
Host smart-5cac8950-9537-48ec-a529-5d186606ba80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874275692 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.1874275692
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.744553109
Short name T73
Test name
Test status
Simulation time 722154324 ps
CPU time 4.49 seconds
Started Jul 15 07:16:50 PM PDT 24
Finished Jul 15 07:18:01 PM PDT 24
Peak memory 219736 kb
Host smart-30b20c01-e65d-4f90-a4ad-3a1835a81598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744553109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.744553109
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.2304821376
Short name T619
Test name
Test status
Simulation time 50808142 ps
CPU time 1.88 seconds
Started Jul 15 07:16:53 PM PDT 24
Finished Jul 15 07:18:04 PM PDT 24
Peak memory 217512 kb
Host smart-8e8f09f4-ff93-4314-9859-1c8205d47821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304821376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.2304821376
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.3148637592
Short name T989
Test name
Test status
Simulation time 26542005 ps
CPU time 1.22 seconds
Started Jul 15 07:16:51 PM PDT 24
Finished Jul 15 07:18:02 PM PDT 24
Peak memory 218828 kb
Host smart-05f02958-ce62-4df5-a6fb-9ba3ad5a8715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148637592 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.3148637592
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.2114190982
Short name T700
Test name
Test status
Simulation time 62008681 ps
CPU time 1.42 seconds
Started Jul 15 07:16:54 PM PDT 24
Finished Jul 15 07:18:10 PM PDT 24
Peak memory 219236 kb
Host smart-3bb49cb6-175b-46e0-ad6e-4ec4875b9281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114190982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2114190982
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.1350608093
Short name T320
Test name
Test status
Simulation time 229557926 ps
CPU time 2.92 seconds
Started Jul 15 07:16:59 PM PDT 24
Finished Jul 15 07:18:18 PM PDT 24
Peak memory 219980 kb
Host smart-9e6fb886-fd6e-4d9a-8083-4510869d454e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350608093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.1350608093
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.3975439522
Short name T490
Test name
Test status
Simulation time 57971811 ps
CPU time 1.2 seconds
Started Jul 15 07:17:01 PM PDT 24
Finished Jul 15 07:18:24 PM PDT 24
Peak memory 217812 kb
Host smart-1e3ba3be-d4f0-4145-9ede-8424a74790ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975439522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.3975439522
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.1542728380
Short name T904
Test name
Test status
Simulation time 28256279 ps
CPU time 1.22 seconds
Started Jul 15 07:13:33 PM PDT 24
Finished Jul 15 07:15:11 PM PDT 24
Peak memory 215936 kb
Host smart-dc24dcd2-ead9-4a92-9719-734beca7f97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542728380 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.1542728380
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.1017493048
Short name T946
Test name
Test status
Simulation time 17178606 ps
CPU time 0.94 seconds
Started Jul 15 07:13:34 PM PDT 24
Finished Jul 15 07:15:11 PM PDT 24
Peak memory 207028 kb
Host smart-cf7cd592-282d-4ccb-890f-ed7b72104518
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017493048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1017493048
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.2248251785
Short name T143
Test name
Test status
Simulation time 32095079 ps
CPU time 1.13 seconds
Started Jul 15 07:13:38 PM PDT 24
Finished Jul 15 07:15:20 PM PDT 24
Peak memory 219756 kb
Host smart-d56bb91b-a930-4c7e-bd77-de55ab651aaa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248251785 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.2248251785
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.3831863671
Short name T824
Test name
Test status
Simulation time 32989350 ps
CPU time 0.9 seconds
Started Jul 15 07:13:37 PM PDT 24
Finished Jul 15 07:15:18 PM PDT 24
Peak memory 219816 kb
Host smart-20978e82-5d04-4a08-be8c-bc37edc19c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831863671 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.3831863671
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.948101074
Short name T329
Test name
Test status
Simulation time 150885686 ps
CPU time 1.36 seconds
Started Jul 15 07:13:38 PM PDT 24
Finished Jul 15 07:15:20 PM PDT 24
Peak memory 219184 kb
Host smart-e05c2dbf-f5eb-458a-a7b7-5aa4452c376a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948101074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.948101074
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.3704623469
Short name T31
Test name
Test status
Simulation time 57849299 ps
CPU time 0.79 seconds
Started Jul 15 07:13:38 PM PDT 24
Finished Jul 15 07:15:20 PM PDT 24
Peak memory 214280 kb
Host smart-0e6e7033-a0b0-4806-b446-483a923a3519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704623469 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.3704623469
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.2046189079
Short name T744
Test name
Test status
Simulation time 22434954 ps
CPU time 0.92 seconds
Started Jul 15 07:13:34 PM PDT 24
Finished Jul 15 07:15:12 PM PDT 24
Peak memory 215624 kb
Host smart-af5760cd-f5a0-42df-9db2-5067d52f40f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046189079 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2046189079
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2017395922
Short name T6
Test name
Test status
Simulation time 721038259 ps
CPU time 6.48 seconds
Started Jul 15 07:13:33 PM PDT 24
Finished Jul 15 07:15:16 PM PDT 24
Peak memory 219528 kb
Host smart-77662f2d-2c1d-40cf-a6d2-757486e6289f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017395922 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2017395922
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3020162581
Short name T480
Test name
Test status
Simulation time 17351914586 ps
CPU time 448.05 seconds
Started Jul 15 07:13:34 PM PDT 24
Finished Jul 15 07:22:38 PM PDT 24
Peak memory 217660 kb
Host smart-c4806414-ca3f-43b5-8f64-7e8789a45aca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020162581 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3020162581
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.2524080499
Short name T650
Test name
Test status
Simulation time 56898334 ps
CPU time 1.33 seconds
Started Jul 15 07:17:01 PM PDT 24
Finished Jul 15 07:18:24 PM PDT 24
Peak memory 218848 kb
Host smart-cb45c17b-ff6c-4d31-8e2f-01416491edaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524080499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.2524080499
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.1914417725
Short name T595
Test name
Test status
Simulation time 182294847 ps
CPU time 0.93 seconds
Started Jul 15 07:16:57 PM PDT 24
Finished Jul 15 07:18:15 PM PDT 24
Peak memory 217728 kb
Host smart-5f48f3fc-2682-49ae-9b21-a6cf63cb42ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914417725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1914417725
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.406828440
Short name T415
Test name
Test status
Simulation time 37865032 ps
CPU time 1.03 seconds
Started Jul 15 07:16:57 PM PDT 24
Finished Jul 15 07:18:15 PM PDT 24
Peak memory 220172 kb
Host smart-6fbf456f-cd11-4c72-b578-c2da787d8fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406828440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.406828440
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.1307738894
Short name T536
Test name
Test status
Simulation time 98492987 ps
CPU time 1.34 seconds
Started Jul 15 07:16:55 PM PDT 24
Finished Jul 15 07:18:11 PM PDT 24
Peak memory 219272 kb
Host smart-4fd847e7-1d6b-4e8c-940f-cfdd9cb097b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307738894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.1307738894
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.3995849342
Short name T951
Test name
Test status
Simulation time 51955487 ps
CPU time 1.54 seconds
Started Jul 15 07:17:01 PM PDT 24
Finished Jul 15 07:18:24 PM PDT 24
Peak memory 217616 kb
Host smart-dc24348e-6373-4fae-85c5-1c27babe2fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995849342 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.3995849342
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.2899665658
Short name T930
Test name
Test status
Simulation time 56096387 ps
CPU time 1.23 seconds
Started Jul 15 07:16:59 PM PDT 24
Finished Jul 15 07:18:16 PM PDT 24
Peak memory 218852 kb
Host smart-45c34fcc-f2e4-4c8a-8dd3-b2ea7f0066a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899665658 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.2899665658
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.42040896
Short name T23
Test name
Test status
Simulation time 76820318 ps
CPU time 2.48 seconds
Started Jul 15 07:17:00 PM PDT 24
Finished Jul 15 07:18:25 PM PDT 24
Peak memory 220176 kb
Host smart-b15cb228-fa52-4a22-8249-462fcb8aa00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42040896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.42040896
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.2203166283
Short name T50
Test name
Test status
Simulation time 61875651 ps
CPU time 1.41 seconds
Started Jul 15 07:17:00 PM PDT 24
Finished Jul 15 07:18:24 PM PDT 24
Peak memory 218844 kb
Host smart-d64cba32-dd61-4dee-8f17-52cc8e1f2209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203166283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.2203166283
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.592924057
Short name T537
Test name
Test status
Simulation time 79896919 ps
CPU time 1.21 seconds
Started Jul 15 07:16:55 PM PDT 24
Finished Jul 15 07:18:11 PM PDT 24
Peak memory 217704 kb
Host smart-a4522e02-207c-4aab-9e17-04381a44f39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592924057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.592924057
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.2477035139
Short name T662
Test name
Test status
Simulation time 74882934 ps
CPU time 2.48 seconds
Started Jul 15 07:16:56 PM PDT 24
Finished Jul 15 07:18:13 PM PDT 24
Peak memory 220280 kb
Host smart-020a4a75-8a30-43e2-b306-13b1a2b249fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477035139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.2477035139
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.2790796176
Short name T136
Test name
Test status
Simulation time 123744532 ps
CPU time 1.11 seconds
Started Jul 15 07:13:37 PM PDT 24
Finished Jul 15 07:15:18 PM PDT 24
Peak memory 218852 kb
Host smart-5644bf5d-c510-4ee3-8ff4-c3f457b2caf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790796176 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.2790796176
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.1789350523
Short name T748
Test name
Test status
Simulation time 20625335 ps
CPU time 0.91 seconds
Started Jul 15 07:13:37 PM PDT 24
Finished Jul 15 07:15:18 PM PDT 24
Peak memory 207020 kb
Host smart-d6dab462-2b04-42e8-857a-ed706a0d07bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789350523 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.1789350523
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.1412493387
Short name T651
Test name
Test status
Simulation time 11367399 ps
CPU time 0.85 seconds
Started Jul 15 07:13:35 PM PDT 24
Finished Jul 15 07:15:12 PM PDT 24
Peak memory 216380 kb
Host smart-01e356d2-54d6-4a00-b4bd-33ad896df079
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412493387 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.1412493387
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.2053007252
Short name T251
Test name
Test status
Simulation time 47798740 ps
CPU time 1.36 seconds
Started Jul 15 07:13:39 PM PDT 24
Finished Jul 15 07:15:20 PM PDT 24
Peak memory 219472 kb
Host smart-6dfe01c9-7686-4780-89c6-27dba6155bdd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053007252 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.2053007252
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.4088296377
Short name T475
Test name
Test status
Simulation time 27025505 ps
CPU time 0.85 seconds
Started Jul 15 07:13:35 PM PDT 24
Finished Jul 15 07:15:12 PM PDT 24
Peak memory 218512 kb
Host smart-18354515-b7db-4ba4-b425-cc981254f4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088296377 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.4088296377
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.2856557345
Short name T905
Test name
Test status
Simulation time 37962601 ps
CPU time 1.64 seconds
Started Jul 15 07:13:33 PM PDT 24
Finished Jul 15 07:15:12 PM PDT 24
Peak memory 218896 kb
Host smart-6283350d-21d7-4296-8137-e30db4c0f04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856557345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.2856557345
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.2416927666
Short name T533
Test name
Test status
Simulation time 27554330 ps
CPU time 0.94 seconds
Started Jul 15 07:13:38 PM PDT 24
Finished Jul 15 07:15:20 PM PDT 24
Peak memory 215928 kb
Host smart-f37b76ba-1941-4cf8-b0c7-ad26e80d70a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416927666 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.2416927666
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.2925760851
Short name T239
Test name
Test status
Simulation time 24862587 ps
CPU time 0.91 seconds
Started Jul 15 07:13:36 PM PDT 24
Finished Jul 15 07:15:12 PM PDT 24
Peak memory 215640 kb
Host smart-9c01e6a8-136a-492a-988f-f348b43aba2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925760851 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.2925760851
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.3889824285
Short name T689
Test name
Test status
Simulation time 877631981 ps
CPU time 4.85 seconds
Started Jul 15 07:13:33 PM PDT 24
Finished Jul 15 07:15:15 PM PDT 24
Peak memory 215596 kb
Host smart-2f972010-7400-4d2f-b1cc-9dc621fd1557
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889824285 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3889824285
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.41967167
Short name T412
Test name
Test status
Simulation time 43218479612 ps
CPU time 867.04 seconds
Started Jul 15 07:13:39 PM PDT 24
Finished Jul 15 07:29:46 PM PDT 24
Peak memory 218500 kb
Host smart-771c34ac-06a0-4f4b-b580-870414f1db17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41967167 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.41967167
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.4070311383
Short name T334
Test name
Test status
Simulation time 54113451 ps
CPU time 1.7 seconds
Started Jul 15 07:16:59 PM PDT 24
Finished Jul 15 07:18:17 PM PDT 24
Peak memory 217764 kb
Host smart-a6a6195e-2517-4d1c-82cc-450c979b9a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070311383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.4070311383
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.3047720659
Short name T283
Test name
Test status
Simulation time 2186182733 ps
CPU time 71.94 seconds
Started Jul 15 07:16:55 PM PDT 24
Finished Jul 15 07:19:22 PM PDT 24
Peak memory 220692 kb
Host smart-4192200e-ac7c-4a16-b27a-ac093d265408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047720659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3047720659
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.2698139386
Short name T899
Test name
Test status
Simulation time 37626944 ps
CPU time 1.37 seconds
Started Jul 15 07:17:01 PM PDT 24
Finished Jul 15 07:18:24 PM PDT 24
Peak memory 215620 kb
Host smart-00aea899-b899-4923-8ebe-82ce9a797084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698139386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.2698139386
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.944090135
Short name T303
Test name
Test status
Simulation time 150688160 ps
CPU time 2.78 seconds
Started Jul 15 07:17:00 PM PDT 24
Finished Jul 15 07:18:18 PM PDT 24
Peak memory 218880 kb
Host smart-a31572d8-53a9-47ab-8980-b6f8bb7ee532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944090135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.944090135
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.1815448468
Short name T622
Test name
Test status
Simulation time 53092420 ps
CPU time 1.67 seconds
Started Jul 15 07:17:00 PM PDT 24
Finished Jul 15 07:18:24 PM PDT 24
Peak memory 218984 kb
Host smart-d77e4c29-9481-4172-aa56-98972e5fdda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815448468 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.1815448468
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.3274873419
Short name T310
Test name
Test status
Simulation time 45844437 ps
CPU time 1.82 seconds
Started Jul 15 07:16:56 PM PDT 24
Finished Jul 15 07:18:12 PM PDT 24
Peak memory 218692 kb
Host smart-9bfb7c1f-29f2-43bb-a269-a99536a07973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274873419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.3274873419
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.1667468432
Short name T563
Test name
Test status
Simulation time 79094641 ps
CPU time 1.13 seconds
Started Jul 15 07:17:00 PM PDT 24
Finished Jul 15 07:18:17 PM PDT 24
Peak memory 217628 kb
Host smart-4e34178d-3316-4cd0-8e2a-096be690ad0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667468432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.1667468432
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.2210308988
Short name T498
Test name
Test status
Simulation time 28429467 ps
CPU time 1.27 seconds
Started Jul 15 07:16:55 PM PDT 24
Finished Jul 15 07:18:11 PM PDT 24
Peak memory 218860 kb
Host smart-14822146-e528-4902-982f-af88db2a0588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210308988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.2210308988
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.606485420
Short name T782
Test name
Test status
Simulation time 29906343 ps
CPU time 1.08 seconds
Started Jul 15 07:16:59 PM PDT 24
Finished Jul 15 07:18:17 PM PDT 24
Peak memory 219316 kb
Host smart-22a173f9-07f4-4607-bdb9-038c3549e053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606485420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.606485420
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.3287503294
Short name T642
Test name
Test status
Simulation time 48239923 ps
CPU time 1.1 seconds
Started Jul 15 07:16:56 PM PDT 24
Finished Jul 15 07:18:12 PM PDT 24
Peak memory 217592 kb
Host smart-4d8337b3-e14c-4c05-b4f5-ec7fc4519a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287503294 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.3287503294
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.1410585074
Short name T109
Test name
Test status
Simulation time 76180353 ps
CPU time 1.1 seconds
Started Jul 15 07:13:38 PM PDT 24
Finished Jul 15 07:15:20 PM PDT 24
Peak memory 221080 kb
Host smart-2e8ec178-fc53-4abc-bef8-2c9341ead114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410585074 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.1410585074
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.3360246873
Short name T587
Test name
Test status
Simulation time 65478342 ps
CPU time 0.94 seconds
Started Jul 15 07:13:41 PM PDT 24
Finished Jul 15 07:15:21 PM PDT 24
Peak memory 207156 kb
Host smart-4e856ea5-4fc6-42eb-aa11-5911196b917a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360246873 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.3360246873
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.2836205784
Short name T584
Test name
Test status
Simulation time 59339884 ps
CPU time 0.86 seconds
Started Jul 15 07:13:41 PM PDT 24
Finished Jul 15 07:15:21 PM PDT 24
Peak memory 216552 kb
Host smart-f3c42c94-f754-4f93-b4ae-aff6e4ced995
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836205784 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.2836205784
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.823075482
Short name T749
Test name
Test status
Simulation time 79962481 ps
CPU time 1.25 seconds
Started Jul 15 07:13:46 PM PDT 24
Finished Jul 15 07:15:29 PM PDT 24
Peak memory 217328 kb
Host smart-42fc899d-5edb-4e62-bdca-b1b5e639c780
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823075482 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_di
sable_auto_req_mode.823075482
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.2190420479
Short name T58
Test name
Test status
Simulation time 22749562 ps
CPU time 1.18 seconds
Started Jul 15 07:13:45 PM PDT 24
Finished Jul 15 07:15:28 PM PDT 24
Peak memory 229980 kb
Host smart-5c506f99-bc5c-4d73-8e17-a387b0ee1b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190420479 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.2190420479
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.1739598273
Short name T666
Test name
Test status
Simulation time 52646572 ps
CPU time 1.39 seconds
Started Jul 15 07:13:35 PM PDT 24
Finished Jul 15 07:15:13 PM PDT 24
Peak memory 219048 kb
Host smart-aafb3cb9-3288-4f3f-8b9d-1eb2aff2b677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739598273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1739598273
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.2434607385
Short name T866
Test name
Test status
Simulation time 22098692 ps
CPU time 1.09 seconds
Started Jul 15 07:13:37 PM PDT 24
Finished Jul 15 07:15:17 PM PDT 24
Peak memory 216164 kb
Host smart-26d22fc5-6e42-4f25-9934-cb2a44af48c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434607385 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.2434607385
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.2137295122
Short name T541
Test name
Test status
Simulation time 15792282 ps
CPU time 0.97 seconds
Started Jul 15 07:13:34 PM PDT 24
Finished Jul 15 07:15:11 PM PDT 24
Peak memory 215620 kb
Host smart-2954f054-7ec1-437e-883a-a1a61dc36bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137295122 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.2137295122
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.1180858443
Short name T514
Test name
Test status
Simulation time 73251594 ps
CPU time 1.95 seconds
Started Jul 15 07:13:38 PM PDT 24
Finished Jul 15 07:15:21 PM PDT 24
Peak memory 215620 kb
Host smart-9d0cfd75-638f-4a88-82ee-f627a0a67e6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180858443 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.1180858443
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.623313735
Short name T237
Test name
Test status
Simulation time 144391711926 ps
CPU time 1076.64 seconds
Started Jul 15 07:13:37 PM PDT 24
Finished Jul 15 07:33:14 PM PDT 24
Peak memory 223988 kb
Host smart-86349208-3a2f-44eb-9ba7-1ac45c200bdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623313735 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.623313735
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.3903681896
Short name T797
Test name
Test status
Simulation time 137705911 ps
CPU time 1.08 seconds
Started Jul 15 07:17:03 PM PDT 24
Finished Jul 15 07:18:23 PM PDT 24
Peak memory 217544 kb
Host smart-2bad29db-a008-4fa5-a979-b17ed4530fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903681896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.3903681896
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.1608615756
Short name T722
Test name
Test status
Simulation time 65169562 ps
CPU time 1.32 seconds
Started Jul 15 07:16:56 PM PDT 24
Finished Jul 15 07:18:12 PM PDT 24
Peak memory 220404 kb
Host smart-fca1522b-20f7-4bbe-947a-8bd47a67bf27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608615756 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1608615756
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.3670798915
Short name T410
Test name
Test status
Simulation time 43890304 ps
CPU time 1.39 seconds
Started Jul 15 07:16:57 PM PDT 24
Finished Jul 15 07:18:12 PM PDT 24
Peak memory 218788 kb
Host smart-e4ad3156-c311-4400-a9a6-d51dee9b113b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670798915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.3670798915
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.2831937596
Short name T780
Test name
Test status
Simulation time 111371275 ps
CPU time 1.61 seconds
Started Jul 15 07:16:58 PM PDT 24
Finished Jul 15 07:18:16 PM PDT 24
Peak memory 217980 kb
Host smart-bc60027f-5ef6-497a-bb80-2a22e0cc5bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831937596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.2831937596
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.1538458724
Short name T653
Test name
Test status
Simulation time 29322495 ps
CPU time 1.22 seconds
Started Jul 15 07:16:58 PM PDT 24
Finished Jul 15 07:18:16 PM PDT 24
Peak memory 217564 kb
Host smart-85c296f3-0844-4490-95fe-bc7d2ca41147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538458724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.1538458724
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.3611349194
Short name T848
Test name
Test status
Simulation time 283931009 ps
CPU time 2.91 seconds
Started Jul 15 07:17:00 PM PDT 24
Finished Jul 15 07:18:19 PM PDT 24
Peak memory 220184 kb
Host smart-f9a75c31-419d-4909-be45-4ea79e4233b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611349194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.3611349194
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.381565131
Short name T551
Test name
Test status
Simulation time 105353455 ps
CPU time 1.22 seconds
Started Jul 15 07:17:01 PM PDT 24
Finished Jul 15 07:18:24 PM PDT 24
Peak memory 220336 kb
Host smart-1bf7e55e-8db9-493f-b70f-63ed1a3b4fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381565131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.381565131
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.4260717594
Short name T680
Test name
Test status
Simulation time 52782641 ps
CPU time 1.24 seconds
Started Jul 15 07:17:01 PM PDT 24
Finished Jul 15 07:18:24 PM PDT 24
Peak memory 217720 kb
Host smart-16c16734-85bc-406b-97af-1253ac2d4c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260717594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.4260717594
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.3130235331
Short name T518
Test name
Test status
Simulation time 35350479 ps
CPU time 1.29 seconds
Started Jul 15 07:17:07 PM PDT 24
Finished Jul 15 07:18:32 PM PDT 24
Peak memory 217668 kb
Host smart-bf130ab6-f58f-4a72-8b94-cb497527058d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130235331 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.3130235331
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1715800009
Short name T336
Test name
Test status
Simulation time 174166354 ps
CPU time 1.05 seconds
Started Jul 15 07:16:56 PM PDT 24
Finished Jul 15 07:18:12 PM PDT 24
Peak memory 217688 kb
Host smart-2b0ab87f-6112-4e73-b946-257b88c035f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715800009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1715800009
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.2444338699
Short name T88
Test name
Test status
Simulation time 209196331 ps
CPU time 1.16 seconds
Started Jul 15 07:13:51 PM PDT 24
Finished Jul 15 07:15:43 PM PDT 24
Peak memory 220916 kb
Host smart-cafc73d2-997f-4709-a5c5-22d0b2da3beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444338699 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.2444338699
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.577912799
Short name T827
Test name
Test status
Simulation time 33814247 ps
CPU time 0.93 seconds
Started Jul 15 07:13:46 PM PDT 24
Finished Jul 15 07:15:29 PM PDT 24
Peak memory 206988 kb
Host smart-85687343-06f3-4d8a-9d7b-80753ca7ecf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577912799 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.577912799
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.735195429
Short name T581
Test name
Test status
Simulation time 34087589 ps
CPU time 0.82 seconds
Started Jul 15 07:13:47 PM PDT 24
Finished Jul 15 07:15:29 PM PDT 24
Peak memory 216552 kb
Host smart-43f81b67-9573-4bbf-9707-2cdb1450553f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735195429 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.735195429
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.1810564508
Short name T453
Test name
Test status
Simulation time 35211936 ps
CPU time 1.14 seconds
Started Jul 15 07:13:43 PM PDT 24
Finished Jul 15 07:15:27 PM PDT 24
Peak memory 218784 kb
Host smart-b34c78b3-fdee-49f5-86d6-ec808267d54b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810564508 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.1810564508
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.2534212830
Short name T907
Test name
Test status
Simulation time 27566342 ps
CPU time 0.98 seconds
Started Jul 15 07:13:43 PM PDT 24
Finished Jul 15 07:15:27 PM PDT 24
Peak memory 220016 kb
Host smart-b3e80d2c-c2a2-47e2-9aff-b5b294a9f49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534212830 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.2534212830
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.49335981
Short name T44
Test name
Test status
Simulation time 74489615 ps
CPU time 1.42 seconds
Started Jul 15 07:13:51 PM PDT 24
Finished Jul 15 07:15:35 PM PDT 24
Peak memory 217668 kb
Host smart-e4cd6ee3-f8dd-44ad-b867-8ca0ce9c9b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49335981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.49335981
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.2730925668
Short name T39
Test name
Test status
Simulation time 19624176 ps
CPU time 1.06 seconds
Started Jul 15 07:13:51 PM PDT 24
Finished Jul 15 07:15:43 PM PDT 24
Peak memory 216072 kb
Host smart-c28cc8c6-4d57-4e0f-87d9-3eafe463139e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730925668 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2730925668
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.3362666319
Short name T454
Test name
Test status
Simulation time 19125186 ps
CPU time 1 seconds
Started Jul 15 07:13:45 PM PDT 24
Finished Jul 15 07:15:29 PM PDT 24
Peak memory 215604 kb
Host smart-e482a2d1-7bd6-4739-bb9e-14c2d9a04304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362666319 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.3362666319
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.3210520812
Short name T400
Test name
Test status
Simulation time 434762064 ps
CPU time 2 seconds
Started Jul 15 07:13:51 PM PDT 24
Finished Jul 15 07:15:35 PM PDT 24
Peak memory 217676 kb
Host smart-29e571ef-9f3c-4664-9b93-41675198fec9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210520812 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.3210520812
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.798494418
Short name T923
Test name
Test status
Simulation time 19915216945 ps
CPU time 227.29 seconds
Started Jul 15 07:13:43 PM PDT 24
Finished Jul 15 07:19:14 PM PDT 24
Peak memory 216828 kb
Host smart-dfefce60-718c-4663-9014-1fcda7b06d47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798494418 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.798494418
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.835729596
Short name T467
Test name
Test status
Simulation time 81227614 ps
CPU time 3.14 seconds
Started Jul 15 07:17:00 PM PDT 24
Finished Jul 15 07:18:19 PM PDT 24
Peak memory 219264 kb
Host smart-53a634cc-a662-4af0-88f9-77002c6b1f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835729596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.835729596
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2069329437
Short name T871
Test name
Test status
Simulation time 21842521 ps
CPU time 1.14 seconds
Started Jul 15 07:16:57 PM PDT 24
Finished Jul 15 07:18:16 PM PDT 24
Peak memory 219036 kb
Host smart-cb73a417-f35d-4c0c-9c89-afd7dfff68da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069329437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2069329437
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.1128192990
Short name T763
Test name
Test status
Simulation time 35928620 ps
CPU time 1.44 seconds
Started Jul 15 07:16:59 PM PDT 24
Finished Jul 15 07:18:16 PM PDT 24
Peak memory 218648 kb
Host smart-20462336-40f3-4ceb-ac4e-74e7fa91dc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128192990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.1128192990
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.1575064997
Short name T947
Test name
Test status
Simulation time 57184596 ps
CPU time 1.49 seconds
Started Jul 15 07:16:57 PM PDT 24
Finished Jul 15 07:18:12 PM PDT 24
Peak memory 219012 kb
Host smart-fe2ed3de-32aa-486e-b4e4-875d8dcb45ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575064997 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.1575064997
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.75996802
Short name T598
Test name
Test status
Simulation time 43464537 ps
CPU time 1.34 seconds
Started Jul 15 07:16:58 PM PDT 24
Finished Jul 15 07:18:16 PM PDT 24
Peak memory 220168 kb
Host smart-d8e31c86-3293-45c2-bd48-87f58fe84edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75996802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.75996802
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.2136711032
Short name T425
Test name
Test status
Simulation time 58963445 ps
CPU time 1.28 seconds
Started Jul 15 07:16:58 PM PDT 24
Finished Jul 15 07:18:16 PM PDT 24
Peak memory 217676 kb
Host smart-d1c78b23-1b79-40a5-9d30-c53122e4e73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136711032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2136711032
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.27677025
Short name T383
Test name
Test status
Simulation time 47467288 ps
CPU time 1.69 seconds
Started Jul 15 07:17:04 PM PDT 24
Finished Jul 15 07:18:34 PM PDT 24
Peak memory 218892 kb
Host smart-43d05bbc-efcc-41fa-be9d-40bc0dccc9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27677025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.27677025
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.2606691056
Short name T637
Test name
Test status
Simulation time 105877400 ps
CPU time 1.61 seconds
Started Jul 15 07:17:13 PM PDT 24
Finished Jul 15 07:18:42 PM PDT 24
Peak memory 217752 kb
Host smart-106be2b8-81cb-4b45-98f7-14fd36fbb161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606691056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.2606691056
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.630531645
Short name T915
Test name
Test status
Simulation time 66450718 ps
CPU time 1.03 seconds
Started Jul 15 07:17:04 PM PDT 24
Finished Jul 15 07:18:33 PM PDT 24
Peak memory 217580 kb
Host smart-157189fb-6559-4a23-8068-6b656c2cfa8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630531645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.630531645
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.2532629348
Short name T546
Test name
Test status
Simulation time 48957192 ps
CPU time 1.81 seconds
Started Jul 15 07:17:07 PM PDT 24
Finished Jul 15 07:18:32 PM PDT 24
Peak memory 218708 kb
Host smart-ca267607-0da3-408c-86c8-00df601092bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532629348 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.2532629348
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.3252317856
Short name T94
Test name
Test status
Simulation time 41018937 ps
CPU time 1.09 seconds
Started Jul 15 07:13:40 PM PDT 24
Finished Jul 15 07:15:21 PM PDT 24
Peak memory 219856 kb
Host smart-49f62b82-d6c2-4dd5-be19-b21faac28c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252317856 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.3252317856
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.4086559833
Short name T784
Test name
Test status
Simulation time 16700240 ps
CPU time 0.9 seconds
Started Jul 15 07:13:44 PM PDT 24
Finished Jul 15 07:15:27 PM PDT 24
Peak memory 207072 kb
Host smart-336c6b4f-7351-4325-9fb4-07bad9f2fa84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086559833 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.4086559833
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.3014430259
Short name T254
Test name
Test status
Simulation time 126205507 ps
CPU time 1.19 seconds
Started Jul 15 07:13:47 PM PDT 24
Finished Jul 15 07:15:30 PM PDT 24
Peak memory 219736 kb
Host smart-05df4437-01ec-4e3b-a180-040b875ff91c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014430259 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.3014430259
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.1028992319
Short name T935
Test name
Test status
Simulation time 19587108 ps
CPU time 1.15 seconds
Started Jul 15 07:13:43 PM PDT 24
Finished Jul 15 07:15:27 PM PDT 24
Peak memory 224280 kb
Host smart-b751484e-dd57-40be-a834-ac5c275e47ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028992319 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1028992319
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.4707852
Short name T785
Test name
Test status
Simulation time 80473585 ps
CPU time 1.26 seconds
Started Jul 15 07:13:40 PM PDT 24
Finished Jul 15 07:15:21 PM PDT 24
Peak memory 217668 kb
Host smart-5beb3a8d-8f0b-4844-b43a-fa0fde0601ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4707852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.4707852
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.1370115337
Short name T30
Test name
Test status
Simulation time 21603912 ps
CPU time 0.88 seconds
Started Jul 15 07:13:39 PM PDT 24
Finished Jul 15 07:15:20 PM PDT 24
Peak memory 216184 kb
Host smart-a11341f7-e1c7-4297-83c6-5fbfd3dfa502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370115337 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.1370115337
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.3638750128
Short name T368
Test name
Test status
Simulation time 48825638 ps
CPU time 0.9 seconds
Started Jul 15 07:13:40 PM PDT 24
Finished Jul 15 07:15:21 PM PDT 24
Peak memory 215672 kb
Host smart-6e0473b9-915f-4111-9929-6a6fdf0cbaa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638750128 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.3638750128
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.3749924779
Short name T348
Test name
Test status
Simulation time 179036968 ps
CPU time 3.59 seconds
Started Jul 15 07:13:45 PM PDT 24
Finished Jul 15 07:15:31 PM PDT 24
Peak memory 215728 kb
Host smart-ccad06a6-b01b-4b80-8a12-e7b6653d5787
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749924779 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3749924779
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.3470757864
Short name T710
Test name
Test status
Simulation time 41298622035 ps
CPU time 233.42 seconds
Started Jul 15 07:13:43 PM PDT 24
Finished Jul 15 07:19:19 PM PDT 24
Peak memory 218280 kb
Host smart-d5a3d4cb-f592-4a81-8d97-1bb83040aeb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470757864 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.3470757864
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.834140065
Short name T755
Test name
Test status
Simulation time 66485318 ps
CPU time 1.19 seconds
Started Jul 15 07:17:03 PM PDT 24
Finished Jul 15 07:18:23 PM PDT 24
Peak memory 220188 kb
Host smart-35af8545-8f2c-4ad7-a5b9-9ea408a6ac0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834140065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.834140065
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.269657439
Short name T878
Test name
Test status
Simulation time 47099650 ps
CPU time 1.18 seconds
Started Jul 15 07:17:05 PM PDT 24
Finished Jul 15 07:18:34 PM PDT 24
Peak memory 215548 kb
Host smart-828f4214-8e76-4432-b970-e4118e17e4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269657439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.269657439
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.88924674
Short name T497
Test name
Test status
Simulation time 104183218 ps
CPU time 1.46 seconds
Started Jul 15 07:17:04 PM PDT 24
Finished Jul 15 07:18:34 PM PDT 24
Peak memory 218964 kb
Host smart-af7ce010-6e3e-4966-97f3-42787c09d286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88924674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.88924674
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.3583493516
Short name T850
Test name
Test status
Simulation time 28962228 ps
CPU time 1.2 seconds
Started Jul 15 07:17:10 PM PDT 24
Finished Jul 15 07:18:34 PM PDT 24
Peak memory 219612 kb
Host smart-cb698a10-46c5-4817-873f-e8d33094deaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583493516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.3583493516
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.2968212652
Short name T96
Test name
Test status
Simulation time 59994964 ps
CPU time 1.45 seconds
Started Jul 15 07:17:05 PM PDT 24
Finished Jul 15 07:18:24 PM PDT 24
Peak memory 219128 kb
Host smart-90fe3cff-3cb3-4e8b-9860-abe02bb973cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968212652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.2968212652
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.3780422841
Short name T325
Test name
Test status
Simulation time 54742291 ps
CPU time 1.94 seconds
Started Jul 15 07:17:03 PM PDT 24
Finished Jul 15 07:18:24 PM PDT 24
Peak memory 217756 kb
Host smart-5037b0bb-019c-4a72-8e7e-711585abd6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780422841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.3780422841
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.1146906774
Short name T521
Test name
Test status
Simulation time 63375294 ps
CPU time 2.12 seconds
Started Jul 15 07:17:04 PM PDT 24
Finished Jul 15 07:18:24 PM PDT 24
Peak memory 217668 kb
Host smart-02527023-5bca-447e-8299-85e98213f7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146906774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.1146906774
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.3012193467
Short name T714
Test name
Test status
Simulation time 38290953 ps
CPU time 1.3 seconds
Started Jul 15 07:17:11 PM PDT 24
Finished Jul 15 07:18:34 PM PDT 24
Peak memory 219000 kb
Host smart-178f8444-9873-4c27-ac2d-5636feb5bf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012193467 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.3012193467
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.4048499874
Short name T458
Test name
Test status
Simulation time 81490560 ps
CPU time 1.32 seconds
Started Jul 15 07:17:04 PM PDT 24
Finished Jul 15 07:18:23 PM PDT 24
Peak memory 219000 kb
Host smart-c22e56ec-82f2-4d1e-97a9-b89fbec834b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048499874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.4048499874
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.2191226987
Short name T382
Test name
Test status
Simulation time 175544006 ps
CPU time 1.35 seconds
Started Jul 15 07:17:06 PM PDT 24
Finished Jul 15 07:18:32 PM PDT 24
Peak memory 220312 kb
Host smart-df3bd850-fe89-44e8-9541-689ef5be6063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191226987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.2191226987
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.1555952492
Short name T705
Test name
Test status
Simulation time 162707946 ps
CPU time 1.22 seconds
Started Jul 15 07:13:44 PM PDT 24
Finished Jul 15 07:15:28 PM PDT 24
Peak memory 216004 kb
Host smart-88825bdf-9c6f-4c4d-8edd-c3199f07c1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555952492 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.1555952492
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.3329150902
Short name T740
Test name
Test status
Simulation time 36937807 ps
CPU time 0.83 seconds
Started Jul 15 07:13:45 PM PDT 24
Finished Jul 15 07:15:29 PM PDT 24
Peak memory 215032 kb
Host smart-0799e238-b3b5-4209-a15e-a2017af93a30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329150902 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.3329150902
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.1746954224
Short name T207
Test name
Test status
Simulation time 27963900 ps
CPU time 0.81 seconds
Started Jul 15 07:13:43 PM PDT 24
Finished Jul 15 07:15:27 PM PDT 24
Peak memory 216448 kb
Host smart-a6ee86dc-8c77-4ce6-8409-88dbfb6b646e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746954224 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.1746954224
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_genbits.2441482883
Short name T883
Test name
Test status
Simulation time 62674044 ps
CPU time 1.1 seconds
Started Jul 15 07:13:42 PM PDT 24
Finished Jul 15 07:15:21 PM PDT 24
Peak memory 218996 kb
Host smart-f826a7dc-dd7e-4d5f-ba24-7de29552590f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441482883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.2441482883
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.367290672
Short name T16
Test name
Test status
Simulation time 35237979 ps
CPU time 0.99 seconds
Started Jul 15 07:13:51 PM PDT 24
Finished Jul 15 07:15:35 PM PDT 24
Peak memory 224336 kb
Host smart-47ff7780-e165-49d0-9d58-b0a5736e52c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367290672 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.367290672
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.1233680465
Short name T371
Test name
Test status
Simulation time 22125762 ps
CPU time 0.94 seconds
Started Jul 15 07:13:43 PM PDT 24
Finished Jul 15 07:15:27 PM PDT 24
Peak memory 215604 kb
Host smart-3f09d9be-929e-4a6d-b501-8904cdc99fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233680465 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.1233680465
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.284964494
Short name T249
Test name
Test status
Simulation time 186131256 ps
CPU time 1.13 seconds
Started Jul 15 07:13:47 PM PDT 24
Finished Jul 15 07:15:29 PM PDT 24
Peak memory 206992 kb
Host smart-2e3b3c93-fc56-4462-8129-f1f87553c67c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284964494 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.284964494
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.1570649375
Short name T238
Test name
Test status
Simulation time 247093086037 ps
CPU time 3086.45 seconds
Started Jul 15 07:13:43 PM PDT 24
Finished Jul 15 08:06:53 PM PDT 24
Peak memory 236532 kb
Host smart-b0882aae-3e3d-4b7d-991e-5e3ef22bd4a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570649375 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.1570649375
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.2781464142
Short name T351
Test name
Test status
Simulation time 38408911 ps
CPU time 1.65 seconds
Started Jul 15 07:17:06 PM PDT 24
Finished Jul 15 07:18:34 PM PDT 24
Peak memory 218924 kb
Host smart-0ded1541-79fd-4f96-951a-f3f1dc53daa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781464142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2781464142
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.2266318321
Short name T555
Test name
Test status
Simulation time 70870478 ps
CPU time 1.16 seconds
Started Jul 15 07:17:06 PM PDT 24
Finished Jul 15 07:18:32 PM PDT 24
Peak memory 219132 kb
Host smart-3555b277-d0d2-4417-8dd8-daebef3d718e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266318321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.2266318321
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.584869392
Short name T572
Test name
Test status
Simulation time 36773473 ps
CPU time 1.35 seconds
Started Jul 15 07:17:06 PM PDT 24
Finished Jul 15 07:18:34 PM PDT 24
Peak memory 217640 kb
Host smart-2dc0990f-9fd5-40a5-a42e-0e2138ad147e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584869392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.584869392
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.2841572845
Short name T808
Test name
Test status
Simulation time 83846268 ps
CPU time 1.98 seconds
Started Jul 15 07:17:03 PM PDT 24
Finished Jul 15 07:18:24 PM PDT 24
Peak memory 219460 kb
Host smart-9d102dee-64db-4fc0-aed0-74103b01e928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841572845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2841572845
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.4133687780
Short name T918
Test name
Test status
Simulation time 89091647 ps
CPU time 1.23 seconds
Started Jul 15 07:17:06 PM PDT 24
Finished Jul 15 07:18:32 PM PDT 24
Peak memory 217744 kb
Host smart-d52fcd11-3b96-4918-8942-2ed292463eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133687780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.4133687780
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.3961950857
Short name T485
Test name
Test status
Simulation time 31452849 ps
CPU time 1.27 seconds
Started Jul 15 07:17:07 PM PDT 24
Finished Jul 15 07:18:32 PM PDT 24
Peak memory 217844 kb
Host smart-b8a21057-73d1-4191-9a57-7f5bed758613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961950857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.3961950857
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.2762692186
Short name T576
Test name
Test status
Simulation time 56295853 ps
CPU time 1.21 seconds
Started Jul 15 07:17:10 PM PDT 24
Finished Jul 15 07:18:34 PM PDT 24
Peak memory 219856 kb
Host smart-d51b985e-1f7a-44f5-8ff2-2843beaa2157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762692186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.2762692186
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.1135667199
Short name T465
Test name
Test status
Simulation time 27262908 ps
CPU time 1.28 seconds
Started Jul 15 07:17:05 PM PDT 24
Finished Jul 15 07:18:34 PM PDT 24
Peak memory 217864 kb
Host smart-77aa6289-824e-40b5-842a-ce8a4cf9d98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135667199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.1135667199
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.315751308
Short name T688
Test name
Test status
Simulation time 64947890 ps
CPU time 1.15 seconds
Started Jul 15 07:17:08 PM PDT 24
Finished Jul 15 07:18:33 PM PDT 24
Peak memory 219192 kb
Host smart-dff5652f-ab13-446d-afe2-5e284982b5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315751308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.315751308
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.3484783831
Short name T435
Test name
Test status
Simulation time 133150393 ps
CPU time 1.79 seconds
Started Jul 15 07:17:07 PM PDT 24
Finished Jul 15 07:18:33 PM PDT 24
Peak memory 219760 kb
Host smart-64f0ad46-626d-4220-815b-f0103c50e709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484783831 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.3484783831
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.4272860634
Short name T729
Test name
Test status
Simulation time 28059063 ps
CPU time 1.21 seconds
Started Jul 15 07:13:50 PM PDT 24
Finished Jul 15 07:15:30 PM PDT 24
Peak memory 220224 kb
Host smart-d2ee841b-c9cd-475a-8b1c-1872db7609f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272860634 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.4272860634
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.2371501026
Short name T432
Test name
Test status
Simulation time 121446381 ps
CPU time 0.86 seconds
Started Jul 15 07:13:49 PM PDT 24
Finished Jul 15 07:15:30 PM PDT 24
Peak memory 215264 kb
Host smart-ac35bf7d-e1b1-4992-ae61-3c03b71413c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371501026 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2371501026
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.226387629
Short name T758
Test name
Test status
Simulation time 13351746 ps
CPU time 0.9 seconds
Started Jul 15 07:13:51 PM PDT 24
Finished Jul 15 07:15:43 PM PDT 24
Peak memory 216692 kb
Host smart-149f0a85-b4db-4212-98b8-98267e85f680
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226387629 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.226387629
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.248735596
Short name T11
Test name
Test status
Simulation time 77836574 ps
CPU time 1.03 seconds
Started Jul 15 07:13:46 PM PDT 24
Finished Jul 15 07:15:29 PM PDT 24
Peak memory 219976 kb
Host smart-d0fbe2fd-a639-41d1-91dc-ddbef88955fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248735596 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_di
sable_auto_req_mode.248735596
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.2983800589
Short name T840
Test name
Test status
Simulation time 22811191 ps
CPU time 1.16 seconds
Started Jul 15 07:13:49 PM PDT 24
Finished Jul 15 07:15:30 PM PDT 24
Peak memory 218768 kb
Host smart-5727ed89-9162-4e01-aa64-9a4eba1b3667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983800589 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2983800589
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.1745251075
Short name T304
Test name
Test status
Simulation time 51527662 ps
CPU time 1.31 seconds
Started Jul 15 07:13:52 PM PDT 24
Finished Jul 15 07:15:36 PM PDT 24
Peak memory 220436 kb
Host smart-50e5a426-b390-4ed1-a46b-39f8378975da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745251075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.1745251075
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.2087480088
Short name T520
Test name
Test status
Simulation time 24009058 ps
CPU time 1.09 seconds
Started Jul 15 07:13:52 PM PDT 24
Finished Jul 15 07:15:34 PM PDT 24
Peak memory 215812 kb
Host smart-d1f1cfb8-941a-4d94-957e-8fb3dcb477ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087480088 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.2087480088
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.278469996
Short name T925
Test name
Test status
Simulation time 49129536 ps
CPU time 0.89 seconds
Started Jul 15 07:13:49 PM PDT 24
Finished Jul 15 07:15:30 PM PDT 24
Peak memory 215648 kb
Host smart-55ce0b91-5ede-443e-ab7d-7a2ef2f1f58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278469996 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.278469996
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.3632471350
Short name T926
Test name
Test status
Simulation time 133387340 ps
CPU time 3.07 seconds
Started Jul 15 07:13:50 PM PDT 24
Finished Jul 15 07:15:36 PM PDT 24
Peak memory 215524 kb
Host smart-ebd7257e-64b6-411d-9b3e-dca12fe25503
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632471350 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.3632471350
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.2305728559
Short name T244
Test name
Test status
Simulation time 38550268928 ps
CPU time 369.19 seconds
Started Jul 15 07:13:49 PM PDT 24
Finished Jul 15 07:21:38 PM PDT 24
Peak memory 218472 kb
Host smart-80dc4abe-e347-40f0-8ff7-8c1b60d9b271
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305728559 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.2305728559
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.1559390136
Short name T433
Test name
Test status
Simulation time 52359670 ps
CPU time 1.98 seconds
Started Jul 15 07:17:06 PM PDT 24
Finished Jul 15 07:18:35 PM PDT 24
Peak memory 218884 kb
Host smart-5a8de207-7d69-416e-b781-4219df28c673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559390136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.1559390136
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.749824009
Short name T958
Test name
Test status
Simulation time 60820439 ps
CPU time 1.08 seconds
Started Jul 15 07:17:06 PM PDT 24
Finished Jul 15 07:18:32 PM PDT 24
Peak memory 220388 kb
Host smart-796c4e13-75d4-46f0-948b-e3c406e3b047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749824009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.749824009
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.1434713882
Short name T547
Test name
Test status
Simulation time 77729409 ps
CPU time 1.18 seconds
Started Jul 15 07:17:06 PM PDT 24
Finished Jul 15 07:18:32 PM PDT 24
Peak memory 219884 kb
Host smart-f538cc33-3a11-4ed8-bc8a-caec591676e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434713882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.1434713882
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.24462216
Short name T442
Test name
Test status
Simulation time 119553744 ps
CPU time 1.23 seconds
Started Jul 15 07:17:05 PM PDT 24
Finished Jul 15 07:18:34 PM PDT 24
Peak memory 217436 kb
Host smart-9fc23c7a-9333-42f8-b238-1555a39ec396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24462216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.24462216
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.78337052
Short name T337
Test name
Test status
Simulation time 37518986 ps
CPU time 1.3 seconds
Started Jul 15 07:17:05 PM PDT 24
Finished Jul 15 07:18:34 PM PDT 24
Peak memory 217460 kb
Host smart-2091b9f7-8b01-44fa-8680-979cfe237443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78337052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.78337052
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.3016977497
Short name T544
Test name
Test status
Simulation time 53956172 ps
CPU time 1.9 seconds
Started Jul 15 07:17:05 PM PDT 24
Finished Jul 15 07:18:34 PM PDT 24
Peak memory 219684 kb
Host smart-a12b7015-4523-41ed-ab7f-73caaf0245a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016977497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3016977497
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.2397422589
Short name T468
Test name
Test status
Simulation time 103392128 ps
CPU time 1.21 seconds
Started Jul 15 07:17:03 PM PDT 24
Finished Jul 15 07:18:23 PM PDT 24
Peak memory 217676 kb
Host smart-0ba8dfa4-750d-41f8-9266-c8f88f9a7182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397422589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2397422589
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.1723119575
Short name T741
Test name
Test status
Simulation time 54816384 ps
CPU time 1.1 seconds
Started Jul 15 07:17:11 PM PDT 24
Finished Jul 15 07:18:34 PM PDT 24
Peak memory 220096 kb
Host smart-a8807b18-3389-4aa4-883b-eea939466d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723119575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.1723119575
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.176571968
Short name T508
Test name
Test status
Simulation time 45697543 ps
CPU time 0.93 seconds
Started Jul 15 07:17:06 PM PDT 24
Finished Jul 15 07:18:31 PM PDT 24
Peak memory 217528 kb
Host smart-fadfba58-f9e5-48e6-8f8f-2b87c214b197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176571968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.176571968
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.1837738600
Short name T45
Test name
Test status
Simulation time 50689239 ps
CPU time 1.91 seconds
Started Jul 15 07:17:10 PM PDT 24
Finished Jul 15 07:18:34 PM PDT 24
Peak memory 218916 kb
Host smart-71900da2-e396-4113-8c04-528707be5f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837738600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1837738600
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.1524362157
Short name T127
Test name
Test status
Simulation time 98909915 ps
CPU time 1.18 seconds
Started Jul 15 07:13:52 PM PDT 24
Finished Jul 15 07:15:43 PM PDT 24
Peak memory 220116 kb
Host smart-7abea9d5-d1bd-4e94-b4a1-2ec4dc4ad66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524362157 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1524362157
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.2689102290
Short name T754
Test name
Test status
Simulation time 41019221 ps
CPU time 0.84 seconds
Started Jul 15 07:13:53 PM PDT 24
Finished Jul 15 07:15:35 PM PDT 24
Peak memory 214968 kb
Host smart-0500ce04-1fd0-49f8-80d9-d988ef2abb64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689102290 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.2689102290
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.3696208729
Short name T209
Test name
Test status
Simulation time 12512982 ps
CPU time 0.92 seconds
Started Jul 15 07:13:52 PM PDT 24
Finished Jul 15 07:15:43 PM PDT 24
Peak memory 216776 kb
Host smart-9db77b3f-ea4a-42de-afe0-6ea1f94f273e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696208729 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.3696208729
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.2793961150
Short name T693
Test name
Test status
Simulation time 70846215 ps
CPU time 1.29 seconds
Started Jul 15 07:13:51 PM PDT 24
Finished Jul 15 07:15:35 PM PDT 24
Peak memory 218568 kb
Host smart-4d4454c3-b806-44c6-831f-774e081f935d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793961150 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.2793961150
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.1486997066
Short name T206
Test name
Test status
Simulation time 45040373 ps
CPU time 1.18 seconds
Started Jul 15 07:13:51 PM PDT 24
Finished Jul 15 07:15:35 PM PDT 24
Peak memory 219940 kb
Host smart-654c6a66-332e-44ff-bb77-1a418187c1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486997066 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.1486997066
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.828586043
Short name T960
Test name
Test status
Simulation time 77820998 ps
CPU time 1.13 seconds
Started Jul 15 07:13:48 PM PDT 24
Finished Jul 15 07:15:30 PM PDT 24
Peak memory 217660 kb
Host smart-289f0a5f-f3ea-4c73-9731-9aee16503a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828586043 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.828586043
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.944039811
Short name T944
Test name
Test status
Simulation time 25990630 ps
CPU time 0.92 seconds
Started Jul 15 07:13:49 PM PDT 24
Finished Jul 15 07:15:30 PM PDT 24
Peak memory 215704 kb
Host smart-fbd54949-3825-426c-8af5-315311ea31e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944039811 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.944039811
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.3484299368
Short name T529
Test name
Test status
Simulation time 58375201 ps
CPU time 0.92 seconds
Started Jul 15 07:13:50 PM PDT 24
Finished Jul 15 07:15:34 PM PDT 24
Peak memory 215480 kb
Host smart-98ee76f6-cd34-4efa-8b19-003288edd79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484299368 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.3484299368
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.98453302
Short name T405
Test name
Test status
Simulation time 295617716 ps
CPU time 5.96 seconds
Started Jul 15 07:13:50 PM PDT 24
Finished Jul 15 07:15:35 PM PDT 24
Peak memory 220016 kb
Host smart-50913cb5-0fb5-4e7f-9903-84bc521bf48e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98453302 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.98453302
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/290.edn_genbits.3267401227
Short name T991
Test name
Test status
Simulation time 50359431 ps
CPU time 1.05 seconds
Started Jul 15 07:17:08 PM PDT 24
Finished Jul 15 07:18:33 PM PDT 24
Peak memory 219176 kb
Host smart-22fdc298-4d0b-49a7-93b4-654f09fcde87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267401227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.3267401227
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.1247243964
Short name T341
Test name
Test status
Simulation time 82274667 ps
CPU time 1.57 seconds
Started Jul 15 07:17:05 PM PDT 24
Finished Jul 15 07:18:24 PM PDT 24
Peak memory 219224 kb
Host smart-73ee140e-1a18-4129-8812-2c4812cecd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247243964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.1247243964
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.3904072463
Short name T300
Test name
Test status
Simulation time 55586235 ps
CPU time 1.74 seconds
Started Jul 15 07:17:03 PM PDT 24
Finished Jul 15 07:18:24 PM PDT 24
Peak memory 218952 kb
Host smart-b2463c1d-bd72-4f7d-b195-942ecc9a1536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904072463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.3904072463
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.68055552
Short name T355
Test name
Test status
Simulation time 32051706 ps
CPU time 1.33 seconds
Started Jul 15 07:17:10 PM PDT 24
Finished Jul 15 07:18:34 PM PDT 24
Peak memory 218876 kb
Host smart-7da1fa73-26c5-4500-a3ef-e575e87c94b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68055552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.68055552
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3870573986
Short name T374
Test name
Test status
Simulation time 85225889 ps
CPU time 0.94 seconds
Started Jul 15 07:17:08 PM PDT 24
Finished Jul 15 07:18:33 PM PDT 24
Peak memory 219300 kb
Host smart-a63309d3-2bda-462e-9d2c-d0f9356ef7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870573986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3870573986
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.609301927
Short name T638
Test name
Test status
Simulation time 51376357 ps
CPU time 1.58 seconds
Started Jul 15 07:17:08 PM PDT 24
Finished Jul 15 07:18:33 PM PDT 24
Peak memory 218824 kb
Host smart-4690efff-a5e9-4316-91fb-598d77c93319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609301927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.609301927
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.1545427854
Short name T809
Test name
Test status
Simulation time 1263407811 ps
CPU time 8.57 seconds
Started Jul 15 07:17:12 PM PDT 24
Finished Jul 15 07:18:49 PM PDT 24
Peak memory 218900 kb
Host smart-d316e711-056d-4d8d-b4ba-239302fe1151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545427854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.1545427854
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.3405480119
Short name T698
Test name
Test status
Simulation time 72344715 ps
CPU time 1.08 seconds
Started Jul 15 07:17:06 PM PDT 24
Finished Jul 15 07:18:34 PM PDT 24
Peak memory 217636 kb
Host smart-d531e52a-e701-4718-ab10-e46b2d08047e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405480119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.3405480119
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.2868098768
Short name T969
Test name
Test status
Simulation time 158664762 ps
CPU time 1.45 seconds
Started Jul 15 07:17:07 PM PDT 24
Finished Jul 15 07:18:32 PM PDT 24
Peak memory 219176 kb
Host smart-30dbd566-3778-4b72-9a2d-d1a456df6dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868098768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.2868098768
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.1710801759
Short name T593
Test name
Test status
Simulation time 41569057 ps
CPU time 1.37 seconds
Started Jul 15 07:17:05 PM PDT 24
Finished Jul 15 07:18:24 PM PDT 24
Peak memory 218856 kb
Host smart-82a74e70-05e5-4f70-a896-2ae50fd46c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710801759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1710801759
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.3920836862
Short name T592
Test name
Test status
Simulation time 37822067 ps
CPU time 1.09 seconds
Started Jul 15 07:13:00 PM PDT 24
Finished Jul 15 07:14:07 PM PDT 24
Peak memory 219176 kb
Host smart-a0c08bb8-0fa8-4d53-b1bb-bc8d72be5b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920836862 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.3920836862
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.3566301270
Short name T734
Test name
Test status
Simulation time 22813654 ps
CPU time 0.83 seconds
Started Jul 15 07:12:55 PM PDT 24
Finished Jul 15 07:13:52 PM PDT 24
Peak memory 206852 kb
Host smart-26f3131a-16b7-4de7-a806-d7b81b6d1230
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566301270 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3566301270
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.442242976
Short name T515
Test name
Test status
Simulation time 33362227 ps
CPU time 0.84 seconds
Started Jul 15 07:13:02 PM PDT 24
Finished Jul 15 07:14:16 PM PDT 24
Peak memory 216596 kb
Host smart-9719c379-02bf-440e-995f-5ba94ce09ddf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442242976 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.442242976
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.2740459456
Short name T220
Test name
Test status
Simulation time 89586248 ps
CPU time 1.05 seconds
Started Jul 15 07:12:59 PM PDT 24
Finished Jul 15 07:14:00 PM PDT 24
Peak memory 217216 kb
Host smart-66ff7f2c-d5f9-40bf-bf60-72ad63cf6240
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740459456 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.2740459456
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.1167106103
Short name T578
Test name
Test status
Simulation time 19797210 ps
CPU time 1.2 seconds
Started Jul 15 07:13:00 PM PDT 24
Finished Jul 15 07:14:07 PM PDT 24
Peak memory 224196 kb
Host smart-08cb2e09-8c19-406a-8aee-e81c54159674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167106103 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.1167106103
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.4264642657
Short name T12
Test name
Test status
Simulation time 45876618 ps
CPU time 1.45 seconds
Started Jul 15 07:13:01 PM PDT 24
Finished Jul 15 07:14:08 PM PDT 24
Peak memory 219896 kb
Host smart-aa5b831d-98c8-4d48-b870-8e79257e3fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264642657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.4264642657
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.1044862755
Short name T113
Test name
Test status
Simulation time 30861610 ps
CPU time 0.92 seconds
Started Jul 15 07:13:07 PM PDT 24
Finished Jul 15 07:14:25 PM PDT 24
Peak memory 216296 kb
Host smart-0309097e-bfcc-4848-bc30-42d43bbb40b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044862755 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.1044862755
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.272206389
Short name T28
Test name
Test status
Simulation time 52168805 ps
CPU time 0.94 seconds
Started Jul 15 07:13:02 PM PDT 24
Finished Jul 15 07:14:15 PM PDT 24
Peak memory 207376 kb
Host smart-bb495093-d9e4-4fd3-bb88-1c13100fb92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272206389 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.272206389
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.3984396367
Short name T962
Test name
Test status
Simulation time 46866592 ps
CPU time 0.92 seconds
Started Jul 15 07:13:01 PM PDT 24
Finished Jul 15 07:14:08 PM PDT 24
Peak memory 215628 kb
Host smart-a7405614-3fc6-4964-bc5e-1004eb58f129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984396367 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3984396367
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.1899548013
Short name T727
Test name
Test status
Simulation time 212288502 ps
CPU time 1.1 seconds
Started Jul 15 07:12:54 PM PDT 24
Finished Jul 15 07:13:45 PM PDT 24
Peak memory 217692 kb
Host smart-ba052a7b-d0ba-49a9-a35e-f6eeaffd1e5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899548013 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1899548013
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.1052159616
Short name T242
Test name
Test status
Simulation time 96864568566 ps
CPU time 2178.77 seconds
Started Jul 15 07:13:06 PM PDT 24
Finished Jul 15 07:50:42 PM PDT 24
Peak memory 227468 kb
Host smart-feb57ee7-e021-4629-8715-20ac87ab928e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052159616 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.1052159616
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.2287266092
Short name T735
Test name
Test status
Simulation time 25399674 ps
CPU time 1.15 seconds
Started Jul 15 07:13:55 PM PDT 24
Finished Jul 15 07:15:37 PM PDT 24
Peak memory 218832 kb
Host smart-38341364-1324-4be1-9ba2-5bbd6478f1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287266092 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.2287266092
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.3499973391
Short name T489
Test name
Test status
Simulation time 44138308 ps
CPU time 1 seconds
Started Jul 15 07:13:54 PM PDT 24
Finished Jul 15 07:15:36 PM PDT 24
Peak memory 215164 kb
Host smart-4fb35c2b-e43f-4fc5-9094-06173a351efd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499973391 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3499973391
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.587184006
Short name T707
Test name
Test status
Simulation time 68623354 ps
CPU time 0.83 seconds
Started Jul 15 07:13:56 PM PDT 24
Finished Jul 15 07:15:36 PM PDT 24
Peak memory 216264 kb
Host smart-1c2e4c59-699f-4798-a47f-cb81c2b9b8e3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587184006 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.587184006
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.2428184821
Short name T730
Test name
Test status
Simulation time 34956650 ps
CPU time 1.17 seconds
Started Jul 15 07:13:54 PM PDT 24
Finished Jul 15 07:15:36 PM PDT 24
Peak memory 218764 kb
Host smart-52cb9943-e84f-4c07-9ae9-cb2db1937b24
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428184821 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.2428184821
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.1213482167
Short name T147
Test name
Test status
Simulation time 121753986 ps
CPU time 0.92 seconds
Started Jul 15 07:13:58 PM PDT 24
Finished Jul 15 07:15:37 PM PDT 24
Peak memory 220028 kb
Host smart-a4974fcb-431c-4019-b556-9435e65c5b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213482167 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.1213482167
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.856203789
Short name T321
Test name
Test status
Simulation time 116082995 ps
CPU time 1.2 seconds
Started Jul 15 07:13:58 PM PDT 24
Finished Jul 15 07:15:42 PM PDT 24
Peak memory 217788 kb
Host smart-d35d60a8-2388-47e6-b2b4-561113db3c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856203789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.856203789
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.2819831195
Short name T101
Test name
Test status
Simulation time 19760378 ps
CPU time 1.06 seconds
Started Jul 15 07:13:54 PM PDT 24
Finished Jul 15 07:15:36 PM PDT 24
Peak memory 216176 kb
Host smart-c83935ef-0f7b-4d61-9c01-4122aea87f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819831195 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2819831195
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.1615440914
Short name T711
Test name
Test status
Simulation time 25598943 ps
CPU time 0.96 seconds
Started Jul 15 07:13:56 PM PDT 24
Finished Jul 15 07:15:37 PM PDT 24
Peak memory 215536 kb
Host smart-ae1639d4-12fb-4dee-b037-4fbf200d9c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615440914 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.1615440914
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.3542296627
Short name T771
Test name
Test status
Simulation time 765574773 ps
CPU time 4.96 seconds
Started Jul 15 07:13:58 PM PDT 24
Finished Jul 15 07:15:41 PM PDT 24
Peak memory 217572 kb
Host smart-361f3bae-c407-40ce-8e3b-0830fa1d166f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542296627 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.3542296627
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.3181726427
Short name T691
Test name
Test status
Simulation time 334593879419 ps
CPU time 613.56 seconds
Started Jul 15 07:13:56 PM PDT 24
Finished Jul 15 07:25:49 PM PDT 24
Peak memory 220024 kb
Host smart-015b5b84-35f5-4141-9169-8c207b581c44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181726427 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.3181726427
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.2392030333
Short name T842
Test name
Test status
Simulation time 26261857 ps
CPU time 1.18 seconds
Started Jul 15 07:14:00 PM PDT 24
Finished Jul 15 07:15:43 PM PDT 24
Peak memory 221316 kb
Host smart-61d5a6b2-02bc-42c7-92fd-6cc6881e5758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392030333 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.2392030333
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.2392443754
Short name T411
Test name
Test status
Simulation time 36551722 ps
CPU time 0.82 seconds
Started Jul 15 07:14:02 PM PDT 24
Finished Jul 15 07:15:45 PM PDT 24
Peak memory 207068 kb
Host smart-fe6acd14-7df5-41c1-9bf6-c2a63e742935
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392443754 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.2392443754
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.15530999
Short name T119
Test name
Test status
Simulation time 37208196 ps
CPU time 1.22 seconds
Started Jul 15 07:13:59 PM PDT 24
Finished Jul 15 07:15:44 PM PDT 24
Peak memory 218820 kb
Host smart-a134374a-b186-4451-a63b-dbfe5631b218
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15530999 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_dis
able_auto_req_mode.15530999
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.2761086592
Short name T810
Test name
Test status
Simulation time 20265532 ps
CPU time 1.04 seconds
Started Jul 15 07:14:05 PM PDT 24
Finished Jul 15 07:15:45 PM PDT 24
Peak memory 219936 kb
Host smart-e8b8a215-0212-4b9c-b794-15299ff0c355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761086592 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.2761086592
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.4158578484
Short name T751
Test name
Test status
Simulation time 56979468 ps
CPU time 2.06 seconds
Started Jul 15 07:14:03 PM PDT 24
Finished Jul 15 07:15:46 PM PDT 24
Peak memory 218932 kb
Host smart-092843ea-c778-464e-ac00-a40229b994b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158578484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.4158578484
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.1128998280
Short name T4
Test name
Test status
Simulation time 31504777 ps
CPU time 0.83 seconds
Started Jul 15 07:13:59 PM PDT 24
Finished Jul 15 07:15:44 PM PDT 24
Peak memory 215548 kb
Host smart-09fa8f11-3a5e-4989-80bc-a599352301f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128998280 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.1128998280
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.384150421
Short name T731
Test name
Test status
Simulation time 23848065 ps
CPU time 0.91 seconds
Started Jul 15 07:14:00 PM PDT 24
Finished Jul 15 07:15:44 PM PDT 24
Peak memory 215600 kb
Host smart-d8c16153-1278-4a55-80ed-dd8dc3012995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384150421 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.384150421
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.264013045
Short name T632
Test name
Test status
Simulation time 459217827 ps
CPU time 2 seconds
Started Jul 15 07:14:03 PM PDT 24
Finished Jul 15 07:15:46 PM PDT 24
Peak memory 217848 kb
Host smart-99de7ca1-782a-4d59-b7d4-6ebaaa0b0267
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264013045 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.264013045
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.970244606
Short name T781
Test name
Test status
Simulation time 175533236237 ps
CPU time 2320.99 seconds
Started Jul 15 07:14:03 PM PDT 24
Finished Jul 15 07:54:25 PM PDT 24
Peak memory 231724 kb
Host smart-cdc89010-a554-4525-bec5-a29265f255da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970244606 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.970244606
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.1897717625
Short name T820
Test name
Test status
Simulation time 92231241 ps
CPU time 1.24 seconds
Started Jul 15 07:14:02 PM PDT 24
Finished Jul 15 07:15:45 PM PDT 24
Peak memory 218756 kb
Host smart-3c67aa29-38a6-4198-a304-116aca24159a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897717625 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.1897717625
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.1582147036
Short name T396
Test name
Test status
Simulation time 88734328 ps
CPU time 0.93 seconds
Started Jul 15 07:14:08 PM PDT 24
Finished Jul 15 07:15:51 PM PDT 24
Peak memory 215288 kb
Host smart-c9c1fd75-18da-4d71-8cb6-c9efefc3f284
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582147036 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.1582147036
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.2772494550
Short name T163
Test name
Test status
Simulation time 10980616 ps
CPU time 0.87 seconds
Started Jul 15 07:14:07 PM PDT 24
Finished Jul 15 07:15:57 PM PDT 24
Peak memory 215764 kb
Host smart-943113fc-9685-486b-baee-9047fcaab662
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772494550 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.2772494550
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.4248119907
Short name T142
Test name
Test status
Simulation time 29000580 ps
CPU time 1.01 seconds
Started Jul 15 07:14:07 PM PDT 24
Finished Jul 15 07:15:52 PM PDT 24
Peak memory 218732 kb
Host smart-621f3ab7-1f95-4d57-8a87-98f99ff980f8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248119907 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.4248119907
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.367346326
Short name T199
Test name
Test status
Simulation time 25926046 ps
CPU time 1.02 seconds
Started Jul 15 07:14:08 PM PDT 24
Finished Jul 15 07:15:51 PM PDT 24
Peak memory 229732 kb
Host smart-a4b4bc21-203f-4a17-9484-e9705b5bab3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367346326 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.367346326
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.1621292724
Short name T358
Test name
Test status
Simulation time 44992577 ps
CPU time 1.1 seconds
Started Jul 15 07:13:58 PM PDT 24
Finished Jul 15 07:15:42 PM PDT 24
Peak memory 220340 kb
Host smart-bed43684-7a82-4b8f-ab43-79cb5eef67bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621292724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.1621292724
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.3500994591
Short name T401
Test name
Test status
Simulation time 25508976 ps
CPU time 1.08 seconds
Started Jul 15 07:14:00 PM PDT 24
Finished Jul 15 07:15:45 PM PDT 24
Peak memory 224340 kb
Host smart-d684aec2-2bad-4d8e-a85f-6a7a89b33dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500994591 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3500994591
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.1770428958
Short name T62
Test name
Test status
Simulation time 89121649 ps
CPU time 0.96 seconds
Started Jul 15 07:13:59 PM PDT 24
Finished Jul 15 07:15:44 PM PDT 24
Peak memory 215556 kb
Host smart-5a6885fc-454a-42c6-998c-8455aa378aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770428958 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.1770428958
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.3951719985
Short name T513
Test name
Test status
Simulation time 314012615 ps
CPU time 6.11 seconds
Started Jul 15 07:14:03 PM PDT 24
Finished Jul 15 07:15:50 PM PDT 24
Peak memory 220428 kb
Host smart-22d0422f-2342-4c00-9b6f-c6fdda484549
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951719985 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.3951719985
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.907926123
Short name T955
Test name
Test status
Simulation time 288949626717 ps
CPU time 1773.08 seconds
Started Jul 15 07:14:02 PM PDT 24
Finished Jul 15 07:45:17 PM PDT 24
Peak memory 227588 kb
Host smart-2bf497e3-c626-4820-8685-39d844e53484
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907926123 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.907926123
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.2809992397
Short name T720
Test name
Test status
Simulation time 58521502 ps
CPU time 1.13 seconds
Started Jul 15 07:14:07 PM PDT 24
Finished Jul 15 07:15:52 PM PDT 24
Peak memory 219544 kb
Host smart-02ce4f70-6a6c-4c1a-91b7-3b4d748437da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809992397 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.2809992397
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.4259287407
Short name T353
Test name
Test status
Simulation time 48039878 ps
CPU time 0.77 seconds
Started Jul 15 07:14:09 PM PDT 24
Finished Jul 15 07:15:52 PM PDT 24
Peak memory 207084 kb
Host smart-6ec87847-8625-4346-8338-0eab909b73a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259287407 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.4259287407
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.3915746450
Short name T787
Test name
Test status
Simulation time 38177428 ps
CPU time 0.85 seconds
Started Jul 15 07:14:07 PM PDT 24
Finished Jul 15 07:15:50 PM PDT 24
Peak memory 216616 kb
Host smart-86da03d7-cbb1-4aa8-a0e1-772b88d9efdd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915746450 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.3915746450
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_err.449955454
Short name T486
Test name
Test status
Simulation time 32401052 ps
CPU time 0.91 seconds
Started Jul 15 07:14:10 PM PDT 24
Finished Jul 15 07:15:53 PM PDT 24
Peak memory 218668 kb
Host smart-703300ba-e432-49f6-a172-3c8e2baeb2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449955454 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.449955454
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.3522111792
Short name T367
Test name
Test status
Simulation time 53925203 ps
CPU time 1.71 seconds
Started Jul 15 07:14:10 PM PDT 24
Finished Jul 15 07:15:54 PM PDT 24
Peak memory 218748 kb
Host smart-7d3f4ca5-3a64-4890-9788-1d240e4e6b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522111792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.3522111792
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.905253913
Short name T56
Test name
Test status
Simulation time 20909691 ps
CPU time 1.2 seconds
Started Jul 15 07:14:09 PM PDT 24
Finished Jul 15 07:15:52 PM PDT 24
Peak memory 224160 kb
Host smart-cab642f1-001d-4279-8e1b-ab464e124f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905253913 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.905253913
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.4111138766
Short name T864
Test name
Test status
Simulation time 19703194 ps
CPU time 0.89 seconds
Started Jul 15 07:14:07 PM PDT 24
Finished Jul 15 07:15:57 PM PDT 24
Peak memory 215588 kb
Host smart-8db34b84-f158-4ba8-ab03-fd0a5b55eb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111138766 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.4111138766
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3069975220
Short name T927
Test name
Test status
Simulation time 486896714 ps
CPU time 2.96 seconds
Started Jul 15 07:14:07 PM PDT 24
Finished Jul 15 07:15:54 PM PDT 24
Peak memory 215640 kb
Host smart-4cec4b81-8571-4ed2-826d-200d6ee9173c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069975220 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3069975220
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.389075731
Short name T42
Test name
Test status
Simulation time 182388625489 ps
CPU time 1043.77 seconds
Started Jul 15 07:14:08 PM PDT 24
Finished Jul 15 07:33:14 PM PDT 24
Peak memory 221556 kb
Host smart-2382c358-60e3-4b37-bdb2-b130f2d304fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389075731 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.389075731
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert_test.1625234502
Short name T352
Test name
Test status
Simulation time 17851326 ps
CPU time 1.02 seconds
Started Jul 15 07:14:07 PM PDT 24
Finished Jul 15 07:15:50 PM PDT 24
Peak memory 215476 kb
Host smart-b9f70180-84a4-40d5-8850-d0e3fa7808d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625234502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1625234502
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.391096116
Short name T914
Test name
Test status
Simulation time 29197486 ps
CPU time 0.82 seconds
Started Jul 15 07:14:17 PM PDT 24
Finished Jul 15 07:15:58 PM PDT 24
Peak memory 216256 kb
Host smart-94caa77b-8f2f-4881-a8d1-eb33f6567be2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391096116 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.391096116
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2284252930
Short name T150
Test name
Test status
Simulation time 72003190 ps
CPU time 1.24 seconds
Started Jul 15 07:14:08 PM PDT 24
Finished Jul 15 07:15:52 PM PDT 24
Peak memory 217112 kb
Host smart-6d232b6f-9e22-484d-8114-b5326d33db55
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284252930 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2284252930
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.3922996879
Short name T516
Test name
Test status
Simulation time 21027727 ps
CPU time 0.9 seconds
Started Jul 15 07:14:07 PM PDT 24
Finished Jul 15 07:15:57 PM PDT 24
Peak memory 218924 kb
Host smart-d945ca49-f32c-4daa-a55b-3699bc659937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922996879 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.3922996879
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.3641264538
Short name T963
Test name
Test status
Simulation time 58840272 ps
CPU time 1.13 seconds
Started Jul 15 07:14:07 PM PDT 24
Finished Jul 15 07:15:52 PM PDT 24
Peak memory 219004 kb
Host smart-26ecc7c4-69e7-4a57-8a9f-de0fa0872697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641264538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.3641264538
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.2423259586
Short name T413
Test name
Test status
Simulation time 22597061 ps
CPU time 1.06 seconds
Started Jul 15 07:14:07 PM PDT 24
Finished Jul 15 07:15:52 PM PDT 24
Peak memory 215856 kb
Host smart-0e5f91d4-266c-4b24-a3a0-ac6c5ea010cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423259586 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.2423259586
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.3818679244
Short name T424
Test name
Test status
Simulation time 25930682 ps
CPU time 0.95 seconds
Started Jul 15 07:14:09 PM PDT 24
Finished Jul 15 07:15:52 PM PDT 24
Peak memory 215536 kb
Host smart-51bc9fda-dad2-447a-b63b-923648b55762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818679244 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.3818679244
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.1400270130
Short name T639
Test name
Test status
Simulation time 359350280 ps
CPU time 4.19 seconds
Started Jul 15 07:14:08 PM PDT 24
Finished Jul 15 07:15:55 PM PDT 24
Peak memory 217660 kb
Host smart-ae3cff60-1b2e-4016-9ca5-408994589642
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400270130 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1400270130
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.3534205865
Short name T569
Test name
Test status
Simulation time 23382512118 ps
CPU time 516.79 seconds
Started Jul 15 07:14:09 PM PDT 24
Finished Jul 15 07:24:28 PM PDT 24
Peak memory 218440 kb
Host smart-7693d280-424a-4195-b428-8e31dca24bad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534205865 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.3534205865
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.2643297500
Short name T760
Test name
Test status
Simulation time 48683767 ps
CPU time 1.24 seconds
Started Jul 15 07:14:13 PM PDT 24
Finished Jul 15 07:15:54 PM PDT 24
Peak memory 218900 kb
Host smart-3bfc5563-e5bf-45d4-93c8-35049952dcaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643297500 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.2643297500
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.254554614
Short name T607
Test name
Test status
Simulation time 48315255 ps
CPU time 0.88 seconds
Started Jul 15 07:14:13 PM PDT 24
Finished Jul 15 07:15:53 PM PDT 24
Peak memory 207016 kb
Host smart-0e911f20-4311-4f15-9af3-1861c33e5d8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254554614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.254554614
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.4097952611
Short name T483
Test name
Test status
Simulation time 34383507 ps
CPU time 0.86 seconds
Started Jul 15 07:14:14 PM PDT 24
Finished Jul 15 07:15:53 PM PDT 24
Peak memory 215668 kb
Host smart-131fc023-7794-475e-b035-cccc964be1b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097952611 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.4097952611
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.2635281777
Short name T657
Test name
Test status
Simulation time 62231770 ps
CPU time 1.16 seconds
Started Jul 15 07:14:13 PM PDT 24
Finished Jul 15 07:15:54 PM PDT 24
Peak memory 217252 kb
Host smart-74903e6f-7235-480d-a2d8-0720b295e452
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635281777 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.2635281777
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.3011331388
Short name T466
Test name
Test status
Simulation time 33001064 ps
CPU time 1.34 seconds
Started Jul 15 07:14:12 PM PDT 24
Finished Jul 15 07:15:54 PM PDT 24
Peak memory 220076 kb
Host smart-38bffda2-2c12-4421-bf2a-69fb4e3f7460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011331388 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.3011331388
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.2490680438
Short name T459
Test name
Test status
Simulation time 80440447 ps
CPU time 1.14 seconds
Started Jul 15 07:14:12 PM PDT 24
Finished Jul 15 07:15:53 PM PDT 24
Peak memory 219312 kb
Host smart-f93b2719-28a5-47b9-8cca-d0fb73bf1381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490680438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.2490680438
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.551644116
Short name T934
Test name
Test status
Simulation time 24176492 ps
CPU time 0.89 seconds
Started Jul 15 07:14:14 PM PDT 24
Finished Jul 15 07:15:55 PM PDT 24
Peak memory 216008 kb
Host smart-fce70755-522b-470c-a9da-ff642c77241b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551644116 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.551644116
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.247539669
Short name T695
Test name
Test status
Simulation time 60128372 ps
CPU time 0.88 seconds
Started Jul 15 07:14:08 PM PDT 24
Finished Jul 15 07:15:52 PM PDT 24
Peak memory 215556 kb
Host smart-7df26dfd-1bb1-403d-a370-389a58b2c01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247539669 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.247539669
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.2749801069
Short name T333
Test name
Test status
Simulation time 63582492 ps
CPU time 1.24 seconds
Started Jul 15 07:14:13 PM PDT 24
Finished Jul 15 07:15:54 PM PDT 24
Peak memory 217548 kb
Host smart-4832dc43-7774-423c-9c86-856a5ccdae96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749801069 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2749801069
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.396028945
Short name T479
Test name
Test status
Simulation time 81808878562 ps
CPU time 1000.15 seconds
Started Jul 15 07:14:13 PM PDT 24
Finished Jul 15 07:32:33 PM PDT 24
Peak memory 224224 kb
Host smart-4b8f8dfb-896b-40d9-b3b3-9d249b665069
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396028945 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.396028945
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.4071370811
Short name T229
Test name
Test status
Simulation time 25507264 ps
CPU time 1.27 seconds
Started Jul 15 07:14:10 PM PDT 24
Finished Jul 15 07:15:53 PM PDT 24
Peak memory 219700 kb
Host smart-0d17cb1a-56aa-4f13-b3e6-c028945cc51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071370811 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.4071370811
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.384790089
Short name T845
Test name
Test status
Simulation time 27654857 ps
CPU time 0.86 seconds
Started Jul 15 07:14:17 PM PDT 24
Finished Jul 15 07:15:58 PM PDT 24
Peak memory 207084 kb
Host smart-911b43cb-228d-42fa-a9b8-f4defaf5ee55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384790089 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.384790089
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.4088431118
Short name T191
Test name
Test status
Simulation time 33729763 ps
CPU time 0.79 seconds
Started Jul 15 07:14:12 PM PDT 24
Finished Jul 15 07:15:53 PM PDT 24
Peak memory 216524 kb
Host smart-896ce985-f223-41a1-aeb8-25fe5bbec1c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088431118 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.4088431118
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.749268443
Short name T888
Test name
Test status
Simulation time 381379830 ps
CPU time 1.18 seconds
Started Jul 15 07:14:13 PM PDT 24
Finished Jul 15 07:15:54 PM PDT 24
Peak memory 217092 kb
Host smart-bf1f85e1-5a0b-44c9-816a-07f8dcd986d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749268443 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_di
sable_auto_req_mode.749268443
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.2783345696
Short name T677
Test name
Test status
Simulation time 20577971 ps
CPU time 1.12 seconds
Started Jul 15 07:14:17 PM PDT 24
Finished Jul 15 07:15:58 PM PDT 24
Peak memory 219996 kb
Host smart-10d51439-f1be-4e64-a650-c23d0c47c577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783345696 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.2783345696
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.4168546662
Short name T500
Test name
Test status
Simulation time 80706538 ps
CPU time 1.46 seconds
Started Jul 15 07:14:11 PM PDT 24
Finished Jul 15 07:15:54 PM PDT 24
Peak memory 217540 kb
Host smart-2f0f116e-9ea5-4cbe-b322-0145a32d88bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168546662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.4168546662
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.2428427661
Short name T990
Test name
Test status
Simulation time 21225738 ps
CPU time 1.24 seconds
Started Jul 15 07:14:13 PM PDT 24
Finished Jul 15 07:15:54 PM PDT 24
Peak memory 224268 kb
Host smart-7308bf09-c5b4-4f91-8873-5dc62770d1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428427661 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.2428427661
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.3990544878
Short name T709
Test name
Test status
Simulation time 53597785 ps
CPU time 0.88 seconds
Started Jul 15 07:14:12 PM PDT 24
Finished Jul 15 07:15:53 PM PDT 24
Peak memory 215596 kb
Host smart-91ab99c6-dab0-4f71-a033-e1b20dcd4980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990544878 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.3990544878
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.538073242
Short name T543
Test name
Test status
Simulation time 714747416 ps
CPU time 4.72 seconds
Started Jul 15 07:14:13 PM PDT 24
Finished Jul 15 07:15:57 PM PDT 24
Peak memory 217676 kb
Host smart-3b9454d2-63f4-4e5e-bab0-02d01dc338f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538073242 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.538073242
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.2099830176
Short name T441
Test name
Test status
Simulation time 17584182359 ps
CPU time 439.05 seconds
Started Jul 15 07:14:13 PM PDT 24
Finished Jul 15 07:23:12 PM PDT 24
Peak memory 224032 kb
Host smart-77d693ce-bd44-4a90-814e-4271310269c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099830176 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.2099830176
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert_test.4258574602
Short name T403
Test name
Test status
Simulation time 28092353 ps
CPU time 0.91 seconds
Started Jul 15 07:14:21 PM PDT 24
Finished Jul 15 07:15:58 PM PDT 24
Peak memory 206932 kb
Host smart-f9ac3952-1ed5-470f-aa3f-4ad6cfbddbff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258574602 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.4258574602
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.2912712353
Short name T745
Test name
Test status
Simulation time 20879147 ps
CPU time 0.88 seconds
Started Jul 15 07:14:19 PM PDT 24
Finished Jul 15 07:15:58 PM PDT 24
Peak memory 216764 kb
Host smart-cfd35891-073e-4982-af35-1a1a8eea7e52
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912712353 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.2912712353
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_err.2351210487
Short name T670
Test name
Test status
Simulation time 26310481 ps
CPU time 0.96 seconds
Started Jul 15 07:14:20 PM PDT 24
Finished Jul 15 07:15:58 PM PDT 24
Peak memory 219996 kb
Host smart-a5a864b6-1ca1-4837-b55e-4e030dd5ab13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351210487 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2351210487
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.4228747788
Short name T330
Test name
Test status
Simulation time 41935434 ps
CPU time 1.17 seconds
Started Jul 15 07:14:18 PM PDT 24
Finished Jul 15 07:15:58 PM PDT 24
Peak memory 219628 kb
Host smart-abb85a9a-644b-4424-8c4e-5d59bf5f36a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228747788 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.4228747788
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.352549215
Short name T766
Test name
Test status
Simulation time 33947442 ps
CPU time 0.87 seconds
Started Jul 15 07:14:17 PM PDT 24
Finished Jul 15 07:15:58 PM PDT 24
Peak memory 215780 kb
Host smart-6484cdae-3739-4abd-87cf-5f1502118a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352549215 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.352549215
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.2833827573
Short name T380
Test name
Test status
Simulation time 23341191 ps
CPU time 0.95 seconds
Started Jul 15 07:14:18 PM PDT 24
Finished Jul 15 07:15:58 PM PDT 24
Peak memory 215580 kb
Host smart-dc1bab1e-3d59-4cf1-a0f9-1519e86fefb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833827573 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.2833827573
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.3701038506
Short name T538
Test name
Test status
Simulation time 2827347107 ps
CPU time 3.34 seconds
Started Jul 15 07:14:20 PM PDT 24
Finished Jul 15 07:16:01 PM PDT 24
Peak memory 215716 kb
Host smart-b620aa3a-cb05-4c5a-a380-806e51548c60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701038506 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.3701038506
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.3706440079
Short name T970
Test name
Test status
Simulation time 63586859221 ps
CPU time 439.86 seconds
Started Jul 15 07:14:20 PM PDT 24
Finished Jul 15 07:23:17 PM PDT 24
Peak memory 219344 kb
Host smart-8f30a116-bc49-4e83-af45-718a9f54973b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706440079 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.3706440079
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.3740862902
Short name T417
Test name
Test status
Simulation time 35582270 ps
CPU time 1.09 seconds
Started Jul 15 07:14:28 PM PDT 24
Finished Jul 15 07:16:03 PM PDT 24
Peak memory 218976 kb
Host smart-599c12eb-fa28-460c-a549-06801f14fcf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740862902 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3740862902
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.4211458990
Short name T495
Test name
Test status
Simulation time 38309040 ps
CPU time 1.26 seconds
Started Jul 15 07:14:28 PM PDT 24
Finished Jul 15 07:16:03 PM PDT 24
Peak memory 207212 kb
Host smart-d651106c-a801-41cd-8175-cd016801e817
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211458990 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.4211458990
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.4137688593
Short name T506
Test name
Test status
Simulation time 137714572 ps
CPU time 0.81 seconds
Started Jul 15 07:14:25 PM PDT 24
Finished Jul 15 07:16:00 PM PDT 24
Peak memory 215748 kb
Host smart-042c85db-0517-4750-958a-4b17c72f2e77
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137688593 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.4137688593
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.4069009300
Short name T429
Test name
Test status
Simulation time 28994820 ps
CPU time 1.1 seconds
Started Jul 15 07:14:26 PM PDT 24
Finished Jul 15 07:16:02 PM PDT 24
Peak memory 218520 kb
Host smart-3f4ae456-4942-4936-bedd-7adc9dfbb31c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069009300 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.4069009300
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.464407068
Short name T548
Test name
Test status
Simulation time 21584618 ps
CPU time 0.88 seconds
Started Jul 15 07:14:26 PM PDT 24
Finished Jul 15 07:16:02 PM PDT 24
Peak memory 218740 kb
Host smart-445af540-6a4a-4005-a1f2-f92965a1b8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464407068 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.464407068
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.675875876
Short name T611
Test name
Test status
Simulation time 74977168 ps
CPU time 2.67 seconds
Started Jul 15 07:14:20 PM PDT 24
Finished Jul 15 07:16:00 PM PDT 24
Peak memory 218852 kb
Host smart-0d3d2248-649e-4dc7-88e6-78407b6ec223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675875876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.675875876
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.1549055179
Short name T534
Test name
Test status
Simulation time 27206041 ps
CPU time 0.91 seconds
Started Jul 15 07:14:28 PM PDT 24
Finished Jul 15 07:16:03 PM PDT 24
Peak memory 215932 kb
Host smart-f522975d-8914-4266-a2e6-9ec64c7ec0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549055179 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1549055179
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.3014680314
Short name T613
Test name
Test status
Simulation time 22982178 ps
CPU time 0.94 seconds
Started Jul 15 07:14:22 PM PDT 24
Finished Jul 15 07:15:59 PM PDT 24
Peak memory 215592 kb
Host smart-dc1c5f28-5000-46db-bc3d-efa0994e766f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014680314 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.3014680314
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.4039120222
Short name T895
Test name
Test status
Simulation time 491374760 ps
CPU time 3.04 seconds
Started Jul 15 07:14:25 PM PDT 24
Finished Jul 15 07:16:03 PM PDT 24
Peak memory 217636 kb
Host smart-68d8dc93-7f98-4fab-a85a-edf2b72663b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039120222 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.4039120222
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.2647355217
Short name T738
Test name
Test status
Simulation time 117169212613 ps
CPU time 1526.15 seconds
Started Jul 15 07:14:25 PM PDT 24
Finished Jul 15 07:41:27 PM PDT 24
Peak memory 226864 kb
Host smart-3b0df724-6944-426a-acad-c625539f21af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647355217 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.2647355217
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2091836098
Short name T902
Test name
Test status
Simulation time 30982674 ps
CPU time 1.32 seconds
Started Jul 15 07:14:34 PM PDT 24
Finished Jul 15 07:16:08 PM PDT 24
Peak memory 218888 kb
Host smart-394f041f-62e2-424a-82c9-0a49963ec9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091836098 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2091836098
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.1550567819
Short name T644
Test name
Test status
Simulation time 16298666 ps
CPU time 0.96 seconds
Started Jul 15 07:14:32 PM PDT 24
Finished Jul 15 07:16:07 PM PDT 24
Peak memory 207004 kb
Host smart-feaeff56-e49f-4539-bf30-b631ac7331fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550567819 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.1550567819
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.3443831883
Short name T836
Test name
Test status
Simulation time 15483779 ps
CPU time 0.85 seconds
Started Jul 15 07:14:35 PM PDT 24
Finished Jul 15 07:16:07 PM PDT 24
Peak memory 216836 kb
Host smart-b6ac4837-6f6c-4acf-a3d4-95c1b89a5d9e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443831883 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.3443831883
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.1922547621
Short name T965
Test name
Test status
Simulation time 42200865 ps
CPU time 1.35 seconds
Started Jul 15 07:14:31 PM PDT 24
Finished Jul 15 07:16:07 PM PDT 24
Peak memory 217128 kb
Host smart-50eae47c-5799-4d0d-877a-486d43af10ac
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922547621 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.1922547621
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.1788449
Short name T141
Test name
Test status
Simulation time 32603496 ps
CPU time 1.05 seconds
Started Jul 15 07:14:33 PM PDT 24
Finished Jul 15 07:16:07 PM PDT 24
Peak memory 219964 kb
Host smart-d7c6a28a-16ac-4375-a192-ea09b0cf92eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788449 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.1788449
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.3299158160
Short name T503
Test name
Test status
Simulation time 97579514 ps
CPU time 1.33 seconds
Started Jul 15 07:14:27 PM PDT 24
Finished Jul 15 07:16:03 PM PDT 24
Peak memory 218884 kb
Host smart-2f44d743-ce77-4031-85d0-2f54e4e79b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299158160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.3299158160
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.488768081
Short name T652
Test name
Test status
Simulation time 36525473 ps
CPU time 0.85 seconds
Started Jul 15 07:14:33 PM PDT 24
Finished Jul 15 07:16:07 PM PDT 24
Peak memory 215696 kb
Host smart-b9c6915b-0aa1-49d3-b7fb-eebdf8c11cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488768081 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.488768081
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.2337840152
Short name T696
Test name
Test status
Simulation time 16383780 ps
CPU time 0.96 seconds
Started Jul 15 07:14:25 PM PDT 24
Finished Jul 15 07:16:01 PM PDT 24
Peak memory 215588 kb
Host smart-c2db1436-ecce-41fb-9a98-00d7ea036588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337840152 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.2337840152
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.991373814
Short name T838
Test name
Test status
Simulation time 54658720 ps
CPU time 1.59 seconds
Started Jul 15 07:14:28 PM PDT 24
Finished Jul 15 07:16:03 PM PDT 24
Peak memory 215684 kb
Host smart-899e50cf-380f-4f1f-b625-4d65ef511a6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991373814 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.991373814
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.3157710892
Short name T897
Test name
Test status
Simulation time 24737108391 ps
CPU time 393.47 seconds
Started Jul 15 07:14:33 PM PDT 24
Finished Jul 15 07:22:40 PM PDT 24
Peak memory 218348 kb
Host smart-f67e5ba1-33fa-48d1-8da5-1fdc5a990a5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157710892 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.3157710892
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.3533312890
Short name T98
Test name
Test status
Simulation time 328925289 ps
CPU time 1.15 seconds
Started Jul 15 07:13:05 PM PDT 24
Finished Jul 15 07:14:24 PM PDT 24
Peak memory 218876 kb
Host smart-fe9006e1-f411-47dc-b341-be8933d9d26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533312890 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3533312890
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.1765714947
Short name T562
Test name
Test status
Simulation time 36404825 ps
CPU time 0.84 seconds
Started Jul 15 07:13:00 PM PDT 24
Finished Jul 15 07:14:07 PM PDT 24
Peak memory 215244 kb
Host smart-53fe3d51-f6fb-4ab3-a323-fad6b62544eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765714947 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.1765714947
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.345539045
Short name T221
Test name
Test status
Simulation time 41760567 ps
CPU time 0.93 seconds
Started Jul 15 07:13:02 PM PDT 24
Finished Jul 15 07:14:15 PM PDT 24
Peak memory 216564 kb
Host smart-418a727a-a1df-4d53-ac98-1d86340f22f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345539045 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.345539045
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.2900314276
Short name T437
Test name
Test status
Simulation time 32165992 ps
CPU time 1.21 seconds
Started Jul 15 07:13:02 PM PDT 24
Finished Jul 15 07:14:17 PM PDT 24
Peak memory 218792 kb
Host smart-84094ea1-7bbb-435c-97df-2f70c2f6710c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900314276 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.2900314276
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.3255499453
Short name T115
Test name
Test status
Simulation time 24740759 ps
CPU time 1.09 seconds
Started Jul 15 07:13:04 PM PDT 24
Finished Jul 15 07:14:17 PM PDT 24
Peak memory 220120 kb
Host smart-92b9042d-ac2d-462a-8454-41068bd081d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255499453 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.3255499453
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.1616831942
Short name T641
Test name
Test status
Simulation time 73051711 ps
CPU time 1.19 seconds
Started Jul 15 07:13:06 PM PDT 24
Finished Jul 15 07:14:25 PM PDT 24
Peak memory 217600 kb
Host smart-af2ca1d0-d469-4e0b-b504-178d54c8bdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616831942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1616831942
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.4250570398
Short name T841
Test name
Test status
Simulation time 29039872 ps
CPU time 1.09 seconds
Started Jul 15 07:12:59 PM PDT 24
Finished Jul 15 07:14:00 PM PDT 24
Peak memory 224300 kb
Host smart-6fcc0da3-17bb-442e-b6b5-5e7324a91624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250570398 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.4250570398
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_sec_cm.3267667557
Short name T19
Test name
Test status
Simulation time 436648173 ps
CPU time 4.04 seconds
Started Jul 15 07:13:01 PM PDT 24
Finished Jul 15 07:14:11 PM PDT 24
Peak memory 235620 kb
Host smart-e14d3939-fa52-4987-8755-67682b686768
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267667557 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.3267667557
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.3810313365
Short name T865
Test name
Test status
Simulation time 21772474 ps
CPU time 0.89 seconds
Started Jul 15 07:12:59 PM PDT 24
Finished Jul 15 07:14:06 PM PDT 24
Peak memory 215540 kb
Host smart-285336e7-3cde-4979-a37b-4b255313c717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810313365 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3810313365
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.793648368
Short name T75
Test name
Test status
Simulation time 122934552 ps
CPU time 1.2 seconds
Started Jul 15 07:13:00 PM PDT 24
Finished Jul 15 07:14:08 PM PDT 24
Peak memory 217644 kb
Host smart-33da5b0a-3f2b-44cf-a2c0-6877084de2a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793648368 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.793648368
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.3893455534
Short name T219
Test name
Test status
Simulation time 33586625669 ps
CPU time 822.44 seconds
Started Jul 15 07:12:59 PM PDT 24
Finished Jul 15 07:27:48 PM PDT 24
Peak memory 224052 kb
Host smart-3e46625e-9064-45b5-bd3f-b47e6744c656
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893455534 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.3893455534
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.52154402
Short name T170
Test name
Test status
Simulation time 25899331 ps
CPU time 1.19 seconds
Started Jul 15 07:14:30 PM PDT 24
Finished Jul 15 07:16:07 PM PDT 24
Peak memory 219972 kb
Host smart-7196e85f-50d2-4ecc-b26f-f8e6ae696cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52154402 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.52154402
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.1679484150
Short name T339
Test name
Test status
Simulation time 13895775 ps
CPU time 0.88 seconds
Started Jul 15 07:14:30 PM PDT 24
Finished Jul 15 07:16:07 PM PDT 24
Peak memory 207000 kb
Host smart-ab34a3e7-c4fe-48c5-b047-180405c2946b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679484150 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1679484150
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.1642625940
Short name T953
Test name
Test status
Simulation time 17079785 ps
CPU time 0.84 seconds
Started Jul 15 07:14:32 PM PDT 24
Finished Jul 15 07:16:07 PM PDT 24
Peak memory 216260 kb
Host smart-7ee42128-4253-42c6-aa86-aa1d32ab0a4f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642625940 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1642625940
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.3142313008
Short name T156
Test name
Test status
Simulation time 86523524 ps
CPU time 1.06 seconds
Started Jul 15 07:14:30 PM PDT 24
Finished Jul 15 07:16:06 PM PDT 24
Peak memory 217172 kb
Host smart-e8b1dabb-cd2c-466f-ac22-00b888e33aa5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142313008 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.3142313008
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.1973826494
Short name T776
Test name
Test status
Simulation time 38895960 ps
CPU time 1.12 seconds
Started Jul 15 07:14:32 PM PDT 24
Finished Jul 15 07:16:07 PM PDT 24
Peak memory 220880 kb
Host smart-7f4f82d1-601c-4fae-a6be-69fe1d31d103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973826494 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.1973826494
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.4050539147
Short name T679
Test name
Test status
Simulation time 106755106 ps
CPU time 1.33 seconds
Started Jul 15 07:14:32 PM PDT 24
Finished Jul 15 07:16:08 PM PDT 24
Peak memory 219260 kb
Host smart-e60ddae8-cd54-49b4-ac87-bc4a2af18540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050539147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.4050539147
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.479627663
Short name T830
Test name
Test status
Simulation time 38683020 ps
CPU time 0.89 seconds
Started Jul 15 07:14:32 PM PDT 24
Finished Jul 15 07:16:07 PM PDT 24
Peak memory 215656 kb
Host smart-b5f78d43-a149-44c2-9d95-baf394a5f42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479627663 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.479627663
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.2588065322
Short name T894
Test name
Test status
Simulation time 19119963 ps
CPU time 1.04 seconds
Started Jul 15 07:14:31 PM PDT 24
Finished Jul 15 07:16:07 PM PDT 24
Peak memory 215576 kb
Host smart-ea935b42-27dc-42e6-96ef-3efbc697c67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588065322 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.2588065322
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.1571003241
Short name T768
Test name
Test status
Simulation time 145627661 ps
CPU time 1.99 seconds
Started Jul 15 07:14:33 PM PDT 24
Finished Jul 15 07:16:08 PM PDT 24
Peak memory 217568 kb
Host smart-1eb4c697-39d4-4fae-94b6-3e4b644f8293
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571003241 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.1571003241
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.241638603
Short name T481
Test name
Test status
Simulation time 85459290059 ps
CPU time 999.57 seconds
Started Jul 15 07:14:33 PM PDT 24
Finished Jul 15 07:32:46 PM PDT 24
Peak memory 224044 kb
Host smart-0f169628-a30c-4ddf-a3a1-1e2f9a9fb6eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241638603 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.241638603
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.2036839930
Short name T386
Test name
Test status
Simulation time 29852508 ps
CPU time 1.23 seconds
Started Jul 15 07:14:33 PM PDT 24
Finished Jul 15 07:16:07 PM PDT 24
Peak memory 221100 kb
Host smart-e837e397-2fe0-4cf4-a5ee-95602285f202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036839930 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.2036839930
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.3959925285
Short name T431
Test name
Test status
Simulation time 47051146 ps
CPU time 0.85 seconds
Started Jul 15 07:14:39 PM PDT 24
Finished Jul 15 07:16:08 PM PDT 24
Peak memory 215456 kb
Host smart-55376b0e-97f3-4b6f-9418-4bf5a9b71cd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959925285 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.3959925285
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.1752681508
Short name T223
Test name
Test status
Simulation time 33600466 ps
CPU time 0.89 seconds
Started Jul 15 07:14:40 PM PDT 24
Finished Jul 15 07:16:08 PM PDT 24
Peak memory 216692 kb
Host smart-e075e8ef-20ba-47a1-a603-840408e86611
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752681508 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.1752681508
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.1595935432
Short name T717
Test name
Test status
Simulation time 54531550 ps
CPU time 1.13 seconds
Started Jul 15 07:14:39 PM PDT 24
Finished Jul 15 07:16:08 PM PDT 24
Peak memory 218628 kb
Host smart-86f76f50-4b29-4a9d-b236-775833a76763
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595935432 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.1595935432
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.3589546879
Short name T154
Test name
Test status
Simulation time 52514920 ps
CPU time 1.02 seconds
Started Jul 15 07:14:39 PM PDT 24
Finished Jul 15 07:16:08 PM PDT 24
Peak memory 220896 kb
Host smart-7d0c7410-b1d1-4d24-97b5-f683ec382785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589546879 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3589546879
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.1300803658
Short name T658
Test name
Test status
Simulation time 116069129 ps
CPU time 1 seconds
Started Jul 15 07:14:30 PM PDT 24
Finished Jul 15 07:16:07 PM PDT 24
Peak memory 217724 kb
Host smart-dc3fa302-05da-4bf7-b82c-1e6c69637515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300803658 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.1300803658
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.284002108
Short name T626
Test name
Test status
Simulation time 22856585 ps
CPU time 1.08 seconds
Started Jul 15 07:14:32 PM PDT 24
Finished Jul 15 07:16:07 PM PDT 24
Peak memory 215700 kb
Host smart-4d119cd9-d2c8-4264-9b80-611d6f3f7784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284002108 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.284002108
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.3572763313
Short name T49
Test name
Test status
Simulation time 109098971 ps
CPU time 1 seconds
Started Jul 15 07:14:31 PM PDT 24
Finished Jul 15 07:16:06 PM PDT 24
Peak memory 215568 kb
Host smart-00a19a8d-57b0-4eba-9bce-326a86bf8e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572763313 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.3572763313
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.514627391
Short name T610
Test name
Test status
Simulation time 460332431 ps
CPU time 5.05 seconds
Started Jul 15 07:14:32 PM PDT 24
Finished Jul 15 07:16:11 PM PDT 24
Peak memory 217388 kb
Host smart-b3d81555-ebc4-4426-9a1f-aa8fd4044adc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514627391 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.514627391
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.2600271967
Short name T788
Test name
Test status
Simulation time 112716131759 ps
CPU time 611.24 seconds
Started Jul 15 07:14:30 PM PDT 24
Finished Jul 15 07:26:17 PM PDT 24
Peak memory 220140 kb
Host smart-ca0c9d0d-8a67-4a3c-b85d-248493a90fb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600271967 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.2600271967
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.1506857775
Short name T179
Test name
Test status
Simulation time 63700057 ps
CPU time 1.07 seconds
Started Jul 15 07:14:38 PM PDT 24
Finished Jul 15 07:16:08 PM PDT 24
Peak memory 218856 kb
Host smart-f8bb21fa-9e1b-47c7-98bc-d416ad6e2474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506857775 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1506857775
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.4242475358
Short name T2
Test name
Test status
Simulation time 72007573 ps
CPU time 0.84 seconds
Started Jul 15 07:14:40 PM PDT 24
Finished Jul 15 07:16:08 PM PDT 24
Peak memory 206984 kb
Host smart-7f2b5cba-644d-4540-bd0a-9c77799e9cb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242475358 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.4242475358
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.3366504543
Short name T102
Test name
Test status
Simulation time 21384272 ps
CPU time 0.89 seconds
Started Jul 15 07:14:38 PM PDT 24
Finished Jul 15 07:16:08 PM PDT 24
Peak memory 216548 kb
Host smart-8007aa55-7f47-436e-beb3-09316cb0dc20
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366504543 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.3366504543
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.2903648543
Short name T669
Test name
Test status
Simulation time 46071771 ps
CPU time 1.07 seconds
Started Jul 15 07:14:38 PM PDT 24
Finished Jul 15 07:16:08 PM PDT 24
Peak memory 215996 kb
Host smart-eec07848-1faa-4063-aaef-8a6ae1457b8d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903648543 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.2903648543
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.919355080
Short name T146
Test name
Test status
Simulation time 27574103 ps
CPU time 1.34 seconds
Started Jul 15 07:14:39 PM PDT 24
Finished Jul 15 07:16:08 PM PDT 24
Peak memory 232476 kb
Host smart-f0d564c4-2d3c-4f17-b89b-e211f074281a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919355080 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.919355080
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.1120031263
Short name T908
Test name
Test status
Simulation time 28850669 ps
CPU time 1.25 seconds
Started Jul 15 07:14:37 PM PDT 24
Finished Jul 15 07:16:08 PM PDT 24
Peak memory 217448 kb
Host smart-cb09030a-f21e-4786-b37a-d454a0a19de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120031263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.1120031263
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.826413558
Short name T681
Test name
Test status
Simulation time 23059593 ps
CPU time 1.05 seconds
Started Jul 15 07:14:39 PM PDT 24
Finished Jul 15 07:16:08 PM PDT 24
Peak memory 215780 kb
Host smart-6c28003c-b266-4f25-b41b-2f575179ff49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826413558 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.826413558
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.4048612554
Short name T971
Test name
Test status
Simulation time 15286101 ps
CPU time 0.95 seconds
Started Jul 15 07:14:38 PM PDT 24
Finished Jul 15 07:16:08 PM PDT 24
Peak memory 215596 kb
Host smart-e53073a4-482a-4316-a26d-3e80273d3641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048612554 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.4048612554
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.1995619437
Short name T376
Test name
Test status
Simulation time 354414739 ps
CPU time 5.06 seconds
Started Jul 15 07:14:42 PM PDT 24
Finished Jul 15 07:16:13 PM PDT 24
Peak memory 218844 kb
Host smart-d2825339-2a23-4163-a6bc-95671e95d5d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995619437 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1995619437
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.2497187900
Short name T426
Test name
Test status
Simulation time 17484966943 ps
CPU time 417 seconds
Started Jul 15 07:14:37 PM PDT 24
Finished Jul 15 07:23:04 PM PDT 24
Peak memory 224096 kb
Host smart-62421882-8cbf-4a56-95dc-0a38b4dc68de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497187900 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.2497187900
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.3159640027
Short name T232
Test name
Test status
Simulation time 24211364 ps
CPU time 1.21 seconds
Started Jul 15 07:14:40 PM PDT 24
Finished Jul 15 07:16:09 PM PDT 24
Peak memory 220156 kb
Host smart-1997e6cb-8eba-46c2-a6b3-2bf942d0b8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159640027 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.3159640027
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.3353345573
Short name T948
Test name
Test status
Simulation time 20909439 ps
CPU time 0.95 seconds
Started Jul 15 07:14:51 PM PDT 24
Finished Jul 15 07:16:19 PM PDT 24
Peak memory 207000 kb
Host smart-221ce2d7-0f3e-4d38-b524-b39a7990e2dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353345573 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.3353345573
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.3525282812
Short name T203
Test name
Test status
Simulation time 35883775 ps
CPU time 0.84 seconds
Started Jul 15 07:14:39 PM PDT 24
Finished Jul 15 07:16:08 PM PDT 24
Peak memory 216620 kb
Host smart-3fe0b3ec-6f16-4504-91b9-4880b2a5dcc2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525282812 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.3525282812
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.2705055345
Short name T379
Test name
Test status
Simulation time 30535926 ps
CPU time 1.12 seconds
Started Jul 15 07:14:59 PM PDT 24
Finished Jul 15 07:16:23 PM PDT 24
Peak memory 217260 kb
Host smart-fa139a13-e3a1-47f9-8a3e-97207a05fec5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705055345 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.2705055345
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.128451086
Short name T531
Test name
Test status
Simulation time 33306616 ps
CPU time 0.85 seconds
Started Jul 15 07:14:40 PM PDT 24
Finished Jul 15 07:16:08 PM PDT 24
Peak memory 218488 kb
Host smart-e7d42bb4-4a27-4818-b7d0-0add1d712a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128451086 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.128451086
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.3418113361
Short name T554
Test name
Test status
Simulation time 83114749 ps
CPU time 1.13 seconds
Started Jul 15 07:14:40 PM PDT 24
Finished Jul 15 07:16:09 PM PDT 24
Peak memory 217732 kb
Host smart-d9ffa48e-2673-484e-a4b1-8eeea0a2b558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418113361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.3418113361
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.645559896
Short name T580
Test name
Test status
Simulation time 21718267 ps
CPU time 1.08 seconds
Started Jul 15 07:14:41 PM PDT 24
Finished Jul 15 07:16:09 PM PDT 24
Peak memory 215720 kb
Host smart-414568ff-20b6-48ac-b5ad-2e96ce287711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645559896 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.645559896
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.2719885575
Short name T568
Test name
Test status
Simulation time 50400404 ps
CPU time 0.93 seconds
Started Jul 15 07:14:41 PM PDT 24
Finished Jul 15 07:16:08 PM PDT 24
Peak memory 215616 kb
Host smart-3c796f02-4bbd-4b87-80c8-2262d0f48a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719885575 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2719885575
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.602634365
Short name T248
Test name
Test status
Simulation time 240620008 ps
CPU time 4.72 seconds
Started Jul 15 07:14:41 PM PDT 24
Finished Jul 15 07:16:12 PM PDT 24
Peak memory 215600 kb
Host smart-b7493338-b61e-40e3-ba7d-23a03c4e8bbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602634365 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.602634365
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.1660146292
Short name T656
Test name
Test status
Simulation time 104176925527 ps
CPU time 1346.2 seconds
Started Jul 15 07:14:39 PM PDT 24
Finished Jul 15 07:38:33 PM PDT 24
Peak memory 224680 kb
Host smart-4261cc98-6cf1-49cf-b528-786275a36794
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660146292 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.1660146292
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert_test.1089381592
Short name T629
Test name
Test status
Simulation time 45007273 ps
CPU time 0.87 seconds
Started Jul 15 07:14:47 PM PDT 24
Finished Jul 15 07:16:14 PM PDT 24
Peak memory 207076 kb
Host smart-c4ce0151-062f-4df0-ba03-19d926852561
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089381592 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.1089381592
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.742303827
Short name T131
Test name
Test status
Simulation time 81391033 ps
CPU time 0.98 seconds
Started Jul 15 07:14:59 PM PDT 24
Finished Jul 15 07:16:22 PM PDT 24
Peak memory 217244 kb
Host smart-cfa06c96-b02a-4aee-ad93-7f0e7698779e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742303827 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_di
sable_auto_req_mode.742303827
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.2070836996
Short name T438
Test name
Test status
Simulation time 19520248 ps
CPU time 1.08 seconds
Started Jul 15 07:14:59 PM PDT 24
Finished Jul 15 07:16:23 PM PDT 24
Peak memory 218844 kb
Host smart-c1798c8f-3741-4abc-a76c-36489d6aadde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070836996 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.2070836996
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.2912202108
Short name T821
Test name
Test status
Simulation time 49108723 ps
CPU time 1.86 seconds
Started Jul 15 07:14:44 PM PDT 24
Finished Jul 15 07:16:15 PM PDT 24
Peak memory 218856 kb
Host smart-df709a11-e6e3-4b55-ae19-69ae1583da02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912202108 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.2912202108
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.3391687839
Short name T523
Test name
Test status
Simulation time 45911375 ps
CPU time 0.98 seconds
Started Jul 15 07:14:46 PM PDT 24
Finished Jul 15 07:16:12 PM PDT 24
Peak memory 224312 kb
Host smart-f587cc1f-eaa4-49c9-95fd-93210566dd3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391687839 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.3391687839
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.876103379
Short name T556
Test name
Test status
Simulation time 28147567 ps
CPU time 0.92 seconds
Started Jul 15 07:14:59 PM PDT 24
Finished Jul 15 07:16:22 PM PDT 24
Peak memory 215576 kb
Host smart-b62f4c2b-8805-495d-8468-77aac86b27cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876103379 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.876103379
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.1625924441
Short name T354
Test name
Test status
Simulation time 98188700 ps
CPU time 1.71 seconds
Started Jul 15 07:14:44 PM PDT 24
Finished Jul 15 07:16:15 PM PDT 24
Peak memory 218804 kb
Host smart-5d8b09fd-dd14-4c2e-85f6-96f901552996
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625924441 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1625924441
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2931122779
Short name T911
Test name
Test status
Simulation time 45798775941 ps
CPU time 363.03 seconds
Started Jul 15 07:14:46 PM PDT 24
Finished Jul 15 07:22:14 PM PDT 24
Peak memory 218784 kb
Host smart-1d099450-3d24-4cf1-92dd-60823e622f1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931122779 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2931122779
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert_test.3061587312
Short name T978
Test name
Test status
Simulation time 61771806 ps
CPU time 0.84 seconds
Started Jul 15 07:14:59 PM PDT 24
Finished Jul 15 07:16:22 PM PDT 24
Peak memory 206808 kb
Host smart-666bd126-f2f7-473b-8e30-b4f636387b40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061587312 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3061587312
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.2960979942
Short name T779
Test name
Test status
Simulation time 11649863 ps
CPU time 0.85 seconds
Started Jul 15 07:14:45 PM PDT 24
Finished Jul 15 07:16:11 PM PDT 24
Peak memory 216620 kb
Host smart-b47941b7-51a6-4260-af16-a0ae8050fe42
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960979942 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2960979942
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.1449730300
Short name T588
Test name
Test status
Simulation time 37999869 ps
CPU time 0.97 seconds
Started Jul 15 07:14:46 PM PDT 24
Finished Jul 15 07:16:11 PM PDT 24
Peak memory 218528 kb
Host smart-463cab90-4dfa-47d6-ba6a-262bc8a5a3cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449730300 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.1449730300
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.3175778894
Short name T211
Test name
Test status
Simulation time 36111406 ps
CPU time 0.91 seconds
Started Jul 15 07:14:58 PM PDT 24
Finished Jul 15 07:16:19 PM PDT 24
Peak memory 220192 kb
Host smart-fb2849e2-f733-47e4-84d0-30695ca1f535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175778894 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.3175778894
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.3499143890
Short name T980
Test name
Test status
Simulation time 34870237 ps
CPU time 1.59 seconds
Started Jul 15 07:14:47 PM PDT 24
Finished Jul 15 07:16:15 PM PDT 24
Peak memory 218804 kb
Host smart-2f24bbf1-5126-4b18-aa6f-e2a6f9aaf6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499143890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.3499143890
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.2400639122
Short name T33
Test name
Test status
Simulation time 75618533 ps
CPU time 0.82 seconds
Started Jul 15 07:14:44 PM PDT 24
Finished Jul 15 07:16:14 PM PDT 24
Peak memory 215768 kb
Host smart-ff242626-f450-44c8-84a7-60cfa42f632e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400639122 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.2400639122
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.599262253
Short name T844
Test name
Test status
Simulation time 45755280 ps
CPU time 0.88 seconds
Started Jul 15 07:14:52 PM PDT 24
Finished Jul 15 07:16:17 PM PDT 24
Peak memory 215556 kb
Host smart-54307f50-76fd-40f5-94d2-3349f7cf9e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599262253 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.599262253
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.3387204842
Short name T363
Test name
Test status
Simulation time 228505136 ps
CPU time 2.59 seconds
Started Jul 15 07:14:46 PM PDT 24
Finished Jul 15 07:16:14 PM PDT 24
Peak memory 215520 kb
Host smart-9f1ae9a2-5da1-490d-8733-6a43a0fd4743
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387204842 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.3387204842
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.2222767071
Short name T725
Test name
Test status
Simulation time 67551303396 ps
CPU time 1698.16 seconds
Started Jul 15 07:14:50 PM PDT 24
Finished Jul 15 07:44:36 PM PDT 24
Peak memory 235528 kb
Host smart-e507d37d-43dd-4522-9e1a-253234a17187
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222767071 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.2222767071
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.2515019020
Short name T984
Test name
Test status
Simulation time 109619010 ps
CPU time 1.16 seconds
Started Jul 15 07:14:48 PM PDT 24
Finished Jul 15 07:16:14 PM PDT 24
Peak memory 218924 kb
Host smart-636f907f-f9ab-4bc3-b58b-22d488efc1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515019020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.2515019020
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.308787074
Short name T815
Test name
Test status
Simulation time 47659745 ps
CPU time 0.99 seconds
Started Jul 15 07:14:45 PM PDT 24
Finished Jul 15 07:16:12 PM PDT 24
Peak memory 207024 kb
Host smart-a55e1ce1-255d-46e0-997c-52f6f72c9dbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308787074 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.308787074
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.3261520708
Short name T822
Test name
Test status
Simulation time 19954829 ps
CPU time 0.83 seconds
Started Jul 15 07:14:52 PM PDT 24
Finished Jul 15 07:16:19 PM PDT 24
Peak memory 215688 kb
Host smart-487dd47f-da8e-49ad-96c3-d19994a25f0d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261520708 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.3261520708
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.1998901871
Short name T124
Test name
Test status
Simulation time 34583674 ps
CPU time 1.18 seconds
Started Jul 15 07:14:58 PM PDT 24
Finished Jul 15 07:16:19 PM PDT 24
Peak memory 217292 kb
Host smart-1d56ca58-34d7-4e53-aa0d-090072254abb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998901871 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.1998901871
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.1497052799
Short name T929
Test name
Test status
Simulation time 28656534 ps
CPU time 0.83 seconds
Started Jul 15 07:14:46 PM PDT 24
Finished Jul 15 07:16:12 PM PDT 24
Peak memory 218516 kb
Host smart-484a7d84-3c4a-4aa4-86a7-454a6d0996c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497052799 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1497052799
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1426312254
Short name T313
Test name
Test status
Simulation time 68319785 ps
CPU time 1.23 seconds
Started Jul 15 07:14:52 PM PDT 24
Finished Jul 15 07:16:17 PM PDT 24
Peak memory 220280 kb
Host smart-e7732dc7-4c40-46ce-8392-90fcce5f4133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426312254 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1426312254
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.966367119
Short name T492
Test name
Test status
Simulation time 42486980 ps
CPU time 0.91 seconds
Started Jul 15 07:14:45 PM PDT 24
Finished Jul 15 07:16:11 PM PDT 24
Peak memory 215800 kb
Host smart-0609c4c3-d580-40ff-b059-3ce22fe327a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966367119 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.966367119
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.3435525173
Short name T470
Test name
Test status
Simulation time 15867286 ps
CPU time 0.95 seconds
Started Jul 15 07:14:45 PM PDT 24
Finished Jul 15 07:16:11 PM PDT 24
Peak memory 215536 kb
Host smart-5d85e78f-1822-4dc6-9ca5-9c580b5a61c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435525173 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.3435525173
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.2000172630
Short name T70
Test name
Test status
Simulation time 327666636 ps
CPU time 2.83 seconds
Started Jul 15 07:14:48 PM PDT 24
Finished Jul 15 07:16:16 PM PDT 24
Peak memory 215576 kb
Host smart-6e4e3bf1-9f59-4a26-b8de-f10e0d70d2be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000172630 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2000172630
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.1987438944
Short name T589
Test name
Test status
Simulation time 178942670897 ps
CPU time 1671.26 seconds
Started Jul 15 07:14:58 PM PDT 24
Finished Jul 15 07:44:09 PM PDT 24
Peak memory 228484 kb
Host smart-573a83b1-bcb9-424b-8221-872bc68ad711
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987438944 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.1987438944
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.1934579422
Short name T687
Test name
Test status
Simulation time 255695139 ps
CPU time 1.17 seconds
Started Jul 15 07:14:48 PM PDT 24
Finished Jul 15 07:16:14 PM PDT 24
Peak memory 219576 kb
Host smart-0c2add83-5642-40ec-b8ed-3a7f8ac0ad65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934579422 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.1934579422
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.3638857791
Short name T647
Test name
Test status
Simulation time 32257263 ps
CPU time 0.95 seconds
Started Jul 15 07:14:45 PM PDT 24
Finished Jul 15 07:16:12 PM PDT 24
Peak memory 207060 kb
Host smart-e14ebd78-ee43-453e-9334-76323b436416
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638857791 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.3638857791
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.3991480235
Short name T943
Test name
Test status
Simulation time 25937235 ps
CPU time 0.82 seconds
Started Jul 15 07:14:46 PM PDT 24
Finished Jul 15 07:16:11 PM PDT 24
Peak memory 216684 kb
Host smart-b7552bf4-2d41-4ee6-a278-5eebdf41b155
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991480235 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3991480235
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.2962680436
Short name T812
Test name
Test status
Simulation time 78502488 ps
CPU time 1 seconds
Started Jul 15 07:14:45 PM PDT 24
Finished Jul 15 07:16:11 PM PDT 24
Peak memory 220280 kb
Host smart-cb638e8f-4781-4036-98cf-d355058b4e6a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962680436 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.2962680436
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.950066302
Short name T791
Test name
Test status
Simulation time 24202457 ps
CPU time 0.88 seconds
Started Jul 15 07:14:52 PM PDT 24
Finished Jul 15 07:16:17 PM PDT 24
Peak memory 218444 kb
Host smart-a8e4c715-5ae2-4799-ab1d-57aee1f2c445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950066302 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.950066302
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_intr.1949530860
Short name T922
Test name
Test status
Simulation time 28890243 ps
CPU time 0.94 seconds
Started Jul 15 07:14:59 PM PDT 24
Finished Jul 15 07:16:22 PM PDT 24
Peak memory 215704 kb
Host smart-0c448443-0467-4f1a-9ba7-0e5e007e0196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949530860 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1949530860
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.135573561
Short name T566
Test name
Test status
Simulation time 29889880 ps
CPU time 0.91 seconds
Started Jul 15 07:14:49 PM PDT 24
Finished Jul 15 07:16:18 PM PDT 24
Peak memory 207380 kb
Host smart-1ab3a104-488c-4e38-abc1-4787984d71a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135573561 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.135573561
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.802277914
Short name T803
Test name
Test status
Simulation time 908682149 ps
CPU time 5.74 seconds
Started Jul 15 07:14:50 PM PDT 24
Finished Jul 15 07:16:23 PM PDT 24
Peak memory 217544 kb
Host smart-4608fd42-ad5b-420a-b7d4-5fc208555ccc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802277914 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.802277914
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2625945550
Short name T105
Test name
Test status
Simulation time 74614175751 ps
CPU time 1002.66 seconds
Started Jul 15 07:14:48 PM PDT 24
Finished Jul 15 07:32:56 PM PDT 24
Peak memory 224032 kb
Host smart-85776273-da0a-4231-9ef5-cb15efe0ea34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625945550 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.2625945550
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.2925687863
Short name T378
Test name
Test status
Simulation time 65108292 ps
CPU time 1.06 seconds
Started Jul 15 07:14:55 PM PDT 24
Finished Jul 15 07:16:17 PM PDT 24
Peak memory 221968 kb
Host smart-fc68d656-6a64-409a-b4b2-9c8203d10f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925687863 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.2925687863
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.2014553718
Short name T635
Test name
Test status
Simulation time 14574744 ps
CPU time 0.91 seconds
Started Jul 15 07:14:57 PM PDT 24
Finished Jul 15 07:16:19 PM PDT 24
Peak memory 215200 kb
Host smart-163f56ba-4210-4691-9fce-36243aca979d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014553718 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.2014553718
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.256178549
Short name T469
Test name
Test status
Simulation time 14756988 ps
CPU time 0.86 seconds
Started Jul 15 07:14:57 PM PDT 24
Finished Jul 15 07:16:18 PM PDT 24
Peak memory 216368 kb
Host smart-85f557cd-75fb-4ff7-9600-a7df9eafc928
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256178549 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.256178549
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.386547225
Short name T132
Test name
Test status
Simulation time 35840149 ps
CPU time 1.27 seconds
Started Jul 15 07:14:53 PM PDT 24
Finished Jul 15 07:16:20 PM PDT 24
Peak memory 217328 kb
Host smart-23548243-ee0f-412d-bd5b-28b6f0970e2c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386547225 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_di
sable_auto_req_mode.386547225
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.2963847985
Short name T159
Test name
Test status
Simulation time 73896515 ps
CPU time 0.88 seconds
Started Jul 15 07:14:54 PM PDT 24
Finished Jul 15 07:16:19 PM PDT 24
Peak memory 218688 kb
Host smart-006e1afc-1ddc-419c-9e66-713e403407d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963847985 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.2963847985
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.87233388
Short name T97
Test name
Test status
Simulation time 72567901 ps
CPU time 1.6 seconds
Started Jul 15 07:14:46 PM PDT 24
Finished Jul 15 07:16:13 PM PDT 24
Peak memory 219184 kb
Host smart-6dba3110-f9bc-422e-8c9f-509e29eee2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87233388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.87233388
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.2858403034
Short name T530
Test name
Test status
Simulation time 35353066 ps
CPU time 0.87 seconds
Started Jul 15 07:14:52 PM PDT 24
Finished Jul 15 07:16:17 PM PDT 24
Peak memory 215860 kb
Host smart-48f1d0c8-3047-464c-bee7-00eff9e5f53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858403034 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.2858403034
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.718312106
Short name T759
Test name
Test status
Simulation time 109562289 ps
CPU time 0.91 seconds
Started Jul 15 07:14:44 PM PDT 24
Finished Jul 15 07:16:14 PM PDT 24
Peak memory 215604 kb
Host smart-c8f56f97-0874-4c85-98ba-8a2f5df59580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718312106 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.718312106
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.258923842
Short name T361
Test name
Test status
Simulation time 694974769 ps
CPU time 2.37 seconds
Started Jul 15 07:14:55 PM PDT 24
Finished Jul 15 07:16:21 PM PDT 24
Peak memory 217628 kb
Host smart-da88fe72-782e-422e-90cf-b57495a5652b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258923842 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.258923842
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.888728748
Short name T945
Test name
Test status
Simulation time 25798082549 ps
CPU time 601.23 seconds
Started Jul 15 07:14:57 PM PDT 24
Finished Jul 15 07:26:19 PM PDT 24
Peak memory 218360 kb
Host smart-1e7ce52d-cd21-4f57-af0d-7b66d3e1963c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888728748 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.888728748
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.2311708146
Short name T347
Test name
Test status
Simulation time 30588716 ps
CPU time 1.32 seconds
Started Jul 15 07:14:52 PM PDT 24
Finished Jul 15 07:16:17 PM PDT 24
Peak memory 219128 kb
Host smart-8612ed61-4a96-43fa-a8b8-40562aecac65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311708146 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.2311708146
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.2115783564
Short name T447
Test name
Test status
Simulation time 29735268 ps
CPU time 0.9 seconds
Started Jul 15 07:14:56 PM PDT 24
Finished Jul 15 07:16:18 PM PDT 24
Peak memory 215328 kb
Host smart-ff87e934-af69-4fbb-bcaa-3165744271c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115783564 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.2115783564
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.3331397372
Short name T774
Test name
Test status
Simulation time 10689855 ps
CPU time 0.86 seconds
Started Jul 15 07:14:55 PM PDT 24
Finished Jul 15 07:16:19 PM PDT 24
Peak memory 216612 kb
Host smart-3c01cfbe-43bb-4df4-9c1f-89c387f4bb32
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331397372 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.3331397372
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.1283299875
Short name T212
Test name
Test status
Simulation time 78389143 ps
CPU time 0.95 seconds
Started Jul 15 07:14:55 PM PDT 24
Finished Jul 15 07:16:20 PM PDT 24
Peak memory 217424 kb
Host smart-4073d723-4b56-4ef0-9491-7dbceb673d62
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283299875 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.1283299875
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.1174576768
Short name T169
Test name
Test status
Simulation time 21182465 ps
CPU time 1.01 seconds
Started Jul 15 07:14:54 PM PDT 24
Finished Jul 15 07:16:20 PM PDT 24
Peak memory 218964 kb
Host smart-1d68ec68-943c-4132-b896-77e8963d13f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174576768 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.1174576768
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.3567050968
Short name T909
Test name
Test status
Simulation time 262616806 ps
CPU time 1.23 seconds
Started Jul 15 07:14:56 PM PDT 24
Finished Jul 15 07:16:19 PM PDT 24
Peak memory 217716 kb
Host smart-4b635f32-5d20-4f9a-902a-77ef672823e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567050968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3567050968
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_smoke.129024774
Short name T625
Test name
Test status
Simulation time 29063789 ps
CPU time 0.92 seconds
Started Jul 15 07:14:55 PM PDT 24
Finished Jul 15 07:16:17 PM PDT 24
Peak memory 215616 kb
Host smart-6352dec4-a499-4bdb-854d-e05d7d4b0c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129024774 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.129024774
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.1071065280
Short name T602
Test name
Test status
Simulation time 69643121 ps
CPU time 1.01 seconds
Started Jul 15 07:14:53 PM PDT 24
Finished Jul 15 07:16:18 PM PDT 24
Peak memory 207328 kb
Host smart-a07acba4-b502-4201-8a70-0f9e1f0f1cd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071065280 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.1071065280
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1738345610
Short name T623
Test name
Test status
Simulation time 349441915939 ps
CPU time 509.77 seconds
Started Jul 15 07:14:54 PM PDT 24
Finished Jul 15 07:24:48 PM PDT 24
Peak memory 220232 kb
Host smart-b33ec867-f548-4c60-ae1e-9a686a25625b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738345610 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1738345610
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.3575264247
Short name T482
Test name
Test status
Simulation time 143854372 ps
CPU time 1.18 seconds
Started Jul 15 07:13:05 PM PDT 24
Finished Jul 15 07:14:24 PM PDT 24
Peak memory 218908 kb
Host smart-788a46b1-d14c-45b0-92f1-29b2bd866e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575264247 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3575264247
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.3804513440
Short name T387
Test name
Test status
Simulation time 120784599 ps
CPU time 0.86 seconds
Started Jul 15 07:13:01 PM PDT 24
Finished Jul 15 07:14:08 PM PDT 24
Peak memory 215420 kb
Host smart-351a27ac-9167-49f6-b753-27738787b818
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804513440 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.3804513440
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.443240158
Short name T920
Test name
Test status
Simulation time 13815423 ps
CPU time 0.92 seconds
Started Jul 15 07:13:01 PM PDT 24
Finished Jul 15 07:14:08 PM PDT 24
Peak memory 216756 kb
Host smart-fa0e4494-784e-4f8a-8919-a4eadefb210e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443240158 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.443240158
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.2817383382
Short name T276
Test name
Test status
Simulation time 189791038 ps
CPU time 0.94 seconds
Started Jul 15 07:12:58 PM PDT 24
Finished Jul 15 07:13:59 PM PDT 24
Peak memory 218680 kb
Host smart-fa629414-32b6-4d9d-9c98-704260088eba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817383382 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.2817383382
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.2790578051
Short name T198
Test name
Test status
Simulation time 23152353 ps
CPU time 0.94 seconds
Started Jul 15 07:13:04 PM PDT 24
Finished Jul 15 07:14:17 PM PDT 24
Peak memory 219560 kb
Host smart-7340b822-1205-4933-a362-3315b80c4272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790578051 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.2790578051
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.4098895504
Short name T86
Test name
Test status
Simulation time 166569012 ps
CPU time 2.18 seconds
Started Jul 15 07:12:58 PM PDT 24
Finished Jul 15 07:14:01 PM PDT 24
Peak memory 220116 kb
Host smart-ab33d740-41e8-4826-ba68-9a4ff1d973b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098895504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.4098895504
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.3783519837
Short name T767
Test name
Test status
Simulation time 30647017 ps
CPU time 0.83 seconds
Started Jul 15 07:12:52 PM PDT 24
Finished Jul 15 07:13:37 PM PDT 24
Peak memory 215636 kb
Host smart-346b6e07-555d-45ef-9448-dceff733c998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783519837 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.3783519837
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.2231500059
Short name T811
Test name
Test status
Simulation time 58704791 ps
CPU time 0.92 seconds
Started Jul 15 07:13:00 PM PDT 24
Finished Jul 15 07:14:08 PM PDT 24
Peak memory 207436 kb
Host smart-404b96d8-dca5-4841-af4b-30d6087221b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231500059 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2231500059
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.3186079938
Short name T391
Test name
Test status
Simulation time 39866229 ps
CPU time 0.97 seconds
Started Jul 15 07:13:03 PM PDT 24
Finished Jul 15 07:14:16 PM PDT 24
Peak memory 215568 kb
Host smart-10783ca3-dad5-4492-ae52-9b4b9b15ba22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186079938 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.3186079938
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.3811980817
Short name T627
Test name
Test status
Simulation time 179875209 ps
CPU time 1.97 seconds
Started Jul 15 07:12:59 PM PDT 24
Finished Jul 15 07:14:01 PM PDT 24
Peak memory 217716 kb
Host smart-8096b163-5aa1-4142-a1ab-5c1830e31ff4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811980817 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.3811980817
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/50.edn_alert.3531293048
Short name T884
Test name
Test status
Simulation time 24867744 ps
CPU time 1.11 seconds
Started Jul 15 07:14:57 PM PDT 24
Finished Jul 15 07:16:19 PM PDT 24
Peak memory 220336 kb
Host smart-5a7df464-d25f-4fd4-895c-804ffe8ef810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531293048 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.3531293048
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.1659875803
Short name T180
Test name
Test status
Simulation time 29575281 ps
CPU time 0.86 seconds
Started Jul 15 07:14:53 PM PDT 24
Finished Jul 15 07:16:19 PM PDT 24
Peak memory 218460 kb
Host smart-697ed951-4f70-4e99-bc9c-1cd902eeb906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659875803 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.1659875803
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.2980349560
Short name T317
Test name
Test status
Simulation time 212316468 ps
CPU time 2.75 seconds
Started Jul 15 07:15:01 PM PDT 24
Finished Jul 15 07:16:25 PM PDT 24
Peak memory 220452 kb
Host smart-4a19de73-677e-4bfb-9fae-71a3e5e3c838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980349560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2980349560
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.3480033918
Short name T654
Test name
Test status
Simulation time 30875653 ps
CPU time 1.23 seconds
Started Jul 15 07:14:56 PM PDT 24
Finished Jul 15 07:16:19 PM PDT 24
Peak memory 220248 kb
Host smart-1f5f941e-c31b-48b0-8fcd-def1125d1ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480033918 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.3480033918
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.1044885537
Short name T428
Test name
Test status
Simulation time 22916947 ps
CPU time 1.12 seconds
Started Jul 15 07:14:55 PM PDT 24
Finished Jul 15 07:16:20 PM PDT 24
Peak memory 218900 kb
Host smart-3ea67a7d-9bf0-42c5-bf41-44a45ab2dcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044885537 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.1044885537
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.2940131199
Short name T718
Test name
Test status
Simulation time 45274775 ps
CPU time 1.12 seconds
Started Jul 15 07:14:57 PM PDT 24
Finished Jul 15 07:16:19 PM PDT 24
Peak memory 218932 kb
Host smart-752153ae-b677-44fb-aaac-8fccc69f9905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940131199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.2940131199
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.2446534845
Short name T195
Test name
Test status
Simulation time 44740403 ps
CPU time 1.15 seconds
Started Jul 15 07:14:51 PM PDT 24
Finished Jul 15 07:16:19 PM PDT 24
Peak memory 219148 kb
Host smart-79b04770-bb91-4ca1-a1d5-6cd19c41a6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446534845 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.2446534845
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.1668898102
Short name T966
Test name
Test status
Simulation time 28030603 ps
CPU time 0.87 seconds
Started Jul 15 07:14:54 PM PDT 24
Finished Jul 15 07:16:19 PM PDT 24
Peak memory 218696 kb
Host smart-e59d7456-c693-435e-af6a-8f67c8b3aa75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668898102 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.1668898102
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.2757380433
Short name T90
Test name
Test status
Simulation time 79387974 ps
CPU time 1.4 seconds
Started Jul 15 07:14:51 PM PDT 24
Finished Jul 15 07:16:20 PM PDT 24
Peak memory 218800 kb
Host smart-7c32be88-98a9-4dcc-a32b-5fa80d0a3ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757380433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.2757380433
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.3593333519
Short name T194
Test name
Test status
Simulation time 25187801 ps
CPU time 1.21 seconds
Started Jul 15 07:15:01 PM PDT 24
Finished Jul 15 07:16:23 PM PDT 24
Peak memory 220204 kb
Host smart-e592b1bf-0f9a-4afc-a8ea-4d43a2cb9e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593333519 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.3593333519
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_genbits.1069091364
Short name T668
Test name
Test status
Simulation time 36095875 ps
CPU time 1.08 seconds
Started Jul 15 07:14:56 PM PDT 24
Finished Jul 15 07:16:19 PM PDT 24
Peak memory 217612 kb
Host smart-4d654178-cdb0-429f-a058-aa122614d7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069091364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.1069091364
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.569697959
Short name T665
Test name
Test status
Simulation time 81417369 ps
CPU time 1.17 seconds
Started Jul 15 07:15:06 PM PDT 24
Finished Jul 15 07:16:24 PM PDT 24
Peak memory 220648 kb
Host smart-2ca18359-f4af-4bf5-93d5-20547c0b7559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569697959 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.569697959
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.2830905260
Short name T140
Test name
Test status
Simulation time 33545259 ps
CPU time 0.96 seconds
Started Jul 15 07:15:05 PM PDT 24
Finished Jul 15 07:16:24 PM PDT 24
Peak memory 220132 kb
Host smart-29af0a25-5c00-43bc-8c02-e8c1275f0aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830905260 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.2830905260
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.43862603
Short name T296
Test name
Test status
Simulation time 29154572 ps
CPU time 1.3 seconds
Started Jul 15 07:15:01 PM PDT 24
Finished Jul 15 07:16:23 PM PDT 24
Peak memory 218876 kb
Host smart-f26de8a9-0686-4b03-9ecc-c1702bcbd15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43862603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.43862603
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.3401645987
Short name T795
Test name
Test status
Simulation time 38001573 ps
CPU time 1.13 seconds
Started Jul 15 07:15:03 PM PDT 24
Finished Jul 15 07:16:24 PM PDT 24
Peak memory 218644 kb
Host smart-49138737-b6fd-4063-928f-3d10275688bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401645987 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.3401645987
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.1832246817
Short name T168
Test name
Test status
Simulation time 23735666 ps
CPU time 0.9 seconds
Started Jul 15 07:15:08 PM PDT 24
Finished Jul 15 07:16:28 PM PDT 24
Peak memory 218552 kb
Host smart-be768935-6b7e-4109-adec-416ac45b3cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832246817 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.1832246817
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.1785093482
Short name T570
Test name
Test status
Simulation time 84237480 ps
CPU time 1 seconds
Started Jul 15 07:15:04 PM PDT 24
Finished Jul 15 07:16:24 PM PDT 24
Peak memory 217500 kb
Host smart-162506ec-dc4c-43e8-b7f0-7c10539f084a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785093482 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.1785093482
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.3839262945
Short name T798
Test name
Test status
Simulation time 36629730 ps
CPU time 1.15 seconds
Started Jul 15 07:15:00 PM PDT 24
Finished Jul 15 07:16:22 PM PDT 24
Peak memory 218832 kb
Host smart-95211e78-4b30-4dfd-bad3-3406600962af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839262945 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.3839262945
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.880725323
Short name T57
Test name
Test status
Simulation time 19712732 ps
CPU time 1.18 seconds
Started Jul 15 07:15:00 PM PDT 24
Finished Jul 15 07:16:23 PM PDT 24
Peak memory 224192 kb
Host smart-046cd128-798b-40dd-855f-63a2e7f624df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880725323 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.880725323
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.4213545458
Short name T801
Test name
Test status
Simulation time 40526952 ps
CPU time 1.25 seconds
Started Jul 15 07:15:02 PM PDT 24
Finished Jul 15 07:16:23 PM PDT 24
Peak memory 218712 kb
Host smart-d8ca9fb0-5212-4eb0-ae63-e4b40bb2c653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213545458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.4213545458
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.287291191
Short name T293
Test name
Test status
Simulation time 81736883 ps
CPU time 1.16 seconds
Started Jul 15 07:15:04 PM PDT 24
Finished Jul 15 07:16:24 PM PDT 24
Peak memory 219468 kb
Host smart-151f38f0-cafa-4e84-9549-c34f8dc593fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287291191 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.287291191
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.4112423493
Short name T189
Test name
Test status
Simulation time 29165950 ps
CPU time 1.07 seconds
Started Jul 15 07:15:03 PM PDT 24
Finished Jul 15 07:16:22 PM PDT 24
Peak memory 224360 kb
Host smart-945e37f4-90c1-4af6-b0b4-af1fa5b9d774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112423493 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.4112423493
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.108815882
Short name T875
Test name
Test status
Simulation time 48249010 ps
CPU time 1.23 seconds
Started Jul 15 07:15:01 PM PDT 24
Finished Jul 15 07:16:23 PM PDT 24
Peak memory 220440 kb
Host smart-8e897e25-d815-477d-9080-9ac8150c65ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108815882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.108815882
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.1421045170
Short name T416
Test name
Test status
Simulation time 23732740 ps
CPU time 1.02 seconds
Started Jul 15 07:15:05 PM PDT 24
Finished Jul 15 07:16:24 PM PDT 24
Peak memory 224268 kb
Host smart-1bef82cb-0442-454f-9de7-d5f7f578ab5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421045170 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.1421045170
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/59.edn_alert.70402600
Short name T739
Test name
Test status
Simulation time 41297877 ps
CPU time 1.17 seconds
Started Jul 15 07:14:59 PM PDT 24
Finished Jul 15 07:16:23 PM PDT 24
Peak memory 219940 kb
Host smart-e3d66843-68ff-4ad1-90e0-3d4909a4878f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70402600 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.70402600
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.1825898203
Short name T200
Test name
Test status
Simulation time 31057672 ps
CPU time 0.91 seconds
Started Jul 15 07:15:02 PM PDT 24
Finished Jul 15 07:16:23 PM PDT 24
Peak memory 219392 kb
Host smart-827d8b05-e350-4413-a0e9-d7d790fff7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825898203 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.1825898203
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3846794036
Short name T633
Test name
Test status
Simulation time 48557390 ps
CPU time 1.32 seconds
Started Jul 15 07:15:00 PM PDT 24
Finished Jul 15 07:16:23 PM PDT 24
Peak memory 217752 kb
Host smart-42dd7144-61c3-4c83-950f-df0445d6213f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846794036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3846794036
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.3685032895
Short name T15
Test name
Test status
Simulation time 25517481 ps
CPU time 1.15 seconds
Started Jul 15 07:12:59 PM PDT 24
Finished Jul 15 07:14:00 PM PDT 24
Peak memory 218948 kb
Host smart-3dca336a-45c1-49a3-97c2-49146d5218f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685032895 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.3685032895
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.720757000
Short name T737
Test name
Test status
Simulation time 14871538 ps
CPU time 0.9 seconds
Started Jul 15 07:12:55 PM PDT 24
Finished Jul 15 07:13:51 PM PDT 24
Peak memory 215476 kb
Host smart-2711c68e-198a-46db-8bf4-06cb536a2bc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720757000 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.720757000
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.2545043210
Short name T829
Test name
Test status
Simulation time 20374413 ps
CPU time 0.82 seconds
Started Jul 15 07:13:05 PM PDT 24
Finished Jul 15 07:14:25 PM PDT 24
Peak memory 216192 kb
Host smart-51800ff2-9a1b-4b86-b706-05a04bee005d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545043210 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.2545043210
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.925151329
Short name T603
Test name
Test status
Simulation time 92154817 ps
CPU time 1.05 seconds
Started Jul 15 07:13:02 PM PDT 24
Finished Jul 15 07:14:16 PM PDT 24
Peak memory 217092 kb
Host smart-70449e84-2ec9-4301-b1f8-6e0b0f4f66bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925151329 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_dis
able_auto_req_mode.925151329
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.12599096
Short name T511
Test name
Test status
Simulation time 19696253 ps
CPU time 1.18 seconds
Started Jul 15 07:13:01 PM PDT 24
Finished Jul 15 07:14:08 PM PDT 24
Peak memory 224292 kb
Host smart-a37229a0-98bb-4520-8fa0-fec911a4f24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12599096 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.12599096
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.4028598141
Short name T608
Test name
Test status
Simulation time 63991750 ps
CPU time 1.03 seconds
Started Jul 15 07:12:57 PM PDT 24
Finished Jul 15 07:13:53 PM PDT 24
Peak memory 217560 kb
Host smart-239656a8-aa6b-4cd8-8db6-3d14ebd15590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028598141 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.4028598141
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.1526146424
Short name T987
Test name
Test status
Simulation time 21664528 ps
CPU time 1.14 seconds
Started Jul 15 07:12:56 PM PDT 24
Finished Jul 15 07:13:53 PM PDT 24
Peak memory 224256 kb
Host smart-8b4ddaef-3e5d-471c-851e-158dc9d59f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526146424 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.1526146424
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.3616051208
Short name T245
Test name
Test status
Simulation time 30072392 ps
CPU time 1.02 seconds
Started Jul 15 07:12:58 PM PDT 24
Finished Jul 15 07:13:59 PM PDT 24
Peak memory 207384 kb
Host smart-10824776-01d9-45a8-b090-56bf550ca3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616051208 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.3616051208
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.2367463897
Short name T976
Test name
Test status
Simulation time 51827177 ps
CPU time 0.92 seconds
Started Jul 15 07:12:58 PM PDT 24
Finished Jul 15 07:14:00 PM PDT 24
Peak memory 215380 kb
Host smart-67840117-4efa-46d2-8469-df0b8f268849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367463897 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.2367463897
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.285681494
Short name T831
Test name
Test status
Simulation time 624393815 ps
CPU time 3.5 seconds
Started Jul 15 07:13:11 PM PDT 24
Finished Jul 15 07:14:34 PM PDT 24
Peak memory 217440 kb
Host smart-ad34f145-cfbe-41d7-900d-93fea1a1d6bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285681494 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.285681494
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.2015361782
Short name T305
Test name
Test status
Simulation time 537503192230 ps
CPU time 3436.56 seconds
Started Jul 15 07:13:03 PM PDT 24
Finished Jul 15 08:11:33 PM PDT 24
Peak memory 236360 kb
Host smart-341d1904-f496-4b17-b731-3d9e20b24022
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015361782 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.2015361782
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.2360564099
Short name T893
Test name
Test status
Simulation time 24066793 ps
CPU time 1.16 seconds
Started Jul 15 07:15:01 PM PDT 24
Finished Jul 15 07:16:23 PM PDT 24
Peak memory 220008 kb
Host smart-1d6aa562-3ff2-42e2-8f80-dc657bfe5588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360564099 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.2360564099
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.3442846891
Short name T197
Test name
Test status
Simulation time 18866348 ps
CPU time 1.12 seconds
Started Jul 15 07:15:05 PM PDT 24
Finished Jul 15 07:16:24 PM PDT 24
Peak memory 224292 kb
Host smart-73d37a75-16e1-42e7-80e5-78c805820cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442846891 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.3442846891
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.3750846018
Short name T855
Test name
Test status
Simulation time 121863685 ps
CPU time 1.32 seconds
Started Jul 15 07:15:04 PM PDT 24
Finished Jul 15 07:16:23 PM PDT 24
Peak memory 217764 kb
Host smart-f5c78f59-7443-4199-bb03-ac8a1ef85c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750846018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3750846018
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.3460356490
Short name T171
Test name
Test status
Simulation time 25076611 ps
CPU time 1.13 seconds
Started Jul 15 07:15:01 PM PDT 24
Finished Jul 15 07:16:22 PM PDT 24
Peak memory 219924 kb
Host smart-488fed32-8697-4904-b169-f733ce3106c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460356490 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.3460356490
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.2934561096
Short name T61
Test name
Test status
Simulation time 19358945 ps
CPU time 1.15 seconds
Started Jul 15 07:15:05 PM PDT 24
Finished Jul 15 07:16:24 PM PDT 24
Peak memory 224336 kb
Host smart-76e4aeb4-d6f0-4432-a0e1-da63d367ed12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934561096 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.2934561096
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.4275973589
Short name T863
Test name
Test status
Simulation time 94594428 ps
CPU time 1.64 seconds
Started Jul 15 07:15:04 PM PDT 24
Finished Jul 15 07:16:24 PM PDT 24
Peak memory 219136 kb
Host smart-443d88c7-a932-4102-9700-44bc192b39f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275973589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.4275973589
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.757597659
Short name T558
Test name
Test status
Simulation time 39537955 ps
CPU time 1.03 seconds
Started Jul 15 07:15:03 PM PDT 24
Finished Jul 15 07:16:23 PM PDT 24
Peak memory 218632 kb
Host smart-88abcfbc-76ad-4721-a29f-0f8926a719a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757597659 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.757597659
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.444147609
Short name T732
Test name
Test status
Simulation time 26495100 ps
CPU time 0.88 seconds
Started Jul 15 07:15:00 PM PDT 24
Finished Jul 15 07:16:22 PM PDT 24
Peak memory 218628 kb
Host smart-d3bc7912-0be2-4a2e-9a3a-da47287316be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444147609 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.444147609
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.2571410563
Short name T526
Test name
Test status
Simulation time 65307033 ps
CPU time 1.44 seconds
Started Jul 15 07:15:01 PM PDT 24
Finished Jul 15 07:16:23 PM PDT 24
Peak memory 218980 kb
Host smart-b42a0019-7e6a-4568-bf76-7f767246dd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571410563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.2571410563
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.2339311052
Short name T281
Test name
Test status
Simulation time 25449409 ps
CPU time 1.19 seconds
Started Jul 15 07:14:59 PM PDT 24
Finished Jul 15 07:16:22 PM PDT 24
Peak memory 219044 kb
Host smart-f69d2b2b-20b1-408a-b891-83a199a2d5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339311052 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.2339311052
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.2687883809
Short name T901
Test name
Test status
Simulation time 21835389 ps
CPU time 0.9 seconds
Started Jul 15 07:15:05 PM PDT 24
Finished Jul 15 07:16:24 PM PDT 24
Peak memory 218776 kb
Host smart-7e26a06e-5ed9-41a6-aa56-b7f7875cef32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687883809 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.2687883809
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.2974809909
Short name T393
Test name
Test status
Simulation time 83923968 ps
CPU time 1.56 seconds
Started Jul 15 07:15:01 PM PDT 24
Finished Jul 15 07:16:23 PM PDT 24
Peak memory 219072 kb
Host smart-677fbdcc-51d6-4c8d-a702-695e6d9bd277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974809909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.2974809909
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.2065486429
Short name T294
Test name
Test status
Simulation time 24174482 ps
CPU time 1.2 seconds
Started Jul 15 07:15:03 PM PDT 24
Finished Jul 15 07:16:24 PM PDT 24
Peak memory 220248 kb
Host smart-417991eb-9514-4e2c-9d06-01e64f6d67c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065486429 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.2065486429
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_genbits.2213723070
Short name T365
Test name
Test status
Simulation time 76440749 ps
CPU time 1.2 seconds
Started Jul 15 07:15:04 PM PDT 24
Finished Jul 15 07:16:24 PM PDT 24
Peak memory 217700 kb
Host smart-053878f6-19aa-4dd2-b005-9b8cbe9f6f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213723070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2213723070
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.979273793
Short name T649
Test name
Test status
Simulation time 82187465 ps
CPU time 1.2 seconds
Started Jul 15 07:15:02 PM PDT 24
Finished Jul 15 07:16:23 PM PDT 24
Peak memory 219796 kb
Host smart-8d7e7235-ea1e-44fe-a7af-3117877209a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979273793 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.979273793
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.2842790822
Short name T452
Test name
Test status
Simulation time 19879099 ps
CPU time 1.04 seconds
Started Jul 15 07:15:04 PM PDT 24
Finished Jul 15 07:16:24 PM PDT 24
Peak memory 224156 kb
Host smart-7e3bcab0-bc81-4e61-822c-75ad8992d977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842790822 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.2842790822
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.788349086
Short name T319
Test name
Test status
Simulation time 46977146 ps
CPU time 1.6 seconds
Started Jul 15 07:15:03 PM PDT 24
Finished Jul 15 07:16:24 PM PDT 24
Peak memory 217680 kb
Host smart-ff834001-a4d6-42de-9e2f-498591a2812e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788349086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.788349086
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.904135411
Short name T769
Test name
Test status
Simulation time 178546807 ps
CPU time 1.03 seconds
Started Jul 15 07:15:04 PM PDT 24
Finished Jul 15 07:16:24 PM PDT 24
Peak memory 218660 kb
Host smart-67e8e116-75d3-4fb7-a1ec-e28c356a53a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904135411 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.904135411
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_genbits.3731024177
Short name T724
Test name
Test status
Simulation time 53398301 ps
CPU time 1.62 seconds
Started Jul 15 07:15:04 PM PDT 24
Finished Jul 15 07:16:24 PM PDT 24
Peak memory 218808 kb
Host smart-b73b35f0-4d02-4101-8331-bba0d0a92cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731024177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3731024177
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.879621267
Short name T699
Test name
Test status
Simulation time 100751235 ps
CPU time 1.17 seconds
Started Jul 15 07:15:05 PM PDT 24
Finished Jul 15 07:16:24 PM PDT 24
Peak memory 215964 kb
Host smart-8505e072-059a-45e6-9bc7-9fe3fb000ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879621267 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.879621267
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.3677166017
Short name T172
Test name
Test status
Simulation time 19859816 ps
CPU time 1 seconds
Started Jul 15 07:15:02 PM PDT 24
Finished Jul 15 07:16:23 PM PDT 24
Peak memory 218588 kb
Host smart-b28c366d-c600-4fd6-a3e5-fc7eb06b1a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677166017 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.3677166017
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.3680207678
Short name T372
Test name
Test status
Simulation time 67646649 ps
CPU time 0.98 seconds
Started Jul 15 07:15:02 PM PDT 24
Finished Jul 15 07:16:22 PM PDT 24
Peak memory 217624 kb
Host smart-7d3e5e5d-c530-4ae3-a06c-e02ac37b5577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680207678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3680207678
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.2311742380
Short name T7
Test name
Test status
Simulation time 56614125 ps
CPU time 1.33 seconds
Started Jul 15 07:15:05 PM PDT 24
Finished Jul 15 07:16:24 PM PDT 24
Peak memory 215996 kb
Host smart-72fc7989-f88e-4a04-b6b6-f65f5ceeefd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311742380 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.2311742380
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.570069844
Short name T80
Test name
Test status
Simulation time 32719329 ps
CPU time 1.08 seconds
Started Jul 15 07:15:07 PM PDT 24
Finished Jul 15 07:16:28 PM PDT 24
Peak memory 218876 kb
Host smart-47dc1dd8-a85c-428c-9b53-393c234444ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570069844 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.570069844
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.2122304530
Short name T346
Test name
Test status
Simulation time 53279939 ps
CPU time 2.02 seconds
Started Jul 15 07:15:07 PM PDT 24
Finished Jul 15 07:16:28 PM PDT 24
Peak memory 219048 kb
Host smart-51f46ba9-26c3-46c4-b663-942c9ce98904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122304530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.2122304530
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.113785170
Short name T849
Test name
Test status
Simulation time 26182541 ps
CPU time 1.25 seconds
Started Jul 15 07:15:06 PM PDT 24
Finished Jul 15 07:16:24 PM PDT 24
Peak memory 221188 kb
Host smart-a3f9fb3f-1b4a-4187-a8b6-bcdc4c2a3157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113785170 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.113785170
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.3897101149
Short name T957
Test name
Test status
Simulation time 74939065 ps
CPU time 0.97 seconds
Started Jul 15 07:15:08 PM PDT 24
Finished Jul 15 07:16:28 PM PDT 24
Peak memory 229580 kb
Host smart-16b7731b-f3aa-4301-bf2e-0c64938b1f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897101149 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.3897101149
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.1099986202
Short name T427
Test name
Test status
Simulation time 46836918 ps
CPU time 1.8 seconds
Started Jul 15 07:15:07 PM PDT 24
Finished Jul 15 07:16:28 PM PDT 24
Peak memory 219708 kb
Host smart-f4771e2b-1c5f-4d97-9ce1-67286ebf534d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099986202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1099986202
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.4030411134
Short name T517
Test name
Test status
Simulation time 35639516 ps
CPU time 1.05 seconds
Started Jul 15 07:12:58 PM PDT 24
Finished Jul 15 07:14:00 PM PDT 24
Peak memory 218800 kb
Host smart-b89b35c7-151c-4350-baee-9aceb63e04f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030411134 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.4030411134
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.4205294877
Short name T823
Test name
Test status
Simulation time 25788229 ps
CPU time 0.9 seconds
Started Jul 15 07:13:01 PM PDT 24
Finished Jul 15 07:14:08 PM PDT 24
Peak memory 206984 kb
Host smart-84b3b707-6e5d-4184-9968-92083e076517
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205294877 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.4205294877
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.1716701427
Short name T176
Test name
Test status
Simulation time 12421891 ps
CPU time 0.95 seconds
Started Jul 15 07:13:03 PM PDT 24
Finished Jul 15 07:14:17 PM PDT 24
Peak memory 216704 kb
Host smart-e742c637-831f-4b8d-96ba-60851dd2d664
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716701427 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.1716701427
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.881730099
Short name T813
Test name
Test status
Simulation time 56765129 ps
CPU time 0.98 seconds
Started Jul 15 07:13:04 PM PDT 24
Finished Jul 15 07:14:17 PM PDT 24
Peak memory 219952 kb
Host smart-a9d5d014-f6e5-466b-b3ce-4dbcbaaed943
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881730099 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_dis
able_auto_req_mode.881730099
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.1461216486
Short name T173
Test name
Test status
Simulation time 67287068 ps
CPU time 0.83 seconds
Started Jul 15 07:12:59 PM PDT 24
Finished Jul 15 07:14:06 PM PDT 24
Peak memory 218768 kb
Host smart-80dee88d-d63f-4772-a123-ba2911d41ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461216486 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.1461216486
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.1694686479
Short name T345
Test name
Test status
Simulation time 122928766 ps
CPU time 1.32 seconds
Started Jul 15 07:12:59 PM PDT 24
Finished Jul 15 07:14:00 PM PDT 24
Peak memory 218952 kb
Host smart-18bab214-9e25-436f-8440-835307c171b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694686479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1694686479
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.395441479
Short name T819
Test name
Test status
Simulation time 28616186 ps
CPU time 1.13 seconds
Started Jul 15 07:13:04 PM PDT 24
Finished Jul 15 07:14:17 PM PDT 24
Peak memory 224268 kb
Host smart-93ffb713-3322-4337-b92f-abc863935685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395441479 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.395441479
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.771657010
Short name T783
Test name
Test status
Simulation time 30098055 ps
CPU time 0.95 seconds
Started Jul 15 07:12:58 PM PDT 24
Finished Jul 15 07:14:00 PM PDT 24
Peak memory 207368 kb
Host smart-b10e1a0d-4501-4696-a144-f5cd7af9e720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771657010 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.771657010
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.2765944199
Short name T805
Test name
Test status
Simulation time 47039615 ps
CPU time 0.91 seconds
Started Jul 15 07:13:04 PM PDT 24
Finished Jul 15 07:14:17 PM PDT 24
Peak memory 215560 kb
Host smart-cae687da-dfd7-4c63-bd82-15c4ad43666a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765944199 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.2765944199
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.3789363194
Short name T949
Test name
Test status
Simulation time 35365985 ps
CPU time 1.23 seconds
Started Jul 15 07:13:05 PM PDT 24
Finished Jul 15 07:14:24 PM PDT 24
Peak memory 215600 kb
Host smart-0c55a5d7-84d7-4178-820c-07699ed308d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789363194 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.3789363194
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.1109021549
Short name T40
Test name
Test status
Simulation time 33484544309 ps
CPU time 217.34 seconds
Started Jul 15 07:12:58 PM PDT 24
Finished Jul 15 07:17:36 PM PDT 24
Peak memory 218360 kb
Host smart-2ab239a5-d40c-46f8-9d21-b7594f1bb7af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109021549 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.1109021549
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.4081793455
Short name T388
Test name
Test status
Simulation time 80729112 ps
CPU time 1.05 seconds
Started Jul 15 07:15:11 PM PDT 24
Finished Jul 15 07:16:28 PM PDT 24
Peak memory 219044 kb
Host smart-aaeb44ca-b444-4ee4-965b-de9dd788d0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081793455 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.4081793455
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.741347753
Short name T137
Test name
Test status
Simulation time 32329495 ps
CPU time 1.05 seconds
Started Jul 15 07:15:11 PM PDT 24
Finished Jul 15 07:16:29 PM PDT 24
Peak memory 220764 kb
Host smart-9177e95a-24fd-4338-8015-3f9bfcce0ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741347753 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.741347753
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.993612478
Short name T297
Test name
Test status
Simulation time 25667273 ps
CPU time 1.29 seconds
Started Jul 15 07:15:08 PM PDT 24
Finished Jul 15 07:16:28 PM PDT 24
Peak memory 217728 kb
Host smart-9cb7ee50-30c2-46a0-a679-57075ea28fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993612478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.993612478
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.3135455020
Short name T746
Test name
Test status
Simulation time 24821582 ps
CPU time 1.16 seconds
Started Jul 15 07:15:09 PM PDT 24
Finished Jul 15 07:16:29 PM PDT 24
Peak memory 219992 kb
Host smart-ca6d5296-2214-423c-97d8-281c2be629a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135455020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.3135455020
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.1144844191
Short name T880
Test name
Test status
Simulation time 57982190 ps
CPU time 1.04 seconds
Started Jul 15 07:15:10 PM PDT 24
Finished Jul 15 07:16:29 PM PDT 24
Peak memory 218900 kb
Host smart-0a333f43-a920-4e32-b71a-a25556f379c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144844191 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.1144844191
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.2635620544
Short name T381
Test name
Test status
Simulation time 50509130 ps
CPU time 1.53 seconds
Started Jul 15 07:15:09 PM PDT 24
Finished Jul 15 07:16:29 PM PDT 24
Peak memory 218736 kb
Host smart-88e98988-fcf2-4965-aa78-b7c7b4e7dd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635620544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.2635620544
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.755494353
Short name T723
Test name
Test status
Simulation time 42322298 ps
CPU time 1.13 seconds
Started Jul 15 07:15:11 PM PDT 24
Finished Jul 15 07:16:28 PM PDT 24
Peak memory 218984 kb
Host smart-3bbc0517-6b84-4dd9-b5c0-98c727a786c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755494353 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.755494353
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.270700586
Short name T455
Test name
Test status
Simulation time 23441423 ps
CPU time 1.15 seconds
Started Jul 15 07:15:09 PM PDT 24
Finished Jul 15 07:16:29 PM PDT 24
Peak memory 218916 kb
Host smart-f58f7e64-c6eb-4578-9216-c3b6a4e56b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270700586 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.270700586
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.2677061128
Short name T392
Test name
Test status
Simulation time 63115667 ps
CPU time 1.25 seconds
Started Jul 15 07:15:09 PM PDT 24
Finished Jul 15 07:16:28 PM PDT 24
Peak memory 217604 kb
Host smart-35ecdd11-7baf-4eec-af1d-20a80faf8b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677061128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2677061128
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.2335938553
Short name T697
Test name
Test status
Simulation time 48191035 ps
CPU time 1.18 seconds
Started Jul 15 07:15:07 PM PDT 24
Finished Jul 15 07:16:28 PM PDT 24
Peak memory 215972 kb
Host smart-d8f034e3-54ee-4880-943b-ddd093336b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335938553 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.2335938553
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.452270630
Short name T81
Test name
Test status
Simulation time 26247382 ps
CPU time 1.19 seconds
Started Jul 15 07:15:07 PM PDT 24
Finished Jul 15 07:16:28 PM PDT 24
Peak memory 221168 kb
Host smart-318dd45a-fd12-44a6-af3c-1f2ad86be184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452270630 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.452270630
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.4227328326
Short name T892
Test name
Test status
Simulation time 40732047 ps
CPU time 1.38 seconds
Started Jul 15 07:15:08 PM PDT 24
Finished Jul 15 07:16:29 PM PDT 24
Peak memory 215624 kb
Host smart-970c133a-9cfc-45b6-8b24-2485e5345267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227328326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.4227328326
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.3006556875
Short name T825
Test name
Test status
Simulation time 21547501 ps
CPU time 1.15 seconds
Started Jul 15 07:15:11 PM PDT 24
Finished Jul 15 07:16:29 PM PDT 24
Peak memory 220012 kb
Host smart-08daddb6-7b37-484b-aa4d-4d5c82d46626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006556875 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.3006556875
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.1597720679
Short name T59
Test name
Test status
Simulation time 19041680 ps
CPU time 1.15 seconds
Started Jul 15 07:15:12 PM PDT 24
Finished Jul 15 07:16:28 PM PDT 24
Peak memory 224304 kb
Host smart-d25818ae-9146-4fae-9858-b9d9b4d1d21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597720679 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.1597720679
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.20998176
Short name T472
Test name
Test status
Simulation time 25744261 ps
CPU time 1.31 seconds
Started Jul 15 07:15:12 PM PDT 24
Finished Jul 15 07:16:28 PM PDT 24
Peak memory 220280 kb
Host smart-4e7e672e-52ad-4cbe-97d2-0b00413f4852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20998176 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.20998176
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.2847672868
Short name T235
Test name
Test status
Simulation time 26764521 ps
CPU time 1.2 seconds
Started Jul 15 07:15:08 PM PDT 24
Finished Jul 15 07:16:27 PM PDT 24
Peak memory 219052 kb
Host smart-369981ba-c168-456e-8d70-4c04ce7bbb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847672868 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.2847672868
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.3999880134
Short name T17
Test name
Test status
Simulation time 20242516 ps
CPU time 1.26 seconds
Started Jul 15 07:15:08 PM PDT 24
Finished Jul 15 07:16:28 PM PDT 24
Peak memory 230056 kb
Host smart-d5bb647c-6fa9-467e-867c-ed8bc5cc601a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999880134 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3999880134
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.1827408002
Short name T451
Test name
Test status
Simulation time 28530784 ps
CPU time 1.24 seconds
Started Jul 15 07:15:08 PM PDT 24
Finished Jul 15 07:16:27 PM PDT 24
Peak memory 217720 kb
Host smart-d8d4c20a-0872-4ffa-8d96-faff3b74ed10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827408002 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.1827408002
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.214037145
Short name T446
Test name
Test status
Simulation time 46654094 ps
CPU time 1.2 seconds
Started Jul 15 07:15:14 PM PDT 24
Finished Jul 15 07:16:29 PM PDT 24
Peak memory 219948 kb
Host smart-c6bf603b-42dd-4ac5-98d8-4e4fe8414dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214037145 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.214037145
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.899670465
Short name T226
Test name
Test status
Simulation time 199198237 ps
CPU time 1.1 seconds
Started Jul 15 07:15:20 PM PDT 24
Finished Jul 15 07:16:32 PM PDT 24
Peak memory 219980 kb
Host smart-631328cf-14df-4d93-9d21-d315ff4b0f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899670465 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.899670465
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.2705964466
Short name T397
Test name
Test status
Simulation time 156584757 ps
CPU time 3.17 seconds
Started Jul 15 07:15:07 PM PDT 24
Finished Jul 15 07:16:30 PM PDT 24
Peak memory 220420 kb
Host smart-5baa9196-e4d3-4737-bfaa-100965f84e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705964466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2705964466
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.1471307952
Short name T106
Test name
Test status
Simulation time 25358486 ps
CPU time 1.17 seconds
Started Jul 15 07:15:12 PM PDT 24
Finished Jul 15 07:16:28 PM PDT 24
Peak memory 218932 kb
Host smart-29414eb3-235b-420e-9d21-53f6a8c28b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471307952 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.1471307952
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.595535163
Short name T837
Test name
Test status
Simulation time 27478051 ps
CPU time 0.92 seconds
Started Jul 15 07:15:15 PM PDT 24
Finished Jul 15 07:16:29 PM PDT 24
Peak memory 218600 kb
Host smart-24441cac-2951-4f1d-b803-c3e30ebd45e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595535163 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.595535163
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.3265612131
Short name T928
Test name
Test status
Simulation time 133550995 ps
CPU time 1.81 seconds
Started Jul 15 07:15:15 PM PDT 24
Finished Jul 15 07:16:30 PM PDT 24
Peak memory 218940 kb
Host smart-ac5fec24-1925-4f77-b4d0-40ecfd764564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265612131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.3265612131
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.195504806
Short name T187
Test name
Test status
Simulation time 41093869 ps
CPU time 1.19 seconds
Started Jul 15 07:15:15 PM PDT 24
Finished Jul 15 07:16:29 PM PDT 24
Peak memory 221532 kb
Host smart-cee1caf4-e583-4130-be71-413b70f58570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195504806 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.195504806
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.2238715124
Short name T224
Test name
Test status
Simulation time 33031959 ps
CPU time 0.98 seconds
Started Jul 15 07:15:17 PM PDT 24
Finished Jul 15 07:16:31 PM PDT 24
Peak memory 224056 kb
Host smart-5949b470-1c5b-4177-a09e-69d7636c81fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238715124 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2238715124
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.738895255
Short name T564
Test name
Test status
Simulation time 136987917 ps
CPU time 1.61 seconds
Started Jul 15 07:15:21 PM PDT 24
Finished Jul 15 07:16:33 PM PDT 24
Peak memory 219312 kb
Host smart-35de4163-32e2-4fc0-9236-8808be5496dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738895255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.738895255
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.3951999458
Short name T222
Test name
Test status
Simulation time 22010518 ps
CPU time 0.93 seconds
Started Jul 15 07:15:12 PM PDT 24
Finished Jul 15 07:16:28 PM PDT 24
Peak memory 219040 kb
Host smart-164a0ad4-a4a7-4d76-8c11-885778701cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951999458 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.3951999458
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.959655464
Short name T933
Test name
Test status
Simulation time 78588497 ps
CPU time 1.19 seconds
Started Jul 15 07:15:17 PM PDT 24
Finished Jul 15 07:16:31 PM PDT 24
Peak memory 219060 kb
Host smart-2863cbf1-7b93-45f7-b930-f39927ec8d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959655464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.959655464
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.700639290
Short name T752
Test name
Test status
Simulation time 94861136 ps
CPU time 1.04 seconds
Started Jul 15 07:12:59 PM PDT 24
Finished Jul 15 07:14:00 PM PDT 24
Peak memory 218784 kb
Host smart-0c342064-c541-465b-a22e-41e37e109421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700639290 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.700639290
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.2652279627
Short name T342
Test name
Test status
Simulation time 46155154 ps
CPU time 0.85 seconds
Started Jul 15 07:13:01 PM PDT 24
Finished Jul 15 07:14:15 PM PDT 24
Peak memory 207040 kb
Host smart-34977be8-44ee-48bf-b6fe-f0fa133e4578
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652279627 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2652279627
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.1306995951
Short name T213
Test name
Test status
Simulation time 13008689 ps
CPU time 0.89 seconds
Started Jul 15 07:13:01 PM PDT 24
Finished Jul 15 07:14:15 PM PDT 24
Peak memory 216840 kb
Host smart-4456a147-536b-4673-b935-bf8694db6a67
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306995951 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.1306995951
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.380434138
Short name T712
Test name
Test status
Simulation time 39812130 ps
CPU time 1.22 seconds
Started Jul 15 07:13:02 PM PDT 24
Finished Jul 15 07:14:16 PM PDT 24
Peak memory 219664 kb
Host smart-8ca8cb79-620d-43c6-914a-9a367012181f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380434138 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_dis
able_auto_req_mode.380434138
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.3307949172
Short name T620
Test name
Test status
Simulation time 18144825 ps
CPU time 1.14 seconds
Started Jul 15 07:13:01 PM PDT 24
Finished Jul 15 07:14:08 PM PDT 24
Peak memory 224364 kb
Host smart-eb5ade74-f38b-4c00-bec3-759e4c58278d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307949172 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3307949172
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.1970653292
Short name T440
Test name
Test status
Simulation time 36743710 ps
CPU time 1.49 seconds
Started Jul 15 07:13:09 PM PDT 24
Finished Jul 15 07:14:31 PM PDT 24
Peak memory 220120 kb
Host smart-2859f19f-e209-437d-a4c0-0de1d55a9100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970653292 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1970653292
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.345530011
Short name T34
Test name
Test status
Simulation time 21292209 ps
CPU time 1.08 seconds
Started Jul 15 07:13:00 PM PDT 24
Finished Jul 15 07:14:07 PM PDT 24
Peak memory 215828 kb
Host smart-c30cd91b-79fd-4b6d-af73-b83b95f24a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345530011 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.345530011
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.3466480916
Short name T851
Test name
Test status
Simulation time 17314471 ps
CPU time 0.98 seconds
Started Jul 15 07:13:03 PM PDT 24
Finished Jul 15 07:14:17 PM PDT 24
Peak memory 207384 kb
Host smart-86cfd59f-93d3-4c32-948f-8f1c9b1216c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466480916 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.3466480916
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.2800633628
Short name T461
Test name
Test status
Simulation time 77039755 ps
CPU time 0.91 seconds
Started Jul 15 07:13:08 PM PDT 24
Finished Jul 15 07:14:25 PM PDT 24
Peak memory 215568 kb
Host smart-d78f3a20-b4e0-4f02-95e5-725f2939b296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800633628 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.2800633628
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.2819243244
Short name T364
Test name
Test status
Simulation time 347211979 ps
CPU time 1.57 seconds
Started Jul 15 07:12:59 PM PDT 24
Finished Jul 15 07:14:00 PM PDT 24
Peak memory 215640 kb
Host smart-41ac259e-607b-47b2-90ad-e3fdf574cd00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819243244 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.2819243244
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.3566676379
Short name T792
Test name
Test status
Simulation time 397439626283 ps
CPU time 1298.1 seconds
Started Jul 15 07:13:13 PM PDT 24
Finished Jul 15 07:36:15 PM PDT 24
Peak memory 225932 kb
Host smart-8a546e78-079a-41e9-9924-4001d5f0924a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566676379 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3566676379
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.4098836052
Short name T685
Test name
Test status
Simulation time 27158170 ps
CPU time 1.19 seconds
Started Jul 15 07:15:22 PM PDT 24
Finished Jul 15 07:16:35 PM PDT 24
Peak memory 219996 kb
Host smart-0924231a-c659-4943-bf70-2d2d67ffb866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098836052 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.4098836052
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.4235891038
Short name T772
Test name
Test status
Simulation time 29905140 ps
CPU time 1.26 seconds
Started Jul 15 07:15:22 PM PDT 24
Finished Jul 15 07:16:35 PM PDT 24
Peak memory 219944 kb
Host smart-4a7087ac-ea96-4862-b3e7-bb99a3eaa97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235891038 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.4235891038
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.948263393
Short name T390
Test name
Test status
Simulation time 70047511 ps
CPU time 1.08 seconds
Started Jul 15 07:15:16 PM PDT 24
Finished Jul 15 07:16:31 PM PDT 24
Peak memory 219036 kb
Host smart-9fb39e87-1645-444e-ae6f-a5f678d7d6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948263393 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.948263393
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.4183600882
Short name T528
Test name
Test status
Simulation time 31101206 ps
CPU time 1.32 seconds
Started Jul 15 07:15:21 PM PDT 24
Finished Jul 15 07:16:32 PM PDT 24
Peak memory 220532 kb
Host smart-ac9ee9be-559c-43a2-8b17-d6d69ffe8c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183600882 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.4183600882
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.530519653
Short name T160
Test name
Test status
Simulation time 23256574 ps
CPU time 1.02 seconds
Started Jul 15 07:15:25 PM PDT 24
Finished Jul 15 07:16:35 PM PDT 24
Peak memory 224228 kb
Host smart-c4ece5d5-d2fb-4e49-aaf1-5d4b1eabad32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530519653 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.530519653
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.1469599768
Short name T802
Test name
Test status
Simulation time 52842592 ps
CPU time 1.27 seconds
Started Jul 15 07:15:25 PM PDT 24
Finished Jul 15 07:16:36 PM PDT 24
Peak memory 218996 kb
Host smart-cb420e8f-62c3-4eb6-9a42-5a966b6fa76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469599768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.1469599768
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.2482576527
Short name T872
Test name
Test status
Simulation time 93914189 ps
CPU time 1.08 seconds
Started Jul 15 07:15:23 PM PDT 24
Finished Jul 15 07:16:35 PM PDT 24
Peak memory 218944 kb
Host smart-de5b4c07-300f-47e8-a7cf-d9100c87496b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482576527 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.2482576527
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.4045700186
Short name T573
Test name
Test status
Simulation time 38834900 ps
CPU time 1.1 seconds
Started Jul 15 07:15:22 PM PDT 24
Finished Jul 15 07:16:35 PM PDT 24
Peak memory 220168 kb
Host smart-86382900-6bce-46a5-8341-4b089c67ca4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045700186 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.4045700186
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.59755651
Short name T25
Test name
Test status
Simulation time 66583386 ps
CPU time 1.06 seconds
Started Jul 15 07:15:24 PM PDT 24
Finished Jul 15 07:16:36 PM PDT 24
Peak memory 217616 kb
Host smart-5a634b4e-e722-4884-b0bc-b3c18b20b841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59755651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.59755651
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.512455398
Short name T231
Test name
Test status
Simulation time 63800282 ps
CPU time 1.11 seconds
Started Jul 15 07:15:24 PM PDT 24
Finished Jul 15 07:16:36 PM PDT 24
Peak memory 219192 kb
Host smart-42f8d6ed-e2be-41e3-a21a-4be9bdeca8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512455398 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.512455398
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.792375346
Short name T116
Test name
Test status
Simulation time 34696460 ps
CPU time 1.05 seconds
Started Jul 15 07:15:21 PM PDT 24
Finished Jul 15 07:16:32 PM PDT 24
Peak memory 219968 kb
Host smart-d6fbb0fe-06de-49da-8ed7-e3e227ad9891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792375346 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.792375346
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.1810483654
Short name T628
Test name
Test status
Simulation time 95899453 ps
CPU time 1.59 seconds
Started Jul 15 07:15:24 PM PDT 24
Finished Jul 15 07:16:36 PM PDT 24
Peak memory 219256 kb
Host smart-bde3367a-21c5-47e2-b1b2-f8b31b904716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810483654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.1810483654
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.265347236
Short name T636
Test name
Test status
Simulation time 28160216 ps
CPU time 1.19 seconds
Started Jul 15 07:15:25 PM PDT 24
Finished Jul 15 07:16:36 PM PDT 24
Peak memory 219964 kb
Host smart-f7a81f00-574c-463e-994d-c05dd0da689c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265347236 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.265347236
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.4072759581
Short name T775
Test name
Test status
Simulation time 33206432 ps
CPU time 0.87 seconds
Started Jul 15 07:15:28 PM PDT 24
Finished Jul 15 07:16:36 PM PDT 24
Peak memory 219412 kb
Host smart-d0165908-d478-44d7-ba4a-bf3010b3e6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072759581 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.4072759581
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.936056129
Short name T890
Test name
Test status
Simulation time 38198058 ps
CPU time 1.15 seconds
Started Jul 15 07:15:21 PM PDT 24
Finished Jul 15 07:16:32 PM PDT 24
Peak memory 217468 kb
Host smart-407bb148-dbdb-4f8c-9816-24e111694613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936056129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.936056129
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.557637732
Short name T139
Test name
Test status
Simulation time 98729730 ps
CPU time 1.04 seconds
Started Jul 15 07:15:26 PM PDT 24
Finished Jul 15 07:16:36 PM PDT 24
Peak memory 219072 kb
Host smart-827a7e88-67bb-4784-9323-6a7f82eb633f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557637732 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.557637732
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.2150691050
Short name T214
Test name
Test status
Simulation time 42487857 ps
CPU time 0.87 seconds
Started Jul 15 07:15:26 PM PDT 24
Finished Jul 15 07:16:36 PM PDT 24
Peak memory 218584 kb
Host smart-9ba3bce9-caee-49f7-9aed-7dd0dabd4416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150691050 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.2150691050
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.2546084278
Short name T615
Test name
Test status
Simulation time 104598324 ps
CPU time 1.24 seconds
Started Jul 15 07:15:27 PM PDT 24
Finished Jul 15 07:16:36 PM PDT 24
Peak memory 218624 kb
Host smart-8f8568ce-3ba6-48bb-9094-ae6a7e69e46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546084278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.2546084278
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.1151983777
Short name T874
Test name
Test status
Simulation time 28350370 ps
CPU time 1.24 seconds
Started Jul 15 07:15:27 PM PDT 24
Finished Jul 15 07:16:36 PM PDT 24
Peak memory 220404 kb
Host smart-2b90af82-de52-4cb5-bf09-d838ac5b3619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151983777 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.1151983777
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.1821833290
Short name T664
Test name
Test status
Simulation time 21389441 ps
CPU time 1.09 seconds
Started Jul 15 07:15:28 PM PDT 24
Finished Jul 15 07:16:36 PM PDT 24
Peak memory 219988 kb
Host smart-f274468c-1cf2-40bf-b882-35eb1305ef6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821833290 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.1821833290
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.3343353349
Short name T742
Test name
Test status
Simulation time 195192148 ps
CPU time 1.28 seconds
Started Jul 15 07:15:26 PM PDT 24
Finished Jul 15 07:16:36 PM PDT 24
Peak memory 217668 kb
Host smart-9a0a5f5c-ef2c-4513-aedc-411506c54128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343353349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3343353349
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.4048483890
Short name T941
Test name
Test status
Simulation time 46896736 ps
CPU time 1.23 seconds
Started Jul 15 07:15:28 PM PDT 24
Finished Jul 15 07:16:37 PM PDT 24
Peak memory 218824 kb
Host smart-5e2bc978-8247-4204-986e-55cddcb02624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048483890 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.4048483890
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.1050274483
Short name T715
Test name
Test status
Simulation time 30017186 ps
CPU time 1.22 seconds
Started Jul 15 07:15:34 PM PDT 24
Finished Jul 15 07:16:40 PM PDT 24
Peak memory 219748 kb
Host smart-45148249-e294-4049-af20-d74ac823d5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050274483 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.1050274483
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.2921683551
Short name T311
Test name
Test status
Simulation time 74073284 ps
CPU time 2.75 seconds
Started Jul 15 07:15:25 PM PDT 24
Finished Jul 15 07:16:37 PM PDT 24
Peak memory 220536 kb
Host smart-d25c9dee-e2e5-4f24-8323-a1f1f42056e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921683551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2921683551
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.1517720432
Short name T834
Test name
Test status
Simulation time 40433771 ps
CPU time 1.1 seconds
Started Jul 15 07:15:35 PM PDT 24
Finished Jul 15 07:16:40 PM PDT 24
Peak memory 221148 kb
Host smart-b30ab78f-219b-4c51-8ad4-244660cc31b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517720432 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.1517720432
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.490165371
Short name T205
Test name
Test status
Simulation time 35363200 ps
CPU time 0.86 seconds
Started Jul 15 07:15:39 PM PDT 24
Finished Jul 15 07:16:43 PM PDT 24
Peak memory 218840 kb
Host smart-a8d04bd1-802d-44b7-b2f8-09af32cffe52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490165371 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.490165371
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.429019845
Short name T981
Test name
Test status
Simulation time 96758671 ps
CPU time 1.35 seconds
Started Jul 15 07:15:34 PM PDT 24
Finished Jul 15 07:16:40 PM PDT 24
Peak memory 219052 kb
Host smart-8bd1692d-cbea-40e6-ae11-2cf3a389e318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429019845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.429019845
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.1078061984
Short name T253
Test name
Test status
Simulation time 95250050 ps
CPU time 1.19 seconds
Started Jul 15 07:15:40 PM PDT 24
Finished Jul 15 07:16:43 PM PDT 24
Peak memory 218848 kb
Host smart-197c1e4f-154e-4d4c-92db-b84c49766c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078061984 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.1078061984
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.2321140816
Short name T5
Test name
Test status
Simulation time 22263559 ps
CPU time 1.23 seconds
Started Jul 15 07:15:34 PM PDT 24
Finished Jul 15 07:16:40 PM PDT 24
Peak memory 224264 kb
Host smart-82b54556-38b6-42bf-9917-7a26183461fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321140816 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.2321140816
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.933425193
Short name T868
Test name
Test status
Simulation time 61655272 ps
CPU time 1.18 seconds
Started Jul 15 07:15:33 PM PDT 24
Finished Jul 15 07:16:39 PM PDT 24
Peak memory 219216 kb
Host smart-061698ac-48f6-4d03-82c6-c5bba9cd8d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933425193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.933425193
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.3088957402
Short name T110
Test name
Test status
Simulation time 28817003 ps
CPU time 1.25 seconds
Started Jul 15 07:13:04 PM PDT 24
Finished Jul 15 07:14:17 PM PDT 24
Peak memory 215936 kb
Host smart-c108cb8d-6d4b-4b40-ad4f-b3457f23486e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088957402 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.3088957402
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.2553596592
Short name T402
Test name
Test status
Simulation time 18113225 ps
CPU time 1.02 seconds
Started Jul 15 07:13:01 PM PDT 24
Finished Jul 15 07:14:08 PM PDT 24
Peak memory 215368 kb
Host smart-6c307799-227c-442f-88fd-377c4f065e2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553596592 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.2553596592
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1908916078
Short name T149
Test name
Test status
Simulation time 325916090 ps
CPU time 1.16 seconds
Started Jul 15 07:13:01 PM PDT 24
Finished Jul 15 07:14:08 PM PDT 24
Peak memory 219960 kb
Host smart-2a0492b7-c589-4bc2-8f51-70d728ada12b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908916078 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1908916078
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.764342096
Short name T879
Test name
Test status
Simulation time 32124409 ps
CPU time 0.88 seconds
Started Jul 15 07:12:56 PM PDT 24
Finished Jul 15 07:13:53 PM PDT 24
Peak memory 218764 kb
Host smart-50e6de29-aa47-493e-86bc-361abe497a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764342096 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.764342096
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.999925371
Short name T793
Test name
Test status
Simulation time 51580875 ps
CPU time 1.6 seconds
Started Jul 15 07:12:58 PM PDT 24
Finished Jul 15 07:14:00 PM PDT 24
Peak memory 217644 kb
Host smart-4fa6f6cc-8b92-4b34-bb7c-9e735cea7514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999925371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.999925371
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_regwen.1958668112
Short name T29
Test name
Test status
Simulation time 28284205 ps
CPU time 0.93 seconds
Started Jul 15 07:13:05 PM PDT 24
Finished Jul 15 07:14:23 PM PDT 24
Peak memory 207400 kb
Host smart-8097f916-3af5-4b2b-a7a6-bb611f664c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958668112 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.1958668112
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.355640568
Short name T246
Test name
Test status
Simulation time 17995204 ps
CPU time 1.02 seconds
Started Jul 15 07:13:09 PM PDT 24
Finished Jul 15 07:14:31 PM PDT 24
Peak memory 207404 kb
Host smart-6f52a12b-3f07-45eb-9e7b-a21d8e26542e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355640568 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.355640568
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.3110957003
Short name T881
Test name
Test status
Simulation time 2273421585 ps
CPU time 4.27 seconds
Started Jul 15 07:13:00 PM PDT 24
Finished Jul 15 07:14:11 PM PDT 24
Peak memory 217596 kb
Host smart-09d52d55-87d8-455e-b85f-67d5ac1aec1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110957003 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.3110957003
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.2043522438
Short name T794
Test name
Test status
Simulation time 37542435978 ps
CPU time 423.53 seconds
Started Jul 15 07:13:01 PM PDT 24
Finished Jul 15 07:21:11 PM PDT 24
Peak memory 224012 kb
Host smart-386d1bb3-726f-401d-91b7-a98d7e70b073
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043522438 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.2043522438
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.2562257033
Short name T790
Test name
Test status
Simulation time 81786615 ps
CPU time 1.2 seconds
Started Jul 15 07:15:34 PM PDT 24
Finished Jul 15 07:16:40 PM PDT 24
Peak memory 220832 kb
Host smart-b85dbb37-24c0-49e6-a801-9873b3262789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562257033 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.2562257033
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.2621930350
Short name T155
Test name
Test status
Simulation time 29073846 ps
CPU time 1.2 seconds
Started Jul 15 07:15:34 PM PDT 24
Finished Jul 15 07:16:40 PM PDT 24
Peak memory 217644 kb
Host smart-ffee84bc-4e3e-4ba2-8098-2fdc3d00daef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621930350 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.2621930350
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.667004414
Short name T373
Test name
Test status
Simulation time 213606747 ps
CPU time 1.32 seconds
Started Jul 15 07:15:34 PM PDT 24
Finished Jul 15 07:16:40 PM PDT 24
Peak memory 220592 kb
Host smart-044ce514-b048-4d67-b582-8492d17c5081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667004414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.667004414
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.2284597924
Short name T183
Test name
Test status
Simulation time 22522143 ps
CPU time 1.12 seconds
Started Jul 15 07:15:41 PM PDT 24
Finished Jul 15 07:16:43 PM PDT 24
Peak memory 218668 kb
Host smart-efc07113-9973-4ddb-a5c5-64afde40e5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284597924 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.2284597924
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.3445727225
Short name T174
Test name
Test status
Simulation time 47167213 ps
CPU time 0.89 seconds
Started Jul 15 07:15:39 PM PDT 24
Finished Jul 15 07:16:43 PM PDT 24
Peak memory 218628 kb
Host smart-3c21e93d-5366-4c84-8ed3-027086154600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445727225 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3445727225
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.175037533
Short name T476
Test name
Test status
Simulation time 91158003 ps
CPU time 1.15 seconds
Started Jul 15 07:15:33 PM PDT 24
Finished Jul 15 07:16:40 PM PDT 24
Peak memory 220076 kb
Host smart-4e4bf534-d8c6-414e-bf6c-6daadc764682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175037533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.175037533
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.2122985329
Short name T560
Test name
Test status
Simulation time 57110740 ps
CPU time 1.27 seconds
Started Jul 15 07:15:40 PM PDT 24
Finished Jul 15 07:16:43 PM PDT 24
Peak memory 216004 kb
Host smart-b1c07bba-df38-4bf8-9491-9561b9601bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122985329 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.2122985329
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.3174880578
Short name T130
Test name
Test status
Simulation time 55593817 ps
CPU time 0.88 seconds
Started Jul 15 07:15:40 PM PDT 24
Finished Jul 15 07:16:43 PM PDT 24
Peak memory 220076 kb
Host smart-cc236e55-2378-4405-a144-f429d7cc237b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174880578 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3174880578
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.319363019
Short name T419
Test name
Test status
Simulation time 45158191 ps
CPU time 1.28 seconds
Started Jul 15 07:15:39 PM PDT 24
Finished Jul 15 07:16:43 PM PDT 24
Peak memory 220252 kb
Host smart-7c2a7253-fb60-4020-9ecf-35c1a4bdfeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319363019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.319363019
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.317088434
Short name T954
Test name
Test status
Simulation time 175741963 ps
CPU time 1.12 seconds
Started Jul 15 07:15:45 PM PDT 24
Finished Jul 15 07:16:44 PM PDT 24
Peak memory 219000 kb
Host smart-e61a5d5c-4d20-4107-99b1-ccaee37b114d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317088434 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.317088434
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.1647918221
Short name T184
Test name
Test status
Simulation time 33436039 ps
CPU time 0.86 seconds
Started Jul 15 07:15:39 PM PDT 24
Finished Jul 15 07:16:43 PM PDT 24
Peak memory 218588 kb
Host smart-2e981fe4-f6c2-4450-8e4a-0295c4b11cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647918221 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.1647918221
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.1589254229
Short name T327
Test name
Test status
Simulation time 153041232 ps
CPU time 1.22 seconds
Started Jul 15 07:15:40 PM PDT 24
Finished Jul 15 07:16:43 PM PDT 24
Peak memory 220420 kb
Host smart-1d5fcb0f-40fc-48dd-8786-1531bab9d448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589254229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.1589254229
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.457784617
Short name T916
Test name
Test status
Simulation time 47553872 ps
CPU time 1.19 seconds
Started Jul 15 07:15:43 PM PDT 24
Finished Jul 15 07:16:44 PM PDT 24
Peak memory 218840 kb
Host smart-d1a8341f-e6be-4732-8278-1e65497f29cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457784617 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.457784617
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.2885091197
Short name T938
Test name
Test status
Simulation time 20367978 ps
CPU time 1.05 seconds
Started Jul 15 07:15:47 PM PDT 24
Finished Jul 15 07:16:45 PM PDT 24
Peak memory 219584 kb
Host smart-1146b984-ecc5-4a84-8a65-a8ee0acfaa03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885091197 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.2885091197
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.431720918
Short name T24
Test name
Test status
Simulation time 112306396 ps
CPU time 1.27 seconds
Started Jul 15 07:15:42 PM PDT 24
Finished Jul 15 07:16:44 PM PDT 24
Peak memory 218984 kb
Host smart-8994e57a-4c04-4c2a-9fd3-d2398a977079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431720918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.431720918
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.2838872232
Short name T395
Test name
Test status
Simulation time 26562309 ps
CPU time 1.11 seconds
Started Jul 15 07:15:43 PM PDT 24
Finished Jul 15 07:16:44 PM PDT 24
Peak memory 218880 kb
Host smart-71dea23b-463e-4cab-b797-f76303a519cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838872232 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.2838872232
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.2106828343
Short name T418
Test name
Test status
Simulation time 21552864 ps
CPU time 0.92 seconds
Started Jul 15 07:15:49 PM PDT 24
Finished Jul 15 07:16:46 PM PDT 24
Peak memory 218484 kb
Host smart-ebc50097-1f1f-4577-a6e1-b28d5ae13b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106828343 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2106828343
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.2628924914
Short name T499
Test name
Test status
Simulation time 51996891 ps
CPU time 1.08 seconds
Started Jul 15 07:15:41 PM PDT 24
Finished Jul 15 07:16:43 PM PDT 24
Peak memory 217572 kb
Host smart-805ea908-9566-4620-8b4d-296457262958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628924914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2628924914
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.680391178
Short name T525
Test name
Test status
Simulation time 38884549 ps
CPU time 1.24 seconds
Started Jul 15 07:15:53 PM PDT 24
Finished Jul 15 07:16:49 PM PDT 24
Peak memory 220640 kb
Host smart-4b40e6d0-380f-4d1c-af38-be2c3347383e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680391178 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.680391178
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.1106046159
Short name T552
Test name
Test status
Simulation time 35285640 ps
CPU time 1.07 seconds
Started Jul 15 07:15:47 PM PDT 24
Finished Jul 15 07:16:46 PM PDT 24
Peak memory 221056 kb
Host smart-6aeb46fa-d803-4896-b4e1-a2f0dc5b0d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106046159 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.1106046159
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.284416015
Short name T430
Test name
Test status
Simulation time 63061933 ps
CPU time 1.01 seconds
Started Jul 15 07:15:47 PM PDT 24
Finished Jul 15 07:16:45 PM PDT 24
Peak memory 217620 kb
Host smart-91f0c3a6-69c5-4f9f-ace8-fff7a58938e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284416015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.284416015
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.874899617
Short name T420
Test name
Test status
Simulation time 52599304 ps
CPU time 1.17 seconds
Started Jul 15 07:15:47 PM PDT 24
Finished Jul 15 07:16:45 PM PDT 24
Peak memory 219012 kb
Host smart-13fa898d-a3f3-47f2-8232-709b6813fa9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874899617 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.874899617
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.32058851
Short name T210
Test name
Test status
Simulation time 33161874 ps
CPU time 1.23 seconds
Started Jul 15 07:15:53 PM PDT 24
Finished Jul 15 07:16:49 PM PDT 24
Peak memory 219884 kb
Host smart-0bb86cfa-5014-449d-8a90-1b2882d9061d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32058851 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.32058851
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.2760375589
Short name T308
Test name
Test status
Simulation time 47807495 ps
CPU time 1.29 seconds
Started Jul 15 07:15:53 PM PDT 24
Finished Jul 15 07:16:49 PM PDT 24
Peak memory 218876 kb
Host smart-e06d9bec-7889-457c-b5d6-dd95b68c6362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760375589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.2760375589
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.1456649292
Short name T145
Test name
Test status
Simulation time 93233024 ps
CPU time 1.21 seconds
Started Jul 15 07:15:47 PM PDT 24
Finished Jul 15 07:16:46 PM PDT 24
Peak memory 218916 kb
Host smart-38959f17-2742-473d-9448-7198fdeae95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456649292 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.1456649292
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.3488020496
Short name T684
Test name
Test status
Simulation time 21429631 ps
CPU time 1.01 seconds
Started Jul 15 07:15:48 PM PDT 24
Finished Jul 15 07:16:46 PM PDT 24
Peak memory 224232 kb
Host smart-38a152ad-c928-4f2c-a226-81e39c61af09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488020496 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.3488020496
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2778427205
Short name T422
Test name
Test status
Simulation time 39603127 ps
CPU time 1.46 seconds
Started Jul 15 07:15:53 PM PDT 24
Finished Jul 15 07:16:49 PM PDT 24
Peak memory 217544 kb
Host smart-3d5ab005-0d8a-4b0f-8616-a9f44f956aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778427205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2778427205
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.4236125190
Short name T708
Test name
Test status
Simulation time 26730819 ps
CPU time 1.21 seconds
Started Jul 15 07:15:54 PM PDT 24
Finished Jul 15 07:16:49 PM PDT 24
Peak memory 219920 kb
Host smart-182cff77-50b5-4dbb-bcb6-874cfc089b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236125190 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.4236125190
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.50279687
Short name T574
Test name
Test status
Simulation time 42829590 ps
CPU time 0.86 seconds
Started Jul 15 07:16:01 PM PDT 24
Finished Jul 15 07:16:53 PM PDT 24
Peak memory 218804 kb
Host smart-4ff5f450-3603-4a88-867a-86024ef432a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50279687 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.50279687
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.2882102002
Short name T328
Test name
Test status
Simulation time 62009457 ps
CPU time 1.41 seconds
Started Jul 15 07:15:54 PM PDT 24
Finished Jul 15 07:16:49 PM PDT 24
Peak memory 218604 kb
Host smart-c46373e4-9931-4909-9669-e19c5cbfc439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882102002 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.2882102002
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%