Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.60 98.25 93.91 96.97 91.86 96.37 99.77 92.08


Total test records in report: 1129
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T1017 /workspace/coverage/cover_reg_top/41.edn_intr_test.747790731 Jul 16 07:10:14 PM PDT 24 Jul 16 07:10:16 PM PDT 24 19468142 ps
T1018 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3464957068 Jul 16 07:09:58 PM PDT 24 Jul 16 07:10:00 PM PDT 24 15958136 ps
T1019 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1107998038 Jul 16 07:09:49 PM PDT 24 Jul 16 07:09:53 PM PDT 24 56039236 ps
T245 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3208444231 Jul 16 07:09:48 PM PDT 24 Jul 16 07:09:51 PM PDT 24 18424650 ps
T273 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.845811620 Jul 16 07:09:49 PM PDT 24 Jul 16 07:09:54 PM PDT 24 95029858 ps
T1020 /workspace/coverage/cover_reg_top/12.edn_csr_rw.3681265087 Jul 16 07:09:58 PM PDT 24 Jul 16 07:10:00 PM PDT 24 86462613 ps
T1021 /workspace/coverage/cover_reg_top/15.edn_intr_test.364579052 Jul 16 07:10:02 PM PDT 24 Jul 16 07:10:06 PM PDT 24 13082422 ps
T260 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.906777481 Jul 16 07:10:00 PM PDT 24 Jul 16 07:10:04 PM PDT 24 18672125 ps
T1022 /workspace/coverage/cover_reg_top/22.edn_intr_test.4099498470 Jul 16 07:10:02 PM PDT 24 Jul 16 07:10:06 PM PDT 24 17010018 ps
T1023 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1383744812 Jul 16 07:09:46 PM PDT 24 Jul 16 07:09:49 PM PDT 24 22488063 ps
T1024 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1788189245 Jul 16 07:10:03 PM PDT 24 Jul 16 07:10:08 PM PDT 24 108796836 ps
T246 /workspace/coverage/cover_reg_top/14.edn_csr_rw.3493003220 Jul 16 07:09:59 PM PDT 24 Jul 16 07:10:01 PM PDT 24 96457294 ps
T278 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1907756008 Jul 16 07:09:57 PM PDT 24 Jul 16 07:09:59 PM PDT 24 74402410 ps
T1025 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3243451744 Jul 16 07:10:03 PM PDT 24 Jul 16 07:10:08 PM PDT 24 35114745 ps
T247 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.495809742 Jul 16 07:09:48 PM PDT 24 Jul 16 07:09:52 PM PDT 24 33090926 ps
T1026 /workspace/coverage/cover_reg_top/17.edn_intr_test.4213626034 Jul 16 07:10:00 PM PDT 24 Jul 16 07:10:04 PM PDT 24 13977743 ps
T1027 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2264782866 Jul 16 07:09:44 PM PDT 24 Jul 16 07:09:46 PM PDT 24 54601277 ps
T274 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3238209320 Jul 16 07:10:00 PM PDT 24 Jul 16 07:10:05 PM PDT 24 383701769 ps
T1028 /workspace/coverage/cover_reg_top/2.edn_csr_rw.3142281375 Jul 16 07:09:47 PM PDT 24 Jul 16 07:09:50 PM PDT 24 15410766 ps
T1029 /workspace/coverage/cover_reg_top/34.edn_intr_test.3100422687 Jul 16 07:10:13 PM PDT 24 Jul 16 07:10:15 PM PDT 24 12915813 ps
T248 /workspace/coverage/cover_reg_top/19.edn_csr_rw.3563652556 Jul 16 07:10:01 PM PDT 24 Jul 16 07:10:05 PM PDT 24 14263574 ps
T1030 /workspace/coverage/cover_reg_top/4.edn_intr_test.2850491310 Jul 16 07:09:49 PM PDT 24 Jul 16 07:09:53 PM PDT 24 25756193 ps
T1031 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1250635342 Jul 16 07:09:59 PM PDT 24 Jul 16 07:10:03 PM PDT 24 19115349 ps
T1032 /workspace/coverage/cover_reg_top/15.edn_tl_errors.220872745 Jul 16 07:10:00 PM PDT 24 Jul 16 07:10:07 PM PDT 24 113081873 ps
T1033 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3366323160 Jul 16 07:10:03 PM PDT 24 Jul 16 07:10:09 PM PDT 24 283907668 ps
T1034 /workspace/coverage/cover_reg_top/46.edn_intr_test.146783848 Jul 16 07:10:21 PM PDT 24 Jul 16 07:10:23 PM PDT 24 55919490 ps
T1035 /workspace/coverage/cover_reg_top/45.edn_intr_test.1313107538 Jul 16 07:10:12 PM PDT 24 Jul 16 07:10:13 PM PDT 24 42983617 ps
T1036 /workspace/coverage/cover_reg_top/33.edn_intr_test.2030677268 Jul 16 07:10:02 PM PDT 24 Jul 16 07:10:06 PM PDT 24 28599124 ps
T1037 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2351871322 Jul 16 07:09:52 PM PDT 24 Jul 16 07:09:56 PM PDT 24 65622575 ps
T1038 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2915285937 Jul 16 07:09:47 PM PDT 24 Jul 16 07:09:50 PM PDT 24 79246014 ps
T1039 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.97495776 Jul 16 07:10:02 PM PDT 24 Jul 16 07:10:06 PM PDT 24 128871816 ps
T1040 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1425726204 Jul 16 07:09:45 PM PDT 24 Jul 16 07:09:50 PM PDT 24 88181702 ps
T1041 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3597238816 Jul 16 07:09:59 PM PDT 24 Jul 16 07:10:03 PM PDT 24 114855955 ps
T1042 /workspace/coverage/cover_reg_top/26.edn_intr_test.2399254151 Jul 16 07:09:59 PM PDT 24 Jul 16 07:10:01 PM PDT 24 46166602 ps
T1043 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.692165347 Jul 16 07:09:59 PM PDT 24 Jul 16 07:10:02 PM PDT 24 39890986 ps
T275 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.250602092 Jul 16 07:09:49 PM PDT 24 Jul 16 07:09:54 PM PDT 24 99491377 ps
T1044 /workspace/coverage/cover_reg_top/28.edn_intr_test.2673011506 Jul 16 07:10:05 PM PDT 24 Jul 16 07:10:08 PM PDT 24 37871787 ps
T1045 /workspace/coverage/cover_reg_top/18.edn_tl_errors.1650258869 Jul 16 07:10:03 PM PDT 24 Jul 16 07:10:09 PM PDT 24 52904951 ps
T1046 /workspace/coverage/cover_reg_top/19.edn_tl_errors.275735350 Jul 16 07:10:00 PM PDT 24 Jul 16 07:10:05 PM PDT 24 124034254 ps
T276 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.688673143 Jul 16 07:10:01 PM PDT 24 Jul 16 07:10:06 PM PDT 24 57834096 ps
T1047 /workspace/coverage/cover_reg_top/10.edn_csr_rw.1981091540 Jul 16 07:10:03 PM PDT 24 Jul 16 07:10:06 PM PDT 24 144288085 ps
T1048 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2899594572 Jul 16 07:09:46 PM PDT 24 Jul 16 07:09:54 PM PDT 24 4300720245 ps
T1049 /workspace/coverage/cover_reg_top/2.edn_intr_test.4146584307 Jul 16 07:09:51 PM PDT 24 Jul 16 07:09:55 PM PDT 24 30440559 ps
T1050 /workspace/coverage/cover_reg_top/38.edn_intr_test.1463137918 Jul 16 07:10:19 PM PDT 24 Jul 16 07:10:21 PM PDT 24 20258126 ps
T1051 /workspace/coverage/cover_reg_top/4.edn_tl_errors.4243073739 Jul 16 07:09:50 PM PDT 24 Jul 16 07:09:56 PM PDT 24 76293668 ps
T1052 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1288441128 Jul 16 07:10:01 PM PDT 24 Jul 16 07:10:05 PM PDT 24 22242328 ps
T1053 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2251645821 Jul 16 07:09:59 PM PDT 24 Jul 16 07:10:03 PM PDT 24 157105829 ps
T1054 /workspace/coverage/cover_reg_top/10.edn_tl_errors.3705616232 Jul 16 07:09:56 PM PDT 24 Jul 16 07:09:59 PM PDT 24 319069934 ps
T279 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3251663474 Jul 16 07:09:47 PM PDT 24 Jul 16 07:09:51 PM PDT 24 277140101 ps
T1055 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.731987660 Jul 16 07:09:49 PM PDT 24 Jul 16 07:09:53 PM PDT 24 82392480 ps
T1056 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1387876921 Jul 16 07:09:47 PM PDT 24 Jul 16 07:09:51 PM PDT 24 124338093 ps
T249 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2037691336 Jul 16 07:09:46 PM PDT 24 Jul 16 07:09:49 PM PDT 24 34788449 ps
T1057 /workspace/coverage/cover_reg_top/3.edn_tl_errors.1067552222 Jul 16 07:09:47 PM PDT 24 Jul 16 07:09:51 PM PDT 24 498323111 ps
T1058 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.223622001 Jul 16 07:09:48 PM PDT 24 Jul 16 07:09:52 PM PDT 24 19765936 ps
T1059 /workspace/coverage/cover_reg_top/24.edn_intr_test.2498242953 Jul 16 07:10:25 PM PDT 24 Jul 16 07:10:27 PM PDT 24 27635381 ps
T1060 /workspace/coverage/cover_reg_top/16.edn_tl_errors.3468097296 Jul 16 07:10:00 PM PDT 24 Jul 16 07:10:04 PM PDT 24 55848762 ps
T1061 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.904124483 Jul 16 07:09:48 PM PDT 24 Jul 16 07:09:52 PM PDT 24 78786317 ps
T1062 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1513827385 Jul 16 07:10:01 PM PDT 24 Jul 16 07:10:06 PM PDT 24 235744248 ps
T1063 /workspace/coverage/cover_reg_top/44.edn_intr_test.3692944032 Jul 16 07:10:18 PM PDT 24 Jul 16 07:10:21 PM PDT 24 24125989 ps
T1064 /workspace/coverage/cover_reg_top/14.edn_tl_errors.3074350805 Jul 16 07:09:57 PM PDT 24 Jul 16 07:10:01 PM PDT 24 397397533 ps
T250 /workspace/coverage/cover_reg_top/16.edn_csr_rw.2192017618 Jul 16 07:10:00 PM PDT 24 Jul 16 07:10:04 PM PDT 24 68957740 ps
T1065 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2774015934 Jul 16 07:09:47 PM PDT 24 Jul 16 07:09:50 PM PDT 24 26815951 ps
T1066 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3139101378 Jul 16 07:10:02 PM PDT 24 Jul 16 07:10:06 PM PDT 24 17214577 ps
T1067 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2481075254 Jul 16 07:09:49 PM PDT 24 Jul 16 07:09:53 PM PDT 24 24745575 ps
T1068 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2203775323 Jul 16 07:09:59 PM PDT 24 Jul 16 07:10:02 PM PDT 24 109772295 ps
T1069 /workspace/coverage/cover_reg_top/12.edn_tl_errors.2981329267 Jul 16 07:10:02 PM PDT 24 Jul 16 07:10:07 PM PDT 24 25844092 ps
T1070 /workspace/coverage/cover_reg_top/40.edn_intr_test.955820121 Jul 16 07:10:15 PM PDT 24 Jul 16 07:10:17 PM PDT 24 17197279 ps
T1071 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.4225748734 Jul 16 07:09:48 PM PDT 24 Jul 16 07:09:52 PM PDT 24 61097958 ps
T1072 /workspace/coverage/cover_reg_top/39.edn_intr_test.217635023 Jul 16 07:10:11 PM PDT 24 Jul 16 07:10:13 PM PDT 24 19434038 ps
T251 /workspace/coverage/cover_reg_top/8.edn_csr_rw.822326165 Jul 16 07:10:05 PM PDT 24 Jul 16 07:10:08 PM PDT 24 12289453 ps
T1073 /workspace/coverage/cover_reg_top/14.edn_intr_test.2390028924 Jul 16 07:09:59 PM PDT 24 Jul 16 07:10:02 PM PDT 24 14963340 ps
T1074 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2096413423 Jul 16 07:09:57 PM PDT 24 Jul 16 07:09:59 PM PDT 24 121717880 ps
T1075 /workspace/coverage/cover_reg_top/11.edn_intr_test.2307027269 Jul 16 07:09:57 PM PDT 24 Jul 16 07:10:00 PM PDT 24 28423714 ps
T1076 /workspace/coverage/cover_reg_top/7.edn_csr_rw.1115770874 Jul 16 07:09:49 PM PDT 24 Jul 16 07:09:52 PM PDT 24 37254872 ps
T1077 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.258128332 Jul 16 07:10:00 PM PDT 24 Jul 16 07:10:04 PM PDT 24 56721308 ps
T1078 /workspace/coverage/cover_reg_top/47.edn_intr_test.1634590193 Jul 16 07:10:13 PM PDT 24 Jul 16 07:10:15 PM PDT 24 29537220 ps
T1079 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3824349147 Jul 16 07:09:48 PM PDT 24 Jul 16 07:09:52 PM PDT 24 139974365 ps
T1080 /workspace/coverage/cover_reg_top/37.edn_intr_test.4118037457 Jul 16 07:10:10 PM PDT 24 Jul 16 07:10:12 PM PDT 24 16248915 ps
T1081 /workspace/coverage/cover_reg_top/5.edn_intr_test.3851287919 Jul 16 07:09:46 PM PDT 24 Jul 16 07:09:49 PM PDT 24 29541012 ps
T1082 /workspace/coverage/cover_reg_top/48.edn_intr_test.1450401284 Jul 16 07:10:11 PM PDT 24 Jul 16 07:10:13 PM PDT 24 30746731 ps
T1083 /workspace/coverage/cover_reg_top/9.edn_intr_test.2567234592 Jul 16 07:09:58 PM PDT 24 Jul 16 07:10:01 PM PDT 24 133628769 ps
T252 /workspace/coverage/cover_reg_top/11.edn_csr_rw.3697573331 Jul 16 07:09:58 PM PDT 24 Jul 16 07:10:01 PM PDT 24 22356098 ps
T1084 /workspace/coverage/cover_reg_top/7.edn_tl_errors.1173317689 Jul 16 07:09:47 PM PDT 24 Jul 16 07:09:51 PM PDT 24 49192035 ps
T1085 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1339121340 Jul 16 07:09:56 PM PDT 24 Jul 16 07:09:58 PM PDT 24 162991076 ps
T1086 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3376036081 Jul 16 07:10:00 PM PDT 24 Jul 16 07:10:04 PM PDT 24 22326637 ps
T1087 /workspace/coverage/cover_reg_top/0.edn_intr_test.2152113355 Jul 16 07:09:36 PM PDT 24 Jul 16 07:09:38 PM PDT 24 11000178 ps
T1088 /workspace/coverage/cover_reg_top/17.edn_tl_errors.2835379501 Jul 16 07:09:58 PM PDT 24 Jul 16 07:10:00 PM PDT 24 50326248 ps
T1089 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3943535782 Jul 16 07:10:01 PM PDT 24 Jul 16 07:10:05 PM PDT 24 21231787 ps
T1090 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1160727053 Jul 16 07:09:51 PM PDT 24 Jul 16 07:09:57 PM PDT 24 587095143 ps
T1091 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2642521499 Jul 16 07:09:58 PM PDT 24 Jul 16 07:10:01 PM PDT 24 87790246 ps
T1092 /workspace/coverage/cover_reg_top/13.edn_csr_rw.1432851783 Jul 16 07:10:20 PM PDT 24 Jul 16 07:10:22 PM PDT 24 13499569 ps
T1093 /workspace/coverage/cover_reg_top/19.edn_intr_test.4279330738 Jul 16 07:10:01 PM PDT 24 Jul 16 07:10:04 PM PDT 24 10930434 ps
T1094 /workspace/coverage/cover_reg_top/35.edn_intr_test.956028317 Jul 16 07:10:14 PM PDT 24 Jul 16 07:10:16 PM PDT 24 140244277 ps
T1095 /workspace/coverage/cover_reg_top/11.edn_tl_errors.3767655466 Jul 16 07:09:59 PM PDT 24 Jul 16 07:10:03 PM PDT 24 70327608 ps
T1096 /workspace/coverage/cover_reg_top/16.edn_intr_test.3092284239 Jul 16 07:10:03 PM PDT 24 Jul 16 07:10:07 PM PDT 24 51411970 ps
T1097 /workspace/coverage/cover_reg_top/5.edn_tl_errors.4294704422 Jul 16 07:09:51 PM PDT 24 Jul 16 07:09:58 PM PDT 24 89164721 ps
T1098 /workspace/coverage/cover_reg_top/32.edn_intr_test.1172287878 Jul 16 07:10:02 PM PDT 24 Jul 16 07:10:06 PM PDT 24 17067780 ps
T1099 /workspace/coverage/cover_reg_top/6.edn_tl_errors.3448607025 Jul 16 07:09:49 PM PDT 24 Jul 16 07:09:54 PM PDT 24 156803216 ps
T1100 /workspace/coverage/cover_reg_top/6.edn_csr_rw.3556420573 Jul 16 07:09:49 PM PDT 24 Jul 16 07:09:53 PM PDT 24 16616727 ps
T1101 /workspace/coverage/cover_reg_top/8.edn_intr_test.882839111 Jul 16 07:10:01 PM PDT 24 Jul 16 07:10:05 PM PDT 24 24122350 ps
T1102 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.935336902 Jul 16 07:09:58 PM PDT 24 Jul 16 07:10:00 PM PDT 24 37919383 ps
T1103 /workspace/coverage/cover_reg_top/10.edn_intr_test.145751234 Jul 16 07:09:59 PM PDT 24 Jul 16 07:10:02 PM PDT 24 12669658 ps
T1104 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.507256946 Jul 16 07:09:49 PM PDT 24 Jul 16 07:09:53 PM PDT 24 120916350 ps
T1105 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3658733590 Jul 16 07:09:58 PM PDT 24 Jul 16 07:10:00 PM PDT 24 128359839 ps
T1106 /workspace/coverage/cover_reg_top/21.edn_intr_test.1582109995 Jul 16 07:09:59 PM PDT 24 Jul 16 07:10:02 PM PDT 24 19071517 ps
T1107 /workspace/coverage/cover_reg_top/3.edn_csr_rw.1956906167 Jul 16 07:09:50 PM PDT 24 Jul 16 07:09:54 PM PDT 24 17497996 ps
T1108 /workspace/coverage/cover_reg_top/13.edn_intr_test.2820291431 Jul 16 07:10:05 PM PDT 24 Jul 16 07:10:08 PM PDT 24 68953751 ps
T1109 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1315185590 Jul 16 07:09:47 PM PDT 24 Jul 16 07:09:53 PM PDT 24 276633392 ps
T1110 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3771904230 Jul 16 07:10:04 PM PDT 24 Jul 16 07:10:08 PM PDT 24 23312206 ps
T1111 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2204862432 Jul 16 07:10:01 PM PDT 24 Jul 16 07:10:06 PM PDT 24 531745573 ps
T1112 /workspace/coverage/cover_reg_top/20.edn_intr_test.4266619421 Jul 16 07:10:02 PM PDT 24 Jul 16 07:10:06 PM PDT 24 22598642 ps
T1113 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3497587117 Jul 16 07:09:48 PM PDT 24 Jul 16 07:09:57 PM PDT 24 250988987 ps
T1114 /workspace/coverage/cover_reg_top/29.edn_intr_test.3160526421 Jul 16 07:10:05 PM PDT 24 Jul 16 07:10:08 PM PDT 24 93308226 ps
T1115 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3227100855 Jul 16 07:10:01 PM PDT 24 Jul 16 07:10:06 PM PDT 24 28662910 ps
T1116 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2978638909 Jul 16 07:10:00 PM PDT 24 Jul 16 07:10:05 PM PDT 24 55958916 ps
T1117 /workspace/coverage/cover_reg_top/49.edn_intr_test.1313717761 Jul 16 07:10:14 PM PDT 24 Jul 16 07:10:16 PM PDT 24 29743388 ps
T1118 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.473335955 Jul 16 07:09:47 PM PDT 24 Jul 16 07:09:49 PM PDT 24 67133605 ps
T1119 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2325663714 Jul 16 07:09:50 PM PDT 24 Jul 16 07:09:56 PM PDT 24 191000614 ps
T1120 /workspace/coverage/cover_reg_top/8.edn_tl_errors.904949196 Jul 16 07:09:57 PM PDT 24 Jul 16 07:10:02 PM PDT 24 259433529 ps
T1121 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.83506511 Jul 16 07:10:03 PM PDT 24 Jul 16 07:10:07 PM PDT 24 175436199 ps
T253 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2576645799 Jul 16 07:09:48 PM PDT 24 Jul 16 07:09:52 PM PDT 24 47158091 ps
T1122 /workspace/coverage/cover_reg_top/31.edn_intr_test.1486077524 Jul 16 07:10:06 PM PDT 24 Jul 16 07:10:08 PM PDT 24 21326571 ps
T1123 /workspace/coverage/cover_reg_top/9.edn_tl_errors.4171877976 Jul 16 07:09:58 PM PDT 24 Jul 16 07:10:03 PM PDT 24 95644065 ps
T1124 /workspace/coverage/cover_reg_top/15.edn_csr_rw.1485726443 Jul 16 07:10:03 PM PDT 24 Jul 16 07:10:07 PM PDT 24 13256590 ps
T1125 /workspace/coverage/cover_reg_top/23.edn_intr_test.4241050280 Jul 16 07:10:02 PM PDT 24 Jul 16 07:10:06 PM PDT 24 28349752 ps
T1126 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.895317126 Jul 16 07:09:45 PM PDT 24 Jul 16 07:09:47 PM PDT 24 41742804 ps
T1127 /workspace/coverage/cover_reg_top/12.edn_intr_test.2947946260 Jul 16 07:09:59 PM PDT 24 Jul 16 07:10:01 PM PDT 24 39868569 ps
T1128 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3075065519 Jul 16 07:09:59 PM PDT 24 Jul 16 07:10:03 PM PDT 24 86399058 ps
T1129 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1997091149 Jul 16 07:10:01 PM PDT 24 Jul 16 07:10:06 PM PDT 24 289738962 ps

Test location /workspace/coverage/default/129.edn_genbits.2008700269
Short name T15
Test name
Test status
Simulation time 674318877 ps
CPU time 5.17 seconds
Started Jul 16 07:14:54 PM PDT 24
Finished Jul 16 07:15:40 PM PDT 24
Peak memory 220496 kb
Host smart-5acb2c7c-fe01-4fad-9c0b-8bb251911aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008700269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2008700269
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.1607039603
Short name T4
Test name
Test status
Simulation time 72849888475 ps
CPU time 1528.12 seconds
Started Jul 16 07:13:24 PM PDT 24
Finished Jul 16 07:39:08 PM PDT 24
Peak memory 224448 kb
Host smart-3361f571-b1e7-4cc3-bd9d-47e5d508b08c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607039603 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.1607039603
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_sec_cm.2768077705
Short name T5
Test name
Test status
Simulation time 1785334797 ps
CPU time 4.44 seconds
Started Jul 16 07:11:55 PM PDT 24
Finished Jul 16 07:13:21 PM PDT 24
Peak memory 235048 kb
Host smart-700116ad-4233-4c36-9f8e-a2cba61fa269
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768077705 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.2768077705
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/17.edn_alert.1708581923
Short name T52
Test name
Test status
Simulation time 29565393 ps
CPU time 1.22 seconds
Started Jul 16 07:12:43 PM PDT 24
Finished Jul 16 07:13:35 PM PDT 24
Peak memory 219092 kb
Host smart-421751a8-7c22-458f-b5fa-ac591dee7528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708581923 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1708581923
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.881143261
Short name T37
Test name
Test status
Simulation time 31259687 ps
CPU time 1.3 seconds
Started Jul 16 07:14:54 PM PDT 24
Finished Jul 16 07:15:36 PM PDT 24
Peak memory 217896 kb
Host smart-c0d92553-970c-405a-8d1f-48d5f05421ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881143261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.881143261
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.613612820
Short name T76
Test name
Test status
Simulation time 34048958 ps
CPU time 1.05 seconds
Started Jul 16 07:14:11 PM PDT 24
Finished Jul 16 07:14:17 PM PDT 24
Peak memory 218900 kb
Host smart-d45955f4-ec33-420f-9906-a276dd5cf40c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613612820 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_di
sable_auto_req_mode.613612820
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_sec_cm.3504707700
Short name T54
Test name
Test status
Simulation time 481161069 ps
CPU time 7.43 seconds
Started Jul 16 07:11:53 PM PDT 24
Finished Jul 16 07:13:23 PM PDT 24
Peak memory 236404 kb
Host smart-ece2c03e-6daa-497b-8cd6-9a80d9207f8a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504707700 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.3504707700
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/29.edn_err.1999495514
Short name T48
Test name
Test status
Simulation time 20379101 ps
CPU time 1.24 seconds
Started Jul 16 07:13:52 PM PDT 24
Finished Jul 16 07:13:58 PM PDT 24
Peak memory 224312 kb
Host smart-fa86404a-0b9a-44a1-9702-8f4d631b390f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999495514 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.1999495514
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/184.edn_alert.2130518893
Short name T79
Test name
Test status
Simulation time 39083430 ps
CPU time 1.16 seconds
Started Jul 16 07:15:16 PM PDT 24
Finished Jul 16 07:16:12 PM PDT 24
Peak memory 220716 kb
Host smart-b2157135-ebde-4b94-b791-431263277937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130518893 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.2130518893
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/106.edn_alert.4173138036
Short name T44
Test name
Test status
Simulation time 80560225 ps
CPU time 1.19 seconds
Started Jul 16 07:14:38 PM PDT 24
Finished Jul 16 07:15:07 PM PDT 24
Peak memory 220628 kb
Host smart-5a813b5e-1138-40e6-b328-2678af99f45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173138036 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.4173138036
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/30.edn_disable.3631689597
Short name T39
Test name
Test status
Simulation time 18751867 ps
CPU time 0.85 seconds
Started Jul 16 07:13:51 PM PDT 24
Finished Jul 16 07:13:57 PM PDT 24
Peak memory 216556 kb
Host smart-19a1208a-9038-4e37-8e6d-57274fe9a3be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631689597 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.3631689597
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/0.edn_regwen.1949572830
Short name T285
Test name
Test status
Simulation time 16415941 ps
CPU time 0.98 seconds
Started Jul 16 07:11:42 PM PDT 24
Finished Jul 16 07:13:11 PM PDT 24
Peak memory 207412 kb
Host smart-03973e81-7588-4986-a820-8343583c47cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949572830 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.1949572830
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/26.edn_alert.1379248000
Short name T177
Test name
Test status
Simulation time 72815180 ps
CPU time 1.07 seconds
Started Jul 16 07:13:39 PM PDT 24
Finished Jul 16 07:13:44 PM PDT 24
Peak memory 220288 kb
Host smart-81ea57f6-6dfe-4013-9161-fb195b2acfa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379248000 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.1379248000
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3238209320
Short name T274
Test name
Test status
Simulation time 383701769 ps
CPU time 2.11 seconds
Started Jul 16 07:10:00 PM PDT 24
Finished Jul 16 07:10:05 PM PDT 24
Peak memory 206872 kb
Host smart-2b4813f7-e118-4838-bff1-6156b1341ab3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238209320 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3238209320
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/default/273.edn_genbits.2448049107
Short name T21
Test name
Test status
Simulation time 55008225 ps
CPU time 1.08 seconds
Started Jul 16 07:15:36 PM PDT 24
Finished Jul 16 07:16:31 PM PDT 24
Peak memory 220288 kb
Host smart-60481d25-965c-4ad1-b079-eaa46fa7460b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448049107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2448049107
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.1488281172
Short name T243
Test name
Test status
Simulation time 92913891 ps
CPU time 0.82 seconds
Started Jul 16 07:09:45 PM PDT 24
Finished Jul 16 07:09:47 PM PDT 24
Peak memory 206720 kb
Host smart-fde04be9-48df-4820-8f34-2dcbcca76874
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488281172 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.1488281172
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2004062468
Short name T99
Test name
Test status
Simulation time 54101808 ps
CPU time 1.17 seconds
Started Jul 16 07:13:01 PM PDT 24
Finished Jul 16 07:13:37 PM PDT 24
Peak memory 218528 kb
Host smart-23f84818-837a-4c07-ad6b-e6533de3ca2c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004062468 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2004062468
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_disable.1216566020
Short name T182
Test name
Test status
Simulation time 11861837 ps
CPU time 0.86 seconds
Started Jul 16 07:12:47 PM PDT 24
Finished Jul 16 07:13:35 PM PDT 24
Peak memory 216628 kb
Host smart-65424367-adad-4cf4-942a-5301fee47e3c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216566020 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1216566020
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable.850282565
Short name T139
Test name
Test status
Simulation time 10694252 ps
CPU time 0.87 seconds
Started Jul 16 07:13:26 PM PDT 24
Finished Jul 16 07:13:41 PM PDT 24
Peak memory 215664 kb
Host smart-e719e0a1-ee01-42a1-8daf-a2c283b71bad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850282565 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.850282565
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.2586840904
Short name T126
Test name
Test status
Simulation time 66135778 ps
CPU time 1.16 seconds
Started Jul 16 07:13:09 PM PDT 24
Finished Jul 16 07:13:38 PM PDT 24
Peak memory 217264 kb
Host smart-9848aa43-0556-4b60-864c-85707c6fef48
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586840904 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.2586840904
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/135.edn_alert.2758849151
Short name T154
Test name
Test status
Simulation time 73051259 ps
CPU time 1.14 seconds
Started Jul 16 07:14:59 PM PDT 24
Finished Jul 16 07:15:50 PM PDT 24
Peak memory 218936 kb
Host smart-b28a4daa-3e8d-47d4-9f84-fe71a52d1731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758849151 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.2758849151
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/180.edn_alert.2064070566
Short name T38
Test name
Test status
Simulation time 93833618 ps
CPU time 1.2 seconds
Started Jul 16 07:15:16 PM PDT 24
Finished Jul 16 07:16:12 PM PDT 24
Peak memory 220048 kb
Host smart-c73800a3-9aa0-46c2-ad2b-b3f8fd323842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064070566 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.2064070566
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.2220465580
Short name T85
Test name
Test status
Simulation time 58718575663 ps
CPU time 1265.47 seconds
Started Jul 16 07:13:39 PM PDT 24
Finished Jul 16 07:34:49 PM PDT 24
Peak memory 220576 kb
Host smart-9e14cf91-7671-4bc3-bf87-2195d6873753
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220465580 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.2220465580
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.1995190296
Short name T57
Test name
Test status
Simulation time 41635491 ps
CPU time 1.43 seconds
Started Jul 16 07:13:50 PM PDT 24
Finished Jul 16 07:13:56 PM PDT 24
Peak memory 217352 kb
Host smart-1e283906-cfca-4b55-b551-35d54f9147e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995190296 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.1995190296
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/55.edn_alert.3907984512
Short name T103
Test name
Test status
Simulation time 83992278 ps
CPU time 1.24 seconds
Started Jul 16 07:14:21 PM PDT 24
Finished Jul 16 07:14:31 PM PDT 24
Peak memory 219796 kb
Host smart-e35cf7c1-2fdf-437b-b561-91a660927732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907984512 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.3907984512
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/64.edn_genbits.3938485364
Short name T12
Test name
Test status
Simulation time 47960635 ps
CPU time 1.28 seconds
Started Jul 16 07:14:28 PM PDT 24
Finished Jul 16 07:14:51 PM PDT 24
Peak memory 219836 kb
Host smart-743e39d2-fedf-42f3-86f4-eed069cf9cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938485364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.3938485364
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.778031883
Short name T167
Test name
Test status
Simulation time 26883337 ps
CPU time 1.18 seconds
Started Jul 16 07:14:57 PM PDT 24
Finished Jul 16 07:15:46 PM PDT 24
Peak memory 218968 kb
Host smart-6a31ae58-6d43-4d8d-9a81-646266a24014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778031883 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.778031883
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/122.edn_alert.1016714889
Short name T172
Test name
Test status
Simulation time 96758697 ps
CPU time 1.19 seconds
Started Jul 16 07:14:51 PM PDT 24
Finished Jul 16 07:15:33 PM PDT 24
Peak memory 220528 kb
Host smart-5f2efc71-4f49-482c-b59a-bebf2e5f35af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016714889 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.1016714889
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/104.edn_alert.974302602
Short name T421
Test name
Test status
Simulation time 27452493 ps
CPU time 1.13 seconds
Started Jul 16 07:14:48 PM PDT 24
Finished Jul 16 07:15:29 PM PDT 24
Peak memory 218744 kb
Host smart-6a45bbfb-4401-4a0d-b3c7-2e5c642633eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974302602 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.974302602
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/108.edn_alert.1777016275
Short name T261
Test name
Test status
Simulation time 25462662 ps
CPU time 1.14 seconds
Started Jul 16 07:14:38 PM PDT 24
Finished Jul 16 07:15:09 PM PDT 24
Peak memory 221172 kb
Host smart-dc58066b-520b-47e0-9fc9-c59acd429eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777016275 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.1777016275
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/115.edn_alert.4034122405
Short name T455
Test name
Test status
Simulation time 25256671 ps
CPU time 1.21 seconds
Started Jul 16 07:14:42 PM PDT 24
Finished Jul 16 07:15:17 PM PDT 24
Peak memory 218992 kb
Host smart-196e052e-2937-482e-80a7-64f30fb86a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034122405 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.4034122405
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/183.edn_alert.710434214
Short name T112
Test name
Test status
Simulation time 51745765 ps
CPU time 1.08 seconds
Started Jul 16 07:15:12 PM PDT 24
Finished Jul 16 07:16:07 PM PDT 24
Peak memory 221080 kb
Host smart-6e7948ec-58d9-49c0-b71d-885da2c9fc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710434214 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.710434214
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/22.edn_disable.3138592073
Short name T193
Test name
Test status
Simulation time 41149897 ps
CPU time 0.86 seconds
Started Jul 16 07:13:24 PM PDT 24
Finished Jul 16 07:13:41 PM PDT 24
Peak memory 216620 kb
Host smart-71794ef5-5718-4c77-b69d-958b6d5175c3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138592073 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3138592073
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/93.edn_alert.2891582237
Short name T770
Test name
Test status
Simulation time 66966226 ps
CPU time 1.13 seconds
Started Jul 16 07:14:50 PM PDT 24
Finished Jul 16 07:15:32 PM PDT 24
Peak memory 220964 kb
Host smart-5e72c76e-4dcb-4bb5-a95a-b6366734b40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891582237 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.2891582237
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/1.edn_intr.4030721010
Short name T28
Test name
Test status
Simulation time 43251428 ps
CPU time 0.9 seconds
Started Jul 16 07:11:41 PM PDT 24
Finished Jul 16 07:13:10 PM PDT 24
Peak memory 215844 kb
Host smart-1ffeaea4-cf6c-4f77-9d97-e9b7b39c8db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030721010 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.4030721010
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/142.edn_genbits.1142549894
Short name T350
Test name
Test status
Simulation time 50248208 ps
CPU time 1.62 seconds
Started Jul 16 07:14:56 PM PDT 24
Finished Jul 16 07:15:41 PM PDT 24
Peak memory 218992 kb
Host smart-9af61f12-7220-41be-8c59-a03b1bc5fd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142549894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.1142549894
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.1572497787
Short name T32
Test name
Test status
Simulation time 31231813 ps
CPU time 0.9 seconds
Started Jul 16 07:11:56 PM PDT 24
Finished Jul 16 07:13:18 PM PDT 24
Peak memory 216016 kb
Host smart-fda9b220-6979-4a23-8fb1-c9ae13812a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572497787 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.1572497787
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/1.edn_disable.3670536527
Short name T160
Test name
Test status
Simulation time 41432931 ps
CPU time 0.78 seconds
Started Jul 16 07:11:37 PM PDT 24
Finished Jul 16 07:13:07 PM PDT 24
Peak memory 216564 kb
Host smart-1c8eca87-c2e9-4235-aa16-09a047e7893c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670536527 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3670536527
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_err.293320219
Short name T537
Test name
Test status
Simulation time 19711625 ps
CPU time 1.02 seconds
Started Jul 16 07:11:40 PM PDT 24
Finished Jul 16 07:13:10 PM PDT 24
Peak memory 219636 kb
Host smart-dc2b940b-07fa-4f91-8c22-c84271f0c316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293320219 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.293320219
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/10.edn_disable.685841893
Short name T628
Test name
Test status
Simulation time 17870636 ps
CPU time 0.93 seconds
Started Jul 16 07:12:21 PM PDT 24
Finished Jul 16 07:13:30 PM PDT 24
Peak memory 216768 kb
Host smart-8f85d198-416c-47d9-861c-794ae3c91b1c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685841893 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.685841893
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/102.edn_alert.4286034634
Short name T162
Test name
Test status
Simulation time 88358689 ps
CPU time 1.16 seconds
Started Jul 16 07:14:30 PM PDT 24
Finished Jul 16 07:14:54 PM PDT 24
Peak memory 219936 kb
Host smart-68dfda1c-cc0f-42f1-aeea-757001fbe7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286034634 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.4286034634
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/105.edn_alert.3699796926
Short name T108
Test name
Test status
Simulation time 26057464 ps
CPU time 1.25 seconds
Started Jul 16 07:14:54 PM PDT 24
Finished Jul 16 07:15:36 PM PDT 24
Peak memory 218912 kb
Host smart-3a1b7b52-8bdf-4423-93f3-c36f40df0256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699796926 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.3699796926
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/13.edn_disable.2029492542
Short name T198
Test name
Test status
Simulation time 12982033 ps
CPU time 0.89 seconds
Started Jul 16 07:12:20 PM PDT 24
Finished Jul 16 07:13:30 PM PDT 24
Peak memory 216820 kb
Host smart-419a63ea-c6cb-43d3-abb0-7675779110c8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029492542 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.2029492542
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.3926834419
Short name T858
Test name
Test status
Simulation time 42734186 ps
CPU time 1.41 seconds
Started Jul 16 07:12:21 PM PDT 24
Finished Jul 16 07:13:31 PM PDT 24
Peak memory 217276 kb
Host smart-b3cdd570-eb59-4780-87fe-3e34d69b4084
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926834419 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.3926834419
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.1853508133
Short name T434
Test name
Test status
Simulation time 57414560 ps
CPU time 1.18 seconds
Started Jul 16 07:12:43 PM PDT 24
Finished Jul 16 07:13:35 PM PDT 24
Peak memory 215912 kb
Host smart-71edf8d4-8019-48c6-9a92-28fde15c6c98
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853508133 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.1853508133
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.3753968360
Short name T176
Test name
Test status
Simulation time 23473679 ps
CPU time 0.93 seconds
Started Jul 16 07:11:54 PM PDT 24
Finished Jul 16 07:13:17 PM PDT 24
Peak memory 218672 kb
Host smart-8d581dfd-4666-4e0e-9f14-5b07b4ddc012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753968360 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.3753968360
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/32.edn_disable.3324853142
Short name T183
Test name
Test status
Simulation time 15276319 ps
CPU time 0.9 seconds
Started Jul 16 07:14:07 PM PDT 24
Finished Jul 16 07:14:12 PM PDT 24
Peak memory 216736 kb
Host smart-3bf34626-eb8a-4cd3-a028-08ee62476c2b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324853142 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3324853142
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable.119279990
Short name T190
Test name
Test status
Simulation time 21898794 ps
CPU time 0.88 seconds
Started Jul 16 07:11:53 PM PDT 24
Finished Jul 16 07:13:17 PM PDT 24
Peak memory 216496 kb
Host smart-3c91e38f-edd6-42df-8090-92489a76d2d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119279990 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.119279990
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/99.edn_err.2412875561
Short name T63
Test name
Test status
Simulation time 30802962 ps
CPU time 0.83 seconds
Started Jul 16 07:14:41 PM PDT 24
Finished Jul 16 07:15:16 PM PDT 24
Peak memory 218524 kb
Host smart-6e6daa92-b113-4e5f-a7b0-f2e66bcbd04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412875561 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.2412875561
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/281.edn_genbits.676696955
Short name T296
Test name
Test status
Simulation time 95372915 ps
CPU time 1.09 seconds
Started Jul 16 07:15:39 PM PDT 24
Finished Jul 16 07:16:37 PM PDT 24
Peak memory 219092 kb
Host smart-1bafed1e-3d53-4697-9b2d-49b81239afb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676696955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.676696955
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_alert_test.125248045
Short name T59
Test name
Test status
Simulation time 39941857 ps
CPU time 0.91 seconds
Started Jul 16 07:12:07 PM PDT 24
Finished Jul 16 07:13:26 PM PDT 24
Peak memory 206960 kb
Host smart-86a1cbf3-b7c2-4ae7-9bcc-a216ccc62b84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125248045 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.125248045
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/123.edn_alert.1617997373
Short name T280
Test name
Test status
Simulation time 30713354 ps
CPU time 1.32 seconds
Started Jul 16 07:14:42 PM PDT 24
Finished Jul 16 07:15:17 PM PDT 24
Peak memory 215956 kb
Host smart-fb8877f4-6992-40f5-99fc-97223c8d5849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617997373 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.1617997373
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.25188660
Short name T363
Test name
Test status
Simulation time 35115797 ps
CPU time 1.46 seconds
Started Jul 16 07:15:16 PM PDT 24
Finished Jul 16 07:16:12 PM PDT 24
Peak memory 218848 kb
Host smart-095d1713-7d8a-45b2-9cb1-bc64a24709a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25188660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.25188660
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.2493605085
Short name T834
Test name
Test status
Simulation time 174323025 ps
CPU time 2.28 seconds
Started Jul 16 07:15:40 PM PDT 24
Finished Jul 16 07:16:38 PM PDT 24
Peak memory 220428 kb
Host smart-9fadaf4d-d3c9-4a61-a0cb-aaa33618e7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493605085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.2493605085
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.1614725814
Short name T80
Test name
Test status
Simulation time 34275424 ps
CPU time 0.86 seconds
Started Jul 16 07:12:16 PM PDT 24
Finished Jul 16 07:13:29 PM PDT 24
Peak memory 215936 kb
Host smart-3744bbc2-cd7e-41d4-9c5d-a851a9d780ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614725814 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.1614725814
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/173.edn_genbits.1621377671
Short name T365
Test name
Test status
Simulation time 153145898 ps
CPU time 1.6 seconds
Started Jul 16 07:15:15 PM PDT 24
Finished Jul 16 07:16:12 PM PDT 24
Peak memory 219744 kb
Host smart-f75a22a5-5fe9-4782-81b8-29c6bafed452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621377671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.1621377671
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3361115443
Short name T244
Test name
Test status
Simulation time 58999642 ps
CPU time 1.72 seconds
Started Jul 16 07:09:46 PM PDT 24
Finished Jul 16 07:09:49 PM PDT 24
Peak memory 206876 kb
Host smart-47139f1d-23d6-4771-bbd7-9b032de2fac1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361115443 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.3361115443
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1907756008
Short name T278
Test name
Test status
Simulation time 74402410 ps
CPU time 1.42 seconds
Started Jul 16 07:09:57 PM PDT 24
Finished Jul 16 07:09:59 PM PDT 24
Peak memory 206960 kb
Host smart-961d4ab4-0c7c-4f38-9b27-c3a79f42d83e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907756008 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.1907756008
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/default/1.edn_alert.2509620931
Short name T918
Test name
Test status
Simulation time 29556495 ps
CPU time 1.22 seconds
Started Jul 16 07:11:41 PM PDT 24
Finished Jul 16 07:13:11 PM PDT 24
Peak memory 216008 kb
Host smart-ba3f6631-c8dc-4296-b24b-712649bf5193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509620931 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.2509620931
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.866722146
Short name T302
Test name
Test status
Simulation time 45070796 ps
CPU time 1.45 seconds
Started Jul 16 07:14:37 PM PDT 24
Finished Jul 16 07:15:07 PM PDT 24
Peak memory 218760 kb
Host smart-985f2575-ba4b-476f-a9c3-c0abaa8a9128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866722146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.866722146
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/120.edn_genbits.1838308180
Short name T325
Test name
Test status
Simulation time 27587763 ps
CPU time 1.3 seconds
Started Jul 16 07:14:46 PM PDT 24
Finished Jul 16 07:15:28 PM PDT 24
Peak memory 220216 kb
Host smart-fd987ad7-b875-45d5-aca8-1ba1d5c63fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838308180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.1838308180
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.1883675517
Short name T313
Test name
Test status
Simulation time 83314407 ps
CPU time 1.12 seconds
Started Jul 16 07:14:41 PM PDT 24
Finished Jul 16 07:15:16 PM PDT 24
Peak memory 219276 kb
Host smart-95637b18-99f0-4dd4-8982-1d30bff14add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883675517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.1883675517
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_stress_all.2735156876
Short name T301
Test name
Test status
Simulation time 260433665 ps
CPU time 5.13 seconds
Started Jul 16 07:12:31 PM PDT 24
Finished Jul 16 07:13:36 PM PDT 24
Peak memory 218916 kb
Host smart-0c8274c3-84b7-471c-92cf-76073b651dbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735156876 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.2735156876
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/152.edn_genbits.1602829817
Short name T897
Test name
Test status
Simulation time 48791441 ps
CPU time 1.18 seconds
Started Jul 16 07:14:56 PM PDT 24
Finished Jul 16 07:15:41 PM PDT 24
Peak memory 217048 kb
Host smart-cc44beea-5860-466f-9ce0-9eb18e463288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602829817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.1602829817
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_genbits.2714374088
Short name T430
Test name
Test status
Simulation time 111862636 ps
CPU time 1.13 seconds
Started Jul 16 07:12:42 PM PDT 24
Finished Jul 16 07:13:35 PM PDT 24
Peak memory 217584 kb
Host smart-85db529a-69fc-474f-b5c9-7dbb6f43b377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714374088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2714374088
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/230.edn_genbits.870251637
Short name T297
Test name
Test status
Simulation time 47832929 ps
CPU time 1.61 seconds
Started Jul 16 07:15:37 PM PDT 24
Finished Jul 16 07:16:35 PM PDT 24
Peak memory 220296 kb
Host smart-8a4ce5b0-1c4d-440d-941a-1861bc11d988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870251637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.870251637
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.2847417746
Short name T308
Test name
Test status
Simulation time 81855527 ps
CPU time 1.6 seconds
Started Jul 16 07:15:34 PM PDT 24
Finished Jul 16 07:16:30 PM PDT 24
Peak memory 219432 kb
Host smart-b3f2accf-71ac-4db5-8ccc-26539f624de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847417746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.2847417746
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.872865683
Short name T925
Test name
Test status
Simulation time 30921392 ps
CPU time 1.5 seconds
Started Jul 16 07:15:38 PM PDT 24
Finished Jul 16 07:16:36 PM PDT 24
Peak memory 218932 kb
Host smart-db44c96c-4bdb-4633-997f-107db47419dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872865683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.872865683
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.2520821543
Short name T27
Test name
Test status
Simulation time 20099748 ps
CPU time 1.08 seconds
Started Jul 16 07:14:06 PM PDT 24
Finished Jul 16 07:14:11 PM PDT 24
Peak memory 216160 kb
Host smart-d37bc564-a644-42af-82cb-d26d078dc2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520821543 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.2520821543
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/11.edn_disable.2331048583
Short name T863
Test name
Test status
Simulation time 14747305 ps
CPU time 0.88 seconds
Started Jul 16 07:12:12 PM PDT 24
Finished Jul 16 07:13:26 PM PDT 24
Peak memory 215888 kb
Host smart-e74c3f30-191a-408d-8798-8fbfa8f58fb3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331048583 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.2331048583
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_err.2203812637
Short name T9
Test name
Test status
Simulation time 35868160 ps
CPU time 1.03 seconds
Started Jul 16 07:12:20 PM PDT 24
Finished Jul 16 07:13:30 PM PDT 24
Peak memory 220188 kb
Host smart-ad3facd9-cd98-479b-88dd-9b4c1455ff6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203812637 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.2203812637
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.4225748734
Short name T1071
Test name
Test status
Simulation time 61097958 ps
CPU time 1.48 seconds
Started Jul 16 07:09:48 PM PDT 24
Finished Jul 16 07:09:52 PM PDT 24
Peak memory 206888 kb
Host smart-cc452297-9c68-47ff-8af6-fdea0cc19b4a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225748734 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.4225748734
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3497587117
Short name T1113
Test name
Test status
Simulation time 250988987 ps
CPU time 6.27 seconds
Started Jul 16 07:09:48 PM PDT 24
Finished Jul 16 07:09:57 PM PDT 24
Peak memory 206900 kb
Host smart-46509f60-a6bc-443e-8e2f-2704cbf624cb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497587117 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.3497587117
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.895317126
Short name T1126
Test name
Test status
Simulation time 41742804 ps
CPU time 0.86 seconds
Started Jul 16 07:09:45 PM PDT 24
Finished Jul 16 07:09:47 PM PDT 24
Peak memory 206740 kb
Host smart-fb90cd34-1932-40ee-8c58-ee39dc69b99f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895317126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.895317126
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1383744812
Short name T1023
Test name
Test status
Simulation time 22488063 ps
CPU time 1.19 seconds
Started Jul 16 07:09:46 PM PDT 24
Finished Jul 16 07:09:49 PM PDT 24
Peak memory 215148 kb
Host smart-13c23159-564c-4783-80ba-7fd506a25583
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383744812 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.1383744812
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.2152113355
Short name T1087
Test name
Test status
Simulation time 11000178 ps
CPU time 0.85 seconds
Started Jul 16 07:09:36 PM PDT 24
Finished Jul 16 07:09:38 PM PDT 24
Peak memory 206868 kb
Host smart-393f7482-3bd3-4776-942c-759b1b7fd799
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152113355 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.2152113355
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2264782866
Short name T1027
Test name
Test status
Simulation time 54601277 ps
CPU time 1.23 seconds
Started Jul 16 07:09:44 PM PDT 24
Finished Jul 16 07:09:46 PM PDT 24
Peak memory 206900 kb
Host smart-2d5ce706-6ba7-4794-b7fe-041106657e26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264782866 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.2264782866
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.2604133962
Short name T1009
Test name
Test status
Simulation time 46321756 ps
CPU time 1.95 seconds
Started Jul 16 07:09:35 PM PDT 24
Finished Jul 16 07:09:37 PM PDT 24
Peak memory 215152 kb
Host smart-9a4cf298-1483-4081-ae9c-029e706431a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604133962 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.2604133962
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.683480983
Short name T267
Test name
Test status
Simulation time 95902197 ps
CPU time 1.61 seconds
Started Jul 16 07:09:33 PM PDT 24
Finished Jul 16 07:09:36 PM PDT 24
Peak memory 206904 kb
Host smart-616b0c5b-db00-4733-b613-2a7d6678070b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683480983 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.683480983
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.513824880
Short name T999
Test name
Test status
Simulation time 255212219 ps
CPU time 3.55 seconds
Started Jul 16 07:09:50 PM PDT 24
Finished Jul 16 07:09:56 PM PDT 24
Peak memory 206944 kb
Host smart-063fe768-1326-4c01-aee1-702dfae5199f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513824880 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.513824880
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1107998038
Short name T1019
Test name
Test status
Simulation time 56039236 ps
CPU time 0.82 seconds
Started Jul 16 07:09:49 PM PDT 24
Finished Jul 16 07:09:53 PM PDT 24
Peak memory 206676 kb
Host smart-0d8d9585-5e74-4361-b9ee-ea9bfb0dddf7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107998038 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1107998038
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2915285937
Short name T1038
Test name
Test status
Simulation time 79246014 ps
CPU time 1.04 seconds
Started Jul 16 07:09:47 PM PDT 24
Finished Jul 16 07:09:50 PM PDT 24
Peak memory 223372 kb
Host smart-78be5660-b38a-42a3-8c64-9edc65bc4c89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915285937 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2915285937
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.2897856952
Short name T1012
Test name
Test status
Simulation time 29271019 ps
CPU time 0.89 seconds
Started Jul 16 07:09:47 PM PDT 24
Finished Jul 16 07:09:49 PM PDT 24
Peak memory 206900 kb
Host smart-b4d0757e-7c5e-4c52-9089-de7f2553c455
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897856952 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.2897856952
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3715758362
Short name T1014
Test name
Test status
Simulation time 42496650 ps
CPU time 0.84 seconds
Started Jul 16 07:09:51 PM PDT 24
Finished Jul 16 07:09:55 PM PDT 24
Peak memory 206848 kb
Host smart-ac9a472b-ab49-4f20-8829-6c133f9a99f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715758362 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3715758362
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.195711383
Short name T258
Test name
Test status
Simulation time 25543595 ps
CPU time 1.21 seconds
Started Jul 16 07:09:45 PM PDT 24
Finished Jul 16 07:09:47 PM PDT 24
Peak memory 206892 kb
Host smart-44081325-bc49-4798-a660-69d0a4986736
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195711383 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_out
standing.195711383
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.4263031331
Short name T1015
Test name
Test status
Simulation time 70691521 ps
CPU time 2.62 seconds
Started Jul 16 07:09:45 PM PDT 24
Finished Jul 16 07:09:48 PM PDT 24
Peak memory 215188 kb
Host smart-7c48f7ea-e75c-4588-ad2f-5b3d413c8a20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263031331 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.4263031331
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.845811620
Short name T273
Test name
Test status
Simulation time 95029858 ps
CPU time 2.46 seconds
Started Jul 16 07:09:49 PM PDT 24
Finished Jul 16 07:09:54 PM PDT 24
Peak memory 215200 kb
Host smart-bf1d12dc-e428-4d26-b90b-8b15efe23188
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845811620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.845811620
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.4003151138
Short name T1001
Test name
Test status
Simulation time 24651675 ps
CPU time 1.55 seconds
Started Jul 16 07:10:00 PM PDT 24
Finished Jul 16 07:10:03 PM PDT 24
Peak memory 215328 kb
Host smart-f1be7ffc-27a3-4b25-8715-7e5097fb1696
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003151138 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.4003151138
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.1981091540
Short name T1047
Test name
Test status
Simulation time 144288085 ps
CPU time 0.97 seconds
Started Jul 16 07:10:03 PM PDT 24
Finished Jul 16 07:10:06 PM PDT 24
Peak memory 206932 kb
Host smart-3f32787c-ecb5-4c32-ba5b-f9188fbef036
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981091540 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1981091540
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.145751234
Short name T1103
Test name
Test status
Simulation time 12669658 ps
CPU time 0.84 seconds
Started Jul 16 07:09:59 PM PDT 24
Finished Jul 16 07:10:02 PM PDT 24
Peak memory 206800 kb
Host smart-2dea4ef6-4996-4c7c-8a72-d689858d5c0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145751234 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.145751234
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.906777481
Short name T260
Test name
Test status
Simulation time 18672125 ps
CPU time 1.21 seconds
Started Jul 16 07:10:00 PM PDT 24
Finished Jul 16 07:10:04 PM PDT 24
Peak memory 206916 kb
Host smart-afa3f13d-7424-4946-86f3-f3d7e9ad90c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906777481 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_ou
tstanding.906777481
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.3705616232
Short name T1054
Test name
Test status
Simulation time 319069934 ps
CPU time 2.3 seconds
Started Jul 16 07:09:56 PM PDT 24
Finished Jul 16 07:09:59 PM PDT 24
Peak memory 215344 kb
Host smart-73307c20-0ab9-44a5-b402-b7ae7967c5ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705616232 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.3705616232
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2445692895
Short name T1003
Test name
Test status
Simulation time 155636636 ps
CPU time 1.66 seconds
Started Jul 16 07:09:59 PM PDT 24
Finished Jul 16 07:10:02 PM PDT 24
Peak memory 207040 kb
Host smart-d999a38b-40a6-46cc-86b7-88ffcee7244a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445692895 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.2445692895
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3771904230
Short name T1110
Test name
Test status
Simulation time 23312206 ps
CPU time 1.23 seconds
Started Jul 16 07:10:04 PM PDT 24
Finished Jul 16 07:10:08 PM PDT 24
Peak memory 217948 kb
Host smart-1a8280c6-7ae1-47c9-b34d-4260b1831795
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771904230 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3771904230
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.3697573331
Short name T252
Test name
Test status
Simulation time 22356098 ps
CPU time 0.87 seconds
Started Jul 16 07:09:58 PM PDT 24
Finished Jul 16 07:10:01 PM PDT 24
Peak memory 206852 kb
Host smart-a8e36732-2fe2-4ed1-b3a7-a715ec0100f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697573331 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3697573331
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.2307027269
Short name T1075
Test name
Test status
Simulation time 28423714 ps
CPU time 0.86 seconds
Started Jul 16 07:09:57 PM PDT 24
Finished Jul 16 07:10:00 PM PDT 24
Peak memory 206848 kb
Host smart-af1ad850-7792-4b35-b468-5e1b1919f615
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307027269 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2307027269
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1250635342
Short name T1031
Test name
Test status
Simulation time 19115349 ps
CPU time 1.05 seconds
Started Jul 16 07:09:59 PM PDT 24
Finished Jul 16 07:10:03 PM PDT 24
Peak memory 206880 kb
Host smart-04a21405-be69-4b64-ac0b-aed2bb39d8e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250635342 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.1250635342
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.3767655466
Short name T1095
Test name
Test status
Simulation time 70327608 ps
CPU time 1.78 seconds
Started Jul 16 07:09:59 PM PDT 24
Finished Jul 16 07:10:03 PM PDT 24
Peak memory 215280 kb
Host smart-efa01614-ea85-4294-88a4-c66cb956245e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767655466 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3767655466
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1997091149
Short name T1129
Test name
Test status
Simulation time 289738962 ps
CPU time 2.22 seconds
Started Jul 16 07:10:01 PM PDT 24
Finished Jul 16 07:10:06 PM PDT 24
Peak memory 206960 kb
Host smart-cc9c60d1-eede-4c74-8c7f-ed7a38ddbafe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997091149 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1997091149
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.935336902
Short name T1102
Test name
Test status
Simulation time 37919383 ps
CPU time 1.65 seconds
Started Jul 16 07:09:58 PM PDT 24
Finished Jul 16 07:10:00 PM PDT 24
Peak memory 215232 kb
Host smart-51c3914e-61e3-49e1-a0b2-fbae3842d03d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935336902 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.935336902
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.3681265087
Short name T1020
Test name
Test status
Simulation time 86462613 ps
CPU time 0.82 seconds
Started Jul 16 07:09:58 PM PDT 24
Finished Jul 16 07:10:00 PM PDT 24
Peak memory 206628 kb
Host smart-0bb6de48-b524-463a-8f5a-752e43fd421b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681265087 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.3681265087
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.2947946260
Short name T1127
Test name
Test status
Simulation time 39868569 ps
CPU time 0.81 seconds
Started Jul 16 07:09:59 PM PDT 24
Finished Jul 16 07:10:01 PM PDT 24
Peak memory 206684 kb
Host smart-8198751a-7a2a-4ebe-bc10-1fb404b6ed4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947946260 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2947946260
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3609160511
Short name T241
Test name
Test status
Simulation time 64328597 ps
CPU time 1.44 seconds
Started Jul 16 07:10:01 PM PDT 24
Finished Jul 16 07:10:06 PM PDT 24
Peak memory 206908 kb
Host smart-6a41bb0e-85c0-41b4-af3f-2039b9985ed1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609160511 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.3609160511
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.2981329267
Short name T1069
Test name
Test status
Simulation time 25844092 ps
CPU time 1.79 seconds
Started Jul 16 07:10:02 PM PDT 24
Finished Jul 16 07:10:07 PM PDT 24
Peak memory 215196 kb
Host smart-df3964c2-62f8-4404-bd54-0bbbeed67b16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981329267 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.2981329267
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.83506511
Short name T1121
Test name
Test status
Simulation time 175436199 ps
CPU time 1.19 seconds
Started Jul 16 07:10:03 PM PDT 24
Finished Jul 16 07:10:07 PM PDT 24
Peak memory 215148 kb
Host smart-fa3ca217-0093-488b-b183-7bfd55018b21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83506511 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.83506511
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.1432851783
Short name T1092
Test name
Test status
Simulation time 13499569 ps
CPU time 0.89 seconds
Started Jul 16 07:10:20 PM PDT 24
Finished Jul 16 07:10:22 PM PDT 24
Peak memory 206884 kb
Host smart-5d244b74-d257-48d5-bb98-fe4fb0348a6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432851783 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1432851783
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.2820291431
Short name T1108
Test name
Test status
Simulation time 68953751 ps
CPU time 0.81 seconds
Started Jul 16 07:10:05 PM PDT 24
Finished Jul 16 07:10:08 PM PDT 24
Peak memory 206656 kb
Host smart-65d4b39a-11d1-49fc-875a-2755d0aef1d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820291431 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.2820291431
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3658733590
Short name T1105
Test name
Test status
Simulation time 128359839 ps
CPU time 1.43 seconds
Started Jul 16 07:09:58 PM PDT 24
Finished Jul 16 07:10:00 PM PDT 24
Peak memory 206876 kb
Host smart-e7795d34-c932-4a98-aeaf-1fe4c9709555
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658733590 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.3658733590
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.2475636535
Short name T1016
Test name
Test status
Simulation time 89414665 ps
CPU time 2.66 seconds
Started Jul 16 07:09:58 PM PDT 24
Finished Jul 16 07:10:02 PM PDT 24
Peak memory 215216 kb
Host smart-af081a5a-3aec-4ce8-8de2-bd2d9ebda7ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475636535 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2475636535
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1339121340
Short name T1085
Test name
Test status
Simulation time 162991076 ps
CPU time 1.54 seconds
Started Jul 16 07:09:56 PM PDT 24
Finished Jul 16 07:09:58 PM PDT 24
Peak memory 206940 kb
Host smart-64882b3e-9a6f-497e-8cb5-e262b9deedde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339121340 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1339121340
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3227100855
Short name T1115
Test name
Test status
Simulation time 28662910 ps
CPU time 1.36 seconds
Started Jul 16 07:10:01 PM PDT 24
Finished Jul 16 07:10:06 PM PDT 24
Peak memory 217556 kb
Host smart-00012310-b23d-436b-8cd2-dad5c8b1c45b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227100855 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.3227100855
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.3493003220
Short name T246
Test name
Test status
Simulation time 96457294 ps
CPU time 0.84 seconds
Started Jul 16 07:09:59 PM PDT 24
Finished Jul 16 07:10:01 PM PDT 24
Peak memory 206736 kb
Host smart-0e29e572-2fa5-46fa-ad6d-9eb03a3ee222
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493003220 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.3493003220
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.2390028924
Short name T1073
Test name
Test status
Simulation time 14963340 ps
CPU time 0.93 seconds
Started Jul 16 07:09:59 PM PDT 24
Finished Jul 16 07:10:02 PM PDT 24
Peak memory 206788 kb
Host smart-be4c16b4-5117-4cdc-b19f-dbcf8a23969a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390028924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.2390028924
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.97495776
Short name T1039
Test name
Test status
Simulation time 128871816 ps
CPU time 1.16 seconds
Started Jul 16 07:10:02 PM PDT 24
Finished Jul 16 07:10:06 PM PDT 24
Peak memory 206920 kb
Host smart-f086bdc9-ea53-4ddd-896b-17b59b84649e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97495776 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_out
standing.97495776
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.3074350805
Short name T1064
Test name
Test status
Simulation time 397397533 ps
CPU time 2.42 seconds
Started Jul 16 07:09:57 PM PDT 24
Finished Jul 16 07:10:01 PM PDT 24
Peak memory 215244 kb
Host smart-fca7bb55-5180-45a8-a5e7-91c70a997a5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074350805 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3074350805
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2642521499
Short name T1091
Test name
Test status
Simulation time 87790246 ps
CPU time 1.64 seconds
Started Jul 16 07:09:58 PM PDT 24
Finished Jul 16 07:10:01 PM PDT 24
Peak memory 206852 kb
Host smart-0e724577-ab3c-41bc-8dd4-fb9c995d024f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642521499 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.2642521499
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3464957068
Short name T1018
Test name
Test status
Simulation time 15958136 ps
CPU time 1.09 seconds
Started Jul 16 07:09:58 PM PDT 24
Finished Jul 16 07:10:00 PM PDT 24
Peak memory 215248 kb
Host smart-9159cbfb-6db9-4c41-b0eb-3d95c7117aa2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464957068 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.3464957068
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.1485726443
Short name T1124
Test name
Test status
Simulation time 13256590 ps
CPU time 0.88 seconds
Started Jul 16 07:10:03 PM PDT 24
Finished Jul 16 07:10:07 PM PDT 24
Peak memory 206876 kb
Host smart-25fc6858-0b5a-4e97-8784-ba0e0e931f58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485726443 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1485726443
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.364579052
Short name T1021
Test name
Test status
Simulation time 13082422 ps
CPU time 0.86 seconds
Started Jul 16 07:10:02 PM PDT 24
Finished Jul 16 07:10:06 PM PDT 24
Peak memory 206856 kb
Host smart-81101844-74a5-4d3f-9d63-e345a3b18d4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364579052 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.364579052
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1513827385
Short name T1062
Test name
Test status
Simulation time 235744248 ps
CPU time 1.34 seconds
Started Jul 16 07:10:01 PM PDT 24
Finished Jul 16 07:10:06 PM PDT 24
Peak memory 206928 kb
Host smart-63c20fa8-fc28-490b-875f-528c9a76072c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513827385 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.1513827385
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.220872745
Short name T1032
Test name
Test status
Simulation time 113081873 ps
CPU time 3.87 seconds
Started Jul 16 07:10:00 PM PDT 24
Finished Jul 16 07:10:07 PM PDT 24
Peak memory 215148 kb
Host smart-95782a86-4762-42db-866b-f1c3e5bf0c93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220872745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.220872745
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2251645821
Short name T1053
Test name
Test status
Simulation time 157105829 ps
CPU time 1.51 seconds
Started Jul 16 07:09:59 PM PDT 24
Finished Jul 16 07:10:03 PM PDT 24
Peak memory 215288 kb
Host smart-a648a840-07f5-47d4-a5bb-3fd44f788701
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251645821 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2251645821
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3243451744
Short name T1025
Test name
Test status
Simulation time 35114745 ps
CPU time 1.5 seconds
Started Jul 16 07:10:03 PM PDT 24
Finished Jul 16 07:10:08 PM PDT 24
Peak memory 218192 kb
Host smart-29a12aa9-513f-48a4-b394-e087e1425ac7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243451744 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.3243451744
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.2192017618
Short name T250
Test name
Test status
Simulation time 68957740 ps
CPU time 0.93 seconds
Started Jul 16 07:10:00 PM PDT 24
Finished Jul 16 07:10:04 PM PDT 24
Peak memory 206928 kb
Host smart-512b353f-cb70-48f7-a8ca-1c2b8fada178
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192017618 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.2192017618
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3092284239
Short name T1096
Test name
Test status
Simulation time 51411970 ps
CPU time 0.85 seconds
Started Jul 16 07:10:03 PM PDT 24
Finished Jul 16 07:10:07 PM PDT 24
Peak memory 206824 kb
Host smart-9bd5579d-ee19-4c34-9e07-492320a73e9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092284239 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3092284239
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2096413423
Short name T1074
Test name
Test status
Simulation time 121717880 ps
CPU time 1.11 seconds
Started Jul 16 07:09:57 PM PDT 24
Finished Jul 16 07:09:59 PM PDT 24
Peak memory 206868 kb
Host smart-b01f6877-b670-4d8a-8d0c-d87400e1d628
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096413423 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.2096413423
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.3468097296
Short name T1060
Test name
Test status
Simulation time 55848762 ps
CPU time 1.94 seconds
Started Jul 16 07:10:00 PM PDT 24
Finished Jul 16 07:10:04 PM PDT 24
Peak memory 215180 kb
Host smart-ec5adc18-e187-4562-a211-5d925177e7df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468097296 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3468097296
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3739681282
Short name T265
Test name
Test status
Simulation time 41728430 ps
CPU time 1.48 seconds
Started Jul 16 07:09:58 PM PDT 24
Finished Jul 16 07:10:01 PM PDT 24
Peak memory 207048 kb
Host smart-a89c995d-8cb5-4f95-8459-3dee2bcc7e07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739681282 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.3739681282
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1788189245
Short name T1024
Test name
Test status
Simulation time 108796836 ps
CPU time 2.15 seconds
Started Jul 16 07:10:03 PM PDT 24
Finished Jul 16 07:10:08 PM PDT 24
Peak memory 215144 kb
Host smart-b606ab0e-fb4a-48bd-80a2-924e5796b17f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788189245 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.1788189245
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.3313779305
Short name T240
Test name
Test status
Simulation time 16690899 ps
CPU time 0.91 seconds
Started Jul 16 07:10:00 PM PDT 24
Finished Jul 16 07:10:04 PM PDT 24
Peak memory 206920 kb
Host smart-f25e70e7-481f-43e9-a8ee-77cc21482b0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313779305 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.3313779305
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.4213626034
Short name T1026
Test name
Test status
Simulation time 13977743 ps
CPU time 0.84 seconds
Started Jul 16 07:10:00 PM PDT 24
Finished Jul 16 07:10:04 PM PDT 24
Peak memory 206856 kb
Host smart-b10d1057-a465-4719-b71a-fe0de5cacd8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213626034 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.4213626034
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.258128332
Short name T1077
Test name
Test status
Simulation time 56721308 ps
CPU time 1.15 seconds
Started Jul 16 07:10:00 PM PDT 24
Finished Jul 16 07:10:04 PM PDT 24
Peak memory 206996 kb
Host smart-f858cea6-841d-45bd-8b87-6e738a7838d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258128332 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_ou
tstanding.258128332
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.2835379501
Short name T1088
Test name
Test status
Simulation time 50326248 ps
CPU time 1.82 seconds
Started Jul 16 07:09:58 PM PDT 24
Finished Jul 16 07:10:00 PM PDT 24
Peak memory 215356 kb
Host smart-c8adb649-9328-4165-a4e5-77f60a5cecee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835379501 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.2835379501
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2978638909
Short name T1116
Test name
Test status
Simulation time 55958916 ps
CPU time 1.31 seconds
Started Jul 16 07:10:00 PM PDT 24
Finished Jul 16 07:10:05 PM PDT 24
Peak memory 217740 kb
Host smart-15d98b96-be9a-44ab-869c-48390e797e8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978638909 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.2978638909
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.411824347
Short name T256
Test name
Test status
Simulation time 14852614 ps
CPU time 0.95 seconds
Started Jul 16 07:10:00 PM PDT 24
Finished Jul 16 07:10:03 PM PDT 24
Peak memory 206912 kb
Host smart-1f361ad3-9aa1-4330-84dc-8a81e036fc05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411824347 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.411824347
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2071312503
Short name T997
Test name
Test status
Simulation time 87086168 ps
CPU time 0.87 seconds
Started Jul 16 07:10:00 PM PDT 24
Finished Jul 16 07:10:04 PM PDT 24
Peak memory 206872 kb
Host smart-5e4e4cf9-2f8b-438c-a641-d491ea30f678
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071312503 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2071312503
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2203775323
Short name T1068
Test name
Test status
Simulation time 109772295 ps
CPU time 1.33 seconds
Started Jul 16 07:09:59 PM PDT 24
Finished Jul 16 07:10:02 PM PDT 24
Peak memory 207020 kb
Host smart-f56ec459-b8e1-4bb4-9bc2-5d58b477d2cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203775323 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.2203775323
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.1650258869
Short name T1045
Test name
Test status
Simulation time 52904951 ps
CPU time 3.65 seconds
Started Jul 16 07:10:03 PM PDT 24
Finished Jul 16 07:10:09 PM PDT 24
Peak memory 223332 kb
Host smart-506bab25-e23c-49a4-8546-d47fa7f1fbe5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650258869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.1650258869
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3366323160
Short name T1033
Test name
Test status
Simulation time 283907668 ps
CPU time 3.28 seconds
Started Jul 16 07:10:03 PM PDT 24
Finished Jul 16 07:10:09 PM PDT 24
Peak memory 207036 kb
Host smart-d375c227-d16c-4ff7-92ea-5243fc0d00ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366323160 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.3366323160
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.66069764
Short name T1011
Test name
Test status
Simulation time 52354659 ps
CPU time 1.28 seconds
Started Jul 16 07:10:03 PM PDT 24
Finished Jul 16 07:10:07 PM PDT 24
Peak memory 223356 kb
Host smart-37f8d117-472b-47e7-90b2-83016c8bd296
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66069764 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.66069764
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.3563652556
Short name T248
Test name
Test status
Simulation time 14263574 ps
CPU time 0.92 seconds
Started Jul 16 07:10:01 PM PDT 24
Finished Jul 16 07:10:05 PM PDT 24
Peak memory 206848 kb
Host smart-13486317-6c95-4ad5-bbdc-50c1a9beca0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563652556 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.3563652556
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.4279330738
Short name T1093
Test name
Test status
Simulation time 10930434 ps
CPU time 0.85 seconds
Started Jul 16 07:10:01 PM PDT 24
Finished Jul 16 07:10:04 PM PDT 24
Peak memory 206796 kb
Host smart-ffd1695f-fc68-4d02-bf90-a363e6651052
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279330738 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.4279330738
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3943535782
Short name T1089
Test name
Test status
Simulation time 21231787 ps
CPU time 1.14 seconds
Started Jul 16 07:10:01 PM PDT 24
Finished Jul 16 07:10:05 PM PDT 24
Peak memory 206844 kb
Host smart-e67ed765-e24b-4561-b184-3923d78a21e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943535782 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.3943535782
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.275735350
Short name T1046
Test name
Test status
Simulation time 124034254 ps
CPU time 2.45 seconds
Started Jul 16 07:10:00 PM PDT 24
Finished Jul 16 07:10:05 PM PDT 24
Peak memory 215260 kb
Host smart-a56069f0-4d87-4faf-8a40-75b8c11d5a7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275735350 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.275735350
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.688673143
Short name T276
Test name
Test status
Simulation time 57834096 ps
CPU time 1.82 seconds
Started Jul 16 07:10:01 PM PDT 24
Finished Jul 16 07:10:06 PM PDT 24
Peak memory 215056 kb
Host smart-47a056f2-b8e6-49ca-aba1-5483bb4168ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688673143 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.688673143
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.495809742
Short name T247
Test name
Test status
Simulation time 33090926 ps
CPU time 1.53 seconds
Started Jul 16 07:09:48 PM PDT 24
Finished Jul 16 07:09:52 PM PDT 24
Peak memory 206884 kb
Host smart-e94a415d-a27d-49cc-8921-f302d57b3cd1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495809742 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.495809742
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1425726204
Short name T1040
Test name
Test status
Simulation time 88181702 ps
CPU time 2.99 seconds
Started Jul 16 07:09:45 PM PDT 24
Finished Jul 16 07:09:50 PM PDT 24
Peak memory 207008 kb
Host smart-d24fda2a-edfd-4107-8e20-9fb3a0a8299f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425726204 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1425726204
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3208444231
Short name T245
Test name
Test status
Simulation time 18424650 ps
CPU time 0.95 seconds
Started Jul 16 07:09:48 PM PDT 24
Finished Jul 16 07:09:51 PM PDT 24
Peak memory 206840 kb
Host smart-e687eaa7-63a6-41af-b092-496aa88dd243
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208444231 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3208444231
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.731987660
Short name T1055
Test name
Test status
Simulation time 82392480 ps
CPU time 1.25 seconds
Started Jul 16 07:09:49 PM PDT 24
Finished Jul 16 07:09:53 PM PDT 24
Peak memory 217776 kb
Host smart-ff51ecd2-b401-4d6d-8120-5a440c405a9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731987660 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.731987660
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.3142281375
Short name T1028
Test name
Test status
Simulation time 15410766 ps
CPU time 0.93 seconds
Started Jul 16 07:09:47 PM PDT 24
Finished Jul 16 07:09:50 PM PDT 24
Peak memory 206876 kb
Host smart-facf477c-246b-4707-928d-5be17bf229da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142281375 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3142281375
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.4146584307
Short name T1049
Test name
Test status
Simulation time 30440559 ps
CPU time 0.79 seconds
Started Jul 16 07:09:51 PM PDT 24
Finished Jul 16 07:09:55 PM PDT 24
Peak memory 206696 kb
Host smart-99a66948-0dc5-411d-9e11-9d50a713f5dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146584307 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.4146584307
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2897107703
Short name T254
Test name
Test status
Simulation time 61664607 ps
CPU time 1.42 seconds
Started Jul 16 07:09:46 PM PDT 24
Finished Jul 16 07:09:49 PM PDT 24
Peak memory 206904 kb
Host smart-028a45c8-3f08-4b7a-ac9c-0123b413b2e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897107703 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.2897107703
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.3770406793
Short name T1005
Test name
Test status
Simulation time 20895846 ps
CPU time 1.57 seconds
Started Jul 16 07:09:50 PM PDT 24
Finished Jul 16 07:09:55 PM PDT 24
Peak memory 215248 kb
Host smart-9d82fa92-fed8-4c61-a54b-ec1f0b2b2687
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770406793 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.3770406793
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1954837341
Short name T266
Test name
Test status
Simulation time 545142011 ps
CPU time 2.25 seconds
Started Jul 16 07:09:47 PM PDT 24
Finished Jul 16 07:09:51 PM PDT 24
Peak memory 206876 kb
Host smart-56e63255-67c1-4060-8e27-bc1db19540f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954837341 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1954837341
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.4266619421
Short name T1112
Test name
Test status
Simulation time 22598642 ps
CPU time 0.88 seconds
Started Jul 16 07:10:02 PM PDT 24
Finished Jul 16 07:10:06 PM PDT 24
Peak memory 206820 kb
Host smart-b199edd9-6397-48d4-bc0b-08c1ed9adf70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266619421 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.4266619421
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.1582109995
Short name T1106
Test name
Test status
Simulation time 19071517 ps
CPU time 0.86 seconds
Started Jul 16 07:09:59 PM PDT 24
Finished Jul 16 07:10:02 PM PDT 24
Peak memory 206784 kb
Host smart-7c94e616-1f2c-43cf-86c6-942a10b18521
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582109995 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.1582109995
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.4099498470
Short name T1022
Test name
Test status
Simulation time 17010018 ps
CPU time 0.86 seconds
Started Jul 16 07:10:02 PM PDT 24
Finished Jul 16 07:10:06 PM PDT 24
Peak memory 206688 kb
Host smart-de79973d-d341-4867-9258-e8eb312c6b6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099498470 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.4099498470
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.4241050280
Short name T1125
Test name
Test status
Simulation time 28349752 ps
CPU time 0.86 seconds
Started Jul 16 07:10:02 PM PDT 24
Finished Jul 16 07:10:06 PM PDT 24
Peak memory 206696 kb
Host smart-67e68e1d-b9ab-4870-99e6-bf1045c6c798
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241050280 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.4241050280
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.2498242953
Short name T1059
Test name
Test status
Simulation time 27635381 ps
CPU time 0.86 seconds
Started Jul 16 07:10:25 PM PDT 24
Finished Jul 16 07:10:27 PM PDT 24
Peak memory 206832 kb
Host smart-d9c16edf-faa9-43a3-8d67-78dc49d3134e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498242953 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.2498242953
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.523148475
Short name T1010
Test name
Test status
Simulation time 12307285 ps
CPU time 0.84 seconds
Started Jul 16 07:09:58 PM PDT 24
Finished Jul 16 07:10:00 PM PDT 24
Peak memory 206824 kb
Host smart-ba1d73f4-ec18-4d12-87a9-45173179c68c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523148475 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.523148475
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.2399254151
Short name T1042
Test name
Test status
Simulation time 46166602 ps
CPU time 0.79 seconds
Started Jul 16 07:09:59 PM PDT 24
Finished Jul 16 07:10:01 PM PDT 24
Peak memory 206728 kb
Host smart-104aea1c-fe4c-4ef9-befb-b1b14a6f5050
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399254151 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2399254151
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.4255710467
Short name T1004
Test name
Test status
Simulation time 13117733 ps
CPU time 0.89 seconds
Started Jul 16 07:10:05 PM PDT 24
Finished Jul 16 07:10:08 PM PDT 24
Peak memory 206856 kb
Host smart-88dad89f-0bcc-4453-a3c0-6c2edf894651
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255710467 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.4255710467
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2673011506
Short name T1044
Test name
Test status
Simulation time 37871787 ps
CPU time 0.82 seconds
Started Jul 16 07:10:05 PM PDT 24
Finished Jul 16 07:10:08 PM PDT 24
Peak memory 206652 kb
Host smart-b83f3e79-3d73-4fed-850b-2e0df8bd7a96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673011506 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2673011506
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.3160526421
Short name T1114
Test name
Test status
Simulation time 93308226 ps
CPU time 0.85 seconds
Started Jul 16 07:10:05 PM PDT 24
Finished Jul 16 07:10:08 PM PDT 24
Peak memory 206680 kb
Host smart-c9d9cd96-158b-4e77-b438-03208e44e3da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160526421 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.3160526421
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2576645799
Short name T253
Test name
Test status
Simulation time 47158091 ps
CPU time 1.18 seconds
Started Jul 16 07:09:48 PM PDT 24
Finished Jul 16 07:09:52 PM PDT 24
Peak memory 206896 kb
Host smart-a307184e-d870-4f87-ab24-0247b694ef59
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576645799 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.2576645799
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2899594572
Short name T1048
Test name
Test status
Simulation time 4300720245 ps
CPU time 6.22 seconds
Started Jul 16 07:09:46 PM PDT 24
Finished Jul 16 07:09:54 PM PDT 24
Peak memory 207036 kb
Host smart-f473842b-5609-4ee6-aa3b-90d7a2ff0099
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899594572 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.2899594572
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.473335955
Short name T1118
Test name
Test status
Simulation time 67133605 ps
CPU time 0.99 seconds
Started Jul 16 07:09:47 PM PDT 24
Finished Jul 16 07:09:49 PM PDT 24
Peak memory 206844 kb
Host smart-4b4854cd-b58b-4680-be23-5e5183b40ac9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473335955 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.473335955
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1973973687
Short name T1007
Test name
Test status
Simulation time 92900798 ps
CPU time 1.63 seconds
Started Jul 16 07:09:47 PM PDT 24
Finished Jul 16 07:09:50 PM PDT 24
Peak memory 215280 kb
Host smart-16434a61-16eb-48cf-ad19-58100c5782d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973973687 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.1973973687
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1956906167
Short name T1107
Test name
Test status
Simulation time 17497996 ps
CPU time 0.94 seconds
Started Jul 16 07:09:50 PM PDT 24
Finished Jul 16 07:09:54 PM PDT 24
Peak memory 206924 kb
Host smart-9c744d6c-4b8a-44bd-8dab-93e44bde6e6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956906167 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1956906167
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.707117834
Short name T1002
Test name
Test status
Simulation time 13014132 ps
CPU time 0.84 seconds
Started Jul 16 07:09:45 PM PDT 24
Finished Jul 16 07:09:47 PM PDT 24
Peak memory 206788 kb
Host smart-6e27d06a-e160-49f5-98be-99696517bc34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707117834 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.707117834
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3824349147
Short name T1079
Test name
Test status
Simulation time 139974365 ps
CPU time 1.49 seconds
Started Jul 16 07:09:48 PM PDT 24
Finished Jul 16 07:09:52 PM PDT 24
Peak memory 206944 kb
Host smart-182c8086-e115-490a-bd3a-3e79d5060d5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824349147 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.3824349147
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.1067552222
Short name T1057
Test name
Test status
Simulation time 498323111 ps
CPU time 3.42 seconds
Started Jul 16 07:09:47 PM PDT 24
Finished Jul 16 07:09:51 PM PDT 24
Peak memory 215148 kb
Host smart-d1c49e8c-1376-49eb-9154-774b084f3b77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067552222 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.1067552222
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1160727053
Short name T1090
Test name
Test status
Simulation time 587095143 ps
CPU time 2.28 seconds
Started Jul 16 07:09:51 PM PDT 24
Finished Jul 16 07:09:57 PM PDT 24
Peak memory 207164 kb
Host smart-91c587c6-74b9-4b93-bd44-bfa38875ef7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160727053 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.1160727053
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.3421793658
Short name T1008
Test name
Test status
Simulation time 17560876 ps
CPU time 0.87 seconds
Started Jul 16 07:10:04 PM PDT 24
Finished Jul 16 07:10:08 PM PDT 24
Peak memory 206832 kb
Host smart-45f9165d-e63a-4903-a52f-5e503ca1375c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421793658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.3421793658
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.1486077524
Short name T1122
Test name
Test status
Simulation time 21326571 ps
CPU time 0.85 seconds
Started Jul 16 07:10:06 PM PDT 24
Finished Jul 16 07:10:08 PM PDT 24
Peak memory 206856 kb
Host smart-409de561-cbcd-4c7f-ac1a-0d2fa473f261
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486077524 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.1486077524
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.1172287878
Short name T1098
Test name
Test status
Simulation time 17067780 ps
CPU time 1 seconds
Started Jul 16 07:10:02 PM PDT 24
Finished Jul 16 07:10:06 PM PDT 24
Peak memory 206744 kb
Host smart-e9a00646-0703-4fe1-b92a-910078d31eb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172287878 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.1172287878
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.2030677268
Short name T1036
Test name
Test status
Simulation time 28599124 ps
CPU time 0.9 seconds
Started Jul 16 07:10:02 PM PDT 24
Finished Jul 16 07:10:06 PM PDT 24
Peak memory 206744 kb
Host smart-12fe74d5-6eb6-43ce-af9a-7863d918d5f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030677268 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2030677268
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.3100422687
Short name T1029
Test name
Test status
Simulation time 12915813 ps
CPU time 0.84 seconds
Started Jul 16 07:10:13 PM PDT 24
Finished Jul 16 07:10:15 PM PDT 24
Peak memory 206828 kb
Host smart-85f5d9e9-6ba1-4531-abe9-4da75bd402a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100422687 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3100422687
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.956028317
Short name T1094
Test name
Test status
Simulation time 140244277 ps
CPU time 0.87 seconds
Started Jul 16 07:10:14 PM PDT 24
Finished Jul 16 07:10:16 PM PDT 24
Peak memory 206776 kb
Host smart-2117a5dc-c27f-4078-b2c8-67c0a43b3af8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956028317 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.956028317
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.528267001
Short name T1000
Test name
Test status
Simulation time 21347958 ps
CPU time 0.82 seconds
Started Jul 16 07:10:20 PM PDT 24
Finished Jul 16 07:10:22 PM PDT 24
Peak memory 206800 kb
Host smart-b40657af-5802-444a-a598-da32a93a24af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528267001 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.528267001
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.4118037457
Short name T1080
Test name
Test status
Simulation time 16248915 ps
CPU time 0.93 seconds
Started Jul 16 07:10:10 PM PDT 24
Finished Jul 16 07:10:12 PM PDT 24
Peak memory 206812 kb
Host smart-52ae766f-f90b-494a-b3d9-460983e6eeb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118037457 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.4118037457
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.1463137918
Short name T1050
Test name
Test status
Simulation time 20258126 ps
CPU time 0.82 seconds
Started Jul 16 07:10:19 PM PDT 24
Finished Jul 16 07:10:21 PM PDT 24
Peak memory 206812 kb
Host smart-2fec88a0-3f27-4292-ac56-7759d9209be9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463137918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1463137918
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.217635023
Short name T1072
Test name
Test status
Simulation time 19434038 ps
CPU time 0.9 seconds
Started Jul 16 07:10:11 PM PDT 24
Finished Jul 16 07:10:13 PM PDT 24
Peak memory 206828 kb
Host smart-a925f9c1-a15a-40b3-9230-0bf2aa4daf13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217635023 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.217635023
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2037691336
Short name T249
Test name
Test status
Simulation time 34788449 ps
CPU time 1.17 seconds
Started Jul 16 07:09:46 PM PDT 24
Finished Jul 16 07:09:49 PM PDT 24
Peak memory 206860 kb
Host smart-95a79cec-46cd-420f-896c-b725e6b56ba7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037691336 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.2037691336
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1387876921
Short name T1056
Test name
Test status
Simulation time 124338093 ps
CPU time 2.04 seconds
Started Jul 16 07:09:47 PM PDT 24
Finished Jul 16 07:09:51 PM PDT 24
Peak memory 206960 kb
Host smart-dbd04f9d-b503-44c6-81b9-60abfc84410d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387876921 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.1387876921
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2774015934
Short name T1065
Test name
Test status
Simulation time 26815951 ps
CPU time 0.91 seconds
Started Jul 16 07:09:47 PM PDT 24
Finished Jul 16 07:09:50 PM PDT 24
Peak memory 206860 kb
Host smart-5bee1ff3-5052-4aca-b760-7094022f254c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774015934 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.2774015934
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.904124483
Short name T1061
Test name
Test status
Simulation time 78786317 ps
CPU time 1.19 seconds
Started Jul 16 07:09:48 PM PDT 24
Finished Jul 16 07:09:52 PM PDT 24
Peak memory 223408 kb
Host smart-30066971-9adb-4aeb-84a1-7730b27baddb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904124483 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.904124483
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.1044994353
Short name T255
Test name
Test status
Simulation time 13932565 ps
CPU time 0.95 seconds
Started Jul 16 07:09:49 PM PDT 24
Finished Jul 16 07:09:53 PM PDT 24
Peak memory 207108 kb
Host smart-3ff2cc0b-49b9-41a9-a459-5633c29ebebf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044994353 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.1044994353
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.2850491310
Short name T1030
Test name
Test status
Simulation time 25756193 ps
CPU time 0.83 seconds
Started Jul 16 07:09:49 PM PDT 24
Finished Jul 16 07:09:53 PM PDT 24
Peak memory 206848 kb
Host smart-52a9461b-dcff-4788-8896-a605d7140595
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850491310 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2850491310
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2351871322
Short name T1037
Test name
Test status
Simulation time 65622575 ps
CPU time 0.97 seconds
Started Jul 16 07:09:52 PM PDT 24
Finished Jul 16 07:09:56 PM PDT 24
Peak memory 206920 kb
Host smart-365aeb32-392b-46c8-ba08-08838d1c7880
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351871322 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.2351871322
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.4243073739
Short name T1051
Test name
Test status
Simulation time 76293668 ps
CPU time 2.77 seconds
Started Jul 16 07:09:50 PM PDT 24
Finished Jul 16 07:09:56 PM PDT 24
Peak memory 215244 kb
Host smart-a00ec81b-e0d8-462d-ba53-39f06b34b4da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243073739 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.4243073739
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3251663474
Short name T279
Test name
Test status
Simulation time 277140101 ps
CPU time 2.11 seconds
Started Jul 16 07:09:47 PM PDT 24
Finished Jul 16 07:09:51 PM PDT 24
Peak memory 206916 kb
Host smart-1a046310-e2d8-43a6-846a-1f40d401096f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251663474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.3251663474
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.955820121
Short name T1070
Test name
Test status
Simulation time 17197279 ps
CPU time 0.8 seconds
Started Jul 16 07:10:15 PM PDT 24
Finished Jul 16 07:10:17 PM PDT 24
Peak memory 206680 kb
Host smart-ea0baeaf-76d2-4eec-8773-c18f96ee833a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955820121 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.955820121
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.747790731
Short name T1017
Test name
Test status
Simulation time 19468142 ps
CPU time 0.94 seconds
Started Jul 16 07:10:14 PM PDT 24
Finished Jul 16 07:10:16 PM PDT 24
Peak memory 206820 kb
Host smart-6e9eef25-c335-48e4-8280-51658647106a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747790731 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.747790731
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.2966242114
Short name T998
Test name
Test status
Simulation time 59602586 ps
CPU time 0.8 seconds
Started Jul 16 07:10:14 PM PDT 24
Finished Jul 16 07:10:15 PM PDT 24
Peak memory 206868 kb
Host smart-d001f755-e614-433d-9507-65aabf566472
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966242114 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.2966242114
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.803578457
Short name T996
Test name
Test status
Simulation time 31403130 ps
CPU time 0.86 seconds
Started Jul 16 07:10:10 PM PDT 24
Finished Jul 16 07:10:12 PM PDT 24
Peak memory 206800 kb
Host smart-c650536a-b3d7-4c05-837b-84e76a3e9fa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803578457 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.803578457
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.3692944032
Short name T1063
Test name
Test status
Simulation time 24125989 ps
CPU time 0.85 seconds
Started Jul 16 07:10:18 PM PDT 24
Finished Jul 16 07:10:21 PM PDT 24
Peak memory 206824 kb
Host smart-5a0b3525-abe5-42c3-b2e2-32b0c53c19fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692944032 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.3692944032
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.1313107538
Short name T1035
Test name
Test status
Simulation time 42983617 ps
CPU time 0.84 seconds
Started Jul 16 07:10:12 PM PDT 24
Finished Jul 16 07:10:13 PM PDT 24
Peak memory 206804 kb
Host smart-66dabe41-0729-4dd8-94ed-7816e54cc580
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313107538 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1313107538
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.146783848
Short name T1034
Test name
Test status
Simulation time 55919490 ps
CPU time 0.86 seconds
Started Jul 16 07:10:21 PM PDT 24
Finished Jul 16 07:10:23 PM PDT 24
Peak memory 206804 kb
Host smart-e52b8be1-01c4-481b-8971-219299e48bbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146783848 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.146783848
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.1634590193
Short name T1078
Test name
Test status
Simulation time 29537220 ps
CPU time 0.89 seconds
Started Jul 16 07:10:13 PM PDT 24
Finished Jul 16 07:10:15 PM PDT 24
Peak memory 206868 kb
Host smart-69c5bd03-f598-4575-81d5-d94bbbd4a92d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634590193 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.1634590193
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.1450401284
Short name T1082
Test name
Test status
Simulation time 30746731 ps
CPU time 0.8 seconds
Started Jul 16 07:10:11 PM PDT 24
Finished Jul 16 07:10:13 PM PDT 24
Peak memory 206648 kb
Host smart-fde42dd5-6b64-4d0c-a63a-a0f6fdc97c76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450401284 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.1450401284
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.1313717761
Short name T1117
Test name
Test status
Simulation time 29743388 ps
CPU time 0.91 seconds
Started Jul 16 07:10:14 PM PDT 24
Finished Jul 16 07:10:16 PM PDT 24
Peak memory 206852 kb
Host smart-a13dd124-22c0-4d5f-be3d-ef7e97f8505d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313717761 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.1313717761
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2481075254
Short name T1067
Test name
Test status
Simulation time 24745575 ps
CPU time 1.18 seconds
Started Jul 16 07:09:49 PM PDT 24
Finished Jul 16 07:09:53 PM PDT 24
Peak memory 215176 kb
Host smart-78f5978c-ef3b-48cd-9cfe-35a980677e38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481075254 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.2481075254
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.2467020578
Short name T257
Test name
Test status
Simulation time 11539372 ps
CPU time 0.87 seconds
Started Jul 16 07:09:45 PM PDT 24
Finished Jul 16 07:09:46 PM PDT 24
Peak memory 206880 kb
Host smart-830261df-cb08-4971-80b0-a7c60946b7a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467020578 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2467020578
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.3851287919
Short name T1081
Test name
Test status
Simulation time 29541012 ps
CPU time 0.9 seconds
Started Jul 16 07:09:46 PM PDT 24
Finished Jul 16 07:09:49 PM PDT 24
Peak memory 206832 kb
Host smart-81f127e6-be31-4b6b-92c2-057b82b731af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851287919 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.3851287919
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2551868756
Short name T259
Test name
Test status
Simulation time 118292747 ps
CPU time 1.07 seconds
Started Jul 16 07:09:48 PM PDT 24
Finished Jul 16 07:09:51 PM PDT 24
Peak memory 206868 kb
Host smart-3be75476-e311-431e-b052-9f76306acda8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551868756 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.2551868756
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.4294704422
Short name T1097
Test name
Test status
Simulation time 89164721 ps
CPU time 3.29 seconds
Started Jul 16 07:09:51 PM PDT 24
Finished Jul 16 07:09:58 PM PDT 24
Peak memory 215184 kb
Host smart-383e33bb-a5fe-4a54-b0d3-366ff4e67e08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294704422 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.4294704422
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.250602092
Short name T275
Test name
Test status
Simulation time 99491377 ps
CPU time 1.44 seconds
Started Jul 16 07:09:49 PM PDT 24
Finished Jul 16 07:09:54 PM PDT 24
Peak memory 215164 kb
Host smart-e3157035-e298-4604-89af-e39ac759d16d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250602092 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.250602092
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.223622001
Short name T1058
Test name
Test status
Simulation time 19765936 ps
CPU time 1.29 seconds
Started Jul 16 07:09:48 PM PDT 24
Finished Jul 16 07:09:52 PM PDT 24
Peak memory 215200 kb
Host smart-3588065a-180a-4aee-aa34-9f1fb083a324
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223622001 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.223622001
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.3556420573
Short name T1100
Test name
Test status
Simulation time 16616727 ps
CPU time 0.85 seconds
Started Jul 16 07:09:49 PM PDT 24
Finished Jul 16 07:09:53 PM PDT 24
Peak memory 206928 kb
Host smart-6f551ff7-d7d2-43eb-b534-b56ceefad07a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556420573 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.3556420573
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.4037629530
Short name T1006
Test name
Test status
Simulation time 26632747 ps
CPU time 0.88 seconds
Started Jul 16 07:09:48 PM PDT 24
Finished Jul 16 07:09:50 PM PDT 24
Peak memory 206884 kb
Host smart-b0509a12-15f2-4a68-906c-49e24b04f82a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037629530 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.4037629530
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.507256946
Short name T1104
Test name
Test status
Simulation time 120916350 ps
CPU time 0.94 seconds
Started Jul 16 07:09:49 PM PDT 24
Finished Jul 16 07:09:53 PM PDT 24
Peak memory 207112 kb
Host smart-2c549f26-8fa1-4999-8340-05e14f22510d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507256946 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_out
standing.507256946
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3448607025
Short name T1099
Test name
Test status
Simulation time 156803216 ps
CPU time 2.88 seconds
Started Jul 16 07:09:49 PM PDT 24
Finished Jul 16 07:09:54 PM PDT 24
Peak memory 215216 kb
Host smart-f9320009-cc6a-4b12-b2ee-5a028dd06809
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448607025 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3448607025
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1315185590
Short name T1109
Test name
Test status
Simulation time 276633392 ps
CPU time 5.05 seconds
Started Jul 16 07:09:47 PM PDT 24
Finished Jul 16 07:09:53 PM PDT 24
Peak memory 207284 kb
Host smart-a522c759-6f98-4390-b386-4da9da2fe4f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315185590 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.1315185590
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3597238816
Short name T1041
Test name
Test status
Simulation time 114855955 ps
CPU time 1.14 seconds
Started Jul 16 07:09:59 PM PDT 24
Finished Jul 16 07:10:03 PM PDT 24
Peak memory 215272 kb
Host smart-343f748e-565b-46f9-a647-9910faf5be3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597238816 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.3597238816
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1115770874
Short name T1076
Test name
Test status
Simulation time 37254872 ps
CPU time 0.83 seconds
Started Jul 16 07:09:49 PM PDT 24
Finished Jul 16 07:09:52 PM PDT 24
Peak memory 206968 kb
Host smart-89db3a25-5e5e-493d-9758-8ef4620ddbd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115770874 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1115770874
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.2367445411
Short name T1013
Test name
Test status
Simulation time 26418254 ps
CPU time 0.84 seconds
Started Jul 16 07:09:51 PM PDT 24
Finished Jul 16 07:09:55 PM PDT 24
Peak memory 206860 kb
Host smart-4c2fd039-93f1-418d-a7bd-7db06727d9ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367445411 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.2367445411
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3376036081
Short name T1086
Test name
Test status
Simulation time 22326637 ps
CPU time 1.12 seconds
Started Jul 16 07:10:00 PM PDT 24
Finished Jul 16 07:10:04 PM PDT 24
Peak memory 206916 kb
Host smart-d7c45b75-82e8-4918-879a-f878310c18cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376036081 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.3376036081
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.1173317689
Short name T1084
Test name
Test status
Simulation time 49192035 ps
CPU time 2.4 seconds
Started Jul 16 07:09:47 PM PDT 24
Finished Jul 16 07:09:51 PM PDT 24
Peak memory 215228 kb
Host smart-ceb6bc48-1bba-4b70-8206-ffd765699cc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173317689 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.1173317689
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2325663714
Short name T1119
Test name
Test status
Simulation time 191000614 ps
CPU time 2.24 seconds
Started Jul 16 07:09:50 PM PDT 24
Finished Jul 16 07:09:56 PM PDT 24
Peak memory 215136 kb
Host smart-8d6e1b0f-f13d-4d3e-aa81-b4e33542d116
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325663714 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2325663714
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2204862432
Short name T1111
Test name
Test status
Simulation time 531745573 ps
CPU time 1.74 seconds
Started Jul 16 07:10:01 PM PDT 24
Finished Jul 16 07:10:06 PM PDT 24
Peak memory 218168 kb
Host smart-315476af-483b-47fa-a098-79a95582b1ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204862432 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.2204862432
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.822326165
Short name T251
Test name
Test status
Simulation time 12289453 ps
CPU time 0.91 seconds
Started Jul 16 07:10:05 PM PDT 24
Finished Jul 16 07:10:08 PM PDT 24
Peak memory 206904 kb
Host smart-9003db1c-fcf5-434e-8556-9dca97306fb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822326165 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.822326165
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.882839111
Short name T1101
Test name
Test status
Simulation time 24122350 ps
CPU time 0.9 seconds
Started Jul 16 07:10:01 PM PDT 24
Finished Jul 16 07:10:05 PM PDT 24
Peak memory 206816 kb
Host smart-3c64a6db-02e9-436f-bfee-29d33ee27f0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882839111 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.882839111
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3139101378
Short name T1066
Test name
Test status
Simulation time 17214577 ps
CPU time 1.02 seconds
Started Jul 16 07:10:02 PM PDT 24
Finished Jul 16 07:10:06 PM PDT 24
Peak memory 206992 kb
Host smart-45e1a4d2-dd47-4f0d-ac55-870d7e4045a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139101378 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.3139101378
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.904949196
Short name T1120
Test name
Test status
Simulation time 259433529 ps
CPU time 4.36 seconds
Started Jul 16 07:09:57 PM PDT 24
Finished Jul 16 07:10:02 PM PDT 24
Peak memory 215168 kb
Host smart-8552af7a-d755-48e5-91b9-280add846451
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904949196 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.904949196
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3075065519
Short name T1128
Test name
Test status
Simulation time 86399058 ps
CPU time 1.5 seconds
Started Jul 16 07:09:59 PM PDT 24
Finished Jul 16 07:10:03 PM PDT 24
Peak memory 215168 kb
Host smart-4e5b7340-1142-4ff2-b74c-951e2761b88b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075065519 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.3075065519
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.692165347
Short name T1043
Test name
Test status
Simulation time 39890986 ps
CPU time 1.19 seconds
Started Jul 16 07:09:59 PM PDT 24
Finished Jul 16 07:10:02 PM PDT 24
Peak memory 215224 kb
Host smart-215ed980-ac39-43f0-b5da-50cf68abc178
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692165347 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.692165347
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2255886414
Short name T242
Test name
Test status
Simulation time 24926318 ps
CPU time 0.94 seconds
Started Jul 16 07:09:59 PM PDT 24
Finished Jul 16 07:10:02 PM PDT 24
Peak memory 206848 kb
Host smart-af8c52ac-e93d-4b4d-a714-03114df70b7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255886414 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2255886414
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2567234592
Short name T1083
Test name
Test status
Simulation time 133628769 ps
CPU time 0.89 seconds
Started Jul 16 07:09:58 PM PDT 24
Finished Jul 16 07:10:01 PM PDT 24
Peak memory 206812 kb
Host smart-f847f44b-1151-4daa-924a-edaa29c90ead
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567234592 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2567234592
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1288441128
Short name T1052
Test name
Test status
Simulation time 22242328 ps
CPU time 1.12 seconds
Started Jul 16 07:10:01 PM PDT 24
Finished Jul 16 07:10:05 PM PDT 24
Peak memory 206960 kb
Host smart-47575901-0127-474e-a325-51d23567d72e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288441128 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1288441128
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.4171877976
Short name T1123
Test name
Test status
Simulation time 95644065 ps
CPU time 3.37 seconds
Started Jul 16 07:09:58 PM PDT 24
Finished Jul 16 07:10:03 PM PDT 24
Peak memory 215368 kb
Host smart-abe41757-07a9-4038-8f9b-e9936ac74f01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171877976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.4171877976
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3683890646
Short name T277
Test name
Test status
Simulation time 74197696 ps
CPU time 1.43 seconds
Started Jul 16 07:09:57 PM PDT 24
Finished Jul 16 07:09:59 PM PDT 24
Peak memory 206956 kb
Host smart-552c8017-bbb6-4d29-91a1-817cc4e0356d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683890646 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3683890646
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.867429331
Short name T797
Test name
Test status
Simulation time 44139672 ps
CPU time 1.09 seconds
Started Jul 16 07:11:45 PM PDT 24
Finished Jul 16 07:13:12 PM PDT 24
Peak memory 215952 kb
Host smart-495e2784-6925-43a9-a6c3-55c0250eaa9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867429331 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.867429331
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.1369004315
Short name T611
Test name
Test status
Simulation time 38345802 ps
CPU time 1.25 seconds
Started Jul 16 07:11:49 PM PDT 24
Finished Jul 16 07:13:13 PM PDT 24
Peak memory 215228 kb
Host smart-d10cbc7c-d057-4a90-8250-a55b8eb1c47e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369004315 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.1369004315
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.2603393805
Short name T637
Test name
Test status
Simulation time 10468649 ps
CPU time 0.85 seconds
Started Jul 16 07:11:40 PM PDT 24
Finished Jul 16 07:13:10 PM PDT 24
Peak memory 216156 kb
Host smart-e92a3f8d-ab26-42e7-b0fe-64c6fdd34282
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603393805 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.2603393805
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.522020803
Short name T131
Test name
Test status
Simulation time 70356823 ps
CPU time 1.04 seconds
Started Jul 16 07:11:39 PM PDT 24
Finished Jul 16 07:13:05 PM PDT 24
Peak memory 217076 kb
Host smart-3a2b76f3-9d75-42d2-87f5-fc803a14a596
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522020803 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_dis
able_auto_req_mode.522020803
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.77258751
Short name T168
Test name
Test status
Simulation time 21064396 ps
CPU time 1.17 seconds
Started Jul 16 07:11:44 PM PDT 24
Finished Jul 16 07:13:12 PM PDT 24
Peak memory 224276 kb
Host smart-f99bc14a-e721-447f-9044-73af95fdddcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77258751 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.77258751
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.2987880061
Short name T631
Test name
Test status
Simulation time 43322071 ps
CPU time 1.71 seconds
Started Jul 16 07:11:44 PM PDT 24
Finished Jul 16 07:13:12 PM PDT 24
Peak memory 218744 kb
Host smart-465c6a55-51e3-4319-9343-678979e2b248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987880061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2987880061
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.2108230674
Short name T647
Test name
Test status
Simulation time 33750944 ps
CPU time 0.99 seconds
Started Jul 16 07:11:41 PM PDT 24
Finished Jul 16 07:13:10 PM PDT 24
Peak memory 224276 kb
Host smart-fc431cbf-e5b3-4c6e-a6d2-d51d6371536f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108230674 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.2108230674
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_sec_cm.1506919534
Short name T18
Test name
Test status
Simulation time 993578477 ps
CPU time 4.17 seconds
Started Jul 16 07:11:39 PM PDT 24
Finished Jul 16 07:13:12 PM PDT 24
Peak memory 235552 kb
Host smart-b462c1c6-729c-499b-91a4-0b8c427bd66b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506919534 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1506919534
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.2947651308
Short name T441
Test name
Test status
Simulation time 25560200 ps
CPU time 0.87 seconds
Started Jul 16 07:11:39 PM PDT 24
Finished Jul 16 07:13:05 PM PDT 24
Peak memory 215728 kb
Host smart-2d96920e-0e02-4bb6-8baa-491b88c55bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947651308 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2947651308
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.1674647464
Short name T983
Test name
Test status
Simulation time 2575448950 ps
CPU time 3.45 seconds
Started Jul 16 07:11:42 PM PDT 24
Finished Jul 16 07:13:20 PM PDT 24
Peak memory 218008 kb
Host smart-db422cb1-0788-49c4-b9ee-d291c985bde3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674647464 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.1674647464
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.1521632024
Short name T608
Test name
Test status
Simulation time 318445316046 ps
CPU time 1984.85 seconds
Started Jul 16 07:11:42 PM PDT 24
Finished Jul 16 07:46:25 PM PDT 24
Peak memory 226888 kb
Host smart-3aac7585-c26c-45e9-9497-34e0dcf194ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521632024 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.1521632024
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert_test.275729604
Short name T576
Test name
Test status
Simulation time 26100312 ps
CPU time 0.9 seconds
Started Jul 16 07:11:42 PM PDT 24
Finished Jul 16 07:13:18 PM PDT 24
Peak memory 207036 kb
Host smart-5f3b9915-3eca-417a-af8c-67aef04478c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275729604 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.275729604
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.1851716227
Short name T388
Test name
Test status
Simulation time 28278426 ps
CPU time 1.12 seconds
Started Jul 16 07:11:43 PM PDT 24
Finished Jul 16 07:13:12 PM PDT 24
Peak memory 218680 kb
Host smart-a54c4b6d-8f9e-4b93-a29d-6e5ddaa3c368
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851716227 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.1851716227
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_genbits.3091009511
Short name T577
Test name
Test status
Simulation time 106781538 ps
CPU time 1.32 seconds
Started Jul 16 07:11:43 PM PDT 24
Finished Jul 16 07:13:08 PM PDT 24
Peak memory 220444 kb
Host smart-a58f7293-12fe-4521-abaa-5e5d8d39713c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091009511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.3091009511
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_regwen.2248039301
Short name T648
Test name
Test status
Simulation time 41601426 ps
CPU time 0.9 seconds
Started Jul 16 07:11:42 PM PDT 24
Finished Jul 16 07:13:18 PM PDT 24
Peak memory 207364 kb
Host smart-a3eaed3c-97ce-4a8c-9e1f-304ad32d1ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248039301 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.2248039301
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.3679473668
Short name T19
Test name
Test status
Simulation time 722156206 ps
CPU time 10.38 seconds
Started Jul 16 07:11:41 PM PDT 24
Finished Jul 16 07:13:19 PM PDT 24
Peak memory 235852 kb
Host smart-68b88bc3-cb13-40fd-bdfe-a77ca52665f7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679473668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.3679473668
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.2745858722
Short name T911
Test name
Test status
Simulation time 45105230 ps
CPU time 0.94 seconds
Started Jul 16 07:11:41 PM PDT 24
Finished Jul 16 07:13:10 PM PDT 24
Peak memory 207368 kb
Host smart-556fac82-af0f-4138-a12f-7aa33dd2730d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745858722 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.2745858722
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.650796568
Short name T764
Test name
Test status
Simulation time 132114891 ps
CPU time 2.79 seconds
Started Jul 16 07:11:42 PM PDT 24
Finished Jul 16 07:13:20 PM PDT 24
Peak memory 215672 kb
Host smart-eedba519-08fb-45bb-8cd6-ecaa7b6834de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650796568 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.650796568
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.1005485939
Short name T952
Test name
Test status
Simulation time 41799019194 ps
CPU time 925.38 seconds
Started Jul 16 07:11:36 PM PDT 24
Finished Jul 16 07:28:30 PM PDT 24
Peak memory 219188 kb
Host smart-080b5573-015e-40a5-847a-dcbffa5f4ec9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005485939 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.1005485939
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.2525691072
Short name T916
Test name
Test status
Simulation time 76845023 ps
CPU time 1.11 seconds
Started Jul 16 07:12:07 PM PDT 24
Finished Jul 16 07:13:26 PM PDT 24
Peak memory 220100 kb
Host smart-ef77560d-37fb-4323-b857-2605b9125839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525691072 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.2525691072
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.302880548
Short name T101
Test name
Test status
Simulation time 75787520 ps
CPU time 1.23 seconds
Started Jul 16 07:12:10 PM PDT 24
Finished Jul 16 07:13:27 PM PDT 24
Peak memory 217308 kb
Host smart-49625acf-2e86-4d58-b9da-5137d2e078f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302880548 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_di
sable_auto_req_mode.302880548
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.1635820589
Short name T124
Test name
Test status
Simulation time 20503056 ps
CPU time 1.23 seconds
Started Jul 16 07:12:18 PM PDT 24
Finished Jul 16 07:13:28 PM PDT 24
Peak memory 230044 kb
Host smart-a90895bb-4424-4d84-b022-357af8e2d424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635820589 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1635820589
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.2599680672
Short name T416
Test name
Test status
Simulation time 33425921 ps
CPU time 1.23 seconds
Started Jul 16 07:12:20 PM PDT 24
Finished Jul 16 07:13:29 PM PDT 24
Peak memory 217864 kb
Host smart-6b11a1e0-2b3d-4a46-832b-b691fd4598bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599680672 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.2599680672
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.4262555865
Short name T446
Test name
Test status
Simulation time 40617467 ps
CPU time 0.91 seconds
Started Jul 16 07:12:11 PM PDT 24
Finished Jul 16 07:13:27 PM PDT 24
Peak memory 215812 kb
Host smart-80e2374b-73e2-4a4e-b0a7-fe4dfde4552e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262555865 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.4262555865
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.1786275284
Short name T358
Test name
Test status
Simulation time 22486441 ps
CPU time 0.92 seconds
Started Jul 16 07:12:12 PM PDT 24
Finished Jul 16 07:13:27 PM PDT 24
Peak memory 215588 kb
Host smart-6b247a0d-b18e-49d8-904d-0a832b07bc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786275284 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1786275284
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.3363655558
Short name T819
Test name
Test status
Simulation time 364222379 ps
CPU time 3.84 seconds
Started Jul 16 07:12:21 PM PDT 24
Finished Jul 16 07:13:33 PM PDT 24
Peak memory 220824 kb
Host smart-df2ba9e6-37a0-4680-b18d-ee882b209ce3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363655558 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.3363655558
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.108975548
Short name T216
Test name
Test status
Simulation time 121511283336 ps
CPU time 714.92 seconds
Started Jul 16 07:12:13 PM PDT 24
Finished Jul 16 07:25:22 PM PDT 24
Peak memory 221704 kb
Host smart-51c1e507-b2e7-4d34-b7c6-1c1b211acbbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108975548 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.108975548
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.1322966305
Short name T803
Test name
Test status
Simulation time 76813170 ps
CPU time 1.23 seconds
Started Jul 16 07:14:42 PM PDT 24
Finished Jul 16 07:15:17 PM PDT 24
Peak memory 220116 kb
Host smart-87ccdadd-9ae6-4e21-936b-dbef3cb08d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322966305 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.1322966305
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.1509603799
Short name T41
Test name
Test status
Simulation time 42567512 ps
CPU time 1.13 seconds
Started Jul 16 07:14:47 PM PDT 24
Finished Jul 16 07:15:28 PM PDT 24
Peak memory 217428 kb
Host smart-590e7ce7-5448-49f3-a569-e66337362404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509603799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.1509603799
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.2200366363
Short name T890
Test name
Test status
Simulation time 95450030 ps
CPU time 1.26 seconds
Started Jul 16 07:14:30 PM PDT 24
Finished Jul 16 07:14:54 PM PDT 24
Peak memory 218764 kb
Host smart-be746734-ab81-4991-a898-fecff5e2374f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200366363 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.2200366363
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.3721054997
Short name T798
Test name
Test status
Simulation time 319080792 ps
CPU time 1.17 seconds
Started Jul 16 07:14:43 PM PDT 24
Finished Jul 16 07:15:19 PM PDT 24
Peak memory 215636 kb
Host smart-c4646770-4921-4843-ac45-0926b66398ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721054997 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.3721054997
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.1694635309
Short name T835
Test name
Test status
Simulation time 141548814 ps
CPU time 1.01 seconds
Started Jul 16 07:14:52 PM PDT 24
Finished Jul 16 07:15:34 PM PDT 24
Peak memory 217400 kb
Host smart-49e54e2f-004f-4fc3-b8ba-f09543617397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694635309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.1694635309
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.3098629384
Short name T344
Test name
Test status
Simulation time 34651984 ps
CPU time 1.17 seconds
Started Jul 16 07:14:49 PM PDT 24
Finished Jul 16 07:15:30 PM PDT 24
Peak memory 220104 kb
Host smart-4c0af38c-7d35-4c45-8e48-3960677cd56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098629384 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.3098629384
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.933303981
Short name T878
Test name
Test status
Simulation time 31837510 ps
CPU time 1.24 seconds
Started Jul 16 07:14:37 PM PDT 24
Finished Jul 16 07:15:07 PM PDT 24
Peak memory 217676 kb
Host smart-8c4e92e4-fc09-4b19-a8ff-be13b6bb8226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933303981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.933303981
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.1338740317
Short name T345
Test name
Test status
Simulation time 41430386 ps
CPU time 0.99 seconds
Started Jul 16 07:14:46 PM PDT 24
Finished Jul 16 07:15:23 PM PDT 24
Peak memory 217428 kb
Host smart-0fb8a4f1-caea-4fc7-a2a2-d9a8277cc849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338740317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.1338740317
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.3286690244
Short name T806
Test name
Test status
Simulation time 36515167 ps
CPU time 1.3 seconds
Started Jul 16 07:14:47 PM PDT 24
Finished Jul 16 07:15:28 PM PDT 24
Peak memory 220436 kb
Host smart-28c40e06-253a-40cb-b14e-d36c9ffa2feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286690244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.3286690244
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.4256187164
Short name T294
Test name
Test status
Simulation time 25758245 ps
CPU time 1.21 seconds
Started Jul 16 07:14:47 PM PDT 24
Finished Jul 16 07:15:28 PM PDT 24
Peak memory 218852 kb
Host smart-2b33b4df-dc31-4a0d-b735-a72016913680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256187164 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.4256187164
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.3853326202
Short name T622
Test name
Test status
Simulation time 64118511 ps
CPU time 1.62 seconds
Started Jul 16 07:14:37 PM PDT 24
Finished Jul 16 07:15:08 PM PDT 24
Peak memory 220632 kb
Host smart-ee402413-786a-41b4-ad06-05659a11729c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853326202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.3853326202
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.1518569777
Short name T720
Test name
Test status
Simulation time 139026991 ps
CPU time 1.92 seconds
Started Jul 16 07:14:37 PM PDT 24
Finished Jul 16 07:15:08 PM PDT 24
Peak memory 218888 kb
Host smart-abcf0b2f-8cac-4fe2-a32d-9c46fe5d1380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518569777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.1518569777
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.3709254143
Short name T90
Test name
Test status
Simulation time 50930689 ps
CPU time 1.24 seconds
Started Jul 16 07:14:37 PM PDT 24
Finished Jul 16 07:15:07 PM PDT 24
Peak memory 215964 kb
Host smart-cb79b8c6-f542-4a76-8747-87f3fa5396e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709254143 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.3709254143
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.510584578
Short name T385
Test name
Test status
Simulation time 101621574 ps
CPU time 1.42 seconds
Started Jul 16 07:14:48 PM PDT 24
Finished Jul 16 07:15:29 PM PDT 24
Peak memory 220404 kb
Host smart-f409dc8a-1b41-4f44-8ca7-1d28e14bc8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510584578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.510584578
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.965525817
Short name T976
Test name
Test status
Simulation time 36608483 ps
CPU time 1.08 seconds
Started Jul 16 07:12:21 PM PDT 24
Finished Jul 16 07:13:31 PM PDT 24
Peak memory 219680 kb
Host smart-3108f7bd-c07a-45f6-a706-a7610fedafd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965525817 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.965525817
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.69961770
Short name T732
Test name
Test status
Simulation time 147025377 ps
CPU time 0.82 seconds
Started Jul 16 07:12:21 PM PDT 24
Finished Jul 16 07:13:30 PM PDT 24
Peak memory 206844 kb
Host smart-b74f8159-9c8c-4b52-82be-e1c59b5f6d00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69961770 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.69961770
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.3490337063
Short name T522
Test name
Test status
Simulation time 67382464 ps
CPU time 1.12 seconds
Started Jul 16 07:12:10 PM PDT 24
Finished Jul 16 07:13:27 PM PDT 24
Peak memory 217076 kb
Host smart-92b5a4b5-2a22-406e-82db-7dd60087880c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490337063 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.3490337063
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_genbits.928953817
Short name T334
Test name
Test status
Simulation time 94186606 ps
CPU time 1.49 seconds
Started Jul 16 07:12:09 PM PDT 24
Finished Jul 16 07:13:27 PM PDT 24
Peak memory 219136 kb
Host smart-1b02e4e8-7bba-4abc-b6ca-61b9e60cfefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928953817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.928953817
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.2752128355
Short name T16
Test name
Test status
Simulation time 28678286 ps
CPU time 1.03 seconds
Started Jul 16 07:12:06 PM PDT 24
Finished Jul 16 07:13:24 PM PDT 24
Peak memory 224300 kb
Host smart-1511afa9-a55d-4f6f-999a-c353f23fadd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752128355 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.2752128355
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.3536706735
Short name T933
Test name
Test status
Simulation time 17655392 ps
CPU time 0.98 seconds
Started Jul 16 07:12:08 PM PDT 24
Finished Jul 16 07:13:26 PM PDT 24
Peak memory 215568 kb
Host smart-1173a4b9-3e86-44d5-896f-629fd92c5f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536706735 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.3536706735
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.1722486683
Short name T228
Test name
Test status
Simulation time 24850723 ps
CPU time 1.02 seconds
Started Jul 16 07:12:13 PM PDT 24
Finished Jul 16 07:13:28 PM PDT 24
Peak memory 206760 kb
Host smart-ad0b45c4-69b6-4da6-b332-281bd8a2766a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722486683 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1722486683
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.1958682598
Short name T853
Test name
Test status
Simulation time 125784448405 ps
CPU time 1595.63 seconds
Started Jul 16 07:12:12 PM PDT 24
Finished Jul 16 07:40:02 PM PDT 24
Peak memory 227732 kb
Host smart-72624a61-49c5-44ef-aa99-3663dbf84a69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958682598 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.1958682598
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.716357710
Short name T133
Test name
Test status
Simulation time 80396508 ps
CPU time 1.16 seconds
Started Jul 16 07:14:39 PM PDT 24
Finished Jul 16 07:15:12 PM PDT 24
Peak memory 218684 kb
Host smart-dc16759b-e4e7-4448-9544-15a8bc007311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716357710 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.716357710
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/111.edn_alert.3423340639
Short name T287
Test name
Test status
Simulation time 25923169 ps
CPU time 1.18 seconds
Started Jul 16 07:14:58 PM PDT 24
Finished Jul 16 07:15:44 PM PDT 24
Peak memory 218860 kb
Host smart-796e8f89-165d-4e3e-a507-bff1ea288adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423340639 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.3423340639
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.3589901749
Short name T40
Test name
Test status
Simulation time 1057516012 ps
CPU time 5.87 seconds
Started Jul 16 07:14:49 PM PDT 24
Finished Jul 16 07:15:34 PM PDT 24
Peak memory 219912 kb
Host smart-7d968e01-153d-4a18-a503-ab6cf92938af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589901749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.3589901749
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.826688427
Short name T17
Test name
Test status
Simulation time 39784311 ps
CPU time 1.06 seconds
Started Jul 16 07:14:40 PM PDT 24
Finished Jul 16 07:15:13 PM PDT 24
Peak memory 218688 kb
Host smart-d6698388-2d88-4479-b6a1-519624fdff61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826688427 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.826688427
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.2050302588
Short name T321
Test name
Test status
Simulation time 310084465 ps
CPU time 1.82 seconds
Started Jul 16 07:14:40 PM PDT 24
Finished Jul 16 07:15:14 PM PDT 24
Peak memory 220040 kb
Host smart-2bb5d171-c342-400e-bf06-a6be79e80f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050302588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.2050302588
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.1679603026
Short name T104
Test name
Test status
Simulation time 32239007 ps
CPU time 1.31 seconds
Started Jul 16 07:14:52 PM PDT 24
Finished Jul 16 07:15:34 PM PDT 24
Peak memory 220240 kb
Host smart-fde0a4b9-2fda-43e8-a0d2-1003c2eb3981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679603026 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.1679603026
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.8207452
Short name T506
Test name
Test status
Simulation time 73695978 ps
CPU time 1.04 seconds
Started Jul 16 07:14:53 PM PDT 24
Finished Jul 16 07:15:36 PM PDT 24
Peak memory 217612 kb
Host smart-cfeb2f15-7fbf-40ba-bcd1-bd5f7f1de32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8207452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.8207452
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.2094291404
Short name T530
Test name
Test status
Simulation time 48457699 ps
CPU time 1.22 seconds
Started Jul 16 07:14:42 PM PDT 24
Finished Jul 16 07:15:17 PM PDT 24
Peak memory 215972 kb
Host smart-f5c12015-98d9-4032-890a-331e764869f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094291404 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.2094291404
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.3277940903
Short name T812
Test name
Test status
Simulation time 48266175 ps
CPU time 1.24 seconds
Started Jul 16 07:14:52 PM PDT 24
Finished Jul 16 07:15:36 PM PDT 24
Peak memory 217752 kb
Host smart-1e712e43-1f55-4609-b2b3-aae2adf488ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277940903 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3277940903
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.757328308
Short name T565
Test name
Test status
Simulation time 62609840 ps
CPU time 1.11 seconds
Started Jul 16 07:14:39 PM PDT 24
Finished Jul 16 07:15:12 PM PDT 24
Peak memory 219024 kb
Host smart-02688c10-fb66-4d3a-b262-181d208d5ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757328308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.757328308
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.1095010610
Short name T658
Test name
Test status
Simulation time 199215265 ps
CPU time 1.46 seconds
Started Jul 16 07:14:54 PM PDT 24
Finished Jul 16 07:15:37 PM PDT 24
Peak memory 218968 kb
Host smart-11ba7cae-a4ba-4128-abda-67d8047e7aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095010610 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.1095010610
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.2757527483
Short name T970
Test name
Test status
Simulation time 23819606 ps
CPU time 1.16 seconds
Started Jul 16 07:14:51 PM PDT 24
Finished Jul 16 07:15:34 PM PDT 24
Peak memory 218832 kb
Host smart-d435e929-faa0-4fb0-9f9f-c405c98fbc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757527483 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.2757527483
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.765351596
Short name T453
Test name
Test status
Simulation time 125575888 ps
CPU time 1.23 seconds
Started Jul 16 07:14:56 PM PDT 24
Finished Jul 16 07:15:41 PM PDT 24
Peak memory 218848 kb
Host smart-7141d01b-cc62-4ee9-bb33-78fc94b30543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765351596 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.765351596
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.91326842
Short name T340
Test name
Test status
Simulation time 45914525 ps
CPU time 1.7 seconds
Started Jul 16 07:14:42 PM PDT 24
Finished Jul 16 07:15:17 PM PDT 24
Peak memory 218960 kb
Host smart-0f8a3e79-5a95-494d-906b-855a5d91d04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91326842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.91326842
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.3606631308
Short name T89
Test name
Test status
Simulation time 117529530 ps
CPU time 1.22 seconds
Started Jul 16 07:14:42 PM PDT 24
Finished Jul 16 07:15:17 PM PDT 24
Peak memory 220920 kb
Host smart-fa6a2d0d-6154-443f-a353-b4a59a7b45f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606631308 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.3606631308
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.2076812621
Short name T532
Test name
Test status
Simulation time 134154527 ps
CPU time 1.08 seconds
Started Jul 16 07:14:42 PM PDT 24
Finished Jul 16 07:15:17 PM PDT 24
Peak memory 217700 kb
Host smart-8bedf016-aed6-483e-9066-445932d6d1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076812621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.2076812621
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.3402154367
Short name T145
Test name
Test status
Simulation time 277717825 ps
CPU time 1.32 seconds
Started Jul 16 07:14:45 PM PDT 24
Finished Jul 16 07:15:24 PM PDT 24
Peak memory 220288 kb
Host smart-a2b2c491-d946-4e8c-9822-499a0d81f0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402154367 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.3402154367
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.3154147048
Short name T354
Test name
Test status
Simulation time 77508609 ps
CPU time 1.14 seconds
Started Jul 16 07:14:40 PM PDT 24
Finished Jul 16 07:15:14 PM PDT 24
Peak memory 217984 kb
Host smart-fe65de23-7351-4a52-8917-dff264c134e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154147048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3154147048
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.259296745
Short name T140
Test name
Test status
Simulation time 110292653 ps
CPU time 1.22 seconds
Started Jul 16 07:12:19 PM PDT 24
Finished Jul 16 07:13:32 PM PDT 24
Peak memory 215964 kb
Host smart-fbb1d7b8-e58f-4818-a7dd-d9f8b125f44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259296745 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.259296745
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.3591851988
Short name T719
Test name
Test status
Simulation time 42280518 ps
CPU time 0.85 seconds
Started Jul 16 07:12:17 PM PDT 24
Finished Jul 16 07:13:34 PM PDT 24
Peak memory 207032 kb
Host smart-b5d7d802-8805-45d4-9d54-68869a19cfbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591851988 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3591851988
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.3554643545
Short name T194
Test name
Test status
Simulation time 13772735 ps
CPU time 0.97 seconds
Started Jul 16 07:12:20 PM PDT 24
Finished Jul 16 07:13:30 PM PDT 24
Peak memory 216720 kb
Host smart-7e51553d-e0c0-49ea-ad6d-d370ad9f482c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554643545 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.3554643545
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.248101519
Short name T705
Test name
Test status
Simulation time 212085896 ps
CPU time 1.11 seconds
Started Jul 16 07:12:16 PM PDT 24
Finished Jul 16 07:13:32 PM PDT 24
Peak memory 217036 kb
Host smart-4b5a4071-cb72-4688-b5c0-31f0c2c998e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248101519 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_di
sable_auto_req_mode.248101519
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.2980975194
Short name T62
Test name
Test status
Simulation time 72573402 ps
CPU time 1.09 seconds
Started Jul 16 07:12:21 PM PDT 24
Finished Jul 16 07:13:30 PM PDT 24
Peak memory 220320 kb
Host smart-2bfaf181-c478-4a84-b814-6e8391a6901d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980975194 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.2980975194
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.2892380036
Short name T854
Test name
Test status
Simulation time 32095142 ps
CPU time 1.3 seconds
Started Jul 16 07:12:08 PM PDT 24
Finished Jul 16 07:13:26 PM PDT 24
Peak memory 217916 kb
Host smart-f3e64241-5a04-4aa2-8a88-7c701775d767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892380036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2892380036
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.2287652513
Short name T374
Test name
Test status
Simulation time 37724473 ps
CPU time 0.95 seconds
Started Jul 16 07:12:15 PM PDT 24
Finished Jul 16 07:13:29 PM PDT 24
Peak memory 224152 kb
Host smart-c69de47b-1e07-4fff-ad85-77792a503160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287652513 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.2287652513
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.2117305587
Short name T979
Test name
Test status
Simulation time 37559137 ps
CPU time 0.84 seconds
Started Jul 16 07:12:22 PM PDT 24
Finished Jul 16 07:13:29 PM PDT 24
Peak memory 215612 kb
Host smart-d0dedbbc-655e-425d-b41f-4aef84f17da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117305587 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2117305587
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.1289047177
Short name T650
Test name
Test status
Simulation time 1175288152 ps
CPU time 3.52 seconds
Started Jul 16 07:12:15 PM PDT 24
Finished Jul 16 07:13:30 PM PDT 24
Peak memory 215536 kb
Host smart-f4de54fb-ec11-47d9-ab26-b492b75afde1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289047177 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.1289047177
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.775447672
Short name T423
Test name
Test status
Simulation time 1071302085084 ps
CPU time 1761.05 seconds
Started Jul 16 07:12:16 PM PDT 24
Finished Jul 16 07:42:49 PM PDT 24
Peak memory 227648 kb
Host smart-72178586-961b-4c8e-80e2-74fddfd02088
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775447672 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.775447672
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.3900151598
Short name T966
Test name
Test status
Simulation time 48757571 ps
CPU time 1.18 seconds
Started Jul 16 07:14:43 PM PDT 24
Finished Jul 16 07:15:17 PM PDT 24
Peak memory 220252 kb
Host smart-f91a62ad-b9fe-44cf-a0c4-8a4d5d1221c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900151598 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.3900151598
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/121.edn_alert.3272606193
Short name T166
Test name
Test status
Simulation time 23709082 ps
CPU time 1.19 seconds
Started Jul 16 07:14:40 PM PDT 24
Finished Jul 16 07:15:14 PM PDT 24
Peak memory 218956 kb
Host smart-af0ea857-3138-4cdd-b6e9-f13abf3f68f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272606193 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.3272606193
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.3337138618
Short name T508
Test name
Test status
Simulation time 98448810 ps
CPU time 1.33 seconds
Started Jul 16 07:14:53 PM PDT 24
Finished Jul 16 07:15:36 PM PDT 24
Peak memory 219204 kb
Host smart-40dab91f-eee9-4821-96dc-3c46527eb933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337138618 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.3337138618
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.4208694036
Short name T327
Test name
Test status
Simulation time 66326649 ps
CPU time 1.1 seconds
Started Jul 16 07:14:49 PM PDT 24
Finished Jul 16 07:15:29 PM PDT 24
Peak memory 217612 kb
Host smart-d18f31d0-94cd-40c1-9fad-c5d8a7f88dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208694036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.4208694036
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.1214914029
Short name T675
Test name
Test status
Simulation time 59542733 ps
CPU time 1.48 seconds
Started Jul 16 07:14:39 PM PDT 24
Finished Jul 16 07:15:09 PM PDT 24
Peak memory 218868 kb
Host smart-53c0aa63-a88e-4d8e-8b62-35c5c06a2c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214914029 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.1214914029
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.429921965
Short name T290
Test name
Test status
Simulation time 87601098 ps
CPU time 1.12 seconds
Started Jul 16 07:14:42 PM PDT 24
Finished Jul 16 07:15:17 PM PDT 24
Peak memory 216016 kb
Host smart-b8eab5c9-1524-4055-ad8c-b4988c773fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429921965 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.429921965
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.545591665
Short name T527
Test name
Test status
Simulation time 100513518 ps
CPU time 1.08 seconds
Started Jul 16 07:14:42 PM PDT 24
Finished Jul 16 07:15:17 PM PDT 24
Peak memory 217416 kb
Host smart-162d03f9-4ca7-497d-aa91-b0c9e1810693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545591665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.545591665
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.3477668463
Short name T716
Test name
Test status
Simulation time 136516910 ps
CPU time 1.15 seconds
Started Jul 16 07:14:58 PM PDT 24
Finished Jul 16 07:15:46 PM PDT 24
Peak memory 219968 kb
Host smart-4cce213f-9880-4682-8fb9-6cfff0638219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477668463 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.3477668463
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.2128796530
Short name T373
Test name
Test status
Simulation time 194464497 ps
CPU time 1.24 seconds
Started Jul 16 07:14:43 PM PDT 24
Finished Jul 16 07:15:17 PM PDT 24
Peak memory 217684 kb
Host smart-fd0070e8-e537-44a5-ad13-096529ee47bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128796530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2128796530
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.2585167389
Short name T778
Test name
Test status
Simulation time 38353673 ps
CPU time 1.15 seconds
Started Jul 16 07:14:42 PM PDT 24
Finished Jul 16 07:15:17 PM PDT 24
Peak memory 218808 kb
Host smart-cef791cc-81e8-4dff-b98b-605e152fefa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585167389 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.2585167389
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.2163201246
Short name T331
Test name
Test status
Simulation time 131777806 ps
CPU time 1.66 seconds
Started Jul 16 07:14:52 PM PDT 24
Finished Jul 16 07:15:36 PM PDT 24
Peak memory 219716 kb
Host smart-b49c4878-fbec-447b-841a-f0163977bc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163201246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.2163201246
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.3137876979
Short name T377
Test name
Test status
Simulation time 74616781 ps
CPU time 1.11 seconds
Started Jul 16 07:14:42 PM PDT 24
Finished Jul 16 07:15:17 PM PDT 24
Peak memory 220212 kb
Host smart-38060163-250e-4c53-ba62-9a4233daed1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137876979 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.3137876979
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.4267344021
Short name T449
Test name
Test status
Simulation time 62653041 ps
CPU time 1.18 seconds
Started Jul 16 07:14:41 PM PDT 24
Finished Jul 16 07:15:16 PM PDT 24
Peak memory 219348 kb
Host smart-73fdeacb-7cb7-4ae7-976f-7dbd11b7e9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267344021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.4267344021
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.1775383027
Short name T264
Test name
Test status
Simulation time 27999699 ps
CPU time 1.21 seconds
Started Jul 16 07:14:39 PM PDT 24
Finished Jul 16 07:15:09 PM PDT 24
Peak memory 218732 kb
Host smart-5a9e4c48-6065-4f70-bbf0-a51cb818d6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775383027 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.1775383027
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/129.edn_alert.2423256451
Short name T896
Test name
Test status
Simulation time 24108151 ps
CPU time 1.15 seconds
Started Jul 16 07:14:50 PM PDT 24
Finished Jul 16 07:15:32 PM PDT 24
Peak memory 219868 kb
Host smart-9a9972b5-4e4f-4a67-b7ab-06c79ff38986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423256451 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.2423256451
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert.3821158813
Short name T371
Test name
Test status
Simulation time 107092493 ps
CPU time 1.04 seconds
Started Jul 16 07:12:17 PM PDT 24
Finished Jul 16 07:13:32 PM PDT 24
Peak memory 218628 kb
Host smart-c9fe1606-b7ee-4ae5-b2bc-328f71dd2482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821158813 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.3821158813
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.3954353960
Short name T510
Test name
Test status
Simulation time 36117634 ps
CPU time 0.82 seconds
Started Jul 16 07:12:17 PM PDT 24
Finished Jul 16 07:13:34 PM PDT 24
Peak memory 207012 kb
Host smart-5e9539e6-1e19-4a35-a993-31105b93f057
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954353960 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3954353960
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_err.984311109
Short name T97
Test name
Test status
Simulation time 24425272 ps
CPU time 1.21 seconds
Started Jul 16 07:12:16 PM PDT 24
Finished Jul 16 07:13:29 PM PDT 24
Peak memory 220824 kb
Host smart-d62a4409-d57c-4607-930b-0d0c2347529e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984311109 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.984311109
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.268477877
Short name T560
Test name
Test status
Simulation time 25092376 ps
CPU time 1.17 seconds
Started Jul 16 07:12:17 PM PDT 24
Finished Jul 16 07:13:34 PM PDT 24
Peak memory 217676 kb
Host smart-06a1895c-ad04-429d-a4e1-75ce9e41e2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268477877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.268477877
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_smoke.1597368768
Short name T609
Test name
Test status
Simulation time 40996136 ps
CPU time 0.84 seconds
Started Jul 16 07:12:15 PM PDT 24
Finished Jul 16 07:13:29 PM PDT 24
Peak memory 215508 kb
Host smart-00fe2bed-6c8f-41e8-be82-02a5a0736c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597368768 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.1597368768
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.3756524506
Short name T431
Test name
Test status
Simulation time 82693084 ps
CPU time 1.13 seconds
Started Jul 16 07:12:17 PM PDT 24
Finished Jul 16 07:13:34 PM PDT 24
Peak memory 215536 kb
Host smart-c51c3d29-3ea0-46cf-bc9e-9dac201d6431
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756524506 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3756524506
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.1392480754
Short name T884
Test name
Test status
Simulation time 21778265011 ps
CPU time 468 seconds
Started Jul 16 07:12:21 PM PDT 24
Finished Jul 16 07:21:17 PM PDT 24
Peak memory 224016 kb
Host smart-38c9c82b-cba4-47a9-98fa-64f3f8dd5047
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392480754 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.1392480754
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.3509511862
Short name T412
Test name
Test status
Simulation time 79346278 ps
CPU time 1.17 seconds
Started Jul 16 07:14:51 PM PDT 24
Finished Jul 16 07:15:33 PM PDT 24
Peak memory 219552 kb
Host smart-ff7247af-51db-4a03-bd2e-80728167b87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509511862 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.3509511862
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.3068402797
Short name T458
Test name
Test status
Simulation time 86306592 ps
CPU time 1.1 seconds
Started Jul 16 07:14:42 PM PDT 24
Finished Jul 16 07:15:17 PM PDT 24
Peak memory 217728 kb
Host smart-9abb19c3-b452-4845-b079-f7b16f8d9219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068402797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.3068402797
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.4137441187
Short name T208
Test name
Test status
Simulation time 43499200 ps
CPU time 1.18 seconds
Started Jul 16 07:14:41 PM PDT 24
Finished Jul 16 07:15:16 PM PDT 24
Peak memory 221452 kb
Host smart-1febe4d8-ddfa-4b78-ac80-eb045407d881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137441187 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.4137441187
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.3178827065
Short name T594
Test name
Test status
Simulation time 262706040 ps
CPU time 1.59 seconds
Started Jul 16 07:14:56 PM PDT 24
Finished Jul 16 07:15:41 PM PDT 24
Peak memory 219276 kb
Host smart-2c95d4c5-49b4-4daf-b837-50019ffde5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178827065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.3178827065
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.3960688978
Short name T498
Test name
Test status
Simulation time 39048177 ps
CPU time 1.08 seconds
Started Jul 16 07:14:42 PM PDT 24
Finished Jul 16 07:15:17 PM PDT 24
Peak memory 219224 kb
Host smart-cdea93b7-e0a8-47b5-b56f-2c67ab328625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960688978 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.3960688978
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.2645638363
Short name T592
Test name
Test status
Simulation time 51816541 ps
CPU time 1.76 seconds
Started Jul 16 07:14:43 PM PDT 24
Finished Jul 16 07:15:20 PM PDT 24
Peak memory 215624 kb
Host smart-f3b8e563-1b65-4e7e-a98f-56c8f7ec68bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645638363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.2645638363
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.262851529
Short name T472
Test name
Test status
Simulation time 47072998 ps
CPU time 1.22 seconds
Started Jul 16 07:14:41 PM PDT 24
Finished Jul 16 07:15:16 PM PDT 24
Peak memory 218848 kb
Host smart-23a10f1f-168c-4a1f-984e-9b99a800ff1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262851529 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.262851529
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.1946738144
Short name T272
Test name
Test status
Simulation time 38737719 ps
CPU time 1.67 seconds
Started Jul 16 07:14:57 PM PDT 24
Finished Jul 16 07:15:46 PM PDT 24
Peak memory 218840 kb
Host smart-5de31e2a-dbf0-4214-9e36-c8b0c3b25567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946738144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1946738144
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.2085399020
Short name T888
Test name
Test status
Simulation time 55962681 ps
CPU time 1.25 seconds
Started Jul 16 07:14:41 PM PDT 24
Finished Jul 16 07:15:16 PM PDT 24
Peak memory 215964 kb
Host smart-20de73e6-2c25-4b6e-bec3-63dbe0ec22ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085399020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.2085399020
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.3026288341
Short name T521
Test name
Test status
Simulation time 35863585 ps
CPU time 1.53 seconds
Started Jul 16 07:14:46 PM PDT 24
Finished Jul 16 07:15:24 PM PDT 24
Peak memory 218716 kb
Host smart-f775690c-7514-4a3d-9056-215d98be4e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026288341 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3026288341
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.402399841
Short name T634
Test name
Test status
Simulation time 131705776 ps
CPU time 1.16 seconds
Started Jul 16 07:14:42 PM PDT 24
Finished Jul 16 07:15:17 PM PDT 24
Peak memory 217760 kb
Host smart-5ed00d01-d4cf-47e5-9181-47b5d5ed2292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402399841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.402399841
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.2778566611
Short name T711
Test name
Test status
Simulation time 44228748 ps
CPU time 1.19 seconds
Started Jul 16 07:15:11 PM PDT 24
Finished Jul 16 07:16:06 PM PDT 24
Peak memory 220248 kb
Host smart-4c8124d3-0dad-4908-beb7-8b68805bfe49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778566611 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.2778566611
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.2872208188
Short name T784
Test name
Test status
Simulation time 56318581 ps
CPU time 1.18 seconds
Started Jul 16 07:14:59 PM PDT 24
Finished Jul 16 07:15:46 PM PDT 24
Peak memory 217536 kb
Host smart-73a0baa4-f3ba-4db0-81d4-ff677774e4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872208188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.2872208188
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.334795504
Short name T791
Test name
Test status
Simulation time 29543576 ps
CPU time 1.3 seconds
Started Jul 16 07:14:55 PM PDT 24
Finished Jul 16 07:15:41 PM PDT 24
Peak memory 220104 kb
Host smart-d364aa32-6278-4736-85e2-9401892b7863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334795504 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.334795504
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.248368913
Short name T958
Test name
Test status
Simulation time 42729049 ps
CPU time 1.61 seconds
Started Jul 16 07:14:56 PM PDT 24
Finished Jul 16 07:15:41 PM PDT 24
Peak memory 218720 kb
Host smart-14fae9e6-ffcc-46dd-a9b1-bd48446c3286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248368913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.248368913
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.763550911
Short name T584
Test name
Test status
Simulation time 48887590 ps
CPU time 1.1 seconds
Started Jul 16 07:14:58 PM PDT 24
Finished Jul 16 07:15:46 PM PDT 24
Peak memory 221076 kb
Host smart-4b5c6176-a0aa-4321-80b6-420d1d9be492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763550911 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.763550911
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.4050915233
Short name T14
Test name
Test status
Simulation time 69450491 ps
CPU time 1.68 seconds
Started Jul 16 07:14:59 PM PDT 24
Finished Jul 16 07:15:50 PM PDT 24
Peak memory 215596 kb
Host smart-fb3f0fa2-fdb9-4b49-a35d-002dbb6cb048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050915233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.4050915233
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.2152799318
Short name T873
Test name
Test status
Simulation time 70533964 ps
CPU time 1.09 seconds
Started Jul 16 07:15:10 PM PDT 24
Finished Jul 16 07:16:02 PM PDT 24
Peak memory 220960 kb
Host smart-e844148a-1349-4989-8fd1-f30bb2e36f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152799318 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.2152799318
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.3188382747
Short name T767
Test name
Test status
Simulation time 48668819 ps
CPU time 0.98 seconds
Started Jul 16 07:14:54 PM PDT 24
Finished Jul 16 07:15:36 PM PDT 24
Peak memory 217756 kb
Host smart-d8ca58ad-37ae-40dc-9703-d50f53758ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188382747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3188382747
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.289095483
Short name T262
Test name
Test status
Simulation time 30553828 ps
CPU time 1.26 seconds
Started Jul 16 07:12:28 PM PDT 24
Finished Jul 16 07:13:34 PM PDT 24
Peak memory 218944 kb
Host smart-af6371a0-f2b4-4765-97c9-270f22dfd4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289095483 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.289095483
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.1571144094
Short name T409
Test name
Test status
Simulation time 21322091 ps
CPU time 0.84 seconds
Started Jul 16 07:12:28 PM PDT 24
Finished Jul 16 07:13:34 PM PDT 24
Peak memory 207036 kb
Host smart-19762d6a-24c7-4f7c-9384-c74367add5fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571144094 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1571144094
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.726352548
Short name T382
Test name
Test status
Simulation time 11079802 ps
CPU time 0.84 seconds
Started Jul 16 07:12:31 PM PDT 24
Finished Jul 16 07:13:32 PM PDT 24
Peak memory 216260 kb
Host smart-4d16883c-9b44-460a-a5e4-3e23a9e8c322
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726352548 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.726352548
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.564547911
Short name T654
Test name
Test status
Simulation time 88394003 ps
CPU time 1 seconds
Started Jul 16 07:12:32 PM PDT 24
Finished Jul 16 07:13:33 PM PDT 24
Peak memory 217064 kb
Host smart-35a75cea-d8f8-409b-a851-0170788de546
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564547911 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_di
sable_auto_req_mode.564547911
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.4105776916
Short name T61
Test name
Test status
Simulation time 30344354 ps
CPU time 1.26 seconds
Started Jul 16 07:12:33 PM PDT 24
Finished Jul 16 07:13:35 PM PDT 24
Peak memory 220052 kb
Host smart-98f68b16-9601-436d-a1c5-23d449295aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105776916 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.4105776916
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.2077219295
Short name T424
Test name
Test status
Simulation time 90590957 ps
CPU time 1.33 seconds
Started Jul 16 07:12:28 PM PDT 24
Finished Jul 16 07:13:34 PM PDT 24
Peak memory 217664 kb
Host smart-bb21978d-2230-4789-8096-b42df559c0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077219295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.2077219295
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.3752702708
Short name T457
Test name
Test status
Simulation time 25905748 ps
CPU time 1.05 seconds
Started Jul 16 07:12:28 PM PDT 24
Finished Jul 16 07:13:32 PM PDT 24
Peak memory 224308 kb
Host smart-e7a38c20-08a6-41e2-9afc-43dc1d37c542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752702708 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3752702708
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.847048042
Short name T504
Test name
Test status
Simulation time 100155597 ps
CPU time 0.92 seconds
Started Jul 16 07:12:29 PM PDT 24
Finished Jul 16 07:13:34 PM PDT 24
Peak memory 215624 kb
Host smart-284b5444-72df-4906-8a9a-e978cf21a739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847048042 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.847048042
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.901567558
Short name T755
Test name
Test status
Simulation time 162423805041 ps
CPU time 1130.72 seconds
Started Jul 16 07:12:29 PM PDT 24
Finished Jul 16 07:32:24 PM PDT 24
Peak memory 223452 kb
Host smart-96a51a02-0312-47a2-b49e-59fe45c6f2aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901567558 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.901567558
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.1708245598
Short name T775
Test name
Test status
Simulation time 24999851 ps
CPU time 1.22 seconds
Started Jul 16 07:14:56 PM PDT 24
Finished Jul 16 07:15:41 PM PDT 24
Peak memory 219044 kb
Host smart-a91163c6-00ff-4e69-8d76-72fe9bdd463c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708245598 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.1708245598
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.2362078545
Short name T660
Test name
Test status
Simulation time 71253150 ps
CPU time 1.38 seconds
Started Jul 16 07:14:55 PM PDT 24
Finished Jul 16 07:15:38 PM PDT 24
Peak memory 218864 kb
Host smart-f3912b09-49e7-4464-bfe4-89e50ea0744c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362078545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2362078545
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.1180540935
Short name T113
Test name
Test status
Simulation time 39133999 ps
CPU time 1.17 seconds
Started Jul 16 07:15:02 PM PDT 24
Finished Jul 16 07:15:55 PM PDT 24
Peak memory 220088 kb
Host smart-261d72c0-275d-4784-ac6e-493f133b6566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180540935 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.1180540935
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.3980401505
Short name T781
Test name
Test status
Simulation time 41775265 ps
CPU time 1.43 seconds
Started Jul 16 07:15:12 PM PDT 24
Finished Jul 16 07:16:06 PM PDT 24
Peak memory 218652 kb
Host smart-c8d8e813-0732-4116-83ad-edefecb4253c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980401505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3980401505
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.3537039473
Short name T899
Test name
Test status
Simulation time 35394123 ps
CPU time 1.23 seconds
Started Jul 16 07:14:56 PM PDT 24
Finished Jul 16 07:15:41 PM PDT 24
Peak memory 218992 kb
Host smart-cc7b9c9f-c8d3-4d64-873e-995dc34e9023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537039473 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.3537039473
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/143.edn_alert.892750743
Short name T238
Test name
Test status
Simulation time 88791617 ps
CPU time 1.19 seconds
Started Jul 16 07:15:04 PM PDT 24
Finished Jul 16 07:15:55 PM PDT 24
Peak memory 218736 kb
Host smart-4ccd70f4-4e25-4e90-8794-55b799873366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892750743 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.892750743
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.3472368217
Short name T567
Test name
Test status
Simulation time 87824378 ps
CPU time 1.02 seconds
Started Jul 16 07:14:59 PM PDT 24
Finished Jul 16 07:15:49 PM PDT 24
Peak memory 217664 kb
Host smart-e3864836-afec-4876-8d63-c4dbfe15ec4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472368217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.3472368217
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.1432231075
Short name T209
Test name
Test status
Simulation time 44271959 ps
CPU time 1.16 seconds
Started Jul 16 07:14:59 PM PDT 24
Finished Jul 16 07:15:49 PM PDT 24
Peak memory 219996 kb
Host smart-4c33c680-e041-43c2-bb26-9f4728d441a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432231075 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.1432231075
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.4045848530
Short name T724
Test name
Test status
Simulation time 39353104 ps
CPU time 1.44 seconds
Started Jul 16 07:14:53 PM PDT 24
Finished Jul 16 07:15:37 PM PDT 24
Peak memory 218912 kb
Host smart-a6648e63-0788-43c6-8353-7e5d18fe6db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045848530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.4045848530
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.2280037446
Short name T814
Test name
Test status
Simulation time 118043503 ps
CPU time 1.05 seconds
Started Jul 16 07:14:54 PM PDT 24
Finished Jul 16 07:15:36 PM PDT 24
Peak memory 219772 kb
Host smart-0ea313af-076a-47d2-bbb6-c60d67f5efb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280037446 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.2280037446
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.295926021
Short name T386
Test name
Test status
Simulation time 92735427 ps
CPU time 1.48 seconds
Started Jul 16 07:15:01 PM PDT 24
Finished Jul 16 07:15:51 PM PDT 24
Peak memory 219116 kb
Host smart-c0a9c5dd-2291-4eff-8ee4-8729e6bf7cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295926021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.295926021
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.3632806680
Short name T148
Test name
Test status
Simulation time 27187038 ps
CPU time 1.19 seconds
Started Jul 16 07:14:56 PM PDT 24
Finished Jul 16 07:15:41 PM PDT 24
Peak memory 220176 kb
Host smart-9006d1d1-12eb-4411-b3dd-44a878dbe6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632806680 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.3632806680
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.3539131264
Short name T349
Test name
Test status
Simulation time 49987744 ps
CPU time 1.27 seconds
Started Jul 16 07:14:57 PM PDT 24
Finished Jul 16 07:15:45 PM PDT 24
Peak memory 217508 kb
Host smart-609eabf0-56ac-43f8-b794-f1f7d60aff4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539131264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.3539131264
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.3473982992
Short name T469
Test name
Test status
Simulation time 77254218 ps
CPU time 1.01 seconds
Started Jul 16 07:14:57 PM PDT 24
Finished Jul 16 07:15:46 PM PDT 24
Peak memory 218684 kb
Host smart-2f2bbef3-c024-41ee-ba63-2582262aa3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473982992 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.3473982992
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.2780455666
Short name T575
Test name
Test status
Simulation time 41256472 ps
CPU time 1.53 seconds
Started Jul 16 07:14:59 PM PDT 24
Finished Jul 16 07:15:47 PM PDT 24
Peak memory 217864 kb
Host smart-d94128d0-091d-4e2f-a390-8ee34567218c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780455666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.2780455666
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.3810386607
Short name T865
Test name
Test status
Simulation time 39324593 ps
CPU time 1.23 seconds
Started Jul 16 07:14:56 PM PDT 24
Finished Jul 16 07:15:41 PM PDT 24
Peak memory 219904 kb
Host smart-5a9611aa-a445-4d41-882e-727a3481d75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810386607 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.3810386607
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.1544055594
Short name T580
Test name
Test status
Simulation time 210441364 ps
CPU time 3.41 seconds
Started Jul 16 07:14:54 PM PDT 24
Finished Jul 16 07:15:39 PM PDT 24
Peak memory 217948 kb
Host smart-f189b87a-9b94-435d-88b7-1bbc3f655a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544055594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.1544055594
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.998790083
Short name T955
Test name
Test status
Simulation time 58787661 ps
CPU time 1.35 seconds
Started Jul 16 07:14:56 PM PDT 24
Finished Jul 16 07:15:41 PM PDT 24
Peak memory 218716 kb
Host smart-b345eba1-8df2-4fe7-bc52-062888d88fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998790083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.998790083
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.3094605854
Short name T501
Test name
Test status
Simulation time 66396017 ps
CPU time 1.24 seconds
Started Jul 16 07:12:32 PM PDT 24
Finished Jul 16 07:13:35 PM PDT 24
Peak memory 220896 kb
Host smart-a800fd47-db82-4aee-bfa1-52d5877e7b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094605854 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3094605854
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.2960089359
Short name T45
Test name
Test status
Simulation time 101655586 ps
CPU time 0.91 seconds
Started Jul 16 07:12:45 PM PDT 24
Finished Jul 16 07:13:36 PM PDT 24
Peak memory 207016 kb
Host smart-ae741c49-60be-4679-abb9-ff408ec84987
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960089359 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2960089359
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.3965976584
Short name T786
Test name
Test status
Simulation time 65508905 ps
CPU time 1.06 seconds
Started Jul 16 07:12:47 PM PDT 24
Finished Jul 16 07:13:35 PM PDT 24
Peak memory 219724 kb
Host smart-955b4f16-7c83-47ae-bee4-6e39ac98a5f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965976584 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.3965976584
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.3526283529
Short name T509
Test name
Test status
Simulation time 27176570 ps
CPU time 0.83 seconds
Started Jul 16 07:12:31 PM PDT 24
Finished Jul 16 07:13:32 PM PDT 24
Peak memory 218660 kb
Host smart-ade36c10-81fd-49ef-8bfa-e6d4d3c54052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526283529 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.3526283529
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.1046300935
Short name T972
Test name
Test status
Simulation time 96700898 ps
CPU time 1.22 seconds
Started Jul 16 07:12:28 PM PDT 24
Finished Jul 16 07:13:34 PM PDT 24
Peak memory 220260 kb
Host smart-0eeaa6d9-3040-4c3d-b8d3-d119172126c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046300935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1046300935
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.281015448
Short name T745
Test name
Test status
Simulation time 31663654 ps
CPU time 0.95 seconds
Started Jul 16 07:12:32 PM PDT 24
Finished Jul 16 07:13:33 PM PDT 24
Peak memory 224308 kb
Host smart-7ac031d5-cbc9-4830-b323-08e5f8b346f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281015448 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.281015448
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.1642134565
Short name T722
Test name
Test status
Simulation time 15996730 ps
CPU time 0.97 seconds
Started Jul 16 07:12:31 PM PDT 24
Finished Jul 16 07:13:31 PM PDT 24
Peak memory 215564 kb
Host smart-b046e7be-7363-4e99-ba08-3e38e2c5cfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642134565 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.1642134565
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.912248768
Short name T467
Test name
Test status
Simulation time 481808021 ps
CPU time 5.17 seconds
Started Jul 16 07:12:33 PM PDT 24
Finished Jul 16 07:13:39 PM PDT 24
Peak memory 218716 kb
Host smart-cbcf6c2e-ecd6-4ad9-b9a5-81fd195172a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912248768 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.912248768
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.3202823975
Short name T222
Test name
Test status
Simulation time 72584153381 ps
CPU time 1545.03 seconds
Started Jul 16 07:12:33 PM PDT 24
Finished Jul 16 07:39:19 PM PDT 24
Peak memory 223284 kb
Host smart-acab65b5-9dc5-41be-99a0-2310a1c110a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202823975 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.3202823975
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.3872877740
Short name T849
Test name
Test status
Simulation time 47004255 ps
CPU time 1.17 seconds
Started Jul 16 07:14:57 PM PDT 24
Finished Jul 16 07:15:46 PM PDT 24
Peak memory 220216 kb
Host smart-fe1864a3-eca6-489c-9c07-e153ea5201e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872877740 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.3872877740
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.3437300630
Short name T620
Test name
Test status
Simulation time 33790827 ps
CPU time 1.64 seconds
Started Jul 16 07:14:56 PM PDT 24
Finished Jul 16 07:15:41 PM PDT 24
Peak memory 217760 kb
Host smart-e3caedc6-1d58-4e94-af14-b5254dcfb929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437300630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3437300630
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.1708249885
Short name T24
Test name
Test status
Simulation time 84567315 ps
CPU time 1.17 seconds
Started Jul 16 07:14:57 PM PDT 24
Finished Jul 16 07:15:46 PM PDT 24
Peak memory 219956 kb
Host smart-9dd66cb9-a1bf-419f-900b-49a4fb98b74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708249885 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.1708249885
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.324089738
Short name T410
Test name
Test status
Simulation time 46637201 ps
CPU time 1.58 seconds
Started Jul 16 07:14:59 PM PDT 24
Finished Jul 16 07:15:50 PM PDT 24
Peak memory 218896 kb
Host smart-ebe4115e-0aa3-4cfa-9fb9-7c54fbdfd285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324089738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.324089738
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.2743886784
Short name T782
Test name
Test status
Simulation time 90209445 ps
CPU time 1.01 seconds
Started Jul 16 07:14:55 PM PDT 24
Finished Jul 16 07:15:41 PM PDT 24
Peak memory 219768 kb
Host smart-d90c384b-8334-474a-93b8-7eb328c0d6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743886784 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.2743886784
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/153.edn_alert.2239851172
Short name T173
Test name
Test status
Simulation time 24470451 ps
CPU time 1.21 seconds
Started Jul 16 07:14:59 PM PDT 24
Finished Jul 16 07:15:50 PM PDT 24
Peak memory 220052 kb
Host smart-6d8e12b3-9a77-48b4-ad9b-7ce000df7450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239851172 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.2239851172
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.1160557709
Short name T316
Test name
Test status
Simulation time 73411316 ps
CPU time 1.88 seconds
Started Jul 16 07:14:59 PM PDT 24
Finished Jul 16 07:15:51 PM PDT 24
Peak memory 220572 kb
Host smart-1d791b93-5808-4c49-8101-f3cd37cb206e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160557709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.1160557709
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.1512362775
Short name T418
Test name
Test status
Simulation time 32608056 ps
CPU time 1.32 seconds
Started Jul 16 07:15:00 PM PDT 24
Finished Jul 16 07:15:50 PM PDT 24
Peak memory 215960 kb
Host smart-4d1a4d4a-b079-4ad8-8cf5-0d8af3b2105f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512362775 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.1512362775
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.1236456843
Short name T22
Test name
Test status
Simulation time 25271712 ps
CPU time 1.14 seconds
Started Jul 16 07:14:57 PM PDT 24
Finished Jul 16 07:15:46 PM PDT 24
Peak memory 217692 kb
Host smart-ffe1473f-c7f6-4be2-a74a-b0edac054a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236456843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1236456843
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.1612485579
Short name T66
Test name
Test status
Simulation time 46309890 ps
CPU time 1.2 seconds
Started Jul 16 07:14:55 PM PDT 24
Finished Jul 16 07:15:41 PM PDT 24
Peak memory 219368 kb
Host smart-51c46dd5-3e97-4c62-8fa6-b9399d3945fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612485579 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.1612485579
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.1378982596
Short name T615
Test name
Test status
Simulation time 57941474 ps
CPU time 1.92 seconds
Started Jul 16 07:14:59 PM PDT 24
Finished Jul 16 07:15:50 PM PDT 24
Peak memory 218920 kb
Host smart-c0b13ae5-99bc-4cd5-8120-31af8586e9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378982596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1378982596
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.4233863232
Short name T833
Test name
Test status
Simulation time 29421793 ps
CPU time 1.32 seconds
Started Jul 16 07:14:58 PM PDT 24
Finished Jul 16 07:15:46 PM PDT 24
Peak memory 218896 kb
Host smart-ceda0aed-4a39-4932-a3f1-b85084619271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233863232 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.4233863232
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.3785840947
Short name T226
Test name
Test status
Simulation time 86212457 ps
CPU time 1.01 seconds
Started Jul 16 07:14:52 PM PDT 24
Finished Jul 16 07:15:36 PM PDT 24
Peak memory 215588 kb
Host smart-842029bf-fd03-4332-a65e-d567495f3275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785840947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3785840947
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.537720811
Short name T572
Test name
Test status
Simulation time 73596916 ps
CPU time 1.09 seconds
Started Jul 16 07:14:57 PM PDT 24
Finished Jul 16 07:15:45 PM PDT 24
Peak memory 218864 kb
Host smart-6d3a41ae-009d-4b3c-9c49-0e21b5c712e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537720811 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.537720811
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.2236484536
Short name T910
Test name
Test status
Simulation time 84894352 ps
CPU time 1.27 seconds
Started Jul 16 07:15:03 PM PDT 24
Finished Jul 16 07:15:55 PM PDT 24
Peak memory 220104 kb
Host smart-1f92e5a0-86ac-4721-a7e9-a05b9578aca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236484536 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.2236484536
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.904877699
Short name T984
Test name
Test status
Simulation time 42414547 ps
CPU time 1.08 seconds
Started Jul 16 07:15:01 PM PDT 24
Finished Jul 16 07:15:50 PM PDT 24
Peak memory 218896 kb
Host smart-6f533f63-9812-42e7-9e8e-7915fad55407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904877699 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.904877699
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.1638840663
Short name T492
Test name
Test status
Simulation time 71043169 ps
CPU time 1.35 seconds
Started Jul 16 07:14:57 PM PDT 24
Finished Jul 16 07:15:46 PM PDT 24
Peak memory 218828 kb
Host smart-8c2ecf20-bb0e-4f1b-9ef1-2267cc976566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638840663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1638840663
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.1691822998
Short name T528
Test name
Test status
Simulation time 36400574 ps
CPU time 1.29 seconds
Started Jul 16 07:14:58 PM PDT 24
Finished Jul 16 07:15:46 PM PDT 24
Peak memory 219700 kb
Host smart-c9e7df0d-3df6-41a4-af26-149c7172c4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691822998 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.1691822998
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.265557348
Short name T917
Test name
Test status
Simulation time 89954103 ps
CPU time 1.11 seconds
Started Jul 16 07:15:01 PM PDT 24
Finished Jul 16 07:15:50 PM PDT 24
Peak memory 217560 kb
Host smart-775e29e8-085a-432c-8afe-d9d211eebb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265557348 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.265557348
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.1528940500
Short name T587
Test name
Test status
Simulation time 65816558 ps
CPU time 1.15 seconds
Started Jul 16 07:12:42 PM PDT 24
Finished Jul 16 07:13:35 PM PDT 24
Peak memory 219968 kb
Host smart-2e38a248-b407-4137-9373-65b914230102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528940500 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.1528940500
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.3107799590
Short name T742
Test name
Test status
Simulation time 21354457 ps
CPU time 0.89 seconds
Started Jul 16 07:12:45 PM PDT 24
Finished Jul 16 07:13:36 PM PDT 24
Peak memory 207028 kb
Host smart-e54834b7-c592-43f9-825b-c1aa365cf19e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107799590 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3107799590
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.2308535252
Short name T169
Test name
Test status
Simulation time 17550342 ps
CPU time 0.89 seconds
Started Jul 16 07:12:44 PM PDT 24
Finished Jul 16 07:13:36 PM PDT 24
Peak memory 216504 kb
Host smart-1a733a32-ab72-4785-aac9-234916dfe233
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308535252 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2308535252
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_err.375277805
Short name T135
Test name
Test status
Simulation time 20400482 ps
CPU time 1.13 seconds
Started Jul 16 07:12:42 PM PDT 24
Finished Jul 16 07:13:35 PM PDT 24
Peak memory 224288 kb
Host smart-8d37e931-95c8-4011-b140-d78a3aa4ab4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375277805 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.375277805
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.1567925435
Short name T351
Test name
Test status
Simulation time 68898653 ps
CPU time 1.12 seconds
Started Jul 16 07:12:43 PM PDT 24
Finished Jul 16 07:13:35 PM PDT 24
Peak memory 220252 kb
Host smart-db97d24c-efa4-42f4-9d49-d564996e1318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567925435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.1567925435
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.35330907
Short name T672
Test name
Test status
Simulation time 87069227 ps
CPU time 0.86 seconds
Started Jul 16 07:12:45 PM PDT 24
Finished Jul 16 07:13:36 PM PDT 24
Peak memory 215616 kb
Host smart-132ef109-9eb1-49a5-b146-94ac483e3e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35330907 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.35330907
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.816289874
Short name T579
Test name
Test status
Simulation time 18045216 ps
CPU time 0.96 seconds
Started Jul 16 07:12:43 PM PDT 24
Finished Jul 16 07:13:34 PM PDT 24
Peak memory 215552 kb
Host smart-7566bb60-8b66-40b2-881e-f702d3213e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816289874 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.816289874
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.1770432038
Short name T407
Test name
Test status
Simulation time 906822297 ps
CPU time 3.67 seconds
Started Jul 16 07:12:44 PM PDT 24
Finished Jul 16 07:13:38 PM PDT 24
Peak memory 217584 kb
Host smart-1d62ea0b-5e1d-45f0-82b7-830ae5c6aeef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770432038 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.1770432038
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.956236674
Short name T641
Test name
Test status
Simulation time 282319381627 ps
CPU time 1789.81 seconds
Started Jul 16 07:12:45 PM PDT 24
Finished Jul 16 07:43:25 PM PDT 24
Peak memory 228380 kb
Host smart-6248154f-afdd-4be9-8f97-17d9a3af4cb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956236674 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.956236674
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.2925882449
Short name T174
Test name
Test status
Simulation time 72362784 ps
CPU time 1.14 seconds
Started Jul 16 07:15:02 PM PDT 24
Finished Jul 16 07:15:54 PM PDT 24
Peak memory 219912 kb
Host smart-553bea95-78f8-4d72-aec4-7c5f8d612750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925882449 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.2925882449
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.1301244886
Short name T393
Test name
Test status
Simulation time 106800986 ps
CPU time 1.62 seconds
Started Jul 16 07:14:56 PM PDT 24
Finished Jul 16 07:15:41 PM PDT 24
Peak memory 218608 kb
Host smart-6c64140b-cb9f-4c64-b361-247d9ea862a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301244886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1301244886
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.1775312551
Short name T864
Test name
Test status
Simulation time 86455612 ps
CPU time 1.1 seconds
Started Jul 16 07:14:58 PM PDT 24
Finished Jul 16 07:15:46 PM PDT 24
Peak memory 219856 kb
Host smart-452faa3c-6dad-40d3-abfd-223d26e10637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775312551 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.1775312551
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.1436469633
Short name T362
Test name
Test status
Simulation time 123900490 ps
CPU time 1 seconds
Started Jul 16 07:14:59 PM PDT 24
Finished Jul 16 07:15:50 PM PDT 24
Peak memory 217628 kb
Host smart-ca1b17e6-07d2-4136-8f9d-74a89dd80154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436469633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1436469633
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.1580123883
Short name T109
Test name
Test status
Simulation time 76693522 ps
CPU time 1.16 seconds
Started Jul 16 07:15:01 PM PDT 24
Finished Jul 16 07:15:50 PM PDT 24
Peak memory 220432 kb
Host smart-2f334901-fd06-4909-93a8-41b9e37ee063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580123883 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.1580123883
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.2473440725
Short name T695
Test name
Test status
Simulation time 84988510 ps
CPU time 0.98 seconds
Started Jul 16 07:14:57 PM PDT 24
Finished Jul 16 07:15:46 PM PDT 24
Peak memory 217496 kb
Host smart-86e5c484-d127-464f-b1fe-0206523ef605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473440725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.2473440725
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.275857496
Short name T682
Test name
Test status
Simulation time 26755121 ps
CPU time 1.25 seconds
Started Jul 16 07:15:10 PM PDT 24
Finished Jul 16 07:16:02 PM PDT 24
Peak memory 220864 kb
Host smart-76918d5c-d815-4289-8775-9721ed5dcdbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275857496 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.275857496
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.3890064118
Short name T627
Test name
Test status
Simulation time 53634281 ps
CPU time 1.25 seconds
Started Jul 16 07:14:56 PM PDT 24
Finished Jul 16 07:15:41 PM PDT 24
Peak memory 217756 kb
Host smart-872bfd08-0499-4500-8ca6-260a2879b131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890064118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.3890064118
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.1507143649
Short name T912
Test name
Test status
Simulation time 51893947 ps
CPU time 1.25 seconds
Started Jul 16 07:15:12 PM PDT 24
Finished Jul 16 07:16:06 PM PDT 24
Peak memory 216028 kb
Host smart-f68f6be3-869c-4329-804a-d6d1cd416378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507143649 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.1507143649
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.2865285437
Short name T397
Test name
Test status
Simulation time 165183378 ps
CPU time 0.97 seconds
Started Jul 16 07:15:15 PM PDT 24
Finished Jul 16 07:16:11 PM PDT 24
Peak memory 217536 kb
Host smart-72fcd305-f2d0-4319-8337-8350d7fa8f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865285437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2865285437
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.932717842
Short name T804
Test name
Test status
Simulation time 48287816 ps
CPU time 1.16 seconds
Started Jul 16 07:15:13 PM PDT 24
Finished Jul 16 07:16:07 PM PDT 24
Peak memory 218956 kb
Host smart-cabe63d9-3581-4e79-92d7-14a46ba4ca53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932717842 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.932717842
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.3328850850
Short name T876
Test name
Test status
Simulation time 64961224 ps
CPU time 1.52 seconds
Started Jul 16 07:15:15 PM PDT 24
Finished Jul 16 07:16:12 PM PDT 24
Peak memory 219052 kb
Host smart-92307c50-45dd-4543-82ff-881a888259f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328850850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3328850850
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.342048026
Short name T121
Test name
Test status
Simulation time 100076105 ps
CPU time 1.2 seconds
Started Jul 16 07:15:14 PM PDT 24
Finished Jul 16 07:16:11 PM PDT 24
Peak memory 216068 kb
Host smart-b61a49b0-5b2d-43b8-a0ab-ad8ab4c0abbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342048026 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.342048026
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.3322905058
Short name T807
Test name
Test status
Simulation time 43662050 ps
CPU time 1.49 seconds
Started Jul 16 07:15:13 PM PDT 24
Finished Jul 16 07:16:08 PM PDT 24
Peak memory 219168 kb
Host smart-cf4186a6-b111-4e25-894f-21cfa2df294b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322905058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.3322905058
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.1215463577
Short name T239
Test name
Test status
Simulation time 49539196 ps
CPU time 1.19 seconds
Started Jul 16 07:15:14 PM PDT 24
Finished Jul 16 07:16:11 PM PDT 24
Peak memory 219568 kb
Host smart-08e49654-390f-4015-9540-85c22ad3eb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215463577 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.1215463577
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.1149202906
Short name T766
Test name
Test status
Simulation time 70856815 ps
CPU time 1.3 seconds
Started Jul 16 07:15:11 PM PDT 24
Finished Jul 16 07:16:06 PM PDT 24
Peak memory 219336 kb
Host smart-ed238027-7cbd-4870-bcf5-4da86e1e98f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149202906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1149202906
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.1101955724
Short name T141
Test name
Test status
Simulation time 91559529 ps
CPU time 1.19 seconds
Started Jul 16 07:15:15 PM PDT 24
Finished Jul 16 07:16:11 PM PDT 24
Peak memory 220116 kb
Host smart-e13e87a6-4fdc-4953-8d8b-cb997cb71b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101955724 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.1101955724
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.3987605592
Short name T629
Test name
Test status
Simulation time 54569590 ps
CPU time 1.19 seconds
Started Jul 16 07:15:15 PM PDT 24
Finished Jul 16 07:16:11 PM PDT 24
Peak memory 218768 kb
Host smart-9045e039-e4f0-47fe-bcb4-0b9182335cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987605592 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.3987605592
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.3735712000
Short name T555
Test name
Test status
Simulation time 206991463 ps
CPU time 1.28 seconds
Started Jul 16 07:15:12 PM PDT 24
Finished Jul 16 07:16:07 PM PDT 24
Peak memory 216008 kb
Host smart-978694b6-0826-4069-b3ba-1497848311f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735712000 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.3735712000
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.1401287781
Short name T320
Test name
Test status
Simulation time 98246947 ps
CPU time 1.42 seconds
Started Jul 16 07:15:14 PM PDT 24
Finished Jul 16 07:16:11 PM PDT 24
Peak memory 219300 kb
Host smart-69539484-f74d-4c43-89c5-f8831b9f1195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401287781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.1401287781
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert_test.3477573497
Short name T514
Test name
Test status
Simulation time 15022115 ps
CPU time 0.87 seconds
Started Jul 16 07:13:01 PM PDT 24
Finished Jul 16 07:13:36 PM PDT 24
Peak memory 206888 kb
Host smart-55b24dce-fd72-48c7-8cdf-5fee707215ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477573497 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3477573497
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.398902730
Short name T201
Test name
Test status
Simulation time 13688303 ps
CPU time 0.91 seconds
Started Jul 16 07:12:43 PM PDT 24
Finished Jul 16 07:13:35 PM PDT 24
Peak memory 216760 kb
Host smart-46a6e2f0-aae8-4c54-836f-6300503453f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398902730 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.398902730
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.3195683330
Short name T920
Test name
Test status
Simulation time 351918319 ps
CPU time 1.13 seconds
Started Jul 16 07:12:56 PM PDT 24
Finished Jul 16 07:13:36 PM PDT 24
Peak memory 217056 kb
Host smart-45cb4d21-789b-4a6d-92c9-9f9aaaf5e1d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195683330 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.3195683330
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.4167671808
Short name T589
Test name
Test status
Simulation time 29190341 ps
CPU time 0.94 seconds
Started Jul 16 07:12:47 PM PDT 24
Finished Jul 16 07:13:35 PM PDT 24
Peak memory 223976 kb
Host smart-31816f2c-85d0-4daa-9c28-9cb2e06a53ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167671808 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.4167671808
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_intr.2832568525
Short name T473
Test name
Test status
Simulation time 35770370 ps
CPU time 0.92 seconds
Started Jul 16 07:12:47 PM PDT 24
Finished Jul 16 07:13:35 PM PDT 24
Peak memory 215748 kb
Host smart-8e0bc780-856f-4e11-894c-1ef387b9207b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832568525 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.2832568525
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.2280881611
Short name T511
Test name
Test status
Simulation time 16477633 ps
CPU time 1 seconds
Started Jul 16 07:12:43 PM PDT 24
Finished Jul 16 07:13:35 PM PDT 24
Peak memory 215612 kb
Host smart-529fb55f-5166-4658-a1ee-77a9a264c3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280881611 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.2280881611
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1079447714
Short name T500
Test name
Test status
Simulation time 287268520 ps
CPU time 3.22 seconds
Started Jul 16 07:12:42 PM PDT 24
Finished Jul 16 07:13:37 PM PDT 24
Peak memory 217696 kb
Host smart-b9fb91f6-8887-446c-87c5-d8fed148f7e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079447714 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1079447714
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.101354415
Short name T941
Test name
Test status
Simulation time 57175425550 ps
CPU time 1056.82 seconds
Started Jul 16 07:12:45 PM PDT 24
Finished Jul 16 07:31:11 PM PDT 24
Peak memory 222544 kb
Host smart-91f4fc65-876a-4f6a-8c9e-29348c6de7b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101354415 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.101354415
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.2422352795
Short name T689
Test name
Test status
Simulation time 49559438 ps
CPU time 1.25 seconds
Started Jul 16 07:15:14 PM PDT 24
Finished Jul 16 07:16:11 PM PDT 24
Peak memory 219056 kb
Host smart-5f24812f-66a6-4be2-a1f7-8584173f2bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422352795 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.2422352795
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.2589480968
Short name T389
Test name
Test status
Simulation time 29200873 ps
CPU time 1.32 seconds
Started Jul 16 07:15:11 PM PDT 24
Finished Jul 16 07:16:07 PM PDT 24
Peak memory 217592 kb
Host smart-615d5667-6c65-432a-9cf5-23a4782b8a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589480968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.2589480968
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.4148385881
Short name T950
Test name
Test status
Simulation time 69704797 ps
CPU time 1.07 seconds
Started Jul 16 07:15:10 PM PDT 24
Finished Jul 16 07:16:02 PM PDT 24
Peak memory 218888 kb
Host smart-643afd1b-4b52-4998-901e-42bd30fe132e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148385881 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.4148385881
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.629617830
Short name T448
Test name
Test status
Simulation time 38071538 ps
CPU time 1.36 seconds
Started Jul 16 07:15:10 PM PDT 24
Finished Jul 16 07:16:02 PM PDT 24
Peak memory 217776 kb
Host smart-ea16c1b2-024c-44ac-a7f6-ac1da966731f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629617830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.629617830
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.296567054
Short name T439
Test name
Test status
Simulation time 86598395 ps
CPU time 1.26 seconds
Started Jul 16 07:15:15 PM PDT 24
Finished Jul 16 07:16:11 PM PDT 24
Peak memory 218836 kb
Host smart-390149ba-5e27-4c32-b863-7a4aa2d22bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296567054 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.296567054
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.3182621984
Short name T750
Test name
Test status
Simulation time 371059691 ps
CPU time 1.8 seconds
Started Jul 16 07:15:15 PM PDT 24
Finished Jul 16 07:16:12 PM PDT 24
Peak memory 219016 kb
Host smart-65a3b5dd-34f3-4a39-be99-382e47484ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182621984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.3182621984
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.2215728727
Short name T597
Test name
Test status
Simulation time 22018234 ps
CPU time 1.11 seconds
Started Jul 16 07:15:14 PM PDT 24
Finished Jul 16 07:16:07 PM PDT 24
Peak memory 220124 kb
Host smart-e3d8d419-b5ce-4ecb-9089-e6621b002d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215728727 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.2215728727
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/174.edn_alert.861224290
Short name T556
Test name
Test status
Simulation time 46582526 ps
CPU time 1.23 seconds
Started Jul 16 07:15:09 PM PDT 24
Finished Jul 16 07:16:01 PM PDT 24
Peak memory 215952 kb
Host smart-4a08931a-e00d-4f48-ac25-7ac2e6c9193e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861224290 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.861224290
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.2978995654
Short name T233
Test name
Test status
Simulation time 39555311 ps
CPU time 1.27 seconds
Started Jul 16 07:15:16 PM PDT 24
Finished Jul 16 07:16:12 PM PDT 24
Peak memory 217524 kb
Host smart-1b8d0419-345c-4a66-8cef-07fe302baef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978995654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.2978995654
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.2916214405
Short name T845
Test name
Test status
Simulation time 85260534 ps
CPU time 1.19 seconds
Started Jul 16 07:15:15 PM PDT 24
Finished Jul 16 07:16:12 PM PDT 24
Peak memory 219964 kb
Host smart-d61ab6b6-06ec-4e8b-874d-b7f8055b5e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916214405 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.2916214405
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.617477888
Short name T512
Test name
Test status
Simulation time 50338543 ps
CPU time 1.08 seconds
Started Jul 16 07:15:12 PM PDT 24
Finished Jul 16 07:16:07 PM PDT 24
Peak memory 217696 kb
Host smart-970750d3-3b03-46cd-b9d0-980350ba5f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617477888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.617477888
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.355058490
Short name T468
Test name
Test status
Simulation time 53292786 ps
CPU time 1.21 seconds
Started Jul 16 07:15:18 PM PDT 24
Finished Jul 16 07:16:14 PM PDT 24
Peak memory 218804 kb
Host smart-2e2a44bd-35bb-4367-9764-8cbfeda9cfff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355058490 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.355058490
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.1974664358
Short name T283
Test name
Test status
Simulation time 74601183 ps
CPU time 1.28 seconds
Started Jul 16 07:15:14 PM PDT 24
Finished Jul 16 07:16:11 PM PDT 24
Peak memory 219264 kb
Host smart-c00ce75e-5397-4387-87ee-9751a2607769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974664358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.1974664358
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.1943857619
Short name T981
Test name
Test status
Simulation time 347094952 ps
CPU time 1.39 seconds
Started Jul 16 07:15:13 PM PDT 24
Finished Jul 16 07:16:08 PM PDT 24
Peak memory 218724 kb
Host smart-067e799e-e341-4498-a0c5-32e3d4aff3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943857619 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.1943857619
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.380797382
Short name T338
Test name
Test status
Simulation time 44437954 ps
CPU time 1.46 seconds
Started Jul 16 07:15:15 PM PDT 24
Finished Jul 16 07:16:12 PM PDT 24
Peak memory 217344 kb
Host smart-46a82276-b434-4e3e-b06a-0462df745059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380797382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.380797382
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.3055951682
Short name T725
Test name
Test status
Simulation time 89533425 ps
CPU time 1.17 seconds
Started Jul 16 07:15:15 PM PDT 24
Finished Jul 16 07:16:11 PM PDT 24
Peak memory 220812 kb
Host smart-8a2e3b0b-a55a-441f-8c72-a114750a7f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055951682 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.3055951682
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.260535241
Short name T83
Test name
Test status
Simulation time 69574448 ps
CPU time 1.16 seconds
Started Jul 16 07:15:12 PM PDT 24
Finished Jul 16 07:16:06 PM PDT 24
Peak memory 217996 kb
Host smart-3567507b-5360-4ee8-bff8-f2a3d0add766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260535241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.260535241
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.1974481119
Short name T147
Test name
Test status
Simulation time 22367347 ps
CPU time 1.17 seconds
Started Jul 16 07:15:12 PM PDT 24
Finished Jul 16 07:16:06 PM PDT 24
Peak memory 215988 kb
Host smart-a2ed4d99-6a22-46d9-b0d5-06d8c10e7c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974481119 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.1974481119
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.1747700815
Short name T655
Test name
Test status
Simulation time 190251157 ps
CPU time 1.03 seconds
Started Jul 16 07:15:14 PM PDT 24
Finished Jul 16 07:16:08 PM PDT 24
Peak memory 217456 kb
Host smart-ba7c5590-2690-47c9-a4c6-4c07b6822800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747700815 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.1747700815
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.443898069
Short name T842
Test name
Test status
Simulation time 65233559 ps
CPU time 1.07 seconds
Started Jul 16 07:12:55 PM PDT 24
Finished Jul 16 07:13:36 PM PDT 24
Peak memory 219048 kb
Host smart-8cb3295e-f582-4340-919b-3f99d7917669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443898069 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.443898069
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.2507291791
Short name T679
Test name
Test status
Simulation time 62763558 ps
CPU time 0.86 seconds
Started Jul 16 07:13:02 PM PDT 24
Finished Jul 16 07:13:37 PM PDT 24
Peak memory 215128 kb
Host smart-71424d4f-c80c-4917-9032-1e46a583691f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507291791 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2507291791
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.2934243410
Short name T205
Test name
Test status
Simulation time 13125623 ps
CPU time 0.96 seconds
Started Jul 16 07:12:57 PM PDT 24
Finished Jul 16 07:13:36 PM PDT 24
Peak memory 216684 kb
Host smart-11ff9d63-e331-428d-a333-65e3fc442685
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934243410 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2934243410
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_err.576593307
Short name T392
Test name
Test status
Simulation time 85494244 ps
CPU time 1.09 seconds
Started Jul 16 07:12:55 PM PDT 24
Finished Jul 16 07:13:36 PM PDT 24
Peak memory 219884 kb
Host smart-528b220d-cb7d-47c5-92b5-434f5a193d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576593307 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.576593307
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.3716562862
Short name T557
Test name
Test status
Simulation time 48799782 ps
CPU time 1.6 seconds
Started Jul 16 07:12:58 PM PDT 24
Finished Jul 16 07:13:37 PM PDT 24
Peak memory 217748 kb
Host smart-661c2623-fee4-4ae3-ade0-4376ae0a59f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716562862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.3716562862
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.3165694813
Short name T630
Test name
Test status
Simulation time 32736290 ps
CPU time 0.9 seconds
Started Jul 16 07:13:01 PM PDT 24
Finished Jul 16 07:13:36 PM PDT 24
Peak memory 215892 kb
Host smart-ea528e50-1502-42cb-89f5-c7b7b138dcb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165694813 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.3165694813
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.1861311209
Short name T874
Test name
Test status
Simulation time 52032024 ps
CPU time 0.95 seconds
Started Jul 16 07:13:01 PM PDT 24
Finished Jul 16 07:13:37 PM PDT 24
Peak memory 215584 kb
Host smart-4809a727-d5b9-4855-8373-e1bb4888e9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861311209 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.1861311209
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.240031094
Short name T668
Test name
Test status
Simulation time 415249003 ps
CPU time 7.85 seconds
Started Jul 16 07:12:56 PM PDT 24
Finished Jul 16 07:13:43 PM PDT 24
Peak memory 217376 kb
Host smart-66623eb6-3906-4ed1-a5db-3b3ffead2fe3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240031094 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.240031094
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2663089767
Short name T569
Test name
Test status
Simulation time 180097952449 ps
CPU time 977.91 seconds
Started Jul 16 07:13:02 PM PDT 24
Finished Jul 16 07:29:53 PM PDT 24
Peak memory 221808 kb
Host smart-7380aea0-8464-4559-8b17-8f8711af1755
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663089767 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.2663089767
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.3705436058
Short name T227
Test name
Test status
Simulation time 37194164 ps
CPU time 1.49 seconds
Started Jul 16 07:15:13 PM PDT 24
Finished Jul 16 07:16:08 PM PDT 24
Peak memory 218960 kb
Host smart-6f6790e0-c6e4-4d5e-beb3-726fe16465af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705436058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.3705436058
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.1403648821
Short name T801
Test name
Test status
Simulation time 91103041 ps
CPU time 1.17 seconds
Started Jul 16 07:15:15 PM PDT 24
Finished Jul 16 07:16:11 PM PDT 24
Peak memory 215992 kb
Host smart-9f62fe07-a1fc-42a2-b4d8-7015f036434f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403648821 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.1403648821
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.4044533999
Short name T602
Test name
Test status
Simulation time 49021272 ps
CPU time 1.43 seconds
Started Jul 16 07:15:15 PM PDT 24
Finished Jul 16 07:16:11 PM PDT 24
Peak memory 218952 kb
Host smart-6086442b-2391-4d4e-bce0-1d31b325eb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044533999 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.4044533999
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.3834747841
Short name T282
Test name
Test status
Simulation time 25929682 ps
CPU time 1.18 seconds
Started Jul 16 07:15:16 PM PDT 24
Finished Jul 16 07:16:12 PM PDT 24
Peak memory 220000 kb
Host smart-7e998b21-010f-4351-82fc-da5f0218d9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834747841 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.3834747841
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.3534637005
Short name T645
Test name
Test status
Simulation time 43841632 ps
CPU time 1.71 seconds
Started Jul 16 07:15:13 PM PDT 24
Finished Jul 16 07:16:08 PM PDT 24
Peak memory 217708 kb
Host smart-01f69d50-d142-4690-996d-77874e92e979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534637005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.3534637005
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.3867027216
Short name T77
Test name
Test status
Simulation time 79780911 ps
CPU time 1.09 seconds
Started Jul 16 07:15:14 PM PDT 24
Finished Jul 16 07:16:11 PM PDT 24
Peak memory 220012 kb
Host smart-1c571ffd-b82a-415e-a136-22ca549591de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867027216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.3867027216
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.1616334357
Short name T289
Test name
Test status
Simulation time 26005052 ps
CPU time 1.18 seconds
Started Jul 16 07:15:15 PM PDT 24
Finished Jul 16 07:16:11 PM PDT 24
Peak memory 219732 kb
Host smart-ccb834e0-4cdb-4568-a2a0-e92016cbff8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616334357 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.1616334357
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.2488744080
Short name T667
Test name
Test status
Simulation time 48519097 ps
CPU time 1.45 seconds
Started Jul 16 07:15:12 PM PDT 24
Finished Jul 16 07:16:07 PM PDT 24
Peak memory 220284 kb
Host smart-f43eb3cc-f6aa-4a7e-be9e-90f1871e14ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488744080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2488744080
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.2987941012
Short name T497
Test name
Test status
Simulation time 73328745 ps
CPU time 1.16 seconds
Started Jul 16 07:15:11 PM PDT 24
Finished Jul 16 07:16:06 PM PDT 24
Peak memory 219228 kb
Host smart-e0464273-78b9-471a-97f0-31c023f6784c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987941012 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.2987941012
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.2137779105
Short name T789
Test name
Test status
Simulation time 110458139 ps
CPU time 1.27 seconds
Started Jul 16 07:15:15 PM PDT 24
Finished Jul 16 07:16:11 PM PDT 24
Peak memory 218604 kb
Host smart-19e2f3f3-3e31-442b-9f3e-f92b55d9d258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137779105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.2137779105
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.1068284584
Short name T73
Test name
Test status
Simulation time 43601491 ps
CPU time 1.23 seconds
Started Jul 16 07:15:12 PM PDT 24
Finished Jul 16 07:16:07 PM PDT 24
Peak memory 218648 kb
Host smart-fca9d3a4-d72a-48c2-8fc6-f226e513727d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068284584 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.1068284584
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.871215051
Short name T927
Test name
Test status
Simulation time 85292827 ps
CPU time 1.43 seconds
Started Jul 16 07:15:14 PM PDT 24
Finished Jul 16 07:16:11 PM PDT 24
Peak memory 217680 kb
Host smart-aa16feed-ebdb-4d24-ac9e-053394ee2fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871215051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.871215051
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.4258331249
Short name T134
Test name
Test status
Simulation time 25050732 ps
CPU time 1.2 seconds
Started Jul 16 07:15:14 PM PDT 24
Finished Jul 16 07:16:08 PM PDT 24
Peak memory 218892 kb
Host smart-7fdf5302-74be-493d-8595-a48bed68fed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258331249 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.4258331249
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.3432549042
Short name T748
Test name
Test status
Simulation time 51123856 ps
CPU time 1.93 seconds
Started Jul 16 07:15:17 PM PDT 24
Finished Jul 16 07:16:12 PM PDT 24
Peak memory 218868 kb
Host smart-99901952-dc3e-4a2d-929d-f724afad64db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432549042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3432549042
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.1348111706
Short name T236
Test name
Test status
Simulation time 84596679 ps
CPU time 1.3 seconds
Started Jul 16 07:15:16 PM PDT 24
Finished Jul 16 07:16:12 PM PDT 24
Peak memory 219964 kb
Host smart-3565cd9e-1310-4020-b865-d2038293fc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348111706 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.1348111706
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.1291743570
Short name T487
Test name
Test status
Simulation time 28939820 ps
CPU time 1.32 seconds
Started Jul 16 07:15:11 PM PDT 24
Finished Jul 16 07:16:06 PM PDT 24
Peak memory 217432 kb
Host smart-62e6c021-4588-46b4-a3d8-f3b106a9ac61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291743570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.1291743570
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.1387235626
Short name T263
Test name
Test status
Simulation time 107979474 ps
CPU time 1.32 seconds
Started Jul 16 07:13:11 PM PDT 24
Finished Jul 16 07:13:39 PM PDT 24
Peak memory 216020 kb
Host smart-e17e7d31-fdb5-47dc-884a-ad7d6ba1ccac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387235626 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.1387235626
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.676442445
Short name T926
Test name
Test status
Simulation time 121080562 ps
CPU time 0.98 seconds
Started Jul 16 07:13:10 PM PDT 24
Finished Jul 16 07:13:38 PM PDT 24
Peak memory 215180 kb
Host smart-fdda2693-9bab-476a-a2c5-1e031a7444ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676442445 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.676442445
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.2513555491
Short name T895
Test name
Test status
Simulation time 32366199 ps
CPU time 0.81 seconds
Started Jul 16 07:13:10 PM PDT 24
Finished Jul 16 07:13:38 PM PDT 24
Peak memory 216632 kb
Host smart-0db1446f-60e9-482a-9042-4e4f7953f97c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513555491 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2513555491
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.2799399672
Short name T72
Test name
Test status
Simulation time 34686116 ps
CPU time 1.27 seconds
Started Jul 16 07:13:10 PM PDT 24
Finished Jul 16 07:13:39 PM PDT 24
Peak memory 217168 kb
Host smart-7f77beca-1db4-4708-9199-89f9b1446cb5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799399672 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.2799399672
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.2178948071
Short name T727
Test name
Test status
Simulation time 19615596 ps
CPU time 1.2 seconds
Started Jul 16 07:13:08 PM PDT 24
Finished Jul 16 07:13:38 PM PDT 24
Peak memory 224196 kb
Host smart-610f3d4b-3cb9-43f2-b6e4-7afa3b5542d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178948071 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.2178948071
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.3239342514
Short name T945
Test name
Test status
Simulation time 132296820 ps
CPU time 2.83 seconds
Started Jul 16 07:12:53 PM PDT 24
Finished Jul 16 07:13:37 PM PDT 24
Peak memory 219348 kb
Host smart-446d4c11-a5d5-49f3-be53-83dcdfc310df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239342514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3239342514
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3950857277
Short name T919
Test name
Test status
Simulation time 25161966 ps
CPU time 1.06 seconds
Started Jul 16 07:13:12 PM PDT 24
Finished Jul 16 07:13:38 PM PDT 24
Peak memory 224248 kb
Host smart-471a3620-9b1e-4486-a261-418b6bda0ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950857277 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3950857277
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.1004398888
Short name T721
Test name
Test status
Simulation time 70085142 ps
CPU time 0.9 seconds
Started Jul 16 07:13:02 PM PDT 24
Finished Jul 16 07:13:36 PM PDT 24
Peak memory 215532 kb
Host smart-4be57f24-b9fa-46b6-a632-7dfb2955cf95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004398888 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.1004398888
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.3907342374
Short name T785
Test name
Test status
Simulation time 467106531 ps
CPU time 4.73 seconds
Started Jul 16 07:12:55 PM PDT 24
Finished Jul 16 07:13:40 PM PDT 24
Peak memory 220388 kb
Host smart-80b6e544-5062-4b96-8933-7a035b7416b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907342374 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.3907342374
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.1252350690
Short name T322
Test name
Test status
Simulation time 383794908612 ps
CPU time 2296.94 seconds
Started Jul 16 07:13:12 PM PDT 24
Finished Jul 16 07:51:55 PM PDT 24
Peak memory 228428 kb
Host smart-2b20f381-b5a8-4e30-b0c9-9f5ad2ad4950
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252350690 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.1252350690
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.152035000
Short name T600
Test name
Test status
Simulation time 49666392 ps
CPU time 1.22 seconds
Started Jul 16 07:15:12 PM PDT 24
Finished Jul 16 07:16:06 PM PDT 24
Peak memory 220196 kb
Host smart-d073e03d-7ca1-4030-9865-942e36cb867a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152035000 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.152035000
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.3510053314
Short name T901
Test name
Test status
Simulation time 97462563 ps
CPU time 0.96 seconds
Started Jul 16 07:15:15 PM PDT 24
Finished Jul 16 07:16:11 PM PDT 24
Peak memory 217672 kb
Host smart-16032ff1-ea69-40c1-9140-b6101621a1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510053314 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3510053314
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.67519978
Short name T872
Test name
Test status
Simulation time 55254401 ps
CPU time 1.19 seconds
Started Jul 16 07:15:12 PM PDT 24
Finished Jul 16 07:16:07 PM PDT 24
Peak memory 218916 kb
Host smart-f2efaf93-14b4-49b0-90d9-6aa15e22b1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67519978 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.67519978
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.1684945246
Short name T415
Test name
Test status
Simulation time 60884344 ps
CPU time 1.43 seconds
Started Jul 16 07:15:14 PM PDT 24
Finished Jul 16 07:16:11 PM PDT 24
Peak memory 218940 kb
Host smart-79021f04-11cf-4635-9ce3-9a25635f6833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684945246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.1684945246
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.3666085983
Short name T69
Test name
Test status
Simulation time 42118517 ps
CPU time 1.14 seconds
Started Jul 16 07:15:12 PM PDT 24
Finished Jul 16 07:16:07 PM PDT 24
Peak memory 218108 kb
Host smart-71885a88-0889-41a0-b82e-2535406ff527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666085983 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.3666085983
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.3069110974
Short name T339
Test name
Test status
Simulation time 70537438 ps
CPU time 1.19 seconds
Started Jul 16 07:15:14 PM PDT 24
Finished Jul 16 07:16:11 PM PDT 24
Peak memory 219068 kb
Host smart-69aed6c7-c1e4-41fb-b011-666648e6f4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069110974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.3069110974
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.4076151107
Short name T810
Test name
Test status
Simulation time 77072542 ps
CPU time 1.07 seconds
Started Jul 16 07:15:17 PM PDT 24
Finished Jul 16 07:16:11 PM PDT 24
Peak memory 219856 kb
Host smart-88d00f9a-67b7-4caf-9338-e4faf42278bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076151107 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.4076151107
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.263079664
Short name T427
Test name
Test status
Simulation time 205625017 ps
CPU time 1.5 seconds
Started Jul 16 07:15:14 PM PDT 24
Finished Jul 16 07:16:12 PM PDT 24
Peak memory 219336 kb
Host smart-c9f02b13-e15a-4ebf-a3d5-32afa473d4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263079664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.263079664
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.2858145307
Short name T793
Test name
Test status
Simulation time 37505382 ps
CPU time 1.18 seconds
Started Jul 16 07:15:17 PM PDT 24
Finished Jul 16 07:16:12 PM PDT 24
Peak memory 219376 kb
Host smart-4a637f24-5a56-4c27-a802-ceaa2f14340c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858145307 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.2858145307
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.2357134280
Short name T304
Test name
Test status
Simulation time 80215413 ps
CPU time 1.76 seconds
Started Jul 16 07:15:15 PM PDT 24
Finished Jul 16 07:16:12 PM PDT 24
Peak memory 219052 kb
Host smart-5a00fd1f-0193-42ae-bfda-ce334b2055f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357134280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2357134280
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.1493447248
Short name T903
Test name
Test status
Simulation time 90703108 ps
CPU time 1.26 seconds
Started Jul 16 07:15:31 PM PDT 24
Finished Jul 16 07:16:26 PM PDT 24
Peak memory 220116 kb
Host smart-74c16b3a-f6f8-4e52-a521-863e1c89b4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493447248 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.1493447248
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.282570197
Short name T420
Test name
Test status
Simulation time 779207773 ps
CPU time 4.63 seconds
Started Jul 16 07:15:14 PM PDT 24
Finished Jul 16 07:16:15 PM PDT 24
Peak memory 220632 kb
Host smart-3b7e75bc-e42d-4984-b750-13460cbe5952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282570197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.282570197
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.2191995924
Short name T892
Test name
Test status
Simulation time 84206453 ps
CPU time 1.22 seconds
Started Jul 16 07:15:31 PM PDT 24
Finished Jul 16 07:16:26 PM PDT 24
Peak memory 220876 kb
Host smart-40daaaa3-a03e-4d80-ab34-b97c3d9882b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191995924 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.2191995924
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.2737392421
Short name T346
Test name
Test status
Simulation time 35859199 ps
CPU time 1.31 seconds
Started Jul 16 07:15:28 PM PDT 24
Finished Jul 16 07:16:24 PM PDT 24
Peak memory 217624 kb
Host smart-ff80bd40-715a-4afa-b0af-3367afd853b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737392421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2737392421
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.1926633498
Short name T776
Test name
Test status
Simulation time 26949598 ps
CPU time 1.22 seconds
Started Jul 16 07:15:29 PM PDT 24
Finished Jul 16 07:16:26 PM PDT 24
Peak memory 221244 kb
Host smart-483ba445-fdef-427c-85f6-d1716c4a7aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926633498 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.1926633498
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.3841964080
Short name T638
Test name
Test status
Simulation time 52276168 ps
CPU time 1.24 seconds
Started Jul 16 07:15:32 PM PDT 24
Finished Jul 16 07:16:27 PM PDT 24
Peak memory 217640 kb
Host smart-2653109d-8e67-4993-a00f-68de41b48523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841964080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3841964080
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.3444669811
Short name T643
Test name
Test status
Simulation time 37229215 ps
CPU time 1.12 seconds
Started Jul 16 07:15:32 PM PDT 24
Finished Jul 16 07:16:26 PM PDT 24
Peak memory 218920 kb
Host smart-673fb4e3-a76c-49d9-ad13-8159c78a4f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444669811 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.3444669811
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.2280963283
Short name T947
Test name
Test status
Simulation time 50508368 ps
CPU time 1.67 seconds
Started Jul 16 07:15:33 PM PDT 24
Finished Jul 16 07:16:27 PM PDT 24
Peak memory 218964 kb
Host smart-0b17ae7c-9cf7-4139-a1e2-cbacef17d0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280963283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.2280963283
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.3793402646
Short name T533
Test name
Test status
Simulation time 166923454 ps
CPU time 1.13 seconds
Started Jul 16 07:15:33 PM PDT 24
Finished Jul 16 07:16:27 PM PDT 24
Peak memory 219524 kb
Host smart-8e750ff0-9fff-4260-bead-cf7091b3b15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793402646 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.3793402646
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.2648019142
Short name T519
Test name
Test status
Simulation time 40848381 ps
CPU time 1.57 seconds
Started Jul 16 07:15:30 PM PDT 24
Finished Jul 16 07:16:26 PM PDT 24
Peak memory 218868 kb
Host smart-b6999b26-00a1-488b-bab2-c8d16186d37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648019142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.2648019142
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.1322055470
Short name T558
Test name
Test status
Simulation time 24232504 ps
CPU time 1.19 seconds
Started Jul 16 07:11:49 PM PDT 24
Finished Jul 16 07:13:13 PM PDT 24
Peak memory 220048 kb
Host smart-e320941a-cc85-45f3-ab33-4c952247df72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322055470 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.1322055470
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.493336373
Short name T429
Test name
Test status
Simulation time 56571595 ps
CPU time 0.98 seconds
Started Jul 16 07:11:52 PM PDT 24
Finished Jul 16 07:13:18 PM PDT 24
Peak memory 207060 kb
Host smart-1326adec-6993-4dc8-92b2-b77d0bfd04ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493336373 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.493336373
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.3964780478
Short name T982
Test name
Test status
Simulation time 10904982 ps
CPU time 0.84 seconds
Started Jul 16 07:11:53 PM PDT 24
Finished Jul 16 07:13:17 PM PDT 24
Peak memory 216568 kb
Host smart-96dee8f5-dbe8-4c1b-8101-e9e9392deeff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964780478 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.3964780478
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.3730200461
Short name T116
Test name
Test status
Simulation time 118271183 ps
CPU time 1.01 seconds
Started Jul 16 07:11:52 PM PDT 24
Finished Jul 16 07:13:18 PM PDT 24
Peak memory 217044 kb
Host smart-d6caddc9-f685-464a-816e-222922ebab7e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730200461 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.3730200461
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.2640595114
Short name T428
Test name
Test status
Simulation time 44627689 ps
CPU time 0.94 seconds
Started Jul 16 07:11:40 PM PDT 24
Finished Jul 16 07:13:10 PM PDT 24
Peak memory 218836 kb
Host smart-89104a98-8e64-4bd4-a677-fddc0fd88cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640595114 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.2640595114
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.4071459488
Short name T596
Test name
Test status
Simulation time 41539012 ps
CPU time 1.45 seconds
Started Jul 16 07:11:46 PM PDT 24
Finished Jul 16 07:13:13 PM PDT 24
Peak memory 220324 kb
Host smart-fbd5ad97-774c-4841-99ff-e1cc843d2545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071459488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.4071459488
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.1296097285
Short name T706
Test name
Test status
Simulation time 29133896 ps
CPU time 0.96 seconds
Started Jul 16 07:11:42 PM PDT 24
Finished Jul 16 07:13:12 PM PDT 24
Peak memory 215692 kb
Host smart-972ac88d-b8c9-49dd-90ae-554f5b47346c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296097285 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.1296097285
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.2632068667
Short name T553
Test name
Test status
Simulation time 29096801 ps
CPU time 0.95 seconds
Started Jul 16 07:11:47 PM PDT 24
Finished Jul 16 07:13:18 PM PDT 24
Peak memory 207400 kb
Host smart-74eead82-300c-4f97-a064-11a26e122670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632068667 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2632068667
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_smoke.2794807929
Short name T607
Test name
Test status
Simulation time 23531693 ps
CPU time 0.87 seconds
Started Jul 16 07:11:43 PM PDT 24
Finished Jul 16 07:13:12 PM PDT 24
Peak memory 215620 kb
Host smart-c730735a-136f-4f53-a278-c31eba61c8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794807929 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.2794807929
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.3277255091
Short name T517
Test name
Test status
Simulation time 762676051 ps
CPU time 4.31 seconds
Started Jul 16 07:11:40 PM PDT 24
Finished Jul 16 07:13:12 PM PDT 24
Peak memory 217408 kb
Host smart-4ab5f974-4642-475f-bcda-ef596d827a8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277255091 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.3277255091
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.460736521
Short name T712
Test name
Test status
Simulation time 85572070122 ps
CPU time 1265.66 seconds
Started Jul 16 07:11:42 PM PDT 24
Finished Jul 16 07:34:26 PM PDT 24
Peak memory 225488 kb
Host smart-c8a771d9-87d6-4b75-b63d-be9310e34fc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460736521 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.460736521
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.3648259510
Short name T995
Test name
Test status
Simulation time 38374298 ps
CPU time 1.12 seconds
Started Jul 16 07:13:10 PM PDT 24
Finished Jul 16 07:13:38 PM PDT 24
Peak memory 219080 kb
Host smart-26096312-3315-46d5-8a9a-e21b9ba73456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648259510 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.3648259510
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.942605468
Short name T662
Test name
Test status
Simulation time 16984470 ps
CPU time 0.93 seconds
Started Jul 16 07:13:12 PM PDT 24
Finished Jul 16 07:13:38 PM PDT 24
Peak memory 206980 kb
Host smart-c7bf10fe-1366-4dfa-b9b6-8ce5de4175f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942605468 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.942605468
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.1067764010
Short name T447
Test name
Test status
Simulation time 17015982 ps
CPU time 0.85 seconds
Started Jul 16 07:13:11 PM PDT 24
Finished Jul 16 07:13:38 PM PDT 24
Peak memory 216560 kb
Host smart-e9284f31-6c1f-43ae-9c43-00d5b646dba5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067764010 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1067764010
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_err.4106185028
Short name T123
Test name
Test status
Simulation time 39428107 ps
CPU time 1.09 seconds
Started Jul 16 07:13:10 PM PDT 24
Finished Jul 16 07:13:38 PM PDT 24
Peak memory 229944 kb
Host smart-830f7cda-e76d-405b-88a2-9b88bfa56bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106185028 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.4106185028
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.787832083
Short name T337
Test name
Test status
Simulation time 81070485 ps
CPU time 1.95 seconds
Started Jul 16 07:13:09 PM PDT 24
Finished Jul 16 07:13:39 PM PDT 24
Peak memory 219108 kb
Host smart-32736ca2-1dcb-4a37-bb0c-57b72310444d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787832083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.787832083
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.3989612144
Short name T81
Test name
Test status
Simulation time 27601937 ps
CPU time 0.96 seconds
Started Jul 16 07:13:11 PM PDT 24
Finished Jul 16 07:13:38 PM PDT 24
Peak memory 216040 kb
Host smart-5c4f4aa6-7646-4dbd-8feb-a51cf286ae50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989612144 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.3989612144
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.833605561
Short name T390
Test name
Test status
Simulation time 25454007 ps
CPU time 1.02 seconds
Started Jul 16 07:13:41 PM PDT 24
Finished Jul 16 07:13:45 PM PDT 24
Peak memory 215552 kb
Host smart-9b08c7fc-ee8c-453a-aabc-f060a248b326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833605561 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.833605561
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.3207029392
Short name T232
Test name
Test status
Simulation time 260691114 ps
CPU time 2.96 seconds
Started Jul 16 07:13:10 PM PDT 24
Finished Jul 16 07:13:40 PM PDT 24
Peak memory 215492 kb
Host smart-cb4bf6bb-7d6d-4c0b-b779-77b90763b37d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207029392 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3207029392
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.3051274119
Short name T790
Test name
Test status
Simulation time 25037954310 ps
CPU time 583.03 seconds
Started Jul 16 07:13:11 PM PDT 24
Finished Jul 16 07:23:20 PM PDT 24
Peak memory 218400 kb
Host smart-6a2652db-cfda-47ea-83db-d5855d0f8dbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051274119 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.3051274119
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.1258458681
Short name T618
Test name
Test status
Simulation time 94121601 ps
CPU time 1.04 seconds
Started Jul 16 07:15:34 PM PDT 24
Finished Jul 16 07:16:30 PM PDT 24
Peak memory 217500 kb
Host smart-72ae63d1-dd1a-4a12-92f0-39e80bc522b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258458681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.1258458681
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.1301119789
Short name T271
Test name
Test status
Simulation time 58024122 ps
CPU time 2.03 seconds
Started Jul 16 07:15:34 PM PDT 24
Finished Jul 16 07:16:31 PM PDT 24
Peak memory 219160 kb
Host smart-536e1e71-bd66-40a4-9b03-c6bfde323517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301119789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.1301119789
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.596142090
Short name T300
Test name
Test status
Simulation time 72076044 ps
CPU time 1.09 seconds
Started Jul 16 07:15:29 PM PDT 24
Finished Jul 16 07:16:24 PM PDT 24
Peak memory 217692 kb
Host smart-ea2c687e-7650-4a6a-9908-7c388f13ed4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596142090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.596142090
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.187207913
Short name T805
Test name
Test status
Simulation time 40943736 ps
CPU time 1.13 seconds
Started Jul 16 07:15:41 PM PDT 24
Finished Jul 16 07:16:40 PM PDT 24
Peak memory 217592 kb
Host smart-6e4f5079-1d90-4fd2-8a26-911bb14f5c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187207913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.187207913
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.3774394023
Short name T624
Test name
Test status
Simulation time 58883813 ps
CPU time 1.46 seconds
Started Jul 16 07:15:38 PM PDT 24
Finished Jul 16 07:16:37 PM PDT 24
Peak memory 219044 kb
Host smart-9fc5fd31-a82f-4421-9453-91fa348cb8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774394023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3774394023
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.880119967
Short name T940
Test name
Test status
Simulation time 36754691 ps
CPU time 1.37 seconds
Started Jul 16 07:15:33 PM PDT 24
Finished Jul 16 07:16:27 PM PDT 24
Peak memory 217672 kb
Host smart-c808da34-6d9b-4fad-b109-761f704d7446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880119967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.880119967
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.239159030
Short name T319
Test name
Test status
Simulation time 94839302 ps
CPU time 1.35 seconds
Started Jul 16 07:15:31 PM PDT 24
Finished Jul 16 07:16:26 PM PDT 24
Peak memory 219004 kb
Host smart-74a036b5-ecb4-4ddf-a844-acd5009ac563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239159030 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.239159030
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.387229899
Short name T595
Test name
Test status
Simulation time 83511518 ps
CPU time 1.32 seconds
Started Jul 16 07:15:28 PM PDT 24
Finished Jul 16 07:16:24 PM PDT 24
Peak memory 219216 kb
Host smart-b2695303-d429-419e-86fa-d1dcb3f5fc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387229899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.387229899
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.3191596315
Short name T326
Test name
Test status
Simulation time 701754200 ps
CPU time 7.07 seconds
Started Jul 16 07:15:32 PM PDT 24
Finished Jul 16 07:16:32 PM PDT 24
Peak memory 217796 kb
Host smart-fde15085-0905-4102-9766-ab3263468866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191596315 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.3191596315
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.857037404
Short name T496
Test name
Test status
Simulation time 283121732 ps
CPU time 1.25 seconds
Started Jul 16 07:15:38 PM PDT 24
Finished Jul 16 07:16:36 PM PDT 24
Peak memory 217724 kb
Host smart-04b1c305-ce77-4dfa-8634-facfb7c30100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857037404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.857037404
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.857564607
Short name T210
Test name
Test status
Simulation time 41581601 ps
CPU time 1.14 seconds
Started Jul 16 07:13:23 PM PDT 24
Finished Jul 16 07:13:41 PM PDT 24
Peak memory 219756 kb
Host smart-254a99d6-9938-4a13-be30-b7e584247855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857564607 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.857564607
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.1226702542
Short name T914
Test name
Test status
Simulation time 31928305 ps
CPU time 0.97 seconds
Started Jul 16 07:13:24 PM PDT 24
Finished Jul 16 07:13:41 PM PDT 24
Peak memory 215412 kb
Host smart-b50619a1-d290-4621-af79-bb0dee9bb387
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226702542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.1226702542
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.2848159660
Short name T651
Test name
Test status
Simulation time 80209363 ps
CPU time 1.02 seconds
Started Jul 16 07:13:24 PM PDT 24
Finished Jul 16 07:13:41 PM PDT 24
Peak memory 217200 kb
Host smart-a37e99d5-8883-4fbf-85e4-9e65609ecccf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848159660 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.2848159660
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.361917610
Short name T206
Test name
Test status
Simulation time 30135341 ps
CPU time 1.34 seconds
Started Jul 16 07:13:24 PM PDT 24
Finished Jul 16 07:13:41 PM PDT 24
Peak memory 220200 kb
Host smart-041a9970-a31e-4243-8c4a-5270344dd251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361917610 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.361917610
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.711189711
Short name T578
Test name
Test status
Simulation time 56735269 ps
CPU time 1.46 seconds
Started Jul 16 07:13:10 PM PDT 24
Finished Jul 16 07:13:39 PM PDT 24
Peak memory 218876 kb
Host smart-21499a9c-258b-454a-9a1b-edc75d55cb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711189711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.711189711
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.1063915870
Short name T518
Test name
Test status
Simulation time 132413135 ps
CPU time 1 seconds
Started Jul 16 07:13:23 PM PDT 24
Finished Jul 16 07:13:41 PM PDT 24
Peak memory 224176 kb
Host smart-f5959690-e74f-405f-9235-ba8296de4f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063915870 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.1063915870
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.2729076862
Short name T674
Test name
Test status
Simulation time 29509949 ps
CPU time 0.95 seconds
Started Jul 16 07:13:09 PM PDT 24
Finished Jul 16 07:13:38 PM PDT 24
Peak memory 215560 kb
Host smart-98f9890f-2b78-4dd5-ae0e-68de73b71ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729076862 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.2729076862
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.1558827534
Short name T312
Test name
Test status
Simulation time 296502379 ps
CPU time 2.2 seconds
Started Jul 16 07:13:25 PM PDT 24
Finished Jul 16 07:13:42 PM PDT 24
Peak memory 217500 kb
Host smart-ce707d9f-cdb8-4044-b916-8269392911f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558827534 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.1558827534
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.674217500
Short name T582
Test name
Test status
Simulation time 311710705380 ps
CPU time 2000.92 seconds
Started Jul 16 07:13:24 PM PDT 24
Finished Jul 16 07:47:01 PM PDT 24
Peak memory 226544 kb
Host smart-49010c5a-78ec-4157-b7fd-47760f5f48e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674217500 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.674217500
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.690855112
Short name T847
Test name
Test status
Simulation time 119984940 ps
CPU time 1.45 seconds
Started Jul 16 07:15:32 PM PDT 24
Finished Jul 16 07:16:27 PM PDT 24
Peak memory 218956 kb
Host smart-c3ea8b8f-2fbb-4cd3-a9ec-c776aa035274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690855112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.690855112
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.4147276025
Short name T599
Test name
Test status
Simulation time 179131544 ps
CPU time 1.13 seconds
Started Jul 16 07:15:34 PM PDT 24
Finished Jul 16 07:16:30 PM PDT 24
Peak memory 220088 kb
Host smart-df0f82c2-ab33-4857-80d3-def6d37a3190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147276025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.4147276025
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.906362977
Short name T451
Test name
Test status
Simulation time 41252821 ps
CPU time 1.38 seconds
Started Jul 16 07:15:34 PM PDT 24
Finished Jul 16 07:16:30 PM PDT 24
Peak memory 218600 kb
Host smart-82e2e6e6-45cb-4888-852f-78759872c694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906362977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.906362977
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.4038377085
Short name T309
Test name
Test status
Simulation time 85505053 ps
CPU time 3.04 seconds
Started Jul 16 07:15:33 PM PDT 24
Finished Jul 16 07:16:28 PM PDT 24
Peak memory 218788 kb
Host smart-a980bbad-02e9-47e2-8019-fdb026e0af66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038377085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.4038377085
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.3429062916
Short name T520
Test name
Test status
Simulation time 68157469 ps
CPU time 1.19 seconds
Started Jul 16 07:15:34 PM PDT 24
Finished Jul 16 07:16:30 PM PDT 24
Peak memory 220332 kb
Host smart-1c6aa9b3-fbfe-4eee-9467-3fc3a5250059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429062916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.3429062916
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.3888247343
Short name T870
Test name
Test status
Simulation time 52379311 ps
CPU time 1.41 seconds
Started Jul 16 07:15:26 PM PDT 24
Finished Jul 16 07:16:23 PM PDT 24
Peak memory 218868 kb
Host smart-a2a64e71-dc70-48c5-977a-86796e942688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888247343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.3888247343
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.2508780125
Short name T715
Test name
Test status
Simulation time 71205440 ps
CPU time 1.07 seconds
Started Jul 16 07:15:30 PM PDT 24
Finished Jul 16 07:16:26 PM PDT 24
Peak memory 217740 kb
Host smart-e5fcb02f-19d4-48e7-91df-824298cfca82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508780125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2508780125
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.1018316668
Short name T70
Test name
Test status
Simulation time 217163272 ps
CPU time 0.96 seconds
Started Jul 16 07:15:36 PM PDT 24
Finished Jul 16 07:16:31 PM PDT 24
Peak memory 217484 kb
Host smart-5f8eff66-4618-44f4-88b7-01d4aa7d6fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018316668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.1018316668
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.1223672661
Short name T401
Test name
Test status
Simulation time 79954862 ps
CPU time 1.07 seconds
Started Jul 16 07:15:31 PM PDT 24
Finished Jul 16 07:16:26 PM PDT 24
Peak memory 217752 kb
Host smart-7c028b6d-91b5-43ed-9770-d498caecb059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223672661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1223672661
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.4195824277
Short name T744
Test name
Test status
Simulation time 74294475 ps
CPU time 1.19 seconds
Started Jul 16 07:14:56 PM PDT 24
Finished Jul 16 07:15:41 PM PDT 24
Peak memory 222196 kb
Host smart-6551f3bf-5ee5-4d25-805d-cf1fbe5ba3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195824277 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.4195824277
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.2500416642
Short name T482
Test name
Test status
Simulation time 14972979 ps
CPU time 0.93 seconds
Started Jul 16 07:13:23 PM PDT 24
Finished Jul 16 07:13:41 PM PDT 24
Peak memory 206956 kb
Host smart-e948e41d-8f39-41b8-8894-f43817bb7382
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500416642 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.2500416642
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.2033958104
Short name T483
Test name
Test status
Simulation time 27631300 ps
CPU time 1.13 seconds
Started Jul 16 07:13:23 PM PDT 24
Finished Jul 16 07:13:41 PM PDT 24
Peak memory 218948 kb
Host smart-96bed84b-6501-4657-8810-506d0af0eeca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033958104 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.2033958104
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.2861053992
Short name T129
Test name
Test status
Simulation time 53211209 ps
CPU time 0.95 seconds
Started Jul 16 07:13:22 PM PDT 24
Finished Jul 16 07:13:41 PM PDT 24
Peak memory 219868 kb
Host smart-46140276-09e3-4725-9b60-60231df0022c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861053992 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.2861053992
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.1026043153
Short name T369
Test name
Test status
Simulation time 37539354 ps
CPU time 1.63 seconds
Started Jul 16 07:13:23 PM PDT 24
Finished Jul 16 07:13:41 PM PDT 24
Peak memory 218900 kb
Host smart-038a699d-3ed0-48f2-b332-6e228e84b71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026043153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.1026043153
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.3417383912
Short name T971
Test name
Test status
Simulation time 38587027 ps
CPU time 0.86 seconds
Started Jul 16 07:13:24 PM PDT 24
Finished Jul 16 07:13:41 PM PDT 24
Peak memory 216052 kb
Host smart-8cff2dbf-8efb-447e-a8c8-e5595f8dea7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417383912 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.3417383912
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.3640659601
Short name T635
Test name
Test status
Simulation time 20088746 ps
CPU time 1.05 seconds
Started Jul 16 07:13:25 PM PDT 24
Finished Jul 16 07:13:41 PM PDT 24
Peak memory 215580 kb
Host smart-f6c06e59-59d0-496d-8f23-80d6b5c6932d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640659601 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.3640659601
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2636961613
Short name T86
Test name
Test status
Simulation time 43197356 ps
CPU time 1.15 seconds
Started Jul 16 07:13:24 PM PDT 24
Finished Jul 16 07:13:41 PM PDT 24
Peak memory 215540 kb
Host smart-444a4834-7acf-42e8-8846-883a6d5552d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636961613 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2636961613
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.1300771580
Short name T502
Test name
Test status
Simulation time 53741648736 ps
CPU time 1191.76 seconds
Started Jul 16 07:13:23 PM PDT 24
Finished Jul 16 07:33:32 PM PDT 24
Peak memory 220720 kb
Host smart-a93180b4-3cf0-40dc-860a-ee459b3ef6a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300771580 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.1300771580
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.1642288655
Short name T542
Test name
Test status
Simulation time 104071827 ps
CPU time 1.29 seconds
Started Jul 16 07:15:38 PM PDT 24
Finished Jul 16 07:16:36 PM PDT 24
Peak memory 219260 kb
Host smart-3e377c25-7c70-4b34-86d3-6d05566bfdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642288655 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.1642288655
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.2087914194
Short name T739
Test name
Test status
Simulation time 79632978 ps
CPU time 1.23 seconds
Started Jul 16 07:15:31 PM PDT 24
Finished Jul 16 07:16:26 PM PDT 24
Peak memory 220164 kb
Host smart-af4fe0d6-a13a-4eb0-8a4f-e199b468f12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087914194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.2087914194
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.2347146651
Short name T868
Test name
Test status
Simulation time 39013141 ps
CPU time 1.58 seconds
Started Jul 16 07:15:34 PM PDT 24
Finished Jul 16 07:16:30 PM PDT 24
Peak memory 220536 kb
Host smart-32d13abb-0a42-455f-ad30-180ef92dea15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347146651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.2347146651
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.4260821236
Short name T3
Test name
Test status
Simulation time 50388825 ps
CPU time 1.55 seconds
Started Jul 16 07:15:28 PM PDT 24
Finished Jul 16 07:16:24 PM PDT 24
Peak memory 220348 kb
Host smart-84d131f8-2147-43ce-aca9-8bdbe93f4202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260821236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.4260821236
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.3675607300
Short name T774
Test name
Test status
Simulation time 50462426 ps
CPU time 1.45 seconds
Started Jul 16 07:15:41 PM PDT 24
Finished Jul 16 07:16:40 PM PDT 24
Peak memory 217720 kb
Host smart-d5c232a8-df8a-4487-baec-38e695542ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675607300 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.3675607300
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.1050841392
Short name T505
Test name
Test status
Simulation time 92579061 ps
CPU time 1.99 seconds
Started Jul 16 07:15:38 PM PDT 24
Finished Jul 16 07:16:36 PM PDT 24
Peak memory 220532 kb
Host smart-f02c5ec1-09b8-46fb-8456-981f4655cc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050841392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.1050841392
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.3821810536
Short name T591
Test name
Test status
Simulation time 63361419 ps
CPU time 1.02 seconds
Started Jul 16 07:15:32 PM PDT 24
Finished Jul 16 07:16:26 PM PDT 24
Peak memory 215644 kb
Host smart-bd5df602-bc9b-4714-8539-4f3c01768fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821810536 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3821810536
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.3151317241
Short name T850
Test name
Test status
Simulation time 38155079 ps
CPU time 1.42 seconds
Started Jul 16 07:15:41 PM PDT 24
Finished Jul 16 07:16:39 PM PDT 24
Peak memory 217612 kb
Host smart-ba61f6b2-5eea-47cf-8c24-1e13803b7c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151317241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3151317241
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.1581895604
Short name T604
Test name
Test status
Simulation time 52275937 ps
CPU time 0.98 seconds
Started Jul 16 07:15:31 PM PDT 24
Finished Jul 16 07:16:26 PM PDT 24
Peak memory 217528 kb
Host smart-0110ff02-1774-48ad-8619-ee5595e75d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581895604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.1581895604
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.630995434
Short name T610
Test name
Test status
Simulation time 106167288 ps
CPU time 1.34 seconds
Started Jul 16 07:15:28 PM PDT 24
Finished Jul 16 07:16:23 PM PDT 24
Peak memory 219592 kb
Host smart-bc101395-eb76-4f75-a0e9-d3f7ff491863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630995434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.630995434
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.781794862
Short name T992
Test name
Test status
Simulation time 41399051 ps
CPU time 1.15 seconds
Started Jul 16 07:13:24 PM PDT 24
Finished Jul 16 07:13:41 PM PDT 24
Peak memory 218868 kb
Host smart-f5680aa7-7ee1-4d01-a3c9-0b44936f4b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781794862 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.781794862
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.2014229053
Short name T838
Test name
Test status
Simulation time 31399242 ps
CPU time 1.01 seconds
Started Jul 16 07:13:25 PM PDT 24
Finished Jul 16 07:13:41 PM PDT 24
Peak memory 206984 kb
Host smart-8f513da9-4d8c-43c0-a10b-6475841d8354
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014229053 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.2014229053
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.2807660038
Short name T665
Test name
Test status
Simulation time 12519342 ps
CPU time 0.91 seconds
Started Jul 16 07:13:26 PM PDT 24
Finished Jul 16 07:13:41 PM PDT 24
Peak memory 216700 kb
Host smart-1c160e2c-7b91-476c-84cd-2ad42470bf07
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807660038 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2807660038
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.311389033
Short name T818
Test name
Test status
Simulation time 35326059 ps
CPU time 1.29 seconds
Started Jul 16 07:13:23 PM PDT 24
Finished Jul 16 07:13:41 PM PDT 24
Peak memory 217156 kb
Host smart-2bf2ce56-cd2a-49e3-bec6-4077d32e3a7a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311389033 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_di
sable_auto_req_mode.311389033
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.1911354643
Short name T968
Test name
Test status
Simulation time 51288263 ps
CPU time 1.11 seconds
Started Jul 16 07:13:22 PM PDT 24
Finished Jul 16 07:13:41 PM PDT 24
Peak memory 229980 kb
Host smart-937a68fb-2fe2-4256-86cb-0185304b06cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911354643 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1911354643
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.3642029664
Short name T669
Test name
Test status
Simulation time 133064892 ps
CPU time 1.97 seconds
Started Jul 16 07:13:26 PM PDT 24
Finished Jul 16 07:13:42 PM PDT 24
Peak memory 219232 kb
Host smart-086205e8-134c-4d51-abb2-57e8a278f3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642029664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3642029664
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.421955298
Short name T829
Test name
Test status
Simulation time 41804167 ps
CPU time 0.89 seconds
Started Jul 16 07:13:23 PM PDT 24
Finished Jul 16 07:13:41 PM PDT 24
Peak memory 215716 kb
Host smart-69b00c23-577f-4170-81e0-4732850dfd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421955298 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.421955298
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.1411876935
Short name T726
Test name
Test status
Simulation time 24451293 ps
CPU time 0.93 seconds
Started Jul 16 07:13:26 PM PDT 24
Finished Jul 16 07:13:41 PM PDT 24
Peak memory 215536 kb
Host smart-da4abbdf-c084-4756-9268-711df04b9432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411876935 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.1411876935
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.3558372597
Short name T230
Test name
Test status
Simulation time 57247523 ps
CPU time 1.62 seconds
Started Jul 16 07:13:25 PM PDT 24
Finished Jul 16 07:13:42 PM PDT 24
Peak memory 217548 kb
Host smart-3be4d274-2ed7-4ca0-9951-efff2e41c5b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558372597 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3558372597
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/231.edn_genbits.470211944
Short name T348
Test name
Test status
Simulation time 201420711 ps
CPU time 2.93 seconds
Started Jul 16 07:15:33 PM PDT 24
Finished Jul 16 07:16:29 PM PDT 24
Peak memory 217680 kb
Host smart-b482301c-410e-4856-bb42-251d0d14d210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470211944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.470211944
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.1019738802
Short name T477
Test name
Test status
Simulation time 45452277 ps
CPU time 1.34 seconds
Started Jul 16 07:15:41 PM PDT 24
Finished Jul 16 07:16:39 PM PDT 24
Peak memory 218844 kb
Host smart-107a005c-0c95-4521-b254-993e0a34464e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019738802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.1019738802
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.777826009
Short name T550
Test name
Test status
Simulation time 42448812 ps
CPU time 1.33 seconds
Started Jul 16 07:15:30 PM PDT 24
Finished Jul 16 07:16:26 PM PDT 24
Peak memory 219188 kb
Host smart-b7d86973-dc98-480d-8c2c-e7987c7127cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777826009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.777826009
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.424638946
Short name T490
Test name
Test status
Simulation time 77937796 ps
CPU time 1.07 seconds
Started Jul 16 07:15:32 PM PDT 24
Finished Jul 16 07:16:26 PM PDT 24
Peak memory 215544 kb
Host smart-1d4ed7ff-1242-456c-8d01-d0aa2bac86f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424638946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.424638946
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.1007717061
Short name T65
Test name
Test status
Simulation time 26877325 ps
CPU time 1.2 seconds
Started Jul 16 07:15:37 PM PDT 24
Finished Jul 16 07:16:35 PM PDT 24
Peak memory 217720 kb
Host smart-eb165bb0-66e1-4c54-b010-762ac6e459e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007717061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.1007717061
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.2682479733
Short name T67
Test name
Test status
Simulation time 75088099 ps
CPU time 1.34 seconds
Started Jul 16 07:15:32 PM PDT 24
Finished Jul 16 07:16:27 PM PDT 24
Peak memory 218816 kb
Host smart-bbe6a81e-c6cd-4458-bd87-a39efb929f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682479733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.2682479733
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.968498076
Short name T993
Test name
Test status
Simulation time 194578598 ps
CPU time 2.3 seconds
Started Jul 16 07:15:34 PM PDT 24
Finished Jul 16 07:16:31 PM PDT 24
Peak memory 219136 kb
Host smart-092c9788-0ce0-46a6-892b-328073c5cb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968498076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.968498076
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.3503714378
Short name T395
Test name
Test status
Simulation time 43048621 ps
CPU time 1.07 seconds
Started Jul 16 07:15:36 PM PDT 24
Finished Jul 16 07:16:31 PM PDT 24
Peak memory 217648 kb
Host smart-4af89115-d16f-46b6-8e30-21f4870046d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503714378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.3503714378
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.1795607948
Short name T535
Test name
Test status
Simulation time 59919829 ps
CPU time 1.3 seconds
Started Jul 16 07:15:47 PM PDT 24
Finished Jul 16 07:16:44 PM PDT 24
Peak memory 219652 kb
Host smart-f264348b-56a9-4b4e-be55-e132b54728fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795607948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.1795607948
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.3482930327
Short name T794
Test name
Test status
Simulation time 89849852 ps
CPU time 1.18 seconds
Started Jul 16 07:13:40 PM PDT 24
Finished Jul 16 07:13:45 PM PDT 24
Peak memory 220988 kb
Host smart-a25df35b-0351-476c-86b2-d659dc0ab1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482930327 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.3482930327
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.285410759
Short name T559
Test name
Test status
Simulation time 27117706 ps
CPU time 0.93 seconds
Started Jul 16 07:13:40 PM PDT 24
Finished Jul 16 07:13:44 PM PDT 24
Peak memory 215116 kb
Host smart-d1a501e2-612e-41d1-88b8-c044f85fa5ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285410759 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.285410759
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.1032185107
Short name T171
Test name
Test status
Simulation time 51311262 ps
CPU time 0.88 seconds
Started Jul 16 07:13:38 PM PDT 24
Finished Jul 16 07:13:44 PM PDT 24
Peak memory 216500 kb
Host smart-314c70c8-e52a-4142-b235-4b0232e041d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032185107 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1032185107
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.2483192035
Short name T759
Test name
Test status
Simulation time 117623616 ps
CPU time 1.13 seconds
Started Jul 16 07:13:39 PM PDT 24
Finished Jul 16 07:13:44 PM PDT 24
Peak memory 220300 kb
Host smart-2ef453fd-a4d8-4a3e-81e5-b2d25c142007
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483192035 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.2483192035
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.740964029
Short name T118
Test name
Test status
Simulation time 38051438 ps
CPU time 1.26 seconds
Started Jul 16 07:13:38 PM PDT 24
Finished Jul 16 07:13:44 PM PDT 24
Peak memory 232460 kb
Host smart-386068bb-2081-420c-bb23-6bff4a485728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740964029 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.740964029
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.1907981749
Short name T299
Test name
Test status
Simulation time 92364833 ps
CPU time 2.56 seconds
Started Jul 16 07:13:40 PM PDT 24
Finished Jul 16 07:13:46 PM PDT 24
Peak memory 218984 kb
Host smart-38bc8269-d613-4afc-b905-6b8e2b9b62de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907981749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1907981749
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.4227907793
Short name T524
Test name
Test status
Simulation time 39238647 ps
CPU time 0.99 seconds
Started Jul 16 07:13:39 PM PDT 24
Finished Jul 16 07:13:44 PM PDT 24
Peak memory 224108 kb
Host smart-5c768b5a-7b9d-47fa-be2a-c417f1718d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227907793 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.4227907793
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.3702124338
Short name T368
Test name
Test status
Simulation time 111627184 ps
CPU time 0.91 seconds
Started Jul 16 07:13:24 PM PDT 24
Finished Jul 16 07:13:41 PM PDT 24
Peak memory 215376 kb
Host smart-033eeff4-65e7-45bb-80b0-1c6cdba4ac7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702124338 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.3702124338
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.2558114683
Short name T959
Test name
Test status
Simulation time 144562050 ps
CPU time 3.21 seconds
Started Jul 16 07:13:36 PM PDT 24
Finished Jul 16 07:13:46 PM PDT 24
Peak memory 217460 kb
Host smart-c4a8b78f-b60a-41b2-8677-4592476191f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558114683 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2558114683
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1380442750
Short name T217
Test name
Test status
Simulation time 175373329248 ps
CPU time 2152.28 seconds
Started Jul 16 07:13:41 PM PDT 24
Finished Jul 16 07:49:36 PM PDT 24
Peak memory 231040 kb
Host smart-1537bb83-27c0-4b32-ac8c-868a6463b532
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380442750 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1380442750
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.3184434929
Short name T516
Test name
Test status
Simulation time 51476113 ps
CPU time 1.37 seconds
Started Jul 16 07:15:29 PM PDT 24
Finished Jul 16 07:16:24 PM PDT 24
Peak memory 219116 kb
Host smart-61fecb0c-a030-4d10-b421-3c39d05e8ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184434929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.3184434929
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.959737885
Short name T317
Test name
Test status
Simulation time 95478695 ps
CPU time 1.24 seconds
Started Jul 16 07:15:30 PM PDT 24
Finished Jul 16 07:16:26 PM PDT 24
Peak memory 217768 kb
Host smart-6461588d-8589-4ef7-8dba-392d2d0e7cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959737885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.959737885
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.2185377955
Short name T1
Test name
Test status
Simulation time 50482980 ps
CPU time 1.82 seconds
Started Jul 16 07:15:35 PM PDT 24
Finished Jul 16 07:16:32 PM PDT 24
Peak memory 218660 kb
Host smart-fab0a717-0abf-4730-aaf4-b532a84e4c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185377955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.2185377955
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.2007147239
Short name T574
Test name
Test status
Simulation time 171551561 ps
CPU time 1.48 seconds
Started Jul 16 07:15:33 PM PDT 24
Finished Jul 16 07:16:28 PM PDT 24
Peak memory 217456 kb
Host smart-11abcc04-e94f-48eb-878f-da0cc521e847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007147239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.2007147239
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.2907821354
Short name T20
Test name
Test status
Simulation time 230331729 ps
CPU time 3.13 seconds
Started Jul 16 07:15:28 PM PDT 24
Finished Jul 16 07:16:26 PM PDT 24
Peak memory 220280 kb
Host smart-2ac7534f-4ddb-4127-9642-00376e7fc3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907821354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.2907821354
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.1265792822
Short name T771
Test name
Test status
Simulation time 44383768 ps
CPU time 1.73 seconds
Started Jul 16 07:15:34 PM PDT 24
Finished Jul 16 07:16:31 PM PDT 24
Peak memory 217612 kb
Host smart-ebf01e17-17de-47cd-a834-8bc97b6867db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265792822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.1265792822
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.4131624505
Short name T573
Test name
Test status
Simulation time 65538337 ps
CPU time 1.15 seconds
Started Jul 16 07:15:30 PM PDT 24
Finished Jul 16 07:16:26 PM PDT 24
Peak memory 217540 kb
Host smart-510cc5eb-4202-4f86-b165-fc101e5cd5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131624505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.4131624505
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.3514581269
Short name T330
Test name
Test status
Simulation time 287650910 ps
CPU time 4.02 seconds
Started Jul 16 07:15:40 PM PDT 24
Finished Jul 16 07:16:40 PM PDT 24
Peak memory 218904 kb
Host smart-6ec30dc5-601e-4ed7-be9a-acb0035004a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514581269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.3514581269
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.1045355808
Short name T855
Test name
Test status
Simulation time 74747533 ps
CPU time 1.15 seconds
Started Jul 16 07:15:27 PM PDT 24
Finished Jul 16 07:16:23 PM PDT 24
Peak memory 217704 kb
Host smart-34f347ec-6fb9-49d6-9d94-2e361eb78e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045355808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.1045355808
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.3349458236
Short name T303
Test name
Test status
Simulation time 24382606 ps
CPU time 1.13 seconds
Started Jul 16 07:15:37 PM PDT 24
Finished Jul 16 07:16:35 PM PDT 24
Peak memory 218732 kb
Host smart-528a5986-0a37-4c8e-86d4-71543e2166ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349458236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.3349458236
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.1076012699
Short name T442
Test name
Test status
Simulation time 30881123 ps
CPU time 1.25 seconds
Started Jul 16 07:13:40 PM PDT 24
Finished Jul 16 07:13:44 PM PDT 24
Peak memory 219744 kb
Host smart-0cc32006-b855-4aec-b94e-7033b7d5a5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076012699 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.1076012699
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.2185937058
Short name T444
Test name
Test status
Simulation time 19491942 ps
CPU time 1.09 seconds
Started Jul 16 07:13:40 PM PDT 24
Finished Jul 16 07:13:44 PM PDT 24
Peak memory 215296 kb
Host smart-40ed8f21-717e-4b16-b38f-c05a592e9093
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185937058 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2185937058
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.228404935
Short name T986
Test name
Test status
Simulation time 23435914 ps
CPU time 0.95 seconds
Started Jul 16 07:13:37 PM PDT 24
Finished Jul 16 07:13:43 PM PDT 24
Peak memory 216744 kb
Host smart-ca2068f3-314f-4997-b9dc-34a666b135fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228404935 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.228404935
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.603300890
Short name T936
Test name
Test status
Simulation time 37698811 ps
CPU time 1.35 seconds
Started Jul 16 07:13:36 PM PDT 24
Finished Jul 16 07:13:43 PM PDT 24
Peak memory 217164 kb
Host smart-da825694-a4fd-4207-88b4-50e9bd23f206
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603300890 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_di
sable_auto_req_mode.603300890
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.173653446
Short name T136
Test name
Test status
Simulation time 45410741 ps
CPU time 0.96 seconds
Started Jul 16 07:13:41 PM PDT 24
Finished Jul 16 07:13:45 PM PDT 24
Peak memory 218736 kb
Host smart-623c6986-79f8-44e8-9ff3-6fa8cc044298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173653446 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.173653446
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.1245191709
Short name T974
Test name
Test status
Simulation time 187735229 ps
CPU time 1.89 seconds
Started Jul 16 07:13:37 PM PDT 24
Finished Jul 16 07:13:44 PM PDT 24
Peak memory 219132 kb
Host smart-7bf2bf3a-763a-45ab-8879-f0b516efeb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245191709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1245191709
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.2920000468
Short name T29
Test name
Test status
Simulation time 26192759 ps
CPU time 0.99 seconds
Started Jul 16 07:13:41 PM PDT 24
Finished Jul 16 07:13:45 PM PDT 24
Peak memory 216080 kb
Host smart-fcb2359e-f5c3-40a4-ae6f-36c19f4cd5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920000468 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2920000468
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.3488658016
Short name T406
Test name
Test status
Simulation time 19700971 ps
CPU time 1.02 seconds
Started Jul 16 07:13:36 PM PDT 24
Finished Jul 16 07:13:43 PM PDT 24
Peak memory 215596 kb
Host smart-97a5a6ae-0ca7-4a05-a37c-ed55448196bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488658016 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.3488658016
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.3220759097
Short name T825
Test name
Test status
Simulation time 531953648 ps
CPU time 5.22 seconds
Started Jul 16 07:13:34 PM PDT 24
Finished Jul 16 07:13:47 PM PDT 24
Peak memory 215736 kb
Host smart-338a9eff-bae4-4fa3-a1c4-3741b2875f78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220759097 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.3220759097
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/250.edn_genbits.4236220119
Short name T541
Test name
Test status
Simulation time 91234357 ps
CPU time 1.13 seconds
Started Jul 16 07:15:37 PM PDT 24
Finished Jul 16 07:16:35 PM PDT 24
Peak memory 217608 kb
Host smart-49033677-bcc2-4e28-91a9-a241e7272300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236220119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.4236220119
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.4034262375
Short name T900
Test name
Test status
Simulation time 64743498 ps
CPU time 1.18 seconds
Started Jul 16 07:15:32 PM PDT 24
Finished Jul 16 07:16:27 PM PDT 24
Peak memory 218824 kb
Host smart-86de9ad8-7703-4934-a4ad-2170051d07ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034262375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.4034262375
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2475999394
Short name T13
Test name
Test status
Simulation time 40025495 ps
CPU time 1.41 seconds
Started Jul 16 07:15:49 PM PDT 24
Finished Jul 16 07:16:46 PM PDT 24
Peak memory 220236 kb
Host smart-320affba-56e8-430d-8d62-182dba0ba64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475999394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2475999394
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.909655293
Short name T777
Test name
Test status
Simulation time 105172658 ps
CPU time 3.06 seconds
Started Jul 16 07:15:41 PM PDT 24
Finished Jul 16 07:16:41 PM PDT 24
Peak memory 218956 kb
Host smart-28196446-7a66-4b4e-86b5-b5b42b42b713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909655293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.909655293
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.2154144518
Short name T731
Test name
Test status
Simulation time 45121142 ps
CPU time 1.23 seconds
Started Jul 16 07:15:38 PM PDT 24
Finished Jul 16 07:16:36 PM PDT 24
Peak memory 219116 kb
Host smart-93474ae3-78cb-428b-b7d8-cb494682c11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154144518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2154144518
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.883709155
Short name T383
Test name
Test status
Simulation time 34823668 ps
CPU time 1.01 seconds
Started Jul 16 07:15:28 PM PDT 24
Finished Jul 16 07:16:23 PM PDT 24
Peak memory 217512 kb
Host smart-1f252856-5a76-46b3-b546-51370a6cd286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883709155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.883709155
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.3094116259
Short name T311
Test name
Test status
Simulation time 39801570 ps
CPU time 1.16 seconds
Started Jul 16 07:15:31 PM PDT 24
Finished Jul 16 07:16:26 PM PDT 24
Peak memory 217764 kb
Host smart-78bf6c22-86ef-4439-8602-3097b5958558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094116259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.3094116259
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.3524053522
Short name T408
Test name
Test status
Simulation time 59051244 ps
CPU time 1.2 seconds
Started Jul 16 07:15:30 PM PDT 24
Finished Jul 16 07:16:26 PM PDT 24
Peak memory 218740 kb
Host smart-a8c2e2f9-901c-4eef-9789-fd5b50ad8741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524053522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.3524053522
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.3625376955
Short name T318
Test name
Test status
Simulation time 43471273 ps
CPU time 1.02 seconds
Started Jul 16 07:15:34 PM PDT 24
Finished Jul 16 07:16:30 PM PDT 24
Peak memory 217448 kb
Host smart-010c5c41-b2dc-448d-bfac-72a9af7b379a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625376955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.3625376955
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.1113400717
Short name T938
Test name
Test status
Simulation time 104681031 ps
CPU time 1.42 seconds
Started Jul 16 07:15:36 PM PDT 24
Finished Jul 16 07:16:32 PM PDT 24
Peak memory 219016 kb
Host smart-1fd0cccb-1d4c-458f-9e3d-ce7ed542db07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113400717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.1113400717
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert_test.685543091
Short name T405
Test name
Test status
Simulation time 14919502 ps
CPU time 0.9 seconds
Started Jul 16 07:13:41 PM PDT 24
Finished Jul 16 07:13:45 PM PDT 24
Peak memory 207104 kb
Host smart-5a18a646-98bc-407d-ae95-366f38928c8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685543091 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.685543091
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.22836712
Short name T956
Test name
Test status
Simulation time 10808405 ps
CPU time 0.89 seconds
Started Jul 16 07:13:38 PM PDT 24
Finished Jul 16 07:13:44 PM PDT 24
Peak memory 216528 kb
Host smart-bbf46074-4d4c-445d-abb1-0cab0411ea4e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22836712 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.22836712
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.3016394227
Short name T106
Test name
Test status
Simulation time 64981928 ps
CPU time 1.11 seconds
Started Jul 16 07:13:39 PM PDT 24
Finished Jul 16 07:13:44 PM PDT 24
Peak memory 217044 kb
Host smart-f82ff143-4598-4bf4-8be6-f4fbf11be2a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016394227 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.3016394227
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.3337475344
Short name T353
Test name
Test status
Simulation time 22241279 ps
CPU time 0.96 seconds
Started Jul 16 07:13:37 PM PDT 24
Finished Jul 16 07:13:43 PM PDT 24
Peak memory 218740 kb
Host smart-b5554673-fc8a-44f7-a063-4a5c2896d10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337475344 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.3337475344
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.3230350300
Short name T590
Test name
Test status
Simulation time 65760058 ps
CPU time 1.27 seconds
Started Jul 16 07:13:36 PM PDT 24
Finished Jul 16 07:13:44 PM PDT 24
Peak memory 219728 kb
Host smart-55b20779-9001-4c0c-aa0f-c471c03dad8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230350300 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3230350300
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.845742355
Short name T540
Test name
Test status
Simulation time 32259382 ps
CPU time 0.99 seconds
Started Jul 16 07:13:40 PM PDT 24
Finished Jul 16 07:13:45 PM PDT 24
Peak memory 215772 kb
Host smart-7455dfaf-b797-48a9-8e93-b527cc3f2481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845742355 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.845742355
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.4138701158
Short name T332
Test name
Test status
Simulation time 19164797 ps
CPU time 1.05 seconds
Started Jul 16 07:13:35 PM PDT 24
Finished Jul 16 07:13:43 PM PDT 24
Peak memory 215556 kb
Host smart-023a5e64-fde7-4171-945c-c4d9d907ecb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138701158 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.4138701158
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.3470201788
Short name T787
Test name
Test status
Simulation time 62157612 ps
CPU time 1.74 seconds
Started Jul 16 07:13:41 PM PDT 24
Finished Jul 16 07:13:45 PM PDT 24
Peak memory 217612 kb
Host smart-335faf44-fbda-4e14-a91d-b909c9912c99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470201788 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3470201788
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.281751415
Short name T704
Test name
Test status
Simulation time 107297910260 ps
CPU time 651.95 seconds
Started Jul 16 07:13:40 PM PDT 24
Finished Jul 16 07:24:36 PM PDT 24
Peak memory 224068 kb
Host smart-6e59680f-5e72-49ce-a131-557f024374e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281751415 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.281751415
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.862581963
Short name T387
Test name
Test status
Simulation time 56848183 ps
CPU time 1.08 seconds
Started Jul 16 07:15:42 PM PDT 24
Finished Jul 16 07:16:40 PM PDT 24
Peak memory 218560 kb
Host smart-dc04f4b4-9ca4-4e43-ab75-ede8c2c39032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862581963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.862581963
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.3128078635
Short name T696
Test name
Test status
Simulation time 62114306 ps
CPU time 2.16 seconds
Started Jul 16 07:15:42 PM PDT 24
Finished Jul 16 07:16:41 PM PDT 24
Peak memory 219692 kb
Host smart-f5ae0888-6d9d-4263-b70f-c8ddb7004c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128078635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.3128078635
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.187970875
Short name T269
Test name
Test status
Simulation time 33852870 ps
CPU time 1.55 seconds
Started Jul 16 07:15:41 PM PDT 24
Finished Jul 16 07:16:40 PM PDT 24
Peak memory 218980 kb
Host smart-98a93023-6cb5-4270-be90-2985bedef57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187970875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.187970875
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.2564803910
Short name T328
Test name
Test status
Simulation time 55236845 ps
CPU time 1.04 seconds
Started Jul 16 07:15:42 PM PDT 24
Finished Jul 16 07:16:39 PM PDT 24
Peak memory 217608 kb
Host smart-9a4f2021-5a51-4a55-9596-e83db940ee39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564803910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.2564803910
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.3522621200
Short name T729
Test name
Test status
Simulation time 154118447 ps
CPU time 1.5 seconds
Started Jul 16 07:15:42 PM PDT 24
Finished Jul 16 07:16:41 PM PDT 24
Peak memory 218512 kb
Host smart-8f3c5de2-56a1-42ef-a5f1-e5eedb1787bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522621200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.3522621200
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2311945319
Short name T329
Test name
Test status
Simulation time 45599354 ps
CPU time 1.14 seconds
Started Jul 16 07:15:35 PM PDT 24
Finished Jul 16 07:16:31 PM PDT 24
Peak memory 220040 kb
Host smart-159865db-e7e3-4dda-b9c2-42e0d12ae87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311945319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2311945319
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.2423499498
Short name T2
Test name
Test status
Simulation time 57221933 ps
CPU time 1.54 seconds
Started Jul 16 07:15:36 PM PDT 24
Finished Jul 16 07:16:32 PM PDT 24
Peak memory 217712 kb
Host smart-ffe75722-9abf-4945-9ce1-c4145bf5e2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423499498 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2423499498
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.1024779311
Short name T885
Test name
Test status
Simulation time 33171096 ps
CPU time 1.3 seconds
Started Jul 16 07:15:42 PM PDT 24
Finished Jul 16 07:16:40 PM PDT 24
Peak memory 218720 kb
Host smart-1e49c52e-3aec-40f9-ac87-c126abb8242d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024779311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.1024779311
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.4179994851
Short name T681
Test name
Test status
Simulation time 75288889 ps
CPU time 1.69 seconds
Started Jul 16 07:15:34 PM PDT 24
Finished Jul 16 07:16:31 PM PDT 24
Peak memory 219392 kb
Host smart-e830e64e-bbd6-40f5-aef0-466b4915d960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179994851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.4179994851
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.1519061068
Short name T91
Test name
Test status
Simulation time 148360581 ps
CPU time 1.16 seconds
Started Jul 16 07:13:54 PM PDT 24
Finished Jul 16 07:13:59 PM PDT 24
Peak memory 218856 kb
Host smart-d0d911c0-163e-4dc4-a915-acc5e65f5eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519061068 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.1519061068
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1053129141
Short name T357
Test name
Test status
Simulation time 287869286 ps
CPU time 1.88 seconds
Started Jul 16 07:13:49 PM PDT 24
Finished Jul 16 07:13:55 PM PDT 24
Peak memory 207204 kb
Host smart-4dd23f6a-6621-4686-8227-5bc66e20eb62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053129141 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1053129141
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.2804346091
Short name T184
Test name
Test status
Simulation time 23654428 ps
CPU time 0.91 seconds
Started Jul 16 07:13:53 PM PDT 24
Finished Jul 16 07:13:59 PM PDT 24
Peak memory 216580 kb
Host smart-6dc4202f-4766-475b-b5fe-f4e23878477a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804346091 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.2804346091
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.3319790403
Short name T127
Test name
Test status
Simulation time 27241585 ps
CPU time 1.13 seconds
Started Jul 16 07:13:50 PM PDT 24
Finished Jul 16 07:13:56 PM PDT 24
Peak memory 217088 kb
Host smart-b9d18df8-bd60-4438-9c46-07913142fe09
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319790403 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.3319790403
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.2538934048
Short name T891
Test name
Test status
Simulation time 32061606 ps
CPU time 1.17 seconds
Started Jul 16 07:13:50 PM PDT 24
Finished Jul 16 07:13:56 PM PDT 24
Peak memory 217848 kb
Host smart-2bccd1f1-ef43-43cc-97c3-502e935ebcb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538934048 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2538934048
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.1213299126
Short name T690
Test name
Test status
Simulation time 47097789 ps
CPU time 1.3 seconds
Started Jul 16 07:13:53 PM PDT 24
Finished Jul 16 07:13:59 PM PDT 24
Peak memory 219216 kb
Host smart-9b3d0b82-b577-4832-a19a-20e10cb97c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213299126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.1213299126
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.1685052148
Short name T656
Test name
Test status
Simulation time 26455206 ps
CPU time 0.95 seconds
Started Jul 16 07:13:52 PM PDT 24
Finished Jul 16 07:13:58 PM PDT 24
Peak memory 216144 kb
Host smart-b8e2fcc0-cebb-425f-b664-44de33ae41a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685052148 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.1685052148
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.3244278698
Short name T772
Test name
Test status
Simulation time 27436090 ps
CPU time 0.92 seconds
Started Jul 16 07:13:50 PM PDT 24
Finished Jul 16 07:13:56 PM PDT 24
Peak memory 215556 kb
Host smart-7f37bd7f-6b2b-4eca-94ab-325ca918e138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244278698 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.3244278698
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.128714976
Short name T231
Test name
Test status
Simulation time 466768792 ps
CPU time 2.71 seconds
Started Jul 16 07:13:51 PM PDT 24
Finished Jul 16 07:13:59 PM PDT 24
Peak memory 217652 kb
Host smart-7969739a-855f-4882-8bb6-d435efbcb80a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128714976 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.128714976
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.1875923140
Short name T730
Test name
Test status
Simulation time 37801132285 ps
CPU time 976.69 seconds
Started Jul 16 07:13:52 PM PDT 24
Finished Jul 16 07:30:14 PM PDT 24
Peak memory 221180 kb
Host smart-b54dc1ce-b8be-4105-bd80-79c26793dce3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875923140 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.1875923140
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.1270155910
Short name T760
Test name
Test status
Simulation time 48021731 ps
CPU time 1.17 seconds
Started Jul 16 07:15:34 PM PDT 24
Finished Jul 16 07:16:30 PM PDT 24
Peak memory 217832 kb
Host smart-906e9e56-c204-414c-a419-d7de73b8ebd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270155910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.1270155910
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.1302277903
Short name T471
Test name
Test status
Simulation time 219959606 ps
CPU time 3.06 seconds
Started Jul 16 07:15:50 PM PDT 24
Finished Jul 16 07:16:48 PM PDT 24
Peak memory 217740 kb
Host smart-355d7244-bf0a-472e-b42d-65cc967782a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302277903 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.1302277903
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.3104048127
Short name T824
Test name
Test status
Simulation time 67712105 ps
CPU time 1.37 seconds
Started Jul 16 07:15:38 PM PDT 24
Finished Jul 16 07:16:36 PM PDT 24
Peak memory 220100 kb
Host smart-83d222bf-ade3-424e-b0c2-43c3a333f680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104048127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.3104048127
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.205603379
Short name T426
Test name
Test status
Simulation time 46394403 ps
CPU time 1.2 seconds
Started Jul 16 07:15:42 PM PDT 24
Finished Jul 16 07:16:40 PM PDT 24
Peak memory 217344 kb
Host smart-e1c4c9cf-0e10-4e22-b3ed-ed5e729bdb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205603379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.205603379
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.14234196
Short name T830
Test name
Test status
Simulation time 23218515 ps
CPU time 1.18 seconds
Started Jul 16 07:15:39 PM PDT 24
Finished Jul 16 07:16:37 PM PDT 24
Peak memory 217756 kb
Host smart-91fac46c-f747-4570-b712-afc871d9df79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14234196 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.14234196
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.4020549727
Short name T909
Test name
Test status
Simulation time 103515112 ps
CPU time 1.25 seconds
Started Jul 16 07:15:50 PM PDT 24
Finished Jul 16 07:16:47 PM PDT 24
Peak memory 217752 kb
Host smart-ea403973-2187-4435-a209-1c4eb9f99945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020549727 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.4020549727
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.984586773
Short name T616
Test name
Test status
Simulation time 85949645 ps
CPU time 1.03 seconds
Started Jul 16 07:15:41 PM PDT 24
Finished Jul 16 07:16:39 PM PDT 24
Peak memory 217824 kb
Host smart-e783a0af-ed30-45af-9352-67e35c177b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984586773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.984586773
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.3756660338
Short name T36
Test name
Test status
Simulation time 45820622 ps
CPU time 1.48 seconds
Started Jul 16 07:15:38 PM PDT 24
Finished Jul 16 07:16:36 PM PDT 24
Peak memory 218764 kb
Host smart-a3fdc167-2917-4762-a2ee-4c4e0bfad505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756660338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3756660338
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.4153510340
Short name T78
Test name
Test status
Simulation time 106137079 ps
CPU time 1.38 seconds
Started Jul 16 07:15:37 PM PDT 24
Finished Jul 16 07:16:35 PM PDT 24
Peak memory 219216 kb
Host smart-5245ba8e-d1c1-4489-923e-9193667e3dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153510340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.4153510340
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.2723896746
Short name T762
Test name
Test status
Simulation time 37922998 ps
CPU time 1.14 seconds
Started Jul 16 07:13:53 PM PDT 24
Finished Jul 16 07:13:59 PM PDT 24
Peak memory 220244 kb
Host smart-cf5d3df5-49b4-46cb-8b1e-8aa3d3ac6fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723896746 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2723896746
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.88535043
Short name T435
Test name
Test status
Simulation time 39408025 ps
CPU time 0.92 seconds
Started Jul 16 07:13:54 PM PDT 24
Finished Jul 16 07:13:59 PM PDT 24
Peak memory 215208 kb
Host smart-2362d5f8-1f3d-4af8-bd09-f050fefa8bdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88535043 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.88535043
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.1843646778
Short name T646
Test name
Test status
Simulation time 32919544 ps
CPU time 0.85 seconds
Started Jul 16 07:13:51 PM PDT 24
Finished Jul 16 07:13:57 PM PDT 24
Peak memory 216344 kb
Host smart-e3ef79ea-8fea-42b1-b04b-1051514a1bb1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843646778 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1843646778
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.351949745
Short name T132
Test name
Test status
Simulation time 166350555 ps
CPU time 1.08 seconds
Started Jul 16 07:13:51 PM PDT 24
Finished Jul 16 07:13:57 PM PDT 24
Peak memory 217320 kb
Host smart-a03c05e5-7c13-4388-ad52-a48cab6d68ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351949745 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_di
sable_auto_req_mode.351949745
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.2096019307
Short name T8
Test name
Test status
Simulation time 31922139 ps
CPU time 1.09 seconds
Started Jul 16 07:13:47 PM PDT 24
Finished Jul 16 07:13:52 PM PDT 24
Peak memory 229824 kb
Host smart-b4616d50-717c-496f-9922-5bcb036a4422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096019307 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2096019307
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.4173004299
Short name T913
Test name
Test status
Simulation time 69689360 ps
CPU time 1.04 seconds
Started Jul 16 07:13:51 PM PDT 24
Finished Jul 16 07:13:57 PM PDT 24
Peak memory 217516 kb
Host smart-74993c3e-f153-4511-acf2-ecc8ce3f8e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173004299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.4173004299
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.3218935016
Short name T355
Test name
Test status
Simulation time 52212915 ps
CPU time 0.86 seconds
Started Jul 16 07:13:52 PM PDT 24
Finished Jul 16 07:13:58 PM PDT 24
Peak memory 215624 kb
Host smart-2b37b86c-293f-4846-9148-463a6ced4dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218935016 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.3218935016
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.4238249471
Short name T613
Test name
Test status
Simulation time 42811450 ps
CPU time 0.96 seconds
Started Jul 16 07:13:55 PM PDT 24
Finished Jul 16 07:14:00 PM PDT 24
Peak memory 215564 kb
Host smart-7b125c4c-9124-40ab-b7ba-9fc3ec7072c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238249471 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.4238249471
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.2559680953
Short name T436
Test name
Test status
Simulation time 105299997 ps
CPU time 2.57 seconds
Started Jul 16 07:13:49 PM PDT 24
Finished Jul 16 07:13:56 PM PDT 24
Peak memory 215672 kb
Host smart-3766be7d-016c-494c-b2f7-64e232d0dfd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559680953 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2559680953
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.2142103188
Short name T87
Test name
Test status
Simulation time 36633520757 ps
CPU time 905.5 seconds
Started Jul 16 07:13:48 PM PDT 24
Finished Jul 16 07:28:59 PM PDT 24
Peak memory 218960 kb
Host smart-2ebfe090-caef-4e6f-9502-3d5c015d8471
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142103188 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.2142103188
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.4028860611
Short name T921
Test name
Test status
Simulation time 66191271 ps
CPU time 2.03 seconds
Started Jul 16 07:15:39 PM PDT 24
Finished Jul 16 07:16:38 PM PDT 24
Peak memory 220292 kb
Host smart-7acb6021-de12-427d-b52c-317a6023c1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028860611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.4028860611
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.4274709414
Short name T661
Test name
Test status
Simulation time 91428582 ps
CPU time 1.15 seconds
Started Jul 16 07:15:39 PM PDT 24
Finished Jul 16 07:16:37 PM PDT 24
Peak memory 217640 kb
Host smart-f253b728-8e70-4b81-8f6a-013cf8bec530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274709414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.4274709414
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.3470377990
Short name T585
Test name
Test status
Simulation time 38002098 ps
CPU time 1.37 seconds
Started Jul 16 07:15:37 PM PDT 24
Finished Jul 16 07:16:36 PM PDT 24
Peak memory 217564 kb
Host smart-d4d94941-4be8-4fa3-be85-e55c2ff12926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470377990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.3470377990
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.3210521364
Short name T649
Test name
Test status
Simulation time 61817630 ps
CPU time 1.28 seconds
Started Jul 16 07:15:42 PM PDT 24
Finished Jul 16 07:16:41 PM PDT 24
Peak memory 217564 kb
Host smart-36915665-bb74-4977-82d0-c1e45c076e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210521364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3210521364
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.4018474893
Short name T466
Test name
Test status
Simulation time 64309644 ps
CPU time 1.53 seconds
Started Jul 16 07:15:39 PM PDT 24
Finished Jul 16 07:16:37 PM PDT 24
Peak memory 218800 kb
Host smart-48fa1638-9fa7-4a10-b666-16d92fb3c960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018474893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.4018474893
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.680216266
Short name T324
Test name
Test status
Simulation time 114714003 ps
CPU time 1.53 seconds
Started Jul 16 07:15:36 PM PDT 24
Finished Jul 16 07:16:32 PM PDT 24
Peak memory 220280 kb
Host smart-f5475b68-4bdb-4723-92ba-085021faece4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680216266 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.680216266
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.487698764
Short name T612
Test name
Test status
Simulation time 49931008 ps
CPU time 1.54 seconds
Started Jul 16 07:15:50 PM PDT 24
Finished Jul 16 07:16:47 PM PDT 24
Peak memory 218808 kb
Host smart-e5432790-3333-4e29-b946-6b83a6fab316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487698764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.487698764
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.1901478656
Short name T526
Test name
Test status
Simulation time 292937522 ps
CPU time 1.33 seconds
Started Jul 16 07:15:38 PM PDT 24
Finished Jul 16 07:16:36 PM PDT 24
Peak memory 219088 kb
Host smart-f9bd8576-056a-4c94-a400-2f966bc0b953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901478656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.1901478656
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.2878225398
Short name T465
Test name
Test status
Simulation time 97283400 ps
CPU time 1.31 seconds
Started Jul 16 07:15:42 PM PDT 24
Finished Jul 16 07:16:40 PM PDT 24
Peak memory 219104 kb
Host smart-e6c105c5-20a4-4e09-a0f0-f7941c44e119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878225398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.2878225398
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.1505095232
Short name T633
Test name
Test status
Simulation time 37165818 ps
CPU time 1.15 seconds
Started Jul 16 07:13:54 PM PDT 24
Finished Jul 16 07:14:00 PM PDT 24
Peak memory 218836 kb
Host smart-c5652884-a4ae-456b-82ae-061bbf4f1e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505095232 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1505095232
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.3517670511
Short name T861
Test name
Test status
Simulation time 72771111 ps
CPU time 0.98 seconds
Started Jul 16 07:13:49 PM PDT 24
Finished Jul 16 07:13:55 PM PDT 24
Peak memory 207020 kb
Host smart-534f1076-3eb8-41f9-86e5-a97ecc035bca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517670511 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3517670511
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.2314216513
Short name T881
Test name
Test status
Simulation time 33629528 ps
CPU time 0.91 seconds
Started Jul 16 07:13:49 PM PDT 24
Finished Jul 16 07:13:54 PM PDT 24
Peak memory 216560 kb
Host smart-1e7251a0-16bb-4e6e-af56-ac1978caeee9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314216513 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2314216513
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_genbits.562375463
Short name T503
Test name
Test status
Simulation time 100204110 ps
CPU time 1.2 seconds
Started Jul 16 07:13:54 PM PDT 24
Finished Jul 16 07:14:00 PM PDT 24
Peak memory 219156 kb
Host smart-14cdcbf9-1ce9-45f7-91dd-af4027954d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562375463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.562375463
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.3798612555
Short name T450
Test name
Test status
Simulation time 119459622 ps
CPU time 1.03 seconds
Started Jul 16 07:13:52 PM PDT 24
Finished Jul 16 07:13:58 PM PDT 24
Peak memory 224092 kb
Host smart-3bfd04aa-3b66-43b2-b002-b9ad526a365a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798612555 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.3798612555
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.2116597235
Short name T342
Test name
Test status
Simulation time 46192147 ps
CPU time 0.95 seconds
Started Jul 16 07:13:54 PM PDT 24
Finished Jul 16 07:13:59 PM PDT 24
Peak memory 215608 kb
Host smart-524737de-0c5f-4ebc-9a91-c7d256506166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116597235 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.2116597235
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.4266706233
Short name T394
Test name
Test status
Simulation time 107235828 ps
CPU time 2.66 seconds
Started Jul 16 07:13:50 PM PDT 24
Finished Jul 16 07:13:58 PM PDT 24
Peak memory 220232 kb
Host smart-fe3c0f35-bc5c-4c53-988e-40630741a149
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266706233 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.4266706233
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.4265530151
Short name T856
Test name
Test status
Simulation time 90747110863 ps
CPU time 616.9 seconds
Started Jul 16 07:13:51 PM PDT 24
Finished Jul 16 07:24:13 PM PDT 24
Peak memory 223924 kb
Host smart-d06c54a4-306e-40d1-859e-caaa3821e3a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265530151 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.4265530151
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.2496487530
Short name T343
Test name
Test status
Simulation time 53712958 ps
CPU time 1.14 seconds
Started Jul 16 07:15:36 PM PDT 24
Finished Jul 16 07:16:31 PM PDT 24
Peak memory 218760 kb
Host smart-aacf5e4d-d4f8-4518-be0b-b47146de8a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496487530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.2496487530
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.409343611
Short name T310
Test name
Test status
Simulation time 200647079 ps
CPU time 2.68 seconds
Started Jul 16 07:15:38 PM PDT 24
Finished Jul 16 07:16:37 PM PDT 24
Peak memory 218120 kb
Host smart-45eef5f2-1a49-4f53-b7d2-473863abd253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409343611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.409343611
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.3823251017
Short name T413
Test name
Test status
Simulation time 69946348 ps
CPU time 1.2 seconds
Started Jul 16 07:15:49 PM PDT 24
Finished Jul 16 07:16:46 PM PDT 24
Peak memory 218944 kb
Host smart-21131d7f-b6db-4576-9aab-6630669403e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823251017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.3823251017
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.56822554
Short name T531
Test name
Test status
Simulation time 49230577 ps
CPU time 1.12 seconds
Started Jul 16 07:15:36 PM PDT 24
Finished Jul 16 07:16:31 PM PDT 24
Peak memory 217696 kb
Host smart-e3f7ae5d-18bb-43d3-b685-382ee04b975b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56822554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.56822554
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.972490824
Short name T746
Test name
Test status
Simulation time 33983649 ps
CPU time 1.28 seconds
Started Jul 16 07:15:37 PM PDT 24
Finished Jul 16 07:16:35 PM PDT 24
Peak memory 217580 kb
Host smart-0b86a94a-4f22-4c81-87d4-e640cdaecf34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972490824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.972490824
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3845953412
Short name T939
Test name
Test status
Simulation time 60447331 ps
CPU time 0.93 seconds
Started Jul 16 07:15:36 PM PDT 24
Finished Jul 16 07:16:31 PM PDT 24
Peak memory 217592 kb
Host smart-0d4a61d6-8513-41e4-903c-b430d5a26f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845953412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3845953412
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.4266333470
Short name T360
Test name
Test status
Simulation time 26066915 ps
CPU time 1.31 seconds
Started Jul 16 07:15:38 PM PDT 24
Finished Jul 16 07:16:35 PM PDT 24
Peak memory 218644 kb
Host smart-7edcf121-364c-49c1-bce4-15aa9237d0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266333470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.4266333470
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.2788511640
Short name T549
Test name
Test status
Simulation time 82023423 ps
CPU time 1.11 seconds
Started Jul 16 07:15:40 PM PDT 24
Finished Jul 16 07:16:37 PM PDT 24
Peak memory 217524 kb
Host smart-7234944c-502b-403b-99dc-ca82e394647d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788511640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.2788511640
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.3359713003
Short name T562
Test name
Test status
Simulation time 47281572 ps
CPU time 1.69 seconds
Started Jul 16 07:15:38 PM PDT 24
Finished Jul 16 07:16:36 PM PDT 24
Peak memory 218888 kb
Host smart-aef6ba3b-8ddf-4160-ba2d-5a1a183e5eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359713003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3359713003
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.2919285076
Short name T987
Test name
Test status
Simulation time 106989339 ps
CPU time 1.3 seconds
Started Jul 16 07:11:55 PM PDT 24
Finished Jul 16 07:13:18 PM PDT 24
Peak memory 221576 kb
Host smart-1a329578-dc77-42d6-8dba-3eccce94aa5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919285076 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.2919285076
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.3313286485
Short name T749
Test name
Test status
Simulation time 20662169 ps
CPU time 1.02 seconds
Started Jul 16 07:11:54 PM PDT 24
Finished Jul 16 07:13:17 PM PDT 24
Peak memory 215152 kb
Host smart-3ec59ce4-756c-46ad-a52d-297a057c1c42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313286485 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3313286485
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.1426871606
Short name T692
Test name
Test status
Simulation time 31677517 ps
CPU time 0.82 seconds
Started Jul 16 07:11:55 PM PDT 24
Finished Jul 16 07:13:17 PM PDT 24
Peak memory 216500 kb
Host smart-2f12373a-4b9f-4f97-a2af-c5cdb9cf8608
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426871606 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1426871606
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.69469950
Short name T437
Test name
Test status
Simulation time 43115234 ps
CPU time 1.05 seconds
Started Jul 16 07:11:55 PM PDT 24
Finished Jul 16 07:13:18 PM PDT 24
Peak memory 220276 kb
Host smart-0ea6358b-ef16-4176-aad7-29b790bc7566
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69469950 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disa
ble_auto_req_mode.69469950
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_genbits.2999304711
Short name T398
Test name
Test status
Simulation time 60979121 ps
CPU time 0.95 seconds
Started Jul 16 07:11:53 PM PDT 24
Finished Jul 16 07:13:17 PM PDT 24
Peak memory 217716 kb
Host smart-cfab310f-e3cb-485c-8942-36ed0cc61c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999304711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.2999304711
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_regwen.1648739876
Short name T929
Test name
Test status
Simulation time 36344694 ps
CPU time 0.87 seconds
Started Jul 16 07:11:53 PM PDT 24
Finished Jul 16 07:13:17 PM PDT 24
Peak memory 207432 kb
Host smart-1c169d40-6cf0-4af5-a187-a2dd32a8799d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648739876 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1648739876
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.608334892
Short name T55
Test name
Test status
Simulation time 509616089 ps
CPU time 7.35 seconds
Started Jul 16 07:11:53 PM PDT 24
Finished Jul 16 07:13:23 PM PDT 24
Peak memory 236612 kb
Host smart-6e3e129b-0f7a-4d8c-af72-fc42c5a7a305
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608334892 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.608334892
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.326813649
Short name T685
Test name
Test status
Simulation time 27611707 ps
CPU time 0.92 seconds
Started Jul 16 07:11:55 PM PDT 24
Finished Jul 16 07:13:18 PM PDT 24
Peak memory 215612 kb
Host smart-be3bddb3-23ad-4fc6-80ea-7e6e8ef0b30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326813649 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.326813649
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.1768480188
Short name T563
Test name
Test status
Simulation time 245588154 ps
CPU time 3.05 seconds
Started Jul 16 07:11:53 PM PDT 24
Finished Jul 16 07:13:19 PM PDT 24
Peak memory 215716 kb
Host smart-1f7b1c30-f529-425a-a499-074d2a12cebf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768480188 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1768480188
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3184506671
Short name T223
Test name
Test status
Simulation time 136636335610 ps
CPU time 312.33 seconds
Started Jul 16 07:11:55 PM PDT 24
Finished Jul 16 07:18:29 PM PDT 24
Peak memory 218616 kb
Host smart-0eac058c-108e-4f94-9a8a-40e55fb45786
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184506671 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3184506671
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.483961581
Short name T165
Test name
Test status
Simulation time 87262261 ps
CPU time 1.14 seconds
Started Jul 16 07:13:48 PM PDT 24
Finished Jul 16 07:13:54 PM PDT 24
Peak memory 219868 kb
Host smart-9b23928e-7605-4a62-ac8e-7aef15e2ceff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483961581 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.483961581
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.228714114
Short name T359
Test name
Test status
Simulation time 28172251 ps
CPU time 0.92 seconds
Started Jul 16 07:13:51 PM PDT 24
Finished Jul 16 07:13:56 PM PDT 24
Peak memory 207012 kb
Host smart-1fe53c08-f456-4f46-8d47-490461cb819b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228714114 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.228714114
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.3869479286
Short name T652
Test name
Test status
Simulation time 37098516 ps
CPU time 1.27 seconds
Started Jul 16 07:13:49 PM PDT 24
Finished Jul 16 07:13:55 PM PDT 24
Peak memory 217324 kb
Host smart-f23e574d-9470-4a06-a33d-f3fe6b47717f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869479286 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.3869479286
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.2973482306
Short name T923
Test name
Test status
Simulation time 29485618 ps
CPU time 1.27 seconds
Started Jul 16 07:13:53 PM PDT 24
Finished Jul 16 07:13:59 PM PDT 24
Peak memory 220032 kb
Host smart-af5a5a59-bcf0-44db-a0a2-8fb1488b0fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973482306 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.2973482306
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.3870806901
Short name T882
Test name
Test status
Simulation time 70217797 ps
CPU time 1.39 seconds
Started Jul 16 07:13:49 PM PDT 24
Finished Jul 16 07:13:55 PM PDT 24
Peak memory 217744 kb
Host smart-c4f2ec01-0489-4b71-bf11-51bf1a3d1358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870806901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3870806901
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.2816370830
Short name T30
Test name
Test status
Simulation time 23499542 ps
CPU time 1.04 seconds
Started Jul 16 07:13:52 PM PDT 24
Finished Jul 16 07:13:58 PM PDT 24
Peak memory 216232 kb
Host smart-d519cba8-9e3d-49d5-9016-3561cf1a3e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816370830 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2816370830
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.2303103887
Short name T571
Test name
Test status
Simulation time 53894756 ps
CPU time 0.84 seconds
Started Jul 16 07:13:46 PM PDT 24
Finished Jul 16 07:13:48 PM PDT 24
Peak memory 215612 kb
Host smart-477a8926-b364-4c35-a358-ef04d9887c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303103887 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.2303103887
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.1646112220
Short name T452
Test name
Test status
Simulation time 759478590 ps
CPU time 3.51 seconds
Started Jul 16 07:13:47 PM PDT 24
Finished Jul 16 07:13:55 PM PDT 24
Peak memory 217720 kb
Host smart-b5376f95-958d-4c74-9386-aec4a936ce0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646112220 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.1646112220
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2161074204
Short name T56
Test name
Test status
Simulation time 9909272697 ps
CPU time 241.78 seconds
Started Jul 16 07:13:51 PM PDT 24
Finished Jul 16 07:17:58 PM PDT 24
Peak memory 221960 kb
Host smart-55e7abe4-0681-4d7a-9a45-160f8ec9e852
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161074204 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2161074204
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.4246823133
Short name T709
Test name
Test status
Simulation time 26046272 ps
CPU time 1.21 seconds
Started Jul 16 07:13:52 PM PDT 24
Finished Jul 16 07:13:58 PM PDT 24
Peak memory 219812 kb
Host smart-1c2ad784-2add-4550-96c1-2ae59fd4c1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246823133 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.4246823133
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.1947243406
Short name T859
Test name
Test status
Simulation time 24629361 ps
CPU time 0.9 seconds
Started Jul 16 07:13:52 PM PDT 24
Finished Jul 16 07:13:58 PM PDT 24
Peak memory 206976 kb
Host smart-06d5f859-ee7c-49f2-8537-ea67dd838da6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947243406 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.1947243406
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.1763532859
Short name T170
Test name
Test status
Simulation time 32129476 ps
CPU time 0.88 seconds
Started Jul 16 07:13:50 PM PDT 24
Finished Jul 16 07:13:56 PM PDT 24
Peak memory 216508 kb
Host smart-30cac040-f237-4702-abf3-87547f6a1583
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763532859 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.1763532859
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.854505428
Short name T905
Test name
Test status
Simulation time 44108491 ps
CPU time 1.38 seconds
Started Jul 16 07:13:51 PM PDT 24
Finished Jul 16 07:13:58 PM PDT 24
Peak memory 216864 kb
Host smart-597fda53-1e61-44ed-b883-973e65a4aa8f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854505428 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_di
sable_auto_req_mode.854505428
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.1619962850
Short name T733
Test name
Test status
Simulation time 91276470 ps
CPU time 1.11 seconds
Started Jul 16 07:13:50 PM PDT 24
Finished Jul 16 07:13:56 PM PDT 24
Peak memory 219972 kb
Host smart-4db3530d-1aa2-4fbd-b6ee-c5d4343d951b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619962850 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.1619962850
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.269839761
Short name T402
Test name
Test status
Simulation time 71484865 ps
CPU time 1.14 seconds
Started Jul 16 07:13:51 PM PDT 24
Finished Jul 16 07:13:57 PM PDT 24
Peak memory 217576 kb
Host smart-50f828d9-bef3-443b-8c29-2f04524da606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269839761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.269839761
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.3672802502
Short name T82
Test name
Test status
Simulation time 36843908 ps
CPU time 0.87 seconds
Started Jul 16 07:13:54 PM PDT 24
Finished Jul 16 07:13:59 PM PDT 24
Peak memory 215864 kb
Host smart-6ce3bd38-54ad-4f81-a6b8-d123e17c0537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672802502 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.3672802502
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.3151761620
Short name T399
Test name
Test status
Simulation time 51583645 ps
CPU time 0.94 seconds
Started Jul 16 07:13:51 PM PDT 24
Finished Jul 16 07:13:56 PM PDT 24
Peak memory 215588 kb
Host smart-a82cccc8-a2c0-4426-ba23-5285fd73d9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151761620 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.3151761620
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.4141775722
Short name T811
Test name
Test status
Simulation time 278566117 ps
CPU time 2.67 seconds
Started Jul 16 07:13:50 PM PDT 24
Finished Jul 16 07:13:58 PM PDT 24
Peak memory 217496 kb
Host smart-7c4fb3ea-f216-4c60-8689-9669a3a93dd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141775722 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.4141775722
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.3719098199
Short name T817
Test name
Test status
Simulation time 485718438910 ps
CPU time 2819.32 seconds
Started Jul 16 07:13:50 PM PDT 24
Finished Jul 16 08:00:55 PM PDT 24
Peak memory 231348 kb
Host smart-164d15d2-e29d-43bf-ab54-ef8dbc1761f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719098199 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.3719098199
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.2510606448
Short name T102
Test name
Test status
Simulation time 45339158 ps
CPU time 1.24 seconds
Started Jul 16 07:14:05 PM PDT 24
Finished Jul 16 07:14:09 PM PDT 24
Peak memory 220828 kb
Host smart-0b3cea1d-f24f-459d-a7ed-3be60d4c24ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510606448 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.2510606448
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.1027871244
Short name T962
Test name
Test status
Simulation time 62287146 ps
CPU time 1.03 seconds
Started Jul 16 07:14:02 PM PDT 24
Finished Jul 16 07:14:04 PM PDT 24
Peak memory 207000 kb
Host smart-560da1ef-befd-44f9-b709-dd490bedc565
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027871244 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.1027871244
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.2108506211
Short name T625
Test name
Test status
Simulation time 35260625 ps
CPU time 1.24 seconds
Started Jul 16 07:14:05 PM PDT 24
Finished Jul 16 07:14:09 PM PDT 24
Peak memory 217636 kb
Host smart-f548e488-e055-4bd6-8d62-73ad1fb789fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108506211 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.2108506211
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.3926669290
Short name T581
Test name
Test status
Simulation time 50583316 ps
CPU time 0.83 seconds
Started Jul 16 07:14:08 PM PDT 24
Finished Jul 16 07:14:13 PM PDT 24
Peak memory 218668 kb
Host smart-118cef40-49a1-4bb8-a8e7-e16129756a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926669290 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.3926669290
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.613828080
Short name T463
Test name
Test status
Simulation time 34037491 ps
CPU time 1.26 seconds
Started Jul 16 07:13:51 PM PDT 24
Finished Jul 16 07:13:58 PM PDT 24
Peak memory 218712 kb
Host smart-5a0aa2f6-c7a5-467f-866b-edb8f150f85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613828080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.613828080
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.2756305783
Short name T975
Test name
Test status
Simulation time 27372473 ps
CPU time 1.01 seconds
Started Jul 16 07:14:02 PM PDT 24
Finished Jul 16 07:14:04 PM PDT 24
Peak memory 216188 kb
Host smart-4f2ab1e9-57cf-4425-9201-8bf1d749e22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756305783 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.2756305783
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.3026072546
Short name T663
Test name
Test status
Simulation time 147458119 ps
CPU time 0.9 seconds
Started Jul 16 07:13:52 PM PDT 24
Finished Jul 16 07:13:58 PM PDT 24
Peak memory 215376 kb
Host smart-85825d9d-1ffd-40db-b2b7-d1304d24bb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026072546 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.3026072546
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.4104007444
Short name T846
Test name
Test status
Simulation time 1671117067 ps
CPU time 4.14 seconds
Started Jul 16 07:13:50 PM PDT 24
Finished Jul 16 07:13:59 PM PDT 24
Peak memory 217420 kb
Host smart-0af3f0ac-3f78-4c45-8d37-43e02e47ada2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104007444 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.4104007444
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.483727688
Short name T33
Test name
Test status
Simulation time 26697078944 ps
CPU time 637.29 seconds
Started Jul 16 07:14:07 PM PDT 24
Finished Jul 16 07:24:48 PM PDT 24
Peak memory 223832 kb
Host smart-5e2904d8-7b14-455e-8389-e692a751a256
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483727688 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.483727688
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.2679017621
Short name T235
Test name
Test status
Simulation time 48217008 ps
CPU time 1.22 seconds
Started Jul 16 07:14:11 PM PDT 24
Finished Jul 16 07:14:17 PM PDT 24
Peak memory 219520 kb
Host smart-c02b0aee-3996-4abb-8cf9-be329ea85a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679017621 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.2679017621
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.281354927
Short name T538
Test name
Test status
Simulation time 44731112 ps
CPU time 0.9 seconds
Started Jul 16 07:14:07 PM PDT 24
Finished Jul 16 07:14:12 PM PDT 24
Peak memory 215188 kb
Host smart-bc20a6d6-3dca-4310-968f-4d944a7f7a1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281354927 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.281354927
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.2529217234
Short name T196
Test name
Test status
Simulation time 19782373 ps
CPU time 0.87 seconds
Started Jul 16 07:14:06 PM PDT 24
Finished Jul 16 07:14:10 PM PDT 24
Peak memory 216556 kb
Host smart-5232a707-5e56-4f53-81bb-05c08a3cad28
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529217234 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.2529217234
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.1424689071
Short name T588
Test name
Test status
Simulation time 33967204 ps
CPU time 1.24 seconds
Started Jul 16 07:14:11 PM PDT 24
Finished Jul 16 07:14:18 PM PDT 24
Peak memory 217176 kb
Host smart-284e98f6-adc0-4441-b22d-0add29f9285a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424689071 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.1424689071
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.26631806
Short name T494
Test name
Test status
Simulation time 37443786 ps
CPU time 1.01 seconds
Started Jul 16 07:14:02 PM PDT 24
Finished Jul 16 07:14:04 PM PDT 24
Peak memory 218724 kb
Host smart-6964db59-b6ee-4dc2-9728-3af899b13c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26631806 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.26631806
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.1211664653
Short name T305
Test name
Test status
Simulation time 71896938 ps
CPU time 1.61 seconds
Started Jul 16 07:14:07 PM PDT 24
Finished Jul 16 07:14:13 PM PDT 24
Peak memory 218788 kb
Host smart-14d5b0e4-bafd-48f8-8e7c-e17c0fba22b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211664653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.1211664653
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.2830956172
Short name T813
Test name
Test status
Simulation time 26188141 ps
CPU time 0.96 seconds
Started Jul 16 07:14:08 PM PDT 24
Finished Jul 16 07:14:13 PM PDT 24
Peak memory 215808 kb
Host smart-e6d3dff5-ce71-49b8-9f39-7c409a144385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830956172 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.2830956172
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.3419161521
Short name T937
Test name
Test status
Simulation time 23386709 ps
CPU time 1.01 seconds
Started Jul 16 07:14:07 PM PDT 24
Finished Jul 16 07:14:12 PM PDT 24
Peak memory 215612 kb
Host smart-7103bcc8-a0a6-4332-8e62-25300ae83276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419161521 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.3419161521
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.505199458
Short name T989
Test name
Test status
Simulation time 650006282 ps
CPU time 3.74 seconds
Started Jul 16 07:14:04 PM PDT 24
Finished Jul 16 07:14:09 PM PDT 24
Peak memory 217508 kb
Host smart-0a886d25-ed57-44cf-af6a-b7f1be69d3c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505199458 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.505199458
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.2459317846
Short name T220
Test name
Test status
Simulation time 148790286419 ps
CPU time 413.88 seconds
Started Jul 16 07:14:08 PM PDT 24
Finished Jul 16 07:21:06 PM PDT 24
Peak memory 218812 kb
Host smart-18600140-a665-4587-8f03-773bf2cdd2df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459317846 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.2459317846
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.2739728264
Short name T935
Test name
Test status
Simulation time 46650408 ps
CPU time 1.3 seconds
Started Jul 16 07:14:05 PM PDT 24
Finished Jul 16 07:14:08 PM PDT 24
Peak memory 219008 kb
Host smart-32c1cf34-23d0-4e8c-b2cc-b5d93fc53fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739728264 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2739728264
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.3172615766
Short name T702
Test name
Test status
Simulation time 38091200 ps
CPU time 0.92 seconds
Started Jul 16 07:14:06 PM PDT 24
Finished Jul 16 07:14:10 PM PDT 24
Peak memory 215108 kb
Host smart-4169aa41-9d11-4ee8-8128-40f5601b3eb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172615766 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.3172615766
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.339140800
Short name T676
Test name
Test status
Simulation time 21273764 ps
CPU time 0.86 seconds
Started Jul 16 07:14:08 PM PDT 24
Finished Jul 16 07:14:13 PM PDT 24
Peak memory 216644 kb
Host smart-ef5964de-e0d0-44e4-89c9-5b519b05d725
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339140800 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.339140800
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_err.4125595064
Short name T94
Test name
Test status
Simulation time 62735142 ps
CPU time 1.14 seconds
Started Jul 16 07:14:04 PM PDT 24
Finished Jul 16 07:14:06 PM PDT 24
Peak memory 230036 kb
Host smart-968121ba-d2fd-45ec-9efd-7341d0f6e330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125595064 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.4125595064
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.560109603
Short name T71
Test name
Test status
Simulation time 80757011 ps
CPU time 1.98 seconds
Started Jul 16 07:14:07 PM PDT 24
Finished Jul 16 07:14:12 PM PDT 24
Peak memory 215552 kb
Host smart-79c99a6a-9f34-4e20-8020-55e98d98b740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560109603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.560109603
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.3961910002
Short name T741
Test name
Test status
Simulation time 39007457 ps
CPU time 0.9 seconds
Started Jul 16 07:14:06 PM PDT 24
Finished Jul 16 07:14:10 PM PDT 24
Peak memory 215752 kb
Host smart-0c47e23d-d96d-4b96-b7b2-a4431596e854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961910002 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.3961910002
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.2867140929
Short name T639
Test name
Test status
Simulation time 17606651 ps
CPU time 0.97 seconds
Started Jul 16 07:14:07 PM PDT 24
Finished Jul 16 07:14:12 PM PDT 24
Peak memory 215572 kb
Host smart-82253f5d-ecd2-4cf3-86fe-91e006064d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867140929 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.2867140929
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.2353826764
Short name T653
Test name
Test status
Simulation time 523114208 ps
CPU time 5.11 seconds
Started Jul 16 07:14:01 PM PDT 24
Finished Jul 16 07:14:07 PM PDT 24
Peak memory 215592 kb
Host smart-207041bb-cb50-4c08-939a-a290ef71a0be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353826764 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.2353826764
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.3290715448
Short name T34
Test name
Test status
Simulation time 170800882679 ps
CPU time 1010.25 seconds
Started Jul 16 07:14:05 PM PDT 24
Finished Jul 16 07:30:57 PM PDT 24
Peak memory 221784 kb
Host smart-25f10df3-330b-45fa-9fa0-8163d756e1a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290715448 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.3290715448
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.517237578
Short name T476
Test name
Test status
Simulation time 41553651 ps
CPU time 1.11 seconds
Started Jul 16 07:14:03 PM PDT 24
Finished Jul 16 07:14:05 PM PDT 24
Peak memory 218692 kb
Host smart-16bc1c64-be04-48a9-8ad6-030fd23d4402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517237578 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.517237578
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.148843149
Short name T470
Test name
Test status
Simulation time 20069116 ps
CPU time 0.81 seconds
Started Jul 16 07:14:19 PM PDT 24
Finished Jul 16 07:14:26 PM PDT 24
Peak memory 207036 kb
Host smart-31ab96fa-7cbd-420e-bdd4-c1549901d4e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148843149 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.148843149
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.1541863987
Short name T189
Test name
Test status
Simulation time 27261579 ps
CPU time 0.82 seconds
Started Jul 16 07:14:06 PM PDT 24
Finished Jul 16 07:14:09 PM PDT 24
Peak memory 216616 kb
Host smart-b1f57792-5a40-4a79-b0de-7480347a4c8b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541863987 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1541863987
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.2168772382
Short name T200
Test name
Test status
Simulation time 44326741 ps
CPU time 1.13 seconds
Started Jul 16 07:14:11 PM PDT 24
Finished Jul 16 07:14:17 PM PDT 24
Peak memory 217264 kb
Host smart-c762dafd-e13b-464d-b4b5-f158fc1c592b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168772382 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.2168772382
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.3310994306
Short name T440
Test name
Test status
Simulation time 20431129 ps
CPU time 1.07 seconds
Started Jul 16 07:14:08 PM PDT 24
Finished Jul 16 07:14:13 PM PDT 24
Peak memory 218752 kb
Host smart-abd8aa32-30bb-42ef-bcc7-476ed10404da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310994306 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.3310994306
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.2525530657
Short name T743
Test name
Test status
Simulation time 90045876 ps
CPU time 1.06 seconds
Started Jul 16 07:14:02 PM PDT 24
Finished Jul 16 07:14:04 PM PDT 24
Peak memory 218664 kb
Host smart-c177571b-1cc7-4dc6-9b63-a37006ec8f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525530657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.2525530657
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.1105747284
Short name T525
Test name
Test status
Simulation time 27918477 ps
CPU time 0.96 seconds
Started Jul 16 07:14:07 PM PDT 24
Finished Jul 16 07:14:12 PM PDT 24
Peak memory 215792 kb
Host smart-cf0c7381-d247-4427-a6d4-b1ab780fac5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105747284 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.1105747284
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.2389845511
Short name T605
Test name
Test status
Simulation time 26208036 ps
CPU time 0.97 seconds
Started Jul 16 07:14:11 PM PDT 24
Finished Jul 16 07:14:17 PM PDT 24
Peak memory 215532 kb
Host smart-805a1870-00fa-4cb8-b3a3-9f998f64a2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389845511 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.2389845511
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.2005780319
Short name T187
Test name
Test status
Simulation time 287079839 ps
CPU time 2.09 seconds
Started Jul 16 07:14:08 PM PDT 24
Finished Jul 16 07:14:14 PM PDT 24
Peak memory 217496 kb
Host smart-29ab0540-6129-4abc-85c7-1c6b078d5724
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005780319 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2005780319
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.3748927193
Short name T880
Test name
Test status
Simulation time 99107875687 ps
CPU time 628.62 seconds
Started Jul 16 07:14:11 PM PDT 24
Finished Jul 16 07:24:45 PM PDT 24
Peak memory 224056 kb
Host smart-df1ccc0b-073b-4085-8530-6cce2528d70e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748927193 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.3748927193
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.3832276534
Short name T816
Test name
Test status
Simulation time 29521249 ps
CPU time 1.14 seconds
Started Jul 16 07:14:05 PM PDT 24
Finished Jul 16 07:14:08 PM PDT 24
Peak memory 218640 kb
Host smart-c8ae531a-12e6-4c49-a20b-10ddfb640da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832276534 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3832276534
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.142381147
Short name T991
Test name
Test status
Simulation time 73667204 ps
CPU time 0.84 seconds
Started Jul 16 07:14:03 PM PDT 24
Finished Jul 16 07:14:05 PM PDT 24
Peak memory 206364 kb
Host smart-cfec4f5a-7446-4640-bdb9-3aa08891532d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142381147 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.142381147
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.3512355021
Short name T197
Test name
Test status
Simulation time 15925785 ps
CPU time 0.85 seconds
Started Jul 16 07:14:06 PM PDT 24
Finished Jul 16 07:14:10 PM PDT 24
Peak memory 216560 kb
Host smart-5e88859f-b247-47ef-850a-a2d8078cfa6f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512355021 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3512355021
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.1506269177
Short name T364
Test name
Test status
Simulation time 66779513 ps
CPU time 1.07 seconds
Started Jul 16 07:14:07 PM PDT 24
Finished Jul 16 07:14:12 PM PDT 24
Peak memory 217032 kb
Host smart-371fb7f6-43da-48ed-8076-075cc3edbbb3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506269177 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.1506269177
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.2030449230
Short name T180
Test name
Test status
Simulation time 21589059 ps
CPU time 1.1 seconds
Started Jul 16 07:14:08 PM PDT 24
Finished Jul 16 07:14:13 PM PDT 24
Peak memory 219900 kb
Host smart-fc75d508-5858-4731-90d4-9617cfd58e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030449230 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.2030449230
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.3403229466
Short name T536
Test name
Test status
Simulation time 46159139 ps
CPU time 1.52 seconds
Started Jul 16 07:14:03 PM PDT 24
Finished Jul 16 07:14:05 PM PDT 24
Peak memory 218828 kb
Host smart-85b50de1-22ca-4b60-80d6-44fb485095a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403229466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.3403229466
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_smoke.2434277040
Short name T964
Test name
Test status
Simulation time 28781715 ps
CPU time 0.96 seconds
Started Jul 16 07:14:04 PM PDT 24
Finished Jul 16 07:14:06 PM PDT 24
Peak memory 215608 kb
Host smart-ffd669f0-eee3-4e82-b7ad-4a36999454f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434277040 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.2434277040
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.313650921
Short name T737
Test name
Test status
Simulation time 214623701 ps
CPU time 2.66 seconds
Started Jul 16 07:14:03 PM PDT 24
Finished Jul 16 07:14:07 PM PDT 24
Peak memory 217644 kb
Host smart-6bd4e461-9724-4448-aa9a-5eeaa97d0dd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313650921 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.313650921
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.2872250018
Short name T828
Test name
Test status
Simulation time 101107006435 ps
CPU time 1827.74 seconds
Started Jul 16 07:14:06 PM PDT 24
Finished Jul 16 07:44:36 PM PDT 24
Peak memory 228160 kb
Host smart-147870de-0cc5-4627-a461-8a6a0d88a0b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872250018 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.2872250018
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.750150526
Short name T735
Test name
Test status
Simulation time 60387627 ps
CPU time 1.09 seconds
Started Jul 16 07:14:08 PM PDT 24
Finished Jul 16 07:14:13 PM PDT 24
Peak memory 220028 kb
Host smart-2380d46b-713e-4e36-9a10-c18a60481d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750150526 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.750150526
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.2960768132
Short name T871
Test name
Test status
Simulation time 12791722 ps
CPU time 0.87 seconds
Started Jul 16 07:14:06 PM PDT 24
Finished Jul 16 07:14:09 PM PDT 24
Peak memory 207268 kb
Host smart-4d064a38-b125-4325-86db-53ff2149c3c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960768132 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2960768132
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.3878682550
Short name T967
Test name
Test status
Simulation time 49604659 ps
CPU time 0.88 seconds
Started Jul 16 07:14:06 PM PDT 24
Finished Jul 16 07:14:11 PM PDT 24
Peak memory 216324 kb
Host smart-4ef5f669-a792-4f9e-a2b6-d93eaa18d931
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878682550 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.3878682550
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.3146746967
Short name T486
Test name
Test status
Simulation time 53015977 ps
CPU time 1.04 seconds
Started Jul 16 07:14:05 PM PDT 24
Finished Jul 16 07:14:07 PM PDT 24
Peak memory 217292 kb
Host smart-f23927da-a3f2-4270-abbc-e6d5c9df316a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146746967 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.3146746967
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.2169631168
Short name T191
Test name
Test status
Simulation time 43876480 ps
CPU time 1.2 seconds
Started Jul 16 07:14:12 PM PDT 24
Finished Jul 16 07:14:18 PM PDT 24
Peak memory 219848 kb
Host smart-75da1950-2202-45ec-8384-c3cdeeca52ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169631168 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2169631168
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.3506154064
Short name T677
Test name
Test status
Simulation time 44622031 ps
CPU time 1.42 seconds
Started Jul 16 07:14:06 PM PDT 24
Finished Jul 16 07:14:10 PM PDT 24
Peak memory 218776 kb
Host smart-22834ba1-db9d-4296-8ed9-4c947da3a303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506154064 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.3506154064
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.1589536798
Short name T756
Test name
Test status
Simulation time 44243047 ps
CPU time 0.88 seconds
Started Jul 16 07:14:05 PM PDT 24
Finished Jul 16 07:14:08 PM PDT 24
Peak memory 215500 kb
Host smart-b87f17dd-dcd1-4ec2-a657-3177e94d4e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589536798 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.1589536798
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.1698532430
Short name T879
Test name
Test status
Simulation time 15612148 ps
CPU time 1 seconds
Started Jul 16 07:14:08 PM PDT 24
Finished Jul 16 07:14:13 PM PDT 24
Peak memory 215580 kb
Host smart-244bfd75-5eaa-41f5-9f7c-81b7cb7b1ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698532430 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.1698532430
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.3196353254
Short name T671
Test name
Test status
Simulation time 191098351 ps
CPU time 2.46 seconds
Started Jul 16 07:14:06 PM PDT 24
Finished Jul 16 07:14:12 PM PDT 24
Peak memory 217480 kb
Host smart-b74c8c26-3275-45bf-824f-15449bfaca6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196353254 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.3196353254
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_alert.1540875197
Short name T644
Test name
Test status
Simulation time 58888835 ps
CPU time 1 seconds
Started Jul 16 07:14:12 PM PDT 24
Finished Jul 16 07:14:18 PM PDT 24
Peak memory 219716 kb
Host smart-94efcc73-dbe1-478a-9830-25a55c79e536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540875197 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.1540875197
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.2572352560
Short name T547
Test name
Test status
Simulation time 25912633 ps
CPU time 1.09 seconds
Started Jul 16 07:14:04 PM PDT 24
Finished Jul 16 07:14:07 PM PDT 24
Peak memory 215204 kb
Host smart-da0f8fc3-eb91-4b3d-b852-55b5c904a651
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572352560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.2572352560
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.1441269093
Short name T621
Test name
Test status
Simulation time 10962377 ps
CPU time 0.89 seconds
Started Jul 16 07:14:05 PM PDT 24
Finished Jul 16 07:14:08 PM PDT 24
Peak memory 216516 kb
Host smart-7af4bcd6-5621-45bd-a059-6c3cfc5ccc86
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441269093 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.1441269093
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.192436446
Short name T203
Test name
Test status
Simulation time 46583648 ps
CPU time 1.14 seconds
Started Jul 16 07:14:04 PM PDT 24
Finished Jul 16 07:14:07 PM PDT 24
Peak memory 217284 kb
Host smart-5c35b0b8-ac67-4c0d-9985-7a006360dcb1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192436446 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_di
sable_auto_req_mode.192436446
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.2790585236
Short name T534
Test name
Test status
Simulation time 21297832 ps
CPU time 1.01 seconds
Started Jul 16 07:14:06 PM PDT 24
Finished Jul 16 07:14:11 PM PDT 24
Peak memory 223956 kb
Host smart-fee03c81-4171-4031-ac05-8047b893d535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790585236 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.2790585236
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.1858322970
Short name T323
Test name
Test status
Simulation time 36415093 ps
CPU time 1.48 seconds
Started Jul 16 07:14:06 PM PDT 24
Finished Jul 16 07:14:12 PM PDT 24
Peak memory 219160 kb
Host smart-3886fb63-a9bc-4419-a656-9e60d39c819f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858322970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.1858322970
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.2023665276
Short name T821
Test name
Test status
Simulation time 20589417 ps
CPU time 1.1 seconds
Started Jul 16 07:14:06 PM PDT 24
Finished Jul 16 07:14:11 PM PDT 24
Peak memory 216060 kb
Host smart-5613f10c-aaeb-4b17-b4df-3456bba9307a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023665276 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.2023665276
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1143295708
Short name T445
Test name
Test status
Simulation time 28835286 ps
CPU time 0.95 seconds
Started Jul 16 07:14:06 PM PDT 24
Finished Jul 16 07:14:09 PM PDT 24
Peak memory 207372 kb
Host smart-f47a7ccd-9a79-4363-ba2c-29547fe3f3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143295708 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1143295708
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.824960039
Short name T539
Test name
Test status
Simulation time 89854668 ps
CPU time 2.28 seconds
Started Jul 16 07:14:04 PM PDT 24
Finished Jul 16 07:14:08 PM PDT 24
Peak memory 217544 kb
Host smart-75976580-847a-4a06-bdf9-1aa520265a75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824960039 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.824960039
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.2451611284
Short name T219
Test name
Test status
Simulation time 173223883640 ps
CPU time 981.4 seconds
Started Jul 16 07:14:11 PM PDT 24
Finished Jul 16 07:30:37 PM PDT 24
Peak memory 221784 kb
Host smart-6a198aca-2332-4cf2-b906-906f1beea6e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451611284 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.2451611284
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2660685840
Short name T111
Test name
Test status
Simulation time 79930356 ps
CPU time 1.25 seconds
Started Jul 16 07:14:06 PM PDT 24
Finished Jul 16 07:14:11 PM PDT 24
Peak memory 219056 kb
Host smart-9d8652b1-ced4-498b-ab84-9da4f430c080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660685840 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2660685840
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.2862907082
Short name T546
Test name
Test status
Simulation time 18997832 ps
CPU time 0.85 seconds
Started Jul 16 07:14:28 PM PDT 24
Finished Jul 16 07:14:51 PM PDT 24
Peak memory 206288 kb
Host smart-732590d4-ff14-4a46-849e-2a6f73dc2041
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862907082 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.2862907082
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.4292472220
Short name T883
Test name
Test status
Simulation time 74108462 ps
CPU time 0.83 seconds
Started Jul 16 07:14:05 PM PDT 24
Finished Jul 16 07:14:07 PM PDT 24
Peak memory 215736 kb
Host smart-70de5f54-a6d3-41a7-84d1-992b81b58f8a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292472220 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.4292472220
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.3672583697
Short name T683
Test name
Test status
Simulation time 79557390 ps
CPU time 1.03 seconds
Started Jul 16 07:14:05 PM PDT 24
Finished Jul 16 07:14:09 PM PDT 24
Peak memory 220016 kb
Host smart-2f2a79c0-aa01-41bc-9594-9d430570d1ac
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672583697 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.3672583697
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.1823884832
Short name T110
Test name
Test status
Simulation time 22218378 ps
CPU time 1.04 seconds
Started Jul 16 07:14:11 PM PDT 24
Finished Jul 16 07:14:17 PM PDT 24
Peak memory 220120 kb
Host smart-f8343f0d-da9a-453b-8827-6c9bbc77eab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823884832 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.1823884832
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.791994052
Short name T384
Test name
Test status
Simulation time 139969580 ps
CPU time 2.85 seconds
Started Jul 16 07:14:06 PM PDT 24
Finished Jul 16 07:14:11 PM PDT 24
Peak memory 219940 kb
Host smart-2b697c79-ea00-478f-b0ab-6872fa3e6678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791994052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.791994052
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.2373871662
Short name T31
Test name
Test status
Simulation time 34664885 ps
CPU time 0.86 seconds
Started Jul 16 07:14:19 PM PDT 24
Finished Jul 16 07:14:26 PM PDT 24
Peak memory 215956 kb
Host smart-e338662a-9647-4e39-a6e5-7d568776db12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373871662 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.2373871662
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.2971505378
Short name T370
Test name
Test status
Simulation time 14840565 ps
CPU time 0.96 seconds
Started Jul 16 07:14:07 PM PDT 24
Finished Jul 16 07:14:12 PM PDT 24
Peak memory 215564 kb
Host smart-c837adbd-19a4-4e7d-b389-3cd9694de4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971505378 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.2971505378
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.3045610569
Short name T761
Test name
Test status
Simulation time 879689097 ps
CPU time 2.76 seconds
Started Jul 16 07:14:06 PM PDT 24
Finished Jul 16 07:14:12 PM PDT 24
Peak memory 217460 kb
Host smart-082bbf72-984f-4808-beb4-79c933b09863
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045610569 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3045610569
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.2916493009
Short name T953
Test name
Test status
Simulation time 185430939515 ps
CPU time 909.27 seconds
Started Jul 16 07:14:19 PM PDT 24
Finished Jul 16 07:29:34 PM PDT 24
Peak memory 223968 kb
Host smart-b80da368-c748-49ec-8172-2f43bcec912a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916493009 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.2916493009
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.4144927926
Short name T851
Test name
Test status
Simulation time 28696054 ps
CPU time 1.15 seconds
Started Jul 16 07:12:02 PM PDT 24
Finished Jul 16 07:13:22 PM PDT 24
Peak memory 218936 kb
Host smart-5cd748dd-077f-4063-a04e-db847c1f147b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144927926 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.4144927926
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.626376426
Short name T707
Test name
Test status
Simulation time 18760314 ps
CPU time 1 seconds
Started Jul 16 07:11:55 PM PDT 24
Finished Jul 16 07:13:18 PM PDT 24
Peak memory 215536 kb
Host smart-621c7b28-ba0b-403d-a7f8-00755dd584f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626376426 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.626376426
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.2095208884
Short name T185
Test name
Test status
Simulation time 17970767 ps
CPU time 0.85 seconds
Started Jul 16 07:11:55 PM PDT 24
Finished Jul 16 07:13:18 PM PDT 24
Peak memory 216524 kb
Host smart-5005fbd0-9685-4a3a-aff9-7e596cea6851
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095208884 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.2095208884
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.544808373
Short name T404
Test name
Test status
Simulation time 50248551 ps
CPU time 1.09 seconds
Started Jul 16 07:11:53 PM PDT 24
Finished Jul 16 07:13:17 PM PDT 24
Peak memory 218756 kb
Host smart-9f8a6c78-2c1c-4d94-8c8a-aa3c7aed4262
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544808373 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_dis
able_auto_req_mode.544808373
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.3065290619
Short name T6
Test name
Test status
Simulation time 20552354 ps
CPU time 1.19 seconds
Started Jul 16 07:11:55 PM PDT 24
Finished Jul 16 07:13:18 PM PDT 24
Peak memory 224144 kb
Host smart-9f432e3f-111b-4a0f-af23-49c4a041cfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065290619 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.3065290619
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.4119667492
Short name T298
Test name
Test status
Simulation time 68678708 ps
CPU time 1.3 seconds
Started Jul 16 07:11:55 PM PDT 24
Finished Jul 16 07:13:18 PM PDT 24
Peak memory 219096 kb
Host smart-efd26a38-902e-4dff-bd8d-eefc2afd4e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119667492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.4119667492
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.320348859
Short name T568
Test name
Test status
Simulation time 31866570 ps
CPU time 1.33 seconds
Started Jul 16 07:11:55 PM PDT 24
Finished Jul 16 07:13:18 PM PDT 24
Peak memory 225468 kb
Host smart-ef310341-6e75-4733-b6e5-554b237dde10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320348859 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.320348859
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.1237313812
Short name T284
Test name
Test status
Simulation time 21301526 ps
CPU time 0.91 seconds
Started Jul 16 07:11:54 PM PDT 24
Finished Jul 16 07:13:17 PM PDT 24
Peak memory 207448 kb
Host smart-e43d9faa-fc0f-4b82-b9a7-9d6bbf0a6ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237313812 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.1237313812
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_smoke.1706614258
Short name T788
Test name
Test status
Simulation time 16336862 ps
CPU time 0.97 seconds
Started Jul 16 07:12:04 PM PDT 24
Finished Jul 16 07:13:24 PM PDT 24
Peak memory 215604 kb
Host smart-4c91ed97-43f8-47b2-bb54-f67411fbf8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706614258 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.1706614258
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.3443652929
Short name T306
Test name
Test status
Simulation time 434464217 ps
CPU time 2.78 seconds
Started Jul 16 07:11:55 PM PDT 24
Finished Jul 16 07:13:20 PM PDT 24
Peak memory 215548 kb
Host smart-8aa9e372-9cc2-4d7f-89a6-8a71148d875e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443652929 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.3443652929
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2971219990
Short name T214
Test name
Test status
Simulation time 47960359146 ps
CPU time 1042.96 seconds
Started Jul 16 07:11:54 PM PDT 24
Finished Jul 16 07:30:39 PM PDT 24
Peak memory 219204 kb
Host smart-2544bcf5-1997-4891-af9d-cbc5361d9d71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971219990 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.2971219990
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.2744796307
Short name T474
Test name
Test status
Simulation time 42936007 ps
CPU time 1.21 seconds
Started Jul 16 07:14:13 PM PDT 24
Finished Jul 16 07:14:19 PM PDT 24
Peak memory 220104 kb
Host smart-86488644-8c72-420b-9ba8-668a5664aca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744796307 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.2744796307
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.3842238779
Short name T601
Test name
Test status
Simulation time 28125158 ps
CPU time 0.96 seconds
Started Jul 16 07:14:12 PM PDT 24
Finished Jul 16 07:14:18 PM PDT 24
Peak memory 207020 kb
Host smart-04c83e10-380b-4428-a9be-a93e5dbbee98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842238779 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3842238779
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.2792001317
Short name T780
Test name
Test status
Simulation time 11040668 ps
CPU time 0.87 seconds
Started Jul 16 07:14:12 PM PDT 24
Finished Jul 16 07:14:18 PM PDT 24
Peak memory 216624 kb
Host smart-3bc4cb91-c15e-4637-9751-c29b472e138f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792001317 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.2792001317
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.3154534940
Short name T698
Test name
Test status
Simulation time 45328222 ps
CPU time 1.57 seconds
Started Jul 16 07:14:10 PM PDT 24
Finished Jul 16 07:14:17 PM PDT 24
Peak memory 217284 kb
Host smart-2fbeee54-ade1-4dbb-99a7-d1abb50da104
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154534940 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.3154534940
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.2890129748
Short name T994
Test name
Test status
Simulation time 53728848 ps
CPU time 1.31 seconds
Started Jul 16 07:14:13 PM PDT 24
Finished Jul 16 07:14:19 PM PDT 24
Peak memory 219980 kb
Host smart-a8095bd8-fb29-479e-87e7-90e0a6916343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890129748 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.2890129748
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.3279655353
Short name T551
Test name
Test status
Simulation time 62381140 ps
CPU time 1.63 seconds
Started Jul 16 07:14:08 PM PDT 24
Finished Jul 16 07:14:13 PM PDT 24
Peak memory 219008 kb
Host smart-b586e673-e1ff-4660-8805-791135687b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279655353 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.3279655353
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.1366905985
Short name T942
Test name
Test status
Simulation time 22011910 ps
CPU time 1.12 seconds
Started Jul 16 07:14:07 PM PDT 24
Finished Jul 16 07:14:12 PM PDT 24
Peak memory 215796 kb
Host smart-17b22f8e-fc6d-4ffe-80cf-bdeb0ecfd572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366905985 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.1366905985
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.3465643608
Short name T617
Test name
Test status
Simulation time 21313538 ps
CPU time 0.93 seconds
Started Jul 16 07:14:12 PM PDT 24
Finished Jul 16 07:14:17 PM PDT 24
Peak memory 215592 kb
Host smart-907d78e9-e3c9-4319-8347-b347b4bdcd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465643608 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.3465643608
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.3120452786
Short name T186
Test name
Test status
Simulation time 572423307 ps
CPU time 5.81 seconds
Started Jul 16 07:14:05 PM PDT 24
Finished Jul 16 07:14:13 PM PDT 24
Peak memory 217576 kb
Host smart-120941dd-d9ee-4d0a-aed1-f8f907d69fd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120452786 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.3120452786
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2867273668
Short name T980
Test name
Test status
Simulation time 204176248259 ps
CPU time 1339.36 seconds
Started Jul 16 07:14:12 PM PDT 24
Finished Jul 16 07:36:37 PM PDT 24
Peak memory 225856 kb
Host smart-8c8cb868-1027-4d49-921e-b63f0ba38057
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867273668 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.2867273668
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.3223892453
Short name T664
Test name
Test status
Simulation time 43805596 ps
CPU time 1.17 seconds
Started Jul 16 07:14:12 PM PDT 24
Finished Jul 16 07:14:18 PM PDT 24
Peak memory 220380 kb
Host smart-f0a22234-9d25-4f08-bb8f-99e3fa430ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223892453 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.3223892453
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.3523124291
Short name T391
Test name
Test status
Simulation time 38495519 ps
CPU time 1.04 seconds
Started Jul 16 07:14:12 PM PDT 24
Finished Jul 16 07:14:17 PM PDT 24
Peak memory 215260 kb
Host smart-257be620-7263-4200-8800-7ad616eb82c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523124291 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.3523124291
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.2472632670
Short name T758
Test name
Test status
Simulation time 20256667 ps
CPU time 0.87 seconds
Started Jul 16 07:14:05 PM PDT 24
Finished Jul 16 07:14:07 PM PDT 24
Peak memory 216608 kb
Host smart-9acc168d-7ea6-4a87-b35c-6eea606a0a6d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472632670 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2472632670
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.818033012
Short name T857
Test name
Test status
Simulation time 70755257 ps
CPU time 0.95 seconds
Started Jul 16 07:14:07 PM PDT 24
Finished Jul 16 07:14:12 PM PDT 24
Peak memory 218524 kb
Host smart-ed22709b-b287-45ca-b2cb-dc1cd8fb3821
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818033012 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_di
sable_auto_req_mode.818033012
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.1288523567
Short name T195
Test name
Test status
Simulation time 54473544 ps
CPU time 1.2 seconds
Started Jul 16 07:14:14 PM PDT 24
Finished Jul 16 07:14:21 PM PDT 24
Peak memory 225952 kb
Host smart-380db88b-4858-43be-9977-94232321bb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288523567 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.1288523567
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.3952471929
Short name T691
Test name
Test status
Simulation time 41733178 ps
CPU time 1.44 seconds
Started Jul 16 07:14:10 PM PDT 24
Finished Jul 16 07:14:17 PM PDT 24
Peak memory 218988 kb
Host smart-4c32b7d7-9963-4148-bb20-41e5cc62f55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952471929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.3952471929
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.878949787
Short name T495
Test name
Test status
Simulation time 51630942 ps
CPU time 0.87 seconds
Started Jul 16 07:14:10 PM PDT 24
Finished Jul 16 07:14:16 PM PDT 24
Peak memory 215552 kb
Host smart-5335d045-55c0-4462-b260-2a0989ee8441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878949787 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.878949787
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.549885552
Short name T414
Test name
Test status
Simulation time 17344046 ps
CPU time 0.99 seconds
Started Jul 16 07:14:07 PM PDT 24
Finished Jul 16 07:14:11 PM PDT 24
Peak memory 215620 kb
Host smart-4a08cf57-837a-4c9f-a7d1-d3dad5a74d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549885552 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.549885552
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.646926192
Short name T678
Test name
Test status
Simulation time 57416948 ps
CPU time 1.65 seconds
Started Jul 16 07:14:10 PM PDT 24
Finished Jul 16 07:14:17 PM PDT 24
Peak memory 207484 kb
Host smart-00dabeec-c562-475d-bf94-52f57d08f0d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646926192 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.646926192
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1733342749
Short name T479
Test name
Test status
Simulation time 144233298337 ps
CPU time 409.74 seconds
Started Jul 16 07:14:10 PM PDT 24
Finished Jul 16 07:21:05 PM PDT 24
Peak memory 219396 kb
Host smart-a218a963-9e0c-411f-8d03-a49c78c8f20e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733342749 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.1733342749
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.3512622748
Short name T156
Test name
Test status
Simulation time 85853038 ps
CPU time 1.13 seconds
Started Jul 16 07:14:10 PM PDT 24
Finished Jul 16 07:14:16 PM PDT 24
Peak memory 219152 kb
Host smart-8ec754c4-b1c1-4273-9281-003067a0c3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512622748 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.3512622748
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.2660931100
Short name T841
Test name
Test status
Simulation time 50377800 ps
CPU time 0.89 seconds
Started Jul 16 07:14:19 PM PDT 24
Finished Jul 16 07:14:26 PM PDT 24
Peak memory 215168 kb
Host smart-7238eccf-1d3c-44dd-8fdf-8ff8e3af2f79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660931100 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2660931100
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.2160601880
Short name T152
Test name
Test status
Simulation time 152539095 ps
CPU time 0.9 seconds
Started Jul 16 07:14:11 PM PDT 24
Finished Jul 16 07:14:16 PM PDT 24
Peak memory 216560 kb
Host smart-4d277fb9-903f-4c8d-bcf2-7b7e9026d3d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160601880 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.2160601880
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.3832047455
Short name T115
Test name
Test status
Simulation time 55624759 ps
CPU time 1.06 seconds
Started Jul 16 07:14:20 PM PDT 24
Finished Jul 16 07:14:29 PM PDT 24
Peak memory 218892 kb
Host smart-1b231086-c67a-40e2-a7c8-17f986675af5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832047455 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.3832047455
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.2699622547
Short name T51
Test name
Test status
Simulation time 20106948 ps
CPU time 1.22 seconds
Started Jul 16 07:14:10 PM PDT 24
Finished Jul 16 07:14:17 PM PDT 24
Peak memory 229836 kb
Host smart-5dc24802-1ffd-4b55-b125-b48d00bc8e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699622547 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.2699622547
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.1418088491
Short name T822
Test name
Test status
Simulation time 69208277 ps
CPU time 1.22 seconds
Started Jul 16 07:14:08 PM PDT 24
Finished Jul 16 07:14:13 PM PDT 24
Peak memory 219056 kb
Host smart-6e75ca96-2505-4ec3-b8c6-1e1691ae5646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418088491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.1418088491
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.2994358195
Short name T50
Test name
Test status
Simulation time 20591758 ps
CPU time 1.22 seconds
Started Jul 16 07:14:08 PM PDT 24
Finished Jul 16 07:14:14 PM PDT 24
Peak memory 224320 kb
Host smart-a8b02957-9e55-4e65-9f06-f49e79e2d161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994358195 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.2994358195
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.2843025756
Short name T566
Test name
Test status
Simulation time 53758082 ps
CPU time 0.93 seconds
Started Jul 16 07:14:09 PM PDT 24
Finished Jul 16 07:14:15 PM PDT 24
Peak memory 215784 kb
Host smart-20bfadaf-d3b3-4e37-ae41-ff95357e208f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843025756 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.2843025756
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.673400517
Short name T543
Test name
Test status
Simulation time 1022323825 ps
CPU time 5.73 seconds
Started Jul 16 07:14:11 PM PDT 24
Finished Jul 16 07:14:21 PM PDT 24
Peak memory 215616 kb
Host smart-a4818458-83b2-4b14-834c-3e4248890182
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673400517 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.673400517
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.3611416618
Short name T417
Test name
Test status
Simulation time 75747772299 ps
CPU time 1863.48 seconds
Started Jul 16 07:14:10 PM PDT 24
Finished Jul 16 07:45:19 PM PDT 24
Peak memory 228528 kb
Host smart-3cf6c68e-0e01-4b72-8a1b-6fcc1e070055
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611416618 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.3611416618
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.805505884
Short name T887
Test name
Test status
Simulation time 40265730 ps
CPU time 1.21 seconds
Started Jul 16 07:14:23 PM PDT 24
Finished Jul 16 07:14:36 PM PDT 24
Peak memory 220064 kb
Host smart-b2e44a39-6ddf-42f9-94f9-ef8636774171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805505884 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.805505884
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.176703982
Short name T335
Test name
Test status
Simulation time 63639292 ps
CPU time 0.9 seconds
Started Jul 16 07:14:18 PM PDT 24
Finished Jul 16 07:14:25 PM PDT 24
Peak memory 215508 kb
Host smart-c5093f81-d2da-4813-99b4-85070b1e123f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176703982 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.176703982
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.1521934149
Short name T902
Test name
Test status
Simulation time 29433121 ps
CPU time 0.88 seconds
Started Jul 16 07:14:17 PM PDT 24
Finished Jul 16 07:14:24 PM PDT 24
Peak memory 216536 kb
Host smart-f5ebde46-b03b-425d-a2a1-aef961321e8f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521934149 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.1521934149
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.2882569622
Short name T513
Test name
Test status
Simulation time 46512679 ps
CPU time 1.1 seconds
Started Jul 16 07:14:14 PM PDT 24
Finished Jul 16 07:14:20 PM PDT 24
Peak memory 217212 kb
Host smart-ce39f5c2-ef0c-4b41-8a6d-4d6d8f0e5265
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882569622 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.2882569622
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.2698946583
Short name T92
Test name
Test status
Simulation time 26105441 ps
CPU time 1.18 seconds
Started Jul 16 07:14:17 PM PDT 24
Finished Jul 16 07:14:24 PM PDT 24
Peak memory 220944 kb
Host smart-8e2d1ab0-395a-41f0-a6a4-db0a44f1d969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698946583 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.2698946583
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.3735877800
Short name T74
Test name
Test status
Simulation time 68336718 ps
CPU time 1.43 seconds
Started Jul 16 07:14:22 PM PDT 24
Finished Jul 16 07:14:33 PM PDT 24
Peak memory 219008 kb
Host smart-1af1f865-de45-4c9c-9be8-dfcce48cb867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735877800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.3735877800
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.2943214550
Short name T889
Test name
Test status
Simulation time 22384966 ps
CPU time 1.17 seconds
Started Jul 16 07:14:24 PM PDT 24
Finished Jul 16 07:14:39 PM PDT 24
Peak memory 224396 kb
Host smart-2cb4bac1-8028-41b6-bccb-be71fb8d54bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943214550 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.2943214550
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.624864785
Short name T978
Test name
Test status
Simulation time 58104042 ps
CPU time 0.91 seconds
Started Jul 16 07:14:20 PM PDT 24
Finished Jul 16 07:14:28 PM PDT 24
Peak memory 215500 kb
Host smart-4286dbe2-dbf6-4cda-9e6b-6783f456579b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624864785 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.624864785
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.2472071059
Short name T680
Test name
Test status
Simulation time 788227285 ps
CPU time 4.44 seconds
Started Jul 16 07:14:17 PM PDT 24
Finished Jul 16 07:14:27 PM PDT 24
Peak memory 217808 kb
Host smart-3e23773c-8f68-4f04-a297-279597b30df1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472071059 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.2472071059
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.1255552265
Short name T783
Test name
Test status
Simulation time 103818690750 ps
CPU time 1156.84 seconds
Started Jul 16 07:14:21 PM PDT 24
Finished Jul 16 07:33:45 PM PDT 24
Peak memory 224148 kb
Host smart-6ba5b764-0c4c-4c1c-839f-848eadbcce95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255552265 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.1255552265
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.2699596401
Short name T425
Test name
Test status
Simulation time 80023839 ps
CPU time 1.18 seconds
Started Jul 16 07:14:15 PM PDT 24
Finished Jul 16 07:14:22 PM PDT 24
Peak memory 221028 kb
Host smart-4f1c2ae2-3ab9-4610-9c46-80b7cc940a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699596401 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.2699596401
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.1575759757
Short name T459
Test name
Test status
Simulation time 20264340 ps
CPU time 0.84 seconds
Started Jul 16 07:14:20 PM PDT 24
Finished Jul 16 07:14:28 PM PDT 24
Peak memory 206676 kb
Host smart-8c350055-971b-426c-865c-b1e426df6bc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575759757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.1575759757
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.726232382
Short name T153
Test name
Test status
Simulation time 49323070 ps
CPU time 0.86 seconds
Started Jul 16 07:14:21 PM PDT 24
Finished Jul 16 07:14:31 PM PDT 24
Peak memory 216548 kb
Host smart-78377172-92bd-417a-830e-18826dfc61e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726232382 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.726232382
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.2785815723
Short name T499
Test name
Test status
Simulation time 84356487 ps
CPU time 1.14 seconds
Started Jul 16 07:14:21 PM PDT 24
Finished Jul 16 07:14:31 PM PDT 24
Peak memory 216996 kb
Host smart-7c4a3810-e305-48a7-86f2-fb1b2124c0f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785815723 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.2785815723
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.3078233598
Short name T204
Test name
Test status
Simulation time 73400507 ps
CPU time 1.15 seconds
Started Jul 16 07:14:23 PM PDT 24
Finished Jul 16 07:14:36 PM PDT 24
Peak memory 226004 kb
Host smart-53205ca0-374f-44ca-a92d-f437e3352732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078233598 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.3078233598
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.3166276311
Short name T484
Test name
Test status
Simulation time 112257419 ps
CPU time 1.57 seconds
Started Jul 16 07:14:16 PM PDT 24
Finished Jul 16 07:14:23 PM PDT 24
Peak memory 218976 kb
Host smart-036bf366-44c8-4171-9a68-bf363e32df94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166276311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.3166276311
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.2257934890
Short name T46
Test name
Test status
Simulation time 43185147 ps
CPU time 0.91 seconds
Started Jul 16 07:14:17 PM PDT 24
Finished Jul 16 07:14:24 PM PDT 24
Peak memory 215688 kb
Host smart-a2b0ab3c-9ca3-49de-877b-67c49ba4085b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257934890 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.2257934890
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.3938553268
Short name T564
Test name
Test status
Simulation time 23040187 ps
CPU time 0.91 seconds
Started Jul 16 07:14:23 PM PDT 24
Finished Jul 16 07:14:35 PM PDT 24
Peak memory 215568 kb
Host smart-22e65e8c-43f2-4076-8a86-6e44c8213f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938553268 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.3938553268
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.2516288019
Short name T659
Test name
Test status
Simulation time 588669139 ps
CPU time 3.25 seconds
Started Jul 16 07:14:24 PM PDT 24
Finished Jul 16 07:14:41 PM PDT 24
Peak memory 217480 kb
Host smart-8d66fc23-5321-468f-98e6-ff152b381431
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516288019 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.2516288019
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.710523276
Short name T432
Test name
Test status
Simulation time 125080630823 ps
CPU time 578.76 seconds
Started Jul 16 07:14:14 PM PDT 24
Finished Jul 16 07:23:58 PM PDT 24
Peak memory 224088 kb
Host smart-a8d5f873-7549-4877-a31f-93b86eff2f50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710523276 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.710523276
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.1900112676
Short name T723
Test name
Test status
Simulation time 72436773 ps
CPU time 1.11 seconds
Started Jul 16 07:14:17 PM PDT 24
Finished Jul 16 07:14:24 PM PDT 24
Peak memory 220216 kb
Host smart-1a2332cc-a93e-4bb7-82f0-037217da1125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900112676 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.1900112676
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.3410997662
Short name T831
Test name
Test status
Simulation time 53665382 ps
CPU time 0.88 seconds
Started Jul 16 07:14:25 PM PDT 24
Finished Jul 16 07:14:42 PM PDT 24
Peak memory 215444 kb
Host smart-2669ed14-afdf-43e1-a2a0-5aa180e6f3d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410997662 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3410997662
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.2102172985
Short name T151
Test name
Test status
Simulation time 24092691 ps
CPU time 0.86 seconds
Started Jul 16 07:14:22 PM PDT 24
Finished Jul 16 07:14:34 PM PDT 24
Peak memory 216528 kb
Host smart-c5cbe58f-7a2c-41c9-855c-f6e691adbab8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102172985 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2102172985
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.4263164789
Short name T826
Test name
Test status
Simulation time 71514322 ps
CPU time 1.05 seconds
Started Jul 16 07:14:20 PM PDT 24
Finished Jul 16 07:14:29 PM PDT 24
Peak memory 217268 kb
Host smart-9594a0ed-18df-44dc-bdda-75231e7bbede
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263164789 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.4263164789
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.1768039411
Short name T960
Test name
Test status
Simulation time 26718342 ps
CPU time 0.89 seconds
Started Jul 16 07:14:17 PM PDT 24
Finished Jul 16 07:14:24 PM PDT 24
Peak memory 218448 kb
Host smart-12351b31-fab8-49ec-adaf-a70c7f97bd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768039411 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1768039411
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.696755585
Short name T948
Test name
Test status
Simulation time 54362594 ps
CPU time 1.38 seconds
Started Jul 16 07:14:18 PM PDT 24
Finished Jul 16 07:14:26 PM PDT 24
Peak memory 216968 kb
Host smart-4e287d84-e6e3-4dfb-9926-3ea24fda814a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696755585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.696755585
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.1458623882
Short name T347
Test name
Test status
Simulation time 28624052 ps
CPU time 1.06 seconds
Started Jul 16 07:14:20 PM PDT 24
Finished Jul 16 07:14:29 PM PDT 24
Peak memory 224232 kb
Host smart-c0425957-d89b-4777-8e1d-1a296d4458ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458623882 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.1458623882
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.4249717483
Short name T915
Test name
Test status
Simulation time 18069294 ps
CPU time 1.02 seconds
Started Jul 16 07:14:18 PM PDT 24
Finished Jul 16 07:14:25 PM PDT 24
Peak memory 215612 kb
Host smart-15eb20b6-0c0f-48d1-9c2f-d009b8b90c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249717483 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.4249717483
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1074454191
Short name T694
Test name
Test status
Simulation time 134069434 ps
CPU time 1.32 seconds
Started Jul 16 07:14:19 PM PDT 24
Finished Jul 16 07:14:51 PM PDT 24
Peak memory 217732 kb
Host smart-18d9ec3c-bbd3-4846-8850-4417f56675da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074454191 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1074454191
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.902671476
Short name T221
Test name
Test status
Simulation time 126875108386 ps
CPU time 2872.12 seconds
Started Jul 16 07:14:21 PM PDT 24
Finished Jul 16 08:02:21 PM PDT 24
Peak memory 230376 kb
Host smart-07c6bf90-fd73-4fe0-b7a5-1a607d9004af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902671476 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.902671476
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.1643937602
Short name T946
Test name
Test status
Simulation time 25859357 ps
CPU time 1.18 seconds
Started Jul 16 07:14:23 PM PDT 24
Finished Jul 16 07:14:37 PM PDT 24
Peak memory 219972 kb
Host smart-6b8c6e2b-008d-4d02-98cf-ea19e8d6c59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643937602 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.1643937602
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.3648252518
Short name T593
Test name
Test status
Simulation time 94885774 ps
CPU time 0.93 seconds
Started Jul 16 07:14:24 PM PDT 24
Finished Jul 16 07:14:39 PM PDT 24
Peak memory 215144 kb
Host smart-52948305-b995-42b1-bba4-fea4570aa987
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648252518 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.3648252518
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.267570881
Short name T161
Test name
Test status
Simulation time 128091065 ps
CPU time 0.81 seconds
Started Jul 16 07:14:22 PM PDT 24
Finished Jul 16 07:14:31 PM PDT 24
Peak memory 216476 kb
Host smart-3324cafc-8081-491f-8d73-bf0abeea6764
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267570881 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.267570881
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.2003747973
Short name T736
Test name
Test status
Simulation time 65793822 ps
CPU time 1.22 seconds
Started Jul 16 07:14:20 PM PDT 24
Finished Jul 16 07:14:28 PM PDT 24
Peak memory 217108 kb
Host smart-31d8e8f1-471e-41b2-89d7-54ff5c7370e0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003747973 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.2003747973
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.184592631
Short name T754
Test name
Test status
Simulation time 68441885 ps
CPU time 0.99 seconds
Started Jul 16 07:14:25 PM PDT 24
Finished Jul 16 07:14:42 PM PDT 24
Peak memory 219248 kb
Host smart-8fbcf715-8463-4df6-bcef-e488db1267ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184592631 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.184592631
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.3460255447
Short name T367
Test name
Test status
Simulation time 50976343 ps
CPU time 1.13 seconds
Started Jul 16 07:14:21 PM PDT 24
Finished Jul 16 07:14:31 PM PDT 24
Peak memory 217460 kb
Host smart-14c61f68-dd7d-425c-a230-6c9b60120adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460255447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.3460255447
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.2218421834
Short name T489
Test name
Test status
Simulation time 35911821 ps
CPU time 0.94 seconds
Started Jul 16 07:14:24 PM PDT 24
Finished Jul 16 07:14:39 PM PDT 24
Peak memory 215672 kb
Host smart-a7ef6e1f-e67d-4bb8-8445-b566f5e57b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218421834 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.2218421834
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.1686686243
Short name T53
Test name
Test status
Simulation time 26479959 ps
CPU time 0.91 seconds
Started Jul 16 07:14:16 PM PDT 24
Finished Jul 16 07:14:23 PM PDT 24
Peak memory 215560 kb
Host smart-bf4ce4d5-5cee-413f-acac-c84f097365fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686686243 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.1686686243
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.672925741
Short name T485
Test name
Test status
Simulation time 204461466 ps
CPU time 3.94 seconds
Started Jul 16 07:14:22 PM PDT 24
Finished Jul 16 07:14:37 PM PDT 24
Peak memory 217352 kb
Host smart-21442022-1f0f-423b-8e67-d6c7a77da427
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672925741 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.672925741
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.4251297774
Short name T215
Test name
Test status
Simulation time 105000982158 ps
CPU time 1373.05 seconds
Started Jul 16 07:14:18 PM PDT 24
Finished Jul 16 07:37:18 PM PDT 24
Peak memory 224344 kb
Host smart-b876c2bc-8472-4fce-a647-90959d536647
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251297774 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.4251297774
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.2931946570
Short name T378
Test name
Test status
Simulation time 85784745 ps
CPU time 1.21 seconds
Started Jul 16 07:14:22 PM PDT 24
Finished Jul 16 07:14:35 PM PDT 24
Peak memory 219508 kb
Host smart-e73a60ce-e1fd-46d1-b261-381c2bf0a9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931946570 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2931946570
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.171689433
Short name T626
Test name
Test status
Simulation time 24438793 ps
CPU time 0.87 seconds
Started Jul 16 07:14:23 PM PDT 24
Finished Jul 16 07:14:35 PM PDT 24
Peak memory 215128 kb
Host smart-b9cc065c-0feb-4014-86a7-233b4ee756a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171689433 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.171689433
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.300184513
Short name T138
Test name
Test status
Simulation time 22617259 ps
CPU time 0.88 seconds
Started Jul 16 07:14:22 PM PDT 24
Finished Jul 16 07:14:34 PM PDT 24
Peak memory 215652 kb
Host smart-0e740e0e-c72a-40b4-8181-e811a6e65a64
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300184513 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.300184513
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1558929746
Short name T400
Test name
Test status
Simulation time 26852270 ps
CPU time 1.04 seconds
Started Jul 16 07:14:23 PM PDT 24
Finished Jul 16 07:14:37 PM PDT 24
Peak memory 218680 kb
Host smart-a708d07f-f4e7-4605-8f3d-afec02c286ef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558929746 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1558929746
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.2388441113
Short name T969
Test name
Test status
Simulation time 28385008 ps
CPU time 0.85 seconds
Started Jul 16 07:14:20 PM PDT 24
Finished Jul 16 07:14:28 PM PDT 24
Peak memory 218496 kb
Host smart-697d0505-72f8-466f-b1f9-405ca1bf9f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388441113 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.2388441113
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.876569839
Short name T843
Test name
Test status
Simulation time 42959222 ps
CPU time 1.25 seconds
Started Jul 16 07:14:23 PM PDT 24
Finished Jul 16 07:14:36 PM PDT 24
Peak memory 217628 kb
Host smart-9eeec170-a77e-40de-adfc-0425719f80c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876569839 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.876569839
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.3923152741
Short name T697
Test name
Test status
Simulation time 24822763 ps
CPU time 1.05 seconds
Started Jul 16 07:14:15 PM PDT 24
Finished Jul 16 07:14:22 PM PDT 24
Peak memory 215748 kb
Host smart-6dbecae7-9794-46f3-ae61-b22a871d6058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923152741 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.3923152741
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.2237451388
Short name T687
Test name
Test status
Simulation time 16037102 ps
CPU time 0.97 seconds
Started Jul 16 07:14:19 PM PDT 24
Finished Jul 16 07:14:27 PM PDT 24
Peak memory 215564 kb
Host smart-e6b551cd-af87-4728-9a72-f913c8a9342b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237451388 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.2237451388
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.2523833020
Short name T229
Test name
Test status
Simulation time 222982275 ps
CPU time 4.39 seconds
Started Jul 16 07:14:24 PM PDT 24
Finished Jul 16 07:14:44 PM PDT 24
Peak memory 218848 kb
Host smart-19d706fd-dd5c-4bbb-b4d3-2232ec15e2d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523833020 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.2523833020
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3659673816
Short name T930
Test name
Test status
Simulation time 88120493392 ps
CPU time 963.63 seconds
Started Jul 16 07:14:18 PM PDT 24
Finished Jul 16 07:30:28 PM PDT 24
Peak memory 222924 kb
Host smart-b56e8bbf-b0dc-4d20-bddd-ea77730a4de1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659673816 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3659673816
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.2564986449
Short name T164
Test name
Test status
Simulation time 176344986 ps
CPU time 1.16 seconds
Started Jul 16 07:14:23 PM PDT 24
Finished Jul 16 07:14:36 PM PDT 24
Peak memory 219792 kb
Host smart-828fffbd-d02c-4df7-b4f9-cbadc14d71ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564986449 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.2564986449
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.1858126708
Short name T58
Test name
Test status
Simulation time 26488892 ps
CPU time 1.03 seconds
Started Jul 16 07:14:26 PM PDT 24
Finished Jul 16 07:14:44 PM PDT 24
Peak memory 215532 kb
Host smart-331c90d5-9c9f-43ce-be6c-847ec58a072e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858126708 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1858126708
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.2924418105
Short name T765
Test name
Test status
Simulation time 16828935 ps
CPU time 0.8 seconds
Started Jul 16 07:14:24 PM PDT 24
Finished Jul 16 07:14:39 PM PDT 24
Peak memory 216256 kb
Host smart-ecc6427c-8a1e-4227-807a-a49ca139ecca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924418105 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.2924418105
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.1473330284
Short name T100
Test name
Test status
Simulation time 51834740 ps
CPU time 1.4 seconds
Started Jul 16 07:14:18 PM PDT 24
Finished Jul 16 07:14:25 PM PDT 24
Peak memory 217072 kb
Host smart-ce99f901-f5d9-45d3-a33c-b5f49af7ddf3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473330284 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.1473330284
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.3652705620
Short name T142
Test name
Test status
Simulation time 53665656 ps
CPU time 1.16 seconds
Started Jul 16 07:14:19 PM PDT 24
Finished Jul 16 07:14:28 PM PDT 24
Peak memory 224268 kb
Host smart-4ff4cb2f-1772-4ef8-929e-35cd6ae1dce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652705620 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3652705620
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.3449117955
Short name T908
Test name
Test status
Simulation time 34498341 ps
CPU time 1.31 seconds
Started Jul 16 07:14:19 PM PDT 24
Finished Jul 16 07:14:27 PM PDT 24
Peak memory 220272 kb
Host smart-0a153386-0868-48b1-876a-3dba74250311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449117955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3449117955
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.1049279821
Short name T464
Test name
Test status
Simulation time 77329734 ps
CPU time 0.9 seconds
Started Jul 16 07:14:18 PM PDT 24
Finished Jul 16 07:14:25 PM PDT 24
Peak memory 215568 kb
Host smart-ccbef37d-0267-4252-a011-3d5eab1dee55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049279821 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.1049279821
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.3150840630
Short name T809
Test name
Test status
Simulation time 16095042 ps
CPU time 0.97 seconds
Started Jul 16 07:14:24 PM PDT 24
Finished Jul 16 07:14:39 PM PDT 24
Peak memory 215568 kb
Host smart-39aac5a2-fdef-4848-b4bb-725a693b4054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150840630 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.3150840630
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.2752420032
Short name T225
Test name
Test status
Simulation time 277362198 ps
CPU time 5.22 seconds
Started Jul 16 07:14:19 PM PDT 24
Finished Jul 16 07:14:30 PM PDT 24
Peak memory 219788 kb
Host smart-c41b9c41-47f2-4098-8469-863dd3173112
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752420032 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.2752420032
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.3939543377
Short name T224
Test name
Test status
Simulation time 105956149117 ps
CPU time 1153.6 seconds
Started Jul 16 07:14:15 PM PDT 24
Finished Jul 16 07:33:34 PM PDT 24
Peak memory 223488 kb
Host smart-8a3d454c-6ba5-44aa-892d-7a948e842020
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939543377 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.3939543377
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.1989945028
Short name T128
Test name
Test status
Simulation time 66222553 ps
CPU time 1.22 seconds
Started Jul 16 07:14:24 PM PDT 24
Finished Jul 16 07:14:39 PM PDT 24
Peak memory 220396 kb
Host smart-71f514b5-6c95-4c25-a95f-8e4991460ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989945028 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.1989945028
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.3311308859
Short name T827
Test name
Test status
Simulation time 36488180 ps
CPU time 0.81 seconds
Started Jul 16 07:14:19 PM PDT 24
Finished Jul 16 07:14:26 PM PDT 24
Peak memory 206712 kb
Host smart-2d091831-b27c-494d-86d1-bb98ac5d9047
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311308859 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.3311308859
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.3722078941
Short name T192
Test name
Test status
Simulation time 27723548 ps
CPU time 0.82 seconds
Started Jul 16 07:14:21 PM PDT 24
Finished Jul 16 07:14:31 PM PDT 24
Peak memory 216476 kb
Host smart-838e3e4b-b239-4051-b538-63bc3f7125fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722078941 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.3722078941
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.1603566020
Short name T840
Test name
Test status
Simulation time 74486474 ps
CPU time 1.22 seconds
Started Jul 16 07:14:29 PM PDT 24
Finished Jul 16 07:14:51 PM PDT 24
Peak memory 217068 kb
Host smart-f4e5df02-e586-4c13-9cfb-f6bdb637eb43
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603566020 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.1603566020
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.3884086773
Short name T763
Test name
Test status
Simulation time 41592074 ps
CPU time 1.22 seconds
Started Jul 16 07:14:20 PM PDT 24
Finished Jul 16 07:14:30 PM PDT 24
Peak memory 225772 kb
Host smart-a10054bf-b00c-458a-9cbb-1870c954ff6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884086773 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3884086773
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.3852522446
Short name T640
Test name
Test status
Simulation time 40421243 ps
CPU time 1.86 seconds
Started Jul 16 07:14:26 PM PDT 24
Finished Jul 16 07:14:45 PM PDT 24
Peak memory 217912 kb
Host smart-f63f8944-2c3b-4595-afa7-e8d058efa0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852522446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3852522446
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.2971008690
Short name T757
Test name
Test status
Simulation time 36920253 ps
CPU time 1.09 seconds
Started Jul 16 07:14:26 PM PDT 24
Finished Jul 16 07:14:44 PM PDT 24
Peak memory 224476 kb
Host smart-587d280f-8255-4936-82de-418f1a45a0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971008690 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.2971008690
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.3394030174
Short name T836
Test name
Test status
Simulation time 98330688 ps
CPU time 0.91 seconds
Started Jul 16 07:14:26 PM PDT 24
Finished Jul 16 07:14:44 PM PDT 24
Peak memory 215728 kb
Host smart-c1807c6b-90f6-4ab4-ab95-7fb5a63eae72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394030174 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.3394030174
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.4439779
Short name T751
Test name
Test status
Simulation time 60076473 ps
CPU time 1.87 seconds
Started Jul 16 07:14:26 PM PDT 24
Finished Jul 16 07:14:45 PM PDT 24
Peak memory 215688 kb
Host smart-dfdb58f9-3980-4a07-86ec-f15c81d74555
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4439779 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.4439779
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.463629037
Short name T544
Test name
Test status
Simulation time 71544091359 ps
CPU time 1837.88 seconds
Started Jul 16 07:14:24 PM PDT 24
Finished Jul 16 07:45:16 PM PDT 24
Peak memory 228280 kb
Host smart-7ca80752-b860-42ec-8e13-d59ca22894d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463629037 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.463629037
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.312361448
Short name T898
Test name
Test status
Simulation time 112208904 ps
CPU time 1.31 seconds
Started Jul 16 07:11:56 PM PDT 24
Finished Jul 16 07:13:18 PM PDT 24
Peak memory 218796 kb
Host smart-0b1ef861-9990-4474-85b7-044a0daab55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312361448 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.312361448
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.2189982076
Short name T481
Test name
Test status
Simulation time 20884437 ps
CPU time 0.86 seconds
Started Jul 16 07:11:54 PM PDT 24
Finished Jul 16 07:13:17 PM PDT 24
Peak memory 215376 kb
Host smart-46dbd1a7-c708-4424-9e10-e04de393a520
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189982076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2189982076
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.2528579151
Short name T212
Test name
Test status
Simulation time 14895583 ps
CPU time 0.86 seconds
Started Jul 16 07:11:52 PM PDT 24
Finished Jul 16 07:13:18 PM PDT 24
Peak memory 216456 kb
Host smart-027387e4-1d9d-4ef4-8fb9-4f8aeffc71c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528579151 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.2528579151
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.1455196596
Short name T734
Test name
Test status
Simulation time 59133091 ps
CPU time 1.18 seconds
Started Jul 16 07:11:55 PM PDT 24
Finished Jul 16 07:13:18 PM PDT 24
Peak memory 218592 kb
Host smart-f5d50a61-7859-4963-91be-2df6b9f8d0cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455196596 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.1455196596
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.4091298537
Short name T963
Test name
Test status
Simulation time 21905124 ps
CPU time 0.88 seconds
Started Jul 16 07:11:53 PM PDT 24
Finished Jul 16 07:13:17 PM PDT 24
Peak memory 218336 kb
Host smart-44bd3374-f4af-42d1-bc86-1a3c1f8de328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091298537 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.4091298537
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.3360647729
Short name T42
Test name
Test status
Simulation time 39763557 ps
CPU time 1.33 seconds
Started Jul 16 07:11:55 PM PDT 24
Finished Jul 16 07:13:18 PM PDT 24
Peak memory 217576 kb
Host smart-1553fe79-4c39-4160-9c54-7ef8d9f3507c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360647729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.3360647729
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.3158015168
Short name T684
Test name
Test status
Simulation time 39319251 ps
CPU time 0.86 seconds
Started Jul 16 07:11:55 PM PDT 24
Finished Jul 16 07:13:18 PM PDT 24
Peak memory 215752 kb
Host smart-15083ca4-5a33-411e-831c-b6d51953f397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158015168 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.3158015168
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.3673471911
Short name T26
Test name
Test status
Simulation time 15136374 ps
CPU time 0.98 seconds
Started Jul 16 07:11:56 PM PDT 24
Finished Jul 16 07:13:18 PM PDT 24
Peak memory 207380 kb
Host smart-dabdb43f-a794-4864-bba9-3156a89ed93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673471911 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.3673471911
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.1062704417
Short name T488
Test name
Test status
Simulation time 47538209 ps
CPU time 0.85 seconds
Started Jul 16 07:11:53 PM PDT 24
Finished Jul 16 07:13:17 PM PDT 24
Peak memory 215528 kb
Host smart-87eeef80-fd6c-4366-bb4c-549212965932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062704417 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.1062704417
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.3145606534
Short name T738
Test name
Test status
Simulation time 81870348 ps
CPU time 2.07 seconds
Started Jul 16 07:11:54 PM PDT 24
Finished Jul 16 07:13:18 PM PDT 24
Peak memory 215544 kb
Host smart-64fc1c80-3ad0-453d-995f-3782e24960d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145606534 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.3145606534
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.2354051435
Short name T218
Test name
Test status
Simulation time 86504792590 ps
CPU time 977.52 seconds
Started Jul 16 07:11:52 PM PDT 24
Finished Jul 16 07:29:35 PM PDT 24
Peak memory 221760 kb
Host smart-bebffaf2-9a78-4c71-ba8f-58ad298a7c01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354051435 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.2354051435
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.1431583146
Short name T68
Test name
Test status
Simulation time 49891255 ps
CPU time 1.17 seconds
Started Jul 16 07:14:22 PM PDT 24
Finished Jul 16 07:14:35 PM PDT 24
Peak memory 219016 kb
Host smart-0aa7542b-aff6-4a82-b35c-d0bf95ef01f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431583146 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.1431583146
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.439156373
Short name T381
Test name
Test status
Simulation time 19915171 ps
CPU time 1.03 seconds
Started Jul 16 07:14:18 PM PDT 24
Finished Jul 16 07:14:26 PM PDT 24
Peak memory 218536 kb
Host smart-1fc98726-8327-415c-98f2-3a54b88b8891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439156373 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.439156373
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.1618623221
Short name T375
Test name
Test status
Simulation time 39075129 ps
CPU time 1.44 seconds
Started Jul 16 07:14:22 PM PDT 24
Finished Jul 16 07:14:35 PM PDT 24
Peak memory 217448 kb
Host smart-33204ef9-4c69-4f74-ba6a-61ecd66815b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618623221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1618623221
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.3913558196
Short name T122
Test name
Test status
Simulation time 92187588 ps
CPU time 1.11 seconds
Started Jul 16 07:14:29 PM PDT 24
Finished Jul 16 07:14:51 PM PDT 24
Peak memory 220996 kb
Host smart-8137744d-d300-43c6-acd0-cb49d443f9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913558196 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.3913558196
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.2568777358
Short name T175
Test name
Test status
Simulation time 21334974 ps
CPU time 1.18 seconds
Started Jul 16 07:14:29 PM PDT 24
Finished Jul 16 07:14:51 PM PDT 24
Peak memory 224160 kb
Host smart-3e9924cf-8ac9-4466-885c-4ffe30d70b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568777358 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.2568777358
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.2833953531
Short name T606
Test name
Test status
Simulation time 142708468 ps
CPU time 1.32 seconds
Started Jul 16 07:14:18 PM PDT 24
Finished Jul 16 07:14:25 PM PDT 24
Peak memory 220400 kb
Host smart-e9d5e136-fe46-4db6-ac74-9293f8f273a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833953531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.2833953531
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.1619744694
Short name T837
Test name
Test status
Simulation time 82998181 ps
CPU time 1.12 seconds
Started Jul 16 07:14:29 PM PDT 24
Finished Jul 16 07:14:53 PM PDT 24
Peak memory 218908 kb
Host smart-1719882a-3939-4387-a23b-d9c4b5beb50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619744694 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.1619744694
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.3073059704
Short name T157
Test name
Test status
Simulation time 19378342 ps
CPU time 1.15 seconds
Started Jul 16 07:14:29 PM PDT 24
Finished Jul 16 07:14:51 PM PDT 24
Peak memory 224176 kb
Host smart-f7117687-031a-44a0-adc6-4a75ad9c4b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073059704 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.3073059704
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.1986992733
Short name T493
Test name
Test status
Simulation time 213119679 ps
CPU time 3.33 seconds
Started Jul 16 07:14:29 PM PDT 24
Finished Jul 16 07:14:53 PM PDT 24
Peak memory 220572 kb
Host smart-896e3eef-d561-4845-a448-30e6a5711dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986992733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.1986992733
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.3205602010
Short name T844
Test name
Test status
Simulation time 61805610 ps
CPU time 1.12 seconds
Started Jul 16 07:14:21 PM PDT 24
Finished Jul 16 07:14:30 PM PDT 24
Peak memory 218912 kb
Host smart-94750288-4792-4de0-8e0a-dfdc3c557aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205602010 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.3205602010
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.2931548902
Short name T144
Test name
Test status
Simulation time 28990472 ps
CPU time 0.89 seconds
Started Jul 16 07:14:20 PM PDT 24
Finished Jul 16 07:14:29 PM PDT 24
Peak memory 218520 kb
Host smart-a2a0eeda-6091-47d8-b517-2bcb6371c5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931548902 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2931548902
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.961287515
Short name T561
Test name
Test status
Simulation time 284028094 ps
CPU time 3.76 seconds
Started Jul 16 07:14:16 PM PDT 24
Finished Jul 16 07:14:25 PM PDT 24
Peak memory 218856 kb
Host smart-b8848d52-1014-4cb7-822a-a0d00f155f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961287515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.961287515
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.2843708847
Short name T478
Test name
Test status
Simulation time 79631257 ps
CPU time 1.2 seconds
Started Jul 16 07:14:23 PM PDT 24
Finished Jul 16 07:14:36 PM PDT 24
Peak memory 219284 kb
Host smart-0ca2d5f9-04ac-40ae-b6cb-b75673549522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843708847 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.2843708847
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.197236476
Short name T181
Test name
Test status
Simulation time 37858752 ps
CPU time 0.9 seconds
Started Jul 16 07:14:18 PM PDT 24
Finished Jul 16 07:14:25 PM PDT 24
Peak memory 219620 kb
Host smart-af62695d-becf-4fa4-a2fc-285e1b240128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197236476 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.197236476
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.4230390781
Short name T708
Test name
Test status
Simulation time 70473127 ps
CPU time 1.29 seconds
Started Jul 16 07:14:29 PM PDT 24
Finished Jul 16 07:14:53 PM PDT 24
Peak memory 219072 kb
Host smart-c2f6d9ef-0e06-4cf8-a825-747985ad4527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230390781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.4230390781
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.1690711936
Short name T717
Test name
Test status
Simulation time 261066020 ps
CPU time 1.14 seconds
Started Jul 16 07:14:21 PM PDT 24
Finished Jul 16 07:14:31 PM PDT 24
Peak memory 219840 kb
Host smart-447b43ed-6bf8-4df6-a06e-e14014cd092a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690711936 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.1690711936
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.1934538861
Short name T852
Test name
Test status
Simulation time 43121760 ps
CPU time 1.12 seconds
Started Jul 16 07:14:19 PM PDT 24
Finished Jul 16 07:14:27 PM PDT 24
Peak memory 217580 kb
Host smart-64ab2fb1-d050-4e12-8f07-dc5d596ea95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934538861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.1934538861
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.1210434206
Short name T155
Test name
Test status
Simulation time 63380487 ps
CPU time 1.13 seconds
Started Jul 16 07:14:19 PM PDT 24
Finished Jul 16 07:14:27 PM PDT 24
Peak memory 218916 kb
Host smart-a6c3068b-8906-4ff9-8851-955cffca58bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210434206 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.1210434206
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.1194710631
Short name T614
Test name
Test status
Simulation time 21140982 ps
CPU time 1.09 seconds
Started Jul 16 07:14:25 PM PDT 24
Finished Jul 16 07:14:42 PM PDT 24
Peak memory 219976 kb
Host smart-1e646ea7-dfe7-437b-a0af-47a6594974bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194710631 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.1194710631
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.3869149837
Short name T752
Test name
Test status
Simulation time 93080745 ps
CPU time 1.36 seconds
Started Jul 16 07:14:21 PM PDT 24
Finished Jul 16 07:14:32 PM PDT 24
Peak memory 219252 kb
Host smart-610ded4b-7573-4d10-930c-268066a695e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869149837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.3869149837
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.2425390587
Short name T922
Test name
Test status
Simulation time 174827806 ps
CPU time 1.17 seconds
Started Jul 16 07:14:18 PM PDT 24
Finished Jul 16 07:14:25 PM PDT 24
Peak memory 220276 kb
Host smart-5d2921d6-8f8c-4e44-9d9f-eb1e6c9467d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425390587 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.2425390587
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.3989220993
Short name T150
Test name
Test status
Simulation time 24175721 ps
CPU time 0.89 seconds
Started Jul 16 07:14:18 PM PDT 24
Finished Jul 16 07:14:25 PM PDT 24
Peak memory 218656 kb
Host smart-50d33e59-18ce-40d2-a302-efb4adb59159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989220993 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.3989220993
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.190394150
Short name T341
Test name
Test status
Simulation time 101466201 ps
CPU time 1.26 seconds
Started Jul 16 07:14:20 PM PDT 24
Finished Jul 16 07:14:29 PM PDT 24
Peak memory 215608 kb
Host smart-207eb33e-ec68-4409-b425-eb1d8dc35d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190394150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.190394150
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.3572769837
Short name T376
Test name
Test status
Simulation time 35579419 ps
CPU time 1.12 seconds
Started Jul 16 07:14:19 PM PDT 24
Finished Jul 16 07:14:26 PM PDT 24
Peak memory 218940 kb
Host smart-d820bc14-af03-404a-8e4f-d69bc838b870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572769837 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.3572769837
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.3360584522
Short name T636
Test name
Test status
Simulation time 25508272 ps
CPU time 1.11 seconds
Started Jul 16 07:14:20 PM PDT 24
Finished Jul 16 07:14:29 PM PDT 24
Peak memory 218732 kb
Host smart-e5f7bd41-ab8f-40df-8cc9-eca63a1900a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360584522 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.3360584522
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.3083821234
Short name T438
Test name
Test status
Simulation time 32885737 ps
CPU time 1.32 seconds
Started Jul 16 07:14:21 PM PDT 24
Finished Jul 16 07:14:32 PM PDT 24
Peak memory 219844 kb
Host smart-3074c3e5-2e04-4ef5-a001-11b239440a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083821234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.3083821234
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.154450520
Short name T454
Test name
Test status
Simulation time 47571036 ps
CPU time 1.16 seconds
Started Jul 16 07:14:22 PM PDT 24
Finished Jul 16 07:14:33 PM PDT 24
Peak memory 221048 kb
Host smart-5961bf37-b1f2-4dd4-9a15-3e0b5de3dd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154450520 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.154450520
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.1631057475
Short name T753
Test name
Test status
Simulation time 31116350 ps
CPU time 0.86 seconds
Started Jul 16 07:14:22 PM PDT 24
Finished Jul 16 07:14:33 PM PDT 24
Peak memory 218708 kb
Host smart-c3ab7e6b-b821-40f9-9c78-44036777b9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631057475 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.1631057475
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.567352233
Short name T270
Test name
Test status
Simulation time 83445428 ps
CPU time 1.07 seconds
Started Jul 16 07:14:20 PM PDT 24
Finished Jul 16 07:14:29 PM PDT 24
Peak memory 215548 kb
Host smart-3fcc6256-0696-4736-b9cf-c8f6ab88d751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567352233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.567352233
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.1367893843
Short name T293
Test name
Test status
Simulation time 24335405 ps
CPU time 1.19 seconds
Started Jul 16 07:11:53 PM PDT 24
Finished Jul 16 07:13:15 PM PDT 24
Peak memory 219076 kb
Host smart-ea4d55b4-3ffc-4ada-b0c8-45b09bb9c9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367893843 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.1367893843
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.324831012
Short name T336
Test name
Test status
Simulation time 22945544 ps
CPU time 0.87 seconds
Started Jul 16 07:12:14 PM PDT 24
Finished Jul 16 07:13:27 PM PDT 24
Peak memory 215392 kb
Host smart-6b3d2e44-fc91-437a-aac2-cd0bbd1bc465
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324831012 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.324831012
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.1543368671
Short name T928
Test name
Test status
Simulation time 262408570 ps
CPU time 1.28 seconds
Started Jul 16 07:12:15 PM PDT 24
Finished Jul 16 07:13:29 PM PDT 24
Peak memory 217288 kb
Host smart-a078a121-0d2f-4685-8939-7df34b575847
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543368671 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.1543368671
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.2646238277
Short name T619
Test name
Test status
Simulation time 35810456 ps
CPU time 0.89 seconds
Started Jul 16 07:12:02 PM PDT 24
Finished Jul 16 07:13:21 PM PDT 24
Peak memory 218632 kb
Host smart-43adfb66-06e7-4129-94ca-6bb299021a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646238277 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.2646238277
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.994337143
Short name T462
Test name
Test status
Simulation time 90811788 ps
CPU time 1.21 seconds
Started Jul 16 07:11:52 PM PDT 24
Finished Jul 16 07:13:22 PM PDT 24
Peak memory 219104 kb
Host smart-5a9a312a-9550-43f5-8cfc-358113df327f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994337143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.994337143
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.3868814394
Short name T419
Test name
Test status
Simulation time 22081937 ps
CPU time 1.18 seconds
Started Jul 16 07:11:58 PM PDT 24
Finished Jul 16 07:13:20 PM PDT 24
Peak memory 224320 kb
Host smart-5cfcc220-b8da-47da-8e0d-2922b6e3d2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868814394 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.3868814394
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.1104819120
Short name T747
Test name
Test status
Simulation time 17880120 ps
CPU time 1.03 seconds
Started Jul 16 07:11:56 PM PDT 24
Finished Jul 16 07:13:18 PM PDT 24
Peak memory 207376 kb
Host smart-6d8d626d-0941-4d3e-a78d-64c120eb7ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104819120 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.1104819120
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.1507930027
Short name T673
Test name
Test status
Simulation time 15798639 ps
CPU time 1.01 seconds
Started Jul 16 07:11:56 PM PDT 24
Finished Jul 16 07:13:18 PM PDT 24
Peak memory 215624 kb
Host smart-464c9792-f0f4-4a68-98a7-d0d0b0a4df9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507930027 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.1507930027
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.3681656124
Short name T832
Test name
Test status
Simulation time 327472350 ps
CPU time 3.65 seconds
Started Jul 16 07:11:55 PM PDT 24
Finished Jul 16 07:13:20 PM PDT 24
Peak memory 215616 kb
Host smart-62dbfca2-83fa-4850-8173-4b78075b438d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681656124 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.3681656124
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.4233728889
Short name T800
Test name
Test status
Simulation time 71851177276 ps
CPU time 773.12 seconds
Started Jul 16 07:11:57 PM PDT 24
Finished Jul 16 07:26:12 PM PDT 24
Peak memory 220660 kb
Host smart-f5cb676e-f777-4bd5-bfba-dd5847af1744
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233728889 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.4233728889
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.2835546955
Short name T666
Test name
Test status
Simulation time 53498408 ps
CPU time 1.17 seconds
Started Jul 16 07:14:24 PM PDT 24
Finished Jul 16 07:14:39 PM PDT 24
Peak memory 220276 kb
Host smart-f3ff8504-9fad-4a96-b8d4-6e80109bb1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835546955 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.2835546955
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.1720493021
Short name T977
Test name
Test status
Simulation time 18709774 ps
CPU time 1.13 seconds
Started Jul 16 07:14:19 PM PDT 24
Finished Jul 16 07:14:27 PM PDT 24
Peak memory 218756 kb
Host smart-81019b5d-e7b5-48b1-9636-2f00c444feb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720493021 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1720493021
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.723736469
Short name T931
Test name
Test status
Simulation time 46941425 ps
CPU time 1.33 seconds
Started Jul 16 07:14:20 PM PDT 24
Finished Jul 16 07:14:28 PM PDT 24
Peak memory 218892 kb
Host smart-8247c473-5d5f-4e76-9d83-c7a1cb545ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723736469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.723736469
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.2729204409
Short name T795
Test name
Test status
Simulation time 54052187 ps
CPU time 1.15 seconds
Started Jul 16 07:14:19 PM PDT 24
Finished Jul 16 07:14:28 PM PDT 24
Peak memory 221200 kb
Host smart-17c6008f-e6ee-4a97-aea3-1b4d8af30830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729204409 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.2729204409
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.2647800605
Short name T199
Test name
Test status
Simulation time 18330811 ps
CPU time 1.04 seconds
Started Jul 16 07:14:20 PM PDT 24
Finished Jul 16 07:14:29 PM PDT 24
Peak memory 218860 kb
Host smart-1d3188d2-bd2a-47c4-aa71-8c7ff1820347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647800605 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.2647800605
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.613330316
Short name T43
Test name
Test status
Simulation time 52368333 ps
CPU time 1.32 seconds
Started Jul 16 07:14:24 PM PDT 24
Finished Jul 16 07:14:41 PM PDT 24
Peak memory 217580 kb
Host smart-c6d9a235-0107-4bdd-9378-5cc8bcae9d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613330316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.613330316
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.3964208594
Short name T379
Test name
Test status
Simulation time 105218538 ps
CPU time 1.15 seconds
Started Jul 16 07:14:22 PM PDT 24
Finished Jul 16 07:14:35 PM PDT 24
Peak memory 220688 kb
Host smart-0a6d2eaf-3eba-4a4b-928a-d197e02af8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964208594 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.3964208594
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.3767700085
Short name T701
Test name
Test status
Simulation time 22726503 ps
CPU time 1 seconds
Started Jul 16 07:14:24 PM PDT 24
Finished Jul 16 07:14:39 PM PDT 24
Peak memory 218752 kb
Host smart-9d771064-9a0d-441e-974d-08a10e3e9aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767700085 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.3767700085
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.4241152950
Short name T372
Test name
Test status
Simulation time 58082861 ps
CPU time 1.25 seconds
Started Jul 16 07:14:20 PM PDT 24
Finished Jul 16 07:14:29 PM PDT 24
Peak memory 217720 kb
Host smart-3fa91e93-8a18-4c79-9fa8-7b6e9d506480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241152950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.4241152950
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.38951153
Short name T64
Test name
Test status
Simulation time 29574682 ps
CPU time 1.2 seconds
Started Jul 16 07:14:27 PM PDT 24
Finished Jul 16 07:14:46 PM PDT 24
Peak memory 221152 kb
Host smart-61aad334-976c-4b5b-97d7-ea84148b1de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38951153 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.38951153
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.322397535
Short name T95
Test name
Test status
Simulation time 39215467 ps
CPU time 1.01 seconds
Started Jul 16 07:14:31 PM PDT 24
Finished Jul 16 07:14:56 PM PDT 24
Peak memory 220792 kb
Host smart-5748f5b7-2517-4ed0-949b-66149447cbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322397535 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.322397535
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.3991580433
Short name T894
Test name
Test status
Simulation time 92114532 ps
CPU time 3 seconds
Started Jul 16 07:14:28 PM PDT 24
Finished Jul 16 07:14:50 PM PDT 24
Peak memory 220080 kb
Host smart-37288657-4da0-4a6b-8306-cd07a602ba64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991580433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.3991580433
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.2234069417
Short name T288
Test name
Test status
Simulation time 44853906 ps
CPU time 1.15 seconds
Started Jul 16 07:14:30 PM PDT 24
Finished Jul 16 07:14:54 PM PDT 24
Peak memory 218924 kb
Host smart-313e24d3-73eb-4ba7-a25a-5a624bcade6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234069417 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.2234069417
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.1436856558
Short name T670
Test name
Test status
Simulation time 20753990 ps
CPU time 1.05 seconds
Started Jul 16 07:14:40 PM PDT 24
Finished Jul 16 07:15:14 PM PDT 24
Peak memory 219984 kb
Host smart-eed261e1-94db-474b-858f-438fb36c859a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436856558 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.1436856558
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/65.edn_alert.1270840405
Short name T146
Test name
Test status
Simulation time 30535134 ps
CPU time 1.36 seconds
Started Jul 16 07:14:28 PM PDT 24
Finished Jul 16 07:14:48 PM PDT 24
Peak memory 215980 kb
Host smart-ebb52853-eda5-4eef-ba55-d2313557e138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270840405 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.1270840405
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.547575414
Short name T740
Test name
Test status
Simulation time 56378038 ps
CPU time 1.23 seconds
Started Jul 16 07:14:28 PM PDT 24
Finished Jul 16 07:14:48 PM PDT 24
Peak memory 215744 kb
Host smart-66581329-d4d3-4652-b593-6e7e8817a1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547575414 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.547575414
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.1888994543
Short name T728
Test name
Test status
Simulation time 158790939 ps
CPU time 2.83 seconds
Started Jul 16 07:14:30 PM PDT 24
Finished Jul 16 07:14:55 PM PDT 24
Peak memory 220620 kb
Host smart-465a3a28-b519-4583-a3a6-8355c2776f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888994543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.1888994543
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.1338186467
Short name T657
Test name
Test status
Simulation time 43376602 ps
CPU time 1.14 seconds
Started Jul 16 07:14:37 PM PDT 24
Finished Jul 16 07:15:07 PM PDT 24
Peak memory 218928 kb
Host smart-f4a13b89-4739-4fc3-bafa-d93192a29464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338186467 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.1338186467
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.1942798288
Short name T848
Test name
Test status
Simulation time 26459980 ps
CPU time 1.2 seconds
Started Jul 16 07:14:36 PM PDT 24
Finished Jul 16 07:15:07 PM PDT 24
Peak memory 217760 kb
Host smart-a4570a2f-85a6-413e-8ab0-8fff0b52728d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942798288 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1942798288
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.2280302377
Short name T907
Test name
Test status
Simulation time 85995575 ps
CPU time 1.2 seconds
Started Jul 16 07:14:29 PM PDT 24
Finished Jul 16 07:14:51 PM PDT 24
Peak memory 217752 kb
Host smart-6b24f0e7-5b07-4500-8272-4fd087fa7add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280302377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.2280302377
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.506369960
Short name T461
Test name
Test status
Simulation time 36756779 ps
CPU time 1.37 seconds
Started Jul 16 07:14:29 PM PDT 24
Finished Jul 16 07:14:51 PM PDT 24
Peak memory 215932 kb
Host smart-d83c59ff-68ba-4f20-b5b8-c037e74b4015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506369960 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.506369960
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.2077672794
Short name T944
Test name
Test status
Simulation time 28919016 ps
CPU time 1.31 seconds
Started Jul 16 07:14:38 PM PDT 24
Finished Jul 16 07:15:07 PM PDT 24
Peak memory 225856 kb
Host smart-947d4aa8-de52-4703-a385-f718dfce59ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077672794 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.2077672794
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.2533471306
Short name T710
Test name
Test status
Simulation time 60685271 ps
CPU time 1.29 seconds
Started Jul 16 07:14:27 PM PDT 24
Finished Jul 16 07:14:46 PM PDT 24
Peak memory 220232 kb
Host smart-4785b15b-9b2a-4d0f-99ea-fed75d92fa7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533471306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.2533471306
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.1279530313
Short name T88
Test name
Test status
Simulation time 28967797 ps
CPU time 1.2 seconds
Started Jul 16 07:14:30 PM PDT 24
Finished Jul 16 07:14:54 PM PDT 24
Peak memory 220876 kb
Host smart-a00df6b5-dcfd-4e92-9b9a-0a1b6e994e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279530313 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.1279530313
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.1736790636
Short name T119
Test name
Test status
Simulation time 19831534 ps
CPU time 1.06 seconds
Started Jul 16 07:14:42 PM PDT 24
Finished Jul 16 07:15:17 PM PDT 24
Peak memory 218700 kb
Host smart-1fca5b04-4ce3-4125-8c11-27b5c1762b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736790636 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1736790636
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.1619970830
Short name T904
Test name
Test status
Simulation time 35120620 ps
CPU time 1.32 seconds
Started Jul 16 07:14:31 PM PDT 24
Finished Jul 16 07:14:56 PM PDT 24
Peak memory 217668 kb
Host smart-887da0be-531a-4418-b28b-461a4c507488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619970830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.1619970830
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.2408879660
Short name T507
Test name
Test status
Simulation time 160406121 ps
CPU time 1.31 seconds
Started Jul 16 07:14:31 PM PDT 24
Finished Jul 16 07:14:56 PM PDT 24
Peak memory 218912 kb
Host smart-7217cae0-5e44-4740-9b07-2c0dbeece252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408879660 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.2408879660
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.2321103938
Short name T114
Test name
Test status
Simulation time 62093864 ps
CPU time 0.96 seconds
Started Jul 16 07:14:42 PM PDT 24
Finished Jul 16 07:15:16 PM PDT 24
Peak memory 220852 kb
Host smart-2033ef79-db94-44ca-a1b9-5e60d7d1d560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321103938 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2321103938
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.1023875678
Short name T867
Test name
Test status
Simulation time 46447339 ps
CPU time 1.39 seconds
Started Jul 16 07:14:30 PM PDT 24
Finished Jul 16 07:14:54 PM PDT 24
Peak memory 217696 kb
Host smart-fdcec430-6531-4c13-b30c-9d3180352fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023875678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1023875678
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.3167268766
Short name T906
Test name
Test status
Simulation time 43609864 ps
CPU time 1.12 seconds
Started Jul 16 07:12:10 PM PDT 24
Finished Jul 16 07:13:27 PM PDT 24
Peak memory 219732 kb
Host smart-73bd9893-daad-438a-b8c9-1db57cf89df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167268766 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3167268766
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.2767252524
Short name T60
Test name
Test status
Simulation time 27661074 ps
CPU time 0.9 seconds
Started Jul 16 07:12:07 PM PDT 24
Finished Jul 16 07:13:26 PM PDT 24
Peak memory 207008 kb
Host smart-2824cfff-fd10-4753-8b09-3ff8709455b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767252524 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.2767252524
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.4089520619
Short name T893
Test name
Test status
Simulation time 20050947 ps
CPU time 0.86 seconds
Started Jul 16 07:12:14 PM PDT 24
Finished Jul 16 07:13:28 PM PDT 24
Peak memory 216480 kb
Host smart-145d06ea-cc4f-481c-83f8-1dbd9402b4b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089520619 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.4089520619
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.4244077520
Short name T973
Test name
Test status
Simulation time 86902902 ps
CPU time 1.04 seconds
Started Jul 16 07:12:09 PM PDT 24
Finished Jul 16 07:13:27 PM PDT 24
Peak memory 218596 kb
Host smart-93099deb-ed8f-470c-a59c-4788a2f5cdc9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244077520 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.4244077520
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.1224028617
Short name T443
Test name
Test status
Simulation time 30429813 ps
CPU time 1.02 seconds
Started Jul 16 07:12:12 PM PDT 24
Finished Jul 16 07:13:27 PM PDT 24
Peak memory 218640 kb
Host smart-05924853-48d0-4869-990c-e21fccf75536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224028617 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.1224028617
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.2124731366
Short name T699
Test name
Test status
Simulation time 51221439 ps
CPU time 1.17 seconds
Started Jul 16 07:12:21 PM PDT 24
Finished Jul 16 07:13:31 PM PDT 24
Peak memory 217756 kb
Host smart-8dfc2116-3b77-43eb-b71d-f273dc959dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124731366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.2124731366
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.3500978867
Short name T93
Test name
Test status
Simulation time 31567941 ps
CPU time 0.9 seconds
Started Jul 16 07:12:10 PM PDT 24
Finished Jul 16 07:13:27 PM PDT 24
Peak memory 216008 kb
Host smart-8802750a-c210-499e-b289-eb3b780e8934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500978867 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.3500978867
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.1331962559
Short name T23
Test name
Test status
Simulation time 38655460 ps
CPU time 0.87 seconds
Started Jul 16 07:12:06 PM PDT 24
Finished Jul 16 07:13:24 PM PDT 24
Peak memory 207396 kb
Host smart-341bff72-d7e3-4b45-ac08-52ddf3271fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331962559 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.1331962559
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.3478524466
Short name T333
Test name
Test status
Simulation time 17749328 ps
CPU time 0.98 seconds
Started Jul 16 07:12:09 PM PDT 24
Finished Jul 16 07:13:27 PM PDT 24
Peak memory 215632 kb
Host smart-d8ed4e79-7b94-41a2-81c0-5019c29e1b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478524466 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.3478524466
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.4151091281
Short name T396
Test name
Test status
Simulation time 323127907 ps
CPU time 6.28 seconds
Started Jul 16 07:12:06 PM PDT 24
Finished Jul 16 07:13:30 PM PDT 24
Peak memory 215628 kb
Host smart-0a3aa699-77d8-43f7-b10e-07118ce332e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151091281 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.4151091281
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.3417085928
Short name T934
Test name
Test status
Simulation time 27624116310 ps
CPU time 166.93 seconds
Started Jul 16 07:12:13 PM PDT 24
Finished Jul 16 07:16:14 PM PDT 24
Peak memory 218748 kb
Host smart-3d2cfd0e-d2dd-4356-90e5-a232a661f855
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417085928 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.3417085928
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.3496574626
Short name T961
Test name
Test status
Simulation time 43809294 ps
CPU time 1.29 seconds
Started Jul 16 07:14:31 PM PDT 24
Finished Jul 16 07:14:56 PM PDT 24
Peak memory 221408 kb
Host smart-9c2d2eba-2cfb-4e3d-ab80-40ae1a2bb85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496574626 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.3496574626
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.2434894669
Short name T700
Test name
Test status
Simulation time 39035275 ps
CPU time 1.2 seconds
Started Jul 16 07:14:36 PM PDT 24
Finished Jul 16 07:15:03 PM PDT 24
Peak memory 229868 kb
Host smart-d99522fb-eb93-454a-9be7-ed7a792206ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434894669 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.2434894669
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.3929269637
Short name T932
Test name
Test status
Simulation time 56753858 ps
CPU time 1.18 seconds
Started Jul 16 07:14:34 PM PDT 24
Finished Jul 16 07:15:00 PM PDT 24
Peak memory 217728 kb
Host smart-86de5fab-fdf6-493a-94a7-221d2cc8e968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929269637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3929269637
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.1401639671
Short name T295
Test name
Test status
Simulation time 115179773 ps
CPU time 1.15 seconds
Started Jul 16 07:14:34 PM PDT 24
Finished Jul 16 07:15:00 PM PDT 24
Peak memory 219916 kb
Host smart-4f34a6f9-c715-4be9-b66d-30b9ebc95a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401639671 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.1401639671
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.661073350
Short name T802
Test name
Test status
Simulation time 18457393 ps
CPU time 1.15 seconds
Started Jul 16 07:14:29 PM PDT 24
Finished Jul 16 07:14:51 PM PDT 24
Peak memory 224224 kb
Host smart-f8a7902d-1843-4aa9-bda7-22f782846e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661073350 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.661073350
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.1041958912
Short name T315
Test name
Test status
Simulation time 101645047 ps
CPU time 1.54 seconds
Started Jul 16 07:14:29 PM PDT 24
Finished Jul 16 07:14:52 PM PDT 24
Peak memory 218908 kb
Host smart-c94c28ea-c2a3-4490-b0a9-4f32ae9f2ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041958912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.1041958912
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.1252561450
Short name T380
Test name
Test status
Simulation time 37386300 ps
CPU time 1.13 seconds
Started Jul 16 07:14:41 PM PDT 24
Finished Jul 16 07:15:16 PM PDT 24
Peak memory 220036 kb
Host smart-992cb1b0-3bcf-496b-9968-f3b8ee781c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252561450 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.1252561450
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.2623726618
Short name T366
Test name
Test status
Simulation time 23819960 ps
CPU time 1.07 seconds
Started Jul 16 07:14:36 PM PDT 24
Finished Jul 16 07:15:03 PM PDT 24
Peak memory 224204 kb
Host smart-a21a31dd-89f6-408e-9af2-8d93f806a733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623726618 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.2623726618
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.652320367
Short name T433
Test name
Test status
Simulation time 259739444 ps
CPU time 1.75 seconds
Started Jul 16 07:14:41 PM PDT 24
Finished Jul 16 07:15:17 PM PDT 24
Peak memory 219420 kb
Host smart-257da130-15ce-4389-acd5-07c59d8bd416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652320367 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.652320367
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.1753327511
Short name T815
Test name
Test status
Simulation time 61672517 ps
CPU time 1.02 seconds
Started Jul 16 07:14:29 PM PDT 24
Finished Jul 16 07:14:51 PM PDT 24
Peak memory 219044 kb
Host smart-71e81381-37d1-4b10-83c7-0add0ac298a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753327511 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.1753327511
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.1821792280
Short name T554
Test name
Test status
Simulation time 20132568 ps
CPU time 1.07 seconds
Started Jul 16 07:14:30 PM PDT 24
Finished Jul 16 07:14:54 PM PDT 24
Peak memory 219616 kb
Host smart-b373cd28-a6d2-45b9-a945-83e87aa630fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821792280 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1821792280
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.2660386223
Short name T886
Test name
Test status
Simulation time 52631935 ps
CPU time 1.29 seconds
Started Jul 16 07:14:28 PM PDT 24
Finished Jul 16 07:14:48 PM PDT 24
Peak memory 217552 kb
Host smart-b6aeb47a-4f23-452b-818f-ecdebf1f7f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660386223 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.2660386223
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.2432299406
Short name T107
Test name
Test status
Simulation time 51890426 ps
CPU time 1.19 seconds
Started Jul 16 07:14:31 PM PDT 24
Finished Jul 16 07:14:56 PM PDT 24
Peak memory 218936 kb
Host smart-ba495231-afc3-4dda-b5b1-3163f56d64d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432299406 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.2432299406
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.2304020841
Short name T808
Test name
Test status
Simulation time 22411845 ps
CPU time 1.28 seconds
Started Jul 16 07:14:35 PM PDT 24
Finished Jul 16 07:15:03 PM PDT 24
Peak memory 224220 kb
Host smart-f11e4ca7-97d0-4b52-9515-016340e4451b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304020841 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.2304020841
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.2431668351
Short name T779
Test name
Test status
Simulation time 30732484 ps
CPU time 1.27 seconds
Started Jul 16 07:14:31 PM PDT 24
Finished Jul 16 07:14:56 PM PDT 24
Peak memory 217672 kb
Host smart-124d4023-729d-4de7-b5e9-45c49742e919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431668351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2431668351
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.3610145725
Short name T207
Test name
Test status
Simulation time 26232413 ps
CPU time 1.2 seconds
Started Jul 16 07:14:39 PM PDT 24
Finished Jul 16 07:15:09 PM PDT 24
Peak memory 220008 kb
Host smart-ab6dbf36-4f8c-43a8-b9bb-a6975e46cb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610145725 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.3610145725
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.3371616502
Short name T570
Test name
Test status
Simulation time 27094424 ps
CPU time 0.91 seconds
Started Jul 16 07:14:37 PM PDT 24
Finished Jul 16 07:15:07 PM PDT 24
Peak memory 218804 kb
Host smart-21108273-7745-4b9c-9ace-d8c09ed416a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371616502 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3371616502
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.219865266
Short name T75
Test name
Test status
Simulation time 91145659 ps
CPU time 1.31 seconds
Started Jul 16 07:14:41 PM PDT 24
Finished Jul 16 07:15:17 PM PDT 24
Peak memory 217696 kb
Host smart-327b63db-2c6b-4a9e-bea5-6ff2dfc606ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219865266 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.219865266
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.361823177
Short name T769
Test name
Test status
Simulation time 37904244 ps
CPU time 1.18 seconds
Started Jul 16 07:14:28 PM PDT 24
Finished Jul 16 07:14:48 PM PDT 24
Peak memory 219456 kb
Host smart-8a55ff95-8fbd-4225-8ce6-4662008254e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361823177 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.361823177
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.2856214810
Short name T159
Test name
Test status
Simulation time 39388044 ps
CPU time 0.82 seconds
Started Jul 16 07:14:29 PM PDT 24
Finished Jul 16 07:14:51 PM PDT 24
Peak memory 218540 kb
Host smart-60367b57-7cbf-4e18-89b5-d86713af0464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856214810 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.2856214810
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.764434736
Short name T523
Test name
Test status
Simulation time 40997738 ps
CPU time 1.48 seconds
Started Jul 16 07:14:29 PM PDT 24
Finished Jul 16 07:14:51 PM PDT 24
Peak memory 219116 kb
Host smart-8fcfb8c7-5974-4340-9463-8b6e5474328c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764434736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.764434736
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.1491493524
Short name T951
Test name
Test status
Simulation time 27206149 ps
CPU time 1.33 seconds
Started Jul 16 07:14:42 PM PDT 24
Finished Jul 16 07:15:17 PM PDT 24
Peak memory 219192 kb
Host smart-8826425b-7133-43c4-ad2f-886302163dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491493524 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.1491493524
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.1178082015
Short name T422
Test name
Test status
Simulation time 36849840 ps
CPU time 1 seconds
Started Jul 16 07:14:31 PM PDT 24
Finished Jul 16 07:14:56 PM PDT 24
Peak memory 224060 kb
Host smart-08db0ecc-aa33-4afa-aa93-aa17d0a2cc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178082015 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.1178082015
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.3217376329
Short name T314
Test name
Test status
Simulation time 43628619 ps
CPU time 1.59 seconds
Started Jul 16 07:14:28 PM PDT 24
Finished Jul 16 07:14:51 PM PDT 24
Peak memory 218852 kb
Host smart-a792bb22-03da-4755-8949-9e34bbb361b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217376329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.3217376329
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.4179468821
Short name T281
Test name
Test status
Simulation time 24606857 ps
CPU time 1.16 seconds
Started Jul 16 07:14:35 PM PDT 24
Finished Jul 16 07:15:03 PM PDT 24
Peak memory 220144 kb
Host smart-7cad2a97-1593-45b9-b17a-3f2affe7f6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179468821 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.4179468821
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.2960089644
Short name T954
Test name
Test status
Simulation time 63144616 ps
CPU time 1.12 seconds
Started Jul 16 07:14:36 PM PDT 24
Finished Jul 16 07:15:07 PM PDT 24
Peak memory 219932 kb
Host smart-6855ea93-21ba-40b4-8268-fa27e3ec74fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960089644 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2960089644
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.2933219879
Short name T480
Test name
Test status
Simulation time 45260398 ps
CPU time 1.09 seconds
Started Jul 16 07:14:32 PM PDT 24
Finished Jul 16 07:14:56 PM PDT 24
Peak memory 217480 kb
Host smart-f49aa78e-6b00-4782-9160-301a647e3b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933219879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.2933219879
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.1180953574
Short name T178
Test name
Test status
Simulation time 56496847 ps
CPU time 1.23 seconds
Started Jul 16 07:14:50 PM PDT 24
Finished Jul 16 07:15:41 PM PDT 24
Peak memory 215956 kb
Host smart-3a1e527f-7a15-4990-8bdf-a93787151341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180953574 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.1180953574
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.2221430062
Short name T985
Test name
Test status
Simulation time 27982800 ps
CPU time 0.85 seconds
Started Jul 16 07:14:53 PM PDT 24
Finished Jul 16 07:15:36 PM PDT 24
Peak memory 218524 kb
Host smart-7c06f546-2422-48c5-af3b-6a5125410857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221430062 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.2221430062
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.1249068640
Short name T529
Test name
Test status
Simulation time 105937367 ps
CPU time 1.22 seconds
Started Jul 16 07:14:38 PM PDT 24
Finished Jul 16 07:15:07 PM PDT 24
Peak memory 220228 kb
Host smart-218d6e88-62ce-41de-9c13-35e64f63a6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249068640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.1249068640
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.2852966125
Short name T552
Test name
Test status
Simulation time 25120809 ps
CPU time 1.26 seconds
Started Jul 16 07:12:09 PM PDT 24
Finished Jul 16 07:13:27 PM PDT 24
Peak memory 220876 kb
Host smart-77f63268-0455-43a7-a9b5-561bf0077625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852966125 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.2852966125
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.865056760
Short name T548
Test name
Test status
Simulation time 67711457 ps
CPU time 0.86 seconds
Started Jul 16 07:12:22 PM PDT 24
Finished Jul 16 07:13:30 PM PDT 24
Peak memory 215212 kb
Host smart-7b8ea411-8388-4d3a-8da5-b8cade9b6b27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865056760 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.865056760
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.2864753818
Short name T137
Test name
Test status
Simulation time 11573228 ps
CPU time 0.9 seconds
Started Jul 16 07:12:10 PM PDT 24
Finished Jul 16 07:13:27 PM PDT 24
Peak memory 215704 kb
Host smart-83f4eca0-88b5-4e1d-8ac4-4f070be95a94
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864753818 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.2864753818
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.4017095040
Short name T105
Test name
Test status
Simulation time 29218025 ps
CPU time 1.12 seconds
Started Jul 16 07:12:14 PM PDT 24
Finished Jul 16 07:13:28 PM PDT 24
Peak memory 217080 kb
Host smart-f439e52c-b19a-4884-b573-876c466d1939
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017095040 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.4017095040
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.435328587
Short name T125
Test name
Test status
Simulation time 32098436 ps
CPU time 1.09 seconds
Started Jul 16 07:12:13 PM PDT 24
Finished Jul 16 07:13:28 PM PDT 24
Peak memory 219896 kb
Host smart-790f01b5-398b-48f0-8909-b5470355281b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435328587 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.435328587
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.3283656778
Short name T515
Test name
Test status
Simulation time 91289496 ps
CPU time 1.92 seconds
Started Jul 16 07:12:07 PM PDT 24
Finished Jul 16 07:13:27 PM PDT 24
Peak memory 217804 kb
Host smart-ade064d5-b3cc-49f0-9091-299c97078b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283656778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3283656778
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.2838658409
Short name T799
Test name
Test status
Simulation time 27385140 ps
CPU time 0.96 seconds
Started Jul 16 07:12:18 PM PDT 24
Finished Jul 16 07:13:34 PM PDT 24
Peak memory 215768 kb
Host smart-f773e94d-69f5-4a9c-bc73-39d4d132c780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838658409 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2838658409
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.2280370583
Short name T860
Test name
Test status
Simulation time 53392541 ps
CPU time 0.92 seconds
Started Jul 16 07:12:12 PM PDT 24
Finished Jul 16 07:13:27 PM PDT 24
Peak memory 207368 kb
Host smart-ab69a269-269e-4fbb-b931-ef9d030c5d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280370583 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.2280370583
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.4247253293
Short name T686
Test name
Test status
Simulation time 122472787 ps
CPU time 0.97 seconds
Started Jul 16 07:12:08 PM PDT 24
Finished Jul 16 07:13:26 PM PDT 24
Peak memory 215560 kb
Host smart-7cfc843b-bc76-4e83-94fd-f7d830abb2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247253293 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.4247253293
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.426776605
Short name T943
Test name
Test status
Simulation time 440292431 ps
CPU time 5.03 seconds
Started Jul 16 07:12:07 PM PDT 24
Finished Jul 16 07:13:29 PM PDT 24
Peak memory 217576 kb
Host smart-75a72342-e4be-4588-9854-81b3536e8e7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426776605 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.426776605
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.2383693276
Short name T713
Test name
Test status
Simulation time 239117221765 ps
CPU time 1575.32 seconds
Started Jul 16 07:12:10 PM PDT 24
Finished Jul 16 07:39:41 PM PDT 24
Peak memory 226156 kb
Host smart-3c38087e-2a86-455e-9f30-d11d6d05ac00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383693276 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.2383693276
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.1615914540
Short name T866
Test name
Test status
Simulation time 93791530 ps
CPU time 1.28 seconds
Started Jul 16 07:14:41 PM PDT 24
Finished Jul 16 07:15:16 PM PDT 24
Peak memory 218836 kb
Host smart-36fd4c89-ffb7-45c6-9447-e1c59ca261ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615914540 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.1615914540
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.3179109675
Short name T714
Test name
Test status
Simulation time 62241626 ps
CPU time 0.82 seconds
Started Jul 16 07:14:31 PM PDT 24
Finished Jul 16 07:14:56 PM PDT 24
Peak memory 218736 kb
Host smart-da607381-4b0f-4bc5-8bc5-78949a9b0012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179109675 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.3179109675
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.2736672003
Short name T35
Test name
Test status
Simulation time 45567883 ps
CPU time 1.5 seconds
Started Jul 16 07:14:41 PM PDT 24
Finished Jul 16 07:15:16 PM PDT 24
Peak memory 219500 kb
Host smart-67646bef-6b29-48a4-8f0a-a4e30efa82cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736672003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.2736672003
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.3089186117
Short name T823
Test name
Test status
Simulation time 79870180 ps
CPU time 1.15 seconds
Started Jul 16 07:14:41 PM PDT 24
Finished Jul 16 07:15:16 PM PDT 24
Peak memory 220432 kb
Host smart-a9963a42-a7e9-44c7-b01d-752751f85307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089186117 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.3089186117
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.475242660
Short name T877
Test name
Test status
Simulation time 25997950 ps
CPU time 1.18 seconds
Started Jul 16 07:14:32 PM PDT 24
Finished Jul 16 07:14:58 PM PDT 24
Peak memory 220772 kb
Host smart-c0d656aa-6256-455e-8e88-9f2e96dfe972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475242660 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.475242660
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.3764963043
Short name T583
Test name
Test status
Simulation time 40080845 ps
CPU time 1.48 seconds
Started Jul 16 07:14:34 PM PDT 24
Finished Jul 16 07:15:01 PM PDT 24
Peak memory 220324 kb
Host smart-0e8a2a42-1fe8-4521-b587-dd27b7700b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764963043 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3764963043
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.3556237580
Short name T792
Test name
Test status
Simulation time 34804103 ps
CPU time 1.09 seconds
Started Jul 16 07:14:31 PM PDT 24
Finished Jul 16 07:14:56 PM PDT 24
Peak memory 218664 kb
Host smart-f2bac9e4-9ba5-41c1-bf76-2690ee9a9de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556237580 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.3556237580
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.950055821
Short name T949
Test name
Test status
Simulation time 44267250 ps
CPU time 0.96 seconds
Started Jul 16 07:14:43 PM PDT 24
Finished Jul 16 07:15:19 PM PDT 24
Peak memory 224068 kb
Host smart-dccf3590-cd89-4081-a5bb-07e5eeed089f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950055821 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.950055821
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.2496967536
Short name T693
Test name
Test status
Simulation time 41458848 ps
CPU time 1.5 seconds
Started Jul 16 07:14:31 PM PDT 24
Finished Jul 16 07:14:56 PM PDT 24
Peak memory 217492 kb
Host smart-a1657122-7a3e-47ac-a0ee-cf1204f9c6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496967536 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.2496967536
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.449824815
Short name T268
Test name
Test status
Simulation time 68147669 ps
CPU time 1.11 seconds
Started Jul 16 07:14:35 PM PDT 24
Finished Jul 16 07:15:03 PM PDT 24
Peak memory 219860 kb
Host smart-01fb13ae-0224-404e-8eb4-c47e979d8fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449824815 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.449824815
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.78568979
Short name T957
Test name
Test status
Simulation time 22800045 ps
CPU time 0.92 seconds
Started Jul 16 07:14:41 PM PDT 24
Finished Jul 16 07:15:16 PM PDT 24
Peak memory 218652 kb
Host smart-6b014f3f-e07a-4b9b-a7c9-7644025fc015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78568979 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.78568979
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.2324864866
Short name T796
Test name
Test status
Simulation time 80528772 ps
CPU time 3.06 seconds
Started Jul 16 07:14:30 PM PDT 24
Finished Jul 16 07:14:56 PM PDT 24
Peak memory 220240 kb
Host smart-9b8c5e60-c9f7-4ab2-8446-18a08e1c7e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324864866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.2324864866
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.4112244986
Short name T862
Test name
Test status
Simulation time 47293311 ps
CPU time 1.17 seconds
Started Jul 16 07:14:36 PM PDT 24
Finished Jul 16 07:15:06 PM PDT 24
Peak memory 220208 kb
Host smart-87001888-3aaf-4ad4-ad48-43e2e63ea4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112244986 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.4112244986
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.1715754663
Short name T7
Test name
Test status
Simulation time 24895909 ps
CPU time 1.05 seconds
Started Jul 16 07:14:37 PM PDT 24
Finished Jul 16 07:15:07 PM PDT 24
Peak memory 220036 kb
Host smart-f09a76e7-d210-4d2e-a9a6-d937a0ffbea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715754663 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.1715754663
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.3572594013
Short name T623
Test name
Test status
Simulation time 22840114 ps
CPU time 1.15 seconds
Started Jul 16 07:14:34 PM PDT 24
Finished Jul 16 07:15:00 PM PDT 24
Peak memory 220260 kb
Host smart-5e4924f1-119f-4bd5-9d28-84738c8422c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572594013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3572594013
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.4187083941
Short name T988
Test name
Test status
Simulation time 150161468 ps
CPU time 1.31 seconds
Started Jul 16 07:14:57 PM PDT 24
Finished Jul 16 07:15:46 PM PDT 24
Peak memory 218972 kb
Host smart-b1128dc1-3e7f-4c23-b71a-4455ce9d54d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187083941 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.4187083941
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.796392833
Short name T773
Test name
Test status
Simulation time 17967295 ps
CPU time 1.15 seconds
Started Jul 16 07:14:48 PM PDT 24
Finished Jul 16 07:15:29 PM PDT 24
Peak memory 224232 kb
Host smart-4517eea1-e6bd-4ee7-800c-00b8c0701cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796392833 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.796392833
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.1642132850
Short name T839
Test name
Test status
Simulation time 137360105 ps
CPU time 1.11 seconds
Started Jul 16 07:14:35 PM PDT 24
Finished Jul 16 07:15:03 PM PDT 24
Peak memory 217632 kb
Host smart-0fb60c51-e3bf-469e-8206-469d0f8659c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642132850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.1642132850
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.2132899838
Short name T632
Test name
Test status
Simulation time 86354715 ps
CPU time 1.14 seconds
Started Jul 16 07:14:50 PM PDT 24
Finished Jul 16 07:15:30 PM PDT 24
Peak memory 220048 kb
Host smart-9cc78c09-28f4-4456-9e59-740dc06323d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132899838 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.2132899838
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.1584917087
Short name T179
Test name
Test status
Simulation time 56073283 ps
CPU time 0.82 seconds
Started Jul 16 07:14:38 PM PDT 24
Finished Jul 16 07:15:07 PM PDT 24
Peak memory 219320 kb
Host smart-d578a929-bae3-48b7-a182-ce877caff1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584917087 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.1584917087
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.1018102767
Short name T924
Test name
Test status
Simulation time 83339406 ps
CPU time 1.1 seconds
Started Jul 16 07:14:49 PM PDT 24
Finished Jul 16 07:15:29 PM PDT 24
Peak memory 217632 kb
Host smart-7b779cc4-2e9a-4322-8b22-0e719252951e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018102767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.1018102767
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.3307472524
Short name T456
Test name
Test status
Simulation time 54104808 ps
CPU time 1.11 seconds
Started Jul 16 07:14:36 PM PDT 24
Finished Jul 16 07:15:06 PM PDT 24
Peak memory 216004 kb
Host smart-726c9f95-7cce-42a2-9324-de4e89054ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307472524 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.3307472524
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.850933378
Short name T642
Test name
Test status
Simulation time 34884580 ps
CPU time 1.17 seconds
Started Jul 16 07:14:37 PM PDT 24
Finished Jul 16 07:15:07 PM PDT 24
Peak memory 232424 kb
Host smart-ce9c2092-ba9c-4ffb-b485-0922b94868f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850933378 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.850933378
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.3104239795
Short name T411
Test name
Test status
Simulation time 70654996 ps
CPU time 1.13 seconds
Started Jul 16 07:14:35 PM PDT 24
Finished Jul 16 07:15:03 PM PDT 24
Peak memory 217676 kb
Host smart-f7f3e69a-7ab2-4d7a-95c9-402ba25b2d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104239795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.3104239795
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.3651777233
Short name T292
Test name
Test status
Simulation time 73288014 ps
CPU time 1.06 seconds
Started Jul 16 07:14:46 PM PDT 24
Finished Jul 16 07:15:23 PM PDT 24
Peak memory 218836 kb
Host smart-433b90b9-3b6d-49d6-ae37-bdb4b171c26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651777233 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.3651777233
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.2294700580
Short name T158
Test name
Test status
Simulation time 20683167 ps
CPU time 0.97 seconds
Started Jul 16 07:14:38 PM PDT 24
Finished Jul 16 07:15:09 PM PDT 24
Peak memory 224252 kb
Host smart-84844c4a-3145-4426-8f41-c9dcecede9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294700580 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.2294700580
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1826427825
Short name T869
Test name
Test status
Simulation time 165005639 ps
CPU time 2.24 seconds
Started Jul 16 07:14:49 PM PDT 24
Finished Jul 16 07:15:31 PM PDT 24
Peak memory 220660 kb
Host smart-7e2b20a1-4dee-46ef-9f5f-b65d75ce3a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826427825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1826427825
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.2433686522
Short name T491
Test name
Test status
Simulation time 21685649 ps
CPU time 1.08 seconds
Started Jul 16 07:14:52 PM PDT 24
Finished Jul 16 07:15:36 PM PDT 24
Peak memory 218588 kb
Host smart-cd2bedea-dcd4-4a0f-8b58-4cc34145ccb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433686522 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.2433686522
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.2301637331
Short name T475
Test name
Test status
Simulation time 19186473 ps
CPU time 1.02 seconds
Started Jul 16 07:14:38 PM PDT 24
Finished Jul 16 07:15:07 PM PDT 24
Peak memory 218872 kb
Host smart-6c56c70d-9856-442e-8ce6-a2beda98b38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301637331 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.2301637331
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.4198575060
Short name T545
Test name
Test status
Simulation time 253800143 ps
CPU time 1.77 seconds
Started Jul 16 07:14:52 PM PDT 24
Finished Jul 16 07:15:36 PM PDT 24
Peak memory 219152 kb
Host smart-3c7ffb27-c2cf-4943-9982-6a606d51d038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198575060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.4198575060
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.134258814
Short name T163
Test name
Test status
Simulation time 29472240 ps
CPU time 1.25 seconds
Started Jul 16 07:12:10 PM PDT 24
Finished Jul 16 07:13:27 PM PDT 24
Peak memory 220960 kb
Host smart-6de72eed-ba64-4c5e-aeb0-03f5107989e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134258814 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.134258814
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.692528792
Short name T768
Test name
Test status
Simulation time 41758468 ps
CPU time 0.86 seconds
Started Jul 16 07:12:16 PM PDT 24
Finished Jul 16 07:13:29 PM PDT 24
Peak memory 207092 kb
Host smart-fff1db8e-edb3-4c66-9033-3a22dfb5b211
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692528792 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.692528792
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.4062564286
Short name T211
Test name
Test status
Simulation time 41113340 ps
CPU time 0.86 seconds
Started Jul 16 07:12:10 PM PDT 24
Finished Jul 16 07:13:27 PM PDT 24
Peak memory 216576 kb
Host smart-43616859-c8ff-452a-81d2-0f0b98dce4b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062564286 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.4062564286
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.3742035203
Short name T117
Test name
Test status
Simulation time 59067364 ps
CPU time 0.97 seconds
Started Jul 16 07:12:17 PM PDT 24
Finished Jul 16 07:13:32 PM PDT 24
Peak memory 218768 kb
Host smart-35f4f90b-a82b-49f5-97a8-969873e48dd1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742035203 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.3742035203
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.2470298895
Short name T49
Test name
Test status
Simulation time 23861050 ps
CPU time 1.03 seconds
Started Jul 16 07:12:08 PM PDT 24
Finished Jul 16 07:13:26 PM PDT 24
Peak memory 224364 kb
Host smart-c56d8a1a-e197-498a-99ed-06a7f297efe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470298895 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.2470298895
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.102962377
Short name T598
Test name
Test status
Simulation time 50006080 ps
CPU time 1.19 seconds
Started Jul 16 07:12:08 PM PDT 24
Finished Jul 16 07:13:26 PM PDT 24
Peak memory 218696 kb
Host smart-e2408431-dfcf-49c5-8ef1-e8eded559ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102962377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.102962377
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2941667387
Short name T990
Test name
Test status
Simulation time 22915305 ps
CPU time 0.94 seconds
Started Jul 16 07:12:12 PM PDT 24
Finished Jul 16 07:13:28 PM PDT 24
Peak memory 216136 kb
Host smart-2a281d8b-d57e-4790-8591-3ab10b1389f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941667387 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2941667387
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.4011809699
Short name T25
Test name
Test status
Simulation time 18198419 ps
CPU time 1.01 seconds
Started Jul 16 07:12:12 PM PDT 24
Finished Jul 16 07:13:28 PM PDT 24
Peak memory 207372 kb
Host smart-dab8e661-2562-401e-93f3-0631ad1bab13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011809699 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.4011809699
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.2487023517
Short name T361
Test name
Test status
Simulation time 31839193 ps
CPU time 0.95 seconds
Started Jul 16 07:12:14 PM PDT 24
Finished Jul 16 07:13:27 PM PDT 24
Peak memory 215496 kb
Host smart-57fe4af8-f3a7-4e46-af67-7b0a11080898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487023517 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2487023517
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.372007744
Short name T84
Test name
Test status
Simulation time 450595145 ps
CPU time 3 seconds
Started Jul 16 07:12:10 PM PDT 24
Finished Jul 16 07:13:29 PM PDT 24
Peak memory 217528 kb
Host smart-fc76ccd3-0c20-4c7e-bdf5-5b6064af4080
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372007744 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.372007744
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.4159053728
Short name T965
Test name
Test status
Simulation time 42492968175 ps
CPU time 453.03 seconds
Started Jul 16 07:12:09 PM PDT 24
Finished Jul 16 07:20:59 PM PDT 24
Peak memory 219440 kb
Host smart-0a7e11c9-0682-4359-9545-ba959fa2440b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159053728 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.4159053728
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.2237913015
Short name T291
Test name
Test status
Simulation time 44799659 ps
CPU time 1.11 seconds
Started Jul 16 07:14:38 PM PDT 24
Finished Jul 16 07:15:09 PM PDT 24
Peak memory 219900 kb
Host smart-aea7688d-5f6b-4582-bec6-f61281b1dc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237913015 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.2237913015
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.2923914787
Short name T120
Test name
Test status
Simulation time 26421343 ps
CPU time 1.01 seconds
Started Jul 16 07:14:51 PM PDT 24
Finished Jul 16 07:15:33 PM PDT 24
Peak memory 224264 kb
Host smart-c8793fd7-494e-4aa4-ad63-33193c80b85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923914787 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.2923914787
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.1816014121
Short name T403
Test name
Test status
Simulation time 94407420 ps
CPU time 1.14 seconds
Started Jul 16 07:14:52 PM PDT 24
Finished Jul 16 07:15:34 PM PDT 24
Peak memory 217520 kb
Host smart-74df92cb-775e-4405-a270-59fc9f9f72ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816014121 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1816014121
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.2722775216
Short name T11
Test name
Test status
Simulation time 31350292 ps
CPU time 1.31 seconds
Started Jul 16 07:14:43 PM PDT 24
Finished Jul 16 07:15:17 PM PDT 24
Peak memory 220228 kb
Host smart-96f76eab-8784-40f2-ac9a-d89ca47a6abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722775216 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.2722775216
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.2769094486
Short name T202
Test name
Test status
Simulation time 58470982 ps
CPU time 1.12 seconds
Started Jul 16 07:14:41 PM PDT 24
Finished Jul 16 07:15:16 PM PDT 24
Peak memory 229772 kb
Host smart-58f50a79-679f-4f73-8ec7-e8235f4f56da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769094486 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.2769094486
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.2006566091
Short name T460
Test name
Test status
Simulation time 43085489 ps
CPU time 1.25 seconds
Started Jul 16 07:14:55 PM PDT 24
Finished Jul 16 07:15:40 PM PDT 24
Peak memory 217592 kb
Host smart-bca8c624-e30d-4b9c-a942-ea1b66a48ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006566091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.2006566091
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.2946592432
Short name T10
Test name
Test status
Simulation time 25373549 ps
CPU time 1.12 seconds
Started Jul 16 07:14:39 PM PDT 24
Finished Jul 16 07:15:09 PM PDT 24
Peak memory 220960 kb
Host smart-8b49ade7-6658-449f-8212-6de2511a8dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946592432 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.2946592432
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.1195341954
Short name T188
Test name
Test status
Simulation time 34817238 ps
CPU time 0.85 seconds
Started Jul 16 07:14:48 PM PDT 24
Finished Jul 16 07:15:29 PM PDT 24
Peak memory 218664 kb
Host smart-b1d0a03a-de43-47ee-a17c-89c79813941d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195341954 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.1195341954
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.1543595609
Short name T307
Test name
Test status
Simulation time 84949706 ps
CPU time 1.52 seconds
Started Jul 16 07:14:32 PM PDT 24
Finished Jul 16 07:14:58 PM PDT 24
Peak memory 218744 kb
Host smart-1010960d-1dbe-43f0-bd4c-dd005a36a9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543595609 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1543595609
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.2412504393
Short name T149
Test name
Test status
Simulation time 31369603 ps
CPU time 0.83 seconds
Started Jul 16 07:14:54 PM PDT 24
Finished Jul 16 07:15:36 PM PDT 24
Peak memory 218608 kb
Host smart-547aea6d-4876-41af-b436-f94fc0b8a07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412504393 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.2412504393
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.970163009
Short name T356
Test name
Test status
Simulation time 48235534 ps
CPU time 1.73 seconds
Started Jul 16 07:14:55 PM PDT 24
Finished Jul 16 07:15:41 PM PDT 24
Peak memory 218784 kb
Host smart-c98eafda-6910-4003-9caf-f12c385cb4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970163009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.970163009
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.2282413607
Short name T234
Test name
Test status
Simulation time 23604747 ps
CPU time 1.12 seconds
Started Jul 16 07:14:49 PM PDT 24
Finished Jul 16 07:15:30 PM PDT 24
Peak memory 218844 kb
Host smart-ed16876e-31d5-4f8c-a6e4-955a7c76e421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282413607 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.2282413607
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.2773784501
Short name T96
Test name
Test status
Simulation time 23852266 ps
CPU time 1.07 seconds
Started Jul 16 07:14:47 PM PDT 24
Finished Jul 16 07:15:28 PM PDT 24
Peak memory 229972 kb
Host smart-05658dc0-f597-4024-9b52-5e023d22b26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773784501 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.2773784501
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.307684359
Short name T688
Test name
Test status
Simulation time 35433345 ps
CPU time 1.26 seconds
Started Jul 16 07:14:41 PM PDT 24
Finished Jul 16 07:15:16 PM PDT 24
Peak memory 218696 kb
Host smart-a5a7185a-56ac-4ef4-bb9d-8654c344b7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307684359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.307684359
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.4211512168
Short name T237
Test name
Test status
Simulation time 93318836 ps
CPU time 1.16 seconds
Started Jul 16 07:14:41 PM PDT 24
Finished Jul 16 07:15:16 PM PDT 24
Peak memory 220772 kb
Host smart-cf69aa08-1d9c-45b9-a31a-f9cac61f8ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211512168 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.4211512168
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.4165622774
Short name T130
Test name
Test status
Simulation time 22323813 ps
CPU time 1.07 seconds
Started Jul 16 07:14:50 PM PDT 24
Finished Jul 16 07:15:32 PM PDT 24
Peak memory 220000 kb
Host smart-09f2ec4c-aa2c-421a-8d9c-9964bf940555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165622774 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.4165622774
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.9553359
Short name T875
Test name
Test status
Simulation time 90039275 ps
CPU time 1.45 seconds
Started Jul 16 07:14:39 PM PDT 24
Finished Jul 16 07:15:13 PM PDT 24
Peak memory 218852 kb
Host smart-1a4dcb62-8e66-41e4-bb81-c6e59b7967b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9553359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.9553359
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.1230945823
Short name T603
Test name
Test status
Simulation time 42257114 ps
CPU time 1.09 seconds
Started Jul 16 07:14:42 PM PDT 24
Finished Jul 16 07:15:17 PM PDT 24
Peak memory 220048 kb
Host smart-8079bfa9-cca2-4855-bc0f-b3e634d4c1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230945823 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.1230945823
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.2582650564
Short name T98
Test name
Test status
Simulation time 26373065 ps
CPU time 0.97 seconds
Started Jul 16 07:14:49 PM PDT 24
Finished Jul 16 07:15:29 PM PDT 24
Peak memory 219912 kb
Host smart-90e4686f-541e-43bd-a308-c3c82fbbbe6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582650564 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.2582650564
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.2709430425
Short name T703
Test name
Test status
Simulation time 41060219 ps
CPU time 1.44 seconds
Started Jul 16 07:14:40 PM PDT 24
Finished Jul 16 07:15:14 PM PDT 24
Peak memory 219028 kb
Host smart-862ac59c-9b9d-4f2f-b60c-785e0b69bd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709430425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.2709430425
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.2007226703
Short name T820
Test name
Test status
Simulation time 42612931 ps
CPU time 1.05 seconds
Started Jul 16 07:14:43 PM PDT 24
Finished Jul 16 07:15:19 PM PDT 24
Peak memory 219024 kb
Host smart-7766e563-91dd-46df-962b-2b1b93012f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007226703 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.2007226703
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.2227428542
Short name T143
Test name
Test status
Simulation time 19979295 ps
CPU time 1.05 seconds
Started Jul 16 07:14:51 PM PDT 24
Finished Jul 16 07:15:33 PM PDT 24
Peak memory 218684 kb
Host smart-a3794f94-747c-4469-8e48-1f7e765a6932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227428542 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.2227428542
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.2517089165
Short name T352
Test name
Test status
Simulation time 733244328 ps
CPU time 6.41 seconds
Started Jul 16 07:14:53 PM PDT 24
Finished Jul 16 07:15:41 PM PDT 24
Peak memory 218972 kb
Host smart-758c31b3-cfd0-47fb-b652-e251480c6ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517089165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.2517089165
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.721502576
Short name T213
Test name
Test status
Simulation time 27635286 ps
CPU time 1.24 seconds
Started Jul 16 07:14:35 PM PDT 24
Finished Jul 16 07:15:03 PM PDT 24
Peak memory 220280 kb
Host smart-4aeca450-0db1-446a-8395-df0b3b9581b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721502576 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.721502576
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.3004104439
Short name T47
Test name
Test status
Simulation time 45803443 ps
CPU time 1.21 seconds
Started Jul 16 07:14:34 PM PDT 24
Finished Jul 16 07:15:00 PM PDT 24
Peak memory 226072 kb
Host smart-e175e392-afbe-4464-8b63-2abbc0e0613e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004104439 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.3004104439
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.1768656184
Short name T718
Test name
Test status
Simulation time 37624610 ps
CPU time 1.37 seconds
Started Jul 16 07:14:42 PM PDT 24
Finished Jul 16 07:15:17 PM PDT 24
Peak memory 218988 kb
Host smart-05564ead-1b0e-49d0-b895-b11b8d8dfaa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768656184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.1768656184
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.2749526635
Short name T286
Test name
Test status
Simulation time 49746657 ps
CPU time 1.19 seconds
Started Jul 16 07:14:42 PM PDT 24
Finished Jul 16 07:15:17 PM PDT 24
Peak memory 218908 kb
Host smart-7dd8bf61-04d4-4f78-8c5a-4376539377c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749526635 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.2749526635
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_genbits.872947303
Short name T586
Test name
Test status
Simulation time 33279423 ps
CPU time 0.99 seconds
Started Jul 16 07:14:42 PM PDT 24
Finished Jul 16 07:15:17 PM PDT 24
Peak memory 217660 kb
Host smart-81d45f33-c767-41c9-83a1-3b248b9b6709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872947303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.872947303
Directory /workspace/99.edn_genbits/latest
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