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 LINE       302
 EXPRESSION (csrng_cmd_i.csrng_rsp_ack && sw_cmd_mode)
             ------------1------------    -----2-----
-1--2-StatusTests
01CoveredT1,T2,T6
10CoveredT2,T6,T10
11CoveredT2,T6,T22

 LINE       307
 EXPRESSION (sfifo_rescmd_int_err || sfifo_gencmd_int_err || edn_cntr_err_sum || edn_main_sm_err_sum || edn_ack_sm_err_sum)
             ----------1---------    ----------2---------    --------3-------    ---------4---------    ---------5--------
-1--2--3--4--5-StatusTests
00000CoveredT1,T2,T3
00001CoveredT1,T5,T78
00010CoveredT1,T7,T8
00100CoveredT1,T15,T16
01000CoveredT1,T17,T18
10000CoveredT1,T17,T18

 LINE       314
 EXPRESSION ((edn_enable_fo[FatalErr] && (sfifo_rescmd_err_sum || sfifo_gencmd_err_sum)) || fatal_loc_events)
             -------------------------------------1-------------------------------------    --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T5,T15
10CoveredT33,T34,T35

 LINE       314
 SUB-EXPRESSION (edn_enable_fo[FatalErr] && (sfifo_rescmd_err_sum || sfifo_gencmd_err_sum))
                 -----------1-----------    -----------------------2----------------------
-1--2-StatusTests
01CoveredT1,T33,T34
10CoveredT1,T2,T6
11CoveredT1,T33,T34

 LINE       314
 SUB-EXPRESSION (sfifo_rescmd_err_sum || sfifo_gencmd_err_sum)
                 ----------1---------    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T34,T35
10CoveredT1,T33,T17

 LINE       320
 EXPRESSION (((|sfifo_rescmd_err)) || err_code_test_bit[0])
             ----------1----------    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T33,T17

 LINE       322
 EXPRESSION (((|sfifo_gencmd_err)) || err_code_test_bit[1])
             ----------1----------    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T34,T35

 LINE       324
 EXPRESSION (((|edn_ack_sm_err)) || err_code_test_bit[20])
             ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T5,T15

 LINE       326
 EXPRESSION (edn_main_sm_err || err_code_test_bit[21])
             -------1-------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T5,T15

 LINE       328
 EXPRESSION (edn_cntr_err || err_code_test_bit[22])
             ------1-----    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T15,T16

 LINE       331
 EXPRESSION (sfifo_rescmd_err[2] || sfifo_gencmd_err[2] || err_code_test_bit[28])
             ---------1---------    ---------2---------    ----------3----------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010CoveredT36,T37,T38
100CoveredT79,T80

 LINE       335
 EXPRESSION (sfifo_rescmd_err[1] || sfifo_gencmd_err[1] || err_code_test_bit[29])
             ---------1---------    ---------2---------    ----------3----------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010CoveredT35,T40
100CoveredT39,T77

 LINE       339
 EXPRESSION (sfifo_rescmd_err[0] || sfifo_gencmd_err[0] || err_code_test_bit[30])
             ---------1---------    ---------2---------    ----------3----------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010CoveredT1,T34,T36
100CoveredT1,T33,T17

 LINE       347
 EXPRESSION (edn_enable_fo[ReseedCmdErr] && sfifo_rescmd_err_sum)
             -------------1-------------    ----------2---------
-1--2-StatusTests
01CoveredT1,T33,T17
10CoveredT1,T2,T6
11CoveredT1,T33,T17

 LINE       350
 EXPRESSION (edn_enable_fo[GenCmdErr] && sfifo_gencmd_err_sum)
             ------------1-----------    ----------2---------
-1--2-StatusTests
01CoveredT1,T34,T35
10CoveredT1,T2,T6
11CoveredT1,T34,T35

 LINE       367
 EXPRESSION (edn_enable_fo[FifoWrErr] && fifo_write_err_sum)
             ------------1-----------    ---------2--------
-1--2-StatusTests
01CoveredT36,T37,T38
10CoveredT1,T2,T6
11CoveredT36,T37,T38

 LINE       370
 EXPRESSION (edn_enable_fo[FifoRdErr] && fifo_read_err_sum)
             ------------1-----------    --------2--------
-1--2-StatusTests
01CoveredT35,T39,T40
10CoveredT1,T2,T6
11CoveredT35,T39,T40

 LINE       373
 EXPRESSION (edn_enable_fo[FifoStErr] && fifo_status_err_sum)
             ------------1-----------    ---------2---------
-1--2-StatusTests
01CoveredT1,T33,T34
10CoveredT1,T2,T6
11CoveredT1,T33,T34

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 0) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T22,T4
10CoveredT1,T2,T3
11Not Covered

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 0)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 1) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T22,T4
10Not Covered
11Not Covered

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 1)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 2) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T22,T4
10CoveredT4,T41,T42
11CoveredT4,T41,T42

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 2)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T41,T42

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 3) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T22,T4
10CoveredT4,T41,T42
11CoveredT4,T41,T42

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 3)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T41,T42

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 4) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T22,T4
10CoveredT4,T41,T42
11CoveredT4,T41,T42

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 4)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T41,T42

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 5) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T22,T4
10CoveredT4,T41,T42
11CoveredT4,T41,T42

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 5)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T41,T42

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 6) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T22,T4
10CoveredT41,T42,T81
11CoveredT41,T42,T81

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 6)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT41,T42,T81

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 7) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T22,T4
10CoveredT4,T16,T42
11CoveredT4,T16,T42

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 7)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T16,T42

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 8) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T22,T4
10CoveredT4,T15,T41
11CoveredT4,T15,T41

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 8)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T15,T41

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 9) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T22,T4
10CoveredT4,T41,T42
11CoveredT4,T41,T42

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 9)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T41,T42

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 10) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T22,T4
10CoveredT4,T41,T42
11CoveredT4,T41,T42

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 10)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T41,T42

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 11) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T22,T4
10CoveredT4,T41,T42
11CoveredT4,T41,T42

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 11)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T41,T42

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 12) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T22,T4
10CoveredT4,T16,T41
11CoveredT4,T16,T41

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 12)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T16,T41

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 13) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T22,T4
10CoveredT4,T41,T42
11CoveredT4,T41,T42

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 13)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T41,T42

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 14) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T22,T4
10CoveredT4,T41,T42
11CoveredT4,T41,T42

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 14)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T41,T42

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 15) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T22,T4
10CoveredT4,T30,T41
11CoveredT4,T30,T41

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 15)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T30,T41

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 16) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T22,T4
10CoveredT4,T41,T42
11CoveredT4,T41,T42

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 16)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T41,T42

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 17) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T22,T4
10CoveredT4,T41,T42
11CoveredT4,T41,T42

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 17)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T41,T42

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 18) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T22,T4
10CoveredT29,T15,T41
11CoveredT29,T15,T41

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 18)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT29,T15,T41

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 19) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T22,T4
10CoveredT4,T31,T42
11CoveredT4,T31,T42

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 19)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T31,T42

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 20) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T22,T4
10Not Covered
11Not Covered

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 20)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 21) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T22,T4
10Not Covered
11Not Covered

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 21)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 22) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T22,T4
10Not Covered
11Not Covered

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 22)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 23) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T22,T4
10CoveredT4,T41,T42
11CoveredT4,T41,T42

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 23)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T41,T42

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 24) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T22,T4
10CoveredT4,T42,T81
11CoveredT4,T42,T81

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 24)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T42,T81

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 25) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T22,T4
10CoveredT2,T4,T41
11CoveredT2,T4,T41

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 25)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T41

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 26) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T22,T4
10CoveredT2,T41,T42
11CoveredT2,T41,T42

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 26)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T41,T42

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 27) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T4,T29
10CoveredT22,T4,T42
11CoveredT22,T4,T42

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 27)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T4,T42

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 28) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T22,T4
10Not Covered
11Not Covered

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 28)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 29) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T22,T4
10Not Covered
11Not Covered

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 29)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 30) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T22,T4
10Not Covered
11Not Covered

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 30)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       382
 EXPRESSION (edn_enable_fo[CsrngAckErr] && csrng_cmd_i.csrng_rsp_ack && (csrng_cmd_i.csrng_rsp_sts != CMD_STS_SUCCESS))
             -------------1------------    ------------2------------    -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT32,T76,T62
101Not Covered
110CoveredT2,T6,T22
111CoveredT30,T31,T32

 LINE       382
 SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_sts != CMD_STS_SUCCESS)
                -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T31,T32

 LINE       388
 EXPRESSION (edn_bus_cmp_alert || cmd_fifo_rst_pfa || auto_req_mode_pfa || boot_req_mode_pfa || edn_enable_pfa || csrng_ack_err)
             --------1--------    --------2-------    --------3--------    --------4--------    -------5------    ------6------
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T2,T3
000001CoveredT30,T31,T32
000010CoveredT30,T63,T82
000100CoveredT31,T83,T72
001000CoveredT47,T84,T85
010000CoveredT32,T76,T86
100000CoveredT30,T31,T32

 LINE       407
 EXPRESSION (event_edn_fatal_err || sfifo_rescmd_int_err || sfifo_gencmd_int_err)
             ---------1---------    ----------2---------    ----------3---------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010Not Covered
100CoveredT1,T5,T15

 LINE       410
 SUB-EXPRESSION (reg2hw.alert_test.recov_alert.q && reg2hw.alert_test.recov_alert.qe)
                 ---------------1---------------    ----------------2---------------
-1--2-StatusTests
01CoveredT3,T23,T24
10CoveredT1,T2,T3
11CoveredT3,T23,T24

 LINE       414
 SUB-EXPRESSION (reg2hw.alert_test.fatal_alert.q && reg2hw.alert_test.fatal_alert.qe)
                 ---------------1---------------    ----------------2---------------
-1--2-StatusTests
01CoveredT3,T23,T24
10CoveredT1,T2,T3
11CoveredT3,T23,T24

 LINE       490
 EXPRESSION (reg2hw.sw_cmd_req.qe && cmd_reg_rdy_q)
             ----------1---------    ------2------
-1--2-StatusTests
01CoveredT1,T2,T6
10CoveredT10,T11,T19
11CoveredT2,T6,T22

 LINE       502
 EXPRESSION (cs_cmd_req_vld_out_q && send_cs_cmd_gated)
             ----------1---------    --------2--------
-1--2-StatusTests
01CoveredT2,T6,T22
10CoveredT2,T6,T22
11CoveredT2,T6,T22

 LINE       503
 EXPRESSION (cs_cmd_req_vld_out_q && send_gencmd_gated)
             ----------1---------    --------2--------
-1--2-StatusTests
01CoveredT2,T10,T11
10CoveredT2,T6,T22
11CoveredT2,T10,T11

 LINE       504
 EXPRESSION (cs_cmd_req_vld_out_q && send_rescmd_gated)
             ----------1---------    --------2--------
-1--2-StatusTests
01CoveredT2,T10,T11
10CoveredT2,T6,T22
11CoveredT2,T10,T11

 LINE       507
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[CsrngCmdReq])) ? '0 : (boot_wr_ins_cmd ? boot_ins_cmd : (boot_wr_gen_cmd ? boot_gen_cmd : (boot_wr_uni_cmd ? 32'b00000000000000000000000000000101 : (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q)))))
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT1,T2,T3

 LINE       507
 SUB-EXPRESSION 
 Number  Term
      1  boot_wr_ins_cmd ? boot_ins_cmd : (boot_wr_gen_cmd ? boot_gen_cmd : (boot_wr_uni_cmd ? 32'b00000000000000000000000000000101 : (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q))))
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT6,T29,T30

 LINE       507
 SUB-EXPRESSION (boot_wr_gen_cmd ? boot_gen_cmd : (boot_wr_uni_cmd ? 32'b00000000000000000000000000000101 : (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q)))
                 -------1-------
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT6,T29,T30

 LINE       507
 SUB-EXPRESSION (boot_wr_uni_cmd ? 32'b00000000000000000000000000000101 : (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q))
                 -------1-------
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT6,T29,T30

 LINE       507
 SUB-EXPRESSION (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q)
                 -------1-------
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT2,T6,T22

 LINE       516
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[CsrngCmdReqValid])) ? '0 : (cs_cmd_handshake ? '0 : ((sw_cmd_req_load || boot_wr_ins_cmd || boot_wr_gen_cmd || boot_wr_uni_cmd) ? 1'b1 : cs_cmd_req_vld_q)))
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT1,T2,T3

 LINE       516
 SUB-EXPRESSION (cs_cmd_handshake ? '0 : ((sw_cmd_req_load || boot_wr_ins_cmd || boot_wr_gen_cmd || boot_wr_uni_cmd) ? 1'b1 : cs_cmd_req_vld_q))
                 --------1-------
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT2,T6,T22

 LINE       516
 SUB-EXPRESSION ((sw_cmd_req_load || boot_wr_ins_cmd || boot_wr_gen_cmd || boot_wr_uni_cmd) ? 1'b1 : cs_cmd_req_vld_q)
                 -------------------------------------1------------------------------------
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT2,T6,T22

 LINE       516
 SUB-EXPRESSION (sw_cmd_req_load || boot_wr_ins_cmd || boot_wr_gen_cmd || boot_wr_uni_cmd)
                 -------1-------    -------2-------    -------3-------    -------4-------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T6
0001CoveredT6,T29,T30
0010CoveredT6,T29,T30
0100CoveredT6,T29,T30
1000CoveredT2,T6,T22

 LINE       523
 EXPRESSION (cs_cmd_req_vld_q && csrng_cmd_i.csrng_req_ready)
             --------1-------    -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T22
11CoveredT2,T6,T22

 LINE       527
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[CsrngCmdReqOut])) ? '0 : ((send_rescmd || capt_rescmd_fifo_cnt) ? (sfifo_rescmd_pop ? sfifo_rescmd_rdata : cs_cmd_req_out_q) : ((send_gencmd || capt_gencmd_fifo_cnt) ? (sfifo_gencmd_pop ? sfifo_gencmd_rdata : cs_cmd_req_out_q) : ((cs_cmd_req_vld_q && ((!cs_cmd_handshake))) ? cs_cmd_req_q : cs_cmd_req_out_q))))
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT1,T2,T3

 LINE       527
 SUB-EXPRESSION 
 Number  Term
      1  (send_rescmd || capt_rescmd_fifo_cnt) ? (sfifo_rescmd_pop ? sfifo_rescmd_rdata : cs_cmd_req_out_q) : ((send_gencmd || capt_gencmd_fifo_cnt) ? (sfifo_gencmd_pop ? sfifo_gencmd_rdata : cs_cmd_req_out_q) : ((cs_cmd_req_vld_q && ((!cs_cmd_handshake))) ? cs_cmd_req_q : cs_cmd_req_out_q)))
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT2,T10,T11

 LINE       527
 SUB-EXPRESSION (send_rescmd || capt_rescmd_fifo_cnt)
                 -----1-----    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T6
01CoveredT2,T10,T11
10CoveredT2,T10,T11

 LINE       527
 SUB-EXPRESSION (sfifo_rescmd_pop ? sfifo_rescmd_rdata : cs_cmd_req_out_q)
                 --------1-------
-1-StatusTests
0CoveredT2,T10,T11
1CoveredT2,T10,T11

 LINE       527
 SUB-EXPRESSION 
 Number  Term
      1  (send_gencmd || capt_gencmd_fifo_cnt) ? (sfifo_gencmd_pop ? sfifo_gencmd_rdata : cs_cmd_req_out_q) : ((cs_cmd_req_vld_q && ((!cs_cmd_handshake))) ? cs_cmd_req_q : cs_cmd_req_out_q))
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT2,T10,T11

 LINE       527
 SUB-EXPRESSION (send_gencmd || capt_gencmd_fifo_cnt)
                 -----1-----    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T6
01CoveredT2,T10,T11
10CoveredT2,T10,T11

 LINE       527
 SUB-EXPRESSION (sfifo_gencmd_pop ? sfifo_gencmd_rdata : cs_cmd_req_out_q)
                 --------1-------
-1-StatusTests
0CoveredT2,T10,T11
1CoveredT2,T10,T11

 LINE       527
 SUB-EXPRESSION ((cs_cmd_req_vld_q && ((!cs_cmd_handshake))) ? cs_cmd_req_q : cs_cmd_req_out_q)
                 ---------------------1---------------------
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT2,T6,T22

 LINE       527
 SUB-EXPRESSION (cs_cmd_req_vld_q && ((!cs_cmd_handshake)))
                 --------1-------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T6
10CoveredT2,T6,T22
11CoveredT2,T6,T22

 LINE       543
 EXPRESSION (((!edn_enable_fo[CsrngCmdReqValidOut])) ? 1'b0 : ((cs_cmd_req_vld_hold_q || cs_cmd_req_vld_out_q) && ((!csrng_cmd_i.csrng_req_ready))))
             -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT1,T2,T3

 LINE       543
 SUB-EXPRESSION ((cs_cmd_req_vld_hold_q || cs_cmd_req_vld_out_q) && ((!csrng_cmd_i.csrng_req_ready)))
                 -----------------------1-----------------------    ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T6
10CoveredT2,T6,T22
11CoveredT2,T6,T22

 LINE       543
 SUB-EXPRESSION (cs_cmd_req_vld_hold_q || cs_cmd_req_vld_out_q)
                 ----------1----------    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T6
01CoveredT2,T6,T22
10CoveredT87,T88,T89

 LINE       550
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[CsrngCmdReqValidOut])) ? '0 : (cmd_sent ? '0 : ((send_rescmd || capt_rescmd_fifo_cnt) ? 1'b1 : ((send_gencmd || capt_gencmd_fifo_cnt) ? 1'b1 : (cs_cmd_req_vld_q && ((!cs_cmd_handshake)))))))
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT1,T2,T3

 LINE       550
 SUB-EXPRESSION 
 Number  Term
      1  cmd_sent ? '0 : ((send_rescmd || capt_rescmd_fifo_cnt) ? 1'b1 : ((send_gencmd || capt_gencmd_fifo_cnt) ? 1'b1 : (cs_cmd_req_vld_q && ((!cs_cmd_handshake))))))
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT2,T10,T11

 LINE       550
 SUB-EXPRESSION ((send_rescmd || capt_rescmd_fifo_cnt) ? 1'b1 : ((send_gencmd || capt_gencmd_fifo_cnt) ? 1'b1 : (cs_cmd_req_vld_q && ((!cs_cmd_handshake)))))
                 ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT2,T10,T11

 LINE       550
 SUB-EXPRESSION (send_rescmd || capt_rescmd_fifo_cnt)
                 -----1-----    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T6
01CoveredT2,T10,T11
10CoveredT2,T10,T11

 LINE       550
 SUB-EXPRESSION ((send_gencmd || capt_gencmd_fifo_cnt) ? 1'b1 : (cs_cmd_req_vld_q && ((!cs_cmd_handshake))))
                 ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT2,T10,T11

 LINE       550
 SUB-EXPRESSION (send_gencmd || capt_gencmd_fifo_cnt)
                 -----1-----    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T6
01CoveredT2,T10,T11
10CoveredT2,T10,T11

 LINE       550
 SUB-EXPRESSION (cs_cmd_req_vld_q && ((!cs_cmd_handshake)))
                 --------1-------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T6
10CoveredT2,T6,T22
11CoveredT2,T6,T22

 LINE       558
 EXPRESSION ((cs_cmd_req_vld_out_q && ((!reject_csrng_entropy))) || cs_cmd_req_vld_hold_q)
             -------------------------1-------------------------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT30,T90,T91
10CoveredT2,T6,T22

 LINE       558
 SUB-EXPRESSION (cs_cmd_req_vld_out_q && ((!reject_csrng_entropy)))
                 ----------1---------    ------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T62,T90
11CoveredT2,T6,T22

 LINE       566
 EXPRESSION (((!sw_cmd_req_load)) && cmd_rdy_d && cmd_reg_rdy_d)
             ----------1---------    ----2----    ------3------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T6,T22
110CoveredT30,T32,T76
111CoveredT1,T2,T6

 LINE       570
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[SwCmdSts])) ? 1'b0 : (((!sw_cmd_mode)) ? 1'b0 : (reject_csrng_entropy ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q))))))
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT1,T2,T3

 LINE       570
 SUB-EXPRESSION 
 Number  Term
      1  ((!sw_cmd_mode)) ? 1'b0 : (reject_csrng_entropy ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q)))))
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT1,T2,T6

 LINE       570
 SUB-EXPRESSION (reject_csrng_entropy ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q))))
                 ----------1---------
-1-StatusTests
0CoveredT1,T2,T6
1Not Covered

 LINE       570
 SUB-EXPRESSION (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q)))
                 -------1-------
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT2,T6,T22

 LINE       570
 SUB-EXPRESSION (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q))
                 ----------1---------
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT1,T2,T6

 LINE       570
 SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT2,T6,T22

 LINE       582
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[SwCmdSts])) ? 1'b0 : (((!sw_cmd_mode)) ? 1'b0 : (reject_csrng_entropy ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q))))))
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT1,T2,T3

 LINE       582
 SUB-EXPRESSION 
 Number  Term
      1  ((!sw_cmd_mode)) ? 1'b0 : (reject_csrng_entropy ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q)))))
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT1,T2,T6

 LINE       582
 SUB-EXPRESSION (reject_csrng_entropy ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q))))
                 ----------1---------
-1-StatusTests
0CoveredT1,T2,T6
1Not Covered

 LINE       582
 SUB-EXPRESSION (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q)))
                 -------1-------
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT2,T6,T22

 LINE       582
 SUB-EXPRESSION (accept_sw_cmds_pulse ? 1'b1 : (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q))
                 ----------1---------
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT1,T2,T6

 LINE       582
 SUB-EXPRESSION (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q)
                 --------1-------
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT2,T6,T22

 LINE       594
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[SwCmdSts])) ? CMD_STS_SUCCESS : ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_mode && ((!reject_csrng_entropy))) ? csrng_cmd_i.csrng_rsp_sts : csrng_cmd_sts_q))
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT1,T2,T3

 LINE       594
 SUB-EXPRESSION ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_mode && ((!reject_csrng_entropy))) ? csrng_cmd_i.csrng_rsp_sts : csrng_cmd_sts_q)
                 -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT2,T6,T22

 LINE       594
 SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_ack && sw_cmd_mode && ((!reject_csrng_entropy)))
                 ------------1------------    -----2-----    ------------3------------
-1--2--3-StatusTests
011CoveredT1,T2,T6
101CoveredT2,T6,T10
110Not Covered
111CoveredT2,T6,T22

 LINE       603
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[SwCmdSts])) ? 1'b0 : (sw_cmd_req_load ? 1'b0 : ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_mode && ((!reject_csrng_entropy))) ? 1'b1 : csrng_sw_cmd_ack_q)))
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT1,T2,T3

 LINE       603
 SUB-EXPRESSION (sw_cmd_req_load ? 1'b0 : ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_mode && ((!reject_csrng_entropy))) ? 1'b1 : csrng_sw_cmd_ack_q))
                 -------1-------
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT2,T6,T22

 LINE       603
 SUB-EXPRESSION ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_mode && ((!reject_csrng_entropy))) ? 1'b1 : csrng_sw_cmd_ack_q)
                 -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT2,T6,T22

 LINE       603
 SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_ack && sw_cmd_mode && ((!reject_csrng_entropy)))
                 ------------1------------    -----2-----    ------------3------------
-1--2--3-StatusTests
011CoveredT1,T2,T6
101CoveredT2,T6,T10
110Not Covered
111CoveredT2,T6,T22

 LINE       612
 EXPRESSION (edn_main_sm_state == Idle)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       613
 EXPRESSION (((!sw_cmd_mode)) && csrng_cmd_o.csrng_req_valid && csrng_cmd_i.csrng_req_ready)
             --------1-------    -------------2-------------    -------------3-------------
-1--2--3-StatusTests
011CoveredT2,T6,T22
101CoveredT1,T2,T3
110CoveredT2,T6,T10
111CoveredT2,T6,T10

 LINE       615
 EXPRESSION (cs_hw_cmd_handshake && ((send_rescmd || capt_rescmd_fifo_cnt || send_gencmd || capt_gencmd_fifo_cnt) ? cmd_hdr_busy_q : 1'b1))
             ---------1---------    ---------------------------------------------------2--------------------------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T10,T11
11CoveredT2,T6,T10

 LINE       615
 SUB-EXPRESSION ((send_rescmd || capt_rescmd_fifo_cnt || send_gencmd || capt_gencmd_fifo_cnt) ? cmd_hdr_busy_q : 1'b1)
                 --------------------------------------1-------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T10,T11

 LINE       615
 SUB-EXPRESSION (send_rescmd || capt_rescmd_fifo_cnt || send_gencmd || capt_gencmd_fifo_cnt)
                 -----1-----    ----------2---------    -----3-----    ----------4---------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT2,T10,T11
0010CoveredT2,T10,T11
0100CoveredT2,T10,T11
1000CoveredT2,T10,T11

 LINE       622
 EXPRESSION ((main_sm_done_pulse || main_sm_idle) ? 1'b0 : ((boot_send_ins_cmd && cs_hw_cmd_handshake) ? 1'b1 : boot_mode_q))
             ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT1,T2,T3

 LINE       622
 SUB-EXPRESSION (main_sm_done_pulse || main_sm_idle)
                 ---------1--------    ------2-----
-1--2-StatusTests
00CoveredT1,T2,T6
01CoveredT1,T2,T3
10CoveredT2,T6,T10

 LINE       622
 SUB-EXPRESSION ((boot_send_ins_cmd && cs_hw_cmd_handshake) ? 1'b1 : boot_mode_q)
                 ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT6,T29,T30

 LINE       622
 SUB-EXPRESSION (boot_send_ins_cmd && cs_hw_cmd_handshake)
                 --------1--------    ---------2---------
-1--2-StatusTests
01CoveredT2,T6,T10
10CoveredT6,T29,T30
11CoveredT6,T29,T30

 LINE       630
 EXPRESSION ((main_sm_done_pulse || main_sm_idle) ? 1'b0 : ((auto_req_mode_busy && cs_hw_cmd_handshake) ? 1'b1 : auto_mode_q))
             ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT1,T2,T3

 LINE       630
 SUB-EXPRESSION (main_sm_done_pulse || main_sm_idle)
                 ---------1--------    ------2-----
-1--2-StatusTests
00CoveredT1,T2,T6
01CoveredT1,T2,T3
10CoveredT2,T6,T10

 LINE       630
 SUB-EXPRESSION ((auto_req_mode_busy && cs_hw_cmd_handshake) ? 1'b1 : auto_mode_q)
                 ---------------------1---------------------
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT2,T10,T11

 LINE       630
 SUB-EXPRESSION (auto_req_mode_busy && cs_hw_cmd_handshake)
                 ---------1--------    ---------2---------
-1--2-StatusTests
01CoveredT6,T29,T30
10CoveredT2,T10,T11
11CoveredT2,T10,T11

 LINE       638
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[HwCmdSts])) ? CMD_STS_SUCCESS : ((csrng_cmd_i.csrng_rsp_ack && ((!sw_cmd_mode)) && ((!reject_csrng_entropy))) ? csrng_cmd_i.csrng_rsp_sts : (reject_csrng_entropy ? csrng_hw_cmd_sts_q : (cs_hw_cmd_handshake ? CMD_STS_SUCCESS : csrng_hw_cmd_sts_q))))
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT1,T2,T3

 LINE       638
 SUB-EXPRESSION 
 Number  Term
      1  (csrng_cmd_i.csrng_rsp_ack && ((!sw_cmd_mode)) && ((!reject_csrng_entropy))) ? csrng_cmd_i.csrng_rsp_sts : (reject_csrng_entropy ? csrng_hw_cmd_sts_q : (cs_hw_cmd_handshake ? CMD_STS_SUCCESS : csrng_hw_cmd_sts_q)))
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT2,T6,T10

 LINE       638
 SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_ack && ((!sw_cmd_mode)) && ((!reject_csrng_entropy)))
                 ------------1------------    --------2-------    ------------3------------
-1--2--3-StatusTests
011CoveredT1,T2,T6
101CoveredT2,T6,T22
110CoveredT30,T31,T32
111CoveredT2,T6,T10

 LINE       638
 SUB-EXPRESSION (reject_csrng_entropy ? csrng_hw_cmd_sts_q : (cs_hw_cmd_handshake ? CMD_STS_SUCCESS : csrng_hw_cmd_sts_q))
                 ----------1---------
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT30,T31,T32

 LINE       638
 SUB-EXPRESSION (cs_hw_cmd_handshake ? CMD_STS_SUCCESS : csrng_hw_cmd_sts_q)
                 ---------1---------
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT2,T6,T10

 LINE       650
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[HwCmdSts])) ? 1'b0 : ((csrng_cmd_i.csrng_rsp_ack && ((!sw_cmd_mode)) && ((!reject_csrng_entropy))) ? 1'b1 : (reject_csrng_entropy ? csrng_hw_cmd_ack_q : (cs_hw_cmd_handshake ? 1'b0 : csrng_hw_cmd_ack_q))))
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT1,T2,T3

 LINE       650
 SUB-EXPRESSION 
 Number  Term
      1  (csrng_cmd_i.csrng_rsp_ack && ((!sw_cmd_mode)) && ((!reject_csrng_entropy))) ? 1'b1 : (reject_csrng_entropy ? csrng_hw_cmd_ack_q : (cs_hw_cmd_handshake ? 1'b0 : csrng_hw_cmd_ack_q)))
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT2,T6,T10

 LINE       650
 SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_ack && ((!sw_cmd_mode)) && ((!reject_csrng_entropy)))
                 ------------1------------    --------2-------    ------------3------------
-1--2--3-StatusTests
011CoveredT1,T2,T6
101CoveredT2,T6,T22
110CoveredT30,T31,T32
111CoveredT2,T6,T10

 LINE       650
 SUB-EXPRESSION (reject_csrng_entropy ? csrng_hw_cmd_ack_q : (cs_hw_cmd_handshake ? 1'b0 : csrng_hw_cmd_ack_q))
                 ----------1---------
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT30,T31,T32

 LINE       650
 SUB-EXPRESSION (cs_hw_cmd_handshake ? 1'b0 : csrng_hw_cmd_ack_q)
                 ---------1---------
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT2,T6,T10

 LINE       661
 EXPRESSION (((!edn_enable_fo[HwCmdSts])) ? ({1'b0, INV}) : (reject_csrng_entropy ? cmd_type_q : (cs_hw_cmd_handshake_1st ? cs_cmd_req_out_q[3:0] : cmd_type_q)))
             --------------1-------------
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT1,T2,T3

 LINE       661
 SUB-EXPRESSION (reject_csrng_entropy ? cmd_type_q : (cs_hw_cmd_handshake_1st ? cs_cmd_req_out_q[3:0] : cmd_type_q))
                 ----------1---------
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT30,T31,T32

 LINE       661
 SUB-EXPRESSION (cs_hw_cmd_handshake_1st ? cs_cmd_req_out_q[3:0] : cmd_type_q)
                 -----------1-----------
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT2,T6,T10
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%