Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.61 98.25 93.91 97.02 91.86 96.37 99.77 92.08


Total test records in report: 1129
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T1017 /workspace/coverage/cover_reg_top/1.edn_tl_errors.3394146321 Jul 17 06:59:35 PM PDT 24 Jul 17 06:59:41 PM PDT 24 57102235 ps
T1018 /workspace/coverage/cover_reg_top/13.edn_intr_test.3133347891 Jul 17 07:00:32 PM PDT 24 Jul 17 07:00:37 PM PDT 24 68652520 ps
T1019 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.57143369 Jul 17 06:59:43 PM PDT 24 Jul 17 06:59:48 PM PDT 24 132321388 ps
T1020 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.919442211 Jul 17 07:00:28 PM PDT 24 Jul 17 07:00:30 PM PDT 24 16044727 ps
T247 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3109319392 Jul 17 06:59:42 PM PDT 24 Jul 17 06:59:46 PM PDT 24 62049464 ps
T1021 /workspace/coverage/cover_reg_top/13.edn_tl_errors.589885846 Jul 17 07:00:31 PM PDT 24 Jul 17 07:00:38 PM PDT 24 268920996 ps
T256 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2586303415 Jul 17 06:59:41 PM PDT 24 Jul 17 06:59:46 PM PDT 24 238860914 ps
T1022 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3992291776 Jul 17 06:59:42 PM PDT 24 Jul 17 06:59:49 PM PDT 24 112680193 ps
T1023 /workspace/coverage/cover_reg_top/3.edn_tl_errors.1791864311 Jul 17 06:59:41 PM PDT 24 Jul 17 06:59:47 PM PDT 24 66811555 ps
T1024 /workspace/coverage/cover_reg_top/12.edn_intr_test.3737916830 Jul 17 07:00:34 PM PDT 24 Jul 17 07:00:38 PM PDT 24 111811012 ps
T235 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.186112431 Jul 17 06:59:41 PM PDT 24 Jul 17 06:59:45 PM PDT 24 56656214 ps
T1025 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3465107542 Jul 17 07:00:32 PM PDT 24 Jul 17 07:00:37 PM PDT 24 24574338 ps
T1026 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3385020979 Jul 17 07:00:25 PM PDT 24 Jul 17 07:00:27 PM PDT 24 106934449 ps
T1027 /workspace/coverage/cover_reg_top/26.edn_intr_test.1289689288 Jul 17 07:01:51 PM PDT 24 Jul 17 07:01:54 PM PDT 24 12885594 ps
T1028 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3243757224 Jul 17 07:00:29 PM PDT 24 Jul 17 07:00:32 PM PDT 24 55125758 ps
T265 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.10330716 Jul 17 07:00:32 PM PDT 24 Jul 17 07:00:38 PM PDT 24 54603386 ps
T1029 /workspace/coverage/cover_reg_top/33.edn_intr_test.2967113422 Jul 17 07:01:51 PM PDT 24 Jul 17 07:01:55 PM PDT 24 14425382 ps
T1030 /workspace/coverage/cover_reg_top/19.edn_csr_rw.292081437 Jul 17 07:00:32 PM PDT 24 Jul 17 07:00:37 PM PDT 24 14666897 ps
T1031 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1303855119 Jul 17 07:00:31 PM PDT 24 Jul 17 07:00:36 PM PDT 24 82072160 ps
T1032 /workspace/coverage/cover_reg_top/23.edn_intr_test.3873436245 Jul 17 07:01:49 PM PDT 24 Jul 17 07:01:51 PM PDT 24 24378019 ps
T1033 /workspace/coverage/cover_reg_top/10.edn_tl_errors.2888885634 Jul 17 07:00:30 PM PDT 24 Jul 17 07:00:38 PM PDT 24 419625735 ps
T1034 /workspace/coverage/cover_reg_top/3.edn_csr_rw.1966201841 Jul 17 06:59:42 PM PDT 24 Jul 17 06:59:46 PM PDT 24 15332105 ps
T1035 /workspace/coverage/cover_reg_top/10.edn_intr_test.2200244715 Jul 17 07:00:31 PM PDT 24 Jul 17 07:00:37 PM PDT 24 33085925 ps
T1036 /workspace/coverage/cover_reg_top/2.edn_csr_rw.2933537235 Jul 17 06:59:44 PM PDT 24 Jul 17 06:59:48 PM PDT 24 13867805 ps
T1037 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3495844161 Jul 17 07:00:28 PM PDT 24 Jul 17 07:00:31 PM PDT 24 39292666 ps
T248 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1359971241 Jul 17 07:00:29 PM PDT 24 Jul 17 07:00:32 PM PDT 24 32381417 ps
T1038 /workspace/coverage/cover_reg_top/1.edn_intr_test.2967315439 Jul 17 06:59:42 PM PDT 24 Jul 17 06:59:46 PM PDT 24 52280028 ps
T1039 /workspace/coverage/cover_reg_top/9.edn_tl_errors.167532787 Jul 17 07:00:30 PM PDT 24 Jul 17 07:00:37 PM PDT 24 127003071 ps
T1040 /workspace/coverage/cover_reg_top/47.edn_intr_test.380463284 Jul 17 07:01:51 PM PDT 24 Jul 17 07:01:55 PM PDT 24 41993148 ps
T1041 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.730984632 Jul 17 07:00:33 PM PDT 24 Jul 17 07:00:38 PM PDT 24 22655559 ps
T262 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3923630811 Jul 17 07:00:30 PM PDT 24 Jul 17 07:00:36 PM PDT 24 132292826 ps
T1042 /workspace/coverage/cover_reg_top/14.edn_csr_rw.913315949 Jul 17 07:00:31 PM PDT 24 Jul 17 07:00:35 PM PDT 24 59948522 ps
T1043 /workspace/coverage/cover_reg_top/18.edn_intr_test.471439957 Jul 17 07:00:26 PM PDT 24 Jul 17 07:00:28 PM PDT 24 44948053 ps
T1044 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3337479238 Jul 17 07:00:27 PM PDT 24 Jul 17 07:00:29 PM PDT 24 75009144 ps
T1045 /workspace/coverage/cover_reg_top/44.edn_intr_test.2583466341 Jul 17 07:01:51 PM PDT 24 Jul 17 07:01:54 PM PDT 24 21243403 ps
T1046 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2174488653 Jul 17 07:00:29 PM PDT 24 Jul 17 07:00:33 PM PDT 24 29192808 ps
T236 /workspace/coverage/cover_reg_top/8.edn_csr_rw.3110129837 Jul 17 07:00:31 PM PDT 24 Jul 17 07:00:36 PM PDT 24 17910332 ps
T1047 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2763737682 Jul 17 07:00:32 PM PDT 24 Jul 17 07:00:38 PM PDT 24 103577763 ps
T1048 /workspace/coverage/cover_reg_top/9.edn_csr_rw.3149122879 Jul 17 07:00:28 PM PDT 24 Jul 17 07:00:31 PM PDT 24 47922319 ps
T1049 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3662292997 Jul 17 06:59:39 PM PDT 24 Jul 17 06:59:45 PM PDT 24 33699393 ps
T1050 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1901103760 Jul 17 07:00:32 PM PDT 24 Jul 17 07:00:37 PM PDT 24 32585689 ps
T1051 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.35044582 Jul 17 07:00:30 PM PDT 24 Jul 17 07:00:34 PM PDT 24 37633729 ps
T1052 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.938095332 Jul 17 07:00:28 PM PDT 24 Jul 17 07:00:31 PM PDT 24 76987266 ps
T1053 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.941159886 Jul 17 07:00:28 PM PDT 24 Jul 17 07:00:30 PM PDT 24 54369674 ps
T1054 /workspace/coverage/cover_reg_top/36.edn_intr_test.4053672655 Jul 17 07:01:47 PM PDT 24 Jul 17 07:01:48 PM PDT 24 35781294 ps
T266 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2334191281 Jul 17 07:00:31 PM PDT 24 Jul 17 07:00:37 PM PDT 24 188426291 ps
T1055 /workspace/coverage/cover_reg_top/22.edn_intr_test.2315770688 Jul 17 07:01:52 PM PDT 24 Jul 17 07:01:56 PM PDT 24 24757422 ps
T1056 /workspace/coverage/cover_reg_top/11.edn_csr_rw.3428859651 Jul 17 07:00:31 PM PDT 24 Jul 17 07:00:35 PM PDT 24 15275931 ps
T1057 /workspace/coverage/cover_reg_top/39.edn_intr_test.4113335248 Jul 17 07:01:51 PM PDT 24 Jul 17 07:01:55 PM PDT 24 16025374 ps
T1058 /workspace/coverage/cover_reg_top/41.edn_intr_test.2221834869 Jul 17 07:01:37 PM PDT 24 Jul 17 07:01:39 PM PDT 24 17228939 ps
T1059 /workspace/coverage/cover_reg_top/11.edn_tl_errors.1953705490 Jul 17 07:00:30 PM PDT 24 Jul 17 07:00:36 PM PDT 24 96868281 ps
T1060 /workspace/coverage/cover_reg_top/46.edn_intr_test.3260121484 Jul 17 07:01:50 PM PDT 24 Jul 17 07:01:53 PM PDT 24 27078802 ps
T1061 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1819434640 Jul 17 07:00:30 PM PDT 24 Jul 17 07:00:35 PM PDT 24 43703269 ps
T237 /workspace/coverage/cover_reg_top/6.edn_csr_rw.20456129 Jul 17 07:00:28 PM PDT 24 Jul 17 07:00:30 PM PDT 24 12085404 ps
T238 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3131551840 Jul 17 07:00:30 PM PDT 24 Jul 17 07:00:34 PM PDT 24 41314696 ps
T1062 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.180969329 Jul 17 07:00:32 PM PDT 24 Jul 17 07:00:37 PM PDT 24 27846439 ps
T1063 /workspace/coverage/cover_reg_top/35.edn_intr_test.1459922038 Jul 17 07:01:50 PM PDT 24 Jul 17 07:01:53 PM PDT 24 32127437 ps
T1064 /workspace/coverage/cover_reg_top/5.edn_csr_rw.4013174686 Jul 17 07:00:27 PM PDT 24 Jul 17 07:00:28 PM PDT 24 14779720 ps
T1065 /workspace/coverage/cover_reg_top/6.edn_intr_test.3686222029 Jul 17 07:00:29 PM PDT 24 Jul 17 07:00:33 PM PDT 24 13210461 ps
T1066 /workspace/coverage/cover_reg_top/40.edn_intr_test.667216427 Jul 17 07:01:52 PM PDT 24 Jul 17 07:01:57 PM PDT 24 36982256 ps
T1067 /workspace/coverage/cover_reg_top/0.edn_csr_rw.4202358918 Jul 17 06:59:36 PM PDT 24 Jul 17 06:59:41 PM PDT 24 36990201 ps
T1068 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.723144385 Jul 17 07:00:29 PM PDT 24 Jul 17 07:00:31 PM PDT 24 20503289 ps
T1069 /workspace/coverage/cover_reg_top/19.edn_intr_test.3741904346 Jul 17 07:00:31 PM PDT 24 Jul 17 07:00:36 PM PDT 24 14061238 ps
T1070 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2099954766 Jul 17 06:59:45 PM PDT 24 Jul 17 06:59:50 PM PDT 24 26460998 ps
T1071 /workspace/coverage/cover_reg_top/0.edn_intr_test.1773297564 Jul 17 06:59:38 PM PDT 24 Jul 17 06:59:42 PM PDT 24 42306450 ps
T1072 /workspace/coverage/cover_reg_top/15.edn_tl_errors.3178842361 Jul 17 07:00:29 PM PDT 24 Jul 17 07:00:35 PM PDT 24 737272253 ps
T1073 /workspace/coverage/cover_reg_top/17.edn_intr_test.372026033 Jul 17 07:00:33 PM PDT 24 Jul 17 07:00:38 PM PDT 24 24509360 ps
T1074 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3785300446 Jul 17 06:59:42 PM PDT 24 Jul 17 06:59:46 PM PDT 24 85157225 ps
T1075 /workspace/coverage/cover_reg_top/13.edn_csr_rw.3697218075 Jul 17 07:00:31 PM PDT 24 Jul 17 07:00:36 PM PDT 24 22338161 ps
T1076 /workspace/coverage/cover_reg_top/6.edn_tl_errors.2863369217 Jul 17 07:00:27 PM PDT 24 Jul 17 07:00:31 PM PDT 24 106163995 ps
T1077 /workspace/coverage/cover_reg_top/5.edn_tl_errors.553029535 Jul 17 07:00:31 PM PDT 24 Jul 17 07:00:38 PM PDT 24 186263372 ps
T1078 /workspace/coverage/cover_reg_top/2.edn_tl_errors.1627673914 Jul 17 06:59:44 PM PDT 24 Jul 17 06:59:51 PM PDT 24 270446657 ps
T1079 /workspace/coverage/cover_reg_top/32.edn_intr_test.3746451778 Jul 17 07:01:53 PM PDT 24 Jul 17 07:01:58 PM PDT 24 35463721 ps
T1080 /workspace/coverage/cover_reg_top/45.edn_intr_test.2239634837 Jul 17 07:01:55 PM PDT 24 Jul 17 07:02:03 PM PDT 24 27414698 ps
T1081 /workspace/coverage/cover_reg_top/0.edn_tl_errors.1393891273 Jul 17 06:59:37 PM PDT 24 Jul 17 06:59:43 PM PDT 24 456899050 ps
T1082 /workspace/coverage/cover_reg_top/17.edn_tl_errors.699951721 Jul 17 07:00:31 PM PDT 24 Jul 17 07:00:38 PM PDT 24 977570489 ps
T1083 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3238987956 Jul 17 07:00:31 PM PDT 24 Jul 17 07:00:36 PM PDT 24 24671807 ps
T1084 /workspace/coverage/cover_reg_top/49.edn_intr_test.2786710495 Jul 17 07:01:52 PM PDT 24 Jul 17 07:01:56 PM PDT 24 72369529 ps
T1085 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3197339716 Jul 17 07:00:32 PM PDT 24 Jul 17 07:00:38 PM PDT 24 363728541 ps
T263 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.942820174 Jul 17 07:00:27 PM PDT 24 Jul 17 07:00:29 PM PDT 24 89381251 ps
T1086 /workspace/coverage/cover_reg_top/20.edn_intr_test.1271138993 Jul 17 07:01:50 PM PDT 24 Jul 17 07:01:53 PM PDT 24 18504577 ps
T1087 /workspace/coverage/cover_reg_top/3.edn_intr_test.1211529877 Jul 17 06:59:44 PM PDT 24 Jul 17 06:59:48 PM PDT 24 15176235 ps
T1088 /workspace/coverage/cover_reg_top/5.edn_intr_test.4257777421 Jul 17 07:00:29 PM PDT 24 Jul 17 07:00:32 PM PDT 24 45629099 ps
T1089 /workspace/coverage/cover_reg_top/18.edn_csr_rw.1832439188 Jul 17 07:00:30 PM PDT 24 Jul 17 07:00:35 PM PDT 24 51343417 ps
T267 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.324731410 Jul 17 06:59:34 PM PDT 24 Jul 17 06:59:38 PM PDT 24 244120076 ps
T239 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.4283272428 Jul 17 06:59:40 PM PDT 24 Jul 17 06:59:44 PM PDT 24 15880969 ps
T1090 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3826672352 Jul 17 07:00:32 PM PDT 24 Jul 17 07:00:37 PM PDT 24 35630989 ps
T264 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1130558158 Jul 17 07:00:26 PM PDT 24 Jul 17 07:00:29 PM PDT 24 278047268 ps
T1091 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1625794443 Jul 17 07:00:31 PM PDT 24 Jul 17 07:00:38 PM PDT 24 282139729 ps
T1092 /workspace/coverage/cover_reg_top/2.edn_intr_test.4232190787 Jul 17 06:59:44 PM PDT 24 Jul 17 06:59:48 PM PDT 24 15269561 ps
T1093 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2724899740 Jul 17 07:00:33 PM PDT 24 Jul 17 07:00:39 PM PDT 24 188105363 ps
T1094 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1147668688 Jul 17 07:00:32 PM PDT 24 Jul 17 07:00:37 PM PDT 24 21303449 ps
T1095 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2724270991 Jul 17 06:59:35 PM PDT 24 Jul 17 06:59:39 PM PDT 24 17366597 ps
T1096 /workspace/coverage/cover_reg_top/29.edn_intr_test.3963272778 Jul 17 07:01:53 PM PDT 24 Jul 17 07:01:59 PM PDT 24 19585224 ps
T1097 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2113057495 Jul 17 06:59:42 PM PDT 24 Jul 17 06:59:47 PM PDT 24 37664363 ps
T1098 /workspace/coverage/cover_reg_top/11.edn_intr_test.1469764076 Jul 17 07:00:28 PM PDT 24 Jul 17 07:00:29 PM PDT 24 14910565 ps
T1099 /workspace/coverage/cover_reg_top/28.edn_intr_test.2788240165 Jul 17 07:01:53 PM PDT 24 Jul 17 07:01:57 PM PDT 24 114710173 ps
T1100 /workspace/coverage/cover_reg_top/8.edn_intr_test.3900054998 Jul 17 07:00:31 PM PDT 24 Jul 17 07:00:36 PM PDT 24 14450217 ps
T1101 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.110125165 Jul 17 06:59:44 PM PDT 24 Jul 17 06:59:53 PM PDT 24 181345829 ps
T240 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1776127303 Jul 17 06:59:37 PM PDT 24 Jul 17 06:59:41 PM PDT 24 26081147 ps
T1102 /workspace/coverage/cover_reg_top/10.edn_csr_rw.3529501036 Jul 17 07:00:28 PM PDT 24 Jul 17 07:00:30 PM PDT 24 35167652 ps
T1103 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1219550799 Jul 17 06:59:40 PM PDT 24 Jul 17 06:59:45 PM PDT 24 110042416 ps
T1104 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1533658318 Jul 17 07:00:31 PM PDT 24 Jul 17 07:00:36 PM PDT 24 48168934 ps
T1105 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.335415882 Jul 17 07:00:33 PM PDT 24 Jul 17 07:00:40 PM PDT 24 112191245 ps
T1106 /workspace/coverage/cover_reg_top/4.edn_intr_test.3459629589 Jul 17 06:59:42 PM PDT 24 Jul 17 06:59:47 PM PDT 24 15354687 ps
T1107 /workspace/coverage/cover_reg_top/17.edn_csr_rw.177722267 Jul 17 07:00:33 PM PDT 24 Jul 17 07:00:38 PM PDT 24 24472349 ps
T1108 /workspace/coverage/cover_reg_top/12.edn_tl_errors.3783053647 Jul 17 07:00:30 PM PDT 24 Jul 17 07:00:35 PM PDT 24 26920360 ps
T1109 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3130690345 Jul 17 06:59:42 PM PDT 24 Jul 17 06:59:46 PM PDT 24 22670412 ps
T1110 /workspace/coverage/cover_reg_top/8.edn_tl_errors.1228865135 Jul 17 07:00:28 PM PDT 24 Jul 17 07:00:33 PM PDT 24 147422191 ps
T241 /workspace/coverage/cover_reg_top/7.edn_csr_rw.3263427904 Jul 17 07:00:28 PM PDT 24 Jul 17 07:00:29 PM PDT 24 26558048 ps
T1111 /workspace/coverage/cover_reg_top/31.edn_intr_test.3313140058 Jul 17 07:01:50 PM PDT 24 Jul 17 07:01:52 PM PDT 24 26073335 ps
T1112 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2713366037 Jul 17 06:59:44 PM PDT 24 Jul 17 06:59:50 PM PDT 24 37800556 ps
T1113 /workspace/coverage/cover_reg_top/4.edn_tl_errors.2231984993 Jul 17 06:59:45 PM PDT 24 Jul 17 06:59:52 PM PDT 24 112536110 ps
T1114 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1506018486 Jul 17 06:59:42 PM PDT 24 Jul 17 06:59:46 PM PDT 24 36751613 ps
T1115 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.137910226 Jul 17 06:59:39 PM PDT 24 Jul 17 06:59:46 PM PDT 24 390784407 ps
T1116 /workspace/coverage/cover_reg_top/48.edn_intr_test.3117130504 Jul 17 07:01:41 PM PDT 24 Jul 17 07:01:44 PM PDT 24 22874577 ps
T1117 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3672799674 Jul 17 07:00:29 PM PDT 24 Jul 17 07:00:33 PM PDT 24 56147834 ps
T1118 /workspace/coverage/cover_reg_top/15.edn_csr_rw.2507590565 Jul 17 07:00:31 PM PDT 24 Jul 17 07:00:36 PM PDT 24 20243111 ps
T1119 /workspace/coverage/cover_reg_top/14.edn_intr_test.908007228 Jul 17 07:00:31 PM PDT 24 Jul 17 07:00:37 PM PDT 24 15220233 ps
T1120 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3857754900 Jul 17 06:59:44 PM PDT 24 Jul 17 06:59:50 PM PDT 24 111667611 ps
T1121 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2661488000 Jul 17 07:00:31 PM PDT 24 Jul 17 07:00:37 PM PDT 24 86876544 ps
T1122 /workspace/coverage/cover_reg_top/21.edn_intr_test.3192898259 Jul 17 07:01:50 PM PDT 24 Jul 17 07:01:52 PM PDT 24 18529900 ps
T1123 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2387985588 Jul 17 06:59:36 PM PDT 24 Jul 17 06:59:42 PM PDT 24 302318852 ps
T1124 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.764180100 Jul 17 07:00:29 PM PDT 24 Jul 17 07:00:32 PM PDT 24 28148408 ps
T1125 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2322825721 Jul 17 07:00:29 PM PDT 24 Jul 17 07:00:33 PM PDT 24 85987552 ps
T1126 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1123648329 Jul 17 07:00:34 PM PDT 24 Jul 17 07:00:40 PM PDT 24 198617725 ps
T1127 /workspace/coverage/cover_reg_top/19.edn_tl_errors.2917994883 Jul 17 07:00:31 PM PDT 24 Jul 17 07:00:40 PM PDT 24 106296632 ps
T1128 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3493589143 Jul 17 07:00:33 PM PDT 24 Jul 17 07:00:39 PM PDT 24 139406771 ps
T1129 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3185212019 Jul 17 07:00:31 PM PDT 24 Jul 17 07:00:37 PM PDT 24 90961080 ps

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.3252987794
Short name T4
Test name
Test status
Simulation time 128711267244 ps
CPU time 1335.22 seconds
Started Jul 17 07:16:20 PM PDT 24
Finished Jul 17 07:38:39 PM PDT 24
Peak memory 224552 kb
Host smart-c2ca3003-6b9f-4cca-8855-f7fda6ae72b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252987794 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.3252987794
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/263.edn_genbits.709627451
Short name T21
Test name
Test status
Simulation time 39578338 ps
CPU time 1.73 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:10 PM PDT 24
Peak memory 220008 kb
Host smart-c7f9d58b-9c37-4972-ba61-bcb002af3a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709627451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.709627451
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_sec_cm.2177282354
Short name T1
Test name
Test status
Simulation time 237627325 ps
CPU time 4.34 seconds
Started Jul 17 07:14:35 PM PDT 24
Finished Jul 17 07:14:47 PM PDT 24
Peak memory 236232 kb
Host smart-61235e41-ea3e-40ee-9129-067d94865ab7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177282354 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.2177282354
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_alert.3732603799
Short name T30
Test name
Test status
Simulation time 50490715 ps
CPU time 1.19 seconds
Started Jul 17 07:14:35 PM PDT 24
Finished Jul 17 07:14:44 PM PDT 24
Peak memory 219140 kb
Host smart-6791479e-5751-4af8-b32e-bc6ecf4be2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732603799 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.3732603799
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.872077126
Short name T58
Test name
Test status
Simulation time 89799591 ps
CPU time 0.98 seconds
Started Jul 17 07:15:03 PM PDT 24
Finished Jul 17 07:15:19 PM PDT 24
Peak memory 217188 kb
Host smart-d8d79fc0-8288-48d2-9262-c8351fa93867
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872077126 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_di
sable_auto_req_mode.872077126
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/60.edn_err.1390339157
Short name T15
Test name
Test status
Simulation time 26795427 ps
CPU time 1.04 seconds
Started Jul 17 07:16:27 PM PDT 24
Finished Jul 17 07:16:42 PM PDT 24
Peak memory 224280 kb
Host smart-ffaeaea6-e137-44ae-b4fc-d95bb75f7ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390339157 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1390339157
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/32.edn_disable.759144862
Short name T160
Test name
Test status
Simulation time 13614465 ps
CPU time 0.88 seconds
Started Jul 17 07:14:56 PM PDT 24
Finished Jul 17 07:15:00 PM PDT 24
Peak memory 216692 kb
Host smart-4f72039a-4815-43e0-a19f-99a8be95ba64
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759144862 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.759144862
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/101.edn_alert.2750996583
Short name T47
Test name
Test status
Simulation time 83401381 ps
CPU time 1.17 seconds
Started Jul 17 07:18:06 PM PDT 24
Finished Jul 17 07:18:08 PM PDT 24
Peak memory 219100 kb
Host smart-9ec5af42-9410-42f0-b002-b9f75466227a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750996583 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.2750996583
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/140.edn_alert.4072950130
Short name T31
Test name
Test status
Simulation time 61691448 ps
CPU time 1.14 seconds
Started Jul 17 07:18:13 PM PDT 24
Finished Jul 17 07:18:19 PM PDT 24
Peak memory 219424 kb
Host smart-20c49c84-3e6e-45ce-9866-314ec5d02cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072950130 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.4072950130
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/5.edn_regwen.3133840601
Short name T452
Test name
Test status
Simulation time 16882270 ps
CPU time 0.95 seconds
Started Jul 17 07:14:38 PM PDT 24
Finished Jul 17 07:14:46 PM PDT 24
Peak memory 207280 kb
Host smart-d28311f6-304f-4def-ba9d-8852ccf9d253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133840601 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.3133840601
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/16.edn_genbits.1763911525
Short name T29
Test name
Test status
Simulation time 45854200 ps
CPU time 1.35 seconds
Started Jul 17 07:15:05 PM PDT 24
Finished Jul 17 07:15:22 PM PDT 24
Peak memory 219052 kb
Host smart-8568e7df-37fd-4bfd-bb9b-49eed855fdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763911525 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.1763911525
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.335879588
Short name T76
Test name
Test status
Simulation time 48077069 ps
CPU time 1.2 seconds
Started Jul 17 07:18:08 PM PDT 24
Finished Jul 17 07:18:11 PM PDT 24
Peak memory 218896 kb
Host smart-693c2c96-1dd8-411d-bcfa-ce9e600be504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335879588 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.335879588
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1130558158
Short name T264
Test name
Test status
Simulation time 278047268 ps
CPU time 2.11 seconds
Started Jul 17 07:00:26 PM PDT 24
Finished Jul 17 07:00:29 PM PDT 24
Peak memory 207096 kb
Host smart-b7ec83d8-1550-497c-bb87-662b40323788
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130558158 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.1130558158
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/default/100.edn_alert.76456382
Short name T135
Test name
Test status
Simulation time 125872426 ps
CPU time 1.24 seconds
Started Jul 17 07:18:10 PM PDT 24
Finished Jul 17 07:18:15 PM PDT 24
Peak memory 218828 kb
Host smart-2572b03d-22d8-4b3a-ad6c-ec57567c327f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76456382 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.76456382
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/0.edn_disable.28862793
Short name T153
Test name
Test status
Simulation time 22040262 ps
CPU time 0.9 seconds
Started Jul 17 07:14:34 PM PDT 24
Finished Jul 17 07:14:40 PM PDT 24
Peak memory 216584 kb
Host smart-73e191d1-2e2c-4821-83b6-ceb2c2f10b75
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28862793 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.28862793
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable.3926471562
Short name T196
Test name
Test status
Simulation time 12887530 ps
CPU time 0.88 seconds
Started Jul 17 07:14:30 PM PDT 24
Finished Jul 17 07:14:34 PM PDT 24
Peak memory 216772 kb
Host smart-51dd1dce-74a5-46b6-8440-4bf36d779e04
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926471562 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.3926471562
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable.4232442710
Short name T173
Test name
Test status
Simulation time 14516248 ps
CPU time 0.92 seconds
Started Jul 17 07:15:02 PM PDT 24
Finished Jul 17 07:15:17 PM PDT 24
Peak memory 216772 kb
Host smart-16bdd9b3-daf0-4af1-8e21-ab039f8fe1ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232442710 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.4232442710
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.2742976149
Short name T586
Test name
Test status
Simulation time 50701783 ps
CPU time 1.04 seconds
Started Jul 17 07:14:58 PM PDT 24
Finished Jul 17 07:15:08 PM PDT 24
Peak memory 217112 kb
Host smart-2104d9a5-1148-45d1-ae3a-9a162e1ad55a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742976149 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.2742976149
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.1684548259
Short name T176
Test name
Test status
Simulation time 19491909 ps
CPU time 1.01 seconds
Started Jul 17 07:16:26 PM PDT 24
Finished Jul 17 07:16:42 PM PDT 24
Peak memory 218852 kb
Host smart-361a7c1e-cb60-4d0c-a569-b5298011f9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684548259 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.1684548259
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.3472245179
Short name T233
Test name
Test status
Simulation time 42090875 ps
CPU time 0.91 seconds
Started Jul 17 07:00:29 PM PDT 24
Finished Jul 17 07:00:32 PM PDT 24
Peak memory 206844 kb
Host smart-fa729ccf-0301-40d3-9588-9653ed93d246
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472245179 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.3472245179
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3689578475
Short name T81
Test name
Test status
Simulation time 53235631825 ps
CPU time 1278.48 seconds
Started Jul 17 07:16:27 PM PDT 24
Finished Jul 17 07:38:00 PM PDT 24
Peak memory 223300 kb
Host smart-448119cf-7cef-4ee2-98ac-c564311398a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689578475 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.3689578475
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/123.edn_genbits.1075319163
Short name T61
Test name
Test status
Simulation time 67620166 ps
CPU time 1.56 seconds
Started Jul 17 07:18:11 PM PDT 24
Finished Jul 17 07:18:17 PM PDT 24
Peak memory 218824 kb
Host smart-3cd85611-0476-4988-8b09-81192c957dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075319163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.1075319163
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.2773250411
Short name T2
Test name
Test status
Simulation time 119614826 ps
CPU time 1.22 seconds
Started Jul 17 07:14:34 PM PDT 24
Finished Jul 17 07:14:41 PM PDT 24
Peak memory 217052 kb
Host smart-ed04692e-e4d2-455f-ab3b-b18327877f59
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773250411 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.2773250411
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/192.edn_alert.933078770
Short name T272
Test name
Test status
Simulation time 86421133 ps
CPU time 1.19 seconds
Started Jul 17 07:18:49 PM PDT 24
Finished Jul 17 07:18:52 PM PDT 24
Peak memory 219360 kb
Host smart-8a4ea4c6-f8c8-4329-91db-e7384cc41fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933078770 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.933078770
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert.3114622901
Short name T88
Test name
Test status
Simulation time 42148602 ps
CPU time 1.11 seconds
Started Jul 17 07:14:57 PM PDT 24
Finished Jul 17 07:15:05 PM PDT 24
Peak memory 220940 kb
Host smart-d4098814-6852-4f5c-90d1-9a3b9a7ca14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114622901 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3114622901
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert.1721968545
Short name T157
Test name
Test status
Simulation time 65417073 ps
CPU time 1.07 seconds
Started Jul 17 07:14:57 PM PDT 24
Finished Jul 17 07:15:04 PM PDT 24
Peak memory 220360 kb
Host smart-d78cabcf-b9f6-4e0f-9f49-5d7ff1a8a998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721968545 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.1721968545
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/131.edn_alert.261758767
Short name T125
Test name
Test status
Simulation time 26585172 ps
CPU time 1.17 seconds
Started Jul 17 07:18:13 PM PDT 24
Finished Jul 17 07:18:19 PM PDT 24
Peak memory 221088 kb
Host smart-ff31ae70-6748-44f5-ab66-c46a6e0c01ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261758767 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.261758767
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/132.edn_alert.3898697644
Short name T164
Test name
Test status
Simulation time 42862336 ps
CPU time 1.17 seconds
Started Jul 17 07:18:09 PM PDT 24
Finished Jul 17 07:18:12 PM PDT 24
Peak memory 218884 kb
Host smart-f0d7c7c9-704e-4206-9173-0dfd0ee67076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898697644 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.3898697644
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/150.edn_alert.3459660762
Short name T421
Test name
Test status
Simulation time 71309127 ps
CPU time 1.05 seconds
Started Jul 17 07:18:11 PM PDT 24
Finished Jul 17 07:18:16 PM PDT 24
Peak memory 219956 kb
Host smart-0ffdea3c-3023-4a56-b36c-d7886f8b1eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459660762 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.3459660762
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/32.edn_intr.1439210291
Short name T37
Test name
Test status
Simulation time 25349597 ps
CPU time 0.94 seconds
Started Jul 17 07:14:59 PM PDT 24
Finished Jul 17 07:15:13 PM PDT 24
Peak memory 216168 kb
Host smart-87ac98f8-13e2-4da8-8b45-3d74e56eee2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439210291 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.1439210291
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/295.edn_genbits.3671426324
Short name T259
Test name
Test status
Simulation time 58485942 ps
CPU time 1.49 seconds
Started Jul 17 07:19:01 PM PDT 24
Finished Jul 17 07:19:26 PM PDT 24
Peak memory 220520 kb
Host smart-382b682a-cea3-4904-a538-7ae3519b47a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671426324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.3671426324
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_alert.3855978972
Short name T175
Test name
Test status
Simulation time 144668228 ps
CPU time 1.19 seconds
Started Jul 17 07:16:21 PM PDT 24
Finished Jul 17 07:16:28 PM PDT 24
Peak memory 220096 kb
Host smart-fd989247-206d-40a2-909d-84735a0a143d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855978972 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3855978972
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/5.edn_disable.48480225
Short name T748
Test name
Test status
Simulation time 12778639 ps
CPU time 0.88 seconds
Started Jul 17 07:14:35 PM PDT 24
Finished Jul 17 07:14:43 PM PDT 24
Peak memory 216676 kb
Host smart-c4ec496c-071c-4b44-95fc-0581137177e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48480225 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.48480225
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/23.edn_intr.3258749345
Short name T49
Test name
Test status
Simulation time 34336180 ps
CPU time 1 seconds
Started Jul 17 07:14:59 PM PDT 24
Finished Jul 17 07:15:10 PM PDT 24
Peak memory 224356 kb
Host smart-09059182-3f93-44b1-88d0-8856c9a2bb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258749345 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3258749345
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/18.edn_intr.2425944618
Short name T35
Test name
Test status
Simulation time 22438960 ps
CPU time 0.96 seconds
Started Jul 17 07:14:59 PM PDT 24
Finished Jul 17 07:15:13 PM PDT 24
Peak memory 216220 kb
Host smart-dfb88dcc-1b54-4ff6-8abe-8bc918a08ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425944618 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.2425944618
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.1465006553
Short name T733
Test name
Test status
Simulation time 22706086 ps
CPU time 1.02 seconds
Started Jul 17 07:14:38 PM PDT 24
Finished Jul 17 07:14:46 PM PDT 24
Peak memory 216996 kb
Host smart-ce10a4c5-b0d3-479e-a04e-fbcbe1ad723d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465006553 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.1465006553
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_alert.671011327
Short name T513
Test name
Test status
Simulation time 91213227 ps
CPU time 1.16 seconds
Started Jul 17 07:14:53 PM PDT 24
Finished Jul 17 07:14:56 PM PDT 24
Peak memory 220276 kb
Host smart-4221629f-ae55-48d2-9931-717bca71764c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671011327 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.671011327
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_disable.2140205060
Short name T180
Test name
Test status
Simulation time 19036243 ps
CPU time 0.85 seconds
Started Jul 17 07:14:49 PM PDT 24
Finished Jul 17 07:14:50 PM PDT 24
Peak memory 216500 kb
Host smart-64e7e039-8bad-4602-bd5b-6b7780990adc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140205060 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.2140205060
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/12.edn_alert.3716559659
Short name T121
Test name
Test status
Simulation time 31484391 ps
CPU time 1.37 seconds
Started Jul 17 07:15:00 PM PDT 24
Finished Jul 17 07:15:14 PM PDT 24
Peak memory 216012 kb
Host smart-12d1f73e-ee2c-49a2-9d64-c447e1a5f9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716559659 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.3716559659
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/130.edn_alert.382559422
Short name T114
Test name
Test status
Simulation time 52372341 ps
CPU time 1.26 seconds
Started Jul 17 07:18:10 PM PDT 24
Finished Jul 17 07:18:15 PM PDT 24
Peak memory 219620 kb
Host smart-05161c23-ac62-439f-87ec-04fd20697513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382559422 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.382559422
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/133.edn_alert.625475872
Short name T557
Test name
Test status
Simulation time 152116803 ps
CPU time 1.35 seconds
Started Jul 17 07:18:07 PM PDT 24
Finished Jul 17 07:18:09 PM PDT 24
Peak memory 218828 kb
Host smart-135df07e-3e69-4812-bfd2-8eb8f8d74c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625475872 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.625475872
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2272255958
Short name T724
Test name
Test status
Simulation time 30661383 ps
CPU time 1.19 seconds
Started Jul 17 07:15:05 PM PDT 24
Finished Jul 17 07:15:22 PM PDT 24
Peak memory 217028 kb
Host smart-28ec2ec2-0f75-4c8e-a934-100ec67fa2b4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272255958 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2272255958
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_disable.421645720
Short name T834
Test name
Test status
Simulation time 21420531 ps
CPU time 0.86 seconds
Started Jul 17 07:14:51 PM PDT 24
Finished Jul 17 07:14:53 PM PDT 24
Peak memory 216476 kb
Host smart-30fc4586-b38f-4051-858b-22b17bd2b306
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421645720 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.421645720
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable.1215361877
Short name T189
Test name
Test status
Simulation time 50699991 ps
CPU time 0.88 seconds
Started Jul 17 07:14:59 PM PDT 24
Finished Jul 17 07:15:13 PM PDT 24
Peak memory 216476 kb
Host smart-89176110-12e2-408a-ad54-dfbda169898c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215361877 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.1215361877
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable.2733957511
Short name T179
Test name
Test status
Simulation time 23079760 ps
CPU time 0.88 seconds
Started Jul 17 07:14:57 PM PDT 24
Finished Jul 17 07:15:05 PM PDT 24
Peak memory 216756 kb
Host smart-78f6b471-8bea-4462-bc26-a35cb40993ce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733957511 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.2733957511
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/161.edn_genbits.378426839
Short name T223
Test name
Test status
Simulation time 27724140 ps
CPU time 1.18 seconds
Started Jul 17 07:18:54 PM PDT 24
Finished Jul 17 07:19:00 PM PDT 24
Peak memory 217468 kb
Host smart-0fa5c988-d530-45c9-bcfd-335766052c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378426839 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.378426839
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.1291186281
Short name T69
Test name
Test status
Simulation time 153671973 ps
CPU time 3.18 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:12 PM PDT 24
Peak memory 220212 kb
Host smart-af4013d5-3e63-4ad8-b2dc-aac1cbfee6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291186281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.1291186281
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.1327011234
Short name T3
Test name
Test status
Simulation time 33040217 ps
CPU time 0.84 seconds
Started Jul 17 07:14:58 PM PDT 24
Finished Jul 17 07:15:08 PM PDT 24
Peak memory 215740 kb
Host smart-ed092776-c8a4-4ea7-86f4-c78942bd4234
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327011234 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.1327011234
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/123.edn_alert.1174826315
Short name T269
Test name
Test status
Simulation time 42166809 ps
CPU time 1.19 seconds
Started Jul 17 07:18:12 PM PDT 24
Finished Jul 17 07:18:18 PM PDT 24
Peak memory 220220 kb
Host smart-b2c4426b-4bbe-4e83-a6ba-d62d9421535c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174826315 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.1174826315
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.1709044983
Short name T294
Test name
Test status
Simulation time 147457119 ps
CPU time 1.66 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:15 PM PDT 24
Peak memory 218764 kb
Host smart-7b67a9d3-10c5-4d93-b73b-15ca5fda1ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709044983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1709044983
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.4166800040
Short name T310
Test name
Test status
Simulation time 103847454 ps
CPU time 1.33 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:12 PM PDT 24
Peak memory 217828 kb
Host smart-37e62a3a-cfd0-4a41-a784-ca57974d8f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166800040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.4166800040
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_genbits.1931558916
Short name T598
Test name
Test status
Simulation time 60820686 ps
CPU time 1.37 seconds
Started Jul 17 07:16:29 PM PDT 24
Finished Jul 17 07:16:49 PM PDT 24
Peak memory 220364 kb
Host smart-99fe763e-8ea1-4829-87ef-96bb23c53de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931558916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.1931558916
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.3244769061
Short name T80
Test name
Test status
Simulation time 29810635 ps
CPU time 0.86 seconds
Started Jul 17 07:15:04 PM PDT 24
Finished Jul 17 07:15:21 PM PDT 24
Peak memory 216120 kb
Host smart-d11939a6-2c77-427a-9d8a-373fdec999d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244769061 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.3244769061
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1502570051
Short name T232
Test name
Test status
Simulation time 29344736 ps
CPU time 1.21 seconds
Started Jul 17 06:59:36 PM PDT 24
Finished Jul 17 06:59:40 PM PDT 24
Peak memory 206856 kb
Host smart-8755a8ab-0515-4199-9a6c-c75291dfa8fd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502570051 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1502570051
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2387985588
Short name T1123
Test name
Test status
Simulation time 302318852 ps
CPU time 2.04 seconds
Started Jul 17 06:59:36 PM PDT 24
Finished Jul 17 06:59:42 PM PDT 24
Peak memory 206916 kb
Host smart-c115bb12-8f1c-43aa-9cdf-f3e14ff7d225
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387985588 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.2387985588
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.3412872714
Short name T229
Test name
Test status
Simulation time 62910443 ps
CPU time 1.26 seconds
Started Jul 17 07:14:36 PM PDT 24
Finished Jul 17 07:14:45 PM PDT 24
Peak memory 216056 kb
Host smart-9940a195-ab9e-48e2-b8b8-ff4f4d123d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412872714 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3412872714
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.3280675454
Short name T213
Test name
Test status
Simulation time 73712096480 ps
CPU time 1662.24 seconds
Started Jul 17 07:14:37 PM PDT 24
Finished Jul 17 07:42:27 PM PDT 24
Peak memory 224688 kb
Host smart-dc5f2ea8-fe82-477c-b530-39f3263a2e35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280675454 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.3280675454
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.2022154380
Short name T786
Test name
Test status
Simulation time 156928962052 ps
CPU time 978.83 seconds
Started Jul 17 07:14:38 PM PDT 24
Finished Jul 17 07:31:04 PM PDT 24
Peak memory 224372 kb
Host smart-8f49a5f4-ae69-4473-96e1-a24ce9efb371
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022154380 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.2022154380
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.3897775069
Short name T510
Test name
Test status
Simulation time 94670094574 ps
CPU time 674.66 seconds
Started Jul 17 07:14:49 PM PDT 24
Finished Jul 17 07:26:04 PM PDT 24
Peak memory 223964 kb
Host smart-3a6cd68f-c7d3-44cf-b404-7c953c291f33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897775069 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.3897775069
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/106.edn_genbits.1381040412
Short name T46
Test name
Test status
Simulation time 48963336 ps
CPU time 1.79 seconds
Started Jul 17 07:18:06 PM PDT 24
Finished Jul 17 07:18:09 PM PDT 24
Peak memory 218972 kb
Host smart-416157b8-d6e1-44f2-aa35-e1c65a101b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381040412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1381040412
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_genbits.1191497391
Short name T890
Test name
Test status
Simulation time 1030257414 ps
CPU time 7.53 seconds
Started Jul 17 07:15:00 PM PDT 24
Finished Jul 17 07:15:20 PM PDT 24
Peak memory 220364 kb
Host smart-e4ff7886-06ab-496e-b484-7232db8d54ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191497391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1191497391
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2172029510
Short name T289
Test name
Test status
Simulation time 16435931941 ps
CPU time 361.44 seconds
Started Jul 17 07:15:05 PM PDT 24
Finished Jul 17 07:21:22 PM PDT 24
Peak memory 218380 kb
Host smart-c4e93bf0-0c42-4750-a89a-4e7a75438303
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172029510 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2172029510
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/179.edn_genbits.2451746622
Short name T285
Test name
Test status
Simulation time 44060096 ps
CPU time 1.35 seconds
Started Jul 17 07:18:50 PM PDT 24
Finished Jul 17 07:18:53 PM PDT 24
Peak memory 218896 kb
Host smart-a796654c-3d86-4fad-a05c-23e541744300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451746622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.2451746622
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.2802881806
Short name T300
Test name
Test status
Simulation time 92545887 ps
CPU time 1.25 seconds
Started Jul 17 07:18:55 PM PDT 24
Finished Jul 17 07:19:08 PM PDT 24
Peak memory 219396 kb
Host smart-702ac9ed-05bf-4cfe-a23b-d92641f9ca30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802881806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2802881806
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.133506226
Short name T296
Test name
Test status
Simulation time 37067150 ps
CPU time 1.45 seconds
Started Jul 17 07:18:51 PM PDT 24
Finished Jul 17 07:18:55 PM PDT 24
Peak memory 219148 kb
Host smart-88112db1-b7fc-4d49-aac8-bf5d1302f881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133506226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.133506226
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.2531379759
Short name T77
Test name
Test status
Simulation time 22177906 ps
CPU time 1.03 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:28 PM PDT 24
Peak memory 216072 kb
Host smart-5cc409e2-dc1d-4ba9-ab06-5561a86bb8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531379759 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.2531379759
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/174.edn_alert.2155936916
Short name T93
Test name
Test status
Simulation time 40488975 ps
CPU time 1.12 seconds
Started Jul 17 07:18:55 PM PDT 24
Finished Jul 17 07:19:06 PM PDT 24
Peak memory 219172 kb
Host smart-ad98193d-a16a-4081-ab87-a5a033106da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155936916 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.2155936916
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/11.edn_err.4146332964
Short name T9
Test name
Test status
Simulation time 23148767 ps
CPU time 1.1 seconds
Started Jul 17 07:14:50 PM PDT 24
Finished Jul 17 07:14:52 PM PDT 24
Peak memory 218972 kb
Host smart-86980847-5607-4d3d-89eb-7d3998360d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146332964 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.4146332964
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3100091022
Short name T1004
Test name
Test status
Simulation time 40906627 ps
CPU time 2.03 seconds
Started Jul 17 06:59:37 PM PDT 24
Finished Jul 17 06:59:43 PM PDT 24
Peak memory 206828 kb
Host smart-f20291aa-c7df-41fb-b708-01815dd71d80
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100091022 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.3100091022
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.49282889
Short name T1006
Test name
Test status
Simulation time 24278610 ps
CPU time 0.88 seconds
Started Jul 17 06:59:37 PM PDT 24
Finished Jul 17 06:59:41 PM PDT 24
Peak memory 206788 kb
Host smart-019e4446-2749-41f2-b2b7-2f2a88478913
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49282889 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.49282889
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3662292997
Short name T1049
Test name
Test status
Simulation time 33699393 ps
CPU time 1.52 seconds
Started Jul 17 06:59:39 PM PDT 24
Finished Jul 17 06:59:45 PM PDT 24
Peak memory 215156 kb
Host smart-169078cd-7e3f-42ac-aae8-1d732f8a4c1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662292997 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3662292997
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.4202358918
Short name T1067
Test name
Test status
Simulation time 36990201 ps
CPU time 0.86 seconds
Started Jul 17 06:59:36 PM PDT 24
Finished Jul 17 06:59:41 PM PDT 24
Peak memory 206620 kb
Host smart-82338e7a-5439-41aa-9c0a-faeb53af20df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202358918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.4202358918
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1773297564
Short name T1071
Test name
Test status
Simulation time 42306450 ps
CPU time 0.84 seconds
Started Jul 17 06:59:38 PM PDT 24
Finished Jul 17 06:59:42 PM PDT 24
Peak memory 206812 kb
Host smart-e835855f-4119-4930-b0c6-4e4575d83b1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773297564 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1773297564
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2724270991
Short name T1095
Test name
Test status
Simulation time 17366597 ps
CPU time 1.02 seconds
Started Jul 17 06:59:35 PM PDT 24
Finished Jul 17 06:59:39 PM PDT 24
Peak memory 206936 kb
Host smart-e4ad77c2-78eb-4005-b37a-5b9fd89c3f9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724270991 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.2724270991
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.1393891273
Short name T1081
Test name
Test status
Simulation time 456899050 ps
CPU time 2.43 seconds
Started Jul 17 06:59:37 PM PDT 24
Finished Jul 17 06:59:43 PM PDT 24
Peak memory 215228 kb
Host smart-0be0bfce-4f70-420d-8b16-432250b57bb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393891273 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.1393891273
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.137910226
Short name T1115
Test name
Test status
Simulation time 390784407 ps
CPU time 2.54 seconds
Started Jul 17 06:59:39 PM PDT 24
Finished Jul 17 06:59:46 PM PDT 24
Peak memory 207316 kb
Host smart-001eed7b-9eed-4df4-ab51-f83a8ea6c040
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137910226 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.137910226
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2604095307
Short name T1000
Test name
Test status
Simulation time 24842711 ps
CPU time 1.17 seconds
Started Jul 17 06:59:41 PM PDT 24
Finished Jul 17 06:59:46 PM PDT 24
Peak memory 206824 kb
Host smart-e14dcc25-9f38-4698-b45f-4ed8642c8357
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604095307 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.2604095307
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2113057495
Short name T1097
Test name
Test status
Simulation time 37664363 ps
CPU time 1.96 seconds
Started Jul 17 06:59:42 PM PDT 24
Finished Jul 17 06:59:47 PM PDT 24
Peak memory 206856 kb
Host smart-3265fdb1-1cb6-4a1b-aa51-094791e35957
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113057495 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2113057495
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1776127303
Short name T240
Test name
Test status
Simulation time 26081147 ps
CPU time 0.88 seconds
Started Jul 17 06:59:37 PM PDT 24
Finished Jul 17 06:59:41 PM PDT 24
Peak memory 206804 kb
Host smart-d377efb6-47f4-4d23-b066-1b0d9b5bffea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776127303 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1776127303
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.57143369
Short name T1019
Test name
Test status
Simulation time 132321388 ps
CPU time 1.46 seconds
Started Jul 17 06:59:43 PM PDT 24
Finished Jul 17 06:59:48 PM PDT 24
Peak memory 215140 kb
Host smart-a5fc5a6b-56f9-4992-b732-885839014b58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57143369 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.57143369
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.939571977
Short name T242
Test name
Test status
Simulation time 49197544 ps
CPU time 0.79 seconds
Started Jul 17 06:59:42 PM PDT 24
Finished Jul 17 06:59:46 PM PDT 24
Peak memory 206608 kb
Host smart-efbb02a9-eb5a-4ac8-8153-6d722a4242a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939571977 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.939571977
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.2967315439
Short name T1038
Test name
Test status
Simulation time 52280028 ps
CPU time 0.84 seconds
Started Jul 17 06:59:42 PM PDT 24
Finished Jul 17 06:59:46 PM PDT 24
Peak memory 206772 kb
Host smart-9ed5746f-777d-4d08-b8c7-24bec897067d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967315439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.2967315439
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1506018486
Short name T1114
Test name
Test status
Simulation time 36751613 ps
CPU time 1.02 seconds
Started Jul 17 06:59:42 PM PDT 24
Finished Jul 17 06:59:46 PM PDT 24
Peak memory 206892 kb
Host smart-a45f7154-6372-4820-91fc-e542bb6a3776
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506018486 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.1506018486
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.3394146321
Short name T1017
Test name
Test status
Simulation time 57102235 ps
CPU time 2.3 seconds
Started Jul 17 06:59:35 PM PDT 24
Finished Jul 17 06:59:41 PM PDT 24
Peak memory 215112 kb
Host smart-54917d42-4c16-44da-96db-17153faafa04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394146321 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3394146321
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1533658318
Short name T1104
Test name
Test status
Simulation time 48168934 ps
CPU time 1.25 seconds
Started Jul 17 07:00:31 PM PDT 24
Finished Jul 17 07:00:36 PM PDT 24
Peak memory 215136 kb
Host smart-a6e95234-7f1e-4d94-8dfe-dafa5297a538
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533658318 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.1533658318
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.3529501036
Short name T1102
Test name
Test status
Simulation time 35167652 ps
CPU time 0.8 seconds
Started Jul 17 07:00:28 PM PDT 24
Finished Jul 17 07:00:30 PM PDT 24
Peak memory 206608 kb
Host smart-879906db-baf1-453a-8c84-54f2fd163036
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529501036 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.3529501036
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2200244715
Short name T1035
Test name
Test status
Simulation time 33085925 ps
CPU time 0.77 seconds
Started Jul 17 07:00:31 PM PDT 24
Finished Jul 17 07:00:37 PM PDT 24
Peak memory 206636 kb
Host smart-e866e64a-6a36-45b0-ac23-69b5ee5fca07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200244715 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2200244715
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.723144385
Short name T1068
Test name
Test status
Simulation time 20503289 ps
CPU time 1.07 seconds
Started Jul 17 07:00:29 PM PDT 24
Finished Jul 17 07:00:31 PM PDT 24
Peak memory 206836 kb
Host smart-4e4f2773-eed6-4eb0-a2ee-9ff1557d6228
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723144385 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_ou
tstanding.723144385
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.2888885634
Short name T1033
Test name
Test status
Simulation time 419625735 ps
CPU time 3.7 seconds
Started Jul 17 07:00:30 PM PDT 24
Finished Jul 17 07:00:38 PM PDT 24
Peak memory 215148 kb
Host smart-0c8e875a-2b85-4320-9d23-8c88d6760855
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888885634 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2888885634
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2322825721
Short name T1125
Test name
Test status
Simulation time 85987552 ps
CPU time 2.45 seconds
Started Jul 17 07:00:29 PM PDT 24
Finished Jul 17 07:00:33 PM PDT 24
Peak memory 215096 kb
Host smart-b148d157-59cd-4fcf-a8c8-eb1ed408392e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322825721 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.2322825721
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3238987956
Short name T1083
Test name
Test status
Simulation time 24671807 ps
CPU time 1.2 seconds
Started Jul 17 07:00:31 PM PDT 24
Finished Jul 17 07:00:36 PM PDT 24
Peak memory 215088 kb
Host smart-38fb092f-1425-4978-bb03-b4a4363b999d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238987956 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3238987956
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.3428859651
Short name T1056
Test name
Test status
Simulation time 15275931 ps
CPU time 0.89 seconds
Started Jul 17 07:00:31 PM PDT 24
Finished Jul 17 07:00:35 PM PDT 24
Peak memory 206808 kb
Host smart-95201f96-78ca-4f4d-a979-cd64bd95543d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428859651 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3428859651
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.1469764076
Short name T1098
Test name
Test status
Simulation time 14910565 ps
CPU time 0.9 seconds
Started Jul 17 07:00:28 PM PDT 24
Finished Jul 17 07:00:29 PM PDT 24
Peak memory 206836 kb
Host smart-6d97a522-105d-4f43-b23c-239ba9fc35a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469764076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1469764076
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2174488653
Short name T1046
Test name
Test status
Simulation time 29192808 ps
CPU time 1.3 seconds
Started Jul 17 07:00:29 PM PDT 24
Finished Jul 17 07:00:33 PM PDT 24
Peak memory 206840 kb
Host smart-8a2f6790-fbc0-4441-a164-baa5cd250e93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174488653 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.2174488653
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.1953705490
Short name T1059
Test name
Test status
Simulation time 96868281 ps
CPU time 2.26 seconds
Started Jul 17 07:00:30 PM PDT 24
Finished Jul 17 07:00:36 PM PDT 24
Peak memory 215240 kb
Host smart-351baaf8-f411-44e3-ab7b-767ffbaa8e4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953705490 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.1953705490
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.10330716
Short name T265
Test name
Test status
Simulation time 54603386 ps
CPU time 1.68 seconds
Started Jul 17 07:00:32 PM PDT 24
Finished Jul 17 07:00:38 PM PDT 24
Peak memory 207272 kb
Host smart-13d96e7d-1cd4-460d-ab8f-99488a0263bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10330716 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.10330716
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.35044582
Short name T1051
Test name
Test status
Simulation time 37633729 ps
CPU time 1.54 seconds
Started Jul 17 07:00:30 PM PDT 24
Finished Jul 17 07:00:34 PM PDT 24
Peak memory 215204 kb
Host smart-92bf7f10-b70d-4a1c-8130-02e7f3f428a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35044582 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.35044582
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.3737916830
Short name T1024
Test name
Test status
Simulation time 111811012 ps
CPU time 0.84 seconds
Started Jul 17 07:00:34 PM PDT 24
Finished Jul 17 07:00:38 PM PDT 24
Peak memory 206812 kb
Host smart-ab72c451-e56b-458a-8da8-0adf533a9222
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737916830 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.3737916830
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1359971241
Short name T248
Test name
Test status
Simulation time 32381417 ps
CPU time 1.37 seconds
Started Jul 17 07:00:29 PM PDT 24
Finished Jul 17 07:00:32 PM PDT 24
Peak memory 206852 kb
Host smart-bd79a417-bba6-4bb8-bd05-c347021289c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359971241 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.1359971241
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3783053647
Short name T1108
Test name
Test status
Simulation time 26920360 ps
CPU time 1.77 seconds
Started Jul 17 07:00:30 PM PDT 24
Finished Jul 17 07:00:35 PM PDT 24
Peak memory 215180 kb
Host smart-2156f952-4045-4462-9da9-56869ddda7be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783053647 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3783053647
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1819434640
Short name T1061
Test name
Test status
Simulation time 43703269 ps
CPU time 1.17 seconds
Started Jul 17 07:00:30 PM PDT 24
Finished Jul 17 07:00:35 PM PDT 24
Peak memory 217728 kb
Host smart-12aa185a-cb70-422e-9265-8bc215f9b4fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819434640 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.1819434640
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.3697218075
Short name T1075
Test name
Test status
Simulation time 22338161 ps
CPU time 0.87 seconds
Started Jul 17 07:00:31 PM PDT 24
Finished Jul 17 07:00:36 PM PDT 24
Peak memory 206768 kb
Host smart-d999f3d6-08ba-4342-bfb4-f73e935e7b1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697218075 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3697218075
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.3133347891
Short name T1018
Test name
Test status
Simulation time 68652520 ps
CPU time 0.8 seconds
Started Jul 17 07:00:32 PM PDT 24
Finished Jul 17 07:00:37 PM PDT 24
Peak memory 206512 kb
Host smart-da2eba98-19cf-4deb-a663-18fed10809e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133347891 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.3133347891
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3337479238
Short name T1044
Test name
Test status
Simulation time 75009144 ps
CPU time 0.99 seconds
Started Jul 17 07:00:27 PM PDT 24
Finished Jul 17 07:00:29 PM PDT 24
Peak memory 206920 kb
Host smart-67fcc0fc-c2ac-48e4-8ad2-4772a0b7efa7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337479238 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.3337479238
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.589885846
Short name T1021
Test name
Test status
Simulation time 268920996 ps
CPU time 2.13 seconds
Started Jul 17 07:00:31 PM PDT 24
Finished Jul 17 07:00:38 PM PDT 24
Peak memory 215004 kb
Host smart-438d6411-0172-451c-8c4d-89271b176a4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589885846 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.589885846
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1625794443
Short name T1091
Test name
Test status
Simulation time 282139729 ps
CPU time 2.36 seconds
Started Jul 17 07:00:31 PM PDT 24
Finished Jul 17 07:00:38 PM PDT 24
Peak memory 206916 kb
Host smart-df35e6d7-b94e-4deb-8973-7a7c457dc95b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625794443 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1625794443
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3826672352
Short name T1090
Test name
Test status
Simulation time 35630989 ps
CPU time 1.59 seconds
Started Jul 17 07:00:32 PM PDT 24
Finished Jul 17 07:00:37 PM PDT 24
Peak memory 218220 kb
Host smart-b2b0c245-f30a-4d72-b003-72114dbf8f91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826672352 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.3826672352
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.913315949
Short name T1042
Test name
Test status
Simulation time 59948522 ps
CPU time 0.87 seconds
Started Jul 17 07:00:31 PM PDT 24
Finished Jul 17 07:00:35 PM PDT 24
Peak memory 206996 kb
Host smart-83886a7b-a1c3-44b3-b4ff-c46a4dff139a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913315949 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.913315949
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.908007228
Short name T1119
Test name
Test status
Simulation time 15220233 ps
CPU time 0.9 seconds
Started Jul 17 07:00:31 PM PDT 24
Finished Jul 17 07:00:37 PM PDT 24
Peak memory 206764 kb
Host smart-529464c0-f104-4a56-88eb-7bc0f027d54c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908007228 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.908007228
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3672799674
Short name T1117
Test name
Test status
Simulation time 56147834 ps
CPU time 1.12 seconds
Started Jul 17 07:00:29 PM PDT 24
Finished Jul 17 07:00:33 PM PDT 24
Peak memory 206872 kb
Host smart-98c213a7-e4d4-425e-bea8-61f78de68519
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672799674 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.3672799674
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.3380709503
Short name T1014
Test name
Test status
Simulation time 41926618 ps
CPU time 2.67 seconds
Started Jul 17 07:00:31 PM PDT 24
Finished Jul 17 07:00:38 PM PDT 24
Peak memory 214996 kb
Host smart-370595af-36d0-4437-8ac7-0d7329f9ad11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380709503 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3380709503
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3185212019
Short name T1129
Test name
Test status
Simulation time 90961080 ps
CPU time 1.59 seconds
Started Jul 17 07:00:31 PM PDT 24
Finished Jul 17 07:00:37 PM PDT 24
Peak memory 215556 kb
Host smart-5266359a-ea2a-46be-bbe9-38d9be8c0eec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185212019 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.3185212019
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2210802743
Short name T1009
Test name
Test status
Simulation time 58019674 ps
CPU time 0.98 seconds
Started Jul 17 07:00:29 PM PDT 24
Finished Jul 17 07:00:32 PM PDT 24
Peak memory 206956 kb
Host smart-0eb8460c-06fc-48c9-82fd-9b9eab9c9197
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210802743 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2210802743
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.2507590565
Short name T1118
Test name
Test status
Simulation time 20243111 ps
CPU time 0.84 seconds
Started Jul 17 07:00:31 PM PDT 24
Finished Jul 17 07:00:36 PM PDT 24
Peak memory 207004 kb
Host smart-3222465c-5848-43db-9fad-98c1bf60a61c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507590565 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2507590565
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.417758402
Short name T1005
Test name
Test status
Simulation time 26168745 ps
CPU time 0.89 seconds
Started Jul 17 07:00:30 PM PDT 24
Finished Jul 17 07:00:34 PM PDT 24
Peak memory 206836 kb
Host smart-91632c38-1e87-49f7-ad1a-3b039215083f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417758402 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.417758402
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1316844087
Short name T243
Test name
Test status
Simulation time 20470004 ps
CPU time 1.22 seconds
Started Jul 17 07:00:31 PM PDT 24
Finished Jul 17 07:00:36 PM PDT 24
Peak memory 206888 kb
Host smart-67a0e63c-4efe-4ef3-abbe-8771d13041de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316844087 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.1316844087
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.3178842361
Short name T1072
Test name
Test status
Simulation time 737272253 ps
CPU time 3.46 seconds
Started Jul 17 07:00:29 PM PDT 24
Finished Jul 17 07:00:35 PM PDT 24
Peak memory 215156 kb
Host smart-e9553746-27df-49a6-8d49-daf81fadabdf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178842361 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.3178842361
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2724899740
Short name T1093
Test name
Test status
Simulation time 188105363 ps
CPU time 1.64 seconds
Started Jul 17 07:00:33 PM PDT 24
Finished Jul 17 07:00:39 PM PDT 24
Peak memory 215260 kb
Host smart-82937ae2-8765-42fb-a21e-82506a82944c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724899740 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2724899740
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3206173872
Short name T1012
Test name
Test status
Simulation time 28519726 ps
CPU time 0.99 seconds
Started Jul 17 07:00:32 PM PDT 24
Finished Jul 17 07:00:37 PM PDT 24
Peak memory 206924 kb
Host smart-e1a8c1e6-f955-4649-b2f0-2de8f9629083
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206173872 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.3206173872
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.4201935507
Short name T231
Test name
Test status
Simulation time 10887733 ps
CPU time 0.83 seconds
Started Jul 17 07:00:33 PM PDT 24
Finished Jul 17 07:00:37 PM PDT 24
Peak memory 206832 kb
Host smart-2170e200-d219-49ac-8a28-ca131486fdaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201935507 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.4201935507
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.4058511136
Short name T993
Test name
Test status
Simulation time 16448736 ps
CPU time 0.87 seconds
Started Jul 17 07:00:33 PM PDT 24
Finished Jul 17 07:00:38 PM PDT 24
Peak memory 206932 kb
Host smart-f8097392-c2be-4b32-b60c-6cb575450563
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058511136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.4058511136
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3493589143
Short name T1128
Test name
Test status
Simulation time 139406771 ps
CPU time 1.56 seconds
Started Jul 17 07:00:33 PM PDT 24
Finished Jul 17 07:00:39 PM PDT 24
Peak memory 206972 kb
Host smart-a38702aa-5f79-486b-9b9a-dabf86c076fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493589143 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3493589143
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.3074270365
Short name T995
Test name
Test status
Simulation time 79809632 ps
CPU time 1.75 seconds
Started Jul 17 07:00:30 PM PDT 24
Finished Jul 17 07:00:35 PM PDT 24
Peak memory 215160 kb
Host smart-d02803ea-1c51-49d8-9763-89657784b1f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074270365 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3074270365
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2661488000
Short name T1121
Test name
Test status
Simulation time 86876544 ps
CPU time 2.51 seconds
Started Jul 17 07:00:31 PM PDT 24
Finished Jul 17 07:00:37 PM PDT 24
Peak memory 206888 kb
Host smart-561a93fa-60b7-4089-9a09-87b5f276e23c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661488000 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.2661488000
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1303855119
Short name T1031
Test name
Test status
Simulation time 82072160 ps
CPU time 1.14 seconds
Started Jul 17 07:00:31 PM PDT 24
Finished Jul 17 07:00:36 PM PDT 24
Peak memory 223240 kb
Host smart-b5496c15-82a8-467c-bd88-32f775114794
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303855119 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.1303855119
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.177722267
Short name T1107
Test name
Test status
Simulation time 24472349 ps
CPU time 0.85 seconds
Started Jul 17 07:00:33 PM PDT 24
Finished Jul 17 07:00:38 PM PDT 24
Peak memory 206824 kb
Host smart-d8724b7a-40fd-4ff7-994c-d1ef7d57f4e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177722267 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.177722267
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.372026033
Short name T1073
Test name
Test status
Simulation time 24509360 ps
CPU time 0.8 seconds
Started Jul 17 07:00:33 PM PDT 24
Finished Jul 17 07:00:38 PM PDT 24
Peak memory 206920 kb
Host smart-b119a5b0-3874-4aaf-a5d2-11de221d1b0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372026033 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.372026033
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.610113205
Short name T245
Test name
Test status
Simulation time 19795196 ps
CPU time 1.14 seconds
Started Jul 17 07:00:29 PM PDT 24
Finished Jul 17 07:00:33 PM PDT 24
Peak memory 206848 kb
Host smart-b3766da2-32f4-40b6-b1e9-d3c7e5c18287
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610113205 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_ou
tstanding.610113205
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.699951721
Short name T1082
Test name
Test status
Simulation time 977570489 ps
CPU time 3.01 seconds
Started Jul 17 07:00:31 PM PDT 24
Finished Jul 17 07:00:38 PM PDT 24
Peak memory 215320 kb
Host smart-5fff885a-5e99-49d0-9dd5-666232fb7765
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699951721 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.699951721
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3923630811
Short name T262
Test name
Test status
Simulation time 132292826 ps
CPU time 2.13 seconds
Started Jul 17 07:00:30 PM PDT 24
Finished Jul 17 07:00:36 PM PDT 24
Peak memory 206896 kb
Host smart-42c44ee9-26d6-4265-9234-56ea84851a6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923630811 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3923630811
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3465107542
Short name T1025
Test name
Test status
Simulation time 24574338 ps
CPU time 1.17 seconds
Started Jul 17 07:00:32 PM PDT 24
Finished Jul 17 07:00:37 PM PDT 24
Peak memory 217664 kb
Host smart-87973f38-9f34-4745-9d45-82518a43a72f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465107542 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3465107542
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1832439188
Short name T1089
Test name
Test status
Simulation time 51343417 ps
CPU time 0.88 seconds
Started Jul 17 07:00:30 PM PDT 24
Finished Jul 17 07:00:35 PM PDT 24
Peak memory 206804 kb
Host smart-7b5b4a7f-a1f4-4ee2-a3b4-7747a8d676c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832439188 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1832439188
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.471439957
Short name T1043
Test name
Test status
Simulation time 44948053 ps
CPU time 0.82 seconds
Started Jul 17 07:00:26 PM PDT 24
Finished Jul 17 07:00:28 PM PDT 24
Peak memory 206832 kb
Host smart-552c8a38-864d-48d2-a604-66e5f35d2f23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471439957 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.471439957
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2763737682
Short name T1047
Test name
Test status
Simulation time 103577763 ps
CPU time 1.4 seconds
Started Jul 17 07:00:32 PM PDT 24
Finished Jul 17 07:00:38 PM PDT 24
Peak memory 207024 kb
Host smart-9fc3f470-8955-42fe-a3ab-56dd8f69d798
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763737682 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.2763737682
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3186558954
Short name T1008
Test name
Test status
Simulation time 116734165 ps
CPU time 4.28 seconds
Started Jul 17 07:00:32 PM PDT 24
Finished Jul 17 07:00:41 PM PDT 24
Peak memory 215140 kb
Host smart-ec785232-92b6-4eee-9805-f4ca4f585b94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186558954 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3186558954
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3197339716
Short name T1085
Test name
Test status
Simulation time 363728541 ps
CPU time 1.35 seconds
Started Jul 17 07:00:32 PM PDT 24
Finished Jul 17 07:00:38 PM PDT 24
Peak memory 207044 kb
Host smart-2ae205ec-afad-41ca-acc4-80b0cec79274
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197339716 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.3197339716
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.941159886
Short name T1053
Test name
Test status
Simulation time 54369674 ps
CPU time 1.75 seconds
Started Jul 17 07:00:28 PM PDT 24
Finished Jul 17 07:00:30 PM PDT 24
Peak memory 215188 kb
Host smart-c5578412-3558-4e23-9f7c-a9cb0924df57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941159886 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.941159886
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.292081437
Short name T1030
Test name
Test status
Simulation time 14666897 ps
CPU time 0.89 seconds
Started Jul 17 07:00:32 PM PDT 24
Finished Jul 17 07:00:37 PM PDT 24
Peak memory 206800 kb
Host smart-b81fdfb0-e284-4873-b4e1-2608e85d2441
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292081437 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.292081437
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.3741904346
Short name T1069
Test name
Test status
Simulation time 14061238 ps
CPU time 0.86 seconds
Started Jul 17 07:00:31 PM PDT 24
Finished Jul 17 07:00:36 PM PDT 24
Peak memory 206812 kb
Host smart-dc005a0b-62ab-4ac0-878d-eed579922544
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741904346 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.3741904346
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.180969329
Short name T1062
Test name
Test status
Simulation time 27846439 ps
CPU time 1.19 seconds
Started Jul 17 07:00:32 PM PDT 24
Finished Jul 17 07:00:37 PM PDT 24
Peak memory 206860 kb
Host smart-f8f1a4e6-667b-44ea-addf-135f946bde5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180969329 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_ou
tstanding.180969329
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.2917994883
Short name T1127
Test name
Test status
Simulation time 106296632 ps
CPU time 3.96 seconds
Started Jul 17 07:00:31 PM PDT 24
Finished Jul 17 07:00:40 PM PDT 24
Peak memory 215148 kb
Host smart-992743d0-8eb6-4b3b-be92-24edce37897f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917994883 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.2917994883
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3655727877
Short name T254
Test name
Test status
Simulation time 1016550483 ps
CPU time 5.11 seconds
Started Jul 17 07:00:27 PM PDT 24
Finished Jul 17 07:00:33 PM PDT 24
Peak memory 206860 kb
Host smart-e803601f-7c23-406c-9f49-582074df642a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655727877 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3655727877
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3130690345
Short name T1109
Test name
Test status
Simulation time 22670412 ps
CPU time 1.2 seconds
Started Jul 17 06:59:42 PM PDT 24
Finished Jul 17 06:59:46 PM PDT 24
Peak memory 206908 kb
Host smart-050ab8ce-4447-4df4-8983-9576dcfa6e14
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130690345 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.3130690345
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.110125165
Short name T1101
Test name
Test status
Simulation time 181345829 ps
CPU time 5.33 seconds
Started Jul 17 06:59:44 PM PDT 24
Finished Jul 17 06:59:53 PM PDT 24
Peak memory 206796 kb
Host smart-ff7e735b-0ea6-4172-9acb-a3b70fce5cbc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110125165 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.110125165
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3645618414
Short name T997
Test name
Test status
Simulation time 41618026 ps
CPU time 0.83 seconds
Started Jul 17 06:59:41 PM PDT 24
Finished Jul 17 06:59:45 PM PDT 24
Peak memory 206648 kb
Host smart-a9f6a8dc-012c-4d13-adc9-58643fa0a1d2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645618414 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3645618414
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1219550799
Short name T1103
Test name
Test status
Simulation time 110042416 ps
CPU time 1.41 seconds
Started Jul 17 06:59:40 PM PDT 24
Finished Jul 17 06:59:45 PM PDT 24
Peak memory 223304 kb
Host smart-91e5f80b-1ce1-4418-aca7-89ad77a8d8a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219550799 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.1219550799
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.2933537235
Short name T1036
Test name
Test status
Simulation time 13867805 ps
CPU time 0.94 seconds
Started Jul 17 06:59:44 PM PDT 24
Finished Jul 17 06:59:48 PM PDT 24
Peak memory 206756 kb
Host smart-465ab325-038a-43b5-a817-a71d9be9b769
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933537235 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2933537235
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.4232190787
Short name T1092
Test name
Test status
Simulation time 15269561 ps
CPU time 0.96 seconds
Started Jul 17 06:59:44 PM PDT 24
Finished Jul 17 06:59:48 PM PDT 24
Peak memory 206764 kb
Host smart-3f0837e0-d6a7-487a-9359-60c9750c9dcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232190787 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.4232190787
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3785300446
Short name T1074
Test name
Test status
Simulation time 85157225 ps
CPU time 1.09 seconds
Started Jul 17 06:59:42 PM PDT 24
Finished Jul 17 06:59:46 PM PDT 24
Peak memory 206884 kb
Host smart-84ac56f5-0aab-4907-a5be-983a9414745d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785300446 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.3785300446
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.1627673914
Short name T1078
Test name
Test status
Simulation time 270446657 ps
CPU time 2.67 seconds
Started Jul 17 06:59:44 PM PDT 24
Finished Jul 17 06:59:51 PM PDT 24
Peak memory 215100 kb
Host smart-b8fd9f32-3ccd-4084-a581-ca612deddfb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627673914 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1627673914
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.324731410
Short name T267
Test name
Test status
Simulation time 244120076 ps
CPU time 1.41 seconds
Started Jul 17 06:59:34 PM PDT 24
Finished Jul 17 06:59:38 PM PDT 24
Peak memory 206968 kb
Host smart-3f19cc5d-511e-4352-8660-47ca9ca309d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324731410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.324731410
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.1271138993
Short name T1086
Test name
Test status
Simulation time 18504577 ps
CPU time 0.79 seconds
Started Jul 17 07:01:50 PM PDT 24
Finished Jul 17 07:01:53 PM PDT 24
Peak memory 206632 kb
Host smart-920979c3-7afc-4ff7-aefc-6e66efe79045
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271138993 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.1271138993
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.3192898259
Short name T1122
Test name
Test status
Simulation time 18529900 ps
CPU time 0.8 seconds
Started Jul 17 07:01:50 PM PDT 24
Finished Jul 17 07:01:52 PM PDT 24
Peak memory 206636 kb
Host smart-ca463373-1b46-48c2-80c1-9304cd11844c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192898259 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.3192898259
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.2315770688
Short name T1055
Test name
Test status
Simulation time 24757422 ps
CPU time 0.86 seconds
Started Jul 17 07:01:52 PM PDT 24
Finished Jul 17 07:01:56 PM PDT 24
Peak memory 206752 kb
Host smart-0b4ff37a-411b-47db-a45f-5ce935ad2fa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315770688 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2315770688
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.3873436245
Short name T1032
Test name
Test status
Simulation time 24378019 ps
CPU time 0.85 seconds
Started Jul 17 07:01:49 PM PDT 24
Finished Jul 17 07:01:51 PM PDT 24
Peak memory 206816 kb
Host smart-45a53cb4-c985-4171-b3ed-270cfb5f3602
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873436245 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3873436245
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.552632112
Short name T1002
Test name
Test status
Simulation time 82827663 ps
CPU time 0.82 seconds
Started Jul 17 07:01:50 PM PDT 24
Finished Jul 17 07:01:52 PM PDT 24
Peak memory 206628 kb
Host smart-eff4a98a-076c-4b35-acf7-0bec447cd434
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552632112 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.552632112
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.83326616
Short name T999
Test name
Test status
Simulation time 103986248 ps
CPU time 0.81 seconds
Started Jul 17 07:01:52 PM PDT 24
Finished Jul 17 07:01:56 PM PDT 24
Peak memory 206600 kb
Host smart-e0f87bd3-1936-43a1-9b58-50a75b746f0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83326616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.83326616
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.1289689288
Short name T1027
Test name
Test status
Simulation time 12885594 ps
CPU time 0.86 seconds
Started Jul 17 07:01:51 PM PDT 24
Finished Jul 17 07:01:54 PM PDT 24
Peak memory 206808 kb
Host smart-5f150270-e105-4ccb-8a53-1011d23e3f9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289689288 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.1289689288
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.3134053277
Short name T1010
Test name
Test status
Simulation time 21868985 ps
CPU time 0.84 seconds
Started Jul 17 07:01:51 PM PDT 24
Finished Jul 17 07:01:55 PM PDT 24
Peak memory 206812 kb
Host smart-47972120-2ed4-4f47-9dd4-c72fa4723568
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134053277 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3134053277
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2788240165
Short name T1099
Test name
Test status
Simulation time 114710173 ps
CPU time 0.8 seconds
Started Jul 17 07:01:53 PM PDT 24
Finished Jul 17 07:01:57 PM PDT 24
Peak memory 206544 kb
Host smart-d0116b00-5a05-4611-88bb-f2a4ec76df32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788240165 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2788240165
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.3963272778
Short name T1096
Test name
Test status
Simulation time 19585224 ps
CPU time 0.92 seconds
Started Jul 17 07:01:53 PM PDT 24
Finished Jul 17 07:01:59 PM PDT 24
Peak memory 206752 kb
Host smart-526ad44f-f68b-444b-b78b-4251a5a89637
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963272778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.3963272778
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.186112431
Short name T235
Test name
Test status
Simulation time 56656214 ps
CPU time 1.01 seconds
Started Jul 17 06:59:41 PM PDT 24
Finished Jul 17 06:59:45 PM PDT 24
Peak memory 206892 kb
Host smart-d0f53539-1031-42c2-ad94-cd21939d01c1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186112431 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.186112431
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3992291776
Short name T1022
Test name
Test status
Simulation time 112680193 ps
CPU time 3.4 seconds
Started Jul 17 06:59:42 PM PDT 24
Finished Jul 17 06:59:49 PM PDT 24
Peak memory 206800 kb
Host smart-04fe20df-201a-420b-a6ac-5d5849921c7a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992291776 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3992291776
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.4283272428
Short name T239
Test name
Test status
Simulation time 15880969 ps
CPU time 0.94 seconds
Started Jul 17 06:59:40 PM PDT 24
Finished Jul 17 06:59:44 PM PDT 24
Peak memory 206820 kb
Host smart-6a4602b1-0380-49ea-9a2d-bd4ed3774b60
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283272428 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.4283272428
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2099954766
Short name T1070
Test name
Test status
Simulation time 26460998 ps
CPU time 1.86 seconds
Started Jul 17 06:59:45 PM PDT 24
Finished Jul 17 06:59:50 PM PDT 24
Peak memory 215144 kb
Host smart-9b681ffd-7fb4-4572-9c62-d200f4aebb09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099954766 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2099954766
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1966201841
Short name T1034
Test name
Test status
Simulation time 15332105 ps
CPU time 0.93 seconds
Started Jul 17 06:59:42 PM PDT 24
Finished Jul 17 06:59:46 PM PDT 24
Peak memory 206808 kb
Host smart-d5a661e3-8e51-4f5a-a38b-b75a931ae164
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966201841 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1966201841
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.1211529877
Short name T1087
Test name
Test status
Simulation time 15176235 ps
CPU time 0.88 seconds
Started Jul 17 06:59:44 PM PDT 24
Finished Jul 17 06:59:48 PM PDT 24
Peak memory 206796 kb
Host smart-79fa737c-b50a-47a2-8032-e8c404cf6c16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211529877 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1211529877
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3109319392
Short name T247
Test name
Test status
Simulation time 62049464 ps
CPU time 1.13 seconds
Started Jul 17 06:59:42 PM PDT 24
Finished Jul 17 06:59:46 PM PDT 24
Peak memory 206928 kb
Host smart-5b28a4d8-75d5-4a58-a957-f46b96bf8149
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109319392 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.3109319392
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.1791864311
Short name T1023
Test name
Test status
Simulation time 66811555 ps
CPU time 2.98 seconds
Started Jul 17 06:59:41 PM PDT 24
Finished Jul 17 06:59:47 PM PDT 24
Peak memory 215224 kb
Host smart-12600f3f-7511-4774-a3bf-9c03c41fd69e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791864311 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.1791864311
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2586303415
Short name T256
Test name
Test status
Simulation time 238860914 ps
CPU time 1.79 seconds
Started Jul 17 06:59:41 PM PDT 24
Finished Jul 17 06:59:46 PM PDT 24
Peak memory 206972 kb
Host smart-9cde96ad-f42f-41c3-9427-36fc65af5ad5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586303415 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.2586303415
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.425578424
Short name T998
Test name
Test status
Simulation time 31434841 ps
CPU time 0.82 seconds
Started Jul 17 07:01:50 PM PDT 24
Finished Jul 17 07:01:52 PM PDT 24
Peak memory 206812 kb
Host smart-826b1e21-faf7-4e29-9c87-568a83c7790c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425578424 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.425578424
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.3313140058
Short name T1111
Test name
Test status
Simulation time 26073335 ps
CPU time 0.88 seconds
Started Jul 17 07:01:50 PM PDT 24
Finished Jul 17 07:01:52 PM PDT 24
Peak memory 206816 kb
Host smart-725853b2-da89-4f6b-9254-ccb95d40da29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313140058 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.3313140058
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.3746451778
Short name T1079
Test name
Test status
Simulation time 35463721 ps
CPU time 0.84 seconds
Started Jul 17 07:01:53 PM PDT 24
Finished Jul 17 07:01:58 PM PDT 24
Peak memory 206624 kb
Host smart-3f04012a-1233-471c-89cc-d7d49cb14ec7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746451778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3746451778
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.2967113422
Short name T1029
Test name
Test status
Simulation time 14425382 ps
CPU time 0.86 seconds
Started Jul 17 07:01:51 PM PDT 24
Finished Jul 17 07:01:55 PM PDT 24
Peak memory 206832 kb
Host smart-39b93bfb-ced0-44df-8a4c-676330797578
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967113422 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2967113422
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.1717910770
Short name T996
Test name
Test status
Simulation time 69292557 ps
CPU time 0.8 seconds
Started Jul 17 07:01:51 PM PDT 24
Finished Jul 17 07:01:54 PM PDT 24
Peak memory 206628 kb
Host smart-50d78ddb-4ccb-40b4-bcac-9d4478474d1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717910770 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1717910770
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1459922038
Short name T1063
Test name
Test status
Simulation time 32127437 ps
CPU time 0.77 seconds
Started Jul 17 07:01:50 PM PDT 24
Finished Jul 17 07:01:53 PM PDT 24
Peak memory 206656 kb
Host smart-499be09a-3fa3-4a36-8a0d-1d4f1bd74401
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459922038 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1459922038
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.4053672655
Short name T1054
Test name
Test status
Simulation time 35781294 ps
CPU time 0.86 seconds
Started Jul 17 07:01:47 PM PDT 24
Finished Jul 17 07:01:48 PM PDT 24
Peak memory 206816 kb
Host smart-7e1ed655-6666-4938-badf-8c072bcee3b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053672655 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.4053672655
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.1955565702
Short name T1016
Test name
Test status
Simulation time 31323881 ps
CPU time 0.89 seconds
Started Jul 17 07:01:54 PM PDT 24
Finished Jul 17 07:02:01 PM PDT 24
Peak memory 206812 kb
Host smart-28089397-0431-42ff-8582-352c361969e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955565702 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1955565702
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.2462157350
Short name T1007
Test name
Test status
Simulation time 15558245 ps
CPU time 0.82 seconds
Started Jul 17 07:01:53 PM PDT 24
Finished Jul 17 07:01:58 PM PDT 24
Peak memory 206576 kb
Host smart-a224026d-d6d8-4cfc-a904-1486411479be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462157350 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.2462157350
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.4113335248
Short name T1057
Test name
Test status
Simulation time 16025374 ps
CPU time 0.94 seconds
Started Jul 17 07:01:51 PM PDT 24
Finished Jul 17 07:01:55 PM PDT 24
Peak memory 206684 kb
Host smart-bf8eff5d-c9b0-4874-9b48-9a943f3680eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113335248 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.4113335248
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3131551840
Short name T238
Test name
Test status
Simulation time 41314696 ps
CPU time 1.18 seconds
Started Jul 17 07:00:30 PM PDT 24
Finished Jul 17 07:00:34 PM PDT 24
Peak memory 206792 kb
Host smart-6358ce3f-4cb6-4cc7-9d94-16e1c7388260
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131551840 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.3131551840
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2713366037
Short name T1112
Test name
Test status
Simulation time 37800556 ps
CPU time 2.03 seconds
Started Jul 17 06:59:44 PM PDT 24
Finished Jul 17 06:59:50 PM PDT 24
Peak memory 206896 kb
Host smart-1f8c2abb-bc88-442c-b2fe-c50ddb9f97bb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713366037 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2713366037
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3555157340
Short name T234
Test name
Test status
Simulation time 23794222 ps
CPU time 0.81 seconds
Started Jul 17 06:59:44 PM PDT 24
Finished Jul 17 06:59:49 PM PDT 24
Peak memory 206700 kb
Host smart-f3753199-60fb-4d9d-a720-2f3c50552eb5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555157340 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3555157340
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.919442211
Short name T1020
Test name
Test status
Simulation time 16044727 ps
CPU time 1.13 seconds
Started Jul 17 07:00:28 PM PDT 24
Finished Jul 17 07:00:30 PM PDT 24
Peak memory 215212 kb
Host smart-b1e68ed5-870c-4f02-a6cf-dd5b824b482b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919442211 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.919442211
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.2387386181
Short name T244
Test name
Test status
Simulation time 14089698 ps
CPU time 0.82 seconds
Started Jul 17 06:59:44 PM PDT 24
Finished Jul 17 06:59:49 PM PDT 24
Peak memory 206864 kb
Host smart-8da0b1b9-6019-4fba-b8ce-1ac34a26d234
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387386181 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2387386181
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.3459629589
Short name T1106
Test name
Test status
Simulation time 15354687 ps
CPU time 0.91 seconds
Started Jul 17 06:59:42 PM PDT 24
Finished Jul 17 06:59:47 PM PDT 24
Peak memory 206816 kb
Host smart-182deca2-6ce6-4c8e-a79a-c2e4f166be67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459629589 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.3459629589
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.4231579130
Short name T230
Test name
Test status
Simulation time 25069193 ps
CPU time 0.97 seconds
Started Jul 17 07:00:26 PM PDT 24
Finished Jul 17 07:00:27 PM PDT 24
Peak memory 206912 kb
Host smart-1c62a120-96fb-4b8f-bc0b-78605f84298e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231579130 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.4231579130
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.2231984993
Short name T1113
Test name
Test status
Simulation time 112536110 ps
CPU time 3.96 seconds
Started Jul 17 06:59:45 PM PDT 24
Finished Jul 17 06:59:52 PM PDT 24
Peak memory 215228 kb
Host smart-f7a792bd-f025-429a-8220-5fb501ba231f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231984993 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2231984993
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3857754900
Short name T1120
Test name
Test status
Simulation time 111667611 ps
CPU time 2.53 seconds
Started Jul 17 06:59:44 PM PDT 24
Finished Jul 17 06:59:50 PM PDT 24
Peak memory 215156 kb
Host smart-b248846c-171d-41ee-936a-c6a4cdf249b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857754900 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.3857754900
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.667216427
Short name T1066
Test name
Test status
Simulation time 36982256 ps
CPU time 0.81 seconds
Started Jul 17 07:01:52 PM PDT 24
Finished Jul 17 07:01:57 PM PDT 24
Peak memory 206712 kb
Host smart-3bbc4cda-5233-4109-b627-21e48d505693
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667216427 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.667216427
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.2221834869
Short name T1058
Test name
Test status
Simulation time 17228939 ps
CPU time 0.88 seconds
Started Jul 17 07:01:37 PM PDT 24
Finished Jul 17 07:01:39 PM PDT 24
Peak memory 207032 kb
Host smart-6bc32b92-b1de-445e-a62f-01b49f5970f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221834869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.2221834869
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.3307909102
Short name T1011
Test name
Test status
Simulation time 17098105 ps
CPU time 0.88 seconds
Started Jul 17 07:01:53 PM PDT 24
Finished Jul 17 07:01:58 PM PDT 24
Peak memory 206824 kb
Host smart-b2266f33-3e41-4e24-a242-1acbdaf5ea75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307909102 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3307909102
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.724780647
Short name T994
Test name
Test status
Simulation time 17090725 ps
CPU time 0.89 seconds
Started Jul 17 07:01:50 PM PDT 24
Finished Jul 17 07:01:53 PM PDT 24
Peak memory 206800 kb
Host smart-e5509398-d0ae-42dd-9275-d933152bcdc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724780647 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.724780647
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.2583466341
Short name T1045
Test name
Test status
Simulation time 21243403 ps
CPU time 0.84 seconds
Started Jul 17 07:01:51 PM PDT 24
Finished Jul 17 07:01:54 PM PDT 24
Peak memory 206680 kb
Host smart-813700e7-8a54-4156-bc0a-61a989a80420
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583466341 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2583466341
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.2239634837
Short name T1080
Test name
Test status
Simulation time 27414698 ps
CPU time 0.87 seconds
Started Jul 17 07:01:55 PM PDT 24
Finished Jul 17 07:02:03 PM PDT 24
Peak memory 206904 kb
Host smart-e882cbe1-e76c-475c-8dba-eb55cc0e6671
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239634837 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.2239634837
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.3260121484
Short name T1060
Test name
Test status
Simulation time 27078802 ps
CPU time 0.85 seconds
Started Jul 17 07:01:50 PM PDT 24
Finished Jul 17 07:01:53 PM PDT 24
Peak memory 206684 kb
Host smart-27e1e87f-c124-4d74-87ff-920680a2a44a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260121484 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.3260121484
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.380463284
Short name T1040
Test name
Test status
Simulation time 41993148 ps
CPU time 0.85 seconds
Started Jul 17 07:01:51 PM PDT 24
Finished Jul 17 07:01:55 PM PDT 24
Peak memory 206900 kb
Host smart-1d0a6f84-fefd-4928-9cef-c9d922bdadeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380463284 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.380463284
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.3117130504
Short name T1116
Test name
Test status
Simulation time 22874577 ps
CPU time 0.85 seconds
Started Jul 17 07:01:41 PM PDT 24
Finished Jul 17 07:01:44 PM PDT 24
Peak memory 206816 kb
Host smart-168e43ad-d3bb-451b-877b-2a66d4ee3075
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117130504 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3117130504
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.2786710495
Short name T1084
Test name
Test status
Simulation time 72369529 ps
CPU time 0.88 seconds
Started Jul 17 07:01:52 PM PDT 24
Finished Jul 17 07:01:56 PM PDT 24
Peak memory 206800 kb
Host smart-bef15383-195b-4c3b-8146-d195f0954bdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786710495 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.2786710495
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.764180100
Short name T1124
Test name
Test status
Simulation time 28148408 ps
CPU time 1.28 seconds
Started Jul 17 07:00:29 PM PDT 24
Finished Jul 17 07:00:32 PM PDT 24
Peak memory 215244 kb
Host smart-07db1683-7ece-407d-9667-07838dd9e012
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764180100 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.764180100
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.4013174686
Short name T1064
Test name
Test status
Simulation time 14779720 ps
CPU time 0.92 seconds
Started Jul 17 07:00:27 PM PDT 24
Finished Jul 17 07:00:28 PM PDT 24
Peak memory 207016 kb
Host smart-0660f9ca-8df5-4327-844a-4c870081d1eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013174686 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.4013174686
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.4257777421
Short name T1088
Test name
Test status
Simulation time 45629099 ps
CPU time 0.82 seconds
Started Jul 17 07:00:29 PM PDT 24
Finished Jul 17 07:00:32 PM PDT 24
Peak memory 206816 kb
Host smart-68f09bfd-6123-4c5c-825e-837d600ed86f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257777421 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.4257777421
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1901103760
Short name T1050
Test name
Test status
Simulation time 32585689 ps
CPU time 0.98 seconds
Started Jul 17 07:00:32 PM PDT 24
Finished Jul 17 07:00:37 PM PDT 24
Peak memory 206920 kb
Host smart-360b4a3f-3dbb-4808-a9a0-ce1c51b95c49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901103760 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1901103760
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.553029535
Short name T1077
Test name
Test status
Simulation time 186263372 ps
CPU time 3.16 seconds
Started Jul 17 07:00:31 PM PDT 24
Finished Jul 17 07:00:38 PM PDT 24
Peak memory 215148 kb
Host smart-9db9775e-a3e2-42bb-8a61-81376fb0d28a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553029535 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.553029535
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2334191281
Short name T266
Test name
Test status
Simulation time 188426291 ps
CPU time 2.35 seconds
Started Jul 17 07:00:31 PM PDT 24
Finished Jul 17 07:00:37 PM PDT 24
Peak memory 206872 kb
Host smart-e5c69dbc-e661-451e-a1f7-12f9872d5660
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334191281 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2334191281
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3495844161
Short name T1037
Test name
Test status
Simulation time 39292666 ps
CPU time 1.44 seconds
Started Jul 17 07:00:28 PM PDT 24
Finished Jul 17 07:00:31 PM PDT 24
Peak memory 218676 kb
Host smart-ba9a5155-20d6-4cb9-a83e-956fbb7f032a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495844161 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3495844161
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.20456129
Short name T237
Test name
Test status
Simulation time 12085404 ps
CPU time 0.92 seconds
Started Jul 17 07:00:28 PM PDT 24
Finished Jul 17 07:00:30 PM PDT 24
Peak memory 206776 kb
Host smart-71441332-ea41-4474-ba68-7eb86e5a0b08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20456129 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.20456129
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3686222029
Short name T1065
Test name
Test status
Simulation time 13210461 ps
CPU time 0.85 seconds
Started Jul 17 07:00:29 PM PDT 24
Finished Jul 17 07:00:33 PM PDT 24
Peak memory 206784 kb
Host smart-712d8640-0678-4008-9f96-515e2cb2ecbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686222029 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3686222029
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.938095332
Short name T1052
Test name
Test status
Simulation time 76987266 ps
CPU time 1.1 seconds
Started Jul 17 07:00:28 PM PDT 24
Finished Jul 17 07:00:31 PM PDT 24
Peak memory 206896 kb
Host smart-688f6a57-82e6-4768-93f3-5652d3b8eecd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938095332 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_out
standing.938095332
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.2863369217
Short name T1076
Test name
Test status
Simulation time 106163995 ps
CPU time 3.86 seconds
Started Jul 17 07:00:27 PM PDT 24
Finished Jul 17 07:00:31 PM PDT 24
Peak memory 215208 kb
Host smart-e92f1796-99dc-42f9-b260-9e143f09c2d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863369217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2863369217
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1123648329
Short name T1126
Test name
Test status
Simulation time 198617725 ps
CPU time 2.59 seconds
Started Jul 17 07:00:34 PM PDT 24
Finished Jul 17 07:00:40 PM PDT 24
Peak memory 206968 kb
Host smart-75b79721-c67a-46ec-952d-c60e773fad79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123648329 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.1123648329
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3243757224
Short name T1028
Test name
Test status
Simulation time 55125758 ps
CPU time 0.99 seconds
Started Jul 17 07:00:29 PM PDT 24
Finished Jul 17 07:00:32 PM PDT 24
Peak memory 216544 kb
Host smart-faec04f2-977b-4390-bc85-4c32cb1e5917
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243757224 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.3243757224
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.3263427904
Short name T241
Test name
Test status
Simulation time 26558048 ps
CPU time 0.92 seconds
Started Jul 17 07:00:28 PM PDT 24
Finished Jul 17 07:00:29 PM PDT 24
Peak memory 206736 kb
Host smart-9f4433fe-f7ff-442b-9a8d-709815092cdf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263427904 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.3263427904
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.1653337224
Short name T1001
Test name
Test status
Simulation time 20252813 ps
CPU time 0.82 seconds
Started Jul 17 07:00:29 PM PDT 24
Finished Jul 17 07:00:32 PM PDT 24
Peak memory 206668 kb
Host smart-500da528-b547-48a2-a05f-d3f28baaee0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653337224 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.1653337224
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1147668688
Short name T1094
Test name
Test status
Simulation time 21303449 ps
CPU time 1.14 seconds
Started Jul 17 07:00:32 PM PDT 24
Finished Jul 17 07:00:37 PM PDT 24
Peak memory 206816 kb
Host smart-f08b7dae-e034-4f4d-9262-ed96686d851a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147668688 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.1147668688
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.332306707
Short name T1015
Test name
Test status
Simulation time 199947720 ps
CPU time 3.81 seconds
Started Jul 17 07:00:29 PM PDT 24
Finished Jul 17 07:00:34 PM PDT 24
Peak memory 215236 kb
Host smart-5a4ae90f-326e-4710-81d2-0b39a7be0ea6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332306707 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.332306707
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3011593330
Short name T255
Test name
Test status
Simulation time 187520400 ps
CPU time 1.68 seconds
Started Jul 17 07:00:30 PM PDT 24
Finished Jul 17 07:00:35 PM PDT 24
Peak memory 215144 kb
Host smart-2ac0ef49-0033-48a1-a67e-9ede97a395e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011593330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.3011593330
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.4116242776
Short name T1003
Test name
Test status
Simulation time 36884900 ps
CPU time 1.6 seconds
Started Jul 17 07:00:28 PM PDT 24
Finished Jul 17 07:00:31 PM PDT 24
Peak memory 215300 kb
Host smart-2df184ad-884e-4d22-9111-416ef7411d16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116242776 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.4116242776
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.3110129837
Short name T236
Test name
Test status
Simulation time 17910332 ps
CPU time 1 seconds
Started Jul 17 07:00:31 PM PDT 24
Finished Jul 17 07:00:36 PM PDT 24
Peak memory 206764 kb
Host smart-1ecc391d-8aba-42f2-a999-a99864a3602b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110129837 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.3110129837
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.3900054998
Short name T1100
Test name
Test status
Simulation time 14450217 ps
CPU time 0.86 seconds
Started Jul 17 07:00:31 PM PDT 24
Finished Jul 17 07:00:36 PM PDT 24
Peak memory 206772 kb
Host smart-a9d39ba0-fe3a-4906-8346-aef08f8a559f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900054998 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.3900054998
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.730984632
Short name T1041
Test name
Test status
Simulation time 22655559 ps
CPU time 1.08 seconds
Started Jul 17 07:00:33 PM PDT 24
Finished Jul 17 07:00:38 PM PDT 24
Peak memory 207068 kb
Host smart-23a7616f-87a8-4586-aaf1-7498bf87b4c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730984632 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_out
standing.730984632
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.1228865135
Short name T1110
Test name
Test status
Simulation time 147422191 ps
CPU time 3.15 seconds
Started Jul 17 07:00:28 PM PDT 24
Finished Jul 17 07:00:33 PM PDT 24
Peak memory 215064 kb
Host smart-308301fb-b6ca-4ec0-b30e-aa508a4ee3eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228865135 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.1228865135
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.335415882
Short name T1105
Test name
Test status
Simulation time 112191245 ps
CPU time 2.89 seconds
Started Jul 17 07:00:33 PM PDT 24
Finished Jul 17 07:00:40 PM PDT 24
Peak memory 207080 kb
Host smart-067cd32a-e559-41a8-a169-68fdf0125550
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335415882 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.335415882
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3385020979
Short name T1026
Test name
Test status
Simulation time 106934449 ps
CPU time 1.36 seconds
Started Jul 17 07:00:25 PM PDT 24
Finished Jul 17 07:00:27 PM PDT 24
Peak memory 215168 kb
Host smart-aca8d087-7fe1-418b-b673-551036f09f7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385020979 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.3385020979
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.3149122879
Short name T1048
Test name
Test status
Simulation time 47922319 ps
CPU time 0.8 seconds
Started Jul 17 07:00:28 PM PDT 24
Finished Jul 17 07:00:31 PM PDT 24
Peak memory 206612 kb
Host smart-e2b14af5-b889-4566-9c78-28209ab1a98d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149122879 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3149122879
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2038110967
Short name T1013
Test name
Test status
Simulation time 12064477 ps
CPU time 0.82 seconds
Started Jul 17 07:00:31 PM PDT 24
Finished Jul 17 07:00:37 PM PDT 24
Peak memory 206680 kb
Host smart-ac25a32a-d149-434c-b507-525450c8f41f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038110967 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2038110967
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1615954423
Short name T246
Test name
Test status
Simulation time 245311912 ps
CPU time 0.94 seconds
Started Jul 17 07:00:31 PM PDT 24
Finished Jul 17 07:00:36 PM PDT 24
Peak memory 206864 kb
Host smart-5597b965-96aa-4ea7-8464-99e78dd8195a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615954423 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1615954423
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.167532787
Short name T1039
Test name
Test status
Simulation time 127003071 ps
CPU time 4.06 seconds
Started Jul 17 07:00:30 PM PDT 24
Finished Jul 17 07:00:37 PM PDT 24
Peak memory 219352 kb
Host smart-981c84ec-78b3-405b-8b4e-04218b2beaf5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167532787 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.167532787
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.942820174
Short name T263
Test name
Test status
Simulation time 89381251 ps
CPU time 1.63 seconds
Started Jul 17 07:00:27 PM PDT 24
Finished Jul 17 07:00:29 PM PDT 24
Peak memory 206872 kb
Host smart-236b32a4-5a4a-46dd-bcd8-46b54eb923c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942820174 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.942820174
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert_test.2439076380
Short name T508
Test name
Test status
Simulation time 28577620 ps
CPU time 0.93 seconds
Started Jul 17 07:14:37 PM PDT 24
Finished Jul 17 07:14:45 PM PDT 24
Peak memory 206348 kb
Host smart-e2cbd133-e491-402b-84b7-2a360865f3e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439076380 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2439076380
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_err.2634764028
Short name T419
Test name
Test status
Simulation time 297790854 ps
CPU time 1.1 seconds
Started Jul 17 07:14:33 PM PDT 24
Finished Jul 17 07:14:39 PM PDT 24
Peak memory 220008 kb
Host smart-164d5043-65f3-4c3d-b97f-f2509ae2efc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634764028 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.2634764028
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.2430346113
Short name T988
Test name
Test status
Simulation time 40008130 ps
CPU time 1.25 seconds
Started Jul 17 07:14:37 PM PDT 24
Finished Jul 17 07:14:46 PM PDT 24
Peak memory 218460 kb
Host smart-62e4f6ae-16e5-48cc-8b24-f0f5671e4573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430346113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2430346113
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.50921601
Short name T873
Test name
Test status
Simulation time 22075492 ps
CPU time 1.11 seconds
Started Jul 17 07:14:37 PM PDT 24
Finished Jul 17 07:14:45 PM PDT 24
Peak memory 215800 kb
Host smart-1a6da379-eedc-4a9b-8e58-8d05621b5413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50921601 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.50921601
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.2935379091
Short name T440
Test name
Test status
Simulation time 20287982 ps
CPU time 0.99 seconds
Started Jul 17 07:14:36 PM PDT 24
Finished Jul 17 07:14:44 PM PDT 24
Peak memory 207360 kb
Host smart-6773503f-8e25-486e-be75-e60ff2aa66c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935379091 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.2935379091
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_smoke.4052159977
Short name T466
Test name
Test status
Simulation time 16143022 ps
CPU time 0.99 seconds
Started Jul 17 07:14:36 PM PDT 24
Finished Jul 17 07:14:44 PM PDT 24
Peak memory 215540 kb
Host smart-d55eddd6-c0aa-462a-a655-cb591ab5b5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052159977 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.4052159977
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.4051434596
Short name T406
Test name
Test status
Simulation time 580959326 ps
CPU time 3.82 seconds
Started Jul 17 07:14:37 PM PDT 24
Finished Jul 17 07:14:47 PM PDT 24
Peak memory 215512 kb
Host smart-1b123736-8be9-457b-8d09-82dca852aca2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051434596 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.4051434596
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_alert.3931339843
Short name T177
Test name
Test status
Simulation time 27145117 ps
CPU time 1.14 seconds
Started Jul 17 07:14:37 PM PDT 24
Finished Jul 17 07:14:46 PM PDT 24
Peak memory 220316 kb
Host smart-0e47e8d6-cdd6-4582-9b08-d54cc2d946ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931339843 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.3931339843
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.993566560
Short name T528
Test name
Test status
Simulation time 22676723 ps
CPU time 1.03 seconds
Started Jul 17 07:14:36 PM PDT 24
Finished Jul 17 07:14:44 PM PDT 24
Peak memory 207024 kb
Host smart-8bc6d422-1d7d-491b-9d10-20da7ed8d3b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993566560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.993566560
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.1382778660
Short name T948
Test name
Test status
Simulation time 21650519 ps
CPU time 0.87 seconds
Started Jul 17 07:14:37 PM PDT 24
Finished Jul 17 07:14:45 PM PDT 24
Peak memory 216324 kb
Host smart-7a7e5391-4039-40a9-aecc-8b8e4e2d5dae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382778660 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.1382778660
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_err.3190326708
Short name T360
Test name
Test status
Simulation time 18470413 ps
CPU time 1.01 seconds
Started Jul 17 07:14:37 PM PDT 24
Finished Jul 17 07:14:46 PM PDT 24
Peak memory 218692 kb
Host smart-4298ce6a-4ce2-4181-81f4-00addbb3c329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190326708 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.3190326708
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.3719684834
Short name T288
Test name
Test status
Simulation time 52321206 ps
CPU time 1.9 seconds
Started Jul 17 07:14:38 PM PDT 24
Finished Jul 17 07:14:47 PM PDT 24
Peak memory 220076 kb
Host smart-a6a4b3d7-c648-47ef-b3b9-d76042e21f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719684834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.3719684834
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.1821328360
Short name T34
Test name
Test status
Simulation time 25506992 ps
CPU time 0.97 seconds
Started Jul 17 07:14:38 PM PDT 24
Finished Jul 17 07:14:46 PM PDT 24
Peak memory 216036 kb
Host smart-48051d9d-e3fc-4688-9961-bd2d1a675678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821328360 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.1821328360
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.2471472214
Short name T718
Test name
Test status
Simulation time 37578741 ps
CPU time 0.9 seconds
Started Jul 17 07:14:39 PM PDT 24
Finished Jul 17 07:14:47 PM PDT 24
Peak memory 207444 kb
Host smart-23d970cc-7a13-4673-afe8-e598e0779e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471472214 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.2471472214
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.935533253
Short name T55
Test name
Test status
Simulation time 930014503 ps
CPU time 3.96 seconds
Started Jul 17 07:14:34 PM PDT 24
Finished Jul 17 07:14:44 PM PDT 24
Peak memory 236956 kb
Host smart-d1f07e38-56f6-4838-897e-fb21c800c410
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935533253 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.935533253
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.2263024018
Short name T436
Test name
Test status
Simulation time 33548104 ps
CPU time 0.91 seconds
Started Jul 17 07:14:33 PM PDT 24
Finished Jul 17 07:14:38 PM PDT 24
Peak memory 215556 kb
Host smart-4520017b-c559-4c5e-8ccf-c95cfd253360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263024018 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.2263024018
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.2292749094
Short name T281
Test name
Test status
Simulation time 206685328 ps
CPU time 1.04 seconds
Started Jul 17 07:14:39 PM PDT 24
Finished Jul 17 07:14:47 PM PDT 24
Peak memory 215624 kb
Host smart-f2c3dcc2-5e46-4515-918b-9f7b6851ddc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292749094 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2292749094
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_alert_test.202972916
Short name T887
Test name
Test status
Simulation time 41172810 ps
CPU time 0.83 seconds
Started Jul 17 07:14:51 PM PDT 24
Finished Jul 17 07:14:54 PM PDT 24
Peak memory 206848 kb
Host smart-744fc808-434b-4e05-a918-82fad62af0bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202972916 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.202972916
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.1879706074
Short name T702
Test name
Test status
Simulation time 21159983 ps
CPU time 0.86 seconds
Started Jul 17 07:14:56 PM PDT 24
Finished Jul 17 07:15:01 PM PDT 24
Peak memory 216592 kb
Host smart-f4bdc872-078f-4b44-b706-6c88a9232c80
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879706074 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.1879706074
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.1009418110
Short name T944
Test name
Test status
Simulation time 37101084 ps
CPU time 1.23 seconds
Started Jul 17 07:14:47 PM PDT 24
Finished Jul 17 07:14:49 PM PDT 24
Peak memory 220088 kb
Host smart-7956a7d6-718b-4111-9454-d97fb15aafb0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009418110 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.1009418110
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.3231024339
Short name T143
Test name
Test status
Simulation time 23547749 ps
CPU time 0.97 seconds
Started Jul 17 07:14:58 PM PDT 24
Finished Jul 17 07:15:08 PM PDT 24
Peak memory 218956 kb
Host smart-9292dca8-7e44-4502-a782-8a75befc29f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231024339 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.3231024339
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.3267358494
Short name T319
Test name
Test status
Simulation time 104588964 ps
CPU time 1.22 seconds
Started Jul 17 07:14:58 PM PDT 24
Finished Jul 17 07:15:07 PM PDT 24
Peak memory 217676 kb
Host smart-1e40c86c-2aa8-40b5-ac27-a0827ecaed51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267358494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3267358494
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.1990315982
Short name T974
Test name
Test status
Simulation time 21371039 ps
CPU time 1.06 seconds
Started Jul 17 07:14:56 PM PDT 24
Finished Jul 17 07:14:58 PM PDT 24
Peak memory 215816 kb
Host smart-2589c95f-8972-4d0e-a870-cc8a35dae1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990315982 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1990315982
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.2661582115
Short name T884
Test name
Test status
Simulation time 19410224 ps
CPU time 1.05 seconds
Started Jul 17 07:14:51 PM PDT 24
Finished Jul 17 07:14:54 PM PDT 24
Peak memory 215588 kb
Host smart-2ad40f09-b3d2-43d3-958c-fcb4ab958ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661582115 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.2661582115
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.3089709874
Short name T220
Test name
Test status
Simulation time 70983645 ps
CPU time 1.83 seconds
Started Jul 17 07:14:52 PM PDT 24
Finished Jul 17 07:14:55 PM PDT 24
Peak memory 215532 kb
Host smart-bccf452c-97e8-4eaa-a5d4-165225b7847d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089709874 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.3089709874
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/100.edn_genbits.2859743131
Short name T650
Test name
Test status
Simulation time 66961667 ps
CPU time 1.04 seconds
Started Jul 17 07:18:03 PM PDT 24
Finished Jul 17 07:18:05 PM PDT 24
Peak memory 217600 kb
Host smart-846ae5e9-030d-43fa-bbaa-ac06f9443772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859743131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2859743131
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.2317631596
Short name T940
Test name
Test status
Simulation time 63350542 ps
CPU time 1.42 seconds
Started Jul 17 07:18:12 PM PDT 24
Finished Jul 17 07:18:18 PM PDT 24
Peak memory 218696 kb
Host smart-8411197c-84db-45a0-81a0-ca0a4842c628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317631596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.2317631596
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.3485455763
Short name T202
Test name
Test status
Simulation time 88332812 ps
CPU time 1.11 seconds
Started Jul 17 07:18:08 PM PDT 24
Finished Jul 17 07:18:10 PM PDT 24
Peak memory 220112 kb
Host smart-5649f420-25e9-4a20-868d-3bc7537e7fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485455763 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.3485455763
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.3137710257
Short name T980
Test name
Test status
Simulation time 46101963 ps
CPU time 1.57 seconds
Started Jul 17 07:18:08 PM PDT 24
Finished Jul 17 07:18:11 PM PDT 24
Peak memory 220436 kb
Host smart-bdc9066d-204b-4fe3-aa13-2e42f56677c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137710257 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.3137710257
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.28563845
Short name T86
Test name
Test status
Simulation time 47775583 ps
CPU time 1.24 seconds
Started Jul 17 07:18:06 PM PDT 24
Finished Jul 17 07:18:09 PM PDT 24
Peak memory 218856 kb
Host smart-4338beb6-491d-45df-9999-cf31e9f591ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28563845 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.28563845
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.228372319
Short name T349
Test name
Test status
Simulation time 34883589 ps
CPU time 1.37 seconds
Started Jul 17 07:18:06 PM PDT 24
Finished Jul 17 07:18:08 PM PDT 24
Peak memory 220072 kb
Host smart-cec93346-cc6e-4e3a-8cc9-17536534b51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228372319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.228372319
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.2454393914
Short name T655
Test name
Test status
Simulation time 42702321 ps
CPU time 1.17 seconds
Started Jul 17 07:18:06 PM PDT 24
Finished Jul 17 07:18:08 PM PDT 24
Peak memory 218908 kb
Host smart-48686220-075d-42be-8eb9-4ae212438ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454393914 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.2454393914
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.2253517280
Short name T984
Test name
Test status
Simulation time 100422035 ps
CPU time 1.37 seconds
Started Jul 17 07:18:06 PM PDT 24
Finished Jul 17 07:18:09 PM PDT 24
Peak memory 218928 kb
Host smart-507ef86f-4425-4061-9807-73b5a23e0b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253517280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.2253517280
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.598578515
Short name T622
Test name
Test status
Simulation time 41925781 ps
CPU time 1.06 seconds
Started Jul 17 07:18:08 PM PDT 24
Finished Jul 17 07:18:11 PM PDT 24
Peak memory 219880 kb
Host smart-2267f29e-7eed-4dd1-92fd-ed1203336d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598578515 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.598578515
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.3069983841
Short name T306
Test name
Test status
Simulation time 78407645 ps
CPU time 1.72 seconds
Started Jul 17 07:18:09 PM PDT 24
Finished Jul 17 07:18:12 PM PDT 24
Peak memory 218832 kb
Host smart-0eb72ef7-d3f7-4e59-9997-f53b83a8751c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069983841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.3069983841
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.3803404187
Short name T252
Test name
Test status
Simulation time 45090020 ps
CPU time 1.19 seconds
Started Jul 17 07:18:10 PM PDT 24
Finished Jul 17 07:18:14 PM PDT 24
Peak memory 218708 kb
Host smart-9aee515f-60ed-4066-b7f4-1043d49fddb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803404187 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.3803404187
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.3385953698
Short name T689
Test name
Test status
Simulation time 107406781 ps
CPU time 1.25 seconds
Started Jul 17 07:18:11 PM PDT 24
Finished Jul 17 07:18:15 PM PDT 24
Peak memory 220364 kb
Host smart-6cd35509-93dc-4061-9708-283d010af909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385953698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.3385953698
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.480857495
Short name T765
Test name
Test status
Simulation time 28113382 ps
CPU time 1.24 seconds
Started Jul 17 07:18:06 PM PDT 24
Finished Jul 17 07:18:09 PM PDT 24
Peak memory 220052 kb
Host smart-2852db9c-b53a-4a49-838c-8409efd244c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480857495 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.480857495
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.456230951
Short name T554
Test name
Test status
Simulation time 95573422 ps
CPU time 1.16 seconds
Started Jul 17 07:18:13 PM PDT 24
Finished Jul 17 07:18:19 PM PDT 24
Peak memory 217556 kb
Host smart-69377f3d-a15e-4d83-bee8-3d2658085389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456230951 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.456230951
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.3743054624
Short name T678
Test name
Test status
Simulation time 26288854 ps
CPU time 1.19 seconds
Started Jul 17 07:18:08 PM PDT 24
Finished Jul 17 07:18:10 PM PDT 24
Peak memory 218880 kb
Host smart-b5821ae7-46cd-4c0f-9911-bd9316e748ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743054624 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.3743054624
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.1755988515
Short name T679
Test name
Test status
Simulation time 51953455 ps
CPU time 1.64 seconds
Started Jul 17 07:18:05 PM PDT 24
Finished Jul 17 07:18:07 PM PDT 24
Peak memory 218868 kb
Host smart-d2ee5ea0-d669-4f70-836f-dbcda07b66e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755988515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.1755988515
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.2937501660
Short name T618
Test name
Test status
Simulation time 141523482 ps
CPU time 1.09 seconds
Started Jul 17 07:14:55 PM PDT 24
Finished Jul 17 07:14:58 PM PDT 24
Peak memory 217148 kb
Host smart-81d1efb8-3abe-45ca-8ee1-51ff6ccdaa9f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937501660 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.2937501660
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_genbits.2363950002
Short name T621
Test name
Test status
Simulation time 120010231 ps
CPU time 1.98 seconds
Started Jul 17 07:14:53 PM PDT 24
Finished Jul 17 07:14:57 PM PDT 24
Peak memory 219292 kb
Host smart-4d85890a-1777-4fa8-aea0-9486e54e957a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363950002 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2363950002
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.2715206554
Short name T754
Test name
Test status
Simulation time 27541049 ps
CPU time 0.97 seconds
Started Jul 17 07:14:53 PM PDT 24
Finished Jul 17 07:14:55 PM PDT 24
Peak memory 215664 kb
Host smart-f151ec31-48e0-481e-a5f3-6fbe25de32ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715206554 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.2715206554
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.4286385514
Short name T533
Test name
Test status
Simulation time 13766946 ps
CPU time 0.9 seconds
Started Jul 17 07:14:57 PM PDT 24
Finished Jul 17 07:15:04 PM PDT 24
Peak memory 215720 kb
Host smart-f7754c72-5404-40cc-8542-ae2cd333daeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286385514 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.4286385514
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.1753775982
Short name T796
Test name
Test status
Simulation time 587478603 ps
CPU time 5.73 seconds
Started Jul 17 07:14:57 PM PDT 24
Finished Jul 17 07:15:08 PM PDT 24
Peak memory 217808 kb
Host smart-1c3de25d-a1ff-42c8-9c74-192be51e9b9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753775982 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1753775982
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2599182254
Short name T191
Test name
Test status
Simulation time 38022552869 ps
CPU time 968.87 seconds
Started Jul 17 07:14:51 PM PDT 24
Finished Jul 17 07:31:02 PM PDT 24
Peak memory 223920 kb
Host smart-643dac73-b3a4-4637-bc7b-32f95cdfd810
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599182254 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2599182254
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.604893356
Short name T823
Test name
Test status
Simulation time 184027397 ps
CPU time 1.33 seconds
Started Jul 17 07:18:10 PM PDT 24
Finished Jul 17 07:18:13 PM PDT 24
Peak memory 219848 kb
Host smart-2f6b1378-4999-4eae-8c75-e8dc116f3af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604893356 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.604893356
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.3666601339
Short name T435
Test name
Test status
Simulation time 89299543 ps
CPU time 1.13 seconds
Started Jul 17 07:18:10 PM PDT 24
Finished Jul 17 07:18:13 PM PDT 24
Peak memory 220284 kb
Host smart-fb3399df-eeea-4a2a-a81a-b37727b624b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666601339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.3666601339
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.3348819653
Short name T503
Test name
Test status
Simulation time 36989218 ps
CPU time 1.2 seconds
Started Jul 17 07:18:10 PM PDT 24
Finished Jul 17 07:18:14 PM PDT 24
Peak memory 219040 kb
Host smart-0305eac1-53c9-494c-ac91-fe41caa1dcac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348819653 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.3348819653
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.3000972492
Short name T393
Test name
Test status
Simulation time 44303781 ps
CPU time 1.2 seconds
Started Jul 17 07:18:08 PM PDT 24
Finished Jul 17 07:18:11 PM PDT 24
Peak memory 219640 kb
Host smart-5cc3d5ef-dfb8-41b7-9c3e-72ee7dbc331a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000972492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.3000972492
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.816452816
Short name T606
Test name
Test status
Simulation time 62703575 ps
CPU time 1.14 seconds
Started Jul 17 07:18:08 PM PDT 24
Finished Jul 17 07:18:11 PM PDT 24
Peak memory 219132 kb
Host smart-d1a31daf-a07a-4fd3-a6c0-63ad8242ba50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816452816 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.816452816
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.3641611265
Short name T287
Test name
Test status
Simulation time 64773408 ps
CPU time 1.35 seconds
Started Jul 17 07:18:09 PM PDT 24
Finished Jul 17 07:18:12 PM PDT 24
Peak memory 220216 kb
Host smart-983ab47e-efc0-4dd9-9769-9b509cccafca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641611265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.3641611265
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.2783352734
Short name T631
Test name
Test status
Simulation time 86408201 ps
CPU time 1.32 seconds
Started Jul 17 07:18:10 PM PDT 24
Finished Jul 17 07:18:15 PM PDT 24
Peak memory 220060 kb
Host smart-cfe0bdb3-89ce-4e5e-8a99-3d46e3541e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783352734 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.2783352734
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.2246830517
Short name T515
Test name
Test status
Simulation time 74605266 ps
CPU time 1.17 seconds
Started Jul 17 07:18:09 PM PDT 24
Finished Jul 17 07:18:11 PM PDT 24
Peak memory 220200 kb
Host smart-a5529364-ab67-4c24-8457-c0856ad87011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246830517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.2246830517
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.926385034
Short name T168
Test name
Test status
Simulation time 27479139 ps
CPU time 1.23 seconds
Started Jul 17 07:18:11 PM PDT 24
Finished Jul 17 07:18:17 PM PDT 24
Peak memory 221344 kb
Host smart-f0140769-8c9a-4b92-a524-3e9bb9572241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926385034 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.926385034
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.1867686269
Short name T967
Test name
Test status
Simulation time 101809220 ps
CPU time 1.13 seconds
Started Jul 17 07:18:12 PM PDT 24
Finished Jul 17 07:18:18 PM PDT 24
Peak memory 217472 kb
Host smart-e1512aef-a205-4573-90f6-17513ad1cd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867686269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.1867686269
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.3112697572
Short name T922
Test name
Test status
Simulation time 59123273 ps
CPU time 1.11 seconds
Started Jul 17 07:18:10 PM PDT 24
Finished Jul 17 07:18:15 PM PDT 24
Peak memory 220760 kb
Host smart-7d7d8718-a342-49ce-bb01-94b6777b4296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112697572 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.3112697572
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.3490992045
Short name T362
Test name
Test status
Simulation time 46494482 ps
CPU time 1.48 seconds
Started Jul 17 07:18:11 PM PDT 24
Finished Jul 17 07:18:17 PM PDT 24
Peak memory 218736 kb
Host smart-f875cc2f-dce9-4e47-a20d-b05c5a1d6f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490992045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.3490992045
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.3964040998
Short name T682
Test name
Test status
Simulation time 85380707 ps
CPU time 1.2 seconds
Started Jul 17 07:18:13 PM PDT 24
Finished Jul 17 07:18:19 PM PDT 24
Peak memory 220280 kb
Host smart-ea40724d-f656-44f4-809f-851f214febb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964040998 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.3964040998
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.3489417172
Short name T849
Test name
Test status
Simulation time 86653709 ps
CPU time 1.09 seconds
Started Jul 17 07:18:12 PM PDT 24
Finished Jul 17 07:18:18 PM PDT 24
Peak memory 218648 kb
Host smart-1c2df400-98f7-4aeb-81fd-7abb1f6c44f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489417172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.3489417172
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.1978984110
Short name T992
Test name
Test status
Simulation time 24710988 ps
CPU time 1.17 seconds
Started Jul 17 07:18:12 PM PDT 24
Finished Jul 17 07:18:18 PM PDT 24
Peak memory 219096 kb
Host smart-e421276e-a072-460d-b2a9-6c2a0e107de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978984110 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.1978984110
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.1117663927
Short name T938
Test name
Test status
Simulation time 55506148 ps
CPU time 1.91 seconds
Started Jul 17 07:18:11 PM PDT 24
Finished Jul 17 07:18:16 PM PDT 24
Peak memory 220292 kb
Host smart-dbd8c07d-cec6-482a-9466-eee8defef0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117663927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.1117663927
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.4105919939
Short name T394
Test name
Test status
Simulation time 177280276 ps
CPU time 1.19 seconds
Started Jul 17 07:18:12 PM PDT 24
Finished Jul 17 07:18:18 PM PDT 24
Peak memory 219620 kb
Host smart-13736f14-4990-414d-bbee-81c187cc1b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105919939 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.4105919939
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.2055303221
Short name T791
Test name
Test status
Simulation time 52933505 ps
CPU time 1.5 seconds
Started Jul 17 07:18:11 PM PDT 24
Finished Jul 17 07:18:17 PM PDT 24
Peak memory 218904 kb
Host smart-a5226947-fbaa-4c8b-b324-42ee904d6e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055303221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.2055303221
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.2645068947
Short name T226
Test name
Test status
Simulation time 368346991 ps
CPU time 1.23 seconds
Started Jul 17 07:18:11 PM PDT 24
Finished Jul 17 07:18:17 PM PDT 24
Peak memory 221128 kb
Host smart-c37f938a-19d3-4bc7-9a76-333ecd0cce31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645068947 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.2645068947
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.2560167487
Short name T10
Test name
Test status
Simulation time 32870223 ps
CPU time 1.02 seconds
Started Jul 17 07:18:12 PM PDT 24
Finished Jul 17 07:18:18 PM PDT 24
Peak memory 217704 kb
Host smart-8806c1c6-4260-4d8d-8b53-43cead00242a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560167487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.2560167487
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert_test.3185907902
Short name T904
Test name
Test status
Simulation time 141449670 ps
CPU time 0.95 seconds
Started Jul 17 07:14:58 PM PDT 24
Finished Jul 17 07:15:08 PM PDT 24
Peak memory 207128 kb
Host smart-e99745fb-4119-45db-9c38-f233fea27942
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185907902 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3185907902
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.1739325294
Short name T326
Test name
Test status
Simulation time 34752660 ps
CPU time 0.81 seconds
Started Jul 17 07:14:57 PM PDT 24
Finished Jul 17 07:15:05 PM PDT 24
Peak memory 216240 kb
Host smart-795486c7-4014-4377-a2f0-4342d58d6b55
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739325294 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.1739325294
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.819732190
Short name T828
Test name
Test status
Simulation time 275463274 ps
CPU time 1.04 seconds
Started Jul 17 07:14:51 PM PDT 24
Finished Jul 17 07:14:54 PM PDT 24
Peak memory 217188 kb
Host smart-d4688891-3cc3-4b47-a8d9-755531d014a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819732190 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_di
sable_auto_req_mode.819732190
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.4133342081
Short name T438
Test name
Test status
Simulation time 18337474 ps
CPU time 1.04 seconds
Started Jul 17 07:14:58 PM PDT 24
Finished Jul 17 07:15:08 PM PDT 24
Peak memory 218284 kb
Host smart-b71c81dd-e014-4c87-9d56-d7ada5d550fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133342081 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.4133342081
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.2629826819
Short name T840
Test name
Test status
Simulation time 51588572 ps
CPU time 1.66 seconds
Started Jul 17 07:14:54 PM PDT 24
Finished Jul 17 07:14:57 PM PDT 24
Peak memory 217416 kb
Host smart-53bf6ca7-56ad-4f3f-ad87-0cc9dfe25d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629826819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2629826819
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.327911597
Short name T764
Test name
Test status
Simulation time 21140581 ps
CPU time 0.99 seconds
Started Jul 17 07:14:52 PM PDT 24
Finished Jul 17 07:14:55 PM PDT 24
Peak memory 216260 kb
Host smart-0c7931cd-847b-411b-92d6-64aa89c46b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327911597 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.327911597
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.1577929802
Short name T751
Test name
Test status
Simulation time 38995928 ps
CPU time 0.89 seconds
Started Jul 17 07:14:58 PM PDT 24
Finished Jul 17 07:15:09 PM PDT 24
Peak memory 215572 kb
Host smart-5d001aab-11d1-4c76-8930-a2d0410d5cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577929802 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.1577929802
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.1251098452
Short name T832
Test name
Test status
Simulation time 183162753 ps
CPU time 3.65 seconds
Started Jul 17 07:15:02 PM PDT 24
Finished Jul 17 07:15:21 PM PDT 24
Peak memory 218748 kb
Host smart-b2a4ffe6-99d5-4956-b15c-8ef81f30606a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251098452 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.1251098452
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.1345828212
Short name T471
Test name
Test status
Simulation time 355597619690 ps
CPU time 2214.26 seconds
Started Jul 17 07:14:53 PM PDT 24
Finished Jul 17 07:51:49 PM PDT 24
Peak memory 238000 kb
Host smart-bdaf7743-8c42-49b7-99c4-8e3df76e7724
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345828212 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.1345828212
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.1334247449
Short name T200
Test name
Test status
Simulation time 31136124 ps
CPU time 1.36 seconds
Started Jul 17 07:18:14 PM PDT 24
Finished Jul 17 07:18:20 PM PDT 24
Peak memory 215988 kb
Host smart-ae81d1ce-9af6-4e60-9028-6442a40fbc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334247449 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.1334247449
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.3853416887
Short name T916
Test name
Test status
Simulation time 37573909 ps
CPU time 1.35 seconds
Started Jul 17 07:18:10 PM PDT 24
Finished Jul 17 07:18:13 PM PDT 24
Peak memory 217452 kb
Host smart-45193547-5e1e-4ab1-ba6d-58fc69d416c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853416887 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3853416887
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.379040561
Short name T628
Test name
Test status
Simulation time 74771244 ps
CPU time 1.19 seconds
Started Jul 17 07:18:14 PM PDT 24
Finished Jul 17 07:18:20 PM PDT 24
Peak memory 219044 kb
Host smart-c8c0f0b6-6cba-4ebc-b08d-14a36293868f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379040561 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.379040561
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.184837094
Short name T871
Test name
Test status
Simulation time 78170742 ps
CPU time 1.09 seconds
Started Jul 17 07:18:12 PM PDT 24
Finished Jul 17 07:18:18 PM PDT 24
Peak memory 217664 kb
Host smart-4b8d060c-8f23-456a-b935-d6eeef48b987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184837094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.184837094
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.710244077
Short name T879
Test name
Test status
Simulation time 43518682 ps
CPU time 1.16 seconds
Started Jul 17 07:18:10 PM PDT 24
Finished Jul 17 07:18:15 PM PDT 24
Peak memory 220184 kb
Host smart-73f2e184-3f91-4bfe-90a7-abf1a0da1542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710244077 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.710244077
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.3574045678
Short name T747
Test name
Test status
Simulation time 44642589 ps
CPU time 1.06 seconds
Started Jul 17 07:18:13 PM PDT 24
Finished Jul 17 07:18:19 PM PDT 24
Peak memory 217588 kb
Host smart-37308724-53b7-41ce-bc77-22edf55c688f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574045678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.3574045678
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.2248966874
Short name T802
Test name
Test status
Simulation time 32534407 ps
CPU time 1.25 seconds
Started Jul 17 07:18:13 PM PDT 24
Finished Jul 17 07:18:20 PM PDT 24
Peak memory 218844 kb
Host smart-f54863c8-b848-46c2-8a4a-59f288919c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248966874 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.2248966874
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.4294402683
Short name T260
Test name
Test status
Simulation time 39733801 ps
CPU time 1.32 seconds
Started Jul 17 07:18:11 PM PDT 24
Finished Jul 17 07:18:16 PM PDT 24
Peak memory 220204 kb
Host smart-48473ee1-e692-461e-8245-24bb5c330a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294402683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.4294402683
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.1103426595
Short name T822
Test name
Test status
Simulation time 107893806 ps
CPU time 1.06 seconds
Started Jul 17 07:18:14 PM PDT 24
Finished Jul 17 07:18:20 PM PDT 24
Peak memory 218732 kb
Host smart-1d192ef6-d2b6-4f9a-b8af-2fca54ebec6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103426595 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.1103426595
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.2869723708
Short name T509
Test name
Test status
Simulation time 102823269 ps
CPU time 1.14 seconds
Started Jul 17 07:18:12 PM PDT 24
Finished Jul 17 07:18:18 PM PDT 24
Peak memory 217724 kb
Host smart-225b0f83-be17-4865-831f-a6774e8e2d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869723708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2869723708
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.3140648690
Short name T458
Test name
Test status
Simulation time 32266548 ps
CPU time 1.36 seconds
Started Jul 17 07:18:14 PM PDT 24
Finished Jul 17 07:18:20 PM PDT 24
Peak memory 220812 kb
Host smart-3af48d32-a31c-4bd8-a739-254655a7d77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140648690 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.3140648690
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.1016882087
Short name T950
Test name
Test status
Simulation time 268760081 ps
CPU time 2.06 seconds
Started Jul 17 07:18:12 PM PDT 24
Finished Jul 17 07:18:18 PM PDT 24
Peak memory 220136 kb
Host smart-ffa18c6e-c367-4471-8401-6405f6fb964f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016882087 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.1016882087
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.838137451
Short name T274
Test name
Test status
Simulation time 51728129 ps
CPU time 1.27 seconds
Started Jul 17 07:18:14 PM PDT 24
Finished Jul 17 07:18:20 PM PDT 24
Peak memory 220364 kb
Host smart-09fde58e-efe4-48f4-83b5-0e7146bb8a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838137451 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.838137451
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.939505926
Short name T602
Test name
Test status
Simulation time 39414886 ps
CPU time 1.37 seconds
Started Jul 17 07:18:14 PM PDT 24
Finished Jul 17 07:18:20 PM PDT 24
Peak memory 218704 kb
Host smart-7c63de95-d36f-4bcc-8363-d48b50abd6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939505926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.939505926
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.2512127742
Short name T198
Test name
Test status
Simulation time 284127019 ps
CPU time 1.21 seconds
Started Jul 17 07:18:14 PM PDT 24
Finished Jul 17 07:18:20 PM PDT 24
Peak memory 219380 kb
Host smart-ceb1ee40-2221-4fa8-9825-0fb546b674d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512127742 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.2512127742
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.800958895
Short name T411
Test name
Test status
Simulation time 41998305 ps
CPU time 1.59 seconds
Started Jul 17 07:18:11 PM PDT 24
Finished Jul 17 07:18:17 PM PDT 24
Peak memory 218716 kb
Host smart-389c465d-dcd6-4da2-82d3-0cbd8e967337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800958895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.800958895
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.4255445492
Short name T257
Test name
Test status
Simulation time 51230376 ps
CPU time 1.2 seconds
Started Jul 17 07:18:15 PM PDT 24
Finished Jul 17 07:18:21 PM PDT 24
Peak memory 219076 kb
Host smart-d7b23d20-7fea-4b90-9c22-e8d2a720fc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255445492 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.4255445492
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.2369739593
Short name T11
Test name
Test status
Simulation time 55820801 ps
CPU time 1.17 seconds
Started Jul 17 07:18:11 PM PDT 24
Finished Jul 17 07:18:17 PM PDT 24
Peak memory 217744 kb
Host smart-ce68e8b7-225a-48c9-8a39-29155254b225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369739593 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2369739593
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.2656621161
Short name T486
Test name
Test status
Simulation time 147537856 ps
CPU time 1.31 seconds
Started Jul 17 07:14:59 PM PDT 24
Finished Jul 17 07:15:13 PM PDT 24
Peak memory 220132 kb
Host smart-bf5f48aa-15a7-4479-892b-a9928b93f34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656621161 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.2656621161
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.2873911375
Short name T555
Test name
Test status
Simulation time 27725342 ps
CPU time 1.11 seconds
Started Jul 17 07:14:58 PM PDT 24
Finished Jul 17 07:15:10 PM PDT 24
Peak memory 207112 kb
Host smart-16a4481c-841f-41fa-8c09-89dd5b47ebff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873911375 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.2873911375
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.4196491848
Short name T379
Test name
Test status
Simulation time 21470628 ps
CPU time 0.87 seconds
Started Jul 17 07:14:56 PM PDT 24
Finished Jul 17 07:14:59 PM PDT 24
Peak memory 216200 kb
Host smart-24ca76a8-f0af-4939-a1e9-25009e403187
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196491848 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.4196491848
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.2437391471
Short name T108
Test name
Test status
Simulation time 41311844 ps
CPU time 1.31 seconds
Started Jul 17 07:14:57 PM PDT 24
Finished Jul 17 07:15:04 PM PDT 24
Peak memory 217188 kb
Host smart-2f080d74-b623-4e16-9f13-22b15838a0e4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437391471 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.2437391471
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.740140239
Short name T772
Test name
Test status
Simulation time 47575776 ps
CPU time 0.93 seconds
Started Jul 17 07:14:58 PM PDT 24
Finished Jul 17 07:15:09 PM PDT 24
Peak memory 220244 kb
Host smart-57d2ebbc-a712-4449-94d8-d92639ea4bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740140239 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.740140239
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.613009513
Short name T636
Test name
Test status
Simulation time 73998113 ps
CPU time 1.07 seconds
Started Jul 17 07:14:57 PM PDT 24
Finished Jul 17 07:15:05 PM PDT 24
Peak memory 217520 kb
Host smart-b1c3dca9-5868-4c95-a57e-1b9f9b60c3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613009513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.613009513
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.3181162465
Short name T585
Test name
Test status
Simulation time 23542172 ps
CPU time 0.94 seconds
Started Jul 17 07:14:59 PM PDT 24
Finished Jul 17 07:15:11 PM PDT 24
Peak memory 215872 kb
Host smart-7fb52642-6d1b-41c8-beb7-08e432ebbbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181162465 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.3181162465
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.1861363827
Short name T903
Test name
Test status
Simulation time 16361600 ps
CPU time 0.94 seconds
Started Jul 17 07:14:55 PM PDT 24
Finished Jul 17 07:14:57 PM PDT 24
Peak memory 207352 kb
Host smart-b19592af-6db1-4e1a-97f9-5bbb16a20565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861363827 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.1861363827
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.3850515011
Short name T593
Test name
Test status
Simulation time 276026770 ps
CPU time 5.27 seconds
Started Jul 17 07:14:57 PM PDT 24
Finished Jul 17 07:15:06 PM PDT 24
Peak memory 220440 kb
Host smart-5d75be45-8b96-4158-b98a-f6aef3b4d8cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850515011 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3850515011
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.485557969
Short name T719
Test name
Test status
Simulation time 17291915504 ps
CPU time 303.85 seconds
Started Jul 17 07:14:58 PM PDT 24
Finished Jul 17 07:20:09 PM PDT 24
Peak memory 218320 kb
Host smart-5b37fc28-3c60-490d-a5b8-a45fbe661ece
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485557969 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.485557969
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.1036867798
Short name T331
Test name
Test status
Simulation time 64175334 ps
CPU time 1.13 seconds
Started Jul 17 07:18:14 PM PDT 24
Finished Jul 17 07:18:20 PM PDT 24
Peak memory 219244 kb
Host smart-225a55e5-a16e-4df7-bcf1-ec300d5e1b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036867798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1036867798
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.3208579959
Short name T629
Test name
Test status
Simulation time 71167137 ps
CPU time 1.13 seconds
Started Jul 17 07:18:08 PM PDT 24
Finished Jul 17 07:18:11 PM PDT 24
Peak memory 218728 kb
Host smart-cda67f45-b71b-4810-9c25-5b8a4f327756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208579959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.3208579959
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.863261757
Short name T966
Test name
Test status
Simulation time 51518005 ps
CPU time 1.29 seconds
Started Jul 17 07:18:10 PM PDT 24
Finished Jul 17 07:18:15 PM PDT 24
Peak memory 220144 kb
Host smart-c4963247-1549-4c29-ac64-5041ff07a079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863261757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.863261757
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.2409604903
Short name T60
Test name
Test status
Simulation time 34781560 ps
CPU time 1.13 seconds
Started Jul 17 07:18:08 PM PDT 24
Finished Jul 17 07:18:10 PM PDT 24
Peak memory 217452 kb
Host smart-3840c3cc-d1ca-476a-b1b3-879873eff2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409604903 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.2409604903
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.585191434
Short name T956
Test name
Test status
Simulation time 141601174 ps
CPU time 1.13 seconds
Started Jul 17 07:18:09 PM PDT 24
Finished Jul 17 07:18:11 PM PDT 24
Peak memory 218928 kb
Host smart-8f313841-9248-4e3c-9551-0dfc223ed39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585191434 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.585191434
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.1682290661
Short name T625
Test name
Test status
Simulation time 46596559 ps
CPU time 1.66 seconds
Started Jul 17 07:18:09 PM PDT 24
Finished Jul 17 07:18:12 PM PDT 24
Peak memory 218752 kb
Host smart-119e10c3-18e1-43cf-9b02-e789d8a87e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682290661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.1682290661
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.2007405517
Short name T743
Test name
Test status
Simulation time 66600352 ps
CPU time 1.14 seconds
Started Jul 17 07:18:09 PM PDT 24
Finished Jul 17 07:18:12 PM PDT 24
Peak memory 219064 kb
Host smart-b6adb300-eb74-4173-ba61-ff3ad2496fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007405517 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.2007405517
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.1741941630
Short name T537
Test name
Test status
Simulation time 51220230 ps
CPU time 1.38 seconds
Started Jul 17 07:18:08 PM PDT 24
Finished Jul 17 07:18:11 PM PDT 24
Peak memory 217648 kb
Host smart-7fd14ea8-c6b8-4816-9b1a-2ed8b7e987ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741941630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.1741941630
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.3538988128
Short name T626
Test name
Test status
Simulation time 30408521 ps
CPU time 1.26 seconds
Started Jul 17 07:18:10 PM PDT 24
Finished Jul 17 07:18:13 PM PDT 24
Peak memory 219756 kb
Host smart-7e88ba66-989a-4c39-becb-e9d30733b352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538988128 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.3538988128
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.1761179736
Short name T399
Test name
Test status
Simulation time 32456984 ps
CPU time 1.26 seconds
Started Jul 17 07:18:12 PM PDT 24
Finished Jul 17 07:18:18 PM PDT 24
Peak memory 215560 kb
Host smart-fc562fad-41d4-42ba-8172-2bd6086fa8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761179736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.1761179736
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.1000036267
Short name T700
Test name
Test status
Simulation time 45501445 ps
CPU time 1.18 seconds
Started Jul 17 07:18:11 PM PDT 24
Finished Jul 17 07:18:15 PM PDT 24
Peak memory 220268 kb
Host smart-10103276-bce6-41b5-ae09-bb3d8d3f74e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000036267 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.1000036267
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.3180836074
Short name T316
Test name
Test status
Simulation time 50707174 ps
CPU time 1.18 seconds
Started Jul 17 07:18:11 PM PDT 24
Finished Jul 17 07:18:15 PM PDT 24
Peak memory 217724 kb
Host smart-b72f9074-e5bf-40a5-a667-63de0a2f92bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180836074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.3180836074
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.3009359919
Short name T579
Test name
Test status
Simulation time 24894065 ps
CPU time 1.21 seconds
Started Jul 17 07:18:13 PM PDT 24
Finished Jul 17 07:18:19 PM PDT 24
Peak memory 220172 kb
Host smart-06d50923-d0bc-427b-a234-19748cfa69b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009359919 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.3009359919
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.4059727707
Short name T669
Test name
Test status
Simulation time 56488588 ps
CPU time 1.16 seconds
Started Jul 17 07:18:11 PM PDT 24
Finished Jul 17 07:18:16 PM PDT 24
Peak memory 217732 kb
Host smart-b1e44df3-b2c5-40fc-a9e3-d0d9d5417c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059727707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.4059727707
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.2508068631
Short name T906
Test name
Test status
Simulation time 68622785 ps
CPU time 1.15 seconds
Started Jul 17 07:18:12 PM PDT 24
Finished Jul 17 07:18:18 PM PDT 24
Peak memory 220504 kb
Host smart-4124d367-c098-403e-84c9-96824c941a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508068631 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.2508068631
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.355083137
Short name T71
Test name
Test status
Simulation time 57221072 ps
CPU time 1.31 seconds
Started Jul 17 07:18:11 PM PDT 24
Finished Jul 17 07:18:17 PM PDT 24
Peak memory 215572 kb
Host smart-7c55d876-1d8f-4946-b727-11237c3cc58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355083137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.355083137
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.720008258
Short name T612
Test name
Test status
Simulation time 48903950 ps
CPU time 1.25 seconds
Started Jul 17 07:14:59 PM PDT 24
Finished Jul 17 07:15:13 PM PDT 24
Peak memory 220232 kb
Host smart-91e17858-1f53-4f58-b5ac-c6e739649410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720008258 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.720008258
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.2721255396
Short name T639
Test name
Test status
Simulation time 19460067 ps
CPU time 0.83 seconds
Started Jul 17 07:15:00 PM PDT 24
Finished Jul 17 07:15:13 PM PDT 24
Peak memory 215024 kb
Host smart-36e8e686-38b2-4341-bea0-5d746e97af8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721255396 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.2721255396
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.2646539351
Short name T140
Test name
Test status
Simulation time 21267150 ps
CPU time 0.91 seconds
Started Jul 17 07:15:00 PM PDT 24
Finished Jul 17 07:15:15 PM PDT 24
Peak memory 215656 kb
Host smart-fe687677-abaa-4986-bc28-c51faedae6bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646539351 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.2646539351
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.176194305
Short name T987
Test name
Test status
Simulation time 55246666 ps
CPU time 0.93 seconds
Started Jul 17 07:15:00 PM PDT 24
Finished Jul 17 07:15:13 PM PDT 24
Peak memory 219932 kb
Host smart-b3d4023d-a305-466c-9993-d2b648acee90
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176194305 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_di
sable_auto_req_mode.176194305
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.453690453
Short name T87
Test name
Test status
Simulation time 23740774 ps
CPU time 1.14 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:15:16 PM PDT 24
Peak memory 220960 kb
Host smart-75cb8e7b-6e13-4511-8e79-bc8b2ae98883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453690453 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.453690453
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.2264288105
Short name T844
Test name
Test status
Simulation time 71828528 ps
CPU time 2.59 seconds
Started Jul 17 07:14:59 PM PDT 24
Finished Jul 17 07:15:15 PM PDT 24
Peak memory 219660 kb
Host smart-bddd7248-0b95-47ed-8958-1cd97d0f5ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264288105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.2264288105
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.2556709137
Short name T51
Test name
Test status
Simulation time 33209074 ps
CPU time 0.98 seconds
Started Jul 17 07:15:00 PM PDT 24
Finished Jul 17 07:15:13 PM PDT 24
Peak memory 224316 kb
Host smart-c3d2e26d-6118-4c87-b78f-73aad2a4b030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556709137 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.2556709137
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.2810334075
Short name T924
Test name
Test status
Simulation time 31809872 ps
CPU time 0.96 seconds
Started Jul 17 07:14:58 PM PDT 24
Finished Jul 17 07:15:08 PM PDT 24
Peak memory 215572 kb
Host smart-7969b4aa-4cec-46b6-918a-611f57f02a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810334075 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2810334075
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.1693245019
Short name T697
Test name
Test status
Simulation time 45883602 ps
CPU time 1.02 seconds
Started Jul 17 07:14:59 PM PDT 24
Finished Jul 17 07:15:12 PM PDT 24
Peak memory 215552 kb
Host smart-70270da1-af08-4d02-b7dd-987f2086aaec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693245019 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1693245019
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.639870228
Short name T965
Test name
Test status
Simulation time 198411771202 ps
CPU time 1334.03 seconds
Started Jul 17 07:14:59 PM PDT 24
Finished Jul 17 07:37:26 PM PDT 24
Peak memory 226208 kb
Host smart-b561448e-f5d4-4566-9924-5d4b0e7bee30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639870228 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.639870228
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.3174663387
Short name T872
Test name
Test status
Simulation time 37265344 ps
CPU time 1.32 seconds
Started Jul 17 07:18:13 PM PDT 24
Finished Jul 17 07:18:19 PM PDT 24
Peak memory 217408 kb
Host smart-7e8d37eb-93af-453e-b30c-c4434f7dc2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174663387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.3174663387
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.1575715893
Short name T762
Test name
Test status
Simulation time 150656140 ps
CPU time 1.1 seconds
Started Jul 17 07:18:11 PM PDT 24
Finished Jul 17 07:18:17 PM PDT 24
Peak memory 220092 kb
Host smart-767ad204-558c-4da1-8fdf-b2b513423ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575715893 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.1575715893
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.1686580023
Short name T855
Test name
Test status
Simulation time 107034858 ps
CPU time 1.33 seconds
Started Jul 17 07:18:11 PM PDT 24
Finished Jul 17 07:18:15 PM PDT 24
Peak memory 220304 kb
Host smart-7f0dee01-caba-459c-9fe7-f9cb1ceb1b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686580023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1686580023
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.625347263
Short name T643
Test name
Test status
Simulation time 98187963 ps
CPU time 1.15 seconds
Started Jul 17 07:18:13 PM PDT 24
Finished Jul 17 07:18:19 PM PDT 24
Peak memory 220048 kb
Host smart-105be079-ce60-4f97-94d2-3fae9b0e92ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625347263 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.625347263
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.2253912157
Short name T398
Test name
Test status
Simulation time 49411520 ps
CPU time 0.99 seconds
Started Jul 17 07:18:11 PM PDT 24
Finished Jul 17 07:18:16 PM PDT 24
Peak memory 217680 kb
Host smart-f924ba5f-0878-4a25-a370-80abbddf0c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253912157 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.2253912157
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.3527035833
Short name T276
Test name
Test status
Simulation time 63665269 ps
CPU time 1.08 seconds
Started Jul 17 07:18:11 PM PDT 24
Finished Jul 17 07:18:15 PM PDT 24
Peak memory 219876 kb
Host smart-8fb7cb2e-758d-454a-8b23-9e48e748ce73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527035833 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.3527035833
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.118132194
Short name T350
Test name
Test status
Simulation time 124028921 ps
CPU time 1.06 seconds
Started Jul 17 07:18:11 PM PDT 24
Finished Jul 17 07:18:16 PM PDT 24
Peak memory 217804 kb
Host smart-45adb677-8dd4-4713-b569-1fe457a72cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118132194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.118132194
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.3160775196
Short name T495
Test name
Test status
Simulation time 24687444 ps
CPU time 1.2 seconds
Started Jul 17 07:18:10 PM PDT 24
Finished Jul 17 07:18:14 PM PDT 24
Peak memory 219120 kb
Host smart-284d6fa6-39ba-40db-a2b8-836fc09577ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160775196 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.3160775196
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.4014081035
Short name T388
Test name
Test status
Simulation time 88956394 ps
CPU time 1.23 seconds
Started Jul 17 07:18:11 PM PDT 24
Finished Jul 17 07:18:16 PM PDT 24
Peak memory 215560 kb
Host smart-08bff46e-6bd0-4a5d-9431-f16fbe86d0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014081035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.4014081035
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.3070972483
Short name T846
Test name
Test status
Simulation time 77080170 ps
CPU time 1.09 seconds
Started Jul 17 07:18:13 PM PDT 24
Finished Jul 17 07:18:18 PM PDT 24
Peak memory 219132 kb
Host smart-97eb247b-4f78-4f22-98ab-c5f26487116c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070972483 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.3070972483
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.1896190567
Short name T548
Test name
Test status
Simulation time 55675408 ps
CPU time 1.14 seconds
Started Jul 17 07:18:13 PM PDT 24
Finished Jul 17 07:18:19 PM PDT 24
Peak memory 217564 kb
Host smart-4553c8d1-f6f2-4e27-9686-b9a02869826a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896190567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.1896190567
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.2774586502
Short name T278
Test name
Test status
Simulation time 216618903 ps
CPU time 1.24 seconds
Started Jul 17 07:18:12 PM PDT 24
Finished Jul 17 07:18:18 PM PDT 24
Peak memory 218676 kb
Host smart-92280be1-0deb-49b3-971f-24ab2b8bc013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774586502 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.2774586502
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.3351403045
Short name T806
Test name
Test status
Simulation time 46410325 ps
CPU time 1.11 seconds
Started Jul 17 07:18:12 PM PDT 24
Finished Jul 17 07:18:18 PM PDT 24
Peak memory 217548 kb
Host smart-5e6a653f-973d-4fc5-b23f-9725f2b127ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351403045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.3351403045
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.3029849184
Short name T130
Test name
Test status
Simulation time 48137773 ps
CPU time 1.18 seconds
Started Jul 17 07:18:13 PM PDT 24
Finished Jul 17 07:18:19 PM PDT 24
Peak memory 219008 kb
Host smart-0a015eb5-30a0-48f0-b7e8-7caf07ea2e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029849184 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.3029849184
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.1693814471
Short name T816
Test name
Test status
Simulation time 160700820 ps
CPU time 1.23 seconds
Started Jul 17 07:18:12 PM PDT 24
Finished Jul 17 07:18:18 PM PDT 24
Peak memory 217464 kb
Host smart-60649645-4c6f-4206-86eb-a35376f0a680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693814471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.1693814471
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.2418809116
Short name T734
Test name
Test status
Simulation time 343625312 ps
CPU time 1.33 seconds
Started Jul 17 07:18:12 PM PDT 24
Finished Jul 17 07:18:18 PM PDT 24
Peak memory 218844 kb
Host smart-9b5758c6-f976-4b83-93f0-23f6efd47e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418809116 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.2418809116
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.3946625560
Short name T536
Test name
Test status
Simulation time 38392957 ps
CPU time 1.5 seconds
Started Jul 17 07:18:11 PM PDT 24
Finished Jul 17 07:18:17 PM PDT 24
Peak memory 217768 kb
Host smart-c3622191-a3cd-40f2-9b84-af5bbeccfd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946625560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.3946625560
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.151687594
Short name T201
Test name
Test status
Simulation time 96482585 ps
CPU time 1.09 seconds
Started Jul 17 07:18:14 PM PDT 24
Finished Jul 17 07:18:20 PM PDT 24
Peak memory 219596 kb
Host smart-3c0c7088-3e93-4f9e-9cff-4efebe185fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151687594 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.151687594
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.3151234139
Short name T439
Test name
Test status
Simulation time 114865350 ps
CPU time 1.11 seconds
Started Jul 17 07:18:11 PM PDT 24
Finished Jul 17 07:18:16 PM PDT 24
Peak memory 217472 kb
Host smart-86e1eba1-6984-4616-adf6-b7c0f8ce0eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151234139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.3151234139
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.3508411774
Short name T115
Test name
Test status
Simulation time 154106578 ps
CPU time 1.16 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:15:17 PM PDT 24
Peak memory 219084 kb
Host smart-bef22360-b647-4e9f-95ab-3e365dc44bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508411774 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3508411774
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.66016334
Short name T404
Test name
Test status
Simulation time 36701171 ps
CPU time 0.96 seconds
Started Jul 17 07:15:02 PM PDT 24
Finished Jul 17 07:15:17 PM PDT 24
Peak memory 215308 kb
Host smart-a0cba860-59a4-4897-8eb7-bbf03e09a5d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66016334 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.66016334
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.2505548456
Short name T68
Test name
Test status
Simulation time 12755363 ps
CPU time 0.86 seconds
Started Jul 17 07:15:04 PM PDT 24
Finished Jul 17 07:15:21 PM PDT 24
Peak memory 216020 kb
Host smart-c252cb89-70bd-43dc-b372-8bdb252237c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505548456 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.2505548456
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.418892494
Short name T985
Test name
Test status
Simulation time 35916903 ps
CPU time 1.06 seconds
Started Jul 17 07:15:04 PM PDT 24
Finished Jul 17 07:15:21 PM PDT 24
Peak memory 220152 kb
Host smart-b0c61631-00db-4424-ad19-5958b02e3ef6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418892494 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_di
sable_auto_req_mode.418892494
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.1274773620
Short name T186
Test name
Test status
Simulation time 27230006 ps
CPU time 0.93 seconds
Started Jul 17 07:15:03 PM PDT 24
Finished Jul 17 07:15:19 PM PDT 24
Peak memory 220208 kb
Host smart-5e054697-84aa-4f61-9c29-1acc95df8ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274773620 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.1274773620
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_intr.2082006364
Short name T600
Test name
Test status
Simulation time 22613109 ps
CPU time 0.91 seconds
Started Jul 17 07:15:00 PM PDT 24
Finished Jul 17 07:15:15 PM PDT 24
Peak memory 216168 kb
Host smart-ff9cd0c1-4fd7-40ee-830a-cc173b2bb8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082006364 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2082006364
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.19644858
Short name T315
Test name
Test status
Simulation time 50198365 ps
CPU time 0.95 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:15:17 PM PDT 24
Peak memory 215552 kb
Host smart-a1693007-773a-42ad-a6c2-8d7816698821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19644858 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.19644858
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.3201424022
Short name T418
Test name
Test status
Simulation time 124865821 ps
CPU time 1.79 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:15:18 PM PDT 24
Peak memory 215464 kb
Host smart-c0d0a73b-97d7-4ad8-87a6-571463f4ec4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201424022 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.3201424022
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2947182906
Short name T484
Test name
Test status
Simulation time 127237920376 ps
CPU time 1872.64 seconds
Started Jul 17 07:15:00 PM PDT 24
Finished Jul 17 07:46:25 PM PDT 24
Peak memory 229384 kb
Host smart-7527730f-d321-41f5-a855-2ee42eee29b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947182906 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.2947182906
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.3845418634
Short name T224
Test name
Test status
Simulation time 27115466 ps
CPU time 1.18 seconds
Started Jul 17 07:18:15 PM PDT 24
Finished Jul 17 07:18:20 PM PDT 24
Peak memory 218712 kb
Host smart-2ea5edf8-f906-443a-bbce-df8c1372ad89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845418634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3845418634
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.2831963728
Short name T250
Test name
Test status
Simulation time 205558898 ps
CPU time 1.04 seconds
Started Jul 17 07:18:15 PM PDT 24
Finished Jul 17 07:18:20 PM PDT 24
Peak memory 220912 kb
Host smart-d215925a-e92d-4363-a1c9-6354671a6575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831963728 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.2831963728
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.2323214521
Short name T837
Test name
Test status
Simulation time 89572507 ps
CPU time 1.17 seconds
Started Jul 17 07:18:13 PM PDT 24
Finished Jul 17 07:18:19 PM PDT 24
Peak memory 220340 kb
Host smart-adcb8957-e9d6-4396-925a-d531664d5f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323214521 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.2323214521
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.3006130057
Short name T773
Test name
Test status
Simulation time 22214440 ps
CPU time 1.13 seconds
Started Jul 17 07:18:14 PM PDT 24
Finished Jul 17 07:18:20 PM PDT 24
Peak memory 218876 kb
Host smart-3f77a051-1033-439f-afe8-63e5275a2c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006130057 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.3006130057
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.860513367
Short name T646
Test name
Test status
Simulation time 36737478 ps
CPU time 1.3 seconds
Started Jul 17 07:18:14 PM PDT 24
Finished Jul 17 07:18:20 PM PDT 24
Peak memory 220016 kb
Host smart-4065a5b4-3418-4770-8282-e391b38b25c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860513367 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.860513367
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.231613145
Short name T156
Test name
Test status
Simulation time 97401508 ps
CPU time 1.2 seconds
Started Jul 17 07:18:10 PM PDT 24
Finished Jul 17 07:18:15 PM PDT 24
Peak memory 221292 kb
Host smart-ef296ad2-032e-46a1-a045-8e1038011984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231613145 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.231613145
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.2007679679
Short name T730
Test name
Test status
Simulation time 60880022 ps
CPU time 1.06 seconds
Started Jul 17 07:18:14 PM PDT 24
Finished Jul 17 07:18:20 PM PDT 24
Peak memory 218760 kb
Host smart-022662fe-9873-4f73-97fa-6fc046205eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007679679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.2007679679
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.1496079338
Short name T91
Test name
Test status
Simulation time 61161789 ps
CPU time 1.03 seconds
Started Jul 17 07:18:04 PM PDT 24
Finished Jul 17 07:18:06 PM PDT 24
Peak memory 219820 kb
Host smart-174ce943-939e-4217-a5b3-0f4e67a8b96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496079338 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.1496079338
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.1683450
Short name T610
Test name
Test status
Simulation time 34668511 ps
CPU time 1.61 seconds
Started Jul 17 07:18:15 PM PDT 24
Finished Jul 17 07:18:21 PM PDT 24
Peak memory 219124 kb
Host smart-819ff9f3-af31-4fab-b617-08781d91c44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1683450
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.3230789645
Short name T90
Test name
Test status
Simulation time 106248777 ps
CPU time 1.12 seconds
Started Jul 17 07:17:51 PM PDT 24
Finished Jul 17 07:17:53 PM PDT 24
Peak memory 218764 kb
Host smart-bf11b77a-8fb1-4eca-b7cd-01e438cb6487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230789645 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.3230789645
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.3520229516
Short name T767
Test name
Test status
Simulation time 49443758 ps
CPU time 1.36 seconds
Started Jul 17 07:18:10 PM PDT 24
Finished Jul 17 07:18:14 PM PDT 24
Peak memory 218712 kb
Host smart-a190dcb6-7892-4c33-b32d-ac440155509b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520229516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3520229516
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.3727272558
Short name T206
Test name
Test status
Simulation time 74042775 ps
CPU time 1.15 seconds
Started Jul 17 07:18:10 PM PDT 24
Finished Jul 17 07:18:13 PM PDT 24
Peak memory 220232 kb
Host smart-e82650d8-bafd-461f-9da5-1859cd9678d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727272558 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.3727272558
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.3317658157
Short name T841
Test name
Test status
Simulation time 172815789 ps
CPU time 1.51 seconds
Started Jul 17 07:18:10 PM PDT 24
Finished Jul 17 07:18:15 PM PDT 24
Peak memory 219476 kb
Host smart-323b88e9-ed26-4861-9d93-c38a8e5250ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317658157 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3317658157
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.815029128
Short name T737
Test name
Test status
Simulation time 44463469 ps
CPU time 1.14 seconds
Started Jul 17 07:18:11 PM PDT 24
Finished Jul 17 07:18:16 PM PDT 24
Peak memory 218892 kb
Host smart-c72e61d0-ca75-45e4-9f26-d3def5037f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815029128 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.815029128
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.589572475
Short name T534
Test name
Test status
Simulation time 35350981 ps
CPU time 1.4 seconds
Started Jul 17 07:18:09 PM PDT 24
Finished Jul 17 07:18:12 PM PDT 24
Peak memory 220284 kb
Host smart-a0ada8ee-267e-4c57-8cc8-69aad8680bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589572475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.589572475
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.3901604451
Short name T357
Test name
Test status
Simulation time 76187685 ps
CPU time 1.13 seconds
Started Jul 17 07:18:13 PM PDT 24
Finished Jul 17 07:18:19 PM PDT 24
Peak memory 220316 kb
Host smart-6bead027-d75d-4e4e-a243-edd8dde7567c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901604451 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.3901604451
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.656227739
Short name T915
Test name
Test status
Simulation time 78670479 ps
CPU time 1.41 seconds
Started Jul 17 07:18:10 PM PDT 24
Finished Jul 17 07:18:15 PM PDT 24
Peak memory 219004 kb
Host smart-2d86c37f-eca6-4b26-a77d-52e77bb8c26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656227739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.656227739
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.3846005122
Short name T468
Test name
Test status
Simulation time 27373606 ps
CPU time 1.3 seconds
Started Jul 17 07:18:46 PM PDT 24
Finished Jul 17 07:18:49 PM PDT 24
Peak memory 219052 kb
Host smart-e3836159-ab0d-4157-9ec9-4ef1eb66b81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846005122 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.3846005122
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.2274888582
Short name T420
Test name
Test status
Simulation time 27904148 ps
CPU time 1.24 seconds
Started Jul 17 07:18:53 PM PDT 24
Finished Jul 17 07:18:58 PM PDT 24
Peak memory 218772 kb
Host smart-55261159-5a4a-4830-a3f8-2287bdb0e7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274888582 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.2274888582
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.848263000
Short name T937
Test name
Test status
Simulation time 71446531 ps
CPU time 1.19 seconds
Started Jul 17 07:15:04 PM PDT 24
Finished Jul 17 07:15:21 PM PDT 24
Peak memory 218800 kb
Host smart-9ca748d5-2248-47d3-80f8-17bbbf63649f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848263000 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.848263000
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.2632525847
Short name T752
Test name
Test status
Simulation time 86732226 ps
CPU time 0.78 seconds
Started Jul 17 07:15:03 PM PDT 24
Finished Jul 17 07:15:20 PM PDT 24
Peak memory 207092 kb
Host smart-f996be2a-61a9-4b39-9498-d9c61f5b0d49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632525847 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.2632525847
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.1231011252
Short name T365
Test name
Test status
Simulation time 31244809 ps
CPU time 0.81 seconds
Started Jul 17 07:14:56 PM PDT 24
Finished Jul 17 07:14:58 PM PDT 24
Peak memory 216656 kb
Host smart-80bc7744-c064-4a23-bd03-bec7e372d844
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231011252 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.1231011252
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_err.155789805
Short name T139
Test name
Test status
Simulation time 24710720 ps
CPU time 1.01 seconds
Started Jul 17 07:15:05 PM PDT 24
Finished Jul 17 07:15:23 PM PDT 24
Peak memory 224328 kb
Host smart-54359c50-081d-4684-b01a-5379db2624f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155789805 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.155789805
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_intr.358279217
Short name T348
Test name
Test status
Simulation time 45856537 ps
CPU time 0.84 seconds
Started Jul 17 07:15:05 PM PDT 24
Finished Jul 17 07:15:23 PM PDT 24
Peak memory 215692 kb
Host smart-54465a47-d164-45c1-a8ec-da97fb14c0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358279217 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.358279217
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.2011712718
Short name T818
Test name
Test status
Simulation time 17111534 ps
CPU time 0.98 seconds
Started Jul 17 07:15:06 PM PDT 24
Finished Jul 17 07:15:23 PM PDT 24
Peak memory 215472 kb
Host smart-afd80618-4880-4e51-a740-a54c7dcd1031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011712718 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.2011712718
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.1367687597
Short name T925
Test name
Test status
Simulation time 552322474 ps
CPU time 4.24 seconds
Started Jul 17 07:15:05 PM PDT 24
Finished Jul 17 07:15:27 PM PDT 24
Peak memory 215628 kb
Host smart-a223f972-1353-41ff-afa8-e586442f47f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367687597 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.1367687597
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/160.edn_alert.924794973
Short name T902
Test name
Test status
Simulation time 88882363 ps
CPU time 1.19 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:17 PM PDT 24
Peak memory 219856 kb
Host smart-97ab9d43-faaa-4f34-ad9a-72f63213ff17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924794973 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.924794973
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.2911389459
Short name T389
Test name
Test status
Simulation time 62480358 ps
CPU time 1.04 seconds
Started Jul 17 07:18:55 PM PDT 24
Finished Jul 17 07:19:08 PM PDT 24
Peak memory 217504 kb
Host smart-e5f201e9-f1ea-4331-bf7a-0a3f2582d781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911389459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.2911389459
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.2821672365
Short name T147
Test name
Test status
Simulation time 48049718 ps
CPU time 1.14 seconds
Started Jul 17 07:18:54 PM PDT 24
Finished Jul 17 07:19:02 PM PDT 24
Peak memory 220168 kb
Host smart-5daddb04-9b67-4955-aa21-561e76fd5863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821672365 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.2821672365
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/162.edn_alert.1283906402
Short name T723
Test name
Test status
Simulation time 41174540 ps
CPU time 1.1 seconds
Started Jul 17 07:18:58 PM PDT 24
Finished Jul 17 07:19:19 PM PDT 24
Peak memory 218792 kb
Host smart-33a78f6c-7457-47ab-9f63-2388b1e01131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283906402 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.1283906402
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.1771943115
Short name T804
Test name
Test status
Simulation time 52475698 ps
CPU time 1.76 seconds
Started Jul 17 07:18:55 PM PDT 24
Finished Jul 17 07:19:05 PM PDT 24
Peak memory 218792 kb
Host smart-9e27d86d-9ff1-4feb-bf22-1b5b19f83e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771943115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.1771943115
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.622151797
Short name T104
Test name
Test status
Simulation time 22930193 ps
CPU time 1.19 seconds
Started Jul 17 07:18:55 PM PDT 24
Finished Jul 17 07:19:06 PM PDT 24
Peak memory 218940 kb
Host smart-5716ad7b-bd08-4ea5-9558-09516b97bce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622151797 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.622151797
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.2432414312
Short name T969
Test name
Test status
Simulation time 42309620 ps
CPU time 1.39 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:11 PM PDT 24
Peak memory 217612 kb
Host smart-2205c153-e6d5-45c9-b6ee-7bdbd83a7584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432414312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.2432414312
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.2916658308
Short name T616
Test name
Test status
Simulation time 48904378 ps
CPU time 1.07 seconds
Started Jul 17 07:18:58 PM PDT 24
Finished Jul 17 07:19:19 PM PDT 24
Peak memory 219108 kb
Host smart-be231bed-f477-4132-86c0-265e12454049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916658308 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.2916658308
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.2809063580
Short name T308
Test name
Test status
Simulation time 123875010 ps
CPU time 2.63 seconds
Started Jul 17 07:18:55 PM PDT 24
Finished Jul 17 07:19:10 PM PDT 24
Peak memory 219024 kb
Host smart-fd80ac7f-f801-4852-96d5-182c337adfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809063580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2809063580
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.3889971629
Short name T463
Test name
Test status
Simulation time 118463859 ps
CPU time 1.16 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:18 PM PDT 24
Peak memory 221368 kb
Host smart-7bf733d5-80f7-43b8-a2df-84e6ab852b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889971629 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.3889971629
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.4100146363
Short name T690
Test name
Test status
Simulation time 79307715 ps
CPU time 1.89 seconds
Started Jul 17 07:18:55 PM PDT 24
Finished Jul 17 07:19:07 PM PDT 24
Peak memory 220472 kb
Host smart-20b9c6ea-a5c7-4a77-8c16-f33829bf069d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100146363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.4100146363
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.500502616
Short name T507
Test name
Test status
Simulation time 30252975 ps
CPU time 1.12 seconds
Started Jul 17 07:19:00 PM PDT 24
Finished Jul 17 07:19:22 PM PDT 24
Peak memory 219452 kb
Host smart-56b30afc-0ea2-4c69-8405-a81f228f9279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500502616 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.500502616
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.2498286814
Short name T648
Test name
Test status
Simulation time 73902450 ps
CPU time 1.09 seconds
Started Jul 17 07:18:46 PM PDT 24
Finished Jul 17 07:18:48 PM PDT 24
Peak memory 220168 kb
Host smart-1014361f-c004-4944-b73f-bda1daafaef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498286814 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.2498286814
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.1371014393
Short name T931
Test name
Test status
Simulation time 88605219 ps
CPU time 1.22 seconds
Started Jul 17 07:18:58 PM PDT 24
Finished Jul 17 07:19:19 PM PDT 24
Peak memory 219660 kb
Host smart-761fb7dc-a9dd-413f-b6ad-8e7c9ca42967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371014393 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.1371014393
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.1260273599
Short name T309
Test name
Test status
Simulation time 86869487 ps
CPU time 1.15 seconds
Started Jul 17 07:18:54 PM PDT 24
Finished Jul 17 07:19:04 PM PDT 24
Peak memory 218856 kb
Host smart-f95975f9-6e44-41b3-94fd-937ad049171f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260273599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1260273599
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.2772067694
Short name T539
Test name
Test status
Simulation time 74974266 ps
CPU time 1.08 seconds
Started Jul 17 07:18:59 PM PDT 24
Finished Jul 17 07:19:20 PM PDT 24
Peak memory 219848 kb
Host smart-019bcd1f-e1f9-4462-9030-97312e404132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772067694 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.2772067694
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.1942804379
Short name T293
Test name
Test status
Simulation time 77641159 ps
CPU time 1.68 seconds
Started Jul 17 07:18:47 PM PDT 24
Finished Jul 17 07:18:50 PM PDT 24
Peak memory 219584 kb
Host smart-d7b5ad85-c9da-4362-a1e6-6d74fc88b718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942804379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1942804379
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.1229370477
Short name T511
Test name
Test status
Simulation time 326593976 ps
CPU time 1.08 seconds
Started Jul 17 07:18:51 PM PDT 24
Finished Jul 17 07:18:55 PM PDT 24
Peak memory 219100 kb
Host smart-0d7f3d5e-6b5d-4c82-b504-9489f6cbcbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229370477 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.1229370477
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.4132568389
Short name T831
Test name
Test status
Simulation time 75583397 ps
CPU time 1.35 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:14 PM PDT 24
Peak memory 219132 kb
Host smart-86f56522-2f72-4c4c-ba4e-a4ad26049b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132568389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.4132568389
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.4140638094
Short name T568
Test name
Test status
Simulation time 93890429 ps
CPU time 1.19 seconds
Started Jul 17 07:14:56 PM PDT 24
Finished Jul 17 07:15:00 PM PDT 24
Peak memory 215900 kb
Host smart-d675838f-648f-4740-850c-17f8283240b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140638094 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.4140638094
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.34539767
Short name T23
Test name
Test status
Simulation time 37517841 ps
CPU time 0.83 seconds
Started Jul 17 07:14:58 PM PDT 24
Finished Jul 17 07:15:09 PM PDT 24
Peak memory 207124 kb
Host smart-eb6423cf-a46e-49af-9c33-d5c10ab9b37c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34539767 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.34539767
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.3884967567
Short name T134
Test name
Test status
Simulation time 25023180 ps
CPU time 1.07 seconds
Started Jul 17 07:14:57 PM PDT 24
Finished Jul 17 07:15:04 PM PDT 24
Peak memory 217076 kb
Host smart-61185e77-06b0-4c45-b5b9-dc40956abfc3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884967567 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.3884967567
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.1806016756
Short name T455
Test name
Test status
Simulation time 44971229 ps
CPU time 1.07 seconds
Started Jul 17 07:14:57 PM PDT 24
Finished Jul 17 07:15:04 PM PDT 24
Peak memory 219836 kb
Host smart-06274874-63e2-478e-b735-9f99d039b68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806016756 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.1806016756
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.1888749668
Short name T990
Test name
Test status
Simulation time 88131220 ps
CPU time 1.12 seconds
Started Jul 17 07:14:56 PM PDT 24
Finished Jul 17 07:14:59 PM PDT 24
Peak memory 217492 kb
Host smart-676eae11-7adf-4556-99a1-ec01fe5312d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888749668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1888749668
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.1297147329
Short name T939
Test name
Test status
Simulation time 50480467 ps
CPU time 0.87 seconds
Started Jul 17 07:14:52 PM PDT 24
Finished Jul 17 07:14:55 PM PDT 24
Peak memory 215560 kb
Host smart-4e1806c6-6807-4f01-98e9-0090a2dd0e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297147329 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1297147329
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.3502883321
Short name T359
Test name
Test status
Simulation time 16817926 ps
CPU time 0.96 seconds
Started Jul 17 07:15:04 PM PDT 24
Finished Jul 17 07:15:21 PM PDT 24
Peak memory 215568 kb
Host smart-ee5525d3-a037-477f-9bbd-8dc0aa6187b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502883321 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.3502883321
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.2980532214
Short name T798
Test name
Test status
Simulation time 376948509 ps
CPU time 5.46 seconds
Started Jul 17 07:14:58 PM PDT 24
Finished Jul 17 07:15:12 PM PDT 24
Peak memory 215548 kb
Host smart-59279ed9-c486-49a3-9328-767f944fa2f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980532214 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.2980532214
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.2870099754
Short name T216
Test name
Test status
Simulation time 156815979234 ps
CPU time 901.3 seconds
Started Jul 17 07:14:58 PM PDT 24
Finished Jul 17 07:30:10 PM PDT 24
Peak memory 221000 kb
Host smart-fceea70d-5fa0-43f1-b5e5-af3bf69ed5e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870099754 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.2870099754
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.1810951344
Short name T681
Test name
Test status
Simulation time 30801317 ps
CPU time 1.23 seconds
Started Jul 17 07:18:55 PM PDT 24
Finished Jul 17 07:19:05 PM PDT 24
Peak memory 219080 kb
Host smart-216bd35f-4421-4208-91e3-b4859e110366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810951344 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.1810951344
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.4284296700
Short name T518
Test name
Test status
Simulation time 94082755 ps
CPU time 1.23 seconds
Started Jul 17 07:18:55 PM PDT 24
Finished Jul 17 07:19:05 PM PDT 24
Peak memory 218604 kb
Host smart-46aaa319-c9dd-4387-b14c-1b3a13d1e345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284296700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.4284296700
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.2076885785
Short name T744
Test name
Test status
Simulation time 56918174 ps
CPU time 1.09 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:18 PM PDT 24
Peak memory 220020 kb
Host smart-2cc19042-4d91-455b-9cb2-97fd337bbd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076885785 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.2076885785
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/172.edn_alert.1094920853
Short name T634
Test name
Test status
Simulation time 94175414 ps
CPU time 1.18 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:11 PM PDT 24
Peak memory 218672 kb
Host smart-55454e9d-f3f9-467f-bcd0-e65a618848dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094920853 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.1094920853
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.1947333402
Short name T699
Test name
Test status
Simulation time 92956007 ps
CPU time 1.36 seconds
Started Jul 17 07:18:54 PM PDT 24
Finished Jul 17 07:19:02 PM PDT 24
Peak memory 220252 kb
Host smart-fffb542f-0ba9-446b-9925-a829b1ed50f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947333402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.1947333402
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.1513491286
Short name T197
Test name
Test status
Simulation time 163743331 ps
CPU time 1.28 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:10 PM PDT 24
Peak memory 219720 kb
Host smart-101d0048-cf9f-4b06-9d42-9546c6a73ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513491286 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.1513491286
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.1787058428
Short name T499
Test name
Test status
Simulation time 270728893 ps
CPU time 1.82 seconds
Started Jul 17 07:18:55 PM PDT 24
Finished Jul 17 07:19:07 PM PDT 24
Peak memory 219052 kb
Host smart-ca1b2844-eea7-4062-b24c-adb7dd0572a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787058428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.1787058428
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.1133551326
Short name T329
Test name
Test status
Simulation time 88855773 ps
CPU time 0.99 seconds
Started Jul 17 07:18:53 PM PDT 24
Finished Jul 17 07:18:58 PM PDT 24
Peak memory 217748 kb
Host smart-7cd3f699-0d70-47d8-b716-631e9b80b016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133551326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.1133551326
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.3839025945
Short name T856
Test name
Test status
Simulation time 133478474 ps
CPU time 1.24 seconds
Started Jul 17 07:18:54 PM PDT 24
Finished Jul 17 07:19:04 PM PDT 24
Peak memory 221860 kb
Host smart-56b1ad9d-9977-44f6-9be2-07baed443b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839025945 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.3839025945
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.1035690366
Short name T258
Test name
Test status
Simulation time 33249207 ps
CPU time 1.45 seconds
Started Jul 17 07:18:55 PM PDT 24
Finished Jul 17 07:19:05 PM PDT 24
Peak memory 218832 kb
Host smart-0c4412e5-cc94-45ee-a549-82b0ffa08975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035690366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.1035690366
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.3941644884
Short name T166
Test name
Test status
Simulation time 89096383 ps
CPU time 1.16 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:14 PM PDT 24
Peak memory 219516 kb
Host smart-d470a272-35d3-4a8c-b3ed-61b75542b451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941644884 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.3941644884
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.2933702235
Short name T304
Test name
Test status
Simulation time 81998232 ps
CPU time 1.16 seconds
Started Jul 17 07:18:53 PM PDT 24
Finished Jul 17 07:19:00 PM PDT 24
Peak memory 217656 kb
Host smart-a027d899-1c06-424e-ac07-3d6bacd37fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933702235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2933702235
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.413379692
Short name T155
Test name
Test status
Simulation time 28878183 ps
CPU time 1.2 seconds
Started Jul 17 07:18:59 PM PDT 24
Finished Jul 17 07:19:20 PM PDT 24
Peak memory 219056 kb
Host smart-e0e7b3c9-dd69-4fa9-a32d-7de9ea60ec37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413379692 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.413379692
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.970447501
Short name T538
Test name
Test status
Simulation time 60960521 ps
CPU time 1.2 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:19 PM PDT 24
Peak memory 219288 kb
Host smart-8e2e7f80-ec24-4c2a-93be-2a92424c91d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970447501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.970447501
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.839558601
Short name T277
Test name
Test status
Simulation time 73925413 ps
CPU time 1.19 seconds
Started Jul 17 07:18:58 PM PDT 24
Finished Jul 17 07:19:19 PM PDT 24
Peak memory 218760 kb
Host smart-9966ef3f-8d11-4da7-b8cb-a8d67b0186cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839558601 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.839558601
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.3738440213
Short name T739
Test name
Test status
Simulation time 74144909 ps
CPU time 1.49 seconds
Started Jul 17 07:18:59 PM PDT 24
Finished Jul 17 07:19:22 PM PDT 24
Peak memory 220180 kb
Host smart-323fb83b-821e-4453-989c-f7bd9340aac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738440213 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3738440213
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.4000993729
Short name T728
Test name
Test status
Simulation time 81453437 ps
CPU time 1.08 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:14 PM PDT 24
Peak memory 218916 kb
Host smart-e8714f45-8015-4d8f-8b9e-b09d9557b789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000993729 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.4000993729
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert.1435336449
Short name T249
Test name
Test status
Simulation time 59624070 ps
CPU time 1.13 seconds
Started Jul 17 07:14:57 PM PDT 24
Finished Jul 17 07:15:03 PM PDT 24
Peak memory 218816 kb
Host smart-7226e6ea-ec4d-4460-989d-59775d64ec82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435336449 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.1435336449
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.2204526654
Short name T320
Test name
Test status
Simulation time 45677597 ps
CPU time 0.8 seconds
Started Jul 17 07:14:57 PM PDT 24
Finished Jul 17 07:15:04 PM PDT 24
Peak memory 207124 kb
Host smart-081f861d-60a8-4483-9090-114398253c1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204526654 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2204526654
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.3126915740
Short name T709
Test name
Test status
Simulation time 13560820 ps
CPU time 0.91 seconds
Started Jul 17 07:14:59 PM PDT 24
Finished Jul 17 07:15:10 PM PDT 24
Peak memory 216676 kb
Host smart-207fc5f4-6a6d-48ed-b737-ac17391fb8d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126915740 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.3126915740
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.1798988930
Short name T787
Test name
Test status
Simulation time 36259991 ps
CPU time 1.21 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:15:16 PM PDT 24
Peak memory 217148 kb
Host smart-cbb8cde8-4d1f-4130-a71f-2173069711b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798988930 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.1798988930
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.1549329908
Short name T107
Test name
Test status
Simulation time 69189261 ps
CPU time 1.09 seconds
Started Jul 17 07:14:59 PM PDT 24
Finished Jul 17 07:15:13 PM PDT 24
Peak memory 220996 kb
Host smart-b696226e-c0a1-45a9-9479-d326d393f0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549329908 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.1549329908
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.2847976981
Short name T665
Test name
Test status
Simulation time 136445709 ps
CPU time 1.59 seconds
Started Jul 17 07:15:00 PM PDT 24
Finished Jul 17 07:15:14 PM PDT 24
Peak memory 219000 kb
Host smart-997417d2-f41c-41b5-a688-eac785f238a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847976981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.2847976981
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_smoke.2315831886
Short name T520
Test name
Test status
Simulation time 28970468 ps
CPU time 0.94 seconds
Started Jul 17 07:14:58 PM PDT 24
Finished Jul 17 07:15:08 PM PDT 24
Peak memory 215204 kb
Host smart-1cdfcaec-2741-4276-8b5b-fafac2850f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315831886 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2315831886
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1201117937
Short name T664
Test name
Test status
Simulation time 1402643673 ps
CPU time 2.88 seconds
Started Jul 17 07:14:58 PM PDT 24
Finished Jul 17 07:15:10 PM PDT 24
Peak memory 217416 kb
Host smart-2e3f5698-16ef-4685-9a75-4a6e8ff0ff59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201117937 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1201117937
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1268526809
Short name T42
Test name
Test status
Simulation time 400404553621 ps
CPU time 2306.17 seconds
Started Jul 17 07:14:56 PM PDT 24
Finished Jul 17 07:53:26 PM PDT 24
Peak memory 227328 kb
Host smart-830018cc-75d9-4e96-8400-2d9a97ca26e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268526809 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1268526809
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.4107121625
Short name T575
Test name
Test status
Simulation time 45572640 ps
CPU time 1.17 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:12 PM PDT 24
Peak memory 218860 kb
Host smart-2d8980ca-848c-41ee-833f-2a596dbcbfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107121625 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.4107121625
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.2497531412
Short name T866
Test name
Test status
Simulation time 50351822 ps
CPU time 1.18 seconds
Started Jul 17 07:18:47 PM PDT 24
Finished Jul 17 07:18:50 PM PDT 24
Peak memory 217532 kb
Host smart-fed76d9d-5fa2-49e5-8ff0-3b488d0aa98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497531412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.2497531412
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.1865702006
Short name T356
Test name
Test status
Simulation time 25647739 ps
CPU time 1.2 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:19 PM PDT 24
Peak memory 219104 kb
Host smart-c7cb2683-b462-41da-85fc-192feecb7108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865702006 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.1865702006
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.3623132249
Short name T836
Test name
Test status
Simulation time 67944481 ps
CPU time 1.86 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:15 PM PDT 24
Peak memory 219020 kb
Host smart-cef0cca1-03ec-4b32-b52a-6ed30bf5b99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623132249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3623132249
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.500332722
Short name T829
Test name
Test status
Simulation time 143121226 ps
CPU time 1.03 seconds
Started Jul 17 07:18:53 PM PDT 24
Finished Jul 17 07:19:00 PM PDT 24
Peak memory 220220 kb
Host smart-cab7bb85-fd0e-4781-a822-7888372ede3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500332722 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.500332722
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.238508242
Short name T712
Test name
Test status
Simulation time 48547162 ps
CPU time 1.1 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:11 PM PDT 24
Peak memory 219696 kb
Host smart-be851d19-765c-4ea8-aa5e-1c7d1f7c6d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238508242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.238508242
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.3583130676
Short name T753
Test name
Test status
Simulation time 37178435 ps
CPU time 1.12 seconds
Started Jul 17 07:18:58 PM PDT 24
Finished Jul 17 07:19:19 PM PDT 24
Peak memory 218840 kb
Host smart-89aa4b99-e1d7-4d80-ae14-dddd9f346055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583130676 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.3583130676
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.527615624
Short name T933
Test name
Test status
Simulation time 55296812 ps
CPU time 1.03 seconds
Started Jul 17 07:18:53 PM PDT 24
Finished Jul 17 07:18:58 PM PDT 24
Peak memory 217712 kb
Host smart-66f9dd12-f0be-4e9a-8b9c-856f6034e37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527615624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.527615624
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.2995173175
Short name T930
Test name
Test status
Simulation time 50853201 ps
CPU time 1.19 seconds
Started Jul 17 07:18:59 PM PDT 24
Finished Jul 17 07:19:21 PM PDT 24
Peak memory 220124 kb
Host smart-0f594547-19f2-44a0-9211-5298ff36a7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995173175 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.2995173175
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.2253760884
Short name T758
Test name
Test status
Simulation time 59364620 ps
CPU time 1.49 seconds
Started Jul 17 07:18:23 PM PDT 24
Finished Jul 17 07:18:25 PM PDT 24
Peak memory 217940 kb
Host smart-284941ff-f60a-4a9a-a295-b8984c059783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253760884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.2253760884
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.1524776495
Short name T799
Test name
Test status
Simulation time 73424035 ps
CPU time 1.18 seconds
Started Jul 17 07:18:58 PM PDT 24
Finished Jul 17 07:19:19 PM PDT 24
Peak memory 221088 kb
Host smart-1ae6be9b-7161-4f3c-8147-49a722b9a8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524776495 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.1524776495
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.1200995027
Short name T736
Test name
Test status
Simulation time 42615664 ps
CPU time 1.49 seconds
Started Jul 17 07:18:53 PM PDT 24
Finished Jul 17 07:18:58 PM PDT 24
Peak memory 219004 kb
Host smart-498c0b73-2427-4b3f-8536-3754e0340e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200995027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.1200995027
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.1399456941
Short name T268
Test name
Test status
Simulation time 194335203 ps
CPU time 1.23 seconds
Started Jul 17 07:19:02 PM PDT 24
Finished Jul 17 07:19:26 PM PDT 24
Peak memory 220620 kb
Host smart-40c105dd-27ef-4f19-95fe-b25af237c93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399456941 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.1399456941
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.918546373
Short name T882
Test name
Test status
Simulation time 46676768 ps
CPU time 1.51 seconds
Started Jul 17 07:18:58 PM PDT 24
Finished Jul 17 07:19:19 PM PDT 24
Peak memory 218532 kb
Host smart-f58c1142-6dc8-4545-9f31-fa38ebbbdcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918546373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.918546373
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.4141406482
Short name T875
Test name
Test status
Simulation time 121734415 ps
CPU time 1.27 seconds
Started Jul 17 07:18:58 PM PDT 24
Finished Jul 17 07:19:20 PM PDT 24
Peak memory 219840 kb
Host smart-b58b7a5e-e0ba-479a-9573-875e3f606e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141406482 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.4141406482
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.3999184361
Short name T727
Test name
Test status
Simulation time 55612203 ps
CPU time 1.17 seconds
Started Jul 17 07:18:59 PM PDT 24
Finished Jul 17 07:19:22 PM PDT 24
Peak memory 217492 kb
Host smart-c721c836-62f3-4121-8a51-547df89b0b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999184361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.3999184361
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.1049320162
Short name T843
Test name
Test status
Simulation time 87314989 ps
CPU time 1.2 seconds
Started Jul 17 07:18:59 PM PDT 24
Finished Jul 17 07:19:22 PM PDT 24
Peak memory 218864 kb
Host smart-2a1945a7-cef6-4056-bcf4-4e72189444e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049320162 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.1049320162
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.2476379451
Short name T556
Test name
Test status
Simulation time 210233429 ps
CPU time 2.69 seconds
Started Jul 17 07:18:59 PM PDT 24
Finished Jul 17 07:19:24 PM PDT 24
Peak memory 217864 kb
Host smart-49408e7d-6e47-46d5-9d5f-86012fe39821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476379451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.2476379451
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.4149565837
Short name T97
Test name
Test status
Simulation time 50051976 ps
CPU time 1.23 seconds
Started Jul 17 07:19:00 PM PDT 24
Finished Jul 17 07:19:23 PM PDT 24
Peak memory 219916 kb
Host smart-13f09e16-8e97-4903-954c-ad836737611f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149565837 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.4149565837
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.127304392
Short name T635
Test name
Test status
Simulation time 173144479 ps
CPU time 1.02 seconds
Started Jul 17 07:18:59 PM PDT 24
Finished Jul 17 07:19:21 PM PDT 24
Peak memory 217684 kb
Host smart-3bf46a90-4ad1-406b-b46b-2fa7b6adcef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127304392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.127304392
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.599095252
Short name T553
Test name
Test status
Simulation time 65681790 ps
CPU time 1.09 seconds
Started Jul 17 07:14:59 PM PDT 24
Finished Jul 17 07:15:13 PM PDT 24
Peak memory 218752 kb
Host smart-1e0e4fa9-2ec2-4c9d-a039-f435fbdf96b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599095252 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.599095252
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.4234749337
Short name T892
Test name
Test status
Simulation time 22303906 ps
CPU time 0.84 seconds
Started Jul 17 07:15:03 PM PDT 24
Finished Jul 17 07:15:19 PM PDT 24
Peak memory 207012 kb
Host smart-62c5089c-1e14-47dd-9a11-6d344f6d7d19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234749337 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.4234749337
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.2006876274
Short name T195
Test name
Test status
Simulation time 18315202 ps
CPU time 0.84 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:15:17 PM PDT 24
Peak memory 216460 kb
Host smart-0ca7cfb7-21ed-4b75-a933-ce55e6364e91
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006876274 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2006876274
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.2452153469
Short name T133
Test name
Test status
Simulation time 36361829 ps
CPU time 1.16 seconds
Started Jul 17 07:15:00 PM PDT 24
Finished Jul 17 07:15:14 PM PDT 24
Peak memory 217256 kb
Host smart-c1b73855-5cbf-46bc-8903-8d9c474a84a2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452153469 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.2452153469
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.4132883773
Short name T188
Test name
Test status
Simulation time 75514285 ps
CPU time 1.05 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:15:15 PM PDT 24
Peak memory 220172 kb
Host smart-b42afb26-008e-4ee6-b9a9-8d1c9695e859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132883773 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.4132883773
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.3638260586
Short name T396
Test name
Test status
Simulation time 89413505 ps
CPU time 1.22 seconds
Started Jul 17 07:15:00 PM PDT 24
Finished Jul 17 07:15:14 PM PDT 24
Peak memory 218884 kb
Host smart-7be49ff9-aea1-445f-a327-391131fa7f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638260586 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3638260586
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.556923487
Short name T38
Test name
Test status
Simulation time 22705384 ps
CPU time 0.94 seconds
Started Jul 17 07:14:57 PM PDT 24
Finished Jul 17 07:15:05 PM PDT 24
Peak memory 216196 kb
Host smart-81dea9ec-e49b-45ac-bdc0-715e32107993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556923487 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.556923487
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.4194774504
Short name T817
Test name
Test status
Simulation time 50930943 ps
CPU time 0.97 seconds
Started Jul 17 07:14:57 PM PDT 24
Finished Jul 17 07:15:03 PM PDT 24
Peak memory 215580 kb
Host smart-253e9084-009f-4c9b-a569-16e20af08ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194774504 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.4194774504
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.1408111368
Short name T671
Test name
Test status
Simulation time 271808650 ps
CPU time 5.4 seconds
Started Jul 17 07:15:00 PM PDT 24
Finished Jul 17 07:15:19 PM PDT 24
Peak memory 220556 kb
Host smart-28b8b4c4-c8f0-40b7-ae95-a5d2d73c30f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408111368 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.1408111368
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.1451819683
Short name T735
Test name
Test status
Simulation time 46105824264 ps
CPU time 922.25 seconds
Started Jul 17 07:15:00 PM PDT 24
Finished Jul 17 07:30:35 PM PDT 24
Peak memory 220052 kb
Host smart-a3d2b7e2-a138-4e8a-9d53-66e629815945
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451819683 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.1451819683
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.1957579350
Short name T704
Test name
Test status
Simulation time 85761633 ps
CPU time 1.16 seconds
Started Jul 17 07:19:01 PM PDT 24
Finished Jul 17 07:19:26 PM PDT 24
Peak memory 219580 kb
Host smart-7e401833-4831-425b-907a-0683be3983e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957579350 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.1957579350
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.930764411
Short name T410
Test name
Test status
Simulation time 35645575 ps
CPU time 1.02 seconds
Started Jul 17 07:19:06 PM PDT 24
Finished Jul 17 07:19:31 PM PDT 24
Peak memory 217544 kb
Host smart-40df1e82-ca02-491d-9553-b5a0318e8b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930764411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.930764411
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.3560225004
Short name T482
Test name
Test status
Simulation time 69615678 ps
CPU time 1.06 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:10 PM PDT 24
Peak memory 220292 kb
Host smart-a8d13e11-5cf3-4956-b575-110cee9b2d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560225004 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.3560225004
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.388252226
Short name T290
Test name
Test status
Simulation time 106978811 ps
CPU time 1.31 seconds
Started Jul 17 07:19:01 PM PDT 24
Finished Jul 17 07:19:26 PM PDT 24
Peak memory 217036 kb
Host smart-47e7e3a4-1839-48b7-9f61-1a9d113e50b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388252226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.388252226
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.3152775599
Short name T443
Test name
Test status
Simulation time 127483190 ps
CPU time 2.81 seconds
Started Jul 17 07:18:54 PM PDT 24
Finished Jul 17 07:19:06 PM PDT 24
Peak memory 219036 kb
Host smart-7dedf342-e64c-45a6-badc-e494e126edd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152775599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.3152775599
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.4241347976
Short name T205
Test name
Test status
Simulation time 24860857 ps
CPU time 1.2 seconds
Started Jul 17 07:18:55 PM PDT 24
Finished Jul 17 07:19:05 PM PDT 24
Peak memory 218880 kb
Host smart-ba8c8d91-4e86-4558-a6e7-109bf05b84b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241347976 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.4241347976
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.961701247
Short name T283
Test name
Test status
Simulation time 72688138 ps
CPU time 1.49 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:15 PM PDT 24
Peak memory 217560 kb
Host smart-66482f1f-7a9e-415d-a203-87d6d92e278c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961701247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.961701247
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.3628178372
Short name T620
Test name
Test status
Simulation time 23795983 ps
CPU time 1.18 seconds
Started Jul 17 07:18:55 PM PDT 24
Finished Jul 17 07:19:07 PM PDT 24
Peak memory 219088 kb
Host smart-75efed99-d427-47f1-9d49-8131503ef0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628178372 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.3628178372
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.2241635599
Short name T470
Test name
Test status
Simulation time 236074155 ps
CPU time 1.88 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:12 PM PDT 24
Peak memory 218908 kb
Host smart-9921b39a-292f-498a-99d0-58c7bec4d424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241635599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2241635599
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.892493887
Short name T594
Test name
Test status
Simulation time 26423409 ps
CPU time 1.14 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:11 PM PDT 24
Peak memory 218856 kb
Host smart-b9f6ed14-e520-426d-9eac-27f688e96ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892493887 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.892493887
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.157076850
Short name T321
Test name
Test status
Simulation time 41064183 ps
CPU time 1.31 seconds
Started Jul 17 07:18:50 PM PDT 24
Finished Jul 17 07:18:53 PM PDT 24
Peak memory 218656 kb
Host smart-dcf59e61-9495-4011-b47c-eff5bcb249c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157076850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.157076850
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.1123928113
Short name T696
Test name
Test status
Simulation time 70344761 ps
CPU time 1.15 seconds
Started Jul 17 07:19:00 PM PDT 24
Finished Jul 17 07:19:22 PM PDT 24
Peak memory 219968 kb
Host smart-3c9f23ee-13a5-4de6-a0e9-f93e0e7b2ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123928113 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.1123928113
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/197.edn_alert.2984717126
Short name T583
Test name
Test status
Simulation time 39260767 ps
CPU time 1.15 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:14 PM PDT 24
Peak memory 220200 kb
Host smart-92d47932-ea8f-4ec7-b79d-6abcf9119f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984717126 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.2984717126
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.1689643983
Short name T45
Test name
Test status
Simulation time 97909480 ps
CPU time 1.17 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:17 PM PDT 24
Peak memory 217644 kb
Host smart-1ae3ee1f-6137-4a55-a7d9-e5da8718ef18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689643983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.1689643983
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.2758461783
Short name T794
Test name
Test status
Simulation time 89258238 ps
CPU time 1.15 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:14 PM PDT 24
Peak memory 220024 kb
Host smart-bd92e7b8-1867-4858-88fc-d41045c4c4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758461783 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.2758461783
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.4096242685
Short name T434
Test name
Test status
Simulation time 74924325 ps
CPU time 1.15 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:18 PM PDT 24
Peak memory 215536 kb
Host smart-4aa39651-d45a-4a5e-9bf5-e49d6088b300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096242685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.4096242685
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.2420994460
Short name T199
Test name
Test status
Simulation time 26970224 ps
CPU time 1.21 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:12 PM PDT 24
Peak memory 218940 kb
Host smart-71721b53-eb62-4b9c-9f06-416d7adaf0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420994460 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.2420994460
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.3848030730
Short name T559
Test name
Test status
Simulation time 35312247 ps
CPU time 1.37 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:10 PM PDT 24
Peak memory 218656 kb
Host smart-887edf7f-b9db-45fd-ac6d-db9553192fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848030730 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.3848030730
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert_test.1064111472
Short name T821
Test name
Test status
Simulation time 56587116 ps
CPU time 0.88 seconds
Started Jul 17 07:14:30 PM PDT 24
Finished Jul 17 07:14:32 PM PDT 24
Peak memory 207064 kb
Host smart-c8869b9b-e914-47ca-95ed-f02e3de1c369
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064111472 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.1064111472
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.3984282990
Short name T109
Test name
Test status
Simulation time 67888382 ps
CPU time 1.25 seconds
Started Jul 17 07:14:35 PM PDT 24
Finished Jul 17 07:14:44 PM PDT 24
Peak memory 217160 kb
Host smart-8b90c546-2f39-47de-98ac-d4bcd0728a4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984282990 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.3984282990
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.1500952855
Short name T138
Test name
Test status
Simulation time 29704655 ps
CPU time 1.35 seconds
Started Jul 17 07:14:34 PM PDT 24
Finished Jul 17 07:14:41 PM PDT 24
Peak memory 226044 kb
Host smart-aa7ec13b-9928-4552-9172-971075e383ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500952855 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.1500952855
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.1905030762
Short name T298
Test name
Test status
Simulation time 85927901 ps
CPU time 1.62 seconds
Started Jul 17 07:14:32 PM PDT 24
Finished Jul 17 07:14:37 PM PDT 24
Peak memory 220224 kb
Host smart-bbe3aba2-6330-4fb6-8dac-01358aabc368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905030762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1905030762
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.3704628913
Short name T391
Test name
Test status
Simulation time 24767527 ps
CPU time 0.93 seconds
Started Jul 17 07:14:30 PM PDT 24
Finished Jul 17 07:14:34 PM PDT 24
Peak memory 215848 kb
Host smart-5ee1df75-ccc7-480e-889e-ba0585727fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704628913 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.3704628913
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.3578554437
Short name T26
Test name
Test status
Simulation time 30785915 ps
CPU time 0.95 seconds
Started Jul 17 07:14:38 PM PDT 24
Finished Jul 17 07:14:46 PM PDT 24
Peak memory 207284 kb
Host smart-f819e732-66db-4d2c-9d94-fb40fa3c82d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578554437 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3578554437
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.3619147424
Short name T56
Test name
Test status
Simulation time 2261004346 ps
CPU time 8.51 seconds
Started Jul 17 07:14:33 PM PDT 24
Finished Jul 17 07:14:46 PM PDT 24
Peak memory 236368 kb
Host smart-102a887c-59d3-4899-a1e9-95cb97f72872
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619147424 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.3619147424
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.2865805093
Short name T973
Test name
Test status
Simulation time 42690062 ps
CPU time 0.92 seconds
Started Jul 17 07:14:36 PM PDT 24
Finished Jul 17 07:14:43 PM PDT 24
Peak memory 215528 kb
Host smart-5228905f-072a-453a-b51b-7acbbdb24fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865805093 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.2865805093
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.2530118883
Short name T546
Test name
Test status
Simulation time 587246868 ps
CPU time 5.47 seconds
Started Jul 17 07:14:35 PM PDT 24
Finished Jul 17 07:14:47 PM PDT 24
Peak memory 215536 kb
Host smart-93af54a9-a39a-462c-a52d-5840edbac4b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530118883 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2530118883
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.2478093930
Short name T208
Test name
Test status
Simulation time 95979469175 ps
CPU time 603.9 seconds
Started Jul 17 07:14:35 PM PDT 24
Finished Jul 17 07:24:46 PM PDT 24
Peak memory 224080 kb
Host smart-c3185ff3-a79b-4c37-bc9d-ee4f72eff7a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478093930 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.2478093930
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.2539516542
Short name T146
Test name
Test status
Simulation time 41537993 ps
CPU time 1.12 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:15:16 PM PDT 24
Peak memory 219044 kb
Host smart-466139f7-f30e-4bd5-b8c9-3f1ce84ab4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539516542 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.2539516542
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.2433937036
Short name T771
Test name
Test status
Simulation time 54631572 ps
CPU time 0.88 seconds
Started Jul 17 07:15:05 PM PDT 24
Finished Jul 17 07:15:23 PM PDT 24
Peak memory 207024 kb
Host smart-e9603f91-21ef-423e-a6d1-7d041a987b05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433937036 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2433937036
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.100435095
Short name T505
Test name
Test status
Simulation time 23174381 ps
CPU time 0.88 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:15:17 PM PDT 24
Peak memory 215536 kb
Host smart-ea6e3f9f-3760-4bfd-a922-de6fd9f2c8e0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100435095 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.100435095
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.3304512040
Short name T597
Test name
Test status
Simulation time 60294312 ps
CPU time 1.37 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:15:18 PM PDT 24
Peak memory 217240 kb
Host smart-d71201f9-723a-4f1f-bde1-6c1f115b1913
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304512040 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.3304512040
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.154238051
Short name T850
Test name
Test status
Simulation time 46356961 ps
CPU time 1 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:15:17 PM PDT 24
Peak memory 218904 kb
Host smart-a676e1e8-01be-4a58-8015-a30a9496678b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154238051 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.154238051
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.481245331
Short name T945
Test name
Test status
Simulation time 53456982 ps
CPU time 0.99 seconds
Started Jul 17 07:15:02 PM PDT 24
Finished Jul 17 07:15:17 PM PDT 24
Peak memory 217636 kb
Host smart-a8c8f3d4-c6f1-465b-93a5-bdc1bbbe89aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481245331 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.481245331
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.1219104941
Short name T891
Test name
Test status
Simulation time 30350818 ps
CPU time 1.05 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:15:17 PM PDT 24
Peak memory 215768 kb
Host smart-9bfd549e-2ae5-4f5f-9aa6-5308c595d20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219104941 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1219104941
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.3601848128
Short name T413
Test name
Test status
Simulation time 26831777 ps
CPU time 0.91 seconds
Started Jul 17 07:15:02 PM PDT 24
Finished Jul 17 07:15:18 PM PDT 24
Peak memory 215532 kb
Host smart-02d34865-0f00-46f7-850f-95c8fe3a478e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601848128 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.3601848128
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.3275150169
Short name T960
Test name
Test status
Simulation time 189464091 ps
CPU time 1.58 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:15:17 PM PDT 24
Peak memory 215564 kb
Host smart-6d7fb44e-8c52-4b54-99fb-ec0a5137b736
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275150169 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3275150169
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.1709718491
Short name T779
Test name
Test status
Simulation time 212338777111 ps
CPU time 1350.69 seconds
Started Jul 17 07:15:04 PM PDT 24
Finished Jul 17 07:37:51 PM PDT 24
Peak memory 226232 kb
Host smart-9b7000ad-47c0-4030-8f51-53132c8fbfad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709718491 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.1709718491
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.898841363
Short name T521
Test name
Test status
Simulation time 70392479 ps
CPU time 2.49 seconds
Started Jul 17 07:18:53 PM PDT 24
Finished Jul 17 07:18:59 PM PDT 24
Peak memory 220068 kb
Host smart-ea31053e-6338-4b10-812a-7ed321943982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898841363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.898841363
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.3992566032
Short name T614
Test name
Test status
Simulation time 59461299 ps
CPU time 1.09 seconds
Started Jul 17 07:18:58 PM PDT 24
Finished Jul 17 07:19:19 PM PDT 24
Peak memory 220068 kb
Host smart-6f0a2758-8183-4c2a-a56a-678661020797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992566032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.3992566032
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.3954381302
Short name T343
Test name
Test status
Simulation time 56762317 ps
CPU time 1.21 seconds
Started Jul 17 07:18:49 PM PDT 24
Finished Jul 17 07:18:52 PM PDT 24
Peak memory 219748 kb
Host smart-3f7431cc-8ba3-4ef3-ad2f-351814623adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954381302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3954381302
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.3017727722
Short name T907
Test name
Test status
Simulation time 76028678 ps
CPU time 1.27 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:14 PM PDT 24
Peak memory 219036 kb
Host smart-41c4345f-b5ea-47ad-88f7-3d53e8cd49aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017727722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.3017727722
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.1883723151
Short name T282
Test name
Test status
Simulation time 101369529 ps
CPU time 2.24 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:11 PM PDT 24
Peak memory 218932 kb
Host smart-5dff4d5b-a8d4-4cd5-8351-c9ce0b8dd4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883723151 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.1883723151
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.911985459
Short name T582
Test name
Test status
Simulation time 295420648 ps
CPU time 1.33 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:10 PM PDT 24
Peak memory 218796 kb
Host smart-95b5e6e7-3d4c-49e4-919c-40a1c2b53ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911985459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.911985459
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2394524109
Short name T774
Test name
Test status
Simulation time 77734358 ps
CPU time 1.2 seconds
Started Jul 17 07:18:52 PM PDT 24
Finished Jul 17 07:18:57 PM PDT 24
Peak memory 218940 kb
Host smart-cc90b49e-5ae2-4cb0-97dc-c345a2a36c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394524109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2394524109
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.2789571663
Short name T453
Test name
Test status
Simulation time 40118024 ps
CPU time 1.41 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:14 PM PDT 24
Peak memory 218680 kb
Host smart-282acf6c-dc4b-441c-990d-1ec589e2922a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789571663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.2789571663
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.3030632785
Short name T480
Test name
Test status
Simulation time 90880713 ps
CPU time 2.01 seconds
Started Jul 17 07:18:54 PM PDT 24
Finished Jul 17 07:19:02 PM PDT 24
Peak memory 218936 kb
Host smart-ff3ca0a3-bf18-43f9-9973-39468effc336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030632785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.3030632785
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.2425377270
Short name T729
Test name
Test status
Simulation time 111185318 ps
CPU time 1.3 seconds
Started Jul 17 07:18:54 PM PDT 24
Finished Jul 17 07:19:04 PM PDT 24
Peak memory 217744 kb
Host smart-d7bbca6d-8d40-49a4-a1b8-6eab1f8b2da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425377270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.2425377270
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.1008332763
Short name T122
Test name
Test status
Simulation time 100486338 ps
CPU time 1.21 seconds
Started Jul 17 07:15:03 PM PDT 24
Finished Jul 17 07:15:20 PM PDT 24
Peak memory 220644 kb
Host smart-4541b16f-8ca4-4300-ba6d-4babff1d10a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008332763 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.1008332763
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.95941688
Short name T584
Test name
Test status
Simulation time 15203544 ps
CPU time 0.96 seconds
Started Jul 17 07:15:04 PM PDT 24
Finished Jul 17 07:15:21 PM PDT 24
Peak memory 214976 kb
Host smart-e3a4e29c-281a-4356-b7d8-2ffa3a57e36d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95941688 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.95941688
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.2594667035
Short name T351
Test name
Test status
Simulation time 11663307 ps
CPU time 0.89 seconds
Started Jul 17 07:15:05 PM PDT 24
Finished Jul 17 07:15:23 PM PDT 24
Peak memory 216208 kb
Host smart-fb1698e6-614b-4af3-b028-06c50de8d5a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594667035 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.2594667035
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.3187958931
Short name T73
Test name
Test status
Simulation time 32973650 ps
CPU time 1.21 seconds
Started Jul 17 07:15:04 PM PDT 24
Finished Jul 17 07:15:21 PM PDT 24
Peak memory 217360 kb
Host smart-719c8077-c503-4b96-b0a5-f2aa4e92f1ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187958931 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.3187958931
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.1655214188
Short name T971
Test name
Test status
Simulation time 61213444 ps
CPU time 0.89 seconds
Started Jul 17 07:15:06 PM PDT 24
Finished Jul 17 07:15:23 PM PDT 24
Peak memory 218924 kb
Host smart-38d17df3-29ad-4d3f-b63c-7b1a88ac14d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655214188 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.1655214188
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.3859909631
Short name T570
Test name
Test status
Simulation time 59729565 ps
CPU time 1.27 seconds
Started Jul 17 07:15:05 PM PDT 24
Finished Jul 17 07:15:23 PM PDT 24
Peak memory 217464 kb
Host smart-7ed9b207-aa93-46f5-b872-52514b377498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859909631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.3859909631
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.3381394288
Short name T713
Test name
Test status
Simulation time 32929380 ps
CPU time 1.04 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:15:17 PM PDT 24
Peak memory 224252 kb
Host smart-60a486c1-cb64-4910-8d61-63874b83565d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381394288 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3381394288
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.3949853965
Short name T607
Test name
Test status
Simulation time 24037437 ps
CPU time 0.94 seconds
Started Jul 17 07:15:05 PM PDT 24
Finished Jul 17 07:15:23 PM PDT 24
Peak memory 215708 kb
Host smart-1ce24772-7ec3-4e0f-b236-ab605b6e4d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949853965 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.3949853965
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.2702242940
Short name T605
Test name
Test status
Simulation time 420649278 ps
CPU time 3 seconds
Started Jul 17 07:15:05 PM PDT 24
Finished Jul 17 07:15:25 PM PDT 24
Peak memory 215752 kb
Host smart-dc687386-a639-47d3-a57b-ba95102198de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702242940 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2702242940
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.1492693139
Short name T209
Test name
Test status
Simulation time 5339096609 ps
CPU time 120.2 seconds
Started Jul 17 07:15:02 PM PDT 24
Finished Jul 17 07:17:17 PM PDT 24
Peak memory 220892 kb
Host smart-c7bad1aa-6b2a-4782-b304-e91df4ec437f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492693139 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.1492693139
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.1298030057
Short name T644
Test name
Test status
Simulation time 95201940 ps
CPU time 1.45 seconds
Started Jul 17 07:18:55 PM PDT 24
Finished Jul 17 07:19:05 PM PDT 24
Peak memory 219208 kb
Host smart-1053e9fd-94e5-4d8a-a942-b21e6c0fb9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298030057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.1298030057
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.1221673425
Short name T297
Test name
Test status
Simulation time 186755006 ps
CPU time 2.66 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:11 PM PDT 24
Peak memory 220384 kb
Host smart-001ca5f5-28f2-4043-b848-6fb5958ae0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221673425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.1221673425
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.3238207302
Short name T684
Test name
Test status
Simulation time 56482056 ps
CPU time 1.25 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:11 PM PDT 24
Peak memory 218840 kb
Host smart-ad823ca2-8a21-43eb-9e22-6e7f8ee8b754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238207302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.3238207302
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.2945257090
Short name T972
Test name
Test status
Simulation time 70015067 ps
CPU time 1.14 seconds
Started Jul 17 07:18:58 PM PDT 24
Finished Jul 17 07:19:19 PM PDT 24
Peak memory 217376 kb
Host smart-c813fc36-b9fe-425e-923f-df44cdc9a1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945257090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.2945257090
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.2153189325
Short name T416
Test name
Test status
Simulation time 49815708 ps
CPU time 1.27 seconds
Started Jul 17 07:19:02 PM PDT 24
Finished Jul 17 07:19:26 PM PDT 24
Peak memory 220344 kb
Host smart-e0e4b71f-825f-4b73-94e8-a4a50974f4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153189325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.2153189325
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.2575020793
Short name T701
Test name
Test status
Simulation time 53470417 ps
CPU time 1.72 seconds
Started Jul 17 07:18:50 PM PDT 24
Finished Jul 17 07:18:53 PM PDT 24
Peak memory 217752 kb
Host smart-9bae4e9f-51fd-445e-b402-bbce483aa0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575020793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.2575020793
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.2113123980
Short name T415
Test name
Test status
Simulation time 39466811 ps
CPU time 1.33 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:15 PM PDT 24
Peak memory 215652 kb
Host smart-88138567-fafc-49e0-82b4-69966d708008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113123980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.2113123980
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.3559972104
Short name T358
Test name
Test status
Simulation time 32509482 ps
CPU time 1.18 seconds
Started Jul 17 07:18:49 PM PDT 24
Finished Jul 17 07:18:52 PM PDT 24
Peak memory 217468 kb
Host smart-0d7a71e3-9436-4bb1-a75b-43c9170ba7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559972104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.3559972104
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.2818968197
Short name T402
Test name
Test status
Simulation time 77048018 ps
CPU time 1.04 seconds
Started Jul 17 07:18:54 PM PDT 24
Finished Jul 17 07:19:02 PM PDT 24
Peak memory 217564 kb
Host smart-795883b5-b099-4565-8a5e-119d56858e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818968197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.2818968197
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.799357746
Short name T763
Test name
Test status
Simulation time 45963267 ps
CPU time 1.16 seconds
Started Jul 17 07:14:58 PM PDT 24
Finished Jul 17 07:15:06 PM PDT 24
Peak memory 219416 kb
Host smart-a1bf69a1-40d0-4139-b114-f39829fbe5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799357746 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.799357746
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.1767826997
Short name T615
Test name
Test status
Simulation time 57075083 ps
CPU time 0.94 seconds
Started Jul 17 07:14:56 PM PDT 24
Finished Jul 17 07:15:00 PM PDT 24
Peak memory 207084 kb
Host smart-2d4f2941-3ebf-4f2a-9149-82cec2e29655
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767826997 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1767826997
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.2486046681
Short name T203
Test name
Test status
Simulation time 33548666 ps
CPU time 0.83 seconds
Started Jul 17 07:14:56 PM PDT 24
Finished Jul 17 07:15:01 PM PDT 24
Peak memory 215676 kb
Host smart-56893a32-aa52-4e08-bd32-4a7a39d4ea26
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486046681 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2486046681
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_err.2132530368
Short name T95
Test name
Test status
Simulation time 33588269 ps
CPU time 1.01 seconds
Started Jul 17 07:14:56 PM PDT 24
Finished Jul 17 07:15:01 PM PDT 24
Peak memory 220008 kb
Host smart-433aabd3-e046-43a5-be6d-0ca76632350b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132530368 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.2132530368
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.4069857587
Short name T14
Test name
Test status
Simulation time 41602040 ps
CPU time 1.49 seconds
Started Jul 17 07:14:53 PM PDT 24
Finished Jul 17 07:14:56 PM PDT 24
Peak memory 220220 kb
Host smart-d02a7b44-5d6b-4911-9224-d32c2bb26aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069857587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.4069857587
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.2522392520
Short name T881
Test name
Test status
Simulation time 57064250 ps
CPU time 0.95 seconds
Started Jul 17 07:14:59 PM PDT 24
Finished Jul 17 07:15:11 PM PDT 24
Peak memory 224168 kb
Host smart-892445d4-618d-41a3-9b3c-36815c1becd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522392520 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.2522392520
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.2071109352
Short name T328
Test name
Test status
Simulation time 18640340 ps
CPU time 0.99 seconds
Started Jul 17 07:14:59 PM PDT 24
Finished Jul 17 07:15:11 PM PDT 24
Peak memory 215508 kb
Host smart-b1c3063d-ecc7-4737-93fb-660703b16b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071109352 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2071109352
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.970875060
Short name T663
Test name
Test status
Simulation time 694848618 ps
CPU time 3.98 seconds
Started Jul 17 07:14:58 PM PDT 24
Finished Jul 17 07:15:09 PM PDT 24
Peak memory 217544 kb
Host smart-9fc3d322-2aba-4200-9f42-8730e7082a2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970875060 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.970875060
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3060161425
Short name T824
Test name
Test status
Simulation time 140741841392 ps
CPU time 1377.51 seconds
Started Jul 17 07:14:57 PM PDT 24
Finished Jul 17 07:38:00 PM PDT 24
Peak memory 224620 kb
Host smart-a2e00d28-bebb-4dd8-bf4b-f2809e40b2ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060161425 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3060161425
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.2864445133
Short name T355
Test name
Test status
Simulation time 88983838 ps
CPU time 1.21 seconds
Started Jul 17 07:18:49 PM PDT 24
Finished Jul 17 07:18:52 PM PDT 24
Peak memory 220156 kb
Host smart-5cbaaae7-daa0-47e2-baaf-c2600063ccb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864445133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.2864445133
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.926765259
Short name T336
Test name
Test status
Simulation time 60916620 ps
CPU time 1.03 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:14 PM PDT 24
Peak memory 217652 kb
Host smart-11d9f076-2e48-4064-b4a0-8c52c5f13f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926765259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.926765259
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.3080219487
Short name T501
Test name
Test status
Simulation time 42534742 ps
CPU time 1.45 seconds
Started Jul 17 07:18:59 PM PDT 24
Finished Jul 17 07:19:21 PM PDT 24
Peak memory 218840 kb
Host smart-23517a75-2f66-4baa-94ce-7c990870659a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080219487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.3080219487
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.262506257
Short name T576
Test name
Test status
Simulation time 68523344 ps
CPU time 1.37 seconds
Started Jul 17 07:18:49 PM PDT 24
Finished Jul 17 07:18:52 PM PDT 24
Peak memory 218940 kb
Host smart-82ee978a-111f-453b-bcc5-584132da4b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262506257 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.262506257
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.1925150287
Short name T448
Test name
Test status
Simulation time 56541272 ps
CPU time 1 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:18 PM PDT 24
Peak memory 219968 kb
Host smart-26c6d948-dc18-4514-a3be-54bc59533fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925150287 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.1925150287
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.3434761317
Short name T425
Test name
Test status
Simulation time 75000082 ps
CPU time 1.13 seconds
Started Jul 17 07:18:55 PM PDT 24
Finished Jul 17 07:19:06 PM PDT 24
Peak memory 217508 kb
Host smart-1ccad3ad-68f5-4a33-ac47-8ada982399b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434761317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.3434761317
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.2978957933
Short name T569
Test name
Test status
Simulation time 102542876 ps
CPU time 1.83 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:15 PM PDT 24
Peak memory 219020 kb
Host smart-ae554737-4a4a-4a64-8fde-92db4adcca8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978957933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.2978957933
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.1635455031
Short name T66
Test name
Test status
Simulation time 98196128 ps
CPU time 1.25 seconds
Started Jul 17 07:18:49 PM PDT 24
Finished Jul 17 07:18:52 PM PDT 24
Peak memory 217692 kb
Host smart-7433d7db-eeb3-48c2-ba11-6a10fc41f05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635455031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.1635455031
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.3247880988
Short name T424
Test name
Test status
Simulation time 26251611 ps
CPU time 1.17 seconds
Started Jul 17 07:18:59 PM PDT 24
Finished Jul 17 07:19:20 PM PDT 24
Peak memory 217688 kb
Host smart-49a90e2e-c05d-4582-b682-d36844a75271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247880988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.3247880988
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.3141027366
Short name T830
Test name
Test status
Simulation time 26666210 ps
CPU time 1.18 seconds
Started Jul 17 07:14:58 PM PDT 24
Finished Jul 17 07:15:10 PM PDT 24
Peak memory 219216 kb
Host smart-8b5c0971-e168-42df-9ffe-8cb28ad28379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141027366 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.3141027366
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.635287998
Short name T565
Test name
Test status
Simulation time 34393317 ps
CPU time 0.8 seconds
Started Jul 17 07:15:00 PM PDT 24
Finished Jul 17 07:15:13 PM PDT 24
Peak memory 207072 kb
Host smart-35e46635-e3af-481a-98df-7ddc2136da91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635287998 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.635287998
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.614619583
Short name T96
Test name
Test status
Simulation time 31739772 ps
CPU time 0.97 seconds
Started Jul 17 07:15:02 PM PDT 24
Finished Jul 17 07:15:17 PM PDT 24
Peak memory 219952 kb
Host smart-3230e681-dfc8-401e-9462-39e43ab840e5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614619583 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_di
sable_auto_req_mode.614619583
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.1113154734
Short name T551
Test name
Test status
Simulation time 63777892 ps
CPU time 0.87 seconds
Started Jul 17 07:14:59 PM PDT 24
Finished Jul 17 07:15:11 PM PDT 24
Peak memory 218608 kb
Host smart-1aa2b306-b3c4-45f4-80e7-c028eb7b61a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113154734 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1113154734
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.3362837322
Short name T720
Test name
Test status
Simulation time 38468661 ps
CPU time 1.34 seconds
Started Jul 17 07:14:56 PM PDT 24
Finished Jul 17 07:15:02 PM PDT 24
Peak memory 217576 kb
Host smart-ae5509b6-5af5-4a87-ad19-f410ba09dbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362837322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3362837322
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_smoke.1465602893
Short name T397
Test name
Test status
Simulation time 39297729 ps
CPU time 0.86 seconds
Started Jul 17 07:14:53 PM PDT 24
Finished Jul 17 07:14:55 PM PDT 24
Peak memory 215504 kb
Host smart-deea19fc-b104-4235-a22c-1216a93c6f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465602893 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.1465602893
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.1048485649
Short name T670
Test name
Test status
Simulation time 1017248220 ps
CPU time 5.21 seconds
Started Jul 17 07:14:56 PM PDT 24
Finished Jul 17 07:15:07 PM PDT 24
Peak memory 215656 kb
Host smart-2127f363-4ce3-4741-8743-e8714100aec7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048485649 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.1048485649
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.1507101133
Short name T214
Test name
Test status
Simulation time 46645111628 ps
CPU time 377.55 seconds
Started Jul 17 07:14:57 PM PDT 24
Finished Jul 17 07:21:22 PM PDT 24
Peak memory 218832 kb
Host smart-bb0c3d87-ef29-471a-8b89-78a2583ab08b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507101133 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.1507101133
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.3180618389
Short name T6
Test name
Test status
Simulation time 55368838 ps
CPU time 2.03 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:15 PM PDT 24
Peak memory 217564 kb
Host smart-a8aced9f-a957-4099-a9c3-0cf67fde8a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180618389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.3180618389
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.2970188321
Short name T833
Test name
Test status
Simulation time 114681093 ps
CPU time 2.7 seconds
Started Jul 17 07:19:00 PM PDT 24
Finished Jul 17 07:19:24 PM PDT 24
Peak memory 219132 kb
Host smart-ec9e70c0-2bc9-40a5-9f55-1f9c75526ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970188321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.2970188321
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.2804721547
Short name T479
Test name
Test status
Simulation time 135155671 ps
CPU time 1.39 seconds
Started Jul 17 07:18:59 PM PDT 24
Finished Jul 17 07:19:22 PM PDT 24
Peak memory 217664 kb
Host smart-da0cd354-6d67-44b8-9ffb-d84c2e40af5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804721547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.2804721547
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.2841189375
Short name T13
Test name
Test status
Simulation time 33397706 ps
CPU time 1.35 seconds
Started Jul 17 07:18:58 PM PDT 24
Finished Jul 17 07:19:19 PM PDT 24
Peak memory 219980 kb
Host smart-3f7c380e-e0fe-41fc-9e61-7ef6a8ef7864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841189375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.2841189375
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.2210032918
Short name T659
Test name
Test status
Simulation time 48707661 ps
CPU time 1.13 seconds
Started Jul 17 07:19:00 PM PDT 24
Finished Jul 17 07:19:23 PM PDT 24
Peak memory 217588 kb
Host smart-16b09102-3352-409f-a4b7-19b8e10defc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210032918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2210032918
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.119323693
Short name T695
Test name
Test status
Simulation time 697886598 ps
CPU time 5.43 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:14 PM PDT 24
Peak memory 220612 kb
Host smart-f92f0e17-acff-4e25-ab19-2682204a5d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119323693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.119323693
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.2494132129
Short name T883
Test name
Test status
Simulation time 59147539 ps
CPU time 1.35 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:14 PM PDT 24
Peak memory 220200 kb
Host smart-ba9a2c57-a3b8-4bb0-8377-9e07caa567d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494132129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.2494132129
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.2488105411
Short name T826
Test name
Test status
Simulation time 66665367 ps
CPU time 1.58 seconds
Started Jul 17 07:18:58 PM PDT 24
Finished Jul 17 07:19:20 PM PDT 24
Peak memory 218800 kb
Host smart-2102f6f5-1e2e-4ec2-8e3e-fcd60c40525e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488105411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.2488105411
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.3641504864
Short name T968
Test name
Test status
Simulation time 29880403 ps
CPU time 1.2 seconds
Started Jul 17 07:18:59 PM PDT 24
Finished Jul 17 07:19:20 PM PDT 24
Peak memory 217756 kb
Host smart-84f0821d-b34c-4a97-8ba3-329fd271d471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641504864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.3641504864
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.1582935066
Short name T848
Test name
Test status
Simulation time 162176676 ps
CPU time 1.02 seconds
Started Jul 17 07:19:05 PM PDT 24
Finished Jul 17 07:19:30 PM PDT 24
Peak memory 217392 kb
Host smart-ea763d8d-6afc-48a2-9bc4-d9b28e4ef25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582935066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.1582935066
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.2161262344
Short name T715
Test name
Test status
Simulation time 64891637 ps
CPU time 1.05 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:15:17 PM PDT 24
Peak memory 220040 kb
Host smart-b4535e1c-9356-473f-88a6-7330728ad580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161262344 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.2161262344
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.2142646631
Short name T24
Test name
Test status
Simulation time 35005979 ps
CPU time 0.97 seconds
Started Jul 17 07:15:02 PM PDT 24
Finished Jul 17 07:15:18 PM PDT 24
Peak memory 215464 kb
Host smart-b577df48-fdf9-4714-b058-bb50cb1fea90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142646631 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.2142646631
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.1426015156
Short name T656
Test name
Test status
Simulation time 16508920 ps
CPU time 0.91 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:15:17 PM PDT 24
Peak memory 216656 kb
Host smart-2aa2d86c-3264-45d7-9a7a-0f2b8fc99be3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426015156 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1426015156
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.3754172328
Short name T897
Test name
Test status
Simulation time 81461626 ps
CPU time 1.12 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:15:16 PM PDT 24
Peak memory 220056 kb
Host smart-aa6de070-4805-4638-9231-3e18131f4b2b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754172328 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.3754172328
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.3681253821
Short name T145
Test name
Test status
Simulation time 19039101 ps
CPU time 1.08 seconds
Started Jul 17 07:15:02 PM PDT 24
Finished Jul 17 07:15:18 PM PDT 24
Peak memory 215792 kb
Host smart-5651f35a-4efb-48ac-8810-952bba8e8145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681253821 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.3681253821
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.2496645213
Short name T380
Test name
Test status
Simulation time 31122555 ps
CPU time 1.23 seconds
Started Jul 17 07:15:02 PM PDT 24
Finished Jul 17 07:15:19 PM PDT 24
Peak memory 217392 kb
Host smart-2d8a6dcb-1f2b-47b9-8d45-405c7446f002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496645213 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.2496645213
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.1498498222
Short name T481
Test name
Test status
Simulation time 22177087 ps
CPU time 1.14 seconds
Started Jul 17 07:15:02 PM PDT 24
Finished Jul 17 07:15:18 PM PDT 24
Peak memory 215736 kb
Host smart-a8d4374b-3ebd-4512-9e36-afab8eda9f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498498222 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.1498498222
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.721880050
Short name T741
Test name
Test status
Simulation time 58292057 ps
CPU time 0.95 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:15:15 PM PDT 24
Peak memory 215524 kb
Host smart-a8072881-12b9-4278-ba5c-7029d401eadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721880050 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.721880050
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.2406632775
Short name T492
Test name
Test status
Simulation time 481571959 ps
CPU time 5.04 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:15:20 PM PDT 24
Peak memory 215564 kb
Host smart-e141ee71-413e-4eab-b62b-cb78be36e832
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406632775 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2406632775
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/240.edn_genbits.4229074081
Short name T547
Test name
Test status
Simulation time 48535503 ps
CPU time 1.54 seconds
Started Jul 17 07:19:06 PM PDT 24
Finished Jul 17 07:19:32 PM PDT 24
Peak memory 218704 kb
Host smart-f3ad862e-b490-47f6-bf89-2473f686becb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229074081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.4229074081
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.3766551012
Short name T722
Test name
Test status
Simulation time 161865965 ps
CPU time 0.98 seconds
Started Jul 17 07:19:03 PM PDT 24
Finished Jul 17 07:19:28 PM PDT 24
Peak memory 217528 kb
Host smart-35a26916-5246-4b70-a83b-d5c0ad3f5a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766551012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.3766551012
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.2063353711
Short name T599
Test name
Test status
Simulation time 19051443 ps
CPU time 1.14 seconds
Started Jul 17 07:18:51 PM PDT 24
Finished Jul 17 07:18:54 PM PDT 24
Peak memory 218924 kb
Host smart-e077d2d3-d6bc-4285-81b7-ffd423277c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063353711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.2063353711
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.2718217829
Short name T489
Test name
Test status
Simulation time 46813021 ps
CPU time 1.72 seconds
Started Jul 17 07:19:06 PM PDT 24
Finished Jul 17 07:19:32 PM PDT 24
Peak memory 218828 kb
Host smart-a8370bfa-68de-4594-8c6f-a41e7062bc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718217829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.2718217829
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.1295385175
Short name T951
Test name
Test status
Simulation time 102672242 ps
CPU time 1.34 seconds
Started Jul 17 07:19:01 PM PDT 24
Finished Jul 17 07:19:24 PM PDT 24
Peak memory 220484 kb
Host smart-33fc0b22-a6bc-4a05-9658-b9ccbd1066a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295385175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.1295385175
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.2383696785
Short name T526
Test name
Test status
Simulation time 35141784 ps
CPU time 1.41 seconds
Started Jul 17 07:19:06 PM PDT 24
Finished Jul 17 07:19:32 PM PDT 24
Peak memory 220164 kb
Host smart-7dde0db4-d9c1-46a8-bbd8-16ab6b2f29e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383696785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.2383696785
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.434948614
Short name T653
Test name
Test status
Simulation time 42177908 ps
CPU time 1.24 seconds
Started Jul 17 07:19:01 PM PDT 24
Finished Jul 17 07:19:26 PM PDT 24
Peak memory 219108 kb
Host smart-48b0e856-5662-4c84-9bf4-5d1804162448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434948614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.434948614
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.1749493810
Short name T456
Test name
Test status
Simulation time 58952534 ps
CPU time 1.43 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:18 PM PDT 24
Peak memory 218824 kb
Host smart-c2dd8186-7a5f-4f70-a76d-c3a5573c943b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749493810 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1749493810
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.2698432103
Short name T44
Test name
Test status
Simulation time 48075902 ps
CPU time 1.68 seconds
Started Jul 17 07:19:01 PM PDT 24
Finished Jul 17 07:19:24 PM PDT 24
Peak memory 218912 kb
Host smart-b7d75e96-ed9d-4dd1-bb33-aef5b0216de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698432103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.2698432103
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.3189071202
Short name T710
Test name
Test status
Simulation time 70953561 ps
CPU time 1.1 seconds
Started Jul 17 07:19:01 PM PDT 24
Finished Jul 17 07:19:23 PM PDT 24
Peak memory 218980 kb
Host smart-f27674ef-2656-4f9c-9807-ffdfcbe89ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189071202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.3189071202
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.786491964
Short name T228
Test name
Test status
Simulation time 34999514 ps
CPU time 1.3 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:15:18 PM PDT 24
Peak memory 220004 kb
Host smart-a0239160-7ece-4a8f-8e33-822fb04fe882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786491964 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.786491964
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.3447686927
Short name T964
Test name
Test status
Simulation time 46613071 ps
CPU time 0.86 seconds
Started Jul 17 07:15:05 PM PDT 24
Finished Jul 17 07:15:23 PM PDT 24
Peak memory 207040 kb
Host smart-211efa56-3450-47ba-9b80-6dea7f63d9ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447686927 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3447686927
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.3981886666
Short name T67
Test name
Test status
Simulation time 10662440 ps
CPU time 0.89 seconds
Started Jul 17 07:15:04 PM PDT 24
Finished Jul 17 07:15:21 PM PDT 24
Peak memory 216348 kb
Host smart-9670f40f-e83f-44fa-80eb-c2c83b593187
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981886666 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.3981886666
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.4270046791
Short name T128
Test name
Test status
Simulation time 124363274 ps
CPU time 1.13 seconds
Started Jul 17 07:15:06 PM PDT 24
Finished Jul 17 07:15:23 PM PDT 24
Peak memory 217172 kb
Host smart-dd467c8e-0798-4fe4-ad4c-0bb0c4200eae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270046791 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.4270046791
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.2277805685
Short name T789
Test name
Test status
Simulation time 19435491 ps
CPU time 1.22 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:15:18 PM PDT 24
Peak memory 224124 kb
Host smart-a6905f8f-051e-4ad0-b1e2-47b6cb5c40d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277805685 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.2277805685
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.4084567932
Short name T426
Test name
Test status
Simulation time 261790434 ps
CPU time 3.8 seconds
Started Jul 17 07:15:03 PM PDT 24
Finished Jul 17 07:15:23 PM PDT 24
Peak memory 220188 kb
Host smart-3c3f9dc1-cdf6-4508-a7d3-5ba036af5e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084567932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.4084567932
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.1690224035
Short name T405
Test name
Test status
Simulation time 22879606 ps
CPU time 1.19 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:15:17 PM PDT 24
Peak memory 224312 kb
Host smart-28f16130-372c-42c3-8a3c-d60019be9800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690224035 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.1690224035
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.30546935
Short name T908
Test name
Test status
Simulation time 52557413 ps
CPU time 1 seconds
Started Jul 17 07:15:03 PM PDT 24
Finished Jul 17 07:15:19 PM PDT 24
Peak memory 215528 kb
Host smart-fe3aabdc-589c-42e7-ad6d-44285b6cc216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30546935 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.30546935
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.1203937947
Short name T662
Test name
Test status
Simulation time 199208201 ps
CPU time 3.95 seconds
Started Jul 17 07:15:04 PM PDT 24
Finished Jul 17 07:15:24 PM PDT 24
Peak memory 217544 kb
Host smart-ac16ca3c-c321-4cb5-8ac5-a92860cdb53f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203937947 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1203937947
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.2004256662
Short name T210
Test name
Test status
Simulation time 124485687866 ps
CPU time 1427.03 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:39:04 PM PDT 24
Peak memory 223232 kb
Host smart-2ce5c72b-a9b2-4779-b35e-169aaedb5c6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004256662 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.2004256662
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.3264061718
Short name T934
Test name
Test status
Simulation time 40436807 ps
CPU time 1.28 seconds
Started Jul 17 07:19:08 PM PDT 24
Finished Jul 17 07:19:33 PM PDT 24
Peak memory 218728 kb
Host smart-ffb9b4b3-1c31-4637-b802-ff70fe5a8a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264061718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3264061718
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.1721123956
Short name T64
Test name
Test status
Simulation time 156818734 ps
CPU time 1.34 seconds
Started Jul 17 07:19:00 PM PDT 24
Finished Jul 17 07:19:23 PM PDT 24
Peak memory 220096 kb
Host smart-775b9e1e-f926-4097-b30f-b201748f4a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721123956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.1721123956
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2559920363
Short name T523
Test name
Test status
Simulation time 31683140 ps
CPU time 1.39 seconds
Started Jul 17 07:19:09 PM PDT 24
Finished Jul 17 07:19:34 PM PDT 24
Peak memory 218824 kb
Host smart-0b8c640e-fc5b-47cb-8a48-df5e6efb0ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559920363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2559920363
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.3388577162
Short name T784
Test name
Test status
Simulation time 2306994723 ps
CPU time 69.96 seconds
Started Jul 17 07:19:09 PM PDT 24
Finished Jul 17 07:20:42 PM PDT 24
Peak memory 220736 kb
Host smart-312cdf2e-e7a2-4a0f-802e-6981020c5dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388577162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.3388577162
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.3396882144
Short name T676
Test name
Test status
Simulation time 32369805 ps
CPU time 1.33 seconds
Started Jul 17 07:19:08 PM PDT 24
Finished Jul 17 07:19:33 PM PDT 24
Peak memory 218768 kb
Host smart-d9a629f9-2660-4484-98bd-34168b27ca4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396882144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.3396882144
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.1029102505
Short name T373
Test name
Test status
Simulation time 242526027 ps
CPU time 2.93 seconds
Started Jul 17 07:19:01 PM PDT 24
Finished Jul 17 07:19:25 PM PDT 24
Peak memory 219388 kb
Host smart-432faf36-e5ab-463c-9946-2b519f7d65b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029102505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.1029102505
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.502769626
Short name T417
Test name
Test status
Simulation time 85693810 ps
CPU time 1.15 seconds
Started Jul 17 07:19:00 PM PDT 24
Finished Jul 17 07:19:23 PM PDT 24
Peak memory 217444 kb
Host smart-674803f9-5d35-45ca-8468-0c389dd3d473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502769626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.502769626
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.2397954730
Short name T853
Test name
Test status
Simulation time 151970678 ps
CPU time 1.43 seconds
Started Jul 17 07:19:07 PM PDT 24
Finished Jul 17 07:19:33 PM PDT 24
Peak memory 219064 kb
Host smart-a10f201d-55de-4079-acda-34f571a41a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397954730 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.2397954730
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.2304105677
Short name T905
Test name
Test status
Simulation time 38033058 ps
CPU time 1.08 seconds
Started Jul 17 07:19:16 PM PDT 24
Finished Jul 17 07:19:36 PM PDT 24
Peak memory 217636 kb
Host smart-bec7d64d-f7e4-448f-afea-6689f2bb5b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304105677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.2304105677
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.548246038
Short name T641
Test name
Test status
Simulation time 33416899 ps
CPU time 1.36 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:19 PM PDT 24
Peak memory 218588 kb
Host smart-ce839ce8-0bd6-467f-a019-21e49c5f64d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548246038 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.548246038
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.2821112194
Short name T797
Test name
Test status
Simulation time 60990361 ps
CPU time 1.15 seconds
Started Jul 17 07:15:04 PM PDT 24
Finished Jul 17 07:15:21 PM PDT 24
Peak memory 219724 kb
Host smart-84410542-8a58-409c-9cce-e7324ce4ef11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821112194 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.2821112194
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.3988324260
Short name T580
Test name
Test status
Simulation time 18185925 ps
CPU time 0.86 seconds
Started Jul 17 07:15:04 PM PDT 24
Finished Jul 17 07:15:21 PM PDT 24
Peak memory 206816 kb
Host smart-7e24d8e6-8aaf-4e8b-b22d-a73276946368
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988324260 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.3988324260
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.1764687983
Short name T475
Test name
Test status
Simulation time 19713983 ps
CPU time 0.81 seconds
Started Jul 17 07:15:03 PM PDT 24
Finished Jul 17 07:15:21 PM PDT 24
Peak memory 216508 kb
Host smart-7d8b1246-fb6e-4bc1-8880-a2ea000f8645
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764687983 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1764687983
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_err.4088015309
Short name T447
Test name
Test status
Simulation time 107145017 ps
CPU time 0.82 seconds
Started Jul 17 07:15:04 PM PDT 24
Finished Jul 17 07:15:21 PM PDT 24
Peak memory 218680 kb
Host smart-4c7a03dc-97c4-4e1d-932e-53d400c178c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088015309 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.4088015309
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.2364889120
Short name T19
Test name
Test status
Simulation time 89072192 ps
CPU time 1.19 seconds
Started Jul 17 07:15:04 PM PDT 24
Finished Jul 17 07:15:21 PM PDT 24
Peak memory 218832 kb
Host smart-f998ceec-c2f1-4ae8-98f0-1c941851e63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364889120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.2364889120
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_smoke.1428339134
Short name T707
Test name
Test status
Simulation time 18767090 ps
CPU time 0.96 seconds
Started Jul 17 07:15:04 PM PDT 24
Finished Jul 17 07:15:21 PM PDT 24
Peak memory 215584 kb
Host smart-eefd74fd-fc3a-475d-9eb2-6bc2ad14ef3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428339134 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.1428339134
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.2057283526
Short name T386
Test name
Test status
Simulation time 88338095 ps
CPU time 2.39 seconds
Started Jul 17 07:15:04 PM PDT 24
Finished Jul 17 07:15:23 PM PDT 24
Peak memory 217316 kb
Host smart-7bcd0efb-bab2-4264-8a17-c70f2d66c0b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057283526 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.2057283526
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1485837622
Short name T914
Test name
Test status
Simulation time 33837641265 ps
CPU time 855.16 seconds
Started Jul 17 07:15:05 PM PDT 24
Finished Jul 17 07:29:36 PM PDT 24
Peak memory 224024 kb
Host smart-4b34aef4-ef1f-4ada-9fdd-7a6a32924a9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485837622 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1485837622
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.2391256502
Short name T768
Test name
Test status
Simulation time 33573728 ps
CPU time 1.5 seconds
Started Jul 17 07:19:07 PM PDT 24
Finished Jul 17 07:19:33 PM PDT 24
Peak memory 217680 kb
Host smart-22350dca-fd67-44e3-9629-c21ef8feb2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391256502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.2391256502
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.2670190812
Short name T647
Test name
Test status
Simulation time 87078103 ps
CPU time 1.4 seconds
Started Jul 17 07:19:08 PM PDT 24
Finished Jul 17 07:19:33 PM PDT 24
Peak memory 217308 kb
Host smart-b427f63a-5d81-4656-9dce-745bde8da89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670190812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.2670190812
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.1184757823
Short name T384
Test name
Test status
Simulation time 44516832 ps
CPU time 1.43 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:10 PM PDT 24
Peak memory 219116 kb
Host smart-9b84c93b-dfa7-4bab-ac87-24784d86603d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184757823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.1184757823
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.2064614233
Short name T725
Test name
Test status
Simulation time 45698667 ps
CPU time 1.2 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:14 PM PDT 24
Peak memory 219960 kb
Host smart-9141becd-6dc3-4029-a4f7-6350e81bc30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064614233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.2064614233
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.450583827
Short name T312
Test name
Test status
Simulation time 47894218 ps
CPU time 1.64 seconds
Started Jul 17 07:18:58 PM PDT 24
Finished Jul 17 07:19:19 PM PDT 24
Peak memory 218844 kb
Host smart-956e5949-7deb-45f5-861e-80b4264fc52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450583827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.450583827
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.1911754510
Short name T623
Test name
Test status
Simulation time 190856319 ps
CPU time 1.13 seconds
Started Jul 17 07:18:58 PM PDT 24
Finished Jul 17 07:19:19 PM PDT 24
Peak memory 217472 kb
Host smart-c1e48a67-4873-48b2-a5f7-f25eb8405761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911754510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.1911754510
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.1657686602
Short name T529
Test name
Test status
Simulation time 109922477 ps
CPU time 1.03 seconds
Started Jul 17 07:18:54 PM PDT 24
Finished Jul 17 07:19:02 PM PDT 24
Peak memory 217500 kb
Host smart-62985bc9-2cc3-478b-bdda-09f94e784525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657686602 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.1657686602
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.815913252
Short name T683
Test name
Test status
Simulation time 50563061 ps
CPU time 1.79 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:18 PM PDT 24
Peak memory 218732 kb
Host smart-86b3cb2b-7454-4d55-af47-45d56b69971e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815913252 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.815913252
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.3954218754
Short name T500
Test name
Test status
Simulation time 94996717 ps
CPU time 1.39 seconds
Started Jul 17 07:18:53 PM PDT 24
Finished Jul 17 07:18:58 PM PDT 24
Peak memory 218900 kb
Host smart-fb8291ab-0793-4738-a5ae-d9f693cd8c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954218754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3954218754
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.2866136248
Short name T174
Test name
Test status
Simulation time 26915075 ps
CPU time 1.25 seconds
Started Jul 17 07:14:58 PM PDT 24
Finished Jul 17 07:15:07 PM PDT 24
Peak memory 221320 kb
Host smart-d7aeb99b-dc2d-4f5e-8cb6-24eeeb643305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866136248 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.2866136248
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.3989792087
Short name T603
Test name
Test status
Simulation time 47776280 ps
CPU time 1.05 seconds
Started Jul 17 07:14:59 PM PDT 24
Finished Jul 17 07:15:11 PM PDT 24
Peak memory 207216 kb
Host smart-99a7eb09-a854-4821-b4e6-8c01472ca335
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989792087 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.3989792087
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.1531543082
Short name T530
Test name
Test status
Simulation time 136661384 ps
CPU time 0.87 seconds
Started Jul 17 07:14:58 PM PDT 24
Finished Jul 17 07:15:06 PM PDT 24
Peak memory 216228 kb
Host smart-f4fa85e1-650e-4a1a-a999-67775fe3dd36
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531543082 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.1531543082
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.2894978167
Short name T854
Test name
Test status
Simulation time 34347307 ps
CPU time 1.22 seconds
Started Jul 17 07:14:58 PM PDT 24
Finished Jul 17 07:15:10 PM PDT 24
Peak memory 217316 kb
Host smart-ee92bda2-1af5-4ba4-a8c9-563518b32350
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894978167 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.2894978167
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.3642570119
Short name T117
Test name
Test status
Simulation time 21295667 ps
CPU time 1.06 seconds
Started Jul 17 07:14:59 PM PDT 24
Finished Jul 17 07:15:11 PM PDT 24
Peak memory 220000 kb
Host smart-5c691f8f-7468-4fb8-a648-1a8ade263a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642570119 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.3642570119
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.788772534
Short name T686
Test name
Test status
Simulation time 51297317 ps
CPU time 1.5 seconds
Started Jul 17 07:14:59 PM PDT 24
Finished Jul 17 07:15:10 PM PDT 24
Peak memory 218932 kb
Host smart-0d83f7e3-45b3-447f-80eb-92c07d166c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788772534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.788772534
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.1228375111
Short name T16
Test name
Test status
Simulation time 21341369 ps
CPU time 1.23 seconds
Started Jul 17 07:14:56 PM PDT 24
Finished Jul 17 07:15:02 PM PDT 24
Peak memory 224344 kb
Host smart-c46b5463-1aa0-414a-a2ad-8240f5f9f214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228375111 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.1228375111
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.3570603262
Short name T961
Test name
Test status
Simulation time 29783049 ps
CPU time 0.9 seconds
Started Jul 17 07:15:04 PM PDT 24
Finished Jul 17 07:15:21 PM PDT 24
Peak memory 215584 kb
Host smart-f62c2f4f-3565-4dd4-bb2e-3434fef6c949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570603262 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.3570603262
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.4221768801
Short name T280
Test name
Test status
Simulation time 196718560 ps
CPU time 3.48 seconds
Started Jul 17 07:14:59 PM PDT 24
Finished Jul 17 07:15:12 PM PDT 24
Peak memory 215508 kb
Host smart-70412c31-d270-4982-89ef-6f0881550c77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221768801 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.4221768801
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.235518610
Short name T578
Test name
Test status
Simulation time 31484140273 ps
CPU time 703.79 seconds
Started Jul 17 07:14:59 PM PDT 24
Finished Jul 17 07:26:52 PM PDT 24
Peak memory 218564 kb
Host smart-e9e71cec-d6e5-414a-beaf-e5cb1bccbc8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235518610 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.235518610
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.571870206
Short name T261
Test name
Test status
Simulation time 36552606 ps
CPU time 1.32 seconds
Started Jul 17 07:18:54 PM PDT 24
Finished Jul 17 07:19:01 PM PDT 24
Peak memory 218716 kb
Host smart-b5d1fb08-7967-4cb5-9692-de83af994fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571870206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.571870206
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.4044058363
Short name T666
Test name
Test status
Simulation time 43491923 ps
CPU time 1.08 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:10 PM PDT 24
Peak memory 217516 kb
Host smart-7ebe0032-106e-4e19-babd-cda8465910f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044058363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.4044058363
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.3847948874
Short name T305
Test name
Test status
Simulation time 63554477 ps
CPU time 1 seconds
Started Jul 17 07:19:00 PM PDT 24
Finished Jul 17 07:19:23 PM PDT 24
Peak memory 217472 kb
Host smart-33f72d8a-5e85-4b52-bc77-d12fc0739228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847948874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.3847948874
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.2015491470
Short name T571
Test name
Test status
Simulation time 41366724 ps
CPU time 1.04 seconds
Started Jul 17 07:18:58 PM PDT 24
Finished Jul 17 07:19:19 PM PDT 24
Peak memory 215556 kb
Host smart-27d3ec3b-5dd8-446d-84cb-b84dc5c00865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015491470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.2015491470
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.979933352
Short name T827
Test name
Test status
Simulation time 106850332 ps
CPU time 1.05 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:17 PM PDT 24
Peak memory 217472 kb
Host smart-69d17b87-4e18-42aa-9d3d-e90de1a56826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979933352 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.979933352
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3236340596
Short name T926
Test name
Test status
Simulation time 38797917 ps
CPU time 1.2 seconds
Started Jul 17 07:19:02 PM PDT 24
Finished Jul 17 07:19:26 PM PDT 24
Peak memory 218744 kb
Host smart-1180edd0-6805-4deb-a1b5-352916210a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236340596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3236340596
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.1983711193
Short name T311
Test name
Test status
Simulation time 261195518 ps
CPU time 1.22 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:10 PM PDT 24
Peak memory 217568 kb
Host smart-a81e600e-6e1a-4b53-ba87-b4ed4f68139e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983711193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.1983711193
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.379315503
Short name T776
Test name
Test status
Simulation time 32707977 ps
CPU time 1.25 seconds
Started Jul 17 07:18:51 PM PDT 24
Finished Jul 17 07:18:55 PM PDT 24
Peak memory 220200 kb
Host smart-c6a96519-f024-4f22-b4b9-72f6c6071657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379315503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.379315503
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.2182041596
Short name T769
Test name
Test status
Simulation time 134802468 ps
CPU time 1.28 seconds
Started Jul 17 07:19:01 PM PDT 24
Finished Jul 17 07:19:26 PM PDT 24
Peak memory 219204 kb
Host smart-d3a73653-4991-4406-a963-bd047365546d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182041596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.2182041596
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.846806629
Short name T909
Test name
Test status
Simulation time 51987523 ps
CPU time 1.21 seconds
Started Jul 17 07:14:57 PM PDT 24
Finished Jul 17 07:15:04 PM PDT 24
Peak memory 220004 kb
Host smart-f9b31da9-e7d8-4d1b-9037-f1d6e851e5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846806629 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.846806629
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.4034831588
Short name T317
Test name
Test status
Simulation time 14071070 ps
CPU time 0.86 seconds
Started Jul 17 07:14:57 PM PDT 24
Finished Jul 17 07:15:06 PM PDT 24
Peak memory 207008 kb
Host smart-f57e4a02-b163-4325-b377-6076b3c166db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034831588 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.4034831588
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.978129662
Short name T162
Test name
Test status
Simulation time 38398156 ps
CPU time 0.78 seconds
Started Jul 17 07:15:00 PM PDT 24
Finished Jul 17 07:15:13 PM PDT 24
Peak memory 216520 kb
Host smart-24199e44-149c-4ace-977f-4c5eb8736158
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978129662 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.978129662
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.3073923018
Short name T103
Test name
Test status
Simulation time 154691208 ps
CPU time 1.05 seconds
Started Jul 17 07:14:57 PM PDT 24
Finished Jul 17 07:15:05 PM PDT 24
Peak memory 217200 kb
Host smart-39b315a5-4129-4a20-b4d6-2cd7c4248da2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073923018 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.3073923018
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.2016388312
Short name T52
Test name
Test status
Simulation time 25898619 ps
CPU time 0.93 seconds
Started Jul 17 07:14:59 PM PDT 24
Finished Jul 17 07:15:11 PM PDT 24
Peak memory 224104 kb
Host smart-1fb1bd81-5d6b-41af-acc5-4fd2eca5c72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016388312 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2016388312
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.1550075268
Short name T893
Test name
Test status
Simulation time 34198463 ps
CPU time 1.38 seconds
Started Jul 17 07:15:00 PM PDT 24
Finished Jul 17 07:15:13 PM PDT 24
Peak memory 218816 kb
Host smart-019e46a6-8a46-4068-87e7-32c3debf0057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550075268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.1550075268
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.674618567
Short name T742
Test name
Test status
Simulation time 22524320 ps
CPU time 1.05 seconds
Started Jul 17 07:14:56 PM PDT 24
Finished Jul 17 07:15:00 PM PDT 24
Peak memory 215856 kb
Host smart-2511fb69-d841-490f-8809-d8b78d48accf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674618567 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.674618567
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.3748072984
Short name T346
Test name
Test status
Simulation time 17548779 ps
CPU time 0.95 seconds
Started Jul 17 07:14:57 PM PDT 24
Finished Jul 17 07:15:05 PM PDT 24
Peak memory 215552 kb
Host smart-5942d609-845a-4e3d-a435-523b171ad0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748072984 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.3748072984
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.238565173
Short name T811
Test name
Test status
Simulation time 493476453 ps
CPU time 3.85 seconds
Started Jul 17 07:14:56 PM PDT 24
Finished Jul 17 07:15:04 PM PDT 24
Peak memory 217316 kb
Host smart-3a0399a7-2a52-446b-9a77-b01aa89b1777
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238565173 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.238565173
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.2526283238
Short name T392
Test name
Test status
Simulation time 183288535650 ps
CPU time 1082.88 seconds
Started Jul 17 07:14:59 PM PDT 24
Finished Jul 17 07:33:14 PM PDT 24
Peak memory 223388 kb
Host smart-5c1137fe-5208-4568-b14b-d76c6bc05048
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526283238 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.2526283238
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.3527365871
Short name T687
Test name
Test status
Simulation time 54940477 ps
CPU time 1.5 seconds
Started Jul 17 07:18:59 PM PDT 24
Finished Jul 17 07:19:21 PM PDT 24
Peak memory 219128 kb
Host smart-42b3c919-c81c-486a-b609-6e98c1e37a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527365871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.3527365871
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.447296721
Short name T756
Test name
Test status
Simulation time 657506028 ps
CPU time 6.08 seconds
Started Jul 17 07:19:01 PM PDT 24
Finished Jul 17 07:19:28 PM PDT 24
Peak memory 220556 kb
Host smart-a40e38ba-8d7f-4460-a6fd-918b5c367dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447296721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.447296721
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.10513027
Short name T318
Test name
Test status
Simulation time 78301609 ps
CPU time 1.03 seconds
Started Jul 17 07:19:05 PM PDT 24
Finished Jul 17 07:19:30 PM PDT 24
Peak memory 217516 kb
Host smart-34850764-713a-41d3-86aa-6210ac29efb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10513027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.10513027
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.1683822367
Short name T364
Test name
Test status
Simulation time 50570757 ps
CPU time 1.3 seconds
Started Jul 17 07:19:03 PM PDT 24
Finished Jul 17 07:19:28 PM PDT 24
Peak memory 217536 kb
Host smart-67d9cd34-c0ef-4662-a14b-1b215e89f7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683822367 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.1683822367
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.2627474337
Short name T976
Test name
Test status
Simulation time 59380371 ps
CPU time 1.36 seconds
Started Jul 17 07:18:58 PM PDT 24
Finished Jul 17 07:19:20 PM PDT 24
Peak memory 218792 kb
Host smart-6d0628ba-2ba2-4de3-9554-eb079813495d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627474337 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2627474337
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.2129422806
Short name T345
Test name
Test status
Simulation time 42118532 ps
CPU time 1.18 seconds
Started Jul 17 07:19:00 PM PDT 24
Finished Jul 17 07:19:22 PM PDT 24
Peak memory 219368 kb
Host smart-a01185d1-ed46-41a7-b2e6-855273123fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129422806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.2129422806
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.3392386881
Short name T459
Test name
Test status
Simulation time 171421012 ps
CPU time 1.12 seconds
Started Jul 17 07:19:02 PM PDT 24
Finished Jul 17 07:19:26 PM PDT 24
Peak memory 217640 kb
Host smart-c3e321b2-530c-42d7-b4b8-60919f85edb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392386881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.3392386881
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.405685144
Short name T286
Test name
Test status
Simulation time 36997121 ps
CPU time 1.41 seconds
Started Jul 17 07:19:05 PM PDT 24
Finished Jul 17 07:19:32 PM PDT 24
Peak memory 218904 kb
Host smart-c5557490-1cd0-4194-ac91-d8fd6ea6f939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405685144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.405685144
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.1543411079
Short name T986
Test name
Test status
Simulation time 47989333 ps
CPU time 1.87 seconds
Started Jul 17 07:19:01 PM PDT 24
Finished Jul 17 07:19:27 PM PDT 24
Peak memory 220528 kb
Host smart-3ee50646-89ca-4f6b-b91c-eeef71d8a78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543411079 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.1543411079
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.1509338702
Short name T441
Test name
Test status
Simulation time 107551308 ps
CPU time 1.18 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:14 PM PDT 24
Peak memory 218612 kb
Host smart-62c9a178-e0ec-4dd6-8cd4-0fbeb56897c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509338702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1509338702
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.1440606760
Short name T917
Test name
Test status
Simulation time 86341647 ps
CPU time 1.17 seconds
Started Jul 17 07:15:02 PM PDT 24
Finished Jul 17 07:15:17 PM PDT 24
Peak memory 218912 kb
Host smart-80ef9699-395a-4ee9-a305-774c5f7e0376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440606760 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1440606760
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.3954890571
Short name T825
Test name
Test status
Simulation time 25522823 ps
CPU time 0.92 seconds
Started Jul 17 07:15:03 PM PDT 24
Finished Jul 17 07:15:19 PM PDT 24
Peak memory 207028 kb
Host smart-acaee5e3-645d-4681-816e-106967d51db7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954890571 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3954890571
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.1231705298
Short name T192
Test name
Test status
Simulation time 34020435 ps
CPU time 0.87 seconds
Started Jul 17 07:15:02 PM PDT 24
Finished Jul 17 07:15:18 PM PDT 24
Peak memory 216568 kb
Host smart-34751aff-e88e-4167-b4ae-e79a61075c30
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231705298 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1231705298
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.1214621383
Short name T194
Test name
Test status
Simulation time 54902737 ps
CPU time 1.18 seconds
Started Jul 17 07:15:02 PM PDT 24
Finished Jul 17 07:15:18 PM PDT 24
Peak memory 217220 kb
Host smart-c183eeca-9b8c-4ae7-8b50-cdd3ee11a694
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214621383 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.1214621383
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.1205963215
Short name T150
Test name
Test status
Simulation time 19418091 ps
CPU time 1.03 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:15:17 PM PDT 24
Peak memory 218548 kb
Host smart-e1b32891-51e3-4ed4-baf1-1b391d85348e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205963215 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.1205963215
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.891498810
Short name T588
Test name
Test status
Simulation time 54376235 ps
CPU time 1.28 seconds
Started Jul 17 07:15:00 PM PDT 24
Finished Jul 17 07:15:14 PM PDT 24
Peak memory 218900 kb
Host smart-6a8f4086-f6ff-479a-858a-c2f885ae2a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891498810 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.891498810
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.2394384159
Short name T630
Test name
Test status
Simulation time 28451471 ps
CPU time 0.92 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:15:17 PM PDT 24
Peak memory 215728 kb
Host smart-3103e8a1-98b3-4f11-b73a-658a8ba4c944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394384159 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2394384159
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.4013210212
Short name T25
Test name
Test status
Simulation time 24865618 ps
CPU time 0.94 seconds
Started Jul 17 07:15:00 PM PDT 24
Finished Jul 17 07:15:13 PM PDT 24
Peak memory 215568 kb
Host smart-0158592e-d27e-4e93-9bd1-01fee0d26be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013210212 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.4013210212
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.984296703
Short name T340
Test name
Test status
Simulation time 327149661 ps
CPU time 3.58 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:15:18 PM PDT 24
Peak memory 217576 kb
Host smart-8fb07fa1-ba99-4bc0-ad20-b979b0d7e2bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984296703 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.984296703
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.957166604
Short name T218
Test name
Test status
Simulation time 22287355333 ps
CPU time 250.03 seconds
Started Jul 17 07:15:02 PM PDT 24
Finished Jul 17 07:19:27 PM PDT 24
Peak memory 219236 kb
Host smart-94230628-99bf-417e-8d66-40ea38400043
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957166604 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.957166604
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.2696017414
Short name T782
Test name
Test status
Simulation time 75481998 ps
CPU time 1.18 seconds
Started Jul 17 07:19:06 PM PDT 24
Finished Jul 17 07:19:32 PM PDT 24
Peak memory 218844 kb
Host smart-14eff130-2e06-430b-87b8-39eaa89c8ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696017414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.2696017414
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.653309388
Short name T649
Test name
Test status
Simulation time 56232663 ps
CPU time 1.72 seconds
Started Jul 17 07:19:05 PM PDT 24
Finished Jul 17 07:19:31 PM PDT 24
Peak memory 218936 kb
Host smart-b74c2147-d154-4956-85e4-e9f63d490c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653309388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.653309388
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.268765454
Short name T367
Test name
Test status
Simulation time 32526743 ps
CPU time 1.24 seconds
Started Jul 17 07:18:59 PM PDT 24
Finished Jul 17 07:19:22 PM PDT 24
Peak memory 217700 kb
Host smart-221dccf9-5b0d-4d2c-93e2-221db8c3bf32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268765454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.268765454
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.4079226087
Short name T74
Test name
Test status
Simulation time 78337528 ps
CPU time 2.94 seconds
Started Jul 17 07:19:08 PM PDT 24
Finished Jul 17 07:19:34 PM PDT 24
Peak memory 220620 kb
Host smart-27f89222-ad93-44f5-9f22-eb00d2cf6f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079226087 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.4079226087
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3040803035
Short name T279
Test name
Test status
Simulation time 51976889 ps
CPU time 1.78 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:19 PM PDT 24
Peak memory 218720 kb
Host smart-6e050989-ad54-4e0e-828e-f894bdab320c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040803035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3040803035
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.2808158387
Short name T324
Test name
Test status
Simulation time 27168571 ps
CPU time 1.2 seconds
Started Jul 17 07:19:01 PM PDT 24
Finished Jul 17 07:19:25 PM PDT 24
Peak memory 218876 kb
Host smart-7e8bef21-6c4f-455d-82f2-227e65b7c85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808158387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.2808158387
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.3611416667
Short name T596
Test name
Test status
Simulation time 66965838 ps
CPU time 1.31 seconds
Started Jul 17 07:19:08 PM PDT 24
Finished Jul 17 07:19:33 PM PDT 24
Peak memory 217280 kb
Host smart-6b8acc17-a9b1-4a10-bd9e-dd8b55a68512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611416667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.3611416667
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.765621030
Short name T490
Test name
Test status
Simulation time 179417958 ps
CPU time 1.18 seconds
Started Jul 17 07:19:09 PM PDT 24
Finished Jul 17 07:19:34 PM PDT 24
Peak memory 217524 kb
Host smart-7604199d-edc6-473c-8ef8-6dff1dc33d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765621030 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.765621030
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.2705014757
Short name T295
Test name
Test status
Simulation time 48936676 ps
CPU time 1.92 seconds
Started Jul 17 07:19:00 PM PDT 24
Finished Jul 17 07:19:23 PM PDT 24
Peak memory 218676 kb
Host smart-c6c966bc-4abb-40e7-af22-ec432b04dcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705014757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.2705014757
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.3314781395
Short name T657
Test name
Test status
Simulation time 21667878 ps
CPU time 1.15 seconds
Started Jul 17 07:14:31 PM PDT 24
Finished Jul 17 07:14:36 PM PDT 24
Peak memory 219064 kb
Host smart-1ad85953-cacb-48b0-82c6-d8f49899814b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314781395 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.3314781395
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.3993622468
Short name T225
Test name
Test status
Simulation time 15366050 ps
CPU time 0.91 seconds
Started Jul 17 07:14:35 PM PDT 24
Finished Jul 17 07:14:41 PM PDT 24
Peak memory 215196 kb
Host smart-43dcbb32-2e7d-453a-8dfd-540f6018028d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993622468 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3993622468
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.2384796784
Short name T172
Test name
Test status
Simulation time 14649558 ps
CPU time 0.92 seconds
Started Jul 17 07:14:35 PM PDT 24
Finished Jul 17 07:14:43 PM PDT 24
Peak memory 216676 kb
Host smart-80a86fc1-9dfe-411b-92e7-6702f702242e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384796784 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.2384796784
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.1099330911
Short name T183
Test name
Test status
Simulation time 42799279 ps
CPU time 1.33 seconds
Started Jul 17 07:14:36 PM PDT 24
Finished Jul 17 07:14:45 PM PDT 24
Peak memory 220048 kb
Host smart-a3c9f456-8a9a-41a7-a84a-61196e4809cf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099330911 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.1099330911
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.4175711232
Short name T857
Test name
Test status
Simulation time 28703115 ps
CPU time 0.96 seconds
Started Jul 17 07:14:32 PM PDT 24
Finished Jul 17 07:14:36 PM PDT 24
Peak memory 219052 kb
Host smart-b306fa4e-f403-451b-a2c6-743bb6f61143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175711232 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.4175711232
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.1768302355
Short name T432
Test name
Test status
Simulation time 47496319 ps
CPU time 1.19 seconds
Started Jul 17 07:14:35 PM PDT 24
Finished Jul 17 07:14:44 PM PDT 24
Peak memory 217640 kb
Host smart-020f96f1-3829-4c79-bc5c-7eb158af1e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768302355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1768302355
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.3810003444
Short name T970
Test name
Test status
Simulation time 22477669 ps
CPU time 1.07 seconds
Started Jul 17 07:14:27 PM PDT 24
Finished Jul 17 07:14:29 PM PDT 24
Peak memory 215840 kb
Host smart-75e9dbea-a1b9-45b6-b831-4dde64e72ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810003444 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.3810003444
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.1900999280
Short name T952
Test name
Test status
Simulation time 20321034 ps
CPU time 0.95 seconds
Started Jul 17 07:14:32 PM PDT 24
Finished Jul 17 07:14:37 PM PDT 24
Peak memory 207360 kb
Host smart-7e5986b5-b689-4710-b1c3-16ade05e0be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900999280 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1900999280
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.1449742087
Short name T17
Test name
Test status
Simulation time 928256683 ps
CPU time 7.84 seconds
Started Jul 17 07:14:36 PM PDT 24
Finished Jul 17 07:14:51 PM PDT 24
Peak memory 236656 kb
Host smart-ead5708a-97c5-4a73-a110-262404aa3711
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449742087 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.1449742087
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.3213811541
Short name T422
Test name
Test status
Simulation time 16269364 ps
CPU time 0.98 seconds
Started Jul 17 07:14:31 PM PDT 24
Finished Jul 17 07:14:36 PM PDT 24
Peak memory 215520 kb
Host smart-1044349c-dd98-4568-9aa8-10fa7f5ab9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213811541 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3213811541
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.3819485450
Short name T619
Test name
Test status
Simulation time 477894902 ps
CPU time 2.77 seconds
Started Jul 17 07:14:36 PM PDT 24
Finished Jul 17 07:14:45 PM PDT 24
Peak memory 217504 kb
Host smart-a19f77a7-18c7-44eb-9f67-eafcf0e2d69a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819485450 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3819485450
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2781335004
Short name T494
Test name
Test status
Simulation time 64481480893 ps
CPU time 359.22 seconds
Started Jul 17 07:14:36 PM PDT 24
Finished Jul 17 07:20:42 PM PDT 24
Peak memory 218076 kb
Host smart-5d986f4c-b127-4a26-a0bb-baf7c5429f5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781335004 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.2781335004
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.3980407221
Short name T506
Test name
Test status
Simulation time 37680674 ps
CPU time 1.14 seconds
Started Jul 17 07:15:03 PM PDT 24
Finished Jul 17 07:15:21 PM PDT 24
Peak memory 219044 kb
Host smart-79d309a7-14f8-4ac5-83af-079f5f0179ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980407221 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.3980407221
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.2712949054
Short name T692
Test name
Test status
Simulation time 22885477 ps
CPU time 1 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:15:15 PM PDT 24
Peak memory 215300 kb
Host smart-3fc7ad20-8ca5-4ae8-b3ce-4fbfe36a1575
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712949054 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.2712949054
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.503242849
Short name T102
Test name
Test status
Simulation time 161685246 ps
CPU time 1.23 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:15:18 PM PDT 24
Peak memory 217248 kb
Host smart-4fbb3ab4-80d6-4527-9e9a-1b49ea1e413c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503242849 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_di
sable_auto_req_mode.503242849
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.2963463035
Short name T105
Test name
Test status
Simulation time 25960403 ps
CPU time 0.99 seconds
Started Jul 17 07:15:04 PM PDT 24
Finished Jul 17 07:15:21 PM PDT 24
Peak memory 220060 kb
Host smart-f0946f7d-aa6d-40ed-8f94-826d8a6b0e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963463035 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.2963463035
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.1112704431
Short name T755
Test name
Test status
Simulation time 59380264 ps
CPU time 1.18 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:15:17 PM PDT 24
Peak memory 220232 kb
Host smart-3d7c5b5c-92fd-4410-aee3-19ea36358308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112704431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1112704431
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.1100423179
Short name T977
Test name
Test status
Simulation time 20898114 ps
CPU time 1.09 seconds
Started Jul 17 07:15:02 PM PDT 24
Finished Jul 17 07:15:18 PM PDT 24
Peak memory 216140 kb
Host smart-d56024c4-986d-4bfa-a56a-4bc3b02d1976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100423179 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.1100423179
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.918886326
Short name T498
Test name
Test status
Simulation time 57969301 ps
CPU time 0.88 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:15:15 PM PDT 24
Peak memory 215532 kb
Host smart-e20f76bc-ca58-46e4-bbca-6f11f104f7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918886326 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.918886326
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.2192641516
Short name T577
Test name
Test status
Simulation time 557592946 ps
CPU time 2.13 seconds
Started Jul 17 07:15:02 PM PDT 24
Finished Jul 17 07:15:20 PM PDT 24
Peak memory 215468 kb
Host smart-93ad63b2-5f12-410b-b94e-f9dee6d1eeef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192641516 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.2192641516
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.1396250923
Short name T395
Test name
Test status
Simulation time 75346460099 ps
CPU time 844.5 seconds
Started Jul 17 07:15:02 PM PDT 24
Finished Jul 17 07:29:22 PM PDT 24
Peak memory 222528 kb
Host smart-ea39bafd-710d-4fc6-9052-50c493388d95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396250923 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.1396250923
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.1289225224
Short name T705
Test name
Test status
Simulation time 27229234 ps
CPU time 1.19 seconds
Started Jul 17 07:15:03 PM PDT 24
Finished Jul 17 07:15:21 PM PDT 24
Peak memory 215992 kb
Host smart-a310be2d-e601-40c0-b031-d7de6d5b99c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289225224 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1289225224
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.362723169
Short name T433
Test name
Test status
Simulation time 25287247 ps
CPU time 0.91 seconds
Started Jul 17 07:15:05 PM PDT 24
Finished Jul 17 07:15:23 PM PDT 24
Peak memory 207080 kb
Host smart-b920e03a-4cf1-46a4-ba78-e3ed68c3b361
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362723169 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.362723169
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.1301631365
Short name T485
Test name
Test status
Simulation time 29125911 ps
CPU time 0.8 seconds
Started Jul 17 07:15:03 PM PDT 24
Finished Jul 17 07:15:20 PM PDT 24
Peak memory 216316 kb
Host smart-6a0f5f12-3ca8-4fc8-90ff-04b6280ebd47
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301631365 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.1301631365
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2920450069
Short name T101
Test name
Test status
Simulation time 83685644 ps
CPU time 1.02 seconds
Started Jul 17 07:15:05 PM PDT 24
Finished Jul 17 07:15:21 PM PDT 24
Peak memory 217224 kb
Host smart-4e70f2f5-8738-49e6-8cbf-3af7f4a9773e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920450069 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2920450069
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.2698469875
Short name T339
Test name
Test status
Simulation time 34608522 ps
CPU time 0.81 seconds
Started Jul 17 07:15:05 PM PDT 24
Finished Jul 17 07:15:22 PM PDT 24
Peak memory 218580 kb
Host smart-f54f91f1-af07-48eb-aba7-d26d2bc8db41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698469875 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.2698469875
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.653281343
Short name T645
Test name
Test status
Simulation time 84311034 ps
CPU time 2.84 seconds
Started Jul 17 07:15:04 PM PDT 24
Finished Jul 17 07:15:23 PM PDT 24
Peak memory 219524 kb
Host smart-c85a441b-0bf3-4e1e-8d82-78ccb159062c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653281343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.653281343
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.219139837
Short name T868
Test name
Test status
Simulation time 27355437 ps
CPU time 0.93 seconds
Started Jul 17 07:15:06 PM PDT 24
Finished Jul 17 07:15:23 PM PDT 24
Peak memory 215760 kb
Host smart-fa0b7fc5-1279-4d52-bbe0-356aee6973ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219139837 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.219139837
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.4269737306
Short name T414
Test name
Test status
Simulation time 15048324 ps
CPU time 0.94 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:15:16 PM PDT 24
Peak memory 215544 kb
Host smart-51c8c829-ceb9-407f-b846-43d9295f2176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269737306 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.4269737306
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.396539918
Short name T550
Test name
Test status
Simulation time 416278522 ps
CPU time 3.4 seconds
Started Jul 17 07:15:03 PM PDT 24
Finished Jul 17 07:15:23 PM PDT 24
Peak memory 217544 kb
Host smart-c81d1eb5-6c9b-446d-980a-d6f6fcddc8d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396539918 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.396539918
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.2446960500
Short name T454
Test name
Test status
Simulation time 465420424489 ps
CPU time 1436.04 seconds
Started Jul 17 07:15:04 PM PDT 24
Finished Jul 17 07:39:16 PM PDT 24
Peak memory 226820 kb
Host smart-720c9b43-af07-4e1c-a4ad-e4a85550b893
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446960500 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.2446960500
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.1395041297
Short name T760
Test name
Test status
Simulation time 45894976 ps
CPU time 1.28 seconds
Started Jul 17 07:14:59 PM PDT 24
Finished Jul 17 07:15:11 PM PDT 24
Peak memory 220068 kb
Host smart-a8304bd5-d505-493c-ac83-265eb8362ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395041297 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.1395041297
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.3609119346
Short name T502
Test name
Test status
Simulation time 13980698 ps
CPU time 0.93 seconds
Started Jul 17 07:14:58 PM PDT 24
Finished Jul 17 07:15:09 PM PDT 24
Peak memory 207040 kb
Host smart-dee95b70-04f3-4ee4-9272-145cf9614f9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609119346 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3609119346
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.3333437063
Short name T573
Test name
Test status
Simulation time 36307697 ps
CPU time 1.2 seconds
Started Jul 17 07:14:59 PM PDT 24
Finished Jul 17 07:15:13 PM PDT 24
Peak memory 218596 kb
Host smart-f01a2546-8542-4c8c-8e5d-c74e2045a1c7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333437063 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.3333437063
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.105162201
Short name T132
Test name
Test status
Simulation time 65976166 ps
CPU time 1.14 seconds
Started Jul 17 07:14:58 PM PDT 24
Finished Jul 17 07:15:06 PM PDT 24
Peak memory 229920 kb
Host smart-e9f77a9d-c9da-4473-a28d-650702a1f624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105162201 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.105162201
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.1345286185
Short name T693
Test name
Test status
Simulation time 45083434 ps
CPU time 1.16 seconds
Started Jul 17 07:14:57 PM PDT 24
Finished Jul 17 07:15:03 PM PDT 24
Peak memory 218728 kb
Host smart-a17fd55c-f54e-4555-9576-0647ccfb1dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345286185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.1345286185
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_smoke.1060360725
Short name T919
Test name
Test status
Simulation time 17404900 ps
CPU time 1.02 seconds
Started Jul 17 07:15:04 PM PDT 24
Finished Jul 17 07:15:21 PM PDT 24
Peak memory 215564 kb
Host smart-27f894ee-9838-4e18-afd5-b08708b86d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060360725 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.1060360725
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.173771804
Short name T608
Test name
Test status
Simulation time 769937628 ps
CPU time 4.75 seconds
Started Jul 17 07:14:57 PM PDT 24
Finished Jul 17 07:15:07 PM PDT 24
Peak memory 217328 kb
Host smart-3fd9b014-0d2a-4f3a-85a8-bda34bca9dc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173771804 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.173771804
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.2827411428
Short name T685
Test name
Test status
Simulation time 229140230642 ps
CPU time 1408.26 seconds
Started Jul 17 07:14:57 PM PDT 24
Finished Jul 17 07:38:30 PM PDT 24
Peak memory 227112 kb
Host smart-eba1ed44-72e7-49e6-95be-ec5cdf55acab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827411428 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.2827411428
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert_test.522115914
Short name T835
Test name
Test status
Simulation time 34040079 ps
CPU time 0.85 seconds
Started Jul 17 07:15:00 PM PDT 24
Finished Jul 17 07:15:15 PM PDT 24
Peak memory 207080 kb
Host smart-659d2b32-0ff8-4495-b011-9d78d95ebe13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522115914 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.522115914
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.180116327
Short name T377
Test name
Test status
Simulation time 21413519 ps
CPU time 0.85 seconds
Started Jul 17 07:14:59 PM PDT 24
Finished Jul 17 07:15:09 PM PDT 24
Peak memory 215652 kb
Host smart-69a5026d-7f0d-421c-a091-3022fb8f92f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180116327 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.180116327
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.653310278
Short name T783
Test name
Test status
Simulation time 95661365 ps
CPU time 1 seconds
Started Jul 17 07:14:58 PM PDT 24
Finished Jul 17 07:15:10 PM PDT 24
Peak memory 218756 kb
Host smart-20c9cc68-1810-4412-b952-68b98e60dc1a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653310278 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_di
sable_auto_req_mode.653310278
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.570973174
Short name T334
Test name
Test status
Simulation time 22562012 ps
CPU time 0.95 seconds
Started Jul 17 07:14:57 PM PDT 24
Finished Jul 17 07:15:04 PM PDT 24
Peak memory 218916 kb
Host smart-d9f38adf-7714-4822-881b-41cc39778bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570973174 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.570973174
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.4083187989
Short name T65
Test name
Test status
Simulation time 125793260 ps
CPU time 2.98 seconds
Started Jul 17 07:14:57 PM PDT 24
Finished Jul 17 07:15:05 PM PDT 24
Peak memory 217772 kb
Host smart-26223883-2dfa-4c3a-aacc-10d29a789596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083187989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.4083187989
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.4131838417
Short name T374
Test name
Test status
Simulation time 24765921 ps
CPU time 1.01 seconds
Started Jul 17 07:14:59 PM PDT 24
Finished Jul 17 07:15:10 PM PDT 24
Peak memory 224364 kb
Host smart-d51c6a77-def4-4791-9c5d-c9acc54a58af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131838417 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.4131838417
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.2032163026
Short name T589
Test name
Test status
Simulation time 18292037 ps
CPU time 0.98 seconds
Started Jul 17 07:15:00 PM PDT 24
Finished Jul 17 07:15:13 PM PDT 24
Peak memory 215556 kb
Host smart-b4ec9d21-ff33-4f1e-a10a-61b81ec92f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032163026 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.2032163026
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.402531585
Short name T813
Test name
Test status
Simulation time 193771357 ps
CPU time 4.1 seconds
Started Jul 17 07:14:56 PM PDT 24
Finished Jul 17 07:15:04 PM PDT 24
Peak memory 218776 kb
Host smart-96c55caf-b6e4-4a7a-80d7-0dc813068300
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402531585 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.402531585
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3830631038
Short name T215
Test name
Test status
Simulation time 574480473486 ps
CPU time 2538.82 seconds
Started Jul 17 07:14:58 PM PDT 24
Finished Jul 17 07:57:28 PM PDT 24
Peak memory 228780 kb
Host smart-b6b8e70e-9f17-46c9-b2f0-604ec0f3bb81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830631038 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3830631038
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.2728320781
Short name T896
Test name
Test status
Simulation time 103844759 ps
CPU time 1.19 seconds
Started Jul 17 07:15:03 PM PDT 24
Finished Jul 17 07:15:21 PM PDT 24
Peak memory 219832 kb
Host smart-64568a3e-ac42-4ee8-87b3-dc9bf3606f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728320781 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2728320781
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.3484984647
Short name T427
Test name
Test status
Simulation time 58923030 ps
CPU time 0.83 seconds
Started Jul 17 07:15:02 PM PDT 24
Finished Jul 17 07:15:18 PM PDT 24
Peak memory 206836 kb
Host smart-9fe05f95-22bf-423c-89ae-2ae5c0ba1349
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484984647 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.3484984647
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.4236001292
Short name T187
Test name
Test status
Simulation time 14681057 ps
CPU time 0.87 seconds
Started Jul 17 07:15:02 PM PDT 24
Finished Jul 17 07:15:18 PM PDT 24
Peak memory 216560 kb
Host smart-54c14d90-bff9-4832-b29d-76ce470e95d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236001292 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.4236001292
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.3759752623
Short name T674
Test name
Test status
Simulation time 49351584 ps
CPU time 1.06 seconds
Started Jul 17 07:15:02 PM PDT 24
Finished Jul 17 07:15:17 PM PDT 24
Peak memory 217080 kb
Host smart-5c7bd35e-5041-470c-8b9b-a713b80430e4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759752623 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.3759752623
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.391938921
Short name T465
Test name
Test status
Simulation time 23495144 ps
CPU time 1.03 seconds
Started Jul 17 07:15:02 PM PDT 24
Finished Jul 17 07:15:18 PM PDT 24
Peak memory 224236 kb
Host smart-b6f8e1e3-a279-434a-bd62-b9645cd95ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391938921 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.391938921
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.2836421895
Short name T749
Test name
Test status
Simulation time 75954606 ps
CPU time 1.18 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:15:17 PM PDT 24
Peak memory 219144 kb
Host smart-e99be024-67d2-4fce-8128-6987c274194c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836421895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.2836421895
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.1973835059
Short name T886
Test name
Test status
Simulation time 27839186 ps
CPU time 0.95 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:15:15 PM PDT 24
Peak memory 215820 kb
Host smart-70abeb2c-d6af-4026-a49e-642b1db59f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973835059 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1973835059
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.2435452857
Short name T921
Test name
Test status
Simulation time 21139319 ps
CPU time 0.97 seconds
Started Jul 17 07:15:02 PM PDT 24
Finished Jul 17 07:15:18 PM PDT 24
Peak memory 215540 kb
Host smart-635b14c1-613c-49b7-8917-3355d918c851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435452857 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.2435452857
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.1281022001
Short name T222
Test name
Test status
Simulation time 222331662 ps
CPU time 4.49 seconds
Started Jul 17 07:15:02 PM PDT 24
Finished Jul 17 07:15:22 PM PDT 24
Peak memory 217428 kb
Host smart-45449273-61c7-48d5-bf64-0124bd4c7f38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281022001 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1281022001
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.1531569705
Short name T847
Test name
Test status
Simulation time 29931749026 ps
CPU time 176.67 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:18:13 PM PDT 24
Peak memory 218560 kb
Host smart-b5cc1d56-3308-420c-b991-dd7c788851ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531569705 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.1531569705
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.3030240449
Short name T446
Test name
Test status
Simulation time 28418152 ps
CPU time 1.22 seconds
Started Jul 17 07:15:02 PM PDT 24
Finished Jul 17 07:15:18 PM PDT 24
Peak memory 218836 kb
Host smart-7aa783cd-1f4b-4daa-86a9-a565c7de4d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030240449 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.3030240449
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.4282834947
Short name T57
Test name
Test status
Simulation time 198465611 ps
CPU time 0.9 seconds
Started Jul 17 07:14:49 PM PDT 24
Finished Jul 17 07:14:51 PM PDT 24
Peak memory 215508 kb
Host smart-5a5eca92-c6d7-463c-9a79-552617e87526
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282834947 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.4282834947
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.1980554680
Short name T43
Test name
Test status
Simulation time 18262769 ps
CPU time 0.84 seconds
Started Jul 17 07:15:02 PM PDT 24
Finished Jul 17 07:15:17 PM PDT 24
Peak memory 216600 kb
Host smart-3ac58e8f-3e82-4693-a5b0-a13ddca96771
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980554680 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1980554680
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.3531398723
Short name T442
Test name
Test status
Simulation time 42537202 ps
CPU time 0.92 seconds
Started Jul 17 07:15:05 PM PDT 24
Finished Jul 17 07:15:23 PM PDT 24
Peak memory 217324 kb
Host smart-a08789ed-6008-4aaf-9875-4f40e8c63a59
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531398723 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.3531398723
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.1144321444
Short name T78
Test name
Test status
Simulation time 27759177 ps
CPU time 0.85 seconds
Started Jul 17 07:15:05 PM PDT 24
Finished Jul 17 07:15:22 PM PDT 24
Peak memory 218848 kb
Host smart-093fad6a-a47a-4bbb-aff6-eee5cb1e6ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144321444 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.1144321444
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.526377630
Short name T335
Test name
Test status
Simulation time 39915528 ps
CPU time 1.09 seconds
Started Jul 17 07:15:00 PM PDT 24
Finished Jul 17 07:15:13 PM PDT 24
Peak memory 217528 kb
Host smart-e27c91f0-41a4-4dd4-b0a5-65eb4d59a6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526377630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.526377630
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.2059327221
Short name T617
Test name
Test status
Simulation time 21019848 ps
CPU time 1.09 seconds
Started Jul 17 07:15:02 PM PDT 24
Finished Jul 17 07:15:18 PM PDT 24
Peak memory 215860 kb
Host smart-a4896113-3bce-4514-9bb2-b1cde6b3133e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059327221 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.2059327221
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.2199749397
Short name T457
Test name
Test status
Simulation time 44472142 ps
CPU time 0.95 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:15:15 PM PDT 24
Peak memory 207376 kb
Host smart-71d5273f-6054-405d-a8af-f9f7c624a25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199749397 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.2199749397
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.1685957241
Short name T698
Test name
Test status
Simulation time 219089478 ps
CPU time 2.7 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:15:18 PM PDT 24
Peak memory 215532 kb
Host smart-9ac8ceb4-1565-40a6-b6e0-83b232ea4372
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685957241 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.1685957241
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1074273813
Short name T869
Test name
Test status
Simulation time 81558513473 ps
CPU time 442.15 seconds
Started Jul 17 07:15:01 PM PDT 24
Finished Jul 17 07:22:38 PM PDT 24
Peak memory 221300 kb
Host smart-f342951a-538c-48ae-9318-ddc1f98e580a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074273813 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1074273813
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.3105150730
Short name T923
Test name
Test status
Simulation time 26906268 ps
CPU time 1.12 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:28 PM PDT 24
Peak memory 216028 kb
Host smart-61a89801-2b45-4416-8dde-e7e646fce4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105150730 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3105150730
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.1606205805
Short name T429
Test name
Test status
Simulation time 25993245 ps
CPU time 1.07 seconds
Started Jul 17 07:16:20 PM PDT 24
Finished Jul 17 07:16:24 PM PDT 24
Peak memory 207144 kb
Host smart-4294a512-ffaf-4076-a199-646b153cabd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606205805 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.1606205805
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.1276819050
Short name T352
Test name
Test status
Simulation time 65389018 ps
CPU time 0.86 seconds
Started Jul 17 07:16:17 PM PDT 24
Finished Jul 17 07:16:19 PM PDT 24
Peak memory 216284 kb
Host smart-803b704e-b953-439c-8fbb-db7a88f786cb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276819050 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1276819050
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.3524196746
Short name T409
Test name
Test status
Simulation time 46788374 ps
CPU time 1.34 seconds
Started Jul 17 07:16:21 PM PDT 24
Finished Jul 17 07:16:27 PM PDT 24
Peak memory 218388 kb
Host smart-5d1bc5ce-d44a-4205-8837-b307079c8e97
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524196746 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.3524196746
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.3921111799
Short name T338
Test name
Test status
Simulation time 33375540 ps
CPU time 0.85 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:29 PM PDT 24
Peak memory 218396 kb
Host smart-7efa65a6-111f-4354-91c4-9fcc0f987c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921111799 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.3921111799
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.454404603
Short name T668
Test name
Test status
Simulation time 59645340 ps
CPU time 1.49 seconds
Started Jul 17 07:16:19 PM PDT 24
Finished Jul 17 07:16:22 PM PDT 24
Peak memory 218828 kb
Host smart-8adf97ce-f2de-45af-8b8e-e6b6c2f2e8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454404603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.454404603
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.2980019423
Short name T562
Test name
Test status
Simulation time 22245522 ps
CPU time 1.1 seconds
Started Jul 17 07:16:19 PM PDT 24
Finished Jul 17 07:16:22 PM PDT 24
Peak memory 215864 kb
Host smart-f65e40bc-9b44-4c6d-bcfb-b4ef883dd424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980019423 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.2980019423
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.3436203278
Short name T859
Test name
Test status
Simulation time 19076837 ps
CPU time 0.93 seconds
Started Jul 17 07:16:18 PM PDT 24
Finished Jul 17 07:16:21 PM PDT 24
Peak memory 215572 kb
Host smart-1c94aacc-4bea-4f6a-a480-41d15819fea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436203278 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.3436203278
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.2644765198
Short name T323
Test name
Test status
Simulation time 78019537 ps
CPU time 1.02 seconds
Started Jul 17 07:16:18 PM PDT 24
Finished Jul 17 07:16:20 PM PDT 24
Peak memory 207368 kb
Host smart-e7b109f5-dacf-4c5d-929e-1acf3b2057a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644765198 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.2644765198
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.1801677018
Short name T563
Test name
Test status
Simulation time 253088904953 ps
CPU time 1389.52 seconds
Started Jul 17 07:16:21 PM PDT 24
Finished Jul 17 07:39:37 PM PDT 24
Peak memory 224548 kb
Host smart-daf466dc-dc1d-4606-a727-0f9376fc5b07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801677018 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.1801677018
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.2776990845
Short name T137
Test name
Test status
Simulation time 26909833 ps
CPU time 1.26 seconds
Started Jul 17 07:16:19 PM PDT 24
Finished Jul 17 07:16:22 PM PDT 24
Peak memory 219976 kb
Host smart-caafd0f4-d5c3-46b9-953a-d9cd0b6ade39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776990845 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.2776990845
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.1614788940
Short name T325
Test name
Test status
Simulation time 32281059 ps
CPU time 0.92 seconds
Started Jul 17 07:16:19 PM PDT 24
Finished Jul 17 07:16:21 PM PDT 24
Peak memory 207088 kb
Host smart-400cdc62-2800-459c-abe0-4b6486f181f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614788940 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.1614788940
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.1646413386
Short name T731
Test name
Test status
Simulation time 20782174 ps
CPU time 0.87 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:28 PM PDT 24
Peak memory 216464 kb
Host smart-f7bd3545-87f9-4004-a67d-fca850758b4e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646413386 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1646413386
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.131432094
Short name T181
Test name
Test status
Simulation time 107124087 ps
CPU time 1.03 seconds
Started Jul 17 07:16:20 PM PDT 24
Finished Jul 17 07:16:23 PM PDT 24
Peak memory 218740 kb
Host smart-cbbd6550-b551-422c-88f5-5207d510d838
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131432094 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_di
sable_auto_req_mode.131432094
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.1912536148
Short name T954
Test name
Test status
Simulation time 19045813 ps
CPU time 1.15 seconds
Started Jul 17 07:16:20 PM PDT 24
Finished Jul 17 07:16:24 PM PDT 24
Peak memory 224280 kb
Host smart-36bcc57e-c93f-4a82-a367-23833911cbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912536148 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.1912536148
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.1306132372
Short name T880
Test name
Test status
Simulation time 56842255 ps
CPU time 1.56 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:29 PM PDT 24
Peak memory 220312 kb
Host smart-e2826f87-b21d-48e7-a37c-b3063763cf7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306132372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1306132372
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2687879807
Short name T491
Test name
Test status
Simulation time 22287798 ps
CPU time 1.22 seconds
Started Jul 17 07:16:17 PM PDT 24
Finished Jul 17 07:16:19 PM PDT 24
Peak memory 224340 kb
Host smart-08abaf03-d027-4d82-9111-ea7bc40d57ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687879807 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2687879807
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.2752817932
Short name T716
Test name
Test status
Simulation time 25830529 ps
CPU time 0.94 seconds
Started Jul 17 07:16:20 PM PDT 24
Finished Jul 17 07:16:25 PM PDT 24
Peak memory 215528 kb
Host smart-8e9d1224-3eef-4306-8830-606f4aff998f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752817932 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.2752817932
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.1972611550
Short name T94
Test name
Test status
Simulation time 66061334 ps
CPU time 0.94 seconds
Started Jul 17 07:16:18 PM PDT 24
Finished Jul 17 07:16:20 PM PDT 24
Peak memory 215572 kb
Host smart-1c472320-6a3e-45c9-af91-609bcde529be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972611550 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1972611550
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.3110268533
Short name T983
Test name
Test status
Simulation time 47586735940 ps
CPU time 1144.15 seconds
Started Jul 17 07:16:21 PM PDT 24
Finished Jul 17 07:35:31 PM PDT 24
Peak memory 222880 kb
Host smart-93d37229-6607-497a-a05d-d784ab890f63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110268533 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.3110268533
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert_test.2199760254
Short name T473
Test name
Test status
Simulation time 46483550 ps
CPU time 0.87 seconds
Started Jul 17 07:16:21 PM PDT 24
Finished Jul 17 07:16:26 PM PDT 24
Peak memory 207264 kb
Host smart-4918fdb7-6be1-4106-b377-0e4046c24c06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199760254 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.2199760254
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.1933910625
Short name T770
Test name
Test status
Simulation time 23496458 ps
CPU time 0.88 seconds
Started Jul 17 07:16:18 PM PDT 24
Finished Jul 17 07:16:20 PM PDT 24
Peak memory 216480 kb
Host smart-57af1c90-113d-4c48-988d-75db29a6f235
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933910625 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.1933910625
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.2144716390
Short name T185
Test name
Test status
Simulation time 303351887 ps
CPU time 1.05 seconds
Started Jul 17 07:16:21 PM PDT 24
Finished Jul 17 07:16:28 PM PDT 24
Peak memory 217120 kb
Host smart-c00d5331-c1f8-4a00-9e01-709497d4a14b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144716390 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.2144716390
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.2228752992
Short name T672
Test name
Test status
Simulation time 19060099 ps
CPU time 0.99 seconds
Started Jul 17 07:16:21 PM PDT 24
Finished Jul 17 07:16:26 PM PDT 24
Peak memory 218908 kb
Host smart-a57680d4-4275-4e0a-81ea-e5e3c1f5866b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228752992 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.2228752992
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.1581043074
Short name T609
Test name
Test status
Simulation time 139511221 ps
CPU time 2.63 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:32 PM PDT 24
Peak memory 217936 kb
Host smart-f3e2f75c-6359-4b1d-9e70-dae1af613473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581043074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.1581043074
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_smoke.3541929155
Short name T878
Test name
Test status
Simulation time 95194035 ps
CPU time 0.92 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:30 PM PDT 24
Peak memory 215544 kb
Host smart-fc061394-fcac-43ed-ba3d-0149ce4c1ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541929155 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.3541929155
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.2960472851
Short name T591
Test name
Test status
Simulation time 712596892 ps
CPU time 4.42 seconds
Started Jul 17 07:16:21 PM PDT 24
Finished Jul 17 07:16:29 PM PDT 24
Peak memory 217588 kb
Host smart-95eb4062-0960-4c7f-bcd2-97ade6da4a10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960472851 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.2960472851
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.764598218
Short name T708
Test name
Test status
Simulation time 61319367757 ps
CPU time 1482.37 seconds
Started Jul 17 07:16:21 PM PDT 24
Finished Jul 17 07:41:08 PM PDT 24
Peak memory 225656 kb
Host smart-1d38f801-e213-4836-aef6-6b41b927e738
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764598218 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.764598218
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.812385912
Short name T148
Test name
Test status
Simulation time 47447743 ps
CPU time 1.16 seconds
Started Jul 17 07:16:21 PM PDT 24
Finished Jul 17 07:16:28 PM PDT 24
Peak memory 220176 kb
Host smart-99c1121b-5468-4119-9a45-e765d91ebc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812385912 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.812385912
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.4108426032
Short name T477
Test name
Test status
Simulation time 23828646 ps
CPU time 0.85 seconds
Started Jul 17 07:16:21 PM PDT 24
Finished Jul 17 07:16:25 PM PDT 24
Peak memory 207020 kb
Host smart-1f2d5065-3d06-44d0-9e67-20bfd77ee24d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108426032 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.4108426032
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.3321795839
Short name T161
Test name
Test status
Simulation time 72169871 ps
CPU time 0.84 seconds
Started Jul 17 07:16:21 PM PDT 24
Finished Jul 17 07:16:27 PM PDT 24
Peak memory 216484 kb
Host smart-1ffdfe05-cf76-49ba-ae9c-af54302d89c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321795839 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.3321795839
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.1950744429
Short name T330
Test name
Test status
Simulation time 95554554 ps
CPU time 1.06 seconds
Started Jul 17 07:16:19 PM PDT 24
Finished Jul 17 07:16:21 PM PDT 24
Peak memory 220072 kb
Host smart-1a85a023-4740-4c97-a007-056555d46810
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950744429 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.1950744429
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.3724696343
Short name T363
Test name
Test status
Simulation time 22859922 ps
CPU time 1.08 seconds
Started Jul 17 07:16:21 PM PDT 24
Finished Jul 17 07:16:27 PM PDT 24
Peak memory 218904 kb
Host smart-ed16fc01-0bb7-4a96-b254-5fa380ea0e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724696343 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3724696343
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.3825962676
Short name T512
Test name
Test status
Simulation time 48246852 ps
CPU time 1.24 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:29 PM PDT 24
Peak memory 218980 kb
Host smart-d23e21c2-b870-4449-b8f4-47f7e1f7d786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825962676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.3825962676
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.823725058
Short name T79
Test name
Test status
Simulation time 28153404 ps
CPU time 0.82 seconds
Started Jul 17 07:16:19 PM PDT 24
Finished Jul 17 07:16:21 PM PDT 24
Peak memory 216008 kb
Host smart-9438fdc4-9fec-4f73-b486-ffae7e1eab04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823725058 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.823725058
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.2917028299
Short name T595
Test name
Test status
Simulation time 19051049 ps
CPU time 0.94 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:29 PM PDT 24
Peak memory 215576 kb
Host smart-b45f90f9-173d-4d8a-8e86-13e2d50ced06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917028299 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.2917028299
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.4258763628
Short name T864
Test name
Test status
Simulation time 911186810 ps
CPU time 4.73 seconds
Started Jul 17 07:16:21 PM PDT 24
Finished Jul 17 07:16:31 PM PDT 24
Peak memory 220728 kb
Host smart-61ba5e47-eec2-49f4-af50-f45b97e936c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258763628 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.4258763628
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.2471687357
Short name T549
Test name
Test status
Simulation time 142641162902 ps
CPU time 854.32 seconds
Started Jul 17 07:16:21 PM PDT 24
Finished Jul 17 07:30:39 PM PDT 24
Peak memory 223944 kb
Host smart-f54acaaf-698d-4150-8727-39c984916030
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471687357 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.2471687357
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.4023756304
Short name T423
Test name
Test status
Simulation time 23314452 ps
CPU time 1.09 seconds
Started Jul 17 07:14:37 PM PDT 24
Finished Jul 17 07:14:44 PM PDT 24
Peak memory 218708 kb
Host smart-e498c0d0-9d73-4a7b-99d7-5fab48ea69b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023756304 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.4023756304
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.2395686291
Short name T691
Test name
Test status
Simulation time 208904620 ps
CPU time 0.95 seconds
Started Jul 17 07:14:39 PM PDT 24
Finished Jul 17 07:14:47 PM PDT 24
Peak memory 207280 kb
Host smart-8db117a2-623d-4308-9bcc-dc3a5ca838ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395686291 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2395686291
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.3239087399
Short name T141
Test name
Test status
Simulation time 13982244 ps
CPU time 0.9 seconds
Started Jul 17 07:14:33 PM PDT 24
Finished Jul 17 07:14:39 PM PDT 24
Peak memory 215868 kb
Host smart-94fbb9bc-ad98-4d15-a598-7052e841126a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239087399 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.3239087399
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.4183735795
Short name T119
Test name
Test status
Simulation time 45870472 ps
CPU time 1.02 seconds
Started Jul 17 07:14:39 PM PDT 24
Finished Jul 17 07:14:47 PM PDT 24
Peak memory 217312 kb
Host smart-54596d02-83c0-4e64-8a77-33696a37f186
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183735795 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.4183735795
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.2329234083
Short name T142
Test name
Test status
Simulation time 19187800 ps
CPU time 1.21 seconds
Started Jul 17 07:14:39 PM PDT 24
Finished Jul 17 07:14:47 PM PDT 24
Peak memory 224340 kb
Host smart-ae8c32a5-8f24-4fcc-87b9-b0db8de7271d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329234083 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.2329234083
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.3038852550
Short name T462
Test name
Test status
Simulation time 106600021 ps
CPU time 1.23 seconds
Started Jul 17 07:14:37 PM PDT 24
Finished Jul 17 07:14:46 PM PDT 24
Peak memory 220220 kb
Host smart-23ce9928-f3a0-4c72-a235-b8b03aac4256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038852550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.3038852550
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.3022437826
Short name T361
Test name
Test status
Simulation time 32240926 ps
CPU time 0.91 seconds
Started Jul 17 07:14:34 PM PDT 24
Finished Jul 17 07:14:40 PM PDT 24
Peak memory 215388 kb
Host smart-2a3a7b52-e642-4891-bfaf-86a489f47584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022437826 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3022437826
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.1960354780
Short name T815
Test name
Test status
Simulation time 82735700 ps
CPU time 0.92 seconds
Started Jul 17 07:14:36 PM PDT 24
Finished Jul 17 07:14:44 PM PDT 24
Peak memory 207072 kb
Host smart-badd420f-852f-40a2-806b-0baae19dd8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960354780 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.1960354780
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.979029477
Short name T18
Test name
Test status
Simulation time 545720758 ps
CPU time 8.01 seconds
Started Jul 17 07:14:39 PM PDT 24
Finished Jul 17 07:14:54 PM PDT 24
Peak memory 238000 kb
Host smart-718ad127-1c99-4053-a1f3-fa853574f876
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979029477 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.979029477
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.518922220
Short name T932
Test name
Test status
Simulation time 28885884 ps
CPU time 0.95 seconds
Started Jul 17 07:14:36 PM PDT 24
Finished Jul 17 07:14:44 PM PDT 24
Peak memory 215588 kb
Host smart-511539d9-0bfa-408d-af9d-fb6a0203af57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518922220 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.518922220
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.4126804877
Short name T544
Test name
Test status
Simulation time 174626147 ps
CPU time 3.85 seconds
Started Jul 17 07:14:36 PM PDT 24
Finished Jul 17 07:14:47 PM PDT 24
Peak memory 220372 kb
Host smart-e0a97933-7ecd-4dcc-b719-b7368b719239
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126804877 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.4126804877
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.807642528
Short name T572
Test name
Test status
Simulation time 157803785297 ps
CPU time 2048.77 seconds
Started Jul 17 07:14:32 PM PDT 24
Finished Jul 17 07:48:45 PM PDT 24
Peak memory 230292 kb
Host smart-e58362ca-5ec0-4ec4-9532-79c1a8d10928
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807642528 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.807642528
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.1663004525
Short name T165
Test name
Test status
Simulation time 27167120 ps
CPU time 1.19 seconds
Started Jul 17 07:16:20 PM PDT 24
Finished Jul 17 07:16:25 PM PDT 24
Peak memory 218876 kb
Host smart-6bbeb5df-bb83-4795-869b-fcb036518fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663004525 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.1663004525
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.3660095941
Short name T627
Test name
Test status
Simulation time 17902878 ps
CPU time 0.96 seconds
Started Jul 17 07:16:18 PM PDT 24
Finished Jul 17 07:16:21 PM PDT 24
Peak memory 207072 kb
Host smart-e91f7297-3884-463e-928c-82a8d3f8a62c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660095941 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3660095941
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.2625805590
Short name T412
Test name
Test status
Simulation time 20392249 ps
CPU time 0.84 seconds
Started Jul 17 07:16:17 PM PDT 24
Finished Jul 17 07:16:18 PM PDT 24
Peak memory 216600 kb
Host smart-26112b2c-35c2-476b-a468-a9bc886c8733
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625805590 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.2625805590
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.2005918002
Short name T658
Test name
Test status
Simulation time 130210429 ps
CPU time 1.26 seconds
Started Jul 17 07:16:21 PM PDT 24
Finished Jul 17 07:16:26 PM PDT 24
Peak memory 219508 kb
Host smart-f4f3a967-d939-42af-a658-f0b0846331d6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005918002 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.2005918002
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.3998837517
Short name T144
Test name
Test status
Simulation time 20958551 ps
CPU time 1.07 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:30 PM PDT 24
Peak memory 218860 kb
Host smart-472cfd45-4e8d-461d-8365-2394fdbf6aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998837517 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.3998837517
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.857583121
Short name T867
Test name
Test status
Simulation time 62655489 ps
CPU time 2 seconds
Started Jul 17 07:16:20 PM PDT 24
Finished Jul 17 07:16:24 PM PDT 24
Peak memory 217896 kb
Host smart-d2644d9c-971d-4335-8c07-21c31dbcd48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857583121 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.857583121
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.993107840
Short name T36
Test name
Test status
Simulation time 28194105 ps
CPU time 0.9 seconds
Started Jul 17 07:16:17 PM PDT 24
Finished Jul 17 07:16:18 PM PDT 24
Peak memory 216088 kb
Host smart-e07ed031-6020-48db-8f1f-c8439b220cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993107840 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.993107840
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.1594501415
Short name T369
Test name
Test status
Simulation time 54210040 ps
CPU time 0.97 seconds
Started Jul 17 07:16:17 PM PDT 24
Finished Jul 17 07:16:19 PM PDT 24
Peak memory 215544 kb
Host smart-b6e1e1e7-1a0e-4780-9ffb-b9f940343079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594501415 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1594501415
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.4106711592
Short name T322
Test name
Test status
Simulation time 296491711 ps
CPU time 0.97 seconds
Started Jul 17 07:16:21 PM PDT 24
Finished Jul 17 07:16:26 PM PDT 24
Peak memory 207336 kb
Host smart-302978a9-b455-4267-be3b-456a493f5157
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106711592 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.4106711592
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2355349115
Short name T746
Test name
Test status
Simulation time 71529366887 ps
CPU time 1648.67 seconds
Started Jul 17 07:16:21 PM PDT 24
Finished Jul 17 07:43:56 PM PDT 24
Peak memory 224636 kb
Host smart-d7013a8f-c389-4b96-a7a8-a66d2c3b2045
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355349115 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.2355349115
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.126865492
Short name T958
Test name
Test status
Simulation time 29540975 ps
CPU time 1.24 seconds
Started Jul 17 07:16:21 PM PDT 24
Finished Jul 17 07:16:28 PM PDT 24
Peak memory 220108 kb
Host smart-53262f01-4778-4d20-85d0-77dd036415f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126865492 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.126865492
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.474740589
Short name T640
Test name
Test status
Simulation time 29840066 ps
CPU time 0.88 seconds
Started Jul 17 07:16:24 PM PDT 24
Finished Jul 17 07:16:36 PM PDT 24
Peak memory 215132 kb
Host smart-3cb24e4d-f77a-4876-a4f5-de64b3c837c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474740589 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.474740589
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.1421338594
Short name T604
Test name
Test status
Simulation time 38170342 ps
CPU time 0.84 seconds
Started Jul 17 07:16:24 PM PDT 24
Finished Jul 17 07:16:37 PM PDT 24
Peak memory 216580 kb
Host smart-423231e3-5940-44b5-9cde-2fa3ca98df8f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421338594 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.1421338594
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.877808102
Short name T332
Test name
Test status
Simulation time 59640500 ps
CPU time 1.19 seconds
Started Jul 17 07:16:21 PM PDT 24
Finished Jul 17 07:16:27 PM PDT 24
Peak memory 217060 kb
Host smart-defa7f67-a94a-4c69-bf8c-1248a3123cc5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877808102 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_di
sable_auto_req_mode.877808102
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.2211158916
Short name T382
Test name
Test status
Simulation time 17957704 ps
CPU time 1.03 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:30 PM PDT 24
Peak memory 218800 kb
Host smart-04adc468-0732-434e-8a04-9b97756b7bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211158916 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2211158916
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.586571017
Short name T303
Test name
Test status
Simulation time 54739304 ps
CPU time 1.53 seconds
Started Jul 17 07:16:21 PM PDT 24
Finished Jul 17 07:16:27 PM PDT 24
Peak memory 217556 kb
Host smart-87e1ff45-20a9-4d9d-aa88-722aad73fd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586571017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.586571017
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.948962202
Short name T962
Test name
Test status
Simulation time 37016386 ps
CPU time 0.89 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:30 PM PDT 24
Peak memory 215760 kb
Host smart-c21bd575-e4d8-46a4-83ab-ab09928ca982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948962202 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.948962202
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.1929609360
Short name T660
Test name
Test status
Simulation time 19326974 ps
CPU time 1.01 seconds
Started Jul 17 07:16:20 PM PDT 24
Finished Jul 17 07:16:22 PM PDT 24
Peak memory 215556 kb
Host smart-850bde90-2bc8-49d1-813c-50ee9ef7d08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929609360 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.1929609360
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.378944043
Short name T778
Test name
Test status
Simulation time 93160506 ps
CPU time 1.57 seconds
Started Jul 17 07:16:17 PM PDT 24
Finished Jul 17 07:16:20 PM PDT 24
Peak memory 217612 kb
Host smart-c9ca6ddf-81ee-4222-8d1e-f09d6c8bc748
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378944043 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.378944043
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.4016598260
Short name T219
Test name
Test status
Simulation time 93041201607 ps
CPU time 2002.61 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:49:50 PM PDT 24
Peak memory 227364 kb
Host smart-c67c5b5c-312f-45a9-aa5e-fd995732427e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016598260 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.4016598260
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.2756274907
Short name T271
Test name
Test status
Simulation time 23738011 ps
CPU time 1.2 seconds
Started Jul 17 07:16:28 PM PDT 24
Finished Jul 17 07:16:46 PM PDT 24
Peak memory 219988 kb
Host smart-8aebb79b-0904-4590-bcd3-a79708972c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756274907 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.2756274907
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.1979840597
Short name T497
Test name
Test status
Simulation time 31261009 ps
CPU time 0.89 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:30 PM PDT 24
Peak memory 207040 kb
Host smart-f1da135e-99fb-427b-933e-4008b7e7789c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979840597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.1979840597
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.4228190882
Short name T182
Test name
Test status
Simulation time 18823638 ps
CPU time 0.82 seconds
Started Jul 17 07:16:23 PM PDT 24
Finished Jul 17 07:16:33 PM PDT 24
Peak memory 216692 kb
Host smart-1ee9b15b-0ff0-4c77-a5e4-4140907524a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228190882 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.4228190882
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.350602582
Short name T877
Test name
Test status
Simulation time 116566193 ps
CPU time 1.1 seconds
Started Jul 17 07:16:25 PM PDT 24
Finished Jul 17 07:16:38 PM PDT 24
Peak memory 218400 kb
Host smart-aafbae62-bba9-4022-9d48-1a4bfafe9339
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350602582 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_di
sable_auto_req_mode.350602582
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.3135695050
Short name T151
Test name
Test status
Simulation time 43882148 ps
CPU time 0.81 seconds
Started Jul 17 07:16:21 PM PDT 24
Finished Jul 17 07:16:28 PM PDT 24
Peak memory 218656 kb
Host smart-22fa329a-8d36-4149-aeeb-ea75f02c3c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135695050 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.3135695050
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.2167074469
Short name T989
Test name
Test status
Simulation time 50512501 ps
CPU time 1.45 seconds
Started Jul 17 07:16:21 PM PDT 24
Finished Jul 17 07:16:26 PM PDT 24
Peak memory 218864 kb
Host smart-d6f57d53-466f-4120-b132-557684539302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167074469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.2167074469
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.4264922469
Short name T874
Test name
Test status
Simulation time 21006940 ps
CPU time 1.06 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:30 PM PDT 24
Peak memory 216028 kb
Host smart-78961616-1ef6-4e74-9c30-c80cd17d5c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264922469 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.4264922469
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.3314034583
Short name T613
Test name
Test status
Simulation time 41133997 ps
CPU time 0.86 seconds
Started Jul 17 07:16:21 PM PDT 24
Finished Jul 17 07:16:26 PM PDT 24
Peak memory 215552 kb
Host smart-3b43c9d5-561b-4426-87b2-bb3fe2fa9919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314034583 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3314034583
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.2035685367
Short name T478
Test name
Test status
Simulation time 269380718 ps
CPU time 5.49 seconds
Started Jul 17 07:16:24 PM PDT 24
Finished Jul 17 07:16:40 PM PDT 24
Peak memory 217420 kb
Host smart-cede46c9-a3f9-4e14-9b85-3cfc5be94b15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035685367 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2035685367
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_alert.2743625007
Short name T885
Test name
Test status
Simulation time 29631920 ps
CPU time 1.21 seconds
Started Jul 17 07:16:26 PM PDT 24
Finished Jul 17 07:16:42 PM PDT 24
Peak memory 220036 kb
Host smart-3c1feaf6-1aca-4ca5-9a4d-c40064508420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743625007 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2743625007
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.493272931
Short name T711
Test name
Test status
Simulation time 30726866 ps
CPU time 0.88 seconds
Started Jul 17 07:16:27 PM PDT 24
Finished Jul 17 07:16:43 PM PDT 24
Peak memory 207024 kb
Host smart-ed7fc86a-c697-42b6-a67e-1a6bcb4c7340
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493272931 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.493272931
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.820887417
Short name T204
Test name
Test status
Simulation time 20591983 ps
CPU time 0.85 seconds
Started Jul 17 07:16:28 PM PDT 24
Finished Jul 17 07:16:46 PM PDT 24
Peak memory 207152 kb
Host smart-0a29ee83-da4b-4f6d-a115-c950a68b13a4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820887417 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.820887417
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.2189899874
Short name T127
Test name
Test status
Simulation time 38906267 ps
CPU time 0.99 seconds
Started Jul 17 07:16:26 PM PDT 24
Finished Jul 17 07:16:42 PM PDT 24
Peak memory 217248 kb
Host smart-97cef4a7-baa5-4c49-9227-66f3ddf60223
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189899874 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.2189899874
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.2479078621
Short name T159
Test name
Test status
Simulation time 23747804 ps
CPU time 1.04 seconds
Started Jul 17 07:16:28 PM PDT 24
Finished Jul 17 07:16:46 PM PDT 24
Peak memory 223924 kb
Host smart-894f7efe-812d-4494-a9fd-cb0c58423afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479078621 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.2479078621
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.650763615
Short name T390
Test name
Test status
Simulation time 52756521 ps
CPU time 1.72 seconds
Started Jul 17 07:16:24 PM PDT 24
Finished Jul 17 07:16:38 PM PDT 24
Peak memory 218792 kb
Host smart-a5a11af8-2069-4599-adda-46f8b8cfd4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650763615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.650763615
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.2312834641
Short name T366
Test name
Test status
Simulation time 32213999 ps
CPU time 0.85 seconds
Started Jul 17 07:16:25 PM PDT 24
Finished Jul 17 07:16:39 PM PDT 24
Peak memory 215544 kb
Host smart-2ddc4ac8-8c13-4b56-8980-798a676f02a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312834641 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.2312834641
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.299100925
Short name T928
Test name
Test status
Simulation time 49653735 ps
CPU time 0.94 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:29 PM PDT 24
Peak memory 215564 kb
Host smart-ba792174-941a-42d3-897a-914cd25abb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299100925 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.299100925
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.2623705711
Short name T842
Test name
Test status
Simulation time 145113841 ps
CPU time 3.05 seconds
Started Jul 17 07:16:25 PM PDT 24
Finished Jul 17 07:16:41 PM PDT 24
Peak memory 217420 kb
Host smart-a6640fdf-82b2-4ac0-b268-56b8859cd1b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623705711 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.2623705711
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.1601994835
Short name T212
Test name
Test status
Simulation time 465326370502 ps
CPU time 1913.29 seconds
Started Jul 17 07:16:25 PM PDT 24
Finished Jul 17 07:48:30 PM PDT 24
Peak memory 227032 kb
Host smart-fd2d877c-0088-4a86-8460-3abf8bc635e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601994835 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.1601994835
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.4073116580
Short name T62
Test name
Test status
Simulation time 25619146 ps
CPU time 1.2 seconds
Started Jul 17 07:16:29 PM PDT 24
Finished Jul 17 07:16:49 PM PDT 24
Peak memory 218892 kb
Host smart-476a74c6-6c65-4aa9-8a70-5b5facfd1109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073116580 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.4073116580
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.1583788067
Short name T469
Test name
Test status
Simulation time 15961050 ps
CPU time 0.91 seconds
Started Jul 17 07:16:30 PM PDT 24
Finished Jul 17 07:16:48 PM PDT 24
Peak memory 207064 kb
Host smart-54c3d951-7f83-4599-ab84-2898d5a9753b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583788067 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.1583788067
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.847676723
Short name T483
Test name
Test status
Simulation time 31154347 ps
CPU time 0.83 seconds
Started Jul 17 07:16:26 PM PDT 24
Finished Jul 17 07:16:40 PM PDT 24
Peak memory 216180 kb
Host smart-865c5d21-a4d9-4d50-ab88-78242e6eb355
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847676723 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.847676723
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.2059253958
Short name T766
Test name
Test status
Simulation time 75782205 ps
CPU time 1.17 seconds
Started Jul 17 07:16:28 PM PDT 24
Finished Jul 17 07:16:46 PM PDT 24
Peak memory 216940 kb
Host smart-a1f89683-3c69-4565-a0f2-c2788bab00ed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059253958 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.2059253958
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.3329585501
Short name T171
Test name
Test status
Simulation time 29829483 ps
CPU time 0.86 seconds
Started Jul 17 07:16:29 PM PDT 24
Finished Jul 17 07:16:46 PM PDT 24
Peak memory 218612 kb
Host smart-c0926191-bf0c-42e0-90c0-8406f8b7f5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329585501 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.3329585501
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.1632060751
Short name T792
Test name
Test status
Simulation time 54450777 ps
CPU time 1.83 seconds
Started Jul 17 07:16:27 PM PDT 24
Finished Jul 17 07:16:44 PM PDT 24
Peak memory 218772 kb
Host smart-74bcb657-754b-4fa6-a5e4-b6bfc714f66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632060751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.1632060751
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.301406034
Short name T517
Test name
Test status
Simulation time 25920357 ps
CPU time 0.91 seconds
Started Jul 17 07:16:29 PM PDT 24
Finished Jul 17 07:16:48 PM PDT 24
Peak memory 215816 kb
Host smart-eb2ae8b8-7ec9-4644-a247-d9ada3f33ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301406034 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.301406034
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.3250561359
Short name T342
Test name
Test status
Simulation time 20964459 ps
CPU time 0.91 seconds
Started Jul 17 07:16:27 PM PDT 24
Finished Jul 17 07:16:43 PM PDT 24
Peak memory 215588 kb
Host smart-dce89db9-2ca8-433e-885c-1d49e04853c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250561359 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.3250561359
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.2169050032
Short name T493
Test name
Test status
Simulation time 190182958 ps
CPU time 2.14 seconds
Started Jul 17 07:16:25 PM PDT 24
Finished Jul 17 07:16:39 PM PDT 24
Peak memory 220468 kb
Host smart-1299df17-fc73-4617-b383-1685277cee69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169050032 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.2169050032
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.4066583017
Short name T207
Test name
Test status
Simulation time 79823867401 ps
CPU time 1092.65 seconds
Started Jul 17 07:16:25 PM PDT 24
Finished Jul 17 07:34:49 PM PDT 24
Peak memory 224240 kb
Host smart-b52e0f73-f48d-41ec-b215-923d3e2b2e58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066583017 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.4066583017
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.2733320103
Short name T85
Test name
Test status
Simulation time 43235749 ps
CPU time 1.21 seconds
Started Jul 17 07:16:29 PM PDT 24
Finished Jul 17 07:16:46 PM PDT 24
Peak memory 215988 kb
Host smart-d5fb46ec-5f2b-4479-91b4-7060fdb25981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733320103 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.2733320103
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.3082182863
Short name T860
Test name
Test status
Simulation time 26858390 ps
CPU time 0.9 seconds
Started Jul 17 07:16:28 PM PDT 24
Finished Jul 17 07:16:43 PM PDT 24
Peak memory 206996 kb
Host smart-7985235d-9987-4000-8db9-4f3d6754bd62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082182863 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3082182863
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.2497316539
Short name T889
Test name
Test status
Simulation time 46352956 ps
CPU time 0.8 seconds
Started Jul 17 07:16:30 PM PDT 24
Finished Jul 17 07:16:48 PM PDT 24
Peak memory 216468 kb
Host smart-89bab2c6-7b86-4474-b14d-a318462e0971
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497316539 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2497316539
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.67628090
Short name T761
Test name
Test status
Simulation time 26919576 ps
CPU time 1.08 seconds
Started Jul 17 07:16:31 PM PDT 24
Finished Jul 17 07:16:50 PM PDT 24
Peak memory 219436 kb
Host smart-189d6cb5-8f45-4e92-a5f7-b494b744842b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67628090 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_dis
able_auto_req_mode.67628090
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.1311761781
Short name T449
Test name
Test status
Simulation time 89514277 ps
CPU time 1.16 seconds
Started Jul 17 07:16:29 PM PDT 24
Finished Jul 17 07:16:48 PM PDT 24
Peak memory 219448 kb
Host smart-49d454d5-425d-437c-bf86-e9d0a99cf365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311761781 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1311761781
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.2424289599
Short name T496
Test name
Test status
Simulation time 64881519 ps
CPU time 1.26 seconds
Started Jul 17 07:16:27 PM PDT 24
Finished Jul 17 07:16:43 PM PDT 24
Peak memory 219380 kb
Host smart-3424bd62-2e5f-4384-a34c-9df4e26611ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424289599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.2424289599
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.3526520956
Short name T40
Test name
Test status
Simulation time 42384301 ps
CPU time 0.86 seconds
Started Jul 17 07:16:29 PM PDT 24
Finished Jul 17 07:16:48 PM PDT 24
Peak memory 215572 kb
Host smart-70d9b43e-c822-4338-814f-d2ce0b6c82c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526520956 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.3526520956
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.196285811
Short name T858
Test name
Test status
Simulation time 23313078 ps
CPU time 1.04 seconds
Started Jul 17 07:16:26 PM PDT 24
Finished Jul 17 07:16:41 PM PDT 24
Peak memory 215636 kb
Host smart-378580b4-cfa5-4aa1-a1cd-1fbdc8b68dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196285811 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.196285811
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.3112272108
Short name T385
Test name
Test status
Simulation time 171660996 ps
CPU time 2.88 seconds
Started Jul 17 07:16:35 PM PDT 24
Finished Jul 17 07:16:57 PM PDT 24
Peak memory 217772 kb
Host smart-0162aefc-adc5-4c20-83e5-435c656c994d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112272108 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.3112272108
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_alert.4222819666
Short name T273
Test name
Test status
Simulation time 23887056 ps
CPU time 1.14 seconds
Started Jul 17 07:16:21 PM PDT 24
Finished Jul 17 07:16:28 PM PDT 24
Peak memory 220036 kb
Host smart-f347cd95-f490-4769-a042-1f6a0e7f7cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222819666 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.4222819666
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.1690829944
Short name T540
Test name
Test status
Simulation time 19296714 ps
CPU time 0.97 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:32 PM PDT 24
Peak memory 207064 kb
Host smart-729b8502-203a-49cf-8dbf-702a03fcd251
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690829944 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.1690829944
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.652872769
Short name T901
Test name
Test status
Simulation time 22942936 ps
CPU time 0.91 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:31 PM PDT 24
Peak memory 216688 kb
Host smart-db7fe44a-6bf6-4f78-bbb5-d5db22ac3a75
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652872769 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.652872769
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.2718590734
Short name T812
Test name
Test status
Simulation time 35292296 ps
CPU time 1.13 seconds
Started Jul 17 07:16:24 PM PDT 24
Finished Jul 17 07:16:37 PM PDT 24
Peak memory 217140 kb
Host smart-a91aa3ec-a5a3-49af-a45c-254b096ffef0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718590734 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.2718590734
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.3540763570
Short name T99
Test name
Test status
Simulation time 28247147 ps
CPU time 1.16 seconds
Started Jul 17 07:16:21 PM PDT 24
Finished Jul 17 07:16:26 PM PDT 24
Peak memory 229852 kb
Host smart-8290cbab-d4a1-4602-bd9b-39dca3e43798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540763570 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.3540763570
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.2493522948
Short name T777
Test name
Test status
Simulation time 46160045 ps
CPU time 1.48 seconds
Started Jul 17 07:16:30 PM PDT 24
Finished Jul 17 07:16:48 PM PDT 24
Peak memory 219000 kb
Host smart-f145fbf4-e3c5-45d2-a514-118fdb4342be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493522948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.2493522948
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.420853091
Short name T33
Test name
Test status
Simulation time 39037439 ps
CPU time 0.79 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:29 PM PDT 24
Peak memory 215972 kb
Host smart-3d381cb1-05d3-4aa8-8134-8377f01823dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420853091 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.420853091
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.3888734037
Short name T431
Test name
Test status
Simulation time 65153936 ps
CPU time 0.94 seconds
Started Jul 17 07:16:29 PM PDT 24
Finished Jul 17 07:16:47 PM PDT 24
Peak memory 215548 kb
Host smart-e8e52c2d-99d4-4c9b-89e5-da089e517c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888734037 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.3888734037
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.3130330334
Short name T863
Test name
Test status
Simulation time 301287663 ps
CPU time 5.94 seconds
Started Jul 17 07:16:30 PM PDT 24
Finished Jul 17 07:16:55 PM PDT 24
Peak memory 217692 kb
Host smart-f352e3a2-721e-4451-b0c2-0efbab617e1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130330334 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.3130330334
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.4072226132
Short name T745
Test name
Test status
Simulation time 77666989563 ps
CPU time 1226.81 seconds
Started Jul 17 07:16:29 PM PDT 24
Finished Jul 17 07:37:14 PM PDT 24
Peak memory 223656 kb
Host smart-d13ab88e-1fb0-4408-887a-7fc34975fd0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072226132 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.4072226132
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.3987431881
Short name T84
Test name
Test status
Simulation time 43555384 ps
CPU time 1.08 seconds
Started Jul 17 07:16:23 PM PDT 24
Finished Jul 17 07:16:32 PM PDT 24
Peak memory 219388 kb
Host smart-6b69cf95-0370-4684-811c-fc32522ac449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987431881 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.3987431881
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.864535963
Short name T592
Test name
Test status
Simulation time 19783470 ps
CPU time 0.99 seconds
Started Jul 17 07:16:25 PM PDT 24
Finished Jul 17 07:16:38 PM PDT 24
Peak memory 215468 kb
Host smart-d8bb85e7-00d2-4520-a36c-4f3b6747fa88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864535963 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.864535963
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.1947773249
Short name T750
Test name
Test status
Simulation time 12155352 ps
CPU time 0.88 seconds
Started Jul 17 07:16:23 PM PDT 24
Finished Jul 17 07:16:31 PM PDT 24
Peak memory 216696 kb
Host smart-6b5e771e-8be7-4171-990a-b572d0125b2b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947773249 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1947773249
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.3438258030
Short name T118
Test name
Test status
Simulation time 49903203 ps
CPU time 0.92 seconds
Started Jul 17 07:16:24 PM PDT 24
Finished Jul 17 07:16:37 PM PDT 24
Peak memory 218764 kb
Host smart-c7d9a414-0c16-4055-8cbe-70416846bd32
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438258030 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.3438258030
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.1569240645
Short name T638
Test name
Test status
Simulation time 22164259 ps
CPU time 0.99 seconds
Started Jul 17 07:16:24 PM PDT 24
Finished Jul 17 07:16:36 PM PDT 24
Peak memory 224220 kb
Host smart-4f2f0a87-b6b3-4d10-9e0d-07d25947afff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569240645 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.1569240645
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.1292519765
Short name T911
Test name
Test status
Simulation time 104715944 ps
CPU time 1.6 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:32 PM PDT 24
Peak memory 217504 kb
Host smart-b3646695-2e76-44f3-ad13-ea58b60862d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292519765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1292519765
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1718097931
Short name T5
Test name
Test status
Simulation time 21467375 ps
CPU time 1.04 seconds
Started Jul 17 07:16:24 PM PDT 24
Finished Jul 17 07:16:36 PM PDT 24
Peak memory 215728 kb
Host smart-a8ca696f-73cc-48a9-aea3-cfcbc02a3137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718097931 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1718097931
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.3739113734
Short name T372
Test name
Test status
Simulation time 30118297 ps
CPU time 0.93 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:29 PM PDT 24
Peak memory 215556 kb
Host smart-1481d529-2e8b-409d-a165-2bcec06d0a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739113734 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.3739113734
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.2898266382
Short name T935
Test name
Test status
Simulation time 330788537 ps
CPU time 3.01 seconds
Started Jul 17 07:16:24 PM PDT 24
Finished Jul 17 07:16:38 PM PDT 24
Peak memory 215564 kb
Host smart-bedb995c-692c-4cf7-a7e8-ba38ba3c8f18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898266382 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.2898266382
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.4266091459
Short name T41
Test name
Test status
Simulation time 554510809380 ps
CPU time 1622.19 seconds
Started Jul 17 07:16:25 PM PDT 24
Finished Jul 17 07:43:40 PM PDT 24
Peak memory 227688 kb
Host smart-10e65d3d-7e6c-4dc0-9f69-17d4399d2937
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266091459 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.4266091459
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.2409711995
Short name T167
Test name
Test status
Simulation time 34556874 ps
CPU time 1.18 seconds
Started Jul 17 07:16:28 PM PDT 24
Finished Jul 17 07:16:46 PM PDT 24
Peak memory 220024 kb
Host smart-461a2332-2214-410d-af25-9c0d4e6b4578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409711995 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.2409711995
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.711822834
Short name T852
Test name
Test status
Simulation time 15995790 ps
CPU time 0.93 seconds
Started Jul 17 07:16:27 PM PDT 24
Finished Jul 17 07:16:42 PM PDT 24
Peak memory 215472 kb
Host smart-4c73a720-a8b8-4b56-94f3-166218babf7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711822834 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.711822834
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.924236640
Short name T154
Test name
Test status
Simulation time 14402252 ps
CPU time 0.86 seconds
Started Jul 17 07:16:28 PM PDT 24
Finished Jul 17 07:16:45 PM PDT 24
Peak memory 216600 kb
Host smart-3bbe7500-b4f9-4d69-937a-e90ac996ae29
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924236640 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.924236640
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.3474172989
Short name T184
Test name
Test status
Simulation time 93964238 ps
CPU time 1.05 seconds
Started Jul 17 07:16:27 PM PDT 24
Finished Jul 17 07:16:43 PM PDT 24
Peak memory 217024 kb
Host smart-e9a2ff37-363b-4229-a72d-08aed69a93ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474172989 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.3474172989
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_genbits.1305221749
Short name T467
Test name
Test status
Simulation time 54984325 ps
CPU time 1.26 seconds
Started Jul 17 07:16:25 PM PDT 24
Finished Jul 17 07:16:39 PM PDT 24
Peak memory 217460 kb
Host smart-d3de9242-2df0-4130-8f3e-a494e8d98978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305221749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1305221749
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.2752578560
Short name T75
Test name
Test status
Simulation time 33006838 ps
CPU time 0.85 seconds
Started Jul 17 07:16:25 PM PDT 24
Finished Jul 17 07:16:38 PM PDT 24
Peak memory 215908 kb
Host smart-de9a910d-c146-4da4-95dd-72767642622f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752578560 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.2752578560
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.945521126
Short name T793
Test name
Test status
Simulation time 28246649 ps
CPU time 0.9 seconds
Started Jul 17 07:16:26 PM PDT 24
Finished Jul 17 07:16:40 PM PDT 24
Peak memory 215536 kb
Host smart-3d6084de-7f68-4788-88d2-d9102e56e225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945521126 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.945521126
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.316800953
Short name T542
Test name
Test status
Simulation time 132263696 ps
CPU time 1.84 seconds
Started Jul 17 07:16:25 PM PDT 24
Finished Jul 17 07:16:39 PM PDT 24
Peak memory 215556 kb
Host smart-f2b57223-5612-4c17-b66d-85168d2ac82e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316800953 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.316800953
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1705867762
Short name T217
Test name
Test status
Simulation time 50596262074 ps
CPU time 1048.18 seconds
Started Jul 17 07:16:25 PM PDT 24
Finished Jul 17 07:34:07 PM PDT 24
Peak memory 221064 kb
Host smart-905e9b3e-1d7b-4c4e-bd02-1c0d27ff9d81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705867762 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.1705867762
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.1284931124
Short name T110
Test name
Test status
Simulation time 45126216 ps
CPU time 1.18 seconds
Started Jul 17 07:16:25 PM PDT 24
Finished Jul 17 07:16:39 PM PDT 24
Peak memory 219088 kb
Host smart-35c1d955-8bc0-41f7-a0ed-1076ae43669f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284931124 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.1284931124
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.961621021
Short name T949
Test name
Test status
Simulation time 24478860 ps
CPU time 0.81 seconds
Started Jul 17 07:16:27 PM PDT 24
Finished Jul 17 07:16:42 PM PDT 24
Peak memory 206856 kb
Host smart-0885774f-1b93-4fc5-834e-80e7923c9399
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961621021 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.961621021
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.668279464
Short name T957
Test name
Test status
Simulation time 96364747 ps
CPU time 0.84 seconds
Started Jul 17 07:16:26 PM PDT 24
Finished Jul 17 07:16:40 PM PDT 24
Peak memory 216236 kb
Host smart-5020795d-44f4-4688-b346-20ae295fe4f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668279464 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.668279464
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.821488128
Short name T476
Test name
Test status
Simulation time 72912810 ps
CPU time 1 seconds
Started Jul 17 07:16:28 PM PDT 24
Finished Jul 17 07:16:43 PM PDT 24
Peak memory 219924 kb
Host smart-a6ad6a81-6fe3-413c-9fda-dbfad80e6e7e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821488128 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_di
sable_auto_req_mode.821488128
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.2859871272
Short name T801
Test name
Test status
Simulation time 23093698 ps
CPU time 0.89 seconds
Started Jul 17 07:16:28 PM PDT 24
Finished Jul 17 07:16:46 PM PDT 24
Peak memory 218896 kb
Host smart-4b355ede-4726-4d51-ac16-bd8de04c6355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859871272 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.2859871272
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.3124396108
Short name T472
Test name
Test status
Simulation time 38470463 ps
CPU time 1.24 seconds
Started Jul 17 07:16:28 PM PDT 24
Finished Jul 17 07:16:46 PM PDT 24
Peak memory 217636 kb
Host smart-a58df070-f76c-43d6-a582-b1fb413f656a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124396108 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3124396108
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.97151646
Short name T39
Test name
Test status
Simulation time 25475188 ps
CPU time 0.95 seconds
Started Jul 17 07:16:29 PM PDT 24
Finished Jul 17 07:16:48 PM PDT 24
Peak memory 216240 kb
Host smart-5286b47d-eafe-4631-9cfd-1a17aa75a346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97151646 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.97151646
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.2054877254
Short name T59
Test name
Test status
Simulation time 46250124 ps
CPU time 0.9 seconds
Started Jul 17 07:16:25 PM PDT 24
Finished Jul 17 07:16:39 PM PDT 24
Peak memory 215532 kb
Host smart-f1084b5c-0923-4f75-bcb7-b51a4ed412e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054877254 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.2054877254
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.2376165223
Short name T341
Test name
Test status
Simulation time 247423403 ps
CPU time 4.99 seconds
Started Jul 17 07:16:26 PM PDT 24
Finished Jul 17 07:16:45 PM PDT 24
Peak memory 219996 kb
Host smart-bf2d7cef-2978-476b-82c3-a61592ba00b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376165223 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2376165223
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1664379811
Short name T927
Test name
Test status
Simulation time 44906134841 ps
CPU time 1003.61 seconds
Started Jul 17 07:16:28 PM PDT 24
Finished Jul 17 07:33:28 PM PDT 24
Peak memory 223976 kb
Host smart-49d333e8-0c79-4166-b47d-a90bf15fcc76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664379811 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1664379811
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.1102384057
Short name T383
Test name
Test status
Simulation time 43824680 ps
CPU time 1.19 seconds
Started Jul 17 07:14:37 PM PDT 24
Finished Jul 17 07:14:46 PM PDT 24
Peak memory 218980 kb
Host smart-b935848f-e65f-4a11-aec1-375521f898e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102384057 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.1102384057
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.2874318167
Short name T445
Test name
Test status
Simulation time 31828777 ps
CPU time 0.83 seconds
Started Jul 17 07:14:32 PM PDT 24
Finished Jul 17 07:14:37 PM PDT 24
Peak memory 206976 kb
Host smart-feb22dbe-162e-44d6-8ffb-3cb141c3ae11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874318167 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2874318167
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.1271643319
Short name T788
Test name
Test status
Simulation time 39718665 ps
CPU time 1.24 seconds
Started Jul 17 07:14:34 PM PDT 24
Finished Jul 17 07:14:41 PM PDT 24
Peak memory 217136 kb
Host smart-749c1cdb-b6d3-438f-9412-f8587a2b0ca2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271643319 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.1271643319
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.1472845388
Short name T106
Test name
Test status
Simulation time 27325724 ps
CPU time 1.16 seconds
Started Jul 17 07:14:37 PM PDT 24
Finished Jul 17 07:14:46 PM PDT 24
Peak memory 220796 kb
Host smart-5d02969f-f762-423c-a309-b79336aadc14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472845388 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.1472845388
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.1044318014
Short name T22
Test name
Test status
Simulation time 51952913 ps
CPU time 1.16 seconds
Started Jul 17 07:14:38 PM PDT 24
Finished Jul 17 07:14:46 PM PDT 24
Peak memory 217568 kb
Host smart-425692b3-4eb6-4cc2-b667-b2c5b8cfc204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044318014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1044318014
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.1257949454
Short name T527
Test name
Test status
Simulation time 48527841 ps
CPU time 0.89 seconds
Started Jul 17 07:14:37 PM PDT 24
Finished Jul 17 07:14:45 PM PDT 24
Peak memory 215768 kb
Host smart-6a6d5084-8d2e-4d47-a9b9-ac2f461be686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257949454 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1257949454
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_smoke.3301444226
Short name T567
Test name
Test status
Simulation time 44239739 ps
CPU time 0.88 seconds
Started Jul 17 07:14:39 PM PDT 24
Finished Jul 17 07:14:47 PM PDT 24
Peak memory 215644 kb
Host smart-2a0d65cb-df3d-41f7-9471-859bcc87f537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301444226 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.3301444226
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.1244228499
Short name T757
Test name
Test status
Simulation time 485674707 ps
CPU time 3.09 seconds
Started Jul 17 07:14:37 PM PDT 24
Finished Jul 17 07:14:47 PM PDT 24
Peak memory 217568 kb
Host smart-579970ee-eabd-49a8-8858-f33833d3e639
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244228499 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.1244228499
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1897208595
Short name T918
Test name
Test status
Simulation time 506317435117 ps
CPU time 1869.89 seconds
Started Jul 17 07:14:30 PM PDT 24
Finished Jul 17 07:45:43 PM PDT 24
Peak memory 229204 kb
Host smart-38ed7611-3ff4-438e-8e7e-e2b77e190749
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897208595 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.1897208595
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.4247920155
Short name T253
Test name
Test status
Simulation time 352313504 ps
CPU time 1.2 seconds
Started Jul 17 07:16:30 PM PDT 24
Finished Jul 17 07:16:49 PM PDT 24
Peak memory 221228 kb
Host smart-2227ca11-45a5-4b45-8080-eb862358ec7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247920155 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.4247920155
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.774192427
Short name T808
Test name
Test status
Simulation time 31489948 ps
CPU time 0.93 seconds
Started Jul 17 07:16:29 PM PDT 24
Finished Jul 17 07:16:48 PM PDT 24
Peak memory 218956 kb
Host smart-816e576c-5750-4e16-bec4-eaac114120f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774192427 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.774192427
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.2479488954
Short name T981
Test name
Test status
Simulation time 373390579 ps
CPU time 2.08 seconds
Started Jul 17 07:16:30 PM PDT 24
Finished Jul 17 07:16:49 PM PDT 24
Peak memory 218912 kb
Host smart-73b7e568-dfeb-41fc-b575-daa7c8dcde70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479488954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2479488954
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.2885232989
Short name T541
Test name
Test status
Simulation time 52825764 ps
CPU time 1.04 seconds
Started Jul 17 07:16:30 PM PDT 24
Finished Jul 17 07:16:48 PM PDT 24
Peak memory 218684 kb
Host smart-ac447e3d-e25c-483e-82e3-6f6221bd176a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885232989 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.2885232989
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.568612832
Short name T667
Test name
Test status
Simulation time 23190147 ps
CPU time 0.92 seconds
Started Jul 17 07:16:29 PM PDT 24
Finished Jul 17 07:16:48 PM PDT 24
Peak memory 218764 kb
Host smart-ef09b32f-da77-480e-aca1-35d94f042032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568612832 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.568612832
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.557453671
Short name T654
Test name
Test status
Simulation time 45203450 ps
CPU time 1.37 seconds
Started Jul 17 07:16:29 PM PDT 24
Finished Jul 17 07:16:49 PM PDT 24
Peak memory 219964 kb
Host smart-2ade2d9b-1bbb-4cdc-8bac-cdabf16c9e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557453671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.557453671
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.2716206583
Short name T805
Test name
Test status
Simulation time 87010658 ps
CPU time 1.18 seconds
Started Jul 17 07:16:28 PM PDT 24
Finished Jul 17 07:16:46 PM PDT 24
Peak memory 218760 kb
Host smart-a8c13713-2fbe-48a9-a2ca-6085f43535e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716206583 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.2716206583
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.681802157
Short name T131
Test name
Test status
Simulation time 33948943 ps
CPU time 1.05 seconds
Started Jul 17 07:16:30 PM PDT 24
Finished Jul 17 07:16:50 PM PDT 24
Peak memory 221052 kb
Host smart-51d0859e-adf0-4745-af39-c23564073321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681802157 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.681802157
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.3241950287
Short name T387
Test name
Test status
Simulation time 105396520 ps
CPU time 2.55 seconds
Started Jul 17 07:16:28 PM PDT 24
Finished Jul 17 07:16:48 PM PDT 24
Peak memory 220316 kb
Host smart-87978281-54cb-4f27-b458-ef7aff9a1b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241950287 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3241950287
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.4154361477
Short name T378
Test name
Test status
Simulation time 97599406 ps
CPU time 1.17 seconds
Started Jul 17 07:16:30 PM PDT 24
Finished Jul 17 07:16:50 PM PDT 24
Peak memory 218732 kb
Host smart-bacaed6b-d55c-46cf-85df-13035cc5f238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154361477 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.4154361477
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.4031199776
Short name T124
Test name
Test status
Simulation time 34304149 ps
CPU time 1.4 seconds
Started Jul 17 07:16:30 PM PDT 24
Finished Jul 17 07:16:48 PM PDT 24
Peak memory 225840 kb
Host smart-cc7d5df7-3bb8-4dce-a90b-3155848e72fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031199776 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.4031199776
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.4279446825
Short name T759
Test name
Test status
Simulation time 125082800 ps
CPU time 2.64 seconds
Started Jul 17 07:16:30 PM PDT 24
Finished Jul 17 07:16:49 PM PDT 24
Peak memory 220072 kb
Host smart-bb10d332-6ab7-43cb-abc1-fbd0260e65f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279446825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.4279446825
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.3022807190
Short name T587
Test name
Test status
Simulation time 74086585 ps
CPU time 1.19 seconds
Started Jul 17 07:16:30 PM PDT 24
Finished Jul 17 07:16:48 PM PDT 24
Peak memory 218856 kb
Host smart-31607a26-328b-4af8-8e5d-3c1a030431be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022807190 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.3022807190
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.2400447924
Short name T450
Test name
Test status
Simulation time 17968825 ps
CPU time 1.01 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:28 PM PDT 24
Peak memory 218736 kb
Host smart-5c18e53c-103c-4b74-bcb0-59d3bc28c005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400447924 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.2400447924
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.1231613863
Short name T870
Test name
Test status
Simulation time 300129040 ps
CPU time 1.6 seconds
Started Jul 17 07:16:30 PM PDT 24
Finished Jul 17 07:16:50 PM PDT 24
Peak memory 219112 kb
Host smart-3c656b9b-0aba-4fb4-91cd-fe29334bff5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231613863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1231613863
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.1071484588
Short name T82
Test name
Test status
Simulation time 24456933 ps
CPU time 1.15 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:29 PM PDT 24
Peak memory 219056 kb
Host smart-171529d0-ff29-4072-92bf-8e330fccb87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071484588 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.1071484588
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.2601511885
Short name T7
Test name
Test status
Simulation time 23717512 ps
CPU time 1.03 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:32 PM PDT 24
Peak memory 219956 kb
Host smart-a8064680-933e-40da-943a-2ea47a8f0ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601511885 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2601511885
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.1058631985
Short name T775
Test name
Test status
Simulation time 43895990 ps
CPU time 1.31 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:32 PM PDT 24
Peak memory 218964 kb
Host smart-0e23e75b-484d-4597-bf6b-d218e5a7d146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058631985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.1058631985
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.3757792793
Short name T251
Test name
Test status
Simulation time 44414248 ps
CPU time 1.13 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:32 PM PDT 24
Peak memory 218888 kb
Host smart-1e5fafbe-3d1b-4bbd-bf86-5071a8574171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757792793 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.3757792793
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.3185667136
Short name T706
Test name
Test status
Simulation time 25607232 ps
CPU time 1.16 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:30 PM PDT 24
Peak memory 220244 kb
Host smart-5c92fe83-ecaa-4a16-b20a-4e8cb2fdf7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185667136 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.3185667136
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.3915738661
Short name T451
Test name
Test status
Simulation time 40800332 ps
CPU time 1.52 seconds
Started Jul 17 07:16:24 PM PDT 24
Finished Jul 17 07:16:36 PM PDT 24
Peak memory 217404 kb
Host smart-f5b2de87-5087-4b7f-979c-a105f840374a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915738661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.3915738661
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.2612565236
Short name T810
Test name
Test status
Simulation time 77038373 ps
CPU time 1.17 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:29 PM PDT 24
Peak memory 218852 kb
Host smart-8774b08b-4b58-4224-be0b-be6324825e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612565236 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.2612565236
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.4158242707
Short name T190
Test name
Test status
Simulation time 74720156 ps
CPU time 1.06 seconds
Started Jul 17 07:16:24 PM PDT 24
Finished Jul 17 07:16:36 PM PDT 24
Peak memory 219732 kb
Host smart-0cbb2e1d-3138-4c5c-9e32-1dd3c32eacf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158242707 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.4158242707
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.2938733441
Short name T910
Test name
Test status
Simulation time 54406970 ps
CPU time 1.52 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:31 PM PDT 24
Peak memory 218568 kb
Host smart-c42f42b1-a71c-4220-8bb2-223ba9bd3d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938733441 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2938733441
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.3110777245
Short name T900
Test name
Test status
Simulation time 100288306 ps
CPU time 1.32 seconds
Started Jul 17 07:16:23 PM PDT 24
Finished Jul 17 07:16:34 PM PDT 24
Peak memory 218824 kb
Host smart-1e729a3d-8332-489b-bff4-1c708b6df636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110777245 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.3110777245
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.1487548621
Short name T898
Test name
Test status
Simulation time 43682243 ps
CPU time 1.12 seconds
Started Jul 17 07:16:24 PM PDT 24
Finished Jul 17 07:16:36 PM PDT 24
Peak memory 220004 kb
Host smart-166ba5d8-093a-4166-b3de-59b7daf0bcb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487548621 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.1487548621
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.2407613215
Short name T461
Test name
Test status
Simulation time 78086331 ps
CPU time 0.98 seconds
Started Jul 17 07:16:27 PM PDT 24
Finished Jul 17 07:16:43 PM PDT 24
Peak memory 217600 kb
Host smart-093ff018-fc27-4cf4-8991-bf6ea679b662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407613215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.2407613215
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.2206042214
Short name T947
Test name
Test status
Simulation time 37499641 ps
CPU time 1.07 seconds
Started Jul 17 07:16:25 PM PDT 24
Finished Jul 17 07:16:38 PM PDT 24
Peak memory 218852 kb
Host smart-67870eea-819a-47f2-bf27-8c8b1c024bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206042214 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.2206042214
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.3045909220
Short name T803
Test name
Test status
Simulation time 22438995 ps
CPU time 0.89 seconds
Started Jul 17 07:16:26 PM PDT 24
Finished Jul 17 07:16:41 PM PDT 24
Peak memory 218776 kb
Host smart-8b9c28dd-cd6d-49ec-8de5-17641368ffaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045909220 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.3045909220
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.1420853759
Short name T291
Test name
Test status
Simulation time 54033836 ps
CPU time 1.35 seconds
Started Jul 17 07:16:25 PM PDT 24
Finished Jul 17 07:16:40 PM PDT 24
Peak memory 219140 kb
Host smart-36d27121-f3ce-483f-8add-507a05ae96c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420853759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.1420853759
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.3461591356
Short name T913
Test name
Test status
Simulation time 26030873 ps
CPU time 1.34 seconds
Started Jul 17 07:14:32 PM PDT 24
Finished Jul 17 07:14:38 PM PDT 24
Peak memory 220156 kb
Host smart-8650aed4-302f-43cf-9485-0c3eda9d36df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461591356 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.3461591356
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3707343486
Short name T327
Test name
Test status
Simulation time 14199740 ps
CPU time 0.88 seconds
Started Jul 17 07:14:35 PM PDT 24
Finished Jul 17 07:14:42 PM PDT 24
Peak memory 207056 kb
Host smart-3544e2f7-f158-487d-89fe-ce5dd9211233
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707343486 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3707343486
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.1461440077
Short name T516
Test name
Test status
Simulation time 27317169 ps
CPU time 0.82 seconds
Started Jul 17 07:14:33 PM PDT 24
Finished Jul 17 07:14:39 PM PDT 24
Peak memory 216092 kb
Host smart-97ee6191-b8e4-4656-af66-cfe263332d8d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461440077 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.1461440077
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.4268581959
Short name T464
Test name
Test status
Simulation time 217106346 ps
CPU time 1.15 seconds
Started Jul 17 07:14:32 PM PDT 24
Finished Jul 17 07:14:37 PM PDT 24
Peak memory 217180 kb
Host smart-9afe6554-eaa2-4b7b-aeb4-2f3e6db7345d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268581959 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.4268581959
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.1272195277
Short name T920
Test name
Test status
Simulation time 30199416 ps
CPU time 1.35 seconds
Started Jul 17 07:14:26 PM PDT 24
Finished Jul 17 07:14:28 PM PDT 24
Peak memory 225908 kb
Host smart-b664f295-da39-4f12-a7cd-670cbb30a7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272195277 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.1272195277
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.1620129914
Short name T714
Test name
Test status
Simulation time 163895170 ps
CPU time 1.38 seconds
Started Jul 17 07:14:32 PM PDT 24
Finished Jul 17 07:14:38 PM PDT 24
Peak memory 217452 kb
Host smart-b8ec185d-f034-4e2f-81eb-41d645780804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620129914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.1620129914
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.3575268248
Short name T979
Test name
Test status
Simulation time 87142595 ps
CPU time 1.01 seconds
Started Jul 17 07:14:30 PM PDT 24
Finished Jul 17 07:14:33 PM PDT 24
Peak memory 224148 kb
Host smart-7a836408-5dd5-47c9-b243-d3d4203f0e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575268248 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.3575268248
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.3574147754
Short name T270
Test name
Test status
Simulation time 14519706 ps
CPU time 0.93 seconds
Started Jul 17 07:14:34 PM PDT 24
Finished Jul 17 07:14:41 PM PDT 24
Peak memory 207300 kb
Host smart-4a427032-eb6c-4b27-b263-8fc5d80ad1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574147754 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.3574147754
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.2961297996
Short name T558
Test name
Test status
Simulation time 28035687 ps
CPU time 0.94 seconds
Started Jul 17 07:14:33 PM PDT 24
Finished Jul 17 07:14:38 PM PDT 24
Peak memory 215468 kb
Host smart-92c12dcf-cda2-437b-8539-f31525431f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961297996 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.2961297996
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.3926331274
Short name T717
Test name
Test status
Simulation time 455791491 ps
CPU time 5.18 seconds
Started Jul 17 07:14:31 PM PDT 24
Finished Jul 17 07:14:39 PM PDT 24
Peak memory 219044 kb
Host smart-e64ba16e-81f4-42be-991c-afdd4dd97aff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926331274 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.3926331274
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.4004202493
Short name T368
Test name
Test status
Simulation time 43083197287 ps
CPU time 1106.33 seconds
Started Jul 17 07:14:30 PM PDT 24
Finished Jul 17 07:32:58 PM PDT 24
Peak memory 223940 kb
Host smart-7c924956-ab3e-4ece-a691-6dc6f7262e04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004202493 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.4004202493
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.2942190318
Short name T581
Test name
Test status
Simulation time 21776848 ps
CPU time 1.09 seconds
Started Jul 17 07:16:25 PM PDT 24
Finished Jul 17 07:16:38 PM PDT 24
Peak memory 218968 kb
Host smart-bb472197-cbd5-462d-9dbe-c39267b75f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942190318 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.2942190318
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_genbits.3559729567
Short name T851
Test name
Test status
Simulation time 47290564 ps
CPU time 1.4 seconds
Started Jul 17 07:16:24 PM PDT 24
Finished Jul 17 07:16:37 PM PDT 24
Peak memory 218708 kb
Host smart-8331f7e6-98da-479f-8ed7-3debe8160a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559729567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3559729567
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.1171379008
Short name T633
Test name
Test status
Simulation time 25408450 ps
CPU time 1.15 seconds
Started Jul 17 07:16:25 PM PDT 24
Finished Jul 17 07:16:40 PM PDT 24
Peak memory 221328 kb
Host smart-bd0a32c7-a0f2-43a3-9da1-75e58bd85524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171379008 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.1171379008
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.1556991053
Short name T839
Test name
Test status
Simulation time 76463644 ps
CPU time 0.84 seconds
Started Jul 17 07:16:27 PM PDT 24
Finished Jul 17 07:16:43 PM PDT 24
Peak memory 219760 kb
Host smart-1959383c-ece5-4018-b54a-7e6b592e83dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556991053 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1556991053
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.3236188739
Short name T403
Test name
Test status
Simulation time 62031620 ps
CPU time 1.52 seconds
Started Jul 17 07:16:26 PM PDT 24
Finished Jul 17 07:16:41 PM PDT 24
Peak memory 219044 kb
Host smart-82d71908-c00f-4aa9-b605-10b789c25378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236188739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.3236188739
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.2515963238
Short name T651
Test name
Test status
Simulation time 80740006 ps
CPU time 1.15 seconds
Started Jul 17 07:16:28 PM PDT 24
Finished Jul 17 07:16:44 PM PDT 24
Peak memory 218776 kb
Host smart-d69aea8b-744b-453a-971a-260bbdccc9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515963238 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.2515963238
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.2299769881
Short name T353
Test name
Test status
Simulation time 40980302 ps
CPU time 1.1 seconds
Started Jul 17 07:16:28 PM PDT 24
Finished Jul 17 07:16:46 PM PDT 24
Peak memory 218956 kb
Host smart-366d3aff-2187-44c5-8df9-8af19cfd98d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299769881 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.2299769881
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.79456113
Short name T814
Test name
Test status
Simulation time 59310349 ps
CPU time 1.63 seconds
Started Jul 17 07:16:27 PM PDT 24
Finished Jul 17 07:16:44 PM PDT 24
Peak memory 218804 kb
Host smart-98485369-3566-4c65-a71d-fb20516b5a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79456113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.79456113
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.2614359698
Short name T912
Test name
Test status
Simulation time 45964581 ps
CPU time 1.14 seconds
Started Jul 17 07:16:26 PM PDT 24
Finished Jul 17 07:16:41 PM PDT 24
Peak memory 218908 kb
Host smart-5af716be-3d45-4255-9aeb-8918d80b39c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614359698 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.2614359698
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.2007798748
Short name T781
Test name
Test status
Simulation time 18832227 ps
CPU time 1.01 seconds
Started Jul 17 07:16:28 PM PDT 24
Finished Jul 17 07:16:43 PM PDT 24
Peak memory 218700 kb
Host smart-f7f46ed4-6fcf-42b4-89da-541efe89676c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007798748 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.2007798748
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.4134569221
Short name T301
Test name
Test status
Simulation time 51407292 ps
CPU time 1.38 seconds
Started Jul 17 07:16:28 PM PDT 24
Finished Jul 17 07:16:44 PM PDT 24
Peak memory 219208 kb
Host smart-e943dea9-bf89-494c-804e-01a8cd62807f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134569221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.4134569221
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.51035391
Short name T694
Test name
Test status
Simulation time 55871367 ps
CPU time 1.13 seconds
Started Jul 17 07:16:25 PM PDT 24
Finished Jul 17 07:16:38 PM PDT 24
Peak memory 219168 kb
Host smart-87972306-6edd-46ab-b13a-2067b32e9ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51035391 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.51035391
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.1899977147
Short name T347
Test name
Test status
Simulation time 22923328 ps
CPU time 0.92 seconds
Started Jul 17 07:16:29 PM PDT 24
Finished Jul 17 07:16:48 PM PDT 24
Peak memory 218828 kb
Host smart-cfd584aa-5039-443e-9198-ed9ca1a0ada0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899977147 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.1899977147
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.126809648
Short name T292
Test name
Test status
Simulation time 50761941 ps
CPU time 1.68 seconds
Started Jul 17 07:16:26 PM PDT 24
Finished Jul 17 07:16:41 PM PDT 24
Peak memory 218768 kb
Host smart-28d4ad6c-b632-47b3-9000-97999283ebe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126809648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.126809648
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.1732374984
Short name T677
Test name
Test status
Simulation time 27084013 ps
CPU time 1.21 seconds
Started Jul 17 07:16:26 PM PDT 24
Finished Jul 17 07:16:41 PM PDT 24
Peak memory 218832 kb
Host smart-f46404b4-1822-478c-be16-6490d7ddf64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732374984 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.1732374984
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.2518066542
Short name T116
Test name
Test status
Simulation time 53499651 ps
CPU time 1.04 seconds
Started Jul 17 07:16:30 PM PDT 24
Finished Jul 17 07:16:48 PM PDT 24
Peak memory 219964 kb
Host smart-d97c4b0e-d02f-400b-a2a6-feaf150ba321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518066542 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.2518066542
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.2351109300
Short name T375
Test name
Test status
Simulation time 185307544 ps
CPU time 2.83 seconds
Started Jul 17 07:16:29 PM PDT 24
Finished Jul 17 07:16:48 PM PDT 24
Peak memory 219420 kb
Host smart-27a93c65-6f70-409d-b523-552b8ce6b263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351109300 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.2351109300
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.4031035234
Short name T820
Test name
Test status
Simulation time 26278704 ps
CPU time 1.22 seconds
Started Jul 17 07:16:29 PM PDT 24
Finished Jul 17 07:16:49 PM PDT 24
Peak memory 218912 kb
Host smart-927abe8e-055f-4363-9218-57df31745332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031035234 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.4031035234
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.1801647815
Short name T50
Test name
Test status
Simulation time 36991015 ps
CPU time 0.92 seconds
Started Jul 17 07:16:27 PM PDT 24
Finished Jul 17 07:16:43 PM PDT 24
Peak memory 224084 kb
Host smart-d41cd894-f932-473f-b4bf-da51a64a7c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801647815 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1801647815
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.201465174
Short name T314
Test name
Test status
Simulation time 102245119 ps
CPU time 1.14 seconds
Started Jul 17 07:16:28 PM PDT 24
Finished Jul 17 07:16:46 PM PDT 24
Peak memory 215420 kb
Host smart-5500d374-e770-482c-89a8-0f2e219071eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201465174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.201465174
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.2978217914
Short name T532
Test name
Test status
Simulation time 63264116 ps
CPU time 1.05 seconds
Started Jul 17 07:16:29 PM PDT 24
Finished Jul 17 07:16:48 PM PDT 24
Peak memory 219728 kb
Host smart-b1aa8c55-9e5a-42f7-a865-334a1a1b64ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978217914 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.2978217914
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.676176597
Short name T807
Test name
Test status
Simulation time 27940658 ps
CPU time 1.2 seconds
Started Jul 17 07:16:29 PM PDT 24
Finished Jul 17 07:16:46 PM PDT 24
Peak memory 219968 kb
Host smart-56696fb5-9554-4f47-b536-aa68dbd7ee90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676176597 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.676176597
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/68.edn_alert.166134041
Short name T661
Test name
Test status
Simulation time 248811431 ps
CPU time 1.45 seconds
Started Jul 17 07:16:30 PM PDT 24
Finished Jul 17 07:16:50 PM PDT 24
Peak memory 220508 kb
Host smart-3648bbf1-9acf-4234-b538-60cc68a8310c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166134041 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.166134041
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.211434168
Short name T152
Test name
Test status
Simulation time 19348576 ps
CPU time 1.04 seconds
Started Jul 17 07:16:31 PM PDT 24
Finished Jul 17 07:16:50 PM PDT 24
Peak memory 219068 kb
Host smart-8939672d-de63-43e9-bfd2-8c4817552e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211434168 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.211434168
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.3931144047
Short name T785
Test name
Test status
Simulation time 188023166 ps
CPU time 1.08 seconds
Started Jul 17 07:16:29 PM PDT 24
Finished Jul 17 07:16:48 PM PDT 24
Peak memory 217612 kb
Host smart-5059b030-5e3f-4574-ac4a-58703fc6989a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931144047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.3931144047
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.2753188891
Short name T221
Test name
Test status
Simulation time 250039562 ps
CPU time 1.25 seconds
Started Jul 17 07:16:30 PM PDT 24
Finished Jul 17 07:16:48 PM PDT 24
Peak memory 219284 kb
Host smart-090620c2-35e2-4b10-b837-f2301d4d7d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753188891 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.2753188891
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.3958577918
Short name T978
Test name
Test status
Simulation time 46120992 ps
CPU time 0.98 seconds
Started Jul 17 07:16:30 PM PDT 24
Finished Jul 17 07:16:48 PM PDT 24
Peak memory 218952 kb
Host smart-209bf884-e496-4763-a4ab-683672250913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958577918 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.3958577918
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.2775439269
Short name T401
Test name
Test status
Simulation time 62906885 ps
CPU time 1.56 seconds
Started Jul 17 07:16:30 PM PDT 24
Finished Jul 17 07:16:48 PM PDT 24
Peak memory 218628 kb
Host smart-7a1f869a-c0d4-44af-96bb-c94d104d3634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775439269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.2775439269
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.1314769325
Short name T809
Test name
Test status
Simulation time 23741930 ps
CPU time 1.23 seconds
Started Jul 17 07:14:31 PM PDT 24
Finished Jul 17 07:14:36 PM PDT 24
Peak memory 220524 kb
Host smart-319522a2-94a0-416a-9886-0b938cc494a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314769325 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1314769325
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.3432237258
Short name T959
Test name
Test status
Simulation time 34962633 ps
CPU time 0.85 seconds
Started Jul 17 07:14:56 PM PDT 24
Finished Jul 17 07:14:58 PM PDT 24
Peak memory 215492 kb
Host smart-e6b59f1a-0042-408b-ada0-a19c0f4ca6a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432237258 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.3432237258
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.1851354269
Short name T946
Test name
Test status
Simulation time 32673261 ps
CPU time 1.12 seconds
Started Jul 17 07:14:52 PM PDT 24
Finished Jul 17 07:14:55 PM PDT 24
Peak memory 217084 kb
Host smart-a8d9f1f1-8689-42d1-8b9a-f463b6f8c9df
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851354269 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.1851354269
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.1123132011
Short name T123
Test name
Test status
Simulation time 22757270 ps
CPU time 1.11 seconds
Started Jul 17 07:14:33 PM PDT 24
Finished Jul 17 07:14:39 PM PDT 24
Peak memory 218736 kb
Host smart-653d0ed4-86fe-4a5d-ae9c-f93901c5f665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123132011 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.1123132011
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.2033408737
Short name T333
Test name
Test status
Simulation time 32571359 ps
CPU time 1.39 seconds
Started Jul 17 07:14:31 PM PDT 24
Finished Jul 17 07:14:36 PM PDT 24
Peak memory 215540 kb
Host smart-6bf4c327-b579-4cb7-87a1-2840ec98b412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033408737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.2033408737
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.2885270178
Short name T574
Test name
Test status
Simulation time 24239432 ps
CPU time 0.93 seconds
Started Jul 17 07:14:31 PM PDT 24
Finished Jul 17 07:14:36 PM PDT 24
Peak memory 215812 kb
Host smart-ed8873ac-2b1d-4aec-9121-b69120fca2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885270178 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.2885270178
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.2397384664
Short name T428
Test name
Test status
Simulation time 98010960 ps
CPU time 0.87 seconds
Started Jul 17 07:14:36 PM PDT 24
Finished Jul 17 07:14:43 PM PDT 24
Peak memory 207188 kb
Host smart-15d9a3c2-3a1d-4b37-a751-e4cbb5f47114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397384664 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.2397384664
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.311399889
Short name T370
Test name
Test status
Simulation time 133280021 ps
CPU time 0.95 seconds
Started Jul 17 07:14:31 PM PDT 24
Finished Jul 17 07:14:35 PM PDT 24
Peak memory 215228 kb
Host smart-b3de8b9d-9786-486c-97a1-cb4e36b98805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311399889 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.311399889
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.3121489863
Short name T535
Test name
Test status
Simulation time 218499381 ps
CPU time 4.28 seconds
Started Jul 17 07:14:31 PM PDT 24
Finished Jul 17 07:14:39 PM PDT 24
Peak memory 217600 kb
Host smart-7188c380-ce91-4fa4-a3b9-365c7b6f5a0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121489863 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.3121489863
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.3574304147
Short name T601
Test name
Test status
Simulation time 46549064928 ps
CPU time 1082.39 seconds
Started Jul 17 07:14:33 PM PDT 24
Finished Jul 17 07:32:40 PM PDT 24
Peak memory 219528 kb
Host smart-fa1c6462-53d2-49f5-871d-4541ecc02aa3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574304147 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.3574304147
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.2813144101
Short name T943
Test name
Test status
Simulation time 196806538 ps
CPU time 1.21 seconds
Started Jul 17 07:16:30 PM PDT 24
Finished Jul 17 07:16:48 PM PDT 24
Peak memory 220076 kb
Host smart-04ad80bc-687a-4436-a08e-3a26e4a6febd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813144101 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.2813144101
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.3744779995
Short name T487
Test name
Test status
Simulation time 24596967 ps
CPU time 0.98 seconds
Started Jul 17 07:16:30 PM PDT 24
Finished Jul 17 07:16:48 PM PDT 24
Peak memory 224280 kb
Host smart-d31849fe-9a11-4501-815e-45783a261c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744779995 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.3744779995
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.3301856809
Short name T514
Test name
Test status
Simulation time 47780392 ps
CPU time 1.63 seconds
Started Jul 17 07:16:31 PM PDT 24
Finished Jul 17 07:16:50 PM PDT 24
Peak memory 217552 kb
Host smart-c4c9448a-c1a1-4104-be3a-bd99c251fd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301856809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3301856809
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.2389542736
Short name T112
Test name
Test status
Simulation time 51615017 ps
CPU time 1.23 seconds
Started Jul 17 07:16:23 PM PDT 24
Finished Jul 17 07:16:34 PM PDT 24
Peak memory 219096 kb
Host smart-f59be76b-df84-4f12-b852-f4af045ff783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389542736 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.2389542736
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.3149145882
Short name T942
Test name
Test status
Simulation time 19206914 ps
CPU time 1.14 seconds
Started Jul 17 07:16:23 PM PDT 24
Finished Jul 17 07:16:33 PM PDT 24
Peak memory 224252 kb
Host smart-c435be25-1a94-4aa7-98c0-7a37081dac22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149145882 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.3149145882
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.11277296
Short name T680
Test name
Test status
Simulation time 52282791 ps
CPU time 1.44 seconds
Started Jul 17 07:16:31 PM PDT 24
Finished Jul 17 07:16:50 PM PDT 24
Peak memory 217608 kb
Host smart-747e1de8-00d5-48fa-8ad4-9c0557338fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11277296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.11277296
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.3899460104
Short name T819
Test name
Test status
Simulation time 91733420 ps
CPU time 1.27 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:32 PM PDT 24
Peak memory 220052 kb
Host smart-34258870-6ee7-44d7-9927-3bb0b752de38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899460104 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.3899460104
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.396269387
Short name T936
Test name
Test status
Simulation time 25789053 ps
CPU time 0.87 seconds
Started Jul 17 07:16:21 PM PDT 24
Finished Jul 17 07:16:28 PM PDT 24
Peak memory 218748 kb
Host smart-6a0200cd-b45b-4514-8d5b-907650d18687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396269387 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.396269387
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.3893721048
Short name T20
Test name
Test status
Simulation time 274463079 ps
CPU time 3.12 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:31 PM PDT 24
Peak memory 215668 kb
Host smart-ca6056a6-16f3-492c-8356-7abaf7992a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893721048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.3893721048
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.1808188296
Short name T83
Test name
Test status
Simulation time 93243322 ps
CPU time 1.23 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:29 PM PDT 24
Peak memory 220104 kb
Host smart-9e34d964-4254-4240-af92-b7c2327efe86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808188296 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.1808188296
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.1743429124
Short name T963
Test name
Test status
Simulation time 27300215 ps
CPU time 1.05 seconds
Started Jul 17 07:16:23 PM PDT 24
Finished Jul 17 07:16:32 PM PDT 24
Peak memory 224324 kb
Host smart-34ed8163-ee36-4beb-8a43-c0c1914d01a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743429124 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1743429124
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1445228453
Short name T474
Test name
Test status
Simulation time 101795304 ps
CPU time 1.54 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:32 PM PDT 24
Peak memory 217776 kb
Host smart-537fc461-09f7-4aab-9c2e-ff49d313c176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445228453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1445228453
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.103800061
Short name T632
Test name
Test status
Simulation time 64268918 ps
CPU time 1.1 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:32 PM PDT 24
Peak memory 220188 kb
Host smart-dc18b0b2-d85a-41c4-bab7-f13c5e5b858d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103800061 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.103800061
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.387895519
Short name T158
Test name
Test status
Simulation time 37454760 ps
CPU time 0.84 seconds
Started Jul 17 07:16:21 PM PDT 24
Finished Jul 17 07:16:26 PM PDT 24
Peak memory 218640 kb
Host smart-09715217-014c-48f7-8017-4c01f1ee347f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387895519 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.387895519
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.3918733277
Short name T894
Test name
Test status
Simulation time 161713653 ps
CPU time 3.18 seconds
Started Jul 17 07:16:21 PM PDT 24
Finished Jul 17 07:16:28 PM PDT 24
Peak memory 220512 kb
Host smart-2f582324-808e-478d-a718-ad103d6ff6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918733277 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.3918733277
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.308482068
Short name T652
Test name
Test status
Simulation time 21244148 ps
CPU time 1.08 seconds
Started Jul 17 07:16:25 PM PDT 24
Finished Jul 17 07:16:37 PM PDT 24
Peak memory 218828 kb
Host smart-72d04128-fb60-4644-af1e-ababd17e8b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308482068 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.308482068
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.1076312657
Short name T519
Test name
Test status
Simulation time 45099287 ps
CPU time 1.15 seconds
Started Jul 17 07:16:25 PM PDT 24
Finished Jul 17 07:16:38 PM PDT 24
Peak memory 219936 kb
Host smart-36abd956-920c-4f2f-9b44-c5386fc0cd60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076312657 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.1076312657
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.1350630031
Short name T313
Test name
Test status
Simulation time 44934728 ps
CPU time 1.17 seconds
Started Jul 17 07:16:24 PM PDT 24
Finished Jul 17 07:16:38 PM PDT 24
Peak memory 218824 kb
Host smart-d936e9df-551d-42a5-99c3-ecdb193ab4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350630031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.1350630031
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.2275264703
Short name T795
Test name
Test status
Simulation time 86263509 ps
CPU time 1.03 seconds
Started Jul 17 07:16:28 PM PDT 24
Finished Jul 17 07:16:46 PM PDT 24
Peak memory 218744 kb
Host smart-b4aeacd3-7092-4379-91fb-2108e9be9352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275264703 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.2275264703
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.4265449593
Short name T545
Test name
Test status
Simulation time 21957693 ps
CPU time 0.9 seconds
Started Jul 17 07:16:27 PM PDT 24
Finished Jul 17 07:16:43 PM PDT 24
Peak memory 218980 kb
Host smart-afde1b06-5897-48c0-a69c-aa26ed1ebdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265449593 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.4265449593
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.115666519
Short name T611
Test name
Test status
Simulation time 34288295 ps
CPU time 1.18 seconds
Started Jul 17 07:16:24 PM PDT 24
Finished Jul 17 07:16:37 PM PDT 24
Peak memory 217548 kb
Host smart-ed3c234a-a1f9-4a73-9941-f7ebb159cba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115666519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.115666519
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.699626349
Short name T72
Test name
Test status
Simulation time 248112481 ps
CPU time 1.11 seconds
Started Jul 17 07:16:27 PM PDT 24
Finished Jul 17 07:16:43 PM PDT 24
Peak memory 220244 kb
Host smart-9f76d793-19d2-452f-86d3-e47a8b005043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699626349 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.699626349
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.4049250156
Short name T170
Test name
Test status
Simulation time 51732672 ps
CPU time 0.93 seconds
Started Jul 17 07:16:28 PM PDT 24
Finished Jul 17 07:16:46 PM PDT 24
Peak memory 223876 kb
Host smart-a0466d69-e797-42a2-97a7-4dcc2f9e0fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049250156 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.4049250156
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.2740903419
Short name T488
Test name
Test status
Simulation time 34846644 ps
CPU time 1.39 seconds
Started Jul 17 07:16:25 PM PDT 24
Finished Jul 17 07:16:40 PM PDT 24
Peak memory 220200 kb
Host smart-3674a2b5-6a74-4231-a68d-3fb8c0bb6cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740903419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.2740903419
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.1599522698
Short name T63
Test name
Test status
Simulation time 44299305 ps
CPU time 1.14 seconds
Started Jul 17 07:16:26 PM PDT 24
Finished Jul 17 07:16:42 PM PDT 24
Peak memory 219412 kb
Host smart-d42a986f-cb8f-4e1b-a31d-15fe5a0fff19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599522698 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.1599522698
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.218494525
Short name T54
Test name
Test status
Simulation time 22597110 ps
CPU time 1.06 seconds
Started Jul 17 07:16:27 PM PDT 24
Finished Jul 17 07:16:43 PM PDT 24
Peak memory 224256 kb
Host smart-612bcd43-0bf7-41ca-baa2-941f2ed313ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218494525 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.218494525
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.3130129840
Short name T70
Test name
Test status
Simulation time 72571644 ps
CPU time 1.43 seconds
Started Jul 17 07:16:26 PM PDT 24
Finished Jul 17 07:16:42 PM PDT 24
Peak memory 217560 kb
Host smart-4803f625-2bda-4498-93b4-ebf1196fc32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130129840 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.3130129840
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.1368390393
Short name T876
Test name
Test status
Simulation time 60111400 ps
CPU time 1.17 seconds
Started Jul 17 07:16:25 PM PDT 24
Finished Jul 17 07:16:39 PM PDT 24
Peak memory 219180 kb
Host smart-5c4bc238-6dac-48e3-9aa4-f5449098d3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368390393 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.1368390393
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.1044669331
Short name T522
Test name
Test status
Simulation time 23980266 ps
CPU time 0.95 seconds
Started Jul 17 07:16:28 PM PDT 24
Finished Jul 17 07:16:46 PM PDT 24
Peak memory 218748 kb
Host smart-b9a93701-fbb0-4fcf-9097-5b8e15113bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044669331 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.1044669331
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.1356246800
Short name T780
Test name
Test status
Simulation time 50551732 ps
CPU time 1.34 seconds
Started Jul 17 07:16:26 PM PDT 24
Finished Jul 17 07:16:42 PM PDT 24
Peak memory 218860 kb
Host smart-80bf2abd-7850-4053-9278-9a229ec3f6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356246800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.1356246800
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.2977894951
Short name T899
Test name
Test status
Simulation time 51264944 ps
CPU time 1.15 seconds
Started Jul 17 07:14:56 PM PDT 24
Finished Jul 17 07:14:59 PM PDT 24
Peak memory 216012 kb
Host smart-627380bf-1103-493f-b403-ea2061f9ffc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977894951 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.2977894951
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.3507921961
Short name T407
Test name
Test status
Simulation time 22607417 ps
CPU time 0.99 seconds
Started Jul 17 07:14:54 PM PDT 24
Finished Jul 17 07:14:56 PM PDT 24
Peak memory 215240 kb
Host smart-ff60a905-b024-4ef1-8fd3-840b0880af12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507921961 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3507921961
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.4228678293
Short name T408
Test name
Test status
Simulation time 19807324 ps
CPU time 0.84 seconds
Started Jul 17 07:14:57 PM PDT 24
Finished Jul 17 07:15:03 PM PDT 24
Peak memory 216668 kb
Host smart-3161c3da-b921-4a6b-9c9c-be0d44bdd309
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228678293 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.4228678293
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.1050612240
Short name T862
Test name
Test status
Simulation time 38019113 ps
CPU time 1.27 seconds
Started Jul 17 07:14:59 PM PDT 24
Finished Jul 17 07:15:13 PM PDT 24
Peak memory 217240 kb
Host smart-b0a30d15-f790-4179-8e92-83c522fa2223
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050612240 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.1050612240
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.1423839087
Short name T624
Test name
Test status
Simulation time 19376962 ps
CPU time 1.05 seconds
Started Jul 17 07:14:50 PM PDT 24
Finished Jul 17 07:14:52 PM PDT 24
Peak memory 218864 kb
Host smart-6b86f68a-1071-4b9f-8e83-f15154c54f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423839087 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.1423839087
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.2595950198
Short name T953
Test name
Test status
Simulation time 89060095 ps
CPU time 1.7 seconds
Started Jul 17 07:14:50 PM PDT 24
Finished Jul 17 07:14:53 PM PDT 24
Peak memory 220232 kb
Host smart-e5116c72-0a4f-48e6-a009-4dfad468ad32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595950198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.2595950198
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.2539519638
Short name T642
Test name
Test status
Simulation time 29093362 ps
CPU time 1.01 seconds
Started Jul 17 07:14:52 PM PDT 24
Finished Jul 17 07:14:55 PM PDT 24
Peak memory 224320 kb
Host smart-7f84962d-68cd-4a5a-8735-78d98250e8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539519638 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2539519638
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.1468543909
Short name T28
Test name
Test status
Simulation time 16740823 ps
CPU time 0.97 seconds
Started Jul 17 07:14:50 PM PDT 24
Finished Jul 17 07:14:51 PM PDT 24
Peak memory 207360 kb
Host smart-08662a81-fdfc-4388-9261-11ba7b4bfa99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468543909 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.1468543909
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.3563549414
Short name T444
Test name
Test status
Simulation time 31851494 ps
CPU time 0.95 seconds
Started Jul 17 07:14:56 PM PDT 24
Finished Jul 17 07:15:01 PM PDT 24
Peak memory 215744 kb
Host smart-47fc309b-bf7b-40dd-b3f0-ffb93eb1d649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563549414 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.3563549414
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.319451193
Short name T430
Test name
Test status
Simulation time 1901472823 ps
CPU time 4.36 seconds
Started Jul 17 07:14:52 PM PDT 24
Finished Jul 17 07:14:58 PM PDT 24
Peak memory 215556 kb
Host smart-6690c512-f79c-41a3-b0b4-813ccd071b0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319451193 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.319451193
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.1059560270
Short name T211
Test name
Test status
Simulation time 96422146518 ps
CPU time 1125.5 seconds
Started Jul 17 07:14:52 PM PDT 24
Finished Jul 17 07:33:40 PM PDT 24
Peak memory 223348 kb
Host smart-f12fb649-cb0b-4247-9abb-262f94fb7f77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059560270 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.1059560270
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.1132272639
Short name T32
Test name
Test status
Simulation time 151872455 ps
CPU time 1.29 seconds
Started Jul 17 07:16:29 PM PDT 24
Finished Jul 17 07:16:49 PM PDT 24
Peak memory 216012 kb
Host smart-6e850b51-a86a-49cc-98bb-22bbb46e1366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132272639 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.1132272639
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.1408740701
Short name T740
Test name
Test status
Simulation time 28360897 ps
CPU time 1.02 seconds
Started Jul 17 07:16:28 PM PDT 24
Finished Jul 17 07:16:46 PM PDT 24
Peak memory 224108 kb
Host smart-729022ad-1ff1-40cf-a98f-a1aa0e941dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408740701 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.1408740701
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.1038900573
Short name T991
Test name
Test status
Simulation time 150001018 ps
CPU time 1.11 seconds
Started Jul 17 07:16:28 PM PDT 24
Finished Jul 17 07:16:43 PM PDT 24
Peak memory 217764 kb
Host smart-f3358013-251f-4e9a-990a-de51119a6413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038900573 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.1038900573
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.1940474938
Short name T126
Test name
Test status
Simulation time 104685570 ps
CPU time 1.12 seconds
Started Jul 17 07:16:29 PM PDT 24
Finished Jul 17 07:16:49 PM PDT 24
Peak memory 220984 kb
Host smart-320a4de0-e5eb-49c7-a199-d454fb8fd30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940474938 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.1940474938
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.3515875616
Short name T98
Test name
Test status
Simulation time 49300672 ps
CPU time 1.03 seconds
Started Jul 17 07:16:29 PM PDT 24
Finished Jul 17 07:16:46 PM PDT 24
Peak memory 229908 kb
Host smart-22af422a-a700-4637-909f-f14d3ba7a195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515875616 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.3515875616
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.3799645020
Short name T566
Test name
Test status
Simulation time 312379128 ps
CPU time 1.95 seconds
Started Jul 17 07:16:29 PM PDT 24
Finished Jul 17 07:16:49 PM PDT 24
Peak memory 219196 kb
Host smart-117ea5cb-2a96-463f-b701-8907e22e172e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799645020 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3799645020
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.4049220758
Short name T129
Test name
Test status
Simulation time 27638727 ps
CPU time 1.18 seconds
Started Jul 17 07:16:27 PM PDT 24
Finished Jul 17 07:16:43 PM PDT 24
Peak memory 218820 kb
Host smart-aee61d9d-2ea4-4ea0-8d04-cf622ddd346b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049220758 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.4049220758
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.2203893285
Short name T113
Test name
Test status
Simulation time 25483722 ps
CPU time 1.26 seconds
Started Jul 17 07:16:28 PM PDT 24
Finished Jul 17 07:16:43 PM PDT 24
Peak memory 229928 kb
Host smart-1137f2b0-e2e2-4203-bdd6-5765969b365f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203893285 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.2203893285
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.2419677633
Short name T337
Test name
Test status
Simulation time 30898589 ps
CPU time 1.22 seconds
Started Jul 17 07:16:29 PM PDT 24
Finished Jul 17 07:16:48 PM PDT 24
Peak memory 217732 kb
Host smart-22c5b0c3-ae7e-4719-a489-a45f71901be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419677633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.2419677633
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.148233962
Short name T552
Test name
Test status
Simulation time 43856436 ps
CPU time 1.19 seconds
Started Jul 17 07:16:27 PM PDT 24
Finished Jul 17 07:16:43 PM PDT 24
Peak memory 219236 kb
Host smart-fbd784a0-fe1d-4cac-9b62-eb0ccfa8e227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148233962 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.148233962
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.3574824391
Short name T738
Test name
Test status
Simulation time 21517623 ps
CPU time 1.02 seconds
Started Jul 17 07:16:28 PM PDT 24
Finished Jul 17 07:16:46 PM PDT 24
Peak memory 224244 kb
Host smart-848fecd7-3c91-4f32-af17-d12ddacad74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574824391 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.3574824391
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.2120877965
Short name T895
Test name
Test status
Simulation time 69982806 ps
CPU time 1.03 seconds
Started Jul 17 07:16:29 PM PDT 24
Finished Jul 17 07:16:46 PM PDT 24
Peak memory 217724 kb
Host smart-901a262e-dd9a-4603-9321-0b90431fab89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120877965 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.2120877965
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.1115793845
Short name T688
Test name
Test status
Simulation time 24800630 ps
CPU time 1.17 seconds
Started Jul 17 07:16:28 PM PDT 24
Finished Jul 17 07:16:46 PM PDT 24
Peak memory 220108 kb
Host smart-4c512f6a-97f7-4e96-baf9-ccab8c114770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115793845 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.1115793845
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.2841107254
Short name T564
Test name
Test status
Simulation time 18917861 ps
CPU time 1.01 seconds
Started Jul 17 07:16:29 PM PDT 24
Finished Jul 17 07:16:48 PM PDT 24
Peak memory 219092 kb
Host smart-6e80889b-aaca-4976-8fe8-5e16ec19a034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841107254 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.2841107254
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.88546282
Short name T845
Test name
Test status
Simulation time 58777387 ps
CPU time 1.65 seconds
Started Jul 17 07:16:30 PM PDT 24
Finished Jul 17 07:16:49 PM PDT 24
Peak memory 218712 kb
Host smart-bfba47d7-0109-40fb-9829-67322239c63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88546282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.88546282
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.1191685934
Short name T929
Test name
Test status
Simulation time 24443724 ps
CPU time 1.1 seconds
Started Jul 17 07:16:30 PM PDT 24
Finished Jul 17 07:16:48 PM PDT 24
Peak memory 221052 kb
Host smart-0a61dd1d-295b-46c4-a2d6-1ab15bda1712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191685934 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.1191685934
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.3527828102
Short name T524
Test name
Test status
Simulation time 23697836 ps
CPU time 0.91 seconds
Started Jul 17 07:16:30 PM PDT 24
Finished Jul 17 07:16:48 PM PDT 24
Peak memory 218956 kb
Host smart-69f60412-fbea-4e63-baa1-b11e8a5f4048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527828102 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.3527828102
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.1218226993
Short name T790
Test name
Test status
Simulation time 66065268 ps
CPU time 1.42 seconds
Started Jul 17 07:16:30 PM PDT 24
Finished Jul 17 07:16:49 PM PDT 24
Peak memory 219028 kb
Host smart-51d70b9e-7fae-46e7-b24e-94576c1f4bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218226993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.1218226993
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.598707168
Short name T460
Test name
Test status
Simulation time 24993783 ps
CPU time 1.18 seconds
Started Jul 17 07:16:30 PM PDT 24
Finished Jul 17 07:16:49 PM PDT 24
Peak memory 219068 kb
Host smart-7b7de32b-7a74-45c8-a2dc-29f4ca336359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598707168 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.598707168
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.2870106561
Short name T53
Test name
Test status
Simulation time 35399213 ps
CPU time 1.03 seconds
Started Jul 17 07:16:31 PM PDT 24
Finished Jul 17 07:16:50 PM PDT 24
Peak memory 224048 kb
Host smart-67cd235f-641c-4cb3-a057-7969eacf03b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870106561 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2870106561
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.1548866269
Short name T371
Test name
Test status
Simulation time 202494410 ps
CPU time 3.67 seconds
Started Jul 17 07:16:31 PM PDT 24
Finished Jul 17 07:16:52 PM PDT 24
Peak memory 217936 kb
Host smart-a72437e4-9753-477e-81b5-0344c0661dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548866269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.1548866269
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.72622916
Short name T732
Test name
Test status
Simulation time 36469112 ps
CPU time 1.09 seconds
Started Jul 17 07:16:19 PM PDT 24
Finished Jul 17 07:16:22 PM PDT 24
Peak memory 218800 kb
Host smart-2e97aa23-bf84-4e56-91b4-e0af8ff3e670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72622916 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.72622916
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.3187219142
Short name T861
Test name
Test status
Simulation time 32702680 ps
CPU time 0.81 seconds
Started Jul 17 07:16:30 PM PDT 24
Finished Jul 17 07:16:49 PM PDT 24
Peak memory 218352 kb
Host smart-cb40200a-23ad-469c-81f9-f5145ba369f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187219142 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3187219142
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.223681005
Short name T543
Test name
Test status
Simulation time 81852871 ps
CPU time 1.23 seconds
Started Jul 17 07:16:19 PM PDT 24
Finished Jul 17 07:16:22 PM PDT 24
Peak memory 217700 kb
Host smart-55590a6b-58f2-48c8-bade-1fc000257abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223681005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.223681005
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.50700780
Short name T178
Test name
Test status
Simulation time 84919112 ps
CPU time 1.17 seconds
Started Jul 17 07:16:23 PM PDT 24
Finished Jul 17 07:16:33 PM PDT 24
Peak memory 221960 kb
Host smart-44610b1b-dc48-4b5e-af52-b8b47b8dd405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50700780 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.50700780
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.1843767294
Short name T48
Test name
Test status
Simulation time 19074117 ps
CPU time 1.11 seconds
Started Jul 17 07:16:26 PM PDT 24
Finished Jul 17 07:16:42 PM PDT 24
Peak memory 224264 kb
Host smart-cad25c7f-674f-4b8b-91cf-c34615b1b618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843767294 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.1843767294
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1971423174
Short name T299
Test name
Test status
Simulation time 47995072 ps
CPU time 1.49 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:32 PM PDT 24
Peak memory 218972 kb
Host smart-3411da56-6a67-46c3-a7a5-e250b8dcfc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971423174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1971423174
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.2981750568
Short name T111
Test name
Test status
Simulation time 38421571 ps
CPU time 1.3 seconds
Started Jul 17 07:16:23 PM PDT 24
Finished Jul 17 07:16:33 PM PDT 24
Peak memory 219388 kb
Host smart-d3159358-32e8-4aba-85a8-2b35cfce592c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981750568 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.2981750568
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.2483503922
Short name T169
Test name
Test status
Simulation time 30990312 ps
CPU time 0.87 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:31 PM PDT 24
Peak memory 218584 kb
Host smart-aa8ac245-7981-4ec7-9787-10963add207e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483503922 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.2483503922
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.3906686801
Short name T302
Test name
Test status
Simulation time 105577956 ps
CPU time 3.25 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:34 PM PDT 24
Peak memory 219156 kb
Host smart-0cdb8687-c106-4df3-babd-1f7639770aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906686801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.3906686801
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.525179109
Short name T982
Test name
Test status
Simulation time 31866360 ps
CPU time 1.33 seconds
Started Jul 17 07:14:56 PM PDT 24
Finished Jul 17 07:15:00 PM PDT 24
Peak memory 218848 kb
Host smart-ce2f2e47-a2fa-4190-9ab7-93a287b8c601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525179109 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.525179109
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.2068232786
Short name T344
Test name
Test status
Simulation time 46850414 ps
CPU time 0.87 seconds
Started Jul 17 07:14:51 PM PDT 24
Finished Jul 17 07:14:54 PM PDT 24
Peak memory 207068 kb
Host smart-f6d31e5b-968f-46aa-a842-c0f9b3bbebfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068232786 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.2068232786
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.3284222053
Short name T525
Test name
Test status
Simulation time 18396775 ps
CPU time 0.82 seconds
Started Jul 17 07:14:50 PM PDT 24
Finished Jul 17 07:14:52 PM PDT 24
Peak memory 216476 kb
Host smart-20d3d681-eb12-4d92-8bf1-bf520fd72dcb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284222053 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.3284222053
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.3998695377
Short name T637
Test name
Test status
Simulation time 55951066 ps
CPU time 1.57 seconds
Started Jul 17 07:14:56 PM PDT 24
Finished Jul 17 07:15:01 PM PDT 24
Peak memory 219288 kb
Host smart-8a3f53bc-4810-4c36-a934-0e7c27d07857
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998695377 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.3998695377
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.476076446
Short name T675
Test name
Test status
Simulation time 33772039 ps
CPU time 0.84 seconds
Started Jul 17 07:14:56 PM PDT 24
Finished Jul 17 07:15:01 PM PDT 24
Peak memory 218668 kb
Host smart-5cc83ae3-9f69-44fc-a247-d6ab584a33b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476076446 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.476076446
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.906548849
Short name T726
Test name
Test status
Simulation time 92230426 ps
CPU time 1.19 seconds
Started Jul 17 07:14:53 PM PDT 24
Finished Jul 17 07:14:56 PM PDT 24
Peak memory 217424 kb
Host smart-63085dfc-a77f-4ed1-8cad-bdb00f0c1525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906548849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.906548849
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.3215067215
Short name T92
Test name
Test status
Simulation time 21828009 ps
CPU time 0.92 seconds
Started Jul 17 07:14:51 PM PDT 24
Finished Jul 17 07:14:54 PM PDT 24
Peak memory 216172 kb
Host smart-1eed6acd-918d-4123-bf06-5d81ba21e4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215067215 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.3215067215
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.2601617178
Short name T27
Test name
Test status
Simulation time 51594115 ps
CPU time 0.9 seconds
Started Jul 17 07:14:52 PM PDT 24
Finished Jul 17 07:14:54 PM PDT 24
Peak memory 207336 kb
Host smart-2accf2d0-144c-4840-8fc0-f91de7365229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601617178 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2601617178
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.1891012541
Short name T560
Test name
Test status
Simulation time 31064309 ps
CPU time 1.05 seconds
Started Jul 17 07:14:56 PM PDT 24
Finished Jul 17 07:15:01 PM PDT 24
Peak memory 215644 kb
Host smart-7dd9d3aa-9149-4505-bfe2-b294a9683dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891012541 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.1891012541
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.2239536709
Short name T376
Test name
Test status
Simulation time 205688261 ps
CPU time 2.61 seconds
Started Jul 17 07:14:51 PM PDT 24
Finished Jul 17 07:14:54 PM PDT 24
Peak memory 219904 kb
Host smart-7683ac71-2ef4-45d4-bc8e-ea7465ab9816
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239536709 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2239536709
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.2281163799
Short name T888
Test name
Test status
Simulation time 194748349628 ps
CPU time 2445.54 seconds
Started Jul 17 07:14:51 PM PDT 24
Finished Jul 17 07:55:38 PM PDT 24
Peak memory 232832 kb
Host smart-3ab5a0b8-762b-4141-8c61-2f53eb789ebe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281163799 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.2281163799
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.2901930426
Short name T531
Test name
Test status
Simulation time 23504210 ps
CPU time 1.12 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:31 PM PDT 24
Peak memory 221032 kb
Host smart-98c29358-09c8-4bc9-95f6-88e0a8376832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901930426 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.2901930426
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.1336039145
Short name T975
Test name
Test status
Simulation time 33778515 ps
CPU time 0.82 seconds
Started Jul 17 07:16:24 PM PDT 24
Finished Jul 17 07:16:36 PM PDT 24
Peak memory 218664 kb
Host smart-cf7ab50e-ae93-4a66-aaaa-75d280e105c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336039145 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.1336039145
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.3904577489
Short name T941
Test name
Test status
Simulation time 85409016 ps
CPU time 1.02 seconds
Started Jul 17 07:16:22 PM PDT 24
Finished Jul 17 07:16:30 PM PDT 24
Peak memory 219560 kb
Host smart-48ae198d-b1fb-4c6a-9e9f-f54312cdcf97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904577489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3904577489
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.1036001615
Short name T163
Test name
Test status
Simulation time 81944784 ps
CPU time 1.03 seconds
Started Jul 17 07:16:25 PM PDT 24
Finished Jul 17 07:16:38 PM PDT 24
Peak memory 219824 kb
Host smart-e7662b87-13e3-4b06-91c6-cf5f117bca69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036001615 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.1036001615
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.3336178982
Short name T193
Test name
Test status
Simulation time 31275624 ps
CPU time 1.02 seconds
Started Jul 17 07:16:24 PM PDT 24
Finished Jul 17 07:16:37 PM PDT 24
Peak memory 220256 kb
Host smart-b84cf1fd-e17b-49c6-8b6b-46d41686c4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336178982 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3336178982
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.1916660682
Short name T354
Test name
Test status
Simulation time 28716917 ps
CPU time 1.22 seconds
Started Jul 17 07:16:23 PM PDT 24
Finished Jul 17 07:16:33 PM PDT 24
Peak memory 220192 kb
Host smart-2b88a1f6-7293-4b6e-b62e-889311ac9309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916660682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.1916660682
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.302684981
Short name T275
Test name
Test status
Simulation time 30445351 ps
CPU time 1.27 seconds
Started Jul 17 07:16:25 PM PDT 24
Finished Jul 17 07:16:38 PM PDT 24
Peak memory 219680 kb
Host smart-2666a1f6-f64e-44a0-8d3f-461739594d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302684981 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.302684981
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.2331081294
Short name T437
Test name
Test status
Simulation time 60743435 ps
CPU time 1.02 seconds
Started Jul 17 07:16:25 PM PDT 24
Finished Jul 17 07:16:40 PM PDT 24
Peak memory 217724 kb
Host smart-bf746d11-6808-4e2d-bcee-b0ac12ec8e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331081294 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.2331081294
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.2421375212
Short name T800
Test name
Test status
Simulation time 129668927 ps
CPU time 1.37 seconds
Started Jul 17 07:16:24 PM PDT 24
Finished Jul 17 07:16:37 PM PDT 24
Peak memory 219256 kb
Host smart-edbfc1e1-204b-4c40-940d-8d29db888fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421375212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.2421375212
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.3914390702
Short name T561
Test name
Test status
Simulation time 37023575 ps
CPU time 1.11 seconds
Started Jul 17 07:16:27 PM PDT 24
Finished Jul 17 07:16:43 PM PDT 24
Peak memory 220156 kb
Host smart-7709b2ca-4cff-4530-bd54-d3397f83bccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914390702 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.3914390702
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.3984107148
Short name T721
Test name
Test status
Simulation time 51225293 ps
CPU time 0.96 seconds
Started Jul 17 07:16:26 PM PDT 24
Finished Jul 17 07:16:41 PM PDT 24
Peak memory 220148 kb
Host smart-ac45ed3b-18bc-4a6c-8974-2e7ec8130d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984107148 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3984107148
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.3673200483
Short name T838
Test name
Test status
Simulation time 40060735 ps
CPU time 1.37 seconds
Started Jul 17 07:16:28 PM PDT 24
Finished Jul 17 07:16:46 PM PDT 24
Peak memory 217280 kb
Host smart-db0c0886-e848-46c7-9f97-9feccc105645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673200483 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.3673200483
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.1509938718
Short name T227
Test name
Test status
Simulation time 30367954 ps
CPU time 1.23 seconds
Started Jul 17 07:16:27 PM PDT 24
Finished Jul 17 07:16:44 PM PDT 24
Peak memory 215992 kb
Host smart-350c6016-5e08-45c9-a265-8beb5e4c055f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509938718 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.1509938718
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.3042820916
Short name T400
Test name
Test status
Simulation time 42311757 ps
CPU time 1.19 seconds
Started Jul 17 07:16:26 PM PDT 24
Finished Jul 17 07:16:41 PM PDT 24
Peak memory 225956 kb
Host smart-a734f2b1-0452-4d85-9a84-094ba50626e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042820916 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3042820916
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.1556029087
Short name T307
Test name
Test status
Simulation time 179677404 ps
CPU time 1.64 seconds
Started Jul 17 07:16:26 PM PDT 24
Finished Jul 17 07:16:41 PM PDT 24
Peak memory 219004 kb
Host smart-38aedc8e-6081-4b6a-aff9-b2040b37385d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556029087 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.1556029087
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.942138978
Short name T136
Test name
Test status
Simulation time 48682661 ps
CPU time 1.16 seconds
Started Jul 17 07:16:27 PM PDT 24
Finished Jul 17 07:16:43 PM PDT 24
Peak memory 219052 kb
Host smart-429c487d-53c3-4be7-836d-807bfc8f3a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942138978 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.942138978
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.309249319
Short name T100
Test name
Test status
Simulation time 37170845 ps
CPU time 1.13 seconds
Started Jul 17 07:16:29 PM PDT 24
Finished Jul 17 07:16:48 PM PDT 24
Peak memory 229896 kb
Host smart-e8570cdc-2c3a-4c5a-b2c0-5d28d7fcd3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309249319 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.309249319
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.1194600135
Short name T703
Test name
Test status
Simulation time 43744177 ps
CPU time 1.67 seconds
Started Jul 17 07:16:26 PM PDT 24
Finished Jul 17 07:16:41 PM PDT 24
Peak memory 218948 kb
Host smart-04fcba2f-d083-46b1-8996-466f018a5ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194600135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.1194600135
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.1548782785
Short name T120
Test name
Test status
Simulation time 93090501 ps
CPU time 1.15 seconds
Started Jul 17 07:16:25 PM PDT 24
Finished Jul 17 07:16:40 PM PDT 24
Peak memory 219960 kb
Host smart-9e1a3316-143c-4a8e-b019-fb78e71bdb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548782785 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.1548782785
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.1330407167
Short name T865
Test name
Test status
Simulation time 18351321 ps
CPU time 1.16 seconds
Started Jul 17 07:16:25 PM PDT 24
Finished Jul 17 07:16:39 PM PDT 24
Peak memory 224304 kb
Host smart-5f9da339-971e-4930-b221-41450df9713e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330407167 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.1330407167
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.1258671529
Short name T504
Test name
Test status
Simulation time 118820445 ps
CPU time 2.46 seconds
Started Jul 17 07:16:25 PM PDT 24
Finished Jul 17 07:16:41 PM PDT 24
Peak memory 220388 kb
Host smart-9b54494b-c44b-4d2c-a396-be5ca4f4efc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258671529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.1258671529
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.3451579791
Short name T590
Test name
Test status
Simulation time 75397689 ps
CPU time 1.11 seconds
Started Jul 17 07:16:29 PM PDT 24
Finished Jul 17 07:16:46 PM PDT 24
Peak memory 220864 kb
Host smart-2b7ccb22-9918-43ca-82b2-1c4ea8e5bbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451579791 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.3451579791
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.344340850
Short name T149
Test name
Test status
Simulation time 18381991 ps
CPU time 1.03 seconds
Started Jul 17 07:18:06 PM PDT 24
Finished Jul 17 07:18:08 PM PDT 24
Peak memory 218636 kb
Host smart-9f3e5fbe-2f1e-41f6-a157-a2a87ea07f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344340850 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.344340850
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.3091036867
Short name T381
Test name
Test status
Simulation time 210636180 ps
CPU time 2.76 seconds
Started Jul 17 07:16:26 PM PDT 24
Finished Jul 17 07:16:42 PM PDT 24
Peak memory 219460 kb
Host smart-f707e770-8031-45ec-afbf-a2e709b4b541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091036867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.3091036867
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.2901777427
Short name T673
Test name
Test status
Simulation time 44981661 ps
CPU time 1.16 seconds
Started Jul 17 07:18:08 PM PDT 24
Finished Jul 17 07:18:11 PM PDT 24
Peak memory 218924 kb
Host smart-0f61b7e8-23d0-4570-8eb4-705e89e3e455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901777427 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.2901777427
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.3310679659
Short name T8
Test name
Test status
Simulation time 37589263 ps
CPU time 1.35 seconds
Started Jul 17 07:18:07 PM PDT 24
Finished Jul 17 07:18:09 PM PDT 24
Peak memory 219952 kb
Host smart-7518e029-3879-4e69-a8ad-31eae8c99381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310679659 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.3310679659
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.401174197
Short name T284
Test name
Test status
Simulation time 42763558 ps
CPU time 1.36 seconds
Started Jul 17 07:18:08 PM PDT 24
Finished Jul 17 07:18:11 PM PDT 24
Peak memory 218940 kb
Host smart-f3c38a33-940c-44a2-908d-2b252c8cec30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401174197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.401174197
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.912257543
Short name T89
Test name
Test status
Simulation time 27449360 ps
CPU time 1.26 seconds
Started Jul 17 07:18:06 PM PDT 24
Finished Jul 17 07:18:08 PM PDT 24
Peak memory 218912 kb
Host smart-8605586b-9e4f-45de-8c50-f30fa127407f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912257543 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.912257543
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.3368127255
Short name T955
Test name
Test status
Simulation time 134506087 ps
CPU time 1.16 seconds
Started Jul 17 07:18:03 PM PDT 24
Finished Jul 17 07:18:05 PM PDT 24
Peak memory 229996 kb
Host smart-48975b04-3d6d-4a17-8a92-31efbebe582b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368127255 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.3368127255
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.1520204479
Short name T12
Test name
Test status
Simulation time 45015996 ps
CPU time 1.2 seconds
Started Jul 17 07:18:06 PM PDT 24
Finished Jul 17 07:18:08 PM PDT 24
Peak memory 220304 kb
Host smart-b583efe7-091e-4e21-a596-92706b0df50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520204479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.1520204479
Directory /workspace/99.edn_genbits/latest
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