Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.36 98.25 93.91 97.02 90.12 96.37 99.77 92.08


Total test records in report: 1130
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T1019 /workspace/coverage/cover_reg_top/16.edn_intr_test.3478174888 Jul 18 06:07:56 PM PDT 24 Jul 18 06:08:01 PM PDT 24 36746065 ps
T278 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1112613119 Jul 18 06:07:39 PM PDT 24 Jul 18 06:07:44 PM PDT 24 133314289 ps
T1020 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.82501187 Jul 18 06:07:40 PM PDT 24 Jul 18 06:07:44 PM PDT 24 97463622 ps
T269 /workspace/coverage/cover_reg_top/10.edn_csr_rw.4232768448 Jul 18 06:07:53 PM PDT 24 Jul 18 06:07:56 PM PDT 24 29881346 ps
T1021 /workspace/coverage/cover_reg_top/13.edn_intr_test.3529256318 Jul 18 06:07:52 PM PDT 24 Jul 18 06:07:55 PM PDT 24 14443241 ps
T1022 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2503257081 Jul 18 06:07:43 PM PDT 24 Jul 18 06:07:50 PM PDT 24 164452629 ps
T251 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.568858689 Jul 18 06:07:40 PM PDT 24 Jul 18 06:07:44 PM PDT 24 13678021 ps
T1023 /workspace/coverage/cover_reg_top/10.edn_intr_test.2885555058 Jul 18 06:07:54 PM PDT 24 Jul 18 06:07:57 PM PDT 24 14559384 ps
T1024 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3398809157 Jul 18 06:07:54 PM PDT 24 Jul 18 06:07:58 PM PDT 24 55300087 ps
T1025 /workspace/coverage/cover_reg_top/12.edn_tl_errors.3889521078 Jul 18 06:07:56 PM PDT 24 Jul 18 06:08:04 PM PDT 24 97316293 ps
T1026 /workspace/coverage/cover_reg_top/4.edn_tl_errors.3586359960 Jul 18 06:07:40 PM PDT 24 Jul 18 06:07:46 PM PDT 24 273935981 ps
T1027 /workspace/coverage/cover_reg_top/30.edn_intr_test.2584654777 Jul 18 06:08:04 PM PDT 24 Jul 18 06:08:08 PM PDT 24 11903926 ps
T1028 /workspace/coverage/cover_reg_top/11.edn_intr_test.3268206198 Jul 18 06:07:52 PM PDT 24 Jul 18 06:07:55 PM PDT 24 34116343 ps
T1029 /workspace/coverage/cover_reg_top/6.edn_csr_rw.3149108556 Jul 18 06:07:41 PM PDT 24 Jul 18 06:07:47 PM PDT 24 40669181 ps
T1030 /workspace/coverage/cover_reg_top/21.edn_intr_test.67923608 Jul 18 06:07:59 PM PDT 24 Jul 18 06:08:03 PM PDT 24 14798186 ps
T279 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1079424214 Jul 18 06:07:52 PM PDT 24 Jul 18 06:07:56 PM PDT 24 273052971 ps
T1031 /workspace/coverage/cover_reg_top/34.edn_intr_test.2504616212 Jul 18 06:08:04 PM PDT 24 Jul 18 06:08:08 PM PDT 24 12209000 ps
T1032 /workspace/coverage/cover_reg_top/9.edn_intr_test.2026582206 Jul 18 06:07:56 PM PDT 24 Jul 18 06:08:02 PM PDT 24 22094503 ps
T1033 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3280699384 Jul 18 06:07:40 PM PDT 24 Jul 18 06:07:47 PM PDT 24 344253357 ps
T1034 /workspace/coverage/cover_reg_top/9.edn_tl_errors.2192986874 Jul 18 06:07:52 PM PDT 24 Jul 18 06:07:59 PM PDT 24 540833565 ps
T1035 /workspace/coverage/cover_reg_top/4.edn_intr_test.4251825687 Jul 18 06:07:41 PM PDT 24 Jul 18 06:07:48 PM PDT 24 17761432 ps
T1036 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2188955381 Jul 18 06:07:52 PM PDT 24 Jul 18 06:07:56 PM PDT 24 29056027 ps
T1037 /workspace/coverage/cover_reg_top/29.edn_intr_test.1298365746 Jul 18 06:08:05 PM PDT 24 Jul 18 06:08:09 PM PDT 24 15003728 ps
T1038 /workspace/coverage/cover_reg_top/3.edn_tl_errors.2306651624 Jul 18 06:07:41 PM PDT 24 Jul 18 06:07:49 PM PDT 24 43445756 ps
T1039 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2394572165 Jul 18 06:07:42 PM PDT 24 Jul 18 06:07:49 PM PDT 24 33088213 ps
T270 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.39802148 Jul 18 06:07:41 PM PDT 24 Jul 18 06:07:48 PM PDT 24 118635904 ps
T1040 /workspace/coverage/cover_reg_top/5.edn_intr_test.934268355 Jul 18 06:07:42 PM PDT 24 Jul 18 06:07:48 PM PDT 24 18347650 ps
T1041 /workspace/coverage/cover_reg_top/19.edn_tl_errors.3123307899 Jul 18 06:08:00 PM PDT 24 Jul 18 06:08:04 PM PDT 24 23262810 ps
T1042 /workspace/coverage/cover_reg_top/28.edn_intr_test.1013350461 Jul 18 06:08:03 PM PDT 24 Jul 18 06:08:06 PM PDT 24 14145121 ps
T1043 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1517199083 Jul 18 06:07:55 PM PDT 24 Jul 18 06:08:00 PM PDT 24 247873148 ps
T280 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.901818753 Jul 18 06:07:43 PM PDT 24 Jul 18 06:07:51 PM PDT 24 321273755 ps
T1044 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2445769317 Jul 18 06:07:53 PM PDT 24 Jul 18 06:07:57 PM PDT 24 13376781 ps
T1045 /workspace/coverage/cover_reg_top/11.edn_tl_errors.434407443 Jul 18 06:07:56 PM PDT 24 Jul 18 06:08:05 PM PDT 24 116731448 ps
T1046 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2963463084 Jul 18 06:07:52 PM PDT 24 Jul 18 06:07:56 PM PDT 24 257498157 ps
T1047 /workspace/coverage/cover_reg_top/41.edn_intr_test.1579353536 Jul 18 06:08:07 PM PDT 24 Jul 18 06:08:10 PM PDT 24 43958470 ps
T1048 /workspace/coverage/cover_reg_top/49.edn_intr_test.2796504567 Jul 18 06:08:18 PM PDT 24 Jul 18 06:08:21 PM PDT 24 12932058 ps
T252 /workspace/coverage/cover_reg_top/3.edn_csr_rw.4095496708 Jul 18 06:07:40 PM PDT 24 Jul 18 06:07:47 PM PDT 24 17302987 ps
T1049 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.90493172 Jul 18 06:07:38 PM PDT 24 Jul 18 06:07:43 PM PDT 24 285420369 ps
T1050 /workspace/coverage/cover_reg_top/6.edn_tl_errors.552686344 Jul 18 06:07:39 PM PDT 24 Jul 18 06:07:45 PM PDT 24 372367338 ps
T1051 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1619649177 Jul 18 06:07:51 PM PDT 24 Jul 18 06:07:54 PM PDT 24 41687936 ps
T1052 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2056730019 Jul 18 06:07:55 PM PDT 24 Jul 18 06:08:00 PM PDT 24 14252494 ps
T1053 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2447617015 Jul 18 06:07:38 PM PDT 24 Jul 18 06:07:41 PM PDT 24 24368024 ps
T1054 /workspace/coverage/cover_reg_top/0.edn_intr_test.1599378386 Jul 18 06:07:37 PM PDT 24 Jul 18 06:07:40 PM PDT 24 15569986 ps
T1055 /workspace/coverage/cover_reg_top/10.edn_tl_errors.3009416941 Jul 18 06:07:58 PM PDT 24 Jul 18 06:08:04 PM PDT 24 67843435 ps
T253 /workspace/coverage/cover_reg_top/19.edn_csr_rw.4008452877 Jul 18 06:07:56 PM PDT 24 Jul 18 06:08:01 PM PDT 24 31174825 ps
T1056 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3478597593 Jul 18 06:07:41 PM PDT 24 Jul 18 06:07:48 PM PDT 24 77281789 ps
T1057 /workspace/coverage/cover_reg_top/0.edn_csr_rw.333020719 Jul 18 06:07:40 PM PDT 24 Jul 18 06:07:47 PM PDT 24 24265855 ps
T1058 /workspace/coverage/cover_reg_top/25.edn_intr_test.3927434039 Jul 18 06:07:52 PM PDT 24 Jul 18 06:07:55 PM PDT 24 64759957 ps
T254 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1544862169 Jul 18 06:07:39 PM PDT 24 Jul 18 06:07:42 PM PDT 24 153036672 ps
T1059 /workspace/coverage/cover_reg_top/18.edn_tl_errors.192405336 Jul 18 06:07:53 PM PDT 24 Jul 18 06:07:58 PM PDT 24 70781962 ps
T1060 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1320911077 Jul 18 06:07:41 PM PDT 24 Jul 18 06:07:49 PM PDT 24 113928627 ps
T1061 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2196260166 Jul 18 06:07:55 PM PDT 24 Jul 18 06:08:00 PM PDT 24 21151801 ps
T1062 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2592636775 Jul 18 06:07:41 PM PDT 24 Jul 18 06:07:49 PM PDT 24 16602428 ps
T1063 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2628013430 Jul 18 06:07:39 PM PDT 24 Jul 18 06:07:43 PM PDT 24 29176841 ps
T1064 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2835467453 Jul 18 06:07:56 PM PDT 24 Jul 18 06:08:01 PM PDT 24 65601827 ps
T1065 /workspace/coverage/cover_reg_top/13.edn_csr_rw.1084074373 Jul 18 06:07:50 PM PDT 24 Jul 18 06:07:52 PM PDT 24 15576472 ps
T1066 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1076826725 Jul 18 06:07:58 PM PDT 24 Jul 18 06:08:03 PM PDT 24 23464672 ps
T1067 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1254794506 Jul 18 06:07:38 PM PDT 24 Jul 18 06:07:40 PM PDT 24 35919681 ps
T255 /workspace/coverage/cover_reg_top/18.edn_csr_rw.337209686 Jul 18 06:07:55 PM PDT 24 Jul 18 06:07:59 PM PDT 24 47481737 ps
T1068 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.216731727 Jul 18 06:07:55 PM PDT 24 Jul 18 06:07:59 PM PDT 24 58378883 ps
T1069 /workspace/coverage/cover_reg_top/5.edn_tl_errors.1745979412 Jul 18 06:07:41 PM PDT 24 Jul 18 06:07:50 PM PDT 24 222747608 ps
T1070 /workspace/coverage/cover_reg_top/36.edn_intr_test.1842952212 Jul 18 06:08:04 PM PDT 24 Jul 18 06:08:08 PM PDT 24 27330515 ps
T1071 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2101017198 Jul 18 06:07:39 PM PDT 24 Jul 18 06:07:43 PM PDT 24 45865799 ps
T1072 /workspace/coverage/cover_reg_top/42.edn_intr_test.2425844991 Jul 18 06:08:07 PM PDT 24 Jul 18 06:08:10 PM PDT 24 14277377 ps
T1073 /workspace/coverage/cover_reg_top/26.edn_intr_test.381748612 Jul 18 06:08:05 PM PDT 24 Jul 18 06:08:08 PM PDT 24 20212694 ps
T1074 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1666230229 Jul 18 06:08:00 PM PDT 24 Jul 18 06:08:04 PM PDT 24 69133901 ps
T1075 /workspace/coverage/cover_reg_top/33.edn_intr_test.4017565893 Jul 18 06:08:03 PM PDT 24 Jul 18 06:08:06 PM PDT 24 14812955 ps
T1076 /workspace/coverage/cover_reg_top/27.edn_intr_test.791672471 Jul 18 06:08:05 PM PDT 24 Jul 18 06:08:08 PM PDT 24 14658649 ps
T1077 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2842901060 Jul 18 06:07:40 PM PDT 24 Jul 18 06:07:47 PM PDT 24 38359867 ps
T1078 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3733400738 Jul 18 06:07:41 PM PDT 24 Jul 18 06:07:52 PM PDT 24 176570167 ps
T1079 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.4166700672 Jul 18 06:07:57 PM PDT 24 Jul 18 06:08:02 PM PDT 24 59575739 ps
T1080 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3072566369 Jul 18 06:07:57 PM PDT 24 Jul 18 06:08:03 PM PDT 24 61344155 ps
T256 /workspace/coverage/cover_reg_top/7.edn_csr_rw.1505606594 Jul 18 06:07:39 PM PDT 24 Jul 18 06:07:43 PM PDT 24 13413329 ps
T1081 /workspace/coverage/cover_reg_top/0.edn_tl_errors.1183818906 Jul 18 06:07:56 PM PDT 24 Jul 18 06:08:02 PM PDT 24 972472079 ps
T1082 /workspace/coverage/cover_reg_top/14.edn_intr_test.3090284160 Jul 18 06:07:56 PM PDT 24 Jul 18 06:08:01 PM PDT 24 72338141 ps
T1083 /workspace/coverage/cover_reg_top/8.edn_intr_test.3927955488 Jul 18 06:07:43 PM PDT 24 Jul 18 06:07:50 PM PDT 24 27460163 ps
T257 /workspace/coverage/cover_reg_top/12.edn_csr_rw.1402207184 Jul 18 06:07:56 PM PDT 24 Jul 18 06:08:01 PM PDT 24 45054065 ps
T1084 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3664386664 Jul 18 06:07:53 PM PDT 24 Jul 18 06:07:56 PM PDT 24 87497121 ps
T1085 /workspace/coverage/cover_reg_top/45.edn_intr_test.1249750324 Jul 18 06:07:54 PM PDT 24 Jul 18 06:07:57 PM PDT 24 118194877 ps
T1086 /workspace/coverage/cover_reg_top/44.edn_intr_test.2001419365 Jul 18 06:08:05 PM PDT 24 Jul 18 06:08:08 PM PDT 24 80322818 ps
T1087 /workspace/coverage/cover_reg_top/15.edn_tl_errors.394843557 Jul 18 06:07:53 PM PDT 24 Jul 18 06:07:58 PM PDT 24 292903962 ps
T1088 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2354539498 Jul 18 06:07:56 PM PDT 24 Jul 18 06:08:02 PM PDT 24 80720952 ps
T1089 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2827370165 Jul 18 06:07:55 PM PDT 24 Jul 18 06:07:59 PM PDT 24 15331452 ps
T1090 /workspace/coverage/cover_reg_top/46.edn_intr_test.1928664659 Jul 18 06:08:23 PM PDT 24 Jul 18 06:08:27 PM PDT 24 28910681 ps
T1091 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1984504634 Jul 18 06:08:04 PM PDT 24 Jul 18 06:08:08 PM PDT 24 281128106 ps
T1092 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3000963623 Jul 18 06:07:39 PM PDT 24 Jul 18 06:07:45 PM PDT 24 117710794 ps
T1093 /workspace/coverage/cover_reg_top/48.edn_intr_test.4093229996 Jul 18 06:08:21 PM PDT 24 Jul 18 06:08:26 PM PDT 24 100790444 ps
T258 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1501958728 Jul 18 06:07:39 PM PDT 24 Jul 18 06:07:44 PM PDT 24 28813814 ps
T1094 /workspace/coverage/cover_reg_top/38.edn_intr_test.2928519254 Jul 18 06:08:07 PM PDT 24 Jul 18 06:08:10 PM PDT 24 12877539 ps
T1095 /workspace/coverage/cover_reg_top/17.edn_tl_errors.2827044680 Jul 18 06:07:53 PM PDT 24 Jul 18 06:07:59 PM PDT 24 403118471 ps
T1096 /workspace/coverage/cover_reg_top/13.edn_tl_errors.134394934 Jul 18 06:07:55 PM PDT 24 Jul 18 06:08:02 PM PDT 24 77295608 ps
T260 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3759091962 Jul 18 06:07:37 PM PDT 24 Jul 18 06:07:40 PM PDT 24 38102132 ps
T1097 /workspace/coverage/cover_reg_top/12.edn_intr_test.314295878 Jul 18 06:07:55 PM PDT 24 Jul 18 06:08:00 PM PDT 24 16113017 ps
T1098 /workspace/coverage/cover_reg_top/9.edn_csr_rw.2328945440 Jul 18 06:07:55 PM PDT 24 Jul 18 06:07:58 PM PDT 24 14460360 ps
T261 /workspace/coverage/cover_reg_top/8.edn_csr_rw.262534811 Jul 18 06:07:42 PM PDT 24 Jul 18 06:07:48 PM PDT 24 17153736 ps
T1099 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.283054766 Jul 18 06:07:40 PM PDT 24 Jul 18 06:07:47 PM PDT 24 55825685 ps
T263 /workspace/coverage/cover_reg_top/1.edn_csr_rw.762404140 Jul 18 06:07:41 PM PDT 24 Jul 18 06:07:48 PM PDT 24 12230169 ps
T1100 /workspace/coverage/cover_reg_top/43.edn_intr_test.804989056 Jul 18 06:08:05 PM PDT 24 Jul 18 06:08:08 PM PDT 24 20916034 ps
T1101 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3616794920 Jul 18 06:07:41 PM PDT 24 Jul 18 06:07:50 PM PDT 24 130425934 ps
T1102 /workspace/coverage/cover_reg_top/1.edn_tl_errors.3820463897 Jul 18 06:07:40 PM PDT 24 Jul 18 06:07:47 PM PDT 24 310952708 ps
T1103 /workspace/coverage/cover_reg_top/2.edn_tl_errors.2963644028 Jul 18 06:07:43 PM PDT 24 Jul 18 06:07:52 PM PDT 24 285300528 ps
T1104 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1729022531 Jul 18 06:07:40 PM PDT 24 Jul 18 06:07:45 PM PDT 24 127548180 ps
T1105 /workspace/coverage/cover_reg_top/7.edn_intr_test.2884009733 Jul 18 06:07:43 PM PDT 24 Jul 18 06:07:50 PM PDT 24 27363783 ps
T1106 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1637124179 Jul 18 06:07:51 PM PDT 24 Jul 18 06:07:54 PM PDT 24 158865306 ps
T1107 /workspace/coverage/cover_reg_top/7.edn_tl_errors.3372196380 Jul 18 06:07:40 PM PDT 24 Jul 18 06:07:48 PM PDT 24 79584433 ps
T1108 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2578817933 Jul 18 06:07:41 PM PDT 24 Jul 18 06:07:48 PM PDT 24 82922557 ps
T1109 /workspace/coverage/cover_reg_top/39.edn_intr_test.2035736203 Jul 18 06:07:54 PM PDT 24 Jul 18 06:07:57 PM PDT 24 69102535 ps
T1110 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2474134881 Jul 18 06:07:52 PM PDT 24 Jul 18 06:07:55 PM PDT 24 17529283 ps
T1111 /workspace/coverage/cover_reg_top/20.edn_intr_test.3341227882 Jul 18 06:07:56 PM PDT 24 Jul 18 06:08:01 PM PDT 24 32982592 ps
T1112 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1808588554 Jul 18 06:07:43 PM PDT 24 Jul 18 06:07:50 PM PDT 24 146898028 ps
T281 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.576242148 Jul 18 06:07:53 PM PDT 24 Jul 18 06:07:57 PM PDT 24 164062448 ps
T1113 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2209924612 Jul 18 06:07:39 PM PDT 24 Jul 18 06:07:44 PM PDT 24 107970466 ps
T1114 /workspace/coverage/cover_reg_top/14.edn_tl_errors.545267908 Jul 18 06:07:52 PM PDT 24 Jul 18 06:07:56 PM PDT 24 146658794 ps
T1115 /workspace/coverage/cover_reg_top/15.edn_csr_rw.942651283 Jul 18 06:07:55 PM PDT 24 Jul 18 06:08:00 PM PDT 24 53461506 ps
T262 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2395480018 Jul 18 06:07:44 PM PDT 24 Jul 18 06:07:50 PM PDT 24 99375804 ps
T1116 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3018388934 Jul 18 06:07:40 PM PDT 24 Jul 18 06:07:49 PM PDT 24 261155575 ps
T1117 /workspace/coverage/cover_reg_top/18.edn_intr_test.1671581623 Jul 18 06:07:55 PM PDT 24 Jul 18 06:07:59 PM PDT 24 18978080 ps
T1118 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3468825397 Jul 18 06:07:57 PM PDT 24 Jul 18 06:08:04 PM PDT 24 128809162 ps
T1119 /workspace/coverage/cover_reg_top/2.edn_intr_test.2099472217 Jul 18 06:07:37 PM PDT 24 Jul 18 06:07:38 PM PDT 24 25201484 ps
T1120 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2711255168 Jul 18 06:07:41 PM PDT 24 Jul 18 06:07:48 PM PDT 24 131997604 ps
T1121 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1408172101 Jul 18 06:08:00 PM PDT 24 Jul 18 06:08:04 PM PDT 24 52564880 ps
T1122 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2190478531 Jul 18 06:07:51 PM PDT 24 Jul 18 06:07:54 PM PDT 24 81218373 ps
T1123 /workspace/coverage/cover_reg_top/32.edn_intr_test.3429693161 Jul 18 06:07:57 PM PDT 24 Jul 18 06:08:02 PM PDT 24 24063657 ps
T1124 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1565644783 Jul 18 06:07:41 PM PDT 24 Jul 18 06:07:48 PM PDT 24 28105566 ps
T1125 /workspace/coverage/cover_reg_top/14.edn_csr_rw.3817087722 Jul 18 06:07:56 PM PDT 24 Jul 18 06:08:01 PM PDT 24 12559726 ps
T1126 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1103738802 Jul 18 06:07:55 PM PDT 24 Jul 18 06:08:00 PM PDT 24 39383348 ps
T1127 /workspace/coverage/cover_reg_top/23.edn_intr_test.2316635571 Jul 18 06:07:59 PM PDT 24 Jul 18 06:08:03 PM PDT 24 14374438 ps
T1128 /workspace/coverage/cover_reg_top/6.edn_intr_test.3742645866 Jul 18 06:07:42 PM PDT 24 Jul 18 06:07:48 PM PDT 24 19010392 ps
T1129 /workspace/coverage/cover_reg_top/19.edn_intr_test.1743486677 Jul 18 06:07:56 PM PDT 24 Jul 18 06:08:01 PM PDT 24 31127572 ps
T1130 /workspace/coverage/cover_reg_top/17.edn_intr_test.2090098918 Jul 18 06:07:57 PM PDT 24 Jul 18 06:08:02 PM PDT 24 14673842 ps

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2453945764
Short name T4
Test name
Test status
Simulation time 95442040080 ps
CPU time 618.43 seconds
Started Jul 18 07:21:43 PM PDT 24
Finished Jul 18 07:32:04 PM PDT 24
Peak memory 220768 kb
Host smart-d1ef0193-58a7-48ac-8daa-82878012e86d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453945764 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.2453945764
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.edn_genbits.185635697
Short name T47
Test name
Test status
Simulation time 240003833 ps
CPU time 3.81 seconds
Started Jul 18 07:25:18 PM PDT 24
Finished Jul 18 07:25:24 PM PDT 24
Peak memory 219492 kb
Host smart-360121f3-0789-4c6a-96d9-f7caaffbc32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185635697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.185635697
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.63207949
Short name T50
Test name
Test status
Simulation time 42158134 ps
CPU time 1.17 seconds
Started Jul 18 07:25:21 PM PDT 24
Finished Jul 18 07:25:29 PM PDT 24
Peak memory 219100 kb
Host smart-ea73601e-8626-48a7-9b91-884ea0fc2edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63207949 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.63207949
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.336876824
Short name T6
Test name
Test status
Simulation time 52786228 ps
CPU time 1.09 seconds
Started Jul 18 07:25:05 PM PDT 24
Finished Jul 18 07:25:10 PM PDT 24
Peak memory 229924 kb
Host smart-9efee115-82bb-4fb7-9e7f-4a039b8ccdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336876824 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.336876824
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/3.edn_sec_cm.3886272800
Short name T15
Test name
Test status
Simulation time 1036947934 ps
CPU time 14.71 seconds
Started Jul 18 07:21:43 PM PDT 24
Finished Jul 18 07:22:01 PM PDT 24
Peak memory 242480 kb
Host smart-701b344c-2d66-4d44-bb53-0cb59c9bbd4f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886272800 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.3886272800
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.3583632354
Short name T18
Test name
Test status
Simulation time 52788894 ps
CPU time 1.04 seconds
Started Jul 18 07:24:39 PM PDT 24
Finished Jul 18 07:24:43 PM PDT 24
Peak memory 217216 kb
Host smart-40fac34d-5bb7-4ed2-a3d0-aa6670b3229b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583632354 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.3583632354
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_stress_all.358827841
Short name T3
Test name
Test status
Simulation time 2073909524 ps
CPU time 5.7 seconds
Started Jul 18 07:22:32 PM PDT 24
Finished Jul 18 07:22:41 PM PDT 24
Peak memory 217612 kb
Host smart-444328b2-9019-4ba3-a1de-8f3ee90aa1a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358827841 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.358827841
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/85.edn_alert.1178396227
Short name T93
Test name
Test status
Simulation time 244486740 ps
CPU time 1.37 seconds
Started Jul 18 07:25:38 PM PDT 24
Finished Jul 18 07:25:43 PM PDT 24
Peak memory 218924 kb
Host smart-baf418e3-0360-4e9b-a9bf-38d153c19569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178396227 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.1178396227
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/8.edn_genbits.1081580431
Short name T40
Test name
Test status
Simulation time 135342242 ps
CPU time 1.24 seconds
Started Jul 18 07:22:15 PM PDT 24
Finished Jul 18 07:22:19 PM PDT 24
Peak memory 219336 kb
Host smart-927b95dc-c490-4d40-96af-9ab50bb1841b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081580431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1081580431
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.4024450347
Short name T112
Test name
Test status
Simulation time 24762209 ps
CPU time 1.3 seconds
Started Jul 18 07:26:01 PM PDT 24
Finished Jul 18 07:26:07 PM PDT 24
Peak memory 216036 kb
Host smart-abe8bc98-f019-491a-a9b4-ae7db40f0c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024450347 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.4024450347
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.192876950
Short name T38
Test name
Test status
Simulation time 122960024611 ps
CPU time 813.08 seconds
Started Jul 18 07:24:43 PM PDT 24
Finished Jul 18 07:38:19 PM PDT 24
Peak memory 224048 kb
Host smart-cfe53301-ecfc-48c6-b6a4-3076c72f2844
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192876950 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.192876950
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.edn_regwen.2227756615
Short name T533
Test name
Test status
Simulation time 14661090 ps
CPU time 0.98 seconds
Started Jul 18 07:22:15 PM PDT 24
Finished Jul 18 07:22:18 PM PDT 24
Peak memory 207380 kb
Host smart-96251065-0978-4b2f-a4ba-f63b405ed100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227756615 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.2227756615
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/29.edn_disable.291998492
Short name T45
Test name
Test status
Simulation time 24919457 ps
CPU time 0.83 seconds
Started Jul 18 07:23:50 PM PDT 24
Finished Jul 18 07:23:53 PM PDT 24
Peak memory 216488 kb
Host smart-d53765a6-ec6a-4e1c-8e4b-e55939095c47
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291998492 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.291998492
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1079424214
Short name T279
Test name
Test status
Simulation time 273052971 ps
CPU time 2.16 seconds
Started Jul 18 06:07:52 PM PDT 24
Finished Jul 18 06:07:56 PM PDT 24
Peak memory 206940 kb
Host smart-e57db5fd-c38a-4f13-9851-e69852b2ebbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079424214 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.1079424214
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/default/162.edn_alert.1751732635
Short name T27
Test name
Test status
Simulation time 36981644 ps
CPU time 1.17 seconds
Started Jul 18 07:26:18 PM PDT 24
Finished Jul 18 07:26:25 PM PDT 24
Peak memory 219908 kb
Host smart-2940d966-5612-4766-a3f7-f487a92dee3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751732635 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.1751732635
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.1654507833
Short name T220
Test name
Test status
Simulation time 98412581626 ps
CPU time 1126.16 seconds
Started Jul 18 07:24:07 PM PDT 24
Finished Jul 18 07:42:56 PM PDT 24
Peak memory 222016 kb
Host smart-ca1cef60-5251-4df4-af17-380cfb2d3036
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654507833 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.1654507833
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.edn_disable.1477425842
Short name T190
Test name
Test status
Simulation time 27147537 ps
CPU time 0.84 seconds
Started Jul 18 07:21:15 PM PDT 24
Finished Jul 18 07:21:20 PM PDT 24
Peak memory 216572 kb
Host smart-8e551c95-52e2-46af-839a-7de4754028ce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477425842 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.1477425842
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable.1774801310
Short name T990
Test name
Test status
Simulation time 12269867 ps
CPU time 0.88 seconds
Started Jul 18 07:22:30 PM PDT 24
Finished Jul 18 07:22:34 PM PDT 24
Peak memory 216780 kb
Host smart-461ac03f-7e53-4533-9b87-9308403f788c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774801310 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.1774801310
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.3170804520
Short name T142
Test name
Test status
Simulation time 23761700 ps
CPU time 1.04 seconds
Started Jul 18 07:23:16 PM PDT 24
Finished Jul 18 07:23:18 PM PDT 24
Peak memory 217088 kb
Host smart-1a552313-38f5-40d1-8bc3-272fa146d606
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170804520 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.3170804520
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/57.edn_err.4038082497
Short name T183
Test name
Test status
Simulation time 20592193 ps
CPU time 1.04 seconds
Started Jul 18 07:25:07 PM PDT 24
Finished Jul 18 07:25:12 PM PDT 24
Peak memory 218928 kb
Host smart-5aeef455-4755-4307-8e4e-41524c0dd132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038082497 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.4038082497
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.568858689
Short name T251
Test name
Test status
Simulation time 13678021 ps
CPU time 0.93 seconds
Started Jul 18 06:07:40 PM PDT 24
Finished Jul 18 06:07:44 PM PDT 24
Peak memory 206768 kb
Host smart-f237ae19-6634-41c9-8749-c68621c3b839
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568858689 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.568858689
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/default/77.edn_alert.923403135
Short name T126
Test name
Test status
Simulation time 92315623 ps
CPU time 1.33 seconds
Started Jul 18 07:25:19 PM PDT 24
Finished Jul 18 07:25:25 PM PDT 24
Peak memory 219868 kb
Host smart-2ade1588-1779-4122-a022-ec99a0e2adb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923403135 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.923403135
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/101.edn_alert.1318960345
Short name T28
Test name
Test status
Simulation time 47000487 ps
CPU time 1.18 seconds
Started Jul 18 07:25:47 PM PDT 24
Finished Jul 18 07:25:50 PM PDT 24
Peak memory 221028 kb
Host smart-3e08d1c8-b5f7-442e-9195-d9a6426e7e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318960345 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.1318960345
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/160.edn_alert.1066162144
Short name T530
Test name
Test status
Simulation time 47605564 ps
CPU time 1.26 seconds
Started Jul 18 07:26:18 PM PDT 24
Finished Jul 18 07:26:26 PM PDT 24
Peak memory 221536 kb
Host smart-225f705b-05c3-42f0-8a6d-8aab1d41547f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066162144 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.1066162144
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/103.edn_alert.1843470721
Short name T104
Test name
Test status
Simulation time 106157406 ps
CPU time 1.27 seconds
Started Jul 18 07:25:48 PM PDT 24
Finished Jul 18 07:25:52 PM PDT 24
Peak memory 216024 kb
Host smart-06175447-6cbe-47eb-ae88-ca0ba1bf4b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843470721 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.1843470721
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/104.edn_alert.3508868279
Short name T288
Test name
Test status
Simulation time 24858150 ps
CPU time 1.17 seconds
Started Jul 18 07:25:47 PM PDT 24
Finished Jul 18 07:25:51 PM PDT 24
Peak memory 221056 kb
Host smart-d2660fac-b2f6-4b5f-a469-da12708a37d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508868279 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.3508868279
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert.2137982343
Short name T89
Test name
Test status
Simulation time 81997030 ps
CPU time 1.13 seconds
Started Jul 18 07:22:37 PM PDT 24
Finished Jul 18 07:22:39 PM PDT 24
Peak memory 220992 kb
Host smart-84d20511-484a-4d59-a0dd-fe8ddaf85b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137982343 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.2137982343
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/198.edn_alert.2673193849
Short name T173
Test name
Test status
Simulation time 47971910 ps
CPU time 1.05 seconds
Started Jul 18 07:26:36 PM PDT 24
Finished Jul 18 07:26:46 PM PDT 24
Peak memory 218648 kb
Host smart-bbb0afb0-f420-44fd-95c2-63eede0878ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673193849 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.2673193849
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.1350551213
Short name T133
Test name
Test status
Simulation time 178212019 ps
CPU time 1.04 seconds
Started Jul 18 07:23:36 PM PDT 24
Finished Jul 18 07:23:40 PM PDT 24
Peak memory 217240 kb
Host smart-68dca254-1f52-4545-9975-728ac06c6261
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350551213 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.1350551213
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_alert.1405770937
Short name T752
Test name
Test status
Simulation time 49576140 ps
CPU time 1.22 seconds
Started Jul 18 07:22:02 PM PDT 24
Finished Jul 18 07:22:05 PM PDT 24
Peak memory 219632 kb
Host smart-969a6412-f263-41e8-9fb0-15a5b57c034a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405770937 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.1405770937
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/1.edn_intr.2225824725
Short name T33
Test name
Test status
Simulation time 25235551 ps
CPU time 0.95 seconds
Started Jul 18 07:21:15 PM PDT 24
Finished Jul 18 07:21:21 PM PDT 24
Peak memory 216152 kb
Host smart-f5556139-c004-419b-b5a4-b70c3cca270e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225824725 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.2225824725
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/255.edn_genbits.3384128672
Short name T294
Test name
Test status
Simulation time 81363830 ps
CPU time 2.95 seconds
Started Jul 18 07:26:51 PM PDT 24
Finished Jul 18 07:26:58 PM PDT 24
Peak memory 220588 kb
Host smart-c6aa56fd-b34c-493a-a333-b6c73faf3ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384128672 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.3384128672
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.477754623
Short name T314
Test name
Test status
Simulation time 81324350 ps
CPU time 1.35 seconds
Started Jul 18 07:27:19 PM PDT 24
Finished Jul 18 07:27:24 PM PDT 24
Peak memory 219420 kb
Host smart-fb31b13b-b7a7-49ba-b857-b63add9ce3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477754623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.477754623
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.212214291
Short name T111
Test name
Test status
Simulation time 39886543 ps
CPU time 1.14 seconds
Started Jul 18 07:25:36 PM PDT 24
Finished Jul 18 07:25:40 PM PDT 24
Peak memory 219008 kb
Host smart-87ef1333-c401-4590-a48e-6ef9f1a2d0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212214291 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.212214291
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.3553574124
Short name T124
Test name
Test status
Simulation time 248733651 ps
CPU time 1.01 seconds
Started Jul 18 07:21:29 PM PDT 24
Finished Jul 18 07:21:34 PM PDT 24
Peak memory 217072 kb
Host smart-dfbcbbd1-4bc0-40a3-aff4-40c7ae14c0fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553574124 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.3553574124
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_intr.2147264462
Short name T30
Test name
Test status
Simulation time 20687617 ps
CPU time 1.06 seconds
Started Jul 18 07:22:29 PM PDT 24
Finished Jul 18 07:22:32 PM PDT 24
Peak memory 216096 kb
Host smart-ce2cfe16-0074-4305-b6aa-aa2825b162ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147264462 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.2147264462
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.3780202990
Short name T192
Test name
Test status
Simulation time 117951169 ps
CPU time 1.2 seconds
Started Jul 18 07:22:31 PM PDT 24
Finished Jul 18 07:22:35 PM PDT 24
Peak memory 217060 kb
Host smart-ca23b9e3-0587-427c-b98f-1989a916e6fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780202990 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.3780202990
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_disable.281091945
Short name T197
Test name
Test status
Simulation time 27789873 ps
CPU time 0.85 seconds
Started Jul 18 07:22:45 PM PDT 24
Finished Jul 18 07:22:48 PM PDT 24
Peak memory 216508 kb
Host smart-8d7150d2-874f-412a-83e1-aaed0c3a18d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281091945 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.281091945
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/131.edn_alert.2091009355
Short name T130
Test name
Test status
Simulation time 223284902 ps
CPU time 1.19 seconds
Started Jul 18 07:25:58 PM PDT 24
Finished Jul 18 07:26:00 PM PDT 24
Peak memory 218876 kb
Host smart-1871c424-cd9a-4d4a-8736-9530510fe0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091009355 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.2091009355
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/153.edn_alert.1832036424
Short name T832
Test name
Test status
Simulation time 270602030 ps
CPU time 1.26 seconds
Started Jul 18 07:26:17 PM PDT 24
Finished Jul 18 07:26:23 PM PDT 24
Peak memory 219612 kb
Host smart-2a43b094-2e0f-4e56-9146-dc9bc888f05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832036424 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.1832036424
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/16.edn_disable.3930880100
Short name T578
Test name
Test status
Simulation time 44883983 ps
CPU time 0.88 seconds
Started Jul 18 07:23:03 PM PDT 24
Finished Jul 18 07:23:05 PM PDT 24
Peak memory 216688 kb
Host smart-62a682c6-6bd6-4636-acb5-6b2d171300d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930880100 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.3930880100
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable.231578974
Short name T343
Test name
Test status
Simulation time 114039390 ps
CPU time 0.86 seconds
Started Jul 18 07:23:22 PM PDT 24
Finished Jul 18 07:23:27 PM PDT 24
Peak memory 216580 kb
Host smart-dff12e77-7dee-424b-b8bd-c3e8a7ce4266
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231578974 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.231578974
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.2593650342
Short name T146
Test name
Test status
Simulation time 106065894 ps
CPU time 1.1 seconds
Started Jul 18 07:23:37 PM PDT 24
Finished Jul 18 07:23:41 PM PDT 24
Peak memory 217208 kb
Host smart-fa3e2e32-3e22-4e2a-8cbf-83b99d2476b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593650342 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.2593650342
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.3089479509
Short name T186
Test name
Test status
Simulation time 24698354 ps
CPU time 0.95 seconds
Started Jul 18 07:23:50 PM PDT 24
Finished Jul 18 07:23:52 PM PDT 24
Peak memory 219832 kb
Host smart-fd04a753-c223-4412-9559-f8488b0bbcfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089479509 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.3089479509
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/42.edn_disable.3828358390
Short name T169
Test name
Test status
Simulation time 37822985 ps
CPU time 0.89 seconds
Started Jul 18 07:24:28 PM PDT 24
Finished Jul 18 07:24:34 PM PDT 24
Peak memory 216492 kb
Host smart-0f3d1e7b-8324-44bc-a576-aca0d3eeb5d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828358390 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.3828358390
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/79.edn_alert.3965286953
Short name T166
Test name
Test status
Simulation time 49162592 ps
CPU time 1.13 seconds
Started Jul 18 07:25:20 PM PDT 24
Finished Jul 18 07:25:27 PM PDT 24
Peak memory 216016 kb
Host smart-629bc5a4-c40d-462f-b136-2469f22906a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965286953 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.3965286953
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.888200013
Short name T335
Test name
Test status
Simulation time 17796525 ps
CPU time 0.9 seconds
Started Jul 18 07:22:31 PM PDT 24
Finished Jul 18 07:22:35 PM PDT 24
Peak memory 207032 kb
Host smart-6db90f3a-e3e3-4ff3-8992-c190c3fa6689
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888200013 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.888200013
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/171.edn_genbits.341165887
Short name T71
Test name
Test status
Simulation time 39188644 ps
CPU time 1.36 seconds
Started Jul 18 07:26:36 PM PDT 24
Finished Jul 18 07:26:45 PM PDT 24
Peak memory 219888 kb
Host smart-2c6466ec-e413-4ce2-8386-db775918cb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341165887 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.341165887
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.3283170004
Short name T216
Test name
Test status
Simulation time 45332826 ps
CPU time 1.2 seconds
Started Jul 18 07:25:20 PM PDT 24
Finished Jul 18 07:25:27 PM PDT 24
Peak memory 216020 kb
Host smart-cd4227a7-27e7-4435-8b8c-ff7e862598a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283170004 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.3283170004
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/295.edn_genbits.2562740471
Short name T302
Test name
Test status
Simulation time 256499679 ps
CPU time 1.46 seconds
Started Jul 18 07:27:22 PM PDT 24
Finished Jul 18 07:27:32 PM PDT 24
Peak memory 220556 kb
Host smart-74d9ee1c-695a-432a-9bde-f9a11e740cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562740471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.2562740471
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.2172773857
Short name T97
Test name
Test status
Simulation time 33087934 ps
CPU time 0.91 seconds
Started Jul 18 07:23:49 PM PDT 24
Finished Jul 18 07:23:51 PM PDT 24
Peak memory 215944 kb
Host smart-b78ead7d-e027-47a2-8cdf-75b5498d011c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172773857 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2172773857
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/153.edn_genbits.1822254178
Short name T11
Test name
Test status
Simulation time 137611925 ps
CPU time 1.13 seconds
Started Jul 18 07:26:17 PM PDT 24
Finished Jul 18 07:26:23 PM PDT 24
Peak memory 220168 kb
Host smart-b746e775-8eb1-486b-b43f-306a2b75ee9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822254178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.1822254178
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.1565028217
Short name T319
Test name
Test status
Simulation time 43330695 ps
CPU time 1.79 seconds
Started Jul 18 07:26:46 PM PDT 24
Finished Jul 18 07:26:53 PM PDT 24
Peak memory 218880 kb
Host smart-843fc6d0-f923-431f-b7b3-e1cf90973a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565028217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.1565028217
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.4232768448
Short name T269
Test name
Test status
Simulation time 29881346 ps
CPU time 0.78 seconds
Started Jul 18 06:07:53 PM PDT 24
Finished Jul 18 06:07:56 PM PDT 24
Peak memory 206652 kb
Host smart-5e68854b-98a7-4a1d-a749-bc0cf3faf6a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232768448 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.4232768448
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.576242148
Short name T281
Test name
Test status
Simulation time 164062448 ps
CPU time 2.42 seconds
Started Jul 18 06:07:53 PM PDT 24
Finished Jul 18 06:07:57 PM PDT 24
Peak memory 206892 kb
Host smart-4aefb199-9b63-4fcc-98b3-42dc52d3c5e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576242148 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.576242148
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/default/1.edn_smoke.1917872112
Short name T331
Test name
Test status
Simulation time 43940891 ps
CPU time 0.88 seconds
Started Jul 18 07:21:15 PM PDT 24
Finished Jul 18 07:21:21 PM PDT 24
Peak memory 215572 kb
Host smart-8783804e-417d-4dba-b699-883e58707942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917872112 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1917872112
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.3422938116
Short name T236
Test name
Test status
Simulation time 185423737 ps
CPU time 3.95 seconds
Started Jul 18 07:21:14 PM PDT 24
Finished Jul 18 07:21:21 PM PDT 24
Peak memory 215584 kb
Host smart-ded429ae-5f1d-4b82-9f82-91703f7e5e76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422938116 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.3422938116
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.523635146
Short name T222
Test name
Test status
Simulation time 172134571821 ps
CPU time 2556.23 seconds
Started Jul 18 07:21:21 PM PDT 24
Finished Jul 18 08:04:03 PM PDT 24
Peak memory 232868 kb
Host smart-cadb278e-b72c-4ac3-8ea9-c3c0107c9df1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523635146 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.523635146
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_stress_all.3907795661
Short name T240
Test name
Test status
Simulation time 1783016501 ps
CPU time 3.51 seconds
Started Jul 18 07:22:33 PM PDT 24
Finished Jul 18 07:22:39 PM PDT 24
Peak memory 217404 kb
Host smart-9f3b991c-f71e-4c56-af1e-1c96509ceaec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907795661 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.3907795661
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/106.edn_alert.3922535562
Short name T115
Test name
Test status
Simulation time 39190234 ps
CPU time 1.37 seconds
Started Jul 18 07:25:47 PM PDT 24
Finished Jul 18 07:25:51 PM PDT 24
Peak memory 219052 kb
Host smart-72aca00d-a666-4c6e-a125-754d88521ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922535562 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.3922535562
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.275534910
Short name T305
Test name
Test status
Simulation time 42555514 ps
CPU time 1.6 seconds
Started Jul 18 07:26:14 PM PDT 24
Finished Jul 18 07:26:17 PM PDT 24
Peak memory 218692 kb
Host smart-46cb69bd-bda6-4390-b872-5babe90b612a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275534910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.275534910
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.1670007063
Short name T310
Test name
Test status
Simulation time 27281694 ps
CPU time 1.5 seconds
Started Jul 18 07:26:18 PM PDT 24
Finished Jul 18 07:26:26 PM PDT 24
Peak memory 218924 kb
Host smart-3ae37d90-76cc-4c41-bce7-bb64372db2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670007063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1670007063
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.3102919948
Short name T317
Test name
Test status
Simulation time 55108746 ps
CPU time 1.32 seconds
Started Jul 18 07:26:34 PM PDT 24
Finished Jul 18 07:26:43 PM PDT 24
Peak memory 220136 kb
Host smart-d36d157b-5436-4f82-a3da-dc464aa13add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102919948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3102919948
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.3579233785
Short name T323
Test name
Test status
Simulation time 238063106 ps
CPU time 3.55 seconds
Started Jul 18 07:26:35 PM PDT 24
Finished Jul 18 07:26:47 PM PDT 24
Peak memory 219904 kb
Host smart-86e98a39-76a8-4ae6-9570-7b915ee2de49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579233785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3579233785
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_stress_all.2024624521
Short name T296
Test name
Test status
Simulation time 195293163 ps
CPU time 4.11 seconds
Started Jul 18 07:23:16 PM PDT 24
Finished Jul 18 07:23:21 PM PDT 24
Peak memory 220488 kb
Host smart-0801dd5e-e429-4b38-b9b0-0762652c3a92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024624521 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.2024624521
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/277.edn_genbits.2738592929
Short name T300
Test name
Test status
Simulation time 48563277 ps
CPU time 1.72 seconds
Started Jul 18 07:27:20 PM PDT 24
Finished Jul 18 07:27:27 PM PDT 24
Peak memory 218924 kb
Host smart-c5eb3115-c572-4e03-bacc-d56bbd9d1640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738592929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2738592929
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.1944863224
Short name T925
Test name
Test status
Simulation time 20971325 ps
CPU time 1.16 seconds
Started Jul 18 07:23:06 PM PDT 24
Finished Jul 18 07:23:10 PM PDT 24
Peak memory 216188 kb
Host smart-eaa73455-127d-46cb-99f3-754279626bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944863224 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1944863224
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/110.edn_genbits.3792591416
Short name T779
Test name
Test status
Simulation time 148563574 ps
CPU time 1.61 seconds
Started Jul 18 07:25:47 PM PDT 24
Finished Jul 18 07:25:51 PM PDT 24
Peak memory 220388 kb
Host smart-4a8417e0-a588-43b0-a3bc-60c9a913e3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792591416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.3792591416
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1544862169
Short name T254
Test name
Test status
Simulation time 153036672 ps
CPU time 1.48 seconds
Started Jul 18 06:07:39 PM PDT 24
Finished Jul 18 06:07:42 PM PDT 24
Peak memory 206920 kb
Host smart-ed8c9011-149a-465e-94dc-61fac0675eea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544862169 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1544862169
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1806846726
Short name T259
Test name
Test status
Simulation time 151945553 ps
CPU time 3.62 seconds
Started Jul 18 06:07:42 PM PDT 24
Finished Jul 18 06:07:51 PM PDT 24
Peak memory 206808 kb
Host smart-88909739-bc35-4fd4-8e54-ff0c302a59e5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806846726 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.1806846726
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3488414655
Short name T1002
Test name
Test status
Simulation time 44166751 ps
CPU time 1.16 seconds
Started Jul 18 06:07:39 PM PDT 24
Finished Jul 18 06:07:44 PM PDT 24
Peak memory 215304 kb
Host smart-d73c0c20-300b-40d1-9e37-7f056fae4009
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488414655 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3488414655
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.333020719
Short name T1057
Test name
Test status
Simulation time 24265855 ps
CPU time 0.86 seconds
Started Jul 18 06:07:40 PM PDT 24
Finished Jul 18 06:07:47 PM PDT 24
Peak memory 206788 kb
Host smart-b694ffe3-2457-491f-97d0-3d4d63f03a83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333020719 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.333020719
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1599378386
Short name T1054
Test name
Test status
Simulation time 15569986 ps
CPU time 0.93 seconds
Started Jul 18 06:07:37 PM PDT 24
Finished Jul 18 06:07:40 PM PDT 24
Peak memory 206820 kb
Host smart-dab8c250-196b-4367-b185-b56cf0b9f618
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599378386 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1599378386
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1254794506
Short name T1067
Test name
Test status
Simulation time 35919681 ps
CPU time 1.01 seconds
Started Jul 18 06:07:38 PM PDT 24
Finished Jul 18 06:07:40 PM PDT 24
Peak memory 206952 kb
Host smart-2a6c5daa-3a59-4b2c-a2c9-c49abf9c87d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254794506 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.1254794506
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.1183818906
Short name T1081
Test name
Test status
Simulation time 972472079 ps
CPU time 2.49 seconds
Started Jul 18 06:07:56 PM PDT 24
Finished Jul 18 06:08:02 PM PDT 24
Peak memory 215236 kb
Host smart-02c1ad4c-6b9e-4cc5-a520-2c7247f31caf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183818906 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.1183818906
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.90493172
Short name T1049
Test name
Test status
Simulation time 285420369 ps
CPU time 2.37 seconds
Started Jul 18 06:07:38 PM PDT 24
Finished Jul 18 06:07:43 PM PDT 24
Peak memory 206912 kb
Host smart-ce8323cf-5f71-44a0-b467-70ba4347c4a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90493172 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.90493172
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1501958728
Short name T258
Test name
Test status
Simulation time 28813814 ps
CPU time 1.24 seconds
Started Jul 18 06:07:39 PM PDT 24
Finished Jul 18 06:07:44 PM PDT 24
Peak memory 206820 kb
Host smart-6ad73ff2-c8ab-4bd7-b27d-f04386ef23ca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501958728 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1501958728
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3000963623
Short name T1092
Test name
Test status
Simulation time 117710794 ps
CPU time 3.33 seconds
Started Jul 18 06:07:39 PM PDT 24
Finished Jul 18 06:07:45 PM PDT 24
Peak memory 206784 kb
Host smart-05f12550-9ca8-4f07-bbb4-a5ee7428849b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000963623 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.3000963623
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2447617015
Short name T1053
Test name
Test status
Simulation time 24368024 ps
CPU time 0.82 seconds
Started Jul 18 06:07:38 PM PDT 24
Finished Jul 18 06:07:41 PM PDT 24
Peak memory 206824 kb
Host smart-4e49f5cf-aca2-4f02-b4e8-716fd528adf7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447617015 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.2447617015
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.283054766
Short name T1099
Test name
Test status
Simulation time 55825685 ps
CPU time 1.05 seconds
Started Jul 18 06:07:40 PM PDT 24
Finished Jul 18 06:07:47 PM PDT 24
Peak memory 215188 kb
Host smart-76419d6c-4ed2-4ca5-8653-bb67a7367dda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283054766 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.283054766
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.762404140
Short name T263
Test name
Test status
Simulation time 12230169 ps
CPU time 0.9 seconds
Started Jul 18 06:07:41 PM PDT 24
Finished Jul 18 06:07:48 PM PDT 24
Peak memory 206816 kb
Host smart-a45ed518-cd3c-4baa-9c72-3356dfc4b1ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762404140 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.762404140
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.624974376
Short name T1004
Test name
Test status
Simulation time 32043024 ps
CPU time 0.8 seconds
Started Jul 18 06:07:41 PM PDT 24
Finished Jul 18 06:07:48 PM PDT 24
Peak memory 206844 kb
Host smart-28d254fa-22b2-4156-90a3-41593a1b33d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624974376 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.624974376
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2711255168
Short name T1120
Test name
Test status
Simulation time 131997604 ps
CPU time 1.49 seconds
Started Jul 18 06:07:41 PM PDT 24
Finished Jul 18 06:07:48 PM PDT 24
Peak memory 206876 kb
Host smart-8647c16b-4e25-498d-9d29-1e413d98af3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711255168 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.2711255168
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.3820463897
Short name T1102
Test name
Test status
Simulation time 310952708 ps
CPU time 2.84 seconds
Started Jul 18 06:07:40 PM PDT 24
Finished Jul 18 06:07:47 PM PDT 24
Peak memory 215224 kb
Host smart-2743dc14-92b7-4976-a9d7-573121184bd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820463897 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3820463897
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1112613119
Short name T278
Test name
Test status
Simulation time 133314289 ps
CPU time 2.49 seconds
Started Jul 18 06:07:39 PM PDT 24
Finished Jul 18 06:07:44 PM PDT 24
Peak memory 207052 kb
Host smart-01adf765-df5f-464e-a592-e7e5c3b0cd66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112613119 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1112613119
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2188955381
Short name T1036
Test name
Test status
Simulation time 29056027 ps
CPU time 1.46 seconds
Started Jul 18 06:07:52 PM PDT 24
Finished Jul 18 06:07:56 PM PDT 24
Peak memory 215164 kb
Host smart-c6ae1187-c5ed-4780-b45c-43217e1a2b3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188955381 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.2188955381
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2885555058
Short name T1023
Test name
Test status
Simulation time 14559384 ps
CPU time 0.88 seconds
Started Jul 18 06:07:54 PM PDT 24
Finished Jul 18 06:07:57 PM PDT 24
Peak memory 206824 kb
Host smart-3c997c43-164c-4ef9-b74a-4a1276467311
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885555058 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2885555058
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2226961882
Short name T249
Test name
Test status
Simulation time 21301210 ps
CPU time 1.06 seconds
Started Jul 18 06:07:52 PM PDT 24
Finished Jul 18 06:07:56 PM PDT 24
Peak memory 206876 kb
Host smart-78309b4f-2a31-4497-a8f6-065ebdcc8d25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226961882 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2226961882
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.3009416941
Short name T1055
Test name
Test status
Simulation time 67843435 ps
CPU time 2.62 seconds
Started Jul 18 06:07:58 PM PDT 24
Finished Jul 18 06:08:04 PM PDT 24
Peak memory 215160 kb
Host smart-cfeb8905-fe33-471e-841c-803b1736362b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009416941 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.3009416941
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3664386664
Short name T1084
Test name
Test status
Simulation time 87497121 ps
CPU time 1.52 seconds
Started Jul 18 06:07:53 PM PDT 24
Finished Jul 18 06:07:56 PM PDT 24
Peak memory 206988 kb
Host smart-0000f735-1b95-481d-8999-56c3d6a47a1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664386664 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3664386664
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1076826725
Short name T1066
Test name
Test status
Simulation time 23464672 ps
CPU time 1.28 seconds
Started Jul 18 06:07:58 PM PDT 24
Finished Jul 18 06:08:03 PM PDT 24
Peak memory 215164 kb
Host smart-0588e8a9-b4ab-4883-b9b9-910dcab84b3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076826725 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.1076826725
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.1664663820
Short name T250
Test name
Test status
Simulation time 44932665 ps
CPU time 0.9 seconds
Started Jul 18 06:07:56 PM PDT 24
Finished Jul 18 06:08:01 PM PDT 24
Peak memory 207016 kb
Host smart-460a29ed-ab97-44b6-8539-e96c56e6198a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664663820 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1664663820
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.3268206198
Short name T1028
Test name
Test status
Simulation time 34116343 ps
CPU time 0.78 seconds
Started Jul 18 06:07:52 PM PDT 24
Finished Jul 18 06:07:55 PM PDT 24
Peak memory 206680 kb
Host smart-c63f0edd-1e36-47c8-8077-8fac28bc7bec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268206198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.3268206198
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1666230229
Short name T1074
Test name
Test status
Simulation time 69133901 ps
CPU time 1.12 seconds
Started Jul 18 06:08:00 PM PDT 24
Finished Jul 18 06:08:04 PM PDT 24
Peak memory 206916 kb
Host smart-2322373c-b4f2-4084-9ae4-30220bab233c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666230229 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.1666230229
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.434407443
Short name T1045
Test name
Test status
Simulation time 116731448 ps
CPU time 4.12 seconds
Started Jul 18 06:07:56 PM PDT 24
Finished Jul 18 06:08:05 PM PDT 24
Peak memory 215212 kb
Host smart-2ad3a2aa-223e-476d-ab3b-d14c256514ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434407443 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.434407443
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1619649177
Short name T1051
Test name
Test status
Simulation time 41687936 ps
CPU time 1.51 seconds
Started Jul 18 06:07:51 PM PDT 24
Finished Jul 18 06:07:54 PM PDT 24
Peak memory 215160 kb
Host smart-43473070-97d7-4c48-9ed3-2eea55a6b774
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619649177 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1619649177
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2827370165
Short name T1089
Test name
Test status
Simulation time 15331452 ps
CPU time 1.07 seconds
Started Jul 18 06:07:55 PM PDT 24
Finished Jul 18 06:07:59 PM PDT 24
Peak memory 206940 kb
Host smart-68c69dbe-ea2a-4500-bac3-9e4cffe0d98e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827370165 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.2827370165
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.1402207184
Short name T257
Test name
Test status
Simulation time 45054065 ps
CPU time 0.89 seconds
Started Jul 18 06:07:56 PM PDT 24
Finished Jul 18 06:08:01 PM PDT 24
Peak memory 206820 kb
Host smart-81c46cc8-5f37-429a-91ae-bc91437bdb3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402207184 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.1402207184
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.314295878
Short name T1097
Test name
Test status
Simulation time 16113017 ps
CPU time 0.89 seconds
Started Jul 18 06:07:55 PM PDT 24
Finished Jul 18 06:08:00 PM PDT 24
Peak memory 206976 kb
Host smart-199166d7-3ce9-44a4-b7f7-b6e784d0e1e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314295878 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.314295878
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.359525297
Short name T266
Test name
Test status
Simulation time 31553646 ps
CPU time 1.34 seconds
Started Jul 18 06:07:51 PM PDT 24
Finished Jul 18 06:07:53 PM PDT 24
Peak memory 206876 kb
Host smart-a3d564de-db62-4937-b67d-422770feb550
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359525297 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_ou
tstanding.359525297
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3889521078
Short name T1025
Test name
Test status
Simulation time 97316293 ps
CPU time 3.49 seconds
Started Jul 18 06:07:56 PM PDT 24
Finished Jul 18 06:08:04 PM PDT 24
Peak memory 215236 kb
Host smart-3f861e39-aba3-4f3c-bacf-4810d89b9ffb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889521078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3889521078
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2190478531
Short name T1122
Test name
Test status
Simulation time 81218373 ps
CPU time 1.16 seconds
Started Jul 18 06:07:51 PM PDT 24
Finished Jul 18 06:07:54 PM PDT 24
Peak memory 215248 kb
Host smart-8aa0af64-13a5-4fb5-af98-66c17673c75e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190478531 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2190478531
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.1084074373
Short name T1065
Test name
Test status
Simulation time 15576472 ps
CPU time 0.93 seconds
Started Jul 18 06:07:50 PM PDT 24
Finished Jul 18 06:07:52 PM PDT 24
Peak memory 206816 kb
Host smart-97d2cf1c-8f13-46a0-bdd6-aa874ab31d49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084074373 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1084074373
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.3529256318
Short name T1021
Test name
Test status
Simulation time 14443241 ps
CPU time 0.89 seconds
Started Jul 18 06:07:52 PM PDT 24
Finished Jul 18 06:07:55 PM PDT 24
Peak memory 206836 kb
Host smart-60e99d2e-60a0-499f-833f-97d3f87f82d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529256318 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.3529256318
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2963463084
Short name T1046
Test name
Test status
Simulation time 257498157 ps
CPU time 1.51 seconds
Started Jul 18 06:07:52 PM PDT 24
Finished Jul 18 06:07:56 PM PDT 24
Peak memory 206956 kb
Host smart-52ebc15f-d1f1-4b64-9f5b-ad7b7e3d87b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963463084 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2963463084
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.134394934
Short name T1096
Test name
Test status
Simulation time 77295608 ps
CPU time 2.8 seconds
Started Jul 18 06:07:55 PM PDT 24
Finished Jul 18 06:08:02 PM PDT 24
Peak memory 215092 kb
Host smart-44d127b1-80ba-49fb-8b76-e51b2d0d19a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134394934 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.134394934
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3072566369
Short name T1080
Test name
Test status
Simulation time 61344155 ps
CPU time 1.78 seconds
Started Jul 18 06:07:57 PM PDT 24
Finished Jul 18 06:08:03 PM PDT 24
Peak memory 215084 kb
Host smart-a7e7604a-a109-464e-a2ea-dd695d0da910
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072566369 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.3072566369
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2445769317
Short name T1044
Test name
Test status
Simulation time 13376781 ps
CPU time 0.94 seconds
Started Jul 18 06:07:53 PM PDT 24
Finished Jul 18 06:07:57 PM PDT 24
Peak memory 206944 kb
Host smart-f2ef7b5a-f396-4461-96bc-10946942deb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445769317 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2445769317
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.3817087722
Short name T1125
Test name
Test status
Simulation time 12559726 ps
CPU time 0.91 seconds
Started Jul 18 06:07:56 PM PDT 24
Finished Jul 18 06:08:01 PM PDT 24
Peak memory 206836 kb
Host smart-8703b00b-a6af-40e9-9bf1-3cd512a2c97e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817087722 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.3817087722
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.3090284160
Short name T1082
Test name
Test status
Simulation time 72338141 ps
CPU time 0.85 seconds
Started Jul 18 06:07:56 PM PDT 24
Finished Jul 18 06:08:01 PM PDT 24
Peak memory 206780 kb
Host smart-d471cb2b-8755-4f2b-9c1d-4e6487136364
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090284160 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.3090284160
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1637124179
Short name T1106
Test name
Test status
Simulation time 158865306 ps
CPU time 0.99 seconds
Started Jul 18 06:07:51 PM PDT 24
Finished Jul 18 06:07:54 PM PDT 24
Peak memory 206944 kb
Host smart-94c74a05-fac2-4527-9924-bb277f6e3adf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637124179 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.1637124179
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.545267908
Short name T1114
Test name
Test status
Simulation time 146658794 ps
CPU time 1.76 seconds
Started Jul 18 06:07:52 PM PDT 24
Finished Jul 18 06:07:56 PM PDT 24
Peak memory 215232 kb
Host smart-f8f77a98-f42f-42ac-868e-4d6121df1948
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545267908 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.545267908
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3398809157
Short name T1024
Test name
Test status
Simulation time 55300087 ps
CPU time 1.81 seconds
Started Jul 18 06:07:54 PM PDT 24
Finished Jul 18 06:07:58 PM PDT 24
Peak memory 206860 kb
Host smart-248ff28c-e53a-459c-8f2a-cc1290d15612
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398809157 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.3398809157
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2056730019
Short name T1052
Test name
Test status
Simulation time 14252494 ps
CPU time 0.98 seconds
Started Jul 18 06:07:55 PM PDT 24
Finished Jul 18 06:08:00 PM PDT 24
Peak memory 206928 kb
Host smart-5487e15e-2852-4ea3-a072-a3803ec219f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056730019 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2056730019
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.942651283
Short name T1115
Test name
Test status
Simulation time 53461506 ps
CPU time 0.84 seconds
Started Jul 18 06:07:55 PM PDT 24
Finished Jul 18 06:08:00 PM PDT 24
Peak memory 206756 kb
Host smart-2c280e8c-44bd-4814-b543-e4a095663deb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942651283 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.942651283
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.2203719627
Short name T1000
Test name
Test status
Simulation time 24961460 ps
CPU time 0.9 seconds
Started Jul 18 06:07:56 PM PDT 24
Finished Jul 18 06:08:01 PM PDT 24
Peak memory 206848 kb
Host smart-3fc86e1c-cf6a-4a4a-95a9-38520bfc7a9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203719627 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.2203719627
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2023106786
Short name T268
Test name
Test status
Simulation time 110893338 ps
CPU time 1.3 seconds
Started Jul 18 06:07:54 PM PDT 24
Finished Jul 18 06:07:58 PM PDT 24
Peak memory 206904 kb
Host smart-eb0b8199-6ae1-4992-ad5d-03740b1c5931
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023106786 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.2023106786
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.394843557
Short name T1087
Test name
Test status
Simulation time 292903962 ps
CPU time 2.81 seconds
Started Jul 18 06:07:53 PM PDT 24
Finished Jul 18 06:07:58 PM PDT 24
Peak memory 215212 kb
Host smart-43364309-c1c0-4502-8bfa-b9b63417e87b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394843557 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.394843557
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.313341343
Short name T277
Test name
Test status
Simulation time 310713126 ps
CPU time 2.34 seconds
Started Jul 18 06:08:00 PM PDT 24
Finished Jul 18 06:08:05 PM PDT 24
Peak memory 206848 kb
Host smart-ee930b94-3308-43d7-8d88-2dc664d8e789
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313341343 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.313341343
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.4166700672
Short name T1079
Test name
Test status
Simulation time 59575739 ps
CPU time 1.02 seconds
Started Jul 18 06:07:57 PM PDT 24
Finished Jul 18 06:08:02 PM PDT 24
Peak memory 206968 kb
Host smart-42592256-51a5-4341-93db-d626dd578374
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166700672 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.4166700672
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.1962074249
Short name T267
Test name
Test status
Simulation time 13155407 ps
CPU time 0.85 seconds
Started Jul 18 06:08:18 PM PDT 24
Finished Jul 18 06:08:21 PM PDT 24
Peak memory 206660 kb
Host smart-50f3208c-4c89-4040-b397-76bb70a2def4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962074249 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1962074249
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3478174888
Short name T1019
Test name
Test status
Simulation time 36746065 ps
CPU time 0.85 seconds
Started Jul 18 06:07:56 PM PDT 24
Finished Jul 18 06:08:01 PM PDT 24
Peak memory 206672 kb
Host smart-6b62da72-c7b9-4e80-945e-1db6df35bcb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478174888 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3478174888
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.216731727
Short name T1068
Test name
Test status
Simulation time 58378883 ps
CPU time 1.13 seconds
Started Jul 18 06:07:55 PM PDT 24
Finished Jul 18 06:07:59 PM PDT 24
Peak memory 206964 kb
Host smart-c99cf16c-9f1f-4ae0-867d-abe03c1be715
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216731727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_ou
tstanding.216731727
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.3507807478
Short name T1011
Test name
Test status
Simulation time 94372181 ps
CPU time 2.37 seconds
Started Jul 18 06:07:53 PM PDT 24
Finished Jul 18 06:07:57 PM PDT 24
Peak memory 215164 kb
Host smart-e619f84c-06a7-42e5-9ff6-9be2c370121f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507807478 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3507807478
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2835467453
Short name T1064
Test name
Test status
Simulation time 65601827 ps
CPU time 1.53 seconds
Started Jul 18 06:07:56 PM PDT 24
Finished Jul 18 06:08:01 PM PDT 24
Peak memory 223336 kb
Host smart-a0017c1b-3b6c-4462-956f-d8336a5a2411
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835467453 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2835467453
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.1207489830
Short name T1008
Test name
Test status
Simulation time 41397079 ps
CPU time 0.85 seconds
Started Jul 18 06:07:57 PM PDT 24
Finished Jul 18 06:08:02 PM PDT 24
Peak memory 206660 kb
Host smart-299f3166-66ae-4f14-8b2f-bd7432e5bc0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207489830 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1207489830
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.2090098918
Short name T1130
Test name
Test status
Simulation time 14673842 ps
CPU time 0.93 seconds
Started Jul 18 06:07:57 PM PDT 24
Finished Jul 18 06:08:02 PM PDT 24
Peak memory 206844 kb
Host smart-61a8ff86-6f1f-40f5-bf46-458c69b4c32a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090098918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.2090098918
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2196260166
Short name T1061
Test name
Test status
Simulation time 21151801 ps
CPU time 1.07 seconds
Started Jul 18 06:07:55 PM PDT 24
Finished Jul 18 06:08:00 PM PDT 24
Peak memory 206956 kb
Host smart-1ef76078-7ce2-49a3-ad97-22ae4193c9a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196260166 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.2196260166
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.2827044680
Short name T1095
Test name
Test status
Simulation time 403118471 ps
CPU time 4.12 seconds
Started Jul 18 06:07:53 PM PDT 24
Finished Jul 18 06:07:59 PM PDT 24
Peak memory 215148 kb
Host smart-2440f854-33d0-40fc-9052-519007380cdc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827044680 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.2827044680
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3828885158
Short name T1018
Test name
Test status
Simulation time 40509095 ps
CPU time 1.52 seconds
Started Jul 18 06:07:56 PM PDT 24
Finished Jul 18 06:08:02 PM PDT 24
Peak memory 206952 kb
Host smart-36f9c725-cfea-4614-8a5b-8ad973b300be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828885158 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3828885158
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1408172101
Short name T1121
Test name
Test status
Simulation time 52564880 ps
CPU time 1.38 seconds
Started Jul 18 06:08:00 PM PDT 24
Finished Jul 18 06:08:04 PM PDT 24
Peak memory 217924 kb
Host smart-0a73db10-ddf1-4145-8be7-196596ecd22b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408172101 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.1408172101
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.337209686
Short name T255
Test name
Test status
Simulation time 47481737 ps
CPU time 0.91 seconds
Started Jul 18 06:07:55 PM PDT 24
Finished Jul 18 06:07:59 PM PDT 24
Peak memory 206824 kb
Host smart-12991201-dfa3-4549-8b64-d7f05bae0d42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337209686 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.337209686
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.1671581623
Short name T1117
Test name
Test status
Simulation time 18978080 ps
CPU time 0.9 seconds
Started Jul 18 06:07:55 PM PDT 24
Finished Jul 18 06:07:59 PM PDT 24
Peak memory 206828 kb
Host smart-d3e4ad23-f333-4794-b083-d2f10a50197d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671581623 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.1671581623
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1517199083
Short name T1043
Test name
Test status
Simulation time 247873148 ps
CPU time 1.21 seconds
Started Jul 18 06:07:55 PM PDT 24
Finished Jul 18 06:08:00 PM PDT 24
Peak memory 206932 kb
Host smart-a17ea8fc-286c-44fd-89c3-73f90e6102a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517199083 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.1517199083
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.192405336
Short name T1059
Test name
Test status
Simulation time 70781962 ps
CPU time 2.92 seconds
Started Jul 18 06:07:53 PM PDT 24
Finished Jul 18 06:07:58 PM PDT 24
Peak memory 215220 kb
Host smart-adbbeb72-c7cc-4278-915b-b646c61bdff1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192405336 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.192405336
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3468825397
Short name T1118
Test name
Test status
Simulation time 128809162 ps
CPU time 2.63 seconds
Started Jul 18 06:07:57 PM PDT 24
Finished Jul 18 06:08:04 PM PDT 24
Peak memory 206884 kb
Host smart-5b05effe-a35a-4738-b10c-59ccf8529cbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468825397 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.3468825397
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2354539498
Short name T1088
Test name
Test status
Simulation time 80720952 ps
CPU time 1.81 seconds
Started Jul 18 06:07:56 PM PDT 24
Finished Jul 18 06:08:02 PM PDT 24
Peak memory 215248 kb
Host smart-5c73aa17-120f-43d9-9ea6-eb385a7b50db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354539498 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.2354539498
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.4008452877
Short name T253
Test name
Test status
Simulation time 31174825 ps
CPU time 0.85 seconds
Started Jul 18 06:07:56 PM PDT 24
Finished Jul 18 06:08:01 PM PDT 24
Peak memory 206824 kb
Host smart-e4671b19-a402-4078-8a69-7974f227ac9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008452877 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.4008452877
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.1743486677
Short name T1129
Test name
Test status
Simulation time 31127572 ps
CPU time 0.78 seconds
Started Jul 18 06:07:56 PM PDT 24
Finished Jul 18 06:08:01 PM PDT 24
Peak memory 206648 kb
Host smart-0a447fce-d248-4c84-bf8a-c983a43d1616
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743486677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.1743486677
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1103738802
Short name T1126
Test name
Test status
Simulation time 39383348 ps
CPU time 1.18 seconds
Started Jul 18 06:07:55 PM PDT 24
Finished Jul 18 06:08:00 PM PDT 24
Peak memory 207080 kb
Host smart-3a8c264c-ad07-4672-9e26-f688383bad2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103738802 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.1103738802
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.3123307899
Short name T1041
Test name
Test status
Simulation time 23262810 ps
CPU time 1.56 seconds
Started Jul 18 06:08:00 PM PDT 24
Finished Jul 18 06:08:04 PM PDT 24
Peak memory 215196 kb
Host smart-6edbd062-b367-4b06-9762-db8dccbbc71e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123307899 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.3123307899
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1984504634
Short name T1091
Test name
Test status
Simulation time 281128106 ps
CPU time 1.5 seconds
Started Jul 18 06:08:04 PM PDT 24
Finished Jul 18 06:08:08 PM PDT 24
Peak memory 206916 kb
Host smart-79f0589a-a926-47cb-b372-3751018b499f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984504634 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1984504634
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3759091962
Short name T260
Test name
Test status
Simulation time 38102132 ps
CPU time 1.27 seconds
Started Jul 18 06:07:37 PM PDT 24
Finished Jul 18 06:07:40 PM PDT 24
Peak memory 206896 kb
Host smart-06fe3c3e-bca0-4f54-9f26-398526d1fe59
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759091962 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.3759091962
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3018388934
Short name T1116
Test name
Test status
Simulation time 261155575 ps
CPU time 5.12 seconds
Started Jul 18 06:07:40 PM PDT 24
Finished Jul 18 06:07:49 PM PDT 24
Peak memory 206852 kb
Host smart-9b79b565-e1c1-43ea-886a-d87325805a3a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018388934 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.3018388934
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1565644783
Short name T1124
Test name
Test status
Simulation time 28105566 ps
CPU time 0.91 seconds
Started Jul 18 06:07:41 PM PDT 24
Finished Jul 18 06:07:48 PM PDT 24
Peak memory 206832 kb
Host smart-dd238030-c865-467a-8b97-7a84a7cffcfc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565644783 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1565644783
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3280699384
Short name T1033
Test name
Test status
Simulation time 344253357 ps
CPU time 1.74 seconds
Started Jul 18 06:07:40 PM PDT 24
Finished Jul 18 06:07:47 PM PDT 24
Peak memory 215176 kb
Host smart-50442384-96d8-4907-b77c-d2b6e854137d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280699384 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3280699384
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.957750212
Short name T997
Test name
Test status
Simulation time 103880903 ps
CPU time 0.89 seconds
Started Jul 18 06:07:38 PM PDT 24
Finished Jul 18 06:07:41 PM PDT 24
Peak memory 206820 kb
Host smart-e42bcaa2-7fd1-4ee0-a660-f5669cfd7b6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957750212 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.957750212
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.2099472217
Short name T1119
Test name
Test status
Simulation time 25201484 ps
CPU time 0.88 seconds
Started Jul 18 06:07:37 PM PDT 24
Finished Jul 18 06:07:38 PM PDT 24
Peak memory 206848 kb
Host smart-4f081486-d943-436e-8e4a-bbfc1785a821
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099472217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.2099472217
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.4191438509
Short name T264
Test name
Test status
Simulation time 70643312 ps
CPU time 1.4 seconds
Started Jul 18 06:07:40 PM PDT 24
Finished Jul 18 06:07:45 PM PDT 24
Peak memory 206800 kb
Host smart-0365b91a-8726-499d-9d96-b9b1b1e1a1b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191438509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.4191438509
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.2963644028
Short name T1103
Test name
Test status
Simulation time 285300528 ps
CPU time 3.71 seconds
Started Jul 18 06:07:43 PM PDT 24
Finished Jul 18 06:07:52 PM PDT 24
Peak memory 215144 kb
Host smart-d90c5ae5-b322-495f-a177-db50db8eebd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963644028 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.2963644028
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3616794920
Short name T1101
Test name
Test status
Simulation time 130425934 ps
CPU time 2.64 seconds
Started Jul 18 06:07:41 PM PDT 24
Finished Jul 18 06:07:50 PM PDT 24
Peak memory 207052 kb
Host smart-34c24652-9777-4698-b7ad-dfad52054c6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616794920 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3616794920
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.3341227882
Short name T1111
Test name
Test status
Simulation time 32982592 ps
CPU time 0.79 seconds
Started Jul 18 06:07:56 PM PDT 24
Finished Jul 18 06:08:01 PM PDT 24
Peak memory 206660 kb
Host smart-88a7115b-91b6-40de-aa2c-e83278b02c9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341227882 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3341227882
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.67923608
Short name T1030
Test name
Test status
Simulation time 14798186 ps
CPU time 0.92 seconds
Started Jul 18 06:07:59 PM PDT 24
Finished Jul 18 06:08:03 PM PDT 24
Peak memory 206800 kb
Host smart-1eef1245-5f15-41a7-8690-47d220b4f6dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67923608 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.67923608
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.4137472722
Short name T1017
Test name
Test status
Simulation time 204725394 ps
CPU time 1.04 seconds
Started Jul 18 06:07:58 PM PDT 24
Finished Jul 18 06:08:03 PM PDT 24
Peak memory 206844 kb
Host smart-b6a782f1-a5b0-4e9c-a2bf-6b8255c6147d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137472722 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.4137472722
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.2316635571
Short name T1127
Test name
Test status
Simulation time 14374438 ps
CPU time 0.91 seconds
Started Jul 18 06:07:59 PM PDT 24
Finished Jul 18 06:08:03 PM PDT 24
Peak memory 206796 kb
Host smart-835f9397-9315-4761-89e7-633d6e90dd3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316635571 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2316635571
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.1324677542
Short name T1003
Test name
Test status
Simulation time 44036803 ps
CPU time 0.86 seconds
Started Jul 18 06:07:59 PM PDT 24
Finished Jul 18 06:08:03 PM PDT 24
Peak memory 206844 kb
Host smart-565f617e-b3c3-4cd3-910e-cd0e003bf207
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324677542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.1324677542
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3927434039
Short name T1058
Test name
Test status
Simulation time 64759957 ps
CPU time 0.81 seconds
Started Jul 18 06:07:52 PM PDT 24
Finished Jul 18 06:07:55 PM PDT 24
Peak memory 206848 kb
Host smart-ea4ae44c-5adf-41f1-87ae-924210edf401
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927434039 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3927434039
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.381748612
Short name T1073
Test name
Test status
Simulation time 20212694 ps
CPU time 0.84 seconds
Started Jul 18 06:08:05 PM PDT 24
Finished Jul 18 06:08:08 PM PDT 24
Peak memory 206596 kb
Host smart-ba24851d-02fd-4392-9346-a4cc880d98a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381748612 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.381748612
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.791672471
Short name T1076
Test name
Test status
Simulation time 14658649 ps
CPU time 0.92 seconds
Started Jul 18 06:08:05 PM PDT 24
Finished Jul 18 06:08:08 PM PDT 24
Peak memory 206656 kb
Host smart-c1c453c5-9aeb-4c2c-a6bd-32846388c781
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791672471 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.791672471
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.1013350461
Short name T1042
Test name
Test status
Simulation time 14145121 ps
CPU time 0.92 seconds
Started Jul 18 06:08:03 PM PDT 24
Finished Jul 18 06:08:06 PM PDT 24
Peak memory 206852 kb
Host smart-599ae85a-3c61-4745-a33d-3d11c8b7a9be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013350461 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.1013350461
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.1298365746
Short name T1037
Test name
Test status
Simulation time 15003728 ps
CPU time 0.92 seconds
Started Jul 18 06:08:05 PM PDT 24
Finished Jul 18 06:08:09 PM PDT 24
Peak memory 206836 kb
Host smart-40f38ea3-9d01-419f-924a-f599a93ca3bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298365746 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1298365746
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2395480018
Short name T262
Test name
Test status
Simulation time 99375804 ps
CPU time 0.98 seconds
Started Jul 18 06:07:44 PM PDT 24
Finished Jul 18 06:07:50 PM PDT 24
Peak memory 206852 kb
Host smart-bc80b107-fc79-474f-847f-0305e473b291
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395480018 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.2395480018
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1624066950
Short name T1006
Test name
Test status
Simulation time 357556612 ps
CPU time 2.81 seconds
Started Jul 18 06:07:38 PM PDT 24
Finished Jul 18 06:07:42 PM PDT 24
Peak memory 206800 kb
Host smart-d0827fdd-e4b1-44eb-8064-1651c71b407f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624066950 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1624066950
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2592636775
Short name T1062
Test name
Test status
Simulation time 16602428 ps
CPU time 0.96 seconds
Started Jul 18 06:07:41 PM PDT 24
Finished Jul 18 06:07:49 PM PDT 24
Peak memory 207016 kb
Host smart-82113641-3bb4-4b73-adf4-b439951ff106
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592636775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2592636775
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3423807922
Short name T1007
Test name
Test status
Simulation time 36692207 ps
CPU time 1.6 seconds
Started Jul 18 06:07:40 PM PDT 24
Finished Jul 18 06:07:47 PM PDT 24
Peak memory 215144 kb
Host smart-5c5d46f1-9eb2-499e-bf47-40adfee23700
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423807922 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3423807922
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.4095496708
Short name T252
Test name
Test status
Simulation time 17302987 ps
CPU time 0.96 seconds
Started Jul 18 06:07:40 PM PDT 24
Finished Jul 18 06:07:47 PM PDT 24
Peak memory 206800 kb
Host smart-14976c1c-4ffc-4038-a983-cf1b7273d369
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095496708 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.4095496708
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.3750149016
Short name T1013
Test name
Test status
Simulation time 11370158 ps
CPU time 0.83 seconds
Started Jul 18 06:07:42 PM PDT 24
Finished Jul 18 06:07:48 PM PDT 24
Peak memory 206828 kb
Host smart-8ee164ea-b930-44ae-b32c-52711d0b9b8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750149016 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.3750149016
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2628013430
Short name T1063
Test name
Test status
Simulation time 29176841 ps
CPU time 1.09 seconds
Started Jul 18 06:07:39 PM PDT 24
Finished Jul 18 06:07:43 PM PDT 24
Peak memory 206876 kb
Host smart-3f38baaf-eb52-4cb4-b26c-f855fe7f0a69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628013430 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.2628013430
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.2306651624
Short name T1038
Test name
Test status
Simulation time 43445756 ps
CPU time 1.84 seconds
Started Jul 18 06:07:41 PM PDT 24
Finished Jul 18 06:07:49 PM PDT 24
Peak memory 215228 kb
Host smart-e2f5be8a-0171-4522-b4bf-ab3e0f451b23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306651624 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.2306651624
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3510469052
Short name T274
Test name
Test status
Simulation time 132595233 ps
CPU time 2.19 seconds
Started Jul 18 06:07:42 PM PDT 24
Finished Jul 18 06:07:50 PM PDT 24
Peak memory 206992 kb
Host smart-0b404c8d-807f-43f1-ad53-a58e1389d9b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510469052 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3510469052
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2584654777
Short name T1027
Test name
Test status
Simulation time 11903926 ps
CPU time 0.84 seconds
Started Jul 18 06:08:04 PM PDT 24
Finished Jul 18 06:08:08 PM PDT 24
Peak memory 206832 kb
Host smart-9cd1c386-1c21-44c8-94da-b16ef8d69fc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584654777 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2584654777
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.2757526856
Short name T998
Test name
Test status
Simulation time 122291621 ps
CPU time 0.77 seconds
Started Jul 18 06:07:56 PM PDT 24
Finished Jul 18 06:08:01 PM PDT 24
Peak memory 206640 kb
Host smart-b6cab049-d969-467d-90c2-616f4fbed929
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757526856 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2757526856
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.3429693161
Short name T1123
Test name
Test status
Simulation time 24063657 ps
CPU time 0.85 seconds
Started Jul 18 06:07:57 PM PDT 24
Finished Jul 18 06:08:02 PM PDT 24
Peak memory 206816 kb
Host smart-d69ec70a-9136-4db5-aec1-0fa137301d81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429693161 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3429693161
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.4017565893
Short name T1075
Test name
Test status
Simulation time 14812955 ps
CPU time 0.88 seconds
Started Jul 18 06:08:03 PM PDT 24
Finished Jul 18 06:08:06 PM PDT 24
Peak memory 206836 kb
Host smart-65730528-06e8-4e04-9d89-25a81f70840f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017565893 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.4017565893
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.2504616212
Short name T1031
Test name
Test status
Simulation time 12209000 ps
CPU time 0.8 seconds
Started Jul 18 06:08:04 PM PDT 24
Finished Jul 18 06:08:08 PM PDT 24
Peak memory 206836 kb
Host smart-c3ce26a8-f7bc-4e09-8ab1-88e6193f4f98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504616212 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.2504616212
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.4267867325
Short name T1010
Test name
Test status
Simulation time 17820388 ps
CPU time 0.96 seconds
Started Jul 18 06:07:54 PM PDT 24
Finished Jul 18 06:07:58 PM PDT 24
Peak memory 206828 kb
Host smart-06eda497-d529-4ea1-96e3-5a18f9624615
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267867325 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.4267867325
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.1842952212
Short name T1070
Test name
Test status
Simulation time 27330515 ps
CPU time 0.9 seconds
Started Jul 18 06:08:04 PM PDT 24
Finished Jul 18 06:08:08 PM PDT 24
Peak memory 206852 kb
Host smart-b0f73649-10b4-46a0-b14b-4158f372ff51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842952212 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.1842952212
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.3358027933
Short name T999
Test name
Test status
Simulation time 23310664 ps
CPU time 0.87 seconds
Started Jul 18 06:08:02 PM PDT 24
Finished Jul 18 06:08:06 PM PDT 24
Peak memory 206836 kb
Host smart-7490c12c-b93e-4caf-8f46-48c286842b48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358027933 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.3358027933
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.2928519254
Short name T1094
Test name
Test status
Simulation time 12877539 ps
CPU time 0.88 seconds
Started Jul 18 06:08:07 PM PDT 24
Finished Jul 18 06:08:10 PM PDT 24
Peak memory 206828 kb
Host smart-fb6dc827-8289-4766-a494-2b329c7a70d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928519254 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.2928519254
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.2035736203
Short name T1109
Test name
Test status
Simulation time 69102535 ps
CPU time 0.84 seconds
Started Jul 18 06:07:54 PM PDT 24
Finished Jul 18 06:07:57 PM PDT 24
Peak memory 206660 kb
Host smart-9a2bba3f-5735-4c64-9fff-53e50998710c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035736203 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.2035736203
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2101017198
Short name T1071
Test name
Test status
Simulation time 45865799 ps
CPU time 1.14 seconds
Started Jul 18 06:07:39 PM PDT 24
Finished Jul 18 06:07:43 PM PDT 24
Peak memory 206836 kb
Host smart-0174f45f-efdf-40b4-970c-2baec7d62f5a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101017198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.2101017198
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3733400738
Short name T1078
Test name
Test status
Simulation time 176570167 ps
CPU time 5.13 seconds
Started Jul 18 06:07:41 PM PDT 24
Finished Jul 18 06:07:52 PM PDT 24
Peak memory 206748 kb
Host smart-7b9ed959-e8ac-4b9f-b514-b33e5d2c52ab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733400738 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.3733400738
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.82501187
Short name T1020
Test name
Test status
Simulation time 97463622 ps
CPU time 0.87 seconds
Started Jul 18 06:07:40 PM PDT 24
Finished Jul 18 06:07:44 PM PDT 24
Peak memory 206728 kb
Host smart-7711a3e9-5fcc-4cfb-b9e0-2de4d6e9b952
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82501187 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.82501187
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2578817933
Short name T1108
Test name
Test status
Simulation time 82922557 ps
CPU time 1.48 seconds
Started Jul 18 06:07:41 PM PDT 24
Finished Jul 18 06:07:48 PM PDT 24
Peak memory 215140 kb
Host smart-eabb46e2-f807-479c-a4d3-ce2c27b822f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578817933 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.2578817933
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.2518708904
Short name T265
Test name
Test status
Simulation time 14302213 ps
CPU time 0.93 seconds
Started Jul 18 06:07:40 PM PDT 24
Finished Jul 18 06:07:46 PM PDT 24
Peak memory 206836 kb
Host smart-42abf586-9c9b-42bf-ae9e-ccfa8e3ff856
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518708904 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2518708904
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.4251825687
Short name T1035
Test name
Test status
Simulation time 17761432 ps
CPU time 0.89 seconds
Started Jul 18 06:07:41 PM PDT 24
Finished Jul 18 06:07:48 PM PDT 24
Peak memory 206972 kb
Host smart-8547eddd-99e7-4069-b80a-5a5dfb846e4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251825687 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.4251825687
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3478597593
Short name T1056
Test name
Test status
Simulation time 77281789 ps
CPU time 1.35 seconds
Started Jul 18 06:07:41 PM PDT 24
Finished Jul 18 06:07:48 PM PDT 24
Peak memory 206800 kb
Host smart-4e51bb8c-ac27-412e-8a9d-208c384afb20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478597593 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.3478597593
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.3586359960
Short name T1026
Test name
Test status
Simulation time 273935981 ps
CPU time 1.61 seconds
Started Jul 18 06:07:40 PM PDT 24
Finished Jul 18 06:07:46 PM PDT 24
Peak memory 215188 kb
Host smart-b2b155d1-954a-410c-bd1e-b17b7443460a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586359960 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.3586359960
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1320911077
Short name T1060
Test name
Test status
Simulation time 113928627 ps
CPU time 2.88 seconds
Started Jul 18 06:07:41 PM PDT 24
Finished Jul 18 06:07:49 PM PDT 24
Peak memory 206912 kb
Host smart-1290e161-962b-4761-9da7-05a0254a27ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320911077 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.1320911077
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.3290563118
Short name T1014
Test name
Test status
Simulation time 37660684 ps
CPU time 0.9 seconds
Started Jul 18 06:08:07 PM PDT 24
Finished Jul 18 06:08:10 PM PDT 24
Peak memory 206840 kb
Host smart-f5730c0e-6b61-4d03-9e63-e338244585cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290563118 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.3290563118
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.1579353536
Short name T1047
Test name
Test status
Simulation time 43958470 ps
CPU time 0.85 seconds
Started Jul 18 06:08:07 PM PDT 24
Finished Jul 18 06:08:10 PM PDT 24
Peak memory 206848 kb
Host smart-afcb3ffe-da1f-46f9-bdec-7d1c7e9789d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579353536 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1579353536
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.2425844991
Short name T1072
Test name
Test status
Simulation time 14277377 ps
CPU time 0.91 seconds
Started Jul 18 06:08:07 PM PDT 24
Finished Jul 18 06:08:10 PM PDT 24
Peak memory 206808 kb
Host smart-4cf1e7e9-004e-406d-9382-ed78694fc9e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425844991 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.2425844991
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.804989056
Short name T1100
Test name
Test status
Simulation time 20916034 ps
CPU time 0.97 seconds
Started Jul 18 06:08:05 PM PDT 24
Finished Jul 18 06:08:08 PM PDT 24
Peak memory 206840 kb
Host smart-18e77473-0200-42fb-9acd-8ffdc2e26c61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804989056 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.804989056
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.2001419365
Short name T1086
Test name
Test status
Simulation time 80322818 ps
CPU time 0.81 seconds
Started Jul 18 06:08:05 PM PDT 24
Finished Jul 18 06:08:08 PM PDT 24
Peak memory 206668 kb
Host smart-46e5d52c-f97b-406d-b0fb-37bbdfdc328a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001419365 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2001419365
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.1249750324
Short name T1085
Test name
Test status
Simulation time 118194877 ps
CPU time 0.87 seconds
Started Jul 18 06:07:54 PM PDT 24
Finished Jul 18 06:07:57 PM PDT 24
Peak memory 206836 kb
Host smart-d93bd45a-779a-495a-9ea7-56e2d0fbd6fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249750324 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1249750324
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1928664659
Short name T1090
Test name
Test status
Simulation time 28910681 ps
CPU time 0.9 seconds
Started Jul 18 06:08:23 PM PDT 24
Finished Jul 18 06:08:27 PM PDT 24
Peak memory 206840 kb
Host smart-691d0222-4e39-49ef-a0ba-8ad875887f5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928664659 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1928664659
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.2562322534
Short name T1009
Test name
Test status
Simulation time 67151412 ps
CPU time 0.92 seconds
Started Jul 18 06:08:19 PM PDT 24
Finished Jul 18 06:08:24 PM PDT 24
Peak memory 206792 kb
Host smart-cb904a19-6e32-43d8-8aa2-e7a54848e5ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562322534 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.2562322534
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.4093229996
Short name T1093
Test name
Test status
Simulation time 100790444 ps
CPU time 0.92 seconds
Started Jul 18 06:08:21 PM PDT 24
Finished Jul 18 06:08:26 PM PDT 24
Peak memory 206804 kb
Host smart-9730c2b3-4f41-47f8-b86e-be288b9f3feb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093229996 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.4093229996
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.2796504567
Short name T1048
Test name
Test status
Simulation time 12932058 ps
CPU time 0.91 seconds
Started Jul 18 06:08:18 PM PDT 24
Finished Jul 18 06:08:21 PM PDT 24
Peak memory 206816 kb
Host smart-59db9d5d-bcb0-4800-8ebe-55d6b0ca85e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796504567 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.2796504567
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1942623197
Short name T1016
Test name
Test status
Simulation time 29595177 ps
CPU time 1 seconds
Started Jul 18 06:07:44 PM PDT 24
Finished Jul 18 06:07:50 PM PDT 24
Peak memory 206996 kb
Host smart-030624d7-46e6-48eb-8f95-550c11fe79d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942623197 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1942623197
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.1411806599
Short name T248
Test name
Test status
Simulation time 11899398 ps
CPU time 0.85 seconds
Started Jul 18 06:07:40 PM PDT 24
Finished Jul 18 06:07:46 PM PDT 24
Peak memory 206792 kb
Host smart-128b3db1-b788-4ff6-b22a-ce28f10572b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411806599 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.1411806599
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.934268355
Short name T1040
Test name
Test status
Simulation time 18347650 ps
CPU time 0.88 seconds
Started Jul 18 06:07:42 PM PDT 24
Finished Jul 18 06:07:48 PM PDT 24
Peak memory 206824 kb
Host smart-d12cada2-cfc8-4742-874a-4039146a83e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934268355 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.934268355
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2209924612
Short name T1113
Test name
Test status
Simulation time 107970466 ps
CPU time 1.32 seconds
Started Jul 18 06:07:39 PM PDT 24
Finished Jul 18 06:07:44 PM PDT 24
Peak memory 206956 kb
Host smart-30c7f1e5-7556-4a15-923b-0833e3f5f4cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209924612 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.2209924612
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.1745979412
Short name T1069
Test name
Test status
Simulation time 222747608 ps
CPU time 3.36 seconds
Started Jul 18 06:07:41 PM PDT 24
Finished Jul 18 06:07:50 PM PDT 24
Peak memory 215172 kb
Host smart-3f0cea7c-1cfc-4932-82e7-dfbf67eec025
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745979412 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.1745979412
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2773198271
Short name T273
Test name
Test status
Simulation time 92859715 ps
CPU time 2.47 seconds
Started Jul 18 06:07:39 PM PDT 24
Finished Jul 18 06:07:44 PM PDT 24
Peak memory 206888 kb
Host smart-8186a425-d43b-4678-a590-0d9e4fd3477b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773198271 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2773198271
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.222301738
Short name T1005
Test name
Test status
Simulation time 232575566 ps
CPU time 1.2 seconds
Started Jul 18 06:07:40 PM PDT 24
Finished Jul 18 06:07:47 PM PDT 24
Peak memory 216992 kb
Host smart-e771f6cb-b84b-4579-a8d2-351d4799040d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222301738 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.222301738
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.3149108556
Short name T1029
Test name
Test status
Simulation time 40669181 ps
CPU time 0.8 seconds
Started Jul 18 06:07:41 PM PDT 24
Finished Jul 18 06:07:47 PM PDT 24
Peak memory 206628 kb
Host smart-60a1df44-6264-4b12-a089-01e2ee8a99ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149108556 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.3149108556
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3742645866
Short name T1128
Test name
Test status
Simulation time 19010392 ps
CPU time 0.82 seconds
Started Jul 18 06:07:42 PM PDT 24
Finished Jul 18 06:07:48 PM PDT 24
Peak memory 206652 kb
Host smart-ce8c601c-c45c-461c-9918-797c7c598ce0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742645866 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3742645866
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1729022531
Short name T1104
Test name
Test status
Simulation time 127548180 ps
CPU time 1.44 seconds
Started Jul 18 06:07:40 PM PDT 24
Finished Jul 18 06:07:45 PM PDT 24
Peak memory 206892 kb
Host smart-1f4d9b10-3220-406b-8df7-b64a1b3b60cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729022531 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.1729022531
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.552686344
Short name T1050
Test name
Test status
Simulation time 372367338 ps
CPU time 3.25 seconds
Started Jul 18 06:07:39 PM PDT 24
Finished Jul 18 06:07:45 PM PDT 24
Peak memory 215168 kb
Host smart-eb0c9790-9581-4ff2-b70c-33410a77665b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552686344 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.552686344
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1808588554
Short name T1112
Test name
Test status
Simulation time 146898028 ps
CPU time 1.43 seconds
Started Jul 18 06:07:43 PM PDT 24
Finished Jul 18 06:07:50 PM PDT 24
Peak memory 215080 kb
Host smart-b2e7e663-296a-4af2-a009-585964154768
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808588554 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.1808588554
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1551091228
Short name T1015
Test name
Test status
Simulation time 33542614 ps
CPU time 1.4 seconds
Started Jul 18 06:07:43 PM PDT 24
Finished Jul 18 06:07:50 PM PDT 24
Peak memory 218484 kb
Host smart-26fe505d-2e23-41bc-a645-90775c9dafc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551091228 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1551091228
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1505606594
Short name T256
Test name
Test status
Simulation time 13413329 ps
CPU time 0.92 seconds
Started Jul 18 06:07:39 PM PDT 24
Finished Jul 18 06:07:43 PM PDT 24
Peak memory 206824 kb
Host smart-2dc59edb-f14e-4027-a5d6-a5bde6a86372
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505606594 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1505606594
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.2884009733
Short name T1105
Test name
Test status
Simulation time 27363783 ps
CPU time 0.91 seconds
Started Jul 18 06:07:43 PM PDT 24
Finished Jul 18 06:07:50 PM PDT 24
Peak memory 206828 kb
Host smart-79958e3f-6a5d-4db2-a8b0-8be54e9ec974
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884009733 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.2884009733
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.39802148
Short name T270
Test name
Test status
Simulation time 118635904 ps
CPU time 1.32 seconds
Started Jul 18 06:07:41 PM PDT 24
Finished Jul 18 06:07:48 PM PDT 24
Peak memory 206908 kb
Host smart-faf75df1-621e-4fe8-9033-dbce5e3c2575
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39802148 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_outs
tanding.39802148
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.3372196380
Short name T1107
Test name
Test status
Simulation time 79584433 ps
CPU time 1.99 seconds
Started Jul 18 06:07:40 PM PDT 24
Finished Jul 18 06:07:48 PM PDT 24
Peak memory 215164 kb
Host smart-bf3f14c1-dba7-4c38-92db-833c1a7e1ca3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372196380 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.3372196380
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.901818753
Short name T280
Test name
Test status
Simulation time 321273755 ps
CPU time 2.41 seconds
Started Jul 18 06:07:43 PM PDT 24
Finished Jul 18 06:07:51 PM PDT 24
Peak memory 206984 kb
Host smart-bebfaff5-66a7-4361-8cdb-cf93af181f98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901818753 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.901818753
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2394572165
Short name T1039
Test name
Test status
Simulation time 33088213 ps
CPU time 1.18 seconds
Started Jul 18 06:07:42 PM PDT 24
Finished Jul 18 06:07:49 PM PDT 24
Peak memory 215204 kb
Host smart-381edf64-b0ec-4ad3-865d-98aab1bdabea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394572165 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.2394572165
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.262534811
Short name T261
Test name
Test status
Simulation time 17153736 ps
CPU time 0.88 seconds
Started Jul 18 06:07:42 PM PDT 24
Finished Jul 18 06:07:48 PM PDT 24
Peak memory 206808 kb
Host smart-2b3abff9-ff72-48b1-aa81-c221a7737c6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262534811 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.262534811
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.3927955488
Short name T1083
Test name
Test status
Simulation time 27460163 ps
CPU time 0.93 seconds
Started Jul 18 06:07:43 PM PDT 24
Finished Jul 18 06:07:50 PM PDT 24
Peak memory 206820 kb
Host smart-834f45ca-5315-4f6e-97a0-bedd54577e68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927955488 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.3927955488
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2842901060
Short name T1077
Test name
Test status
Simulation time 38359867 ps
CPU time 1.05 seconds
Started Jul 18 06:07:40 PM PDT 24
Finished Jul 18 06:07:47 PM PDT 24
Peak memory 206868 kb
Host smart-22eaf353-c495-4fbd-bd1c-93c8a2fee7df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842901060 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.2842901060
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.3796814587
Short name T1012
Test name
Test status
Simulation time 72894800 ps
CPU time 2.82 seconds
Started Jul 18 06:07:41 PM PDT 24
Finished Jul 18 06:07:50 PM PDT 24
Peak memory 215404 kb
Host smart-91a2fa5e-83ef-45e2-84df-de28b713403e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796814587 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.3796814587
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2503257081
Short name T1022
Test name
Test status
Simulation time 164452629 ps
CPU time 1.62 seconds
Started Jul 18 06:07:43 PM PDT 24
Finished Jul 18 06:07:50 PM PDT 24
Peak memory 206956 kb
Host smart-d88cbbb7-4cfa-49e4-aa98-981f8dbb5a2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503257081 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2503257081
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.432593913
Short name T1001
Test name
Test status
Simulation time 22834770 ps
CPU time 1.13 seconds
Started Jul 18 06:07:53 PM PDT 24
Finished Jul 18 06:07:57 PM PDT 24
Peak memory 215076 kb
Host smart-404d5bef-c205-4114-90d6-bab6a0e8e4cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432593913 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.432593913
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2328945440
Short name T1098
Test name
Test status
Simulation time 14460360 ps
CPU time 0.93 seconds
Started Jul 18 06:07:55 PM PDT 24
Finished Jul 18 06:07:58 PM PDT 24
Peak memory 206820 kb
Host smart-c2e936cf-28ce-4e8c-ad18-4e563dcfe594
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328945440 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2328945440
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2026582206
Short name T1032
Test name
Test status
Simulation time 22094503 ps
CPU time 0.86 seconds
Started Jul 18 06:07:56 PM PDT 24
Finished Jul 18 06:08:02 PM PDT 24
Peak memory 206840 kb
Host smart-54507deb-e473-4536-9ac2-f5b672caa3ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026582206 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2026582206
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2474134881
Short name T1110
Test name
Test status
Simulation time 17529283 ps
CPU time 1.22 seconds
Started Jul 18 06:07:52 PM PDT 24
Finished Jul 18 06:07:55 PM PDT 24
Peak memory 206916 kb
Host smart-481479c1-172a-426f-9fd8-3b1f4b494315
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474134881 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.2474134881
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.2192986874
Short name T1034
Test name
Test status
Simulation time 540833565 ps
CPU time 4.5 seconds
Started Jul 18 06:07:52 PM PDT 24
Finished Jul 18 06:07:59 PM PDT 24
Peak memory 215208 kb
Host smart-5652a1ad-4b79-42dc-b485-925db729321f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192986874 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.2192986874
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2198009859
Short name T275
Test name
Test status
Simulation time 185092603 ps
CPU time 1.55 seconds
Started Jul 18 06:07:57 PM PDT 24
Finished Jul 18 06:08:03 PM PDT 24
Peak memory 206956 kb
Host smart-621de2a5-0019-4bda-8865-a314af108715
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198009859 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.2198009859
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.434040
Short name T775
Test name
Test status
Simulation time 23678751 ps
CPU time 1.2 seconds
Started Jul 18 07:21:16 PM PDT 24
Finished Jul 18 07:21:23 PM PDT 24
Peak memory 221044 kb
Host smart-a1a0e17f-34b8-4dd1-ae40-fc1c4358a041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434040 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.434040
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.68953569
Short name T570
Test name
Test status
Simulation time 15210499 ps
CPU time 0.95 seconds
Started Jul 18 07:21:18 PM PDT 24
Finished Jul 18 07:21:24 PM PDT 24
Peak memory 207048 kb
Host smart-76f4112d-4e90-498c-b3c3-952f48832bfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68953569 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.68953569
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.2847529095
Short name T607
Test name
Test status
Simulation time 209576177 ps
CPU time 1.16 seconds
Started Jul 18 07:21:20 PM PDT 24
Finished Jul 18 07:21:27 PM PDT 24
Peak memory 217304 kb
Host smart-aa10bb2a-91fc-40e1-90ca-e44223ffda19
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847529095 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.2847529095
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.3802919644
Short name T629
Test name
Test status
Simulation time 38730543 ps
CPU time 0.91 seconds
Started Jul 18 07:21:21 PM PDT 24
Finished Jul 18 07:21:27 PM PDT 24
Peak memory 218780 kb
Host smart-b1f77285-95ab-406e-bdf1-de296385054d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802919644 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.3802919644
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.1463467299
Short name T952
Test name
Test status
Simulation time 33910578 ps
CPU time 1.24 seconds
Started Jul 18 07:21:04 PM PDT 24
Finished Jul 18 07:21:10 PM PDT 24
Peak memory 218808 kb
Host smart-062c8d75-13ec-41ef-af9c-aece748669f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463467299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.1463467299
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.1119426786
Short name T796
Test name
Test status
Simulation time 36598944 ps
CPU time 0.89 seconds
Started Jul 18 07:21:15 PM PDT 24
Finished Jul 18 07:21:20 PM PDT 24
Peak memory 215576 kb
Host smart-38e08fbd-577a-44ee-b38d-bfab0adccff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119426786 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1119426786
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.6898215
Short name T545
Test name
Test status
Simulation time 37223174 ps
CPU time 0.89 seconds
Started Jul 18 07:21:02 PM PDT 24
Finished Jul 18 07:21:07 PM PDT 24
Peak memory 207388 kb
Host smart-c65a61e6-e3c4-4402-8638-d9941c7171bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6898215 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.6898215
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.4172834103
Short name T16
Test name
Test status
Simulation time 384723164 ps
CPU time 4.65 seconds
Started Jul 18 07:21:17 PM PDT 24
Finished Jul 18 07:21:27 PM PDT 24
Peak memory 235748 kb
Host smart-fa5bcbba-5019-4e08-a711-107d5c8626b4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172834103 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.4172834103
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.2315737961
Short name T344
Test name
Test status
Simulation time 23575917 ps
CPU time 0.94 seconds
Started Jul 18 07:21:02 PM PDT 24
Finished Jul 18 07:21:07 PM PDT 24
Peak memory 215596 kb
Host smart-a71e19f4-6f87-41d2-ac3b-723c3e5f54ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315737961 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2315737961
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.3626120487
Short name T677
Test name
Test status
Simulation time 247366692 ps
CPU time 4.11 seconds
Started Jul 18 07:21:04 PM PDT 24
Finished Jul 18 07:21:12 PM PDT 24
Peak memory 215540 kb
Host smart-777e68a3-ca33-4a0a-8d1e-7d0832e9f69e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626120487 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.3626120487
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2586883243
Short name T227
Test name
Test status
Simulation time 300568636704 ps
CPU time 429.25 seconds
Started Jul 18 07:21:01 PM PDT 24
Finished Jul 18 07:28:14 PM PDT 24
Peak memory 219292 kb
Host smart-2ecca099-bafc-43f7-8d43-fbee2e5ce8bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586883243 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2586883243
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.1467708617
Short name T404
Test name
Test status
Simulation time 48801892 ps
CPU time 1.29 seconds
Started Jul 18 07:21:20 PM PDT 24
Finished Jul 18 07:21:27 PM PDT 24
Peak memory 218928 kb
Host smart-67fb2a45-10ff-44ee-b71f-d9f7c6ad5e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467708617 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1467708617
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.1510900342
Short name T521
Test name
Test status
Simulation time 26087554 ps
CPU time 0.92 seconds
Started Jul 18 07:21:28 PM PDT 24
Finished Jul 18 07:21:33 PM PDT 24
Peak memory 207184 kb
Host smart-41adaaa2-d611-4268-9fff-c5daba047fc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510900342 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1510900342
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.561738111
Short name T932
Test name
Test status
Simulation time 12991015 ps
CPU time 0.91 seconds
Started Jul 18 07:21:28 PM PDT 24
Finished Jul 18 07:21:33 PM PDT 24
Peak memory 215828 kb
Host smart-a70e5eab-7342-4817-b2d1-d49cb7807af4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561738111 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.561738111
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.1277720285
Short name T85
Test name
Test status
Simulation time 46321059 ps
CPU time 1.48 seconds
Started Jul 18 07:21:28 PM PDT 24
Finished Jul 18 07:21:33 PM PDT 24
Peak memory 217264 kb
Host smart-fc339dd1-420e-474b-b9e1-ffb5869aee45
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277720285 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.1277720285
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.2676478306
Short name T156
Test name
Test status
Simulation time 20172832 ps
CPU time 1.07 seconds
Started Jul 18 07:21:16 PM PDT 24
Finished Jul 18 07:21:23 PM PDT 24
Peak memory 218708 kb
Host smart-9395ffa1-a711-476a-a826-d5c9ea09e14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676478306 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.2676478306
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.617654364
Short name T371
Test name
Test status
Simulation time 87715592 ps
CPU time 1.21 seconds
Started Jul 18 07:21:15 PM PDT 24
Finished Jul 18 07:21:21 PM PDT 24
Peak memory 220204 kb
Host smart-0734549a-107e-4f61-9402-31bb16a644c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617654364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.617654364
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_regwen.482051303
Short name T457
Test name
Test status
Simulation time 15000075 ps
CPU time 1.08 seconds
Started Jul 18 07:21:15 PM PDT 24
Finished Jul 18 07:21:20 PM PDT 24
Peak memory 207376 kb
Host smart-41418e1b-0716-4b04-aaaf-1f6e1488dae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482051303 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.482051303
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.3881365370
Short name T62
Test name
Test status
Simulation time 253599456 ps
CPU time 4.45 seconds
Started Jul 18 07:21:36 PM PDT 24
Finished Jul 18 07:21:44 PM PDT 24
Peak memory 236520 kb
Host smart-0094f770-398f-4a11-9844-27bf66b76f01
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881365370 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.3881365370
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/10.edn_alert.2407508098
Short name T856
Test name
Test status
Simulation time 42708210 ps
CPU time 1.19 seconds
Started Jul 18 07:22:32 PM PDT 24
Finished Jul 18 07:22:37 PM PDT 24
Peak memory 220152 kb
Host smart-95fa4fb9-f9f7-49b9-9f63-8febea113442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407508098 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.2407508098
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.3157382103
Short name T761
Test name
Test status
Simulation time 99263858 ps
CPU time 1.14 seconds
Started Jul 18 07:22:31 PM PDT 24
Finished Jul 18 07:22:35 PM PDT 24
Peak memory 217044 kb
Host smart-0526b885-db8e-4bdb-bb07-be290a0bbfde
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157382103 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.3157382103
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.89851785
Short name T406
Test name
Test status
Simulation time 19154945 ps
CPU time 1.07 seconds
Started Jul 18 07:22:32 PM PDT 24
Finished Jul 18 07:22:36 PM PDT 24
Peak memory 218860 kb
Host smart-988dffbb-e3c1-49f6-a9d9-778763212773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89851785 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.89851785
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.4151872552
Short name T563
Test name
Test status
Simulation time 71258586 ps
CPU time 1.44 seconds
Started Jul 18 07:22:32 PM PDT 24
Finished Jul 18 07:22:36 PM PDT 24
Peak memory 220264 kb
Host smart-3b51bc75-85ff-4fe3-ae08-2b9e5353a8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151872552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.4151872552
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_smoke.1592938236
Short name T719
Test name
Test status
Simulation time 76528641 ps
CPU time 0.9 seconds
Started Jul 18 07:22:32 PM PDT 24
Finished Jul 18 07:22:37 PM PDT 24
Peak memory 215548 kb
Host smart-4a96538c-6633-4cf7-8a6a-8b3bf5e3adeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592938236 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1592938236
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.147716699
Short name T405
Test name
Test status
Simulation time 110865194291 ps
CPU time 1346.13 seconds
Started Jul 18 07:22:30 PM PDT 24
Finished Jul 18 07:44:59 PM PDT 24
Peak memory 224284 kb
Host smart-d883d2f0-d7f8-4609-8643-7127c252c83b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147716699 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.147716699
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.255251231
Short name T466
Test name
Test status
Simulation time 91833355 ps
CPU time 1.17 seconds
Started Jul 18 07:25:47 PM PDT 24
Finished Jul 18 07:25:51 PM PDT 24
Peak memory 219688 kb
Host smart-29f1d0ac-3efa-4927-a6f4-473c383bbe60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255251231 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.255251231
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.2857364815
Short name T87
Test name
Test status
Simulation time 31707063 ps
CPU time 1.35 seconds
Started Jul 18 07:25:48 PM PDT 24
Finished Jul 18 07:25:53 PM PDT 24
Peak memory 218884 kb
Host smart-7d96f13f-c91c-4b54-8c10-8831921e2594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857364815 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2857364815
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.78771734
Short name T897
Test name
Test status
Simulation time 61406762 ps
CPU time 2.12 seconds
Started Jul 18 07:25:45 PM PDT 24
Finished Jul 18 07:25:49 PM PDT 24
Peak memory 220328 kb
Host smart-747e8bb0-eb57-4602-b04d-497ead2529b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78771734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.78771734
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.725305296
Short name T149
Test name
Test status
Simulation time 46809912 ps
CPU time 1.28 seconds
Started Jul 18 07:25:48 PM PDT 24
Finished Jul 18 07:25:53 PM PDT 24
Peak memory 218840 kb
Host smart-f7132554-ebf2-4ced-b5fb-6bb17cf41f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725305296 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.725305296
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.979980125
Short name T564
Test name
Test status
Simulation time 89746494 ps
CPU time 1.2 seconds
Started Jul 18 07:25:55 PM PDT 24
Finished Jul 18 07:25:57 PM PDT 24
Peak memory 219300 kb
Host smart-b1c8a2d1-5925-4c94-8441-5a25007b5124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979980125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.979980125
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.4217924778
Short name T494
Test name
Test status
Simulation time 94289828 ps
CPU time 2.14 seconds
Started Jul 18 07:25:48 PM PDT 24
Finished Jul 18 07:25:53 PM PDT 24
Peak memory 218908 kb
Host smart-b07a5618-2e01-4610-95a0-aa81be27cd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217924778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.4217924778
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.642370563
Short name T77
Test name
Test status
Simulation time 71755988 ps
CPU time 1.17 seconds
Started Jul 18 07:25:48 PM PDT 24
Finished Jul 18 07:25:52 PM PDT 24
Peak memory 220220 kb
Host smart-8ed4e865-2806-4d53-af51-aa06be87dca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642370563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.642370563
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.4265359990
Short name T573
Test name
Test status
Simulation time 25403392 ps
CPU time 1.28 seconds
Started Jul 18 07:25:47 PM PDT 24
Finished Jul 18 07:25:50 PM PDT 24
Peak memory 219004 kb
Host smart-bc04dad8-4f66-454c-a506-717d3b954467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265359990 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.4265359990
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.1831876169
Short name T708
Test name
Test status
Simulation time 100126516 ps
CPU time 1.31 seconds
Started Jul 18 07:25:46 PM PDT 24
Finished Jul 18 07:25:50 PM PDT 24
Peak memory 217632 kb
Host smart-04258ebf-be40-4060-af6b-5e86915a6ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831876169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1831876169
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.2875610336
Short name T977
Test name
Test status
Simulation time 82342394 ps
CPU time 1.32 seconds
Started Jul 18 07:25:46 PM PDT 24
Finished Jul 18 07:25:49 PM PDT 24
Peak memory 220532 kb
Host smart-e9021e14-ee30-4879-ba47-617a971191f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875610336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.2875610336
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.1236680795
Short name T68
Test name
Test status
Simulation time 25767287 ps
CPU time 1.22 seconds
Started Jul 18 07:25:46 PM PDT 24
Finished Jul 18 07:25:49 PM PDT 24
Peak memory 218988 kb
Host smart-27a3848e-2f5b-4e75-b9bf-03d06d4121df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236680795 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.1236680795
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.1061586344
Short name T939
Test name
Test status
Simulation time 53290191 ps
CPU time 1.19 seconds
Started Jul 18 07:25:45 PM PDT 24
Finished Jul 18 07:25:48 PM PDT 24
Peak memory 217632 kb
Host smart-595f33c9-552f-431e-80b1-157dc4577ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061586344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.1061586344
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.1565755689
Short name T984
Test name
Test status
Simulation time 29782171 ps
CPU time 1.21 seconds
Started Jul 18 07:25:48 PM PDT 24
Finished Jul 18 07:25:53 PM PDT 24
Peak memory 220076 kb
Host smart-bc62196d-cbe6-472f-a8bd-01879589d8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565755689 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.1565755689
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.1378109719
Short name T364
Test name
Test status
Simulation time 254986745 ps
CPU time 1.28 seconds
Started Jul 18 07:25:46 PM PDT 24
Finished Jul 18 07:25:49 PM PDT 24
Peak memory 217556 kb
Host smart-92a3b07f-5bc8-48b7-9737-4ff1663b8a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378109719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.1378109719
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.3080270749
Short name T844
Test name
Test status
Simulation time 86163529 ps
CPU time 1.23 seconds
Started Jul 18 07:25:48 PM PDT 24
Finished Jul 18 07:25:53 PM PDT 24
Peak memory 221648 kb
Host smart-681c34f5-17e2-447a-b255-3663cc95a2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080270749 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.3080270749
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.1324386977
Short name T441
Test name
Test status
Simulation time 88371054 ps
CPU time 1.48 seconds
Started Jul 18 07:25:47 PM PDT 24
Finished Jul 18 07:25:51 PM PDT 24
Peak memory 220388 kb
Host smart-d344b882-5a81-45ab-8a84-c1a0c9764f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324386977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.1324386977
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.2028972934
Short name T674
Test name
Test status
Simulation time 17950579 ps
CPU time 0.97 seconds
Started Jul 18 07:22:29 PM PDT 24
Finished Jul 18 07:22:31 PM PDT 24
Peak memory 215500 kb
Host smart-5bb01bb8-2428-48e3-ade7-b29342b7c0a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028972934 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.2028972934
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.3950103315
Short name T164
Test name
Test status
Simulation time 21656748 ps
CPU time 0.86 seconds
Started Jul 18 07:22:31 PM PDT 24
Finished Jul 18 07:22:34 PM PDT 24
Peak memory 216676 kb
Host smart-33b00d56-7989-4b3b-8940-02d40fbfff6e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950103315 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3950103315
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_err.1334369611
Short name T7
Test name
Test status
Simulation time 19947622 ps
CPU time 1.07 seconds
Started Jul 18 07:22:34 PM PDT 24
Finished Jul 18 07:22:37 PM PDT 24
Peak memory 218872 kb
Host smart-4a622fb5-2a8f-4339-9721-05927e617daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334369611 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.1334369611
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.1408931894
Short name T237
Test name
Test status
Simulation time 2489469453 ps
CPU time 79.28 seconds
Started Jul 18 07:22:28 PM PDT 24
Finished Jul 18 07:23:49 PM PDT 24
Peak memory 220176 kb
Host smart-32049dbd-2277-4212-8bd8-d0ec8e8d3d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408931894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1408931894
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.2069559954
Short name T96
Test name
Test status
Simulation time 21222863 ps
CPU time 1.08 seconds
Started Jul 18 07:22:37 PM PDT 24
Finished Jul 18 07:22:39 PM PDT 24
Peak memory 216148 kb
Host smart-d317113e-04c0-4088-a346-7add1a053bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069559954 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.2069559954
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.2827996205
Short name T65
Test name
Test status
Simulation time 46151113 ps
CPU time 0.91 seconds
Started Jul 18 07:22:29 PM PDT 24
Finished Jul 18 07:22:31 PM PDT 24
Peak memory 215540 kb
Host smart-30611d2b-c977-44c5-994e-85e1bd37db4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827996205 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.2827996205
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.1117756982
Short name T740
Test name
Test status
Simulation time 756382141 ps
CPU time 4.75 seconds
Started Jul 18 07:22:32 PM PDT 24
Finished Jul 18 07:22:39 PM PDT 24
Peak memory 217660 kb
Host smart-3c7b5810-2dfe-4521-b0c8-09e9fdac3bcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117756982 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1117756982
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.3981501984
Short name T455
Test name
Test status
Simulation time 94664627716 ps
CPU time 1063.97 seconds
Started Jul 18 07:22:29 PM PDT 24
Finished Jul 18 07:40:14 PM PDT 24
Peak memory 223304 kb
Host smart-4323e7d7-1704-484e-a97f-5f1814901d52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981501984 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.3981501984
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.1257447111
Short name T804
Test name
Test status
Simulation time 30081042 ps
CPU time 1.35 seconds
Started Jul 18 07:25:48 PM PDT 24
Finished Jul 18 07:25:52 PM PDT 24
Peak memory 220064 kb
Host smart-ae84528a-9881-47f7-9b63-8a0614613048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257447111 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.1257447111
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/111.edn_alert.322178958
Short name T402
Test name
Test status
Simulation time 31131050 ps
CPU time 1.38 seconds
Started Jul 18 07:25:46 PM PDT 24
Finished Jul 18 07:25:50 PM PDT 24
Peak memory 216040 kb
Host smart-8872d216-c471-4c84-b070-b613814faddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322178958 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.322178958
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.757954179
Short name T328
Test name
Test status
Simulation time 82460491 ps
CPU time 3.07 seconds
Started Jul 18 07:25:48 PM PDT 24
Finished Jul 18 07:25:55 PM PDT 24
Peak memory 218880 kb
Host smart-2116511c-3d79-4510-ad60-a266f6455b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757954179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.757954179
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.4149307360
Short name T449
Test name
Test status
Simulation time 46207644 ps
CPU time 1.13 seconds
Started Jul 18 07:25:51 PM PDT 24
Finished Jul 18 07:25:54 PM PDT 24
Peak memory 218692 kb
Host smart-b6d9fb7c-6714-4867-9782-68dccd5926a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149307360 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.4149307360
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.2709978166
Short name T396
Test name
Test status
Simulation time 96211511 ps
CPU time 1.6 seconds
Started Jul 18 07:25:47 PM PDT 24
Finished Jul 18 07:25:52 PM PDT 24
Peak memory 219028 kb
Host smart-b074e551-3175-40dc-8e95-7fb880c05304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709978166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.2709978166
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.3476771930
Short name T609
Test name
Test status
Simulation time 29469349 ps
CPU time 1.19 seconds
Started Jul 18 07:25:48 PM PDT 24
Finished Jul 18 07:25:52 PM PDT 24
Peak memory 220336 kb
Host smart-8e2b029f-af6c-40d2-bcb3-0d77fc8d27e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476771930 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.3476771930
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.4174499612
Short name T311
Test name
Test status
Simulation time 36417127 ps
CPU time 1.35 seconds
Started Jul 18 07:25:48 PM PDT 24
Finished Jul 18 07:25:53 PM PDT 24
Peak memory 220140 kb
Host smart-f2627a6c-df0c-4dd9-b6ea-d19f1d226140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174499612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.4174499612
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.4087938060
Short name T930
Test name
Test status
Simulation time 23650248 ps
CPU time 1.2 seconds
Started Jul 18 07:25:58 PM PDT 24
Finished Jul 18 07:26:01 PM PDT 24
Peak memory 220052 kb
Host smart-33ba6cdb-bf0c-4237-9ef4-65cdc0775144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087938060 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.4087938060
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.3160664321
Short name T41
Test name
Test status
Simulation time 108147234 ps
CPU time 1.22 seconds
Started Jul 18 07:26:00 PM PDT 24
Finished Jul 18 07:26:05 PM PDT 24
Peak memory 215552 kb
Host smart-1c6aac0e-9a9f-4c3e-8f8e-dd6452eb56c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160664321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3160664321
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.650976773
Short name T461
Test name
Test status
Simulation time 39194977 ps
CPU time 1.25 seconds
Started Jul 18 07:26:00 PM PDT 24
Finished Jul 18 07:26:04 PM PDT 24
Peak memory 221204 kb
Host smart-f6870948-76e2-45de-829d-91f56449cbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650976773 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.650976773
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.863510346
Short name T372
Test name
Test status
Simulation time 65566961 ps
CPU time 1.22 seconds
Started Jul 18 07:25:58 PM PDT 24
Finished Jul 18 07:26:01 PM PDT 24
Peak memory 218948 kb
Host smart-767ae16e-d2a5-4c09-b104-c63ba0cfffa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863510346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.863510346
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.1854555433
Short name T701
Test name
Test status
Simulation time 85836248 ps
CPU time 1.22 seconds
Started Jul 18 07:25:56 PM PDT 24
Finished Jul 18 07:25:59 PM PDT 24
Peak memory 218780 kb
Host smart-846282ad-7ddc-467f-9762-baa2256c33b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854555433 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.1854555433
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.1084260805
Short name T825
Test name
Test status
Simulation time 42642092 ps
CPU time 1.84 seconds
Started Jul 18 07:26:01 PM PDT 24
Finished Jul 18 07:26:07 PM PDT 24
Peak memory 218832 kb
Host smart-3b93d884-47e5-4b6e-b378-9d0128010e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084260805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1084260805
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.1778281110
Short name T244
Test name
Test status
Simulation time 31035001 ps
CPU time 1.36 seconds
Started Jul 18 07:26:00 PM PDT 24
Finished Jul 18 07:26:05 PM PDT 24
Peak memory 220708 kb
Host smart-9c19d653-6349-427b-9090-97097bf5f649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778281110 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.1778281110
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.277641482
Short name T568
Test name
Test status
Simulation time 43260072 ps
CPU time 1.6 seconds
Started Jul 18 07:26:00 PM PDT 24
Finished Jul 18 07:26:05 PM PDT 24
Peak memory 217608 kb
Host smart-abfdbfae-5744-439a-9211-291c84fcc064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277641482 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.277641482
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.3678220459
Short name T693
Test name
Test status
Simulation time 104057702 ps
CPU time 1.2 seconds
Started Jul 18 07:25:59 PM PDT 24
Finished Jul 18 07:26:03 PM PDT 24
Peak memory 218972 kb
Host smart-5ef02795-7894-4d03-97b3-72dda15644a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678220459 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.3678220459
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.3374538629
Short name T987
Test name
Test status
Simulation time 130475007 ps
CPU time 1.4 seconds
Started Jul 18 07:25:57 PM PDT 24
Finished Jul 18 07:26:00 PM PDT 24
Peak memory 217720 kb
Host smart-e4b3f3b2-d50d-489b-b1a2-1b75a364f6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374538629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3374538629
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.3874896549
Short name T271
Test name
Test status
Simulation time 83225920 ps
CPU time 1.22 seconds
Started Jul 18 07:25:58 PM PDT 24
Finished Jul 18 07:26:00 PM PDT 24
Peak memory 220092 kb
Host smart-bd692530-bb70-46ba-8923-642d191f4054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874896549 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.3874896549
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.3347900140
Short name T369
Test name
Test status
Simulation time 68667373 ps
CPU time 1.17 seconds
Started Jul 18 07:26:00 PM PDT 24
Finished Jul 18 07:26:04 PM PDT 24
Peak memory 219076 kb
Host smart-726a93d8-723d-4f6e-ace8-68baf8a393fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347900140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3347900140
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.4279797178
Short name T412
Test name
Test status
Simulation time 27868133 ps
CPU time 1.23 seconds
Started Jul 18 07:22:36 PM PDT 24
Finished Jul 18 07:22:39 PM PDT 24
Peak memory 219860 kb
Host smart-88860529-5e5f-4b53-815a-8c5d6d669325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279797178 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.4279797178
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.2933680333
Short name T332
Test name
Test status
Simulation time 167729157 ps
CPU time 0.85 seconds
Started Jul 18 07:22:32 PM PDT 24
Finished Jul 18 07:22:36 PM PDT 24
Peak memory 206844 kb
Host smart-185e0e93-8897-4560-aa0d-6d53e77c4225
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933680333 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2933680333
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.3873020208
Short name T180
Test name
Test status
Simulation time 30759422 ps
CPU time 0.85 seconds
Started Jul 18 07:22:32 PM PDT 24
Finished Jul 18 07:22:36 PM PDT 24
Peak memory 216588 kb
Host smart-a359e77f-e75b-4425-9a92-28ff5ade82ad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873020208 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.3873020208
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.1210131642
Short name T420
Test name
Test status
Simulation time 98237879 ps
CPU time 1.22 seconds
Started Jul 18 07:22:31 PM PDT 24
Finished Jul 18 07:22:35 PM PDT 24
Peak memory 217116 kb
Host smart-3711c782-592b-4c03-a81e-405f079fd0fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210131642 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.1210131642
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.115999011
Short name T123
Test name
Test status
Simulation time 21733901 ps
CPU time 1.22 seconds
Started Jul 18 07:22:31 PM PDT 24
Finished Jul 18 07:22:35 PM PDT 24
Peak memory 229952 kb
Host smart-bc8a98da-5b6c-4273-a17e-f3b8d9b08a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115999011 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.115999011
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.3664080990
Short name T324
Test name
Test status
Simulation time 51459685 ps
CPU time 1.54 seconds
Started Jul 18 07:22:30 PM PDT 24
Finished Jul 18 07:22:34 PM PDT 24
Peak memory 219056 kb
Host smart-82cff2cc-b61d-4ede-97b5-a2d805b6478d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664080990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.3664080990
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.1775632813
Short name T610
Test name
Test status
Simulation time 27569576 ps
CPU time 0.92 seconds
Started Jul 18 07:22:36 PM PDT 24
Finished Jul 18 07:22:38 PM PDT 24
Peak memory 216076 kb
Host smart-b3625b24-fdae-4ec2-9df2-fc144be43ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775632813 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.1775632813
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.195945455
Short name T437
Test name
Test status
Simulation time 17587808 ps
CPU time 1 seconds
Started Jul 18 07:22:29 PM PDT 24
Finished Jul 18 07:22:31 PM PDT 24
Peak memory 215584 kb
Host smart-b20bc3ff-5fa0-469a-aadd-906b00431d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195945455 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.195945455
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.3286215355
Short name T923
Test name
Test status
Simulation time 131120969585 ps
CPU time 786.95 seconds
Started Jul 18 07:22:30 PM PDT 24
Finished Jul 18 07:35:40 PM PDT 24
Peak memory 224052 kb
Host smart-dc73ca6b-3331-4e45-9391-163047371c36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286215355 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.3286215355
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.2312755733
Short name T42
Test name
Test status
Simulation time 63086539 ps
CPU time 1.14 seconds
Started Jul 18 07:26:00 PM PDT 24
Finished Jul 18 07:26:05 PM PDT 24
Peak memory 220124 kb
Host smart-fb4f0844-00d6-43d5-a630-3080e865c52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312755733 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.2312755733
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.2867738826
Short name T398
Test name
Test status
Simulation time 69303933 ps
CPU time 1.08 seconds
Started Jul 18 07:26:01 PM PDT 24
Finished Jul 18 07:26:06 PM PDT 24
Peak memory 217724 kb
Host smart-3fe1f7db-483d-4050-a8cc-fcf77e9ff3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867738826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.2867738826
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.477895640
Short name T217
Test name
Test status
Simulation time 22308645 ps
CPU time 1.19 seconds
Started Jul 18 07:25:57 PM PDT 24
Finished Jul 18 07:26:00 PM PDT 24
Peak memory 221164 kb
Host smart-7356be54-c451-4f65-9cd3-3d411c6f15bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477895640 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.477895640
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.591139597
Short name T555
Test name
Test status
Simulation time 49780978 ps
CPU time 1.75 seconds
Started Jul 18 07:26:00 PM PDT 24
Finished Jul 18 07:26:05 PM PDT 24
Peak memory 218696 kb
Host smart-faea32c6-4a08-4f92-843a-9def7eef94a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591139597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.591139597
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.617316066
Short name T215
Test name
Test status
Simulation time 21252233 ps
CPU time 1.2 seconds
Started Jul 18 07:26:03 PM PDT 24
Finished Jul 18 07:26:08 PM PDT 24
Peak memory 219172 kb
Host smart-422fbf85-f81b-447e-a4fa-5508944c2331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617316066 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.617316066
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.4223141166
Short name T648
Test name
Test status
Simulation time 53236357 ps
CPU time 1.27 seconds
Started Jul 18 07:25:58 PM PDT 24
Finished Jul 18 07:26:01 PM PDT 24
Peak memory 217444 kb
Host smart-52a40680-bc19-42fa-97a9-a011da114263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223141166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.4223141166
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.908073604
Short name T831
Test name
Test status
Simulation time 75864190 ps
CPU time 1.14 seconds
Started Jul 18 07:25:59 PM PDT 24
Finished Jul 18 07:26:04 PM PDT 24
Peak memory 219192 kb
Host smart-8b782767-5abf-4ff1-af21-8ab33374310e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908073604 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.908073604
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.462159725
Short name T905
Test name
Test status
Simulation time 51138733 ps
CPU time 1.15 seconds
Started Jul 18 07:25:58 PM PDT 24
Finished Jul 18 07:26:00 PM PDT 24
Peak memory 217548 kb
Host smart-87709c61-537e-48f9-8b61-5b4c4ebbc1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462159725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.462159725
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.731598634
Short name T700
Test name
Test status
Simulation time 33196108 ps
CPU time 1.25 seconds
Started Jul 18 07:26:01 PM PDT 24
Finished Jul 18 07:26:06 PM PDT 24
Peak memory 220264 kb
Host smart-bdcbd634-039c-4c53-a9f5-77c579875ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731598634 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.731598634
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.1483498411
Short name T989
Test name
Test status
Simulation time 173279370 ps
CPU time 1.3 seconds
Started Jul 18 07:25:59 PM PDT 24
Finished Jul 18 07:26:02 PM PDT 24
Peak memory 217568 kb
Host smart-c36174ee-9584-4629-9d1c-695afeac9269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483498411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1483498411
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.4085803863
Short name T184
Test name
Test status
Simulation time 94513323 ps
CPU time 1.28 seconds
Started Jul 18 07:26:00 PM PDT 24
Finished Jul 18 07:26:05 PM PDT 24
Peak memory 216008 kb
Host smart-44b7374f-8472-4177-9020-9b43e17c3750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085803863 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.4085803863
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.1349557972
Short name T477
Test name
Test status
Simulation time 76559786 ps
CPU time 2.65 seconds
Started Jul 18 07:26:01 PM PDT 24
Finished Jul 18 07:26:07 PM PDT 24
Peak memory 220520 kb
Host smart-fb97e3a8-bad1-4e37-a529-ef562b18103a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349557972 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.1349557972
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.4288227240
Short name T906
Test name
Test status
Simulation time 80076973 ps
CPU time 1.23 seconds
Started Jul 18 07:26:00 PM PDT 24
Finished Jul 18 07:26:05 PM PDT 24
Peak memory 220168 kb
Host smart-5f1f88d4-ad71-4857-93ea-6262f07af4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288227240 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.4288227240
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.987572231
Short name T903
Test name
Test status
Simulation time 82913649 ps
CPU time 1.28 seconds
Started Jul 18 07:25:57 PM PDT 24
Finished Jul 18 07:25:59 PM PDT 24
Peak memory 219468 kb
Host smart-fa149f60-fb06-4cb3-84e1-463a23fb4050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987572231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.987572231
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.3087064345
Short name T59
Test name
Test status
Simulation time 46013733 ps
CPU time 1.46 seconds
Started Jul 18 07:26:01 PM PDT 24
Finished Jul 18 07:26:06 PM PDT 24
Peak memory 217420 kb
Host smart-f54d12dd-6b52-4ae7-84a6-9df542b6450b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087064345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.3087064345
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.4214376609
Short name T534
Test name
Test status
Simulation time 81139125 ps
CPU time 1.15 seconds
Started Jul 18 07:26:00 PM PDT 24
Finished Jul 18 07:26:04 PM PDT 24
Peak memory 219900 kb
Host smart-ef48c03d-e929-484f-9ed7-619108e1c392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214376609 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.4214376609
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.4283562283
Short name T44
Test name
Test status
Simulation time 82055956 ps
CPU time 1.26 seconds
Started Jul 18 07:25:59 PM PDT 24
Finished Jul 18 07:26:03 PM PDT 24
Peak memory 215556 kb
Host smart-1f801275-5ede-400a-9963-87e7add0fc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283562283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.4283562283
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.278517523
Short name T287
Test name
Test status
Simulation time 28738087 ps
CPU time 1.26 seconds
Started Jul 18 07:25:59 PM PDT 24
Finished Jul 18 07:26:03 PM PDT 24
Peak memory 219248 kb
Host smart-ed8d23c3-0e6b-4406-8142-6216bff9926e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278517523 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.278517523
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.3741511156
Short name T766
Test name
Test status
Simulation time 49858062 ps
CPU time 1.4 seconds
Started Jul 18 07:25:59 PM PDT 24
Finished Jul 18 07:26:03 PM PDT 24
Peak memory 218872 kb
Host smart-07a81425-4684-4e97-922d-19ab97c776b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741511156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.3741511156
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.2568035757
Short name T388
Test name
Test status
Simulation time 52829173 ps
CPU time 1.25 seconds
Started Jul 18 07:22:43 PM PDT 24
Finished Jul 18 07:22:46 PM PDT 24
Peak memory 220184 kb
Host smart-115fb58e-a550-4574-be1b-f68e3586817c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568035757 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.2568035757
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.915693618
Short name T560
Test name
Test status
Simulation time 26076257 ps
CPU time 0.92 seconds
Started Jul 18 07:22:46 PM PDT 24
Finished Jul 18 07:22:50 PM PDT 24
Peak memory 215208 kb
Host smart-d926c6cd-bbf3-449a-8a3d-e0196bfc1834
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915693618 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.915693618
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.3662607865
Short name T125
Test name
Test status
Simulation time 377264073 ps
CPU time 1.3 seconds
Started Jul 18 07:22:45 PM PDT 24
Finished Jul 18 07:22:49 PM PDT 24
Peak memory 217192 kb
Host smart-28506d44-f931-413f-a054-84f21aaa3b2e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662607865 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.3662607865
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.3067433500
Short name T891
Test name
Test status
Simulation time 26430549 ps
CPU time 1.04 seconds
Started Jul 18 07:22:43 PM PDT 24
Finished Jul 18 07:22:45 PM PDT 24
Peak memory 224300 kb
Host smart-f489ca5b-3bfd-4959-b582-4e00e7bd9e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067433500 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.3067433500
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.3979530247
Short name T325
Test name
Test status
Simulation time 65432773 ps
CPU time 2.45 seconds
Started Jul 18 07:22:29 PM PDT 24
Finished Jul 18 07:22:33 PM PDT 24
Peak memory 220444 kb
Host smart-d69485d2-1535-4aa9-ab83-2a4b073f280f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979530247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.3979530247
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.3748200863
Short name T363
Test name
Test status
Simulation time 37271894 ps
CPU time 0.92 seconds
Started Jul 18 07:22:32 PM PDT 24
Finished Jul 18 07:22:36 PM PDT 24
Peak memory 215732 kb
Host smart-2c7200bd-8d96-4a48-ba54-70a270b7f43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748200863 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.3748200863
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.675897252
Short name T739
Test name
Test status
Simulation time 51438676 ps
CPU time 0.97 seconds
Started Jul 18 07:22:29 PM PDT 24
Finished Jul 18 07:22:31 PM PDT 24
Peak memory 215576 kb
Host smart-276e4e30-f369-415c-9313-33a1a92d4cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675897252 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.675897252
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.1975148694
Short name T480
Test name
Test status
Simulation time 118453972 ps
CPU time 2.65 seconds
Started Jul 18 07:22:36 PM PDT 24
Finished Jul 18 07:22:40 PM PDT 24
Peak memory 217556 kb
Host smart-db5e7659-93fd-4c50-a9ae-8241dc4a9656
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975148694 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1975148694
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.3566747703
Short name T681
Test name
Test status
Simulation time 79338062371 ps
CPU time 1052.67 seconds
Started Jul 18 07:22:29 PM PDT 24
Finished Jul 18 07:40:03 PM PDT 24
Peak memory 223984 kb
Host smart-35dea8fe-b856-4a73-b43e-40a298155c2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566747703 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.3566747703
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.590780894
Short name T584
Test name
Test status
Simulation time 27068854 ps
CPU time 1.27 seconds
Started Jul 18 07:26:01 PM PDT 24
Finished Jul 18 07:26:07 PM PDT 24
Peak memory 218904 kb
Host smart-f5a26f01-1a5e-4a3e-be35-9c85e4d20d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590780894 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.590780894
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.3939519438
Short name T996
Test name
Test status
Simulation time 459911348 ps
CPU time 2.01 seconds
Started Jul 18 07:26:01 PM PDT 24
Finished Jul 18 07:26:07 PM PDT 24
Peak memory 219020 kb
Host smart-cec030ff-eb9f-45f6-a160-359bbb8f345d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939519438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.3939519438
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.235669078
Short name T579
Test name
Test status
Simulation time 42392979 ps
CPU time 1.49 seconds
Started Jul 18 07:25:58 PM PDT 24
Finished Jul 18 07:26:02 PM PDT 24
Peak memory 217708 kb
Host smart-56c43319-912c-4646-abef-f893eb52371e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235669078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.235669078
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.3625332136
Short name T908
Test name
Test status
Simulation time 36571673 ps
CPU time 1.2 seconds
Started Jul 18 07:25:59 PM PDT 24
Finished Jul 18 07:26:04 PM PDT 24
Peak memory 220080 kb
Host smart-c768a527-e5af-4106-9370-82d3ce4d1bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625332136 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.3625332136
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.3783462039
Short name T646
Test name
Test status
Simulation time 49168366 ps
CPU time 1.95 seconds
Started Jul 18 07:25:58 PM PDT 24
Finished Jul 18 07:26:03 PM PDT 24
Peak memory 220316 kb
Host smart-c9bef83a-4c90-4f56-b698-3d5063d3299f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783462039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.3783462039
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.1430663678
Short name T606
Test name
Test status
Simulation time 124024110 ps
CPU time 1.14 seconds
Started Jul 18 07:26:17 PM PDT 24
Finished Jul 18 07:26:22 PM PDT 24
Peak memory 219412 kb
Host smart-17726873-de7b-4088-b6c9-6bca42f0c0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430663678 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.1430663678
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.3338464329
Short name T473
Test name
Test status
Simulation time 202648393 ps
CPU time 1.07 seconds
Started Jul 18 07:25:59 PM PDT 24
Finished Jul 18 07:26:03 PM PDT 24
Peak memory 217676 kb
Host smart-caec2f3f-b2a0-412e-b6e3-6002b5fd6304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338464329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3338464329
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.2841313649
Short name T647
Test name
Test status
Simulation time 77090402 ps
CPU time 1.09 seconds
Started Jul 18 07:26:14 PM PDT 24
Finished Jul 18 07:26:17 PM PDT 24
Peak memory 219788 kb
Host smart-275fc9b9-5dc6-4b55-9828-9bbac478a578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841313649 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.2841313649
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.811825844
Short name T814
Test name
Test status
Simulation time 63087531 ps
CPU time 1.01 seconds
Started Jul 18 07:26:15 PM PDT 24
Finished Jul 18 07:26:17 PM PDT 24
Peak memory 217644 kb
Host smart-007b53f0-7fcc-4673-aed4-0fca80c3a2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811825844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.811825844
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.2352691249
Short name T873
Test name
Test status
Simulation time 93303553 ps
CPU time 1.2 seconds
Started Jul 18 07:26:16 PM PDT 24
Finished Jul 18 07:26:21 PM PDT 24
Peak memory 219728 kb
Host smart-396aeecc-3317-4052-ac65-c76b1e5f3f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352691249 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.2352691249
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.386228751
Short name T358
Test name
Test status
Simulation time 73600182 ps
CPU time 1.53 seconds
Started Jul 18 07:26:18 PM PDT 24
Finished Jul 18 07:26:25 PM PDT 24
Peak memory 219160 kb
Host smart-63393a2f-af67-4a87-b13f-74d2af2284ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386228751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.386228751
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.2935708542
Short name T642
Test name
Test status
Simulation time 26069810 ps
CPU time 1.33 seconds
Started Jul 18 07:26:16 PM PDT 24
Finished Jul 18 07:26:20 PM PDT 24
Peak memory 220704 kb
Host smart-7bba1b5d-6154-4bba-998c-5e2fa5514817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935708542 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.2935708542
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.3143689932
Short name T914
Test name
Test status
Simulation time 81607989 ps
CPU time 1.52 seconds
Started Jul 18 07:26:18 PM PDT 24
Finished Jul 18 07:26:26 PM PDT 24
Peak memory 220192 kb
Host smart-5a5c05da-9dc9-4de9-8e0c-bd1c6e5caa7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143689932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.3143689932
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.2322169916
Short name T636
Test name
Test status
Simulation time 21526651 ps
CPU time 1.15 seconds
Started Jul 18 07:26:17 PM PDT 24
Finished Jul 18 07:26:23 PM PDT 24
Peak memory 218740 kb
Host smart-04f195ca-3381-4867-85e5-2f4b1f9b0a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322169916 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.2322169916
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.2092349583
Short name T789
Test name
Test status
Simulation time 48585360 ps
CPU time 1.75 seconds
Started Jul 18 07:26:18 PM PDT 24
Finished Jul 18 07:26:24 PM PDT 24
Peak memory 219024 kb
Host smart-57c83a64-f0d6-4605-824d-4ce51a8f1071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092349583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.2092349583
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.1374160078
Short name T121
Test name
Test status
Simulation time 39158155 ps
CPU time 1.1 seconds
Started Jul 18 07:26:19 PM PDT 24
Finished Jul 18 07:26:27 PM PDT 24
Peak memory 221088 kb
Host smart-b8486f54-7894-4da9-a146-399fe9b6c981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374160078 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.1374160078
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.582160245
Short name T377
Test name
Test status
Simulation time 27440057 ps
CPU time 1.27 seconds
Started Jul 18 07:26:17 PM PDT 24
Finished Jul 18 07:26:23 PM PDT 24
Peak memory 220204 kb
Host smart-096d0fa6-0e28-4eed-bf37-25bab1251ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582160245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.582160245
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.2220379561
Short name T717
Test name
Test status
Simulation time 40834190 ps
CPU time 1.13 seconds
Started Jul 18 07:26:18 PM PDT 24
Finished Jul 18 07:26:26 PM PDT 24
Peak memory 218912 kb
Host smart-b9b5bd09-b362-47ee-9d72-2b23f7efd55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220379561 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.2220379561
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.3429963307
Short name T417
Test name
Test status
Simulation time 66247592 ps
CPU time 1.73 seconds
Started Jul 18 07:26:18 PM PDT 24
Finished Jul 18 07:26:24 PM PDT 24
Peak memory 218864 kb
Host smart-4cd69e0d-d3a2-4555-a323-75d17cd79306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429963307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3429963307
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.3309042352
Short name T92
Test name
Test status
Simulation time 27840135 ps
CPU time 1.23 seconds
Started Jul 18 07:22:43 PM PDT 24
Finished Jul 18 07:22:46 PM PDT 24
Peak memory 218692 kb
Host smart-3551bcd4-47c3-41f1-8b4b-9e7d9c102be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309042352 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3309042352
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.3332580750
Short name T337
Test name
Test status
Simulation time 25657030 ps
CPU time 0.93 seconds
Started Jul 18 07:22:43 PM PDT 24
Finished Jul 18 07:22:46 PM PDT 24
Peak memory 207036 kb
Host smart-f1ed306c-b474-4306-a254-00eb9867b25b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332580750 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3332580750
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.1206230182
Short name T22
Test name
Test status
Simulation time 25479802 ps
CPU time 0.9 seconds
Started Jul 18 07:22:44 PM PDT 24
Finished Jul 18 07:22:47 PM PDT 24
Peak memory 216488 kb
Host smart-0ea97b72-4a29-4c5d-b8e9-fa7ab7413b3c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206230182 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1206230182
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.1775038185
Short name T193
Test name
Test status
Simulation time 99066529 ps
CPU time 1.07 seconds
Started Jul 18 07:22:44 PM PDT 24
Finished Jul 18 07:22:48 PM PDT 24
Peak memory 217176 kb
Host smart-fec5f44f-3e0f-495f-a7a7-816bfdcabaa2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775038185 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.1775038185
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.3091648404
Short name T724
Test name
Test status
Simulation time 32129151 ps
CPU time 0.96 seconds
Started Jul 18 07:22:44 PM PDT 24
Finished Jul 18 07:22:48 PM PDT 24
Peak memory 220056 kb
Host smart-aa03885b-2607-4998-b922-9d39da967682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091648404 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.3091648404
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.546323082
Short name T656
Test name
Test status
Simulation time 155809187 ps
CPU time 2.36 seconds
Started Jul 18 07:22:45 PM PDT 24
Finished Jul 18 07:22:50 PM PDT 24
Peak memory 220592 kb
Host smart-591eb333-cb2e-48ae-bd67-b353232187ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546323082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.546323082
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.132172656
Short name T101
Test name
Test status
Simulation time 20141410 ps
CPU time 1.09 seconds
Started Jul 18 07:22:45 PM PDT 24
Finished Jul 18 07:22:48 PM PDT 24
Peak memory 216188 kb
Host smart-ee3f5059-b31d-4a76-9c43-89d728fd651b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132172656 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.132172656
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.379833297
Short name T74
Test name
Test status
Simulation time 25844233 ps
CPU time 0.91 seconds
Started Jul 18 07:22:45 PM PDT 24
Finished Jul 18 07:22:49 PM PDT 24
Peak memory 215532 kb
Host smart-ecffe5fd-ff68-4bde-ac47-e3b56b25453b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379833297 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.379833297
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.1959191729
Short name T297
Test name
Test status
Simulation time 217965551 ps
CPU time 4.44 seconds
Started Jul 18 07:22:44 PM PDT 24
Finished Jul 18 07:22:50 PM PDT 24
Peak memory 215632 kb
Host smart-467a01c2-85c2-46b1-90f6-fa1bc39bca30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959191729 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1959191729
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.1713034945
Short name T728
Test name
Test status
Simulation time 183203941113 ps
CPU time 1064.35 seconds
Started Jul 18 07:22:44 PM PDT 24
Finished Jul 18 07:40:31 PM PDT 24
Peak memory 222384 kb
Host smart-24564d5d-592c-49cd-affb-8ccae09129b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713034945 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.1713034945
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.2166160240
Short name T622
Test name
Test status
Simulation time 34947643 ps
CPU time 1.27 seconds
Started Jul 18 07:26:14 PM PDT 24
Finished Jul 18 07:26:17 PM PDT 24
Peak memory 220272 kb
Host smart-cdd2104a-bdf5-4fc9-a942-ffb40df2b6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166160240 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.2166160240
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/141.edn_alert.3742499299
Short name T585
Test name
Test status
Simulation time 79506717 ps
CPU time 1.26 seconds
Started Jul 18 07:26:15 PM PDT 24
Finished Jul 18 07:26:17 PM PDT 24
Peak memory 218820 kb
Host smart-53cab604-4292-4fe1-a0fe-ce01eea066d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742499299 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.3742499299
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.2510784598
Short name T682
Test name
Test status
Simulation time 367247489 ps
CPU time 3.13 seconds
Started Jul 18 07:26:17 PM PDT 24
Finished Jul 18 07:26:23 PM PDT 24
Peak memory 219488 kb
Host smart-681f8a84-e8f5-4f62-9dbd-84ca2a2c4c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510784598 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.2510784598
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.180448387
Short name T438
Test name
Test status
Simulation time 148319628 ps
CPU time 1.35 seconds
Started Jul 18 07:26:18 PM PDT 24
Finished Jul 18 07:26:26 PM PDT 24
Peak memory 219016 kb
Host smart-9b6317e6-707f-4fe4-a51b-4d5f45ba83a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180448387 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.180448387
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.2472503742
Short name T733
Test name
Test status
Simulation time 99997890 ps
CPU time 1.25 seconds
Started Jul 18 07:26:20 PM PDT 24
Finished Jul 18 07:26:28 PM PDT 24
Peak memory 217796 kb
Host smart-3133e662-d54f-4b6a-96dc-40285f32b4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472503742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.2472503742
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.2505572193
Short name T659
Test name
Test status
Simulation time 22521713 ps
CPU time 1.21 seconds
Started Jul 18 07:26:20 PM PDT 24
Finished Jul 18 07:26:28 PM PDT 24
Peak memory 219872 kb
Host smart-9c02253f-b5d8-4e0c-99b6-ce669189a55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505572193 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.2505572193
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.1268217167
Short name T453
Test name
Test status
Simulation time 33974429 ps
CPU time 1.48 seconds
Started Jul 18 07:26:15 PM PDT 24
Finished Jul 18 07:26:18 PM PDT 24
Peak memory 218836 kb
Host smart-65e8e1d8-1c93-4e37-a4f6-9e24d2632669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268217167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.1268217167
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.220508519
Short name T152
Test name
Test status
Simulation time 94558259 ps
CPU time 1.32 seconds
Started Jul 18 07:26:18 PM PDT 24
Finished Jul 18 07:26:25 PM PDT 24
Peak memory 219600 kb
Host smart-2d9660ad-3510-4641-906e-a6d4062f3ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220508519 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.220508519
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.1695480930
Short name T295
Test name
Test status
Simulation time 41532354 ps
CPU time 1.45 seconds
Started Jul 18 07:26:18 PM PDT 24
Finished Jul 18 07:26:26 PM PDT 24
Peak memory 220036 kb
Host smart-71e5dd1a-d231-4c49-8ba5-ba33220ce2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695480930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.1695480930
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.1450293601
Short name T69
Test name
Test status
Simulation time 68367723 ps
CPU time 1.4 seconds
Started Jul 18 07:26:17 PM PDT 24
Finished Jul 18 07:26:23 PM PDT 24
Peak memory 220332 kb
Host smart-6d18fa57-ed02-4e93-857d-aafdc888c1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450293601 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.1450293601
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.521382177
Short name T639
Test name
Test status
Simulation time 42607466 ps
CPU time 1.61 seconds
Started Jul 18 07:26:22 PM PDT 24
Finished Jul 18 07:26:29 PM PDT 24
Peak memory 217676 kb
Host smart-f7bb5c4c-a4d0-4a9f-aecc-1c1e8cd68a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521382177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.521382177
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.1559357638
Short name T763
Test name
Test status
Simulation time 30067359 ps
CPU time 1.29 seconds
Started Jul 18 07:26:18 PM PDT 24
Finished Jul 18 07:26:24 PM PDT 24
Peak memory 219040 kb
Host smart-686a4e27-021f-4a31-852f-80740f15bdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559357638 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.1559357638
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.3237817329
Short name T360
Test name
Test status
Simulation time 44076710 ps
CPU time 1.32 seconds
Started Jul 18 07:26:22 PM PDT 24
Finished Jul 18 07:26:29 PM PDT 24
Peak memory 218764 kb
Host smart-b75ec19d-9d18-4c03-b40f-815315ce9a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237817329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.3237817329
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.1171127977
Short name T403
Test name
Test status
Simulation time 61067639 ps
CPU time 1.16 seconds
Started Jul 18 07:26:16 PM PDT 24
Finished Jul 18 07:26:19 PM PDT 24
Peak memory 218904 kb
Host smart-f411a755-786f-47d3-ba1c-5e437dc774e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171127977 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.1171127977
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.3832172274
Short name T464
Test name
Test status
Simulation time 107438113 ps
CPU time 1.24 seconds
Started Jul 18 07:26:15 PM PDT 24
Finished Jul 18 07:26:19 PM PDT 24
Peak memory 220436 kb
Host smart-89423e7b-8b23-48a1-9b46-17d64b77a705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832172274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3832172274
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.712041071
Short name T770
Test name
Test status
Simulation time 27584766 ps
CPU time 1.24 seconds
Started Jul 18 07:26:16 PM PDT 24
Finished Jul 18 07:26:20 PM PDT 24
Peak memory 218876 kb
Host smart-2a28abca-5705-4a1d-9975-b2d82c2b983c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712041071 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.712041071
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.921218784
Short name T66
Test name
Test status
Simulation time 39607373 ps
CPU time 1.54 seconds
Started Jul 18 07:26:18 PM PDT 24
Finished Jul 18 07:26:25 PM PDT 24
Peak memory 218716 kb
Host smart-c52a1162-98b1-434a-b265-6cf27dd12abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921218784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.921218784
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.3477092929
Short name T933
Test name
Test status
Simulation time 41090580 ps
CPU time 1.17 seconds
Started Jul 18 07:26:18 PM PDT 24
Finished Jul 18 07:26:24 PM PDT 24
Peak memory 218920 kb
Host smart-4c3e64bf-73f9-4d06-b832-79dc8f8bbc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477092929 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.3477092929
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.3420014517
Short name T792
Test name
Test status
Simulation time 104494861 ps
CPU time 1.34 seconds
Started Jul 18 07:26:15 PM PDT 24
Finished Jul 18 07:26:18 PM PDT 24
Peak memory 217856 kb
Host smart-efc4cee7-95b0-4573-ab8e-9a7e5fcf1ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420014517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.3420014517
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.4088571244
Short name T159
Test name
Test status
Simulation time 47363049 ps
CPU time 1.18 seconds
Started Jul 18 07:22:44 PM PDT 24
Finished Jul 18 07:22:47 PM PDT 24
Peak memory 221156 kb
Host smart-d9f7ee7a-53d0-4792-894d-d8573a9a3e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088571244 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.4088571244
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.1293394883
Short name T436
Test name
Test status
Simulation time 69914727 ps
CPU time 0.97 seconds
Started Jul 18 07:22:45 PM PDT 24
Finished Jul 18 07:22:48 PM PDT 24
Peak memory 207076 kb
Host smart-b8977048-a280-4233-894e-3b2eebf6d4b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293394883 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.1293394883
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.111629341
Short name T955
Test name
Test status
Simulation time 12738398 ps
CPU time 0.94 seconds
Started Jul 18 07:22:44 PM PDT 24
Finished Jul 18 07:22:46 PM PDT 24
Peak memory 216716 kb
Host smart-a7db0122-1340-4ab4-800c-410562625fbe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111629341 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.111629341
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.497831158
Short name T141
Test name
Test status
Simulation time 42387013 ps
CPU time 1.49 seconds
Started Jul 18 07:22:45 PM PDT 24
Finished Jul 18 07:22:49 PM PDT 24
Peak memory 217128 kb
Host smart-d6748299-d217-4d84-bc74-48b7e10b84ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497831158 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_di
sable_auto_req_mode.497831158
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.1854572897
Short name T670
Test name
Test status
Simulation time 28142917 ps
CPU time 0.98 seconds
Started Jul 18 07:22:44 PM PDT 24
Finished Jul 18 07:22:46 PM PDT 24
Peak memory 224088 kb
Host smart-c0c24746-2e53-4405-99f8-f51c1aeead59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854572897 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.1854572897
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.3020132394
Short name T907
Test name
Test status
Simulation time 32971084 ps
CPU time 0.95 seconds
Started Jul 18 07:22:44 PM PDT 24
Finished Jul 18 07:22:47 PM PDT 24
Peak memory 217596 kb
Host smart-44cc59d6-0e96-4aa0-9558-6adf58c74b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020132394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.3020132394
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.1402444861
Short name T556
Test name
Test status
Simulation time 32701067 ps
CPU time 0.89 seconds
Started Jul 18 07:22:43 PM PDT 24
Finished Jul 18 07:22:46 PM PDT 24
Peak memory 215748 kb
Host smart-1d1d84ff-0623-4184-a144-2b14082548ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402444861 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.1402444861
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.1250954896
Short name T391
Test name
Test status
Simulation time 14706873 ps
CPU time 0.96 seconds
Started Jul 18 07:22:45 PM PDT 24
Finished Jul 18 07:22:48 PM PDT 24
Peak memory 215644 kb
Host smart-824a620c-610e-44e3-9806-11f2cf157e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250954896 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.1250954896
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.1092122854
Short name T602
Test name
Test status
Simulation time 657507358 ps
CPU time 2.62 seconds
Started Jul 18 07:22:43 PM PDT 24
Finished Jul 18 07:22:48 PM PDT 24
Peak memory 217320 kb
Host smart-02e0b565-950c-4500-b803-3555f979d5b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092122854 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1092122854
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2187382918
Short name T37
Test name
Test status
Simulation time 40466102548 ps
CPU time 1057.05 seconds
Started Jul 18 07:22:46 PM PDT 24
Finished Jul 18 07:40:25 PM PDT 24
Peak memory 224040 kb
Host smart-f81315ab-18a1-4029-aad6-68f6a70fe290
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187382918 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.2187382918
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.2354565500
Short name T233
Test name
Test status
Simulation time 316251310 ps
CPU time 1.1 seconds
Started Jul 18 07:26:17 PM PDT 24
Finished Jul 18 07:26:21 PM PDT 24
Peak memory 220976 kb
Host smart-217a998e-baf4-46ae-8e8f-ccd8518a32c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354565500 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.2354565500
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.1948914605
Short name T590
Test name
Test status
Simulation time 51526872 ps
CPU time 1.18 seconds
Started Jul 18 07:26:15 PM PDT 24
Finished Jul 18 07:26:18 PM PDT 24
Peak memory 218636 kb
Host smart-8d5ea6e8-a6ba-44ec-9021-256d1b06adcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948914605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.1948914605
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.3237024593
Short name T778
Test name
Test status
Simulation time 49334021 ps
CPU time 1.21 seconds
Started Jul 18 07:26:18 PM PDT 24
Finished Jul 18 07:26:24 PM PDT 24
Peak memory 219048 kb
Host smart-d0ea8e64-84b5-4c6e-8aac-060299e22ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237024593 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.3237024593
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.3575907538
Short name T566
Test name
Test status
Simulation time 33613878 ps
CPU time 1.32 seconds
Started Jul 18 07:26:16 PM PDT 24
Finished Jul 18 07:26:19 PM PDT 24
Peak memory 217428 kb
Host smart-2af86f6e-d528-415f-939d-84e82162cfea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575907538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.3575907538
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.1371407875
Short name T665
Test name
Test status
Simulation time 39654217 ps
CPU time 1.12 seconds
Started Jul 18 07:26:18 PM PDT 24
Finished Jul 18 07:26:25 PM PDT 24
Peak memory 218556 kb
Host smart-74fbed5c-f705-4277-a5dc-3e2473f82f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371407875 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.1371407875
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.588515877
Short name T953
Test name
Test status
Simulation time 73801979 ps
CPU time 1.55 seconds
Started Jul 18 07:26:22 PM PDT 24
Finished Jul 18 07:26:30 PM PDT 24
Peak memory 219196 kb
Host smart-5a5e7dd8-e18c-4f5b-8b3d-b0aefcb9ae84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588515877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.588515877
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.4213763052
Short name T972
Test name
Test status
Simulation time 39800767 ps
CPU time 1.11 seconds
Started Jul 18 07:26:16 PM PDT 24
Finished Jul 18 07:26:21 PM PDT 24
Peak memory 219116 kb
Host smart-cee67d10-8843-46df-bf91-b26e7c98c13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213763052 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.4213763052
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.3989796757
Short name T410
Test name
Test status
Simulation time 101353497 ps
CPU time 1.56 seconds
Started Jul 18 07:26:16 PM PDT 24
Finished Jul 18 07:26:21 PM PDT 24
Peak memory 219064 kb
Host smart-f877ed37-bc01-4737-b590-38f64b94da61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989796757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.3989796757
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.3310329427
Short name T774
Test name
Test status
Simulation time 30690017 ps
CPU time 1.13 seconds
Started Jul 18 07:26:17 PM PDT 24
Finished Jul 18 07:26:23 PM PDT 24
Peak memory 219148 kb
Host smart-ccef16c8-33aa-49d5-a240-f2a5316e8f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310329427 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.3310329427
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.3018124398
Short name T64
Test name
Test status
Simulation time 28379800 ps
CPU time 1.37 seconds
Started Jul 18 07:26:18 PM PDT 24
Finished Jul 18 07:26:23 PM PDT 24
Peak memory 219008 kb
Host smart-8ea040ad-3b0e-4ccc-87a4-9500d81ddbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018124398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3018124398
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.2054533619
Short name T837
Test name
Test status
Simulation time 33345409 ps
CPU time 1.24 seconds
Started Jul 18 07:26:17 PM PDT 24
Finished Jul 18 07:26:23 PM PDT 24
Peak memory 219976 kb
Host smart-75e53d30-f59b-4f28-9f5f-298cfad31f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054533619 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.2054533619
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.2690430439
Short name T970
Test name
Test status
Simulation time 46202023 ps
CPU time 1.52 seconds
Started Jul 18 07:26:19 PM PDT 24
Finished Jul 18 07:26:26 PM PDT 24
Peak memory 218628 kb
Host smart-74ccadbf-675f-488e-8ede-8244176f15ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690430439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.2690430439
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.3457516312
Short name T742
Test name
Test status
Simulation time 74890915 ps
CPU time 1.12 seconds
Started Jul 18 07:26:18 PM PDT 24
Finished Jul 18 07:26:25 PM PDT 24
Peak memory 220888 kb
Host smart-57e4fec4-1b91-4469-90fc-600e2939e464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457516312 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.3457516312
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.638134989
Short name T336
Test name
Test status
Simulation time 67427649 ps
CPU time 1.33 seconds
Started Jul 18 07:26:18 PM PDT 24
Finished Jul 18 07:26:23 PM PDT 24
Peak memory 219212 kb
Host smart-cd38a546-cee9-4532-89e2-0d8fe97a22bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638134989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.638134989
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.2659499424
Short name T128
Test name
Test status
Simulation time 29449745 ps
CPU time 1.44 seconds
Started Jul 18 07:26:18 PM PDT 24
Finished Jul 18 07:26:24 PM PDT 24
Peak memory 218916 kb
Host smart-34e24ae1-a81d-4760-9e94-0933ad46ff1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659499424 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.2659499424
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.2806549007
Short name T276
Test name
Test status
Simulation time 81004329 ps
CPU time 1.48 seconds
Started Jul 18 07:26:22 PM PDT 24
Finished Jul 18 07:26:29 PM PDT 24
Peak memory 219172 kb
Host smart-1e85b1f2-4891-47a6-b0a0-a703b81ae02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806549007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2806549007
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.1373305702
Short name T758
Test name
Test status
Simulation time 353401225 ps
CPU time 1.34 seconds
Started Jul 18 07:26:20 PM PDT 24
Finished Jul 18 07:26:28 PM PDT 24
Peak memory 218852 kb
Host smart-ba53187a-634a-4b6a-a46d-56d43096d6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373305702 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.1373305702
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.1786244417
Short name T348
Test name
Test status
Simulation time 134245022 ps
CPU time 1.1 seconds
Started Jul 18 07:26:18 PM PDT 24
Finished Jul 18 07:26:26 PM PDT 24
Peak memory 217712 kb
Host smart-ce0fb164-b8d4-4cf6-b8b4-61bb7ac0cce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786244417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1786244417
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.803482890
Short name T552
Test name
Test status
Simulation time 118161812 ps
CPU time 1.19 seconds
Started Jul 18 07:23:03 PM PDT 24
Finished Jul 18 07:23:05 PM PDT 24
Peak memory 219388 kb
Host smart-25c77e46-13ad-45b9-8fee-7eb072e182ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803482890 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.803482890
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.3619330509
Short name T357
Test name
Test status
Simulation time 89897737 ps
CPU time 0.91 seconds
Started Jul 18 07:23:02 PM PDT 24
Finished Jul 18 07:23:04 PM PDT 24
Peak memory 215504 kb
Host smart-ca71776a-b424-4642-8b19-42ab5c4412ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619330509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3619330509
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.1420436108
Short name T964
Test name
Test status
Simulation time 66872279 ps
CPU time 1.02 seconds
Started Jul 18 07:23:05 PM PDT 24
Finished Jul 18 07:23:08 PM PDT 24
Peak memory 218848 kb
Host smart-d1ce5596-02a8-4a97-af9d-bdd8bb5514a2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420436108 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.1420436108
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.18662701
Short name T874
Test name
Test status
Simulation time 24894303 ps
CPU time 1.12 seconds
Started Jul 18 07:23:03 PM PDT 24
Finished Jul 18 07:23:06 PM PDT 24
Peak memory 229856 kb
Host smart-3d3ff8c7-50de-4789-8b3c-608e0e310479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18662701 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.18662701
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.2776293423
Short name T407
Test name
Test status
Simulation time 103631715 ps
CPU time 1.02 seconds
Started Jul 18 07:23:06 PM PDT 24
Finished Jul 18 07:23:10 PM PDT 24
Peak memory 219468 kb
Host smart-5d640ace-7b5e-4770-808d-ef2253036c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776293423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2776293423
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.3792672617
Short name T894
Test name
Test status
Simulation time 41388167 ps
CPU time 0.96 seconds
Started Jul 18 07:23:03 PM PDT 24
Finished Jul 18 07:23:05 PM PDT 24
Peak memory 215864 kb
Host smart-318fb9b0-0a28-4cb7-a89b-58a3dadaa708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792672617 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.3792672617
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.3631078312
Short name T553
Test name
Test status
Simulation time 15951134 ps
CPU time 0.97 seconds
Started Jul 18 07:23:03 PM PDT 24
Finished Jul 18 07:23:05 PM PDT 24
Peak memory 215580 kb
Host smart-81944603-4c63-409b-9dc5-c98e03d69890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631078312 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.3631078312
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.174889321
Short name T242
Test name
Test status
Simulation time 1299017971 ps
CPU time 4.32 seconds
Started Jul 18 07:23:05 PM PDT 24
Finished Jul 18 07:23:12 PM PDT 24
Peak memory 217440 kb
Host smart-c54c72b9-4251-4a10-8153-49cbb3fbc57e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174889321 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.174889321
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.3242367465
Short name T716
Test name
Test status
Simulation time 74741081963 ps
CPU time 967.85 seconds
Started Jul 18 07:23:02 PM PDT 24
Finished Jul 18 07:39:12 PM PDT 24
Peak memory 222912 kb
Host smart-1ac20f22-fd22-4a54-af9b-198d6099f915
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242367465 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.3242367465
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.3524456614
Short name T805
Test name
Test status
Simulation time 30579258 ps
CPU time 1.27 seconds
Started Jul 18 07:26:18 PM PDT 24
Finished Jul 18 07:26:26 PM PDT 24
Peak memory 220208 kb
Host smart-fe96ee22-2b48-4f1f-826c-ddb50ad9e893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524456614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.3524456614
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.2622013899
Short name T650
Test name
Test status
Simulation time 24558635 ps
CPU time 1.17 seconds
Started Jul 18 07:26:15 PM PDT 24
Finished Jul 18 07:26:18 PM PDT 24
Peak memory 219944 kb
Host smart-9c2941ab-7758-4d41-9b0a-0615acb4a5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622013899 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.2622013899
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.3181941768
Short name T519
Test name
Test status
Simulation time 81880547 ps
CPU time 1.27 seconds
Started Jul 18 07:26:19 PM PDT 24
Finished Jul 18 07:26:27 PM PDT 24
Peak memory 215596 kb
Host smart-88229136-4bd6-401d-9cb7-ebcbf52284ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181941768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.3181941768
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.1869195656
Short name T291
Test name
Test status
Simulation time 43220323 ps
CPU time 1.28 seconds
Started Jul 18 07:26:19 PM PDT 24
Finished Jul 18 07:26:27 PM PDT 24
Peak memory 219028 kb
Host smart-7b9d3efc-881f-4290-8989-56dcc490d0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869195656 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.1869195656
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.240270420
Short name T490
Test name
Test status
Simulation time 374779605 ps
CPU time 4.38 seconds
Started Jul 18 07:26:18 PM PDT 24
Finished Jul 18 07:26:29 PM PDT 24
Peak memory 220568 kb
Host smart-61b29e56-3db5-4403-bd0e-9bfbeb39682e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240270420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.240270420
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.2051094603
Short name T690
Test name
Test status
Simulation time 67364465 ps
CPU time 1.15 seconds
Started Jul 18 07:26:18 PM PDT 24
Finished Jul 18 07:26:26 PM PDT 24
Peak memory 221120 kb
Host smart-3facba74-5e7f-4cdd-a06a-af3067dff178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051094603 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.2051094603
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.2064764215
Short name T762
Test name
Test status
Simulation time 46302535 ps
CPU time 1.49 seconds
Started Jul 18 07:26:22 PM PDT 24
Finished Jul 18 07:26:29 PM PDT 24
Peak memory 218740 kb
Host smart-63656e90-0220-43a4-9b23-a83fe9af7f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064764215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2064764215
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.731783675
Short name T470
Test name
Test status
Simulation time 139105372 ps
CPU time 1.25 seconds
Started Jul 18 07:26:31 PM PDT 24
Finished Jul 18 07:26:36 PM PDT 24
Peak memory 220192 kb
Host smart-793e3f36-9bee-4edb-a545-6ec0f3700ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731783675 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.731783675
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.3329626503
Short name T356
Test name
Test status
Simulation time 62338373 ps
CPU time 1.3 seconds
Started Jul 18 07:26:18 PM PDT 24
Finished Jul 18 07:26:26 PM PDT 24
Peak memory 218660 kb
Host smart-44a2ce67-c91c-4b52-8bab-7742865d5d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329626503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3329626503
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.3868872308
Short name T512
Test name
Test status
Simulation time 89491490 ps
CPU time 1.19 seconds
Started Jul 18 07:26:34 PM PDT 24
Finished Jul 18 07:26:44 PM PDT 24
Peak memory 220040 kb
Host smart-33ab0fdc-cf93-4112-b780-0ddd51bcf6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868872308 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.3868872308
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.3215222973
Short name T352
Test name
Test status
Simulation time 33842792 ps
CPU time 1.43 seconds
Started Jul 18 07:26:32 PM PDT 24
Finished Jul 18 07:26:38 PM PDT 24
Peak memory 218896 kb
Host smart-0a751c34-09d6-4cf0-a83a-36c8c9693882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215222973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.3215222973
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.2957910841
Short name T524
Test name
Test status
Simulation time 37473587 ps
CPU time 1.12 seconds
Started Jul 18 07:26:34 PM PDT 24
Finished Jul 18 07:26:42 PM PDT 24
Peak memory 219064 kb
Host smart-208176cd-a4ad-417c-9dd7-a13e5b85086c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957910841 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.2957910841
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.345674340
Short name T883
Test name
Test status
Simulation time 50187148 ps
CPU time 1.66 seconds
Started Jul 18 07:26:30 PM PDT 24
Finished Jul 18 07:26:34 PM PDT 24
Peak memory 220156 kb
Host smart-9ecd90c5-3da7-4bac-81c0-d35420126776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345674340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.345674340
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.2234353126
Short name T144
Test name
Test status
Simulation time 184419958 ps
CPU time 1.19 seconds
Started Jul 18 07:26:30 PM PDT 24
Finished Jul 18 07:26:34 PM PDT 24
Peak memory 218912 kb
Host smart-e541966a-13c0-4f2f-aa47-c1259cdbcb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234353126 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.2234353126
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.2285947645
Short name T329
Test name
Test status
Simulation time 35179322 ps
CPU time 1.47 seconds
Started Jul 18 07:26:32 PM PDT 24
Finished Jul 18 07:26:39 PM PDT 24
Peak memory 218752 kb
Host smart-d0dfebda-af37-47f3-ac2d-51b0db595e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285947645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.2285947645
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.2669640175
Short name T285
Test name
Test status
Simulation time 41032022 ps
CPU time 1.19 seconds
Started Jul 18 07:26:36 PM PDT 24
Finished Jul 18 07:26:45 PM PDT 24
Peak memory 219604 kb
Host smart-455eb6f5-524f-4136-a5b7-9114a32ec796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669640175 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.2669640175
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.3292949373
Short name T959
Test name
Test status
Simulation time 50489219 ps
CPU time 1.6 seconds
Started Jul 18 07:26:33 PM PDT 24
Finished Jul 18 07:26:40 PM PDT 24
Peak memory 220076 kb
Host smart-2c13b0c7-0f66-4216-aeb9-3eecd5f2230d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292949373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.3292949373
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.1145154425
Short name T282
Test name
Test status
Simulation time 22395382 ps
CPU time 1.19 seconds
Started Jul 18 07:23:05 PM PDT 24
Finished Jul 18 07:23:08 PM PDT 24
Peak memory 219292 kb
Host smart-64e8cad6-bb1e-4d49-a41e-6e030c4bb223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145154425 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1145154425
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.3514571504
Short name T980
Test name
Test status
Simulation time 86403387 ps
CPU time 0.86 seconds
Started Jul 18 07:23:05 PM PDT 24
Finished Jul 18 07:23:09 PM PDT 24
Peak memory 206836 kb
Host smart-f660a30d-74d3-43f7-900a-067dcba193da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514571504 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3514571504
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.3560584594
Short name T663
Test name
Test status
Simulation time 35335420 ps
CPU time 0.9 seconds
Started Jul 18 07:23:06 PM PDT 24
Finished Jul 18 07:23:10 PM PDT 24
Peak memory 216580 kb
Host smart-0a8d181f-e802-481c-8f79-3f0e7f3c8ebd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560584594 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3560584594
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.38517738
Short name T915
Test name
Test status
Simulation time 60771611 ps
CPU time 1.07 seconds
Started Jul 18 07:23:05 PM PDT 24
Finished Jul 18 07:23:09 PM PDT 24
Peak memory 219912 kb
Host smart-a8547b82-cdc3-4e1f-a9fb-6026f14b93d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38517738 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_dis
able_auto_req_mode.38517738
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.3237131585
Short name T963
Test name
Test status
Simulation time 19477620 ps
CPU time 1.23 seconds
Started Jul 18 07:23:04 PM PDT 24
Finished Jul 18 07:23:08 PM PDT 24
Peak memory 224268 kb
Host smart-aeff6213-2821-466c-8405-4342e18720f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237131585 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.3237131585
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.2354097806
Short name T375
Test name
Test status
Simulation time 35300067 ps
CPU time 1.09 seconds
Started Jul 18 07:23:07 PM PDT 24
Finished Jul 18 07:23:11 PM PDT 24
Peak memory 217608 kb
Host smart-d01f1cb2-e144-4bf6-9baa-5748e2532acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354097806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2354097806
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3270949584
Short name T34
Test name
Test status
Simulation time 44628018 ps
CPU time 0.81 seconds
Started Jul 18 07:23:05 PM PDT 24
Finished Jul 18 07:23:08 PM PDT 24
Peak memory 215848 kb
Host smart-d74270af-90b2-4abc-940c-c3945242699c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270949584 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3270949584
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.3424703372
Short name T446
Test name
Test status
Simulation time 25619387 ps
CPU time 0.99 seconds
Started Jul 18 07:23:05 PM PDT 24
Finished Jul 18 07:23:09 PM PDT 24
Peak memory 215620 kb
Host smart-5a3553af-5a1f-4805-8c50-cb67c42064a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424703372 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.3424703372
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1860304394
Short name T730
Test name
Test status
Simulation time 182422480 ps
CPU time 4.21 seconds
Started Jul 18 07:23:04 PM PDT 24
Finished Jul 18 07:23:11 PM PDT 24
Peak memory 217332 kb
Host smart-51a8f4bd-2319-40ad-8458-3f28305d70df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860304394 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1860304394
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.1147831572
Short name T223
Test name
Test status
Simulation time 278467313719 ps
CPU time 1583.42 seconds
Started Jul 18 07:23:03 PM PDT 24
Finished Jul 18 07:49:29 PM PDT 24
Peak memory 227412 kb
Host smart-62d780a7-4d53-403d-93fd-441213cc98ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147831572 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.1147831572
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.2653327078
Short name T582
Test name
Test status
Simulation time 27756708 ps
CPU time 1.22 seconds
Started Jul 18 07:26:31 PM PDT 24
Finished Jul 18 07:26:37 PM PDT 24
Peak memory 220068 kb
Host smart-d78f1dc8-0de7-471e-b4a4-a6cdeb779a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653327078 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.2653327078
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.114672322
Short name T798
Test name
Test status
Simulation time 72319431 ps
CPU time 2.61 seconds
Started Jul 18 07:26:32 PM PDT 24
Finished Jul 18 07:26:39 PM PDT 24
Peak memory 220428 kb
Host smart-d1c58b4f-93a3-40f9-aacc-fc90a2f2332f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114672322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.114672322
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.841303153
Short name T283
Test name
Test status
Simulation time 81346509 ps
CPU time 1.24 seconds
Started Jul 18 07:26:32 PM PDT 24
Finished Jul 18 07:26:37 PM PDT 24
Peak memory 218892 kb
Host smart-6748a864-4d82-4b99-b884-374194b8d772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841303153 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.841303153
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/172.edn_alert.1784981170
Short name T812
Test name
Test status
Simulation time 86053595 ps
CPU time 1.21 seconds
Started Jul 18 07:26:30 PM PDT 24
Finished Jul 18 07:26:34 PM PDT 24
Peak memory 216032 kb
Host smart-8233da2c-e64c-4f7a-b1ea-f961ecb7d74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784981170 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.1784981170
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.1555701784
Short name T842
Test name
Test status
Simulation time 48993915 ps
CPU time 1.13 seconds
Started Jul 18 07:26:31 PM PDT 24
Finished Jul 18 07:26:35 PM PDT 24
Peak memory 217748 kb
Host smart-4abc607e-0cd1-4f11-bbeb-fb31a8e2ed2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555701784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.1555701784
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.3040304244
Short name T611
Test name
Test status
Simulation time 47130124 ps
CPU time 1.16 seconds
Started Jul 18 07:26:34 PM PDT 24
Finished Jul 18 07:26:42 PM PDT 24
Peak memory 218928 kb
Host smart-c11b43a9-ab4c-4b4a-b9c4-f0e9efa50833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040304244 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.3040304244
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.2472176246
Short name T737
Test name
Test status
Simulation time 50847116 ps
CPU time 1.53 seconds
Started Jul 18 07:26:31 PM PDT 24
Finished Jul 18 07:26:35 PM PDT 24
Peak memory 220244 kb
Host smart-d9953b5a-2aa1-4072-b100-84bf341ba321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472176246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.2472176246
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.3394829586
Short name T151
Test name
Test status
Simulation time 25934450 ps
CPU time 1.19 seconds
Started Jul 18 07:26:32 PM PDT 24
Finished Jul 18 07:26:37 PM PDT 24
Peak memory 221284 kb
Host smart-51e6e57c-f386-46ff-830f-b922958a797d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394829586 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.3394829586
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/175.edn_alert.3279247801
Short name T127
Test name
Test status
Simulation time 52150233 ps
CPU time 1.27 seconds
Started Jul 18 07:26:34 PM PDT 24
Finished Jul 18 07:26:42 PM PDT 24
Peak memory 216008 kb
Host smart-44e40db6-892a-4f1e-a177-ff591b35f5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279247801 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.3279247801
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.582782983
Short name T427
Test name
Test status
Simulation time 279446702 ps
CPU time 1.32 seconds
Started Jul 18 07:26:32 PM PDT 24
Finished Jul 18 07:26:39 PM PDT 24
Peak memory 218104 kb
Host smart-c809ac06-8a4d-4a70-90c9-d6b94fae92f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582782983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.582782983
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.2845732290
Short name T638
Test name
Test status
Simulation time 61242627 ps
CPU time 1.24 seconds
Started Jul 18 07:26:34 PM PDT 24
Finished Jul 18 07:26:44 PM PDT 24
Peak memory 220072 kb
Host smart-e5526318-bc4e-4842-85c8-d94003446caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845732290 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.2845732290
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.3573247009
Short name T376
Test name
Test status
Simulation time 76105219 ps
CPU time 1.19 seconds
Started Jul 18 07:26:31 PM PDT 24
Finished Jul 18 07:26:36 PM PDT 24
Peak memory 217512 kb
Host smart-bb66b5bd-9fe1-47c4-9cdd-5ba04876bce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573247009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.3573247009
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.2703805568
Short name T859
Test name
Test status
Simulation time 46674938 ps
CPU time 1.18 seconds
Started Jul 18 07:26:30 PM PDT 24
Finished Jul 18 07:26:33 PM PDT 24
Peak memory 220416 kb
Host smart-eab44048-fdc1-4a6e-b5e9-29f2f5911329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703805568 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.2703805568
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.2333797271
Short name T957
Test name
Test status
Simulation time 66057164 ps
CPU time 1.54 seconds
Started Jul 18 07:26:33 PM PDT 24
Finished Jul 18 07:26:40 PM PDT 24
Peak memory 218904 kb
Host smart-007e4d53-dcf3-4932-82cb-2900b10bb704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333797271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2333797271
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.4121616410
Short name T696
Test name
Test status
Simulation time 249762509 ps
CPU time 1.19 seconds
Started Jul 18 07:26:32 PM PDT 24
Finished Jul 18 07:26:39 PM PDT 24
Peak memory 219732 kb
Host smart-9f888ad8-4307-48c0-80b5-46dfc24b13b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121616410 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.4121616410
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.1386690727
Short name T392
Test name
Test status
Simulation time 85017031 ps
CPU time 1.61 seconds
Started Jul 18 07:26:33 PM PDT 24
Finished Jul 18 07:26:40 PM PDT 24
Peak memory 219016 kb
Host smart-3506c47b-f87d-425f-97d8-0f61c479a55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386690727 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1386690727
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.1672039816
Short name T175
Test name
Test status
Simulation time 34318614 ps
CPU time 1.33 seconds
Started Jul 18 07:26:34 PM PDT 24
Finished Jul 18 07:26:44 PM PDT 24
Peak memory 216024 kb
Host smart-a9dd65d4-a6be-4526-ae47-9d4a686e2e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672039816 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.1672039816
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert.368127519
Short name T876
Test name
Test status
Simulation time 26296218 ps
CPU time 1.31 seconds
Started Jul 18 07:23:05 PM PDT 24
Finished Jul 18 07:23:10 PM PDT 24
Peak memory 220188 kb
Host smart-a5623326-9ce5-499c-8d7e-ca68ddc0bed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368127519 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.368127519
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.1264355284
Short name T975
Test name
Test status
Simulation time 71204489 ps
CPU time 1.01 seconds
Started Jul 18 07:23:17 PM PDT 24
Finished Jul 18 07:23:19 PM PDT 24
Peak memory 207080 kb
Host smart-b97b6157-1bc1-4489-a73e-14c069b0f295
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264355284 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.1264355284
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.2785465110
Short name T640
Test name
Test status
Simulation time 24775576 ps
CPU time 0.87 seconds
Started Jul 18 07:23:06 PM PDT 24
Finished Jul 18 07:23:10 PM PDT 24
Peak memory 216648 kb
Host smart-9523f811-6def-42a5-9fa7-f32ba5953201
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785465110 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2785465110
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_err.3949152658
Short name T938
Test name
Test status
Simulation time 19577450 ps
CPU time 1.17 seconds
Started Jul 18 07:23:05 PM PDT 24
Finished Jul 18 07:23:08 PM PDT 24
Peak memory 218896 kb
Host smart-68190bec-7ce5-43a7-ae65-88466c185529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949152658 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.3949152658
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.2185871073
Short name T459
Test name
Test status
Simulation time 72070591 ps
CPU time 1.06 seconds
Started Jul 18 07:23:05 PM PDT 24
Finished Jul 18 07:23:10 PM PDT 24
Peak memory 217452 kb
Host smart-4deb20dc-9b6f-4440-9caa-f2c2abb780c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185871073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.2185871073
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_smoke.2075516545
Short name T954
Test name
Test status
Simulation time 183636307 ps
CPU time 1 seconds
Started Jul 18 07:23:06 PM PDT 24
Finished Jul 18 07:23:10 PM PDT 24
Peak memory 215636 kb
Host smart-8bf11aee-1cf6-444b-8b37-95b68983707c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075516545 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2075516545
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1595356787
Short name T600
Test name
Test status
Simulation time 231828450 ps
CPU time 4.57 seconds
Started Jul 18 07:23:05 PM PDT 24
Finished Jul 18 07:23:13 PM PDT 24
Peak memory 217572 kb
Host smart-c4843d5e-e6c8-4f42-b2aa-9e0d61c6d452
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595356787 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1595356787
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.105186510
Short name T454
Test name
Test status
Simulation time 12394634318 ps
CPU time 338.24 seconds
Started Jul 18 07:23:06 PM PDT 24
Finished Jul 18 07:28:48 PM PDT 24
Peak memory 218624 kb
Host smart-1a88b6b0-2810-4ccb-ae69-f3acf864895d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105186510 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.105186510
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.1228660193
Short name T694
Test name
Test status
Simulation time 88445645 ps
CPU time 1.26 seconds
Started Jul 18 07:26:32 PM PDT 24
Finished Jul 18 07:26:38 PM PDT 24
Peak memory 219092 kb
Host smart-44c43af7-1f95-4f68-be32-798c6cbe3a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228660193 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.1228660193
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.2721021703
Short name T443
Test name
Test status
Simulation time 45785947 ps
CPU time 1.23 seconds
Started Jul 18 07:26:31 PM PDT 24
Finished Jul 18 07:26:37 PM PDT 24
Peak memory 218996 kb
Host smart-11bdd0d2-a6db-4d3c-8a4c-166ba32f19bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721021703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.2721021703
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.135652080
Short name T968
Test name
Test status
Simulation time 82662175 ps
CPU time 1.12 seconds
Started Jul 18 07:26:32 PM PDT 24
Finished Jul 18 07:26:38 PM PDT 24
Peak memory 219872 kb
Host smart-da310968-18e8-45d1-9f59-2c66dde1c7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135652080 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.135652080
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.3042729968
Short name T869
Test name
Test status
Simulation time 39459595 ps
CPU time 1.09 seconds
Started Jul 18 07:26:30 PM PDT 24
Finished Jul 18 07:26:35 PM PDT 24
Peak memory 218844 kb
Host smart-a45f1921-84c7-43cb-82bf-f404901825d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042729968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3042729968
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.719986424
Short name T245
Test name
Test status
Simulation time 133816221 ps
CPU time 1.2 seconds
Started Jul 18 07:26:30 PM PDT 24
Finished Jul 18 07:26:33 PM PDT 24
Peak memory 220724 kb
Host smart-3ecf84f7-9860-45bf-b2ec-ece406a30e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719986424 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.719986424
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.3086870529
Short name T2
Test name
Test status
Simulation time 44401334 ps
CPU time 1.23 seconds
Started Jul 18 07:26:33 PM PDT 24
Finished Jul 18 07:26:42 PM PDT 24
Peak memory 220248 kb
Host smart-ee726915-5856-43cc-b297-658367c0909c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086870529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.3086870529
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.2391942402
Short name T234
Test name
Test status
Simulation time 30776857 ps
CPU time 1.35 seconds
Started Jul 18 07:26:30 PM PDT 24
Finished Jul 18 07:26:34 PM PDT 24
Peak memory 220620 kb
Host smart-431cc665-6a73-4fe9-9957-a39cdf04b338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391942402 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.2391942402
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.193117814
Short name T373
Test name
Test status
Simulation time 92167992 ps
CPU time 1.11 seconds
Started Jul 18 07:26:34 PM PDT 24
Finished Jul 18 07:26:42 PM PDT 24
Peak memory 217512 kb
Host smart-4826f186-3031-49ba-be57-08156df0b804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193117814 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.193117814
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.2636896130
Short name T286
Test name
Test status
Simulation time 98735209 ps
CPU time 1.26 seconds
Started Jul 18 07:26:35 PM PDT 24
Finished Jul 18 07:26:44 PM PDT 24
Peak memory 218760 kb
Host smart-38d72559-b4f8-4f0e-8f9e-8a4fb57be478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636896130 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.2636896130
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.1159493125
Short name T316
Test name
Test status
Simulation time 60793082 ps
CPU time 1.4 seconds
Started Jul 18 07:26:33 PM PDT 24
Finished Jul 18 07:26:42 PM PDT 24
Peak memory 219024 kb
Host smart-407a0d70-973b-4305-a1cb-de0e0999dca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159493125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.1159493125
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.1504058891
Short name T531
Test name
Test status
Simulation time 74220211 ps
CPU time 1.21 seconds
Started Jul 18 07:26:33 PM PDT 24
Finished Jul 18 07:26:41 PM PDT 24
Peak memory 219944 kb
Host smart-014d0ced-ac02-4d4f-860e-8f8aee409a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504058891 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.1504058891
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.2838925158
Short name T655
Test name
Test status
Simulation time 51611489 ps
CPU time 1.22 seconds
Started Jul 18 07:26:34 PM PDT 24
Finished Jul 18 07:26:44 PM PDT 24
Peak memory 218640 kb
Host smart-56f5c525-f36c-460b-9d3c-11734f2194bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838925158 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2838925158
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.1352247138
Short name T926
Test name
Test status
Simulation time 82427863 ps
CPU time 1.16 seconds
Started Jul 18 07:26:32 PM PDT 24
Finished Jul 18 07:26:38 PM PDT 24
Peak memory 220528 kb
Host smart-f5441102-8228-4bfc-94ca-6fd0ea7e9012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352247138 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.1352247138
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.570389672
Short name T303
Test name
Test status
Simulation time 36661339 ps
CPU time 1.15 seconds
Started Jul 18 07:26:32 PM PDT 24
Finished Jul 18 07:26:38 PM PDT 24
Peak memory 217396 kb
Host smart-a1013098-e23d-49c6-a8f0-6bba52fff1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570389672 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.570389672
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.2143775227
Short name T136
Test name
Test status
Simulation time 23691897 ps
CPU time 1.23 seconds
Started Jul 18 07:26:29 PM PDT 24
Finished Jul 18 07:26:32 PM PDT 24
Peak memory 221152 kb
Host smart-26c8e2b9-6d89-49fc-b046-006158440634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143775227 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.2143775227
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.951684829
Short name T993
Test name
Test status
Simulation time 32425511 ps
CPU time 1.39 seconds
Started Jul 18 07:26:34 PM PDT 24
Finished Jul 18 07:26:43 PM PDT 24
Peak memory 218824 kb
Host smart-df945027-d2be-492e-951a-5b1604bde62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951684829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.951684829
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.3707894969
Short name T757
Test name
Test status
Simulation time 30617780 ps
CPU time 1.28 seconds
Started Jul 18 07:26:33 PM PDT 24
Finished Jul 18 07:26:40 PM PDT 24
Peak memory 220556 kb
Host smart-1cc2faf1-2b2f-444c-bd4a-3867d290dd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707894969 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.3707894969
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.3897355036
Short name T734
Test name
Test status
Simulation time 41211550 ps
CPU time 1.42 seconds
Started Jul 18 07:26:33 PM PDT 24
Finished Jul 18 07:26:42 PM PDT 24
Peak memory 220132 kb
Host smart-094b6d71-6bad-4a9d-8f87-916a0d0b9075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897355036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3897355036
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.2590339445
Short name T951
Test name
Test status
Simulation time 22939598 ps
CPU time 1.17 seconds
Started Jul 18 07:26:33 PM PDT 24
Finished Jul 18 07:26:42 PM PDT 24
Peak memory 220200 kb
Host smart-aa797b55-06a1-4b18-aea2-d06eb033cb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590339445 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.2590339445
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.2939423478
Short name T327
Test name
Test status
Simulation time 86283116 ps
CPU time 1.19 seconds
Started Jul 18 07:26:34 PM PDT 24
Finished Jul 18 07:26:44 PM PDT 24
Peak memory 215616 kb
Host smart-96792849-bf7e-4857-9f76-57d357f4f199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939423478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.2939423478
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.1638070355
Short name T366
Test name
Test status
Simulation time 101593217 ps
CPU time 1.11 seconds
Started Jul 18 07:23:17 PM PDT 24
Finished Jul 18 07:23:19 PM PDT 24
Peak memory 219884 kb
Host smart-be82de48-152a-4e26-9b4d-736967fdb30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638070355 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.1638070355
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.3754622403
Short name T625
Test name
Test status
Simulation time 17086051 ps
CPU time 0.96 seconds
Started Jul 18 07:23:18 PM PDT 24
Finished Jul 18 07:23:21 PM PDT 24
Peak memory 207172 kb
Host smart-1c2667a2-abb8-48a0-962d-687c0aa48c6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754622403 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3754622403
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.4177149060
Short name T82
Test name
Test status
Simulation time 12518099 ps
CPU time 0.9 seconds
Started Jul 18 07:23:17 PM PDT 24
Finished Jul 18 07:23:19 PM PDT 24
Peak memory 216576 kb
Host smart-c0a04eee-5272-4a4c-9658-e0c1b6ee678f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177149060 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.4177149060
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.2036189124
Short name T199
Test name
Test status
Simulation time 133915229 ps
CPU time 1.28 seconds
Started Jul 18 07:23:18 PM PDT 24
Finished Jul 18 07:23:22 PM PDT 24
Peak memory 217032 kb
Host smart-eaf481c2-fce6-4c0f-a265-658d55badbe8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036189124 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.2036189124
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.2456008213
Short name T434
Test name
Test status
Simulation time 18018114 ps
CPU time 1.07 seconds
Started Jul 18 07:23:18 PM PDT 24
Finished Jul 18 07:23:21 PM PDT 24
Peak memory 218852 kb
Host smart-d567d33f-fa60-4f67-8bc5-9b1e1d706f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456008213 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.2456008213
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.2968281801
Short name T712
Test name
Test status
Simulation time 66775324 ps
CPU time 1.52 seconds
Started Jul 18 07:23:20 PM PDT 24
Finished Jul 18 07:23:26 PM PDT 24
Peak memory 217656 kb
Host smart-1a80245a-bb27-4d1e-b9ed-824891289006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968281801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.2968281801
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3232950119
Short name T893
Test name
Test status
Simulation time 71539977 ps
CPU time 0.9 seconds
Started Jul 18 07:23:17 PM PDT 24
Finished Jul 18 07:23:20 PM PDT 24
Peak memory 224180 kb
Host smart-946ffad5-587e-4a27-a531-94b88b499a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232950119 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3232950119
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.654183990
Short name T387
Test name
Test status
Simulation time 15286529 ps
CPU time 1.03 seconds
Started Jul 18 07:23:18 PM PDT 24
Finished Jul 18 07:23:21 PM PDT 24
Peak memory 215580 kb
Host smart-3a5c9f5e-17fe-45d6-9252-1df1a55e9cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654183990 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.654183990
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.1116524272
Short name T229
Test name
Test status
Simulation time 56877971820 ps
CPU time 1232.62 seconds
Started Jul 18 07:23:16 PM PDT 24
Finished Jul 18 07:43:49 PM PDT 24
Peak memory 221480 kb
Host smart-e2e422ac-a9fc-4670-90f8-5f29d4f258da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116524272 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.1116524272
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.1992269154
Short name T879
Test name
Test status
Simulation time 34695502 ps
CPU time 1.31 seconds
Started Jul 18 07:26:33 PM PDT 24
Finished Jul 18 07:26:41 PM PDT 24
Peak memory 216040 kb
Host smart-942ec0c2-1376-4776-917d-147e7d46681d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992269154 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.1992269154
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.674203086
Short name T754
Test name
Test status
Simulation time 63991272 ps
CPU time 1.27 seconds
Started Jul 18 07:26:32 PM PDT 24
Finished Jul 18 07:26:38 PM PDT 24
Peak memory 217704 kb
Host smart-a448e3db-6249-45e2-b9e5-2812334e9bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674203086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.674203086
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.2033545002
Short name T176
Test name
Test status
Simulation time 28695456 ps
CPU time 1.18 seconds
Started Jul 18 07:26:34 PM PDT 24
Finished Jul 18 07:26:42 PM PDT 24
Peak memory 219056 kb
Host smart-38efdbd6-4e2f-49f8-a1f7-654c3b4d1580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033545002 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.2033545002
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.4040340021
Short name T501
Test name
Test status
Simulation time 58600635 ps
CPU time 0.99 seconds
Started Jul 18 07:26:34 PM PDT 24
Finished Jul 18 07:26:43 PM PDT 24
Peak memory 217624 kb
Host smart-3c0590ae-7bc1-4516-85b4-d71798857a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040340021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.4040340021
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.3510132813
Short name T687
Test name
Test status
Simulation time 24219764 ps
CPU time 1.17 seconds
Started Jul 18 07:26:34 PM PDT 24
Finished Jul 18 07:26:42 PM PDT 24
Peak memory 221332 kb
Host smart-673ef829-8705-4a3b-a021-7477fcc7d5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510132813 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.3510132813
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.1316464070
Short name T467
Test name
Test status
Simulation time 104081749 ps
CPU time 1.27 seconds
Started Jul 18 07:26:34 PM PDT 24
Finished Jul 18 07:26:43 PM PDT 24
Peak memory 217500 kb
Host smart-1db05bfa-8097-45be-bf63-31dba782918f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316464070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.1316464070
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.2574515364
Short name T843
Test name
Test status
Simulation time 101876504 ps
CPU time 1.33 seconds
Started Jul 18 07:26:36 PM PDT 24
Finished Jul 18 07:26:46 PM PDT 24
Peak memory 220492 kb
Host smart-35208a88-3409-4f6f-9453-fa5ec59d35a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574515364 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.2574515364
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.82962721
Short name T468
Test name
Test status
Simulation time 170932651 ps
CPU time 1.58 seconds
Started Jul 18 07:26:35 PM PDT 24
Finished Jul 18 07:26:44 PM PDT 24
Peak memory 219316 kb
Host smart-5f2c38ea-f8c7-4b07-a2c5-dfbb0a63edc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82962721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.82962721
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.1213992733
Short name T944
Test name
Test status
Simulation time 115891524 ps
CPU time 1.25 seconds
Started Jul 18 07:26:36 PM PDT 24
Finished Jul 18 07:26:45 PM PDT 24
Peak memory 218976 kb
Host smart-b57a201c-329b-4703-9862-4a7de7ab6778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213992733 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.1213992733
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.2262493297
Short name T718
Test name
Test status
Simulation time 33511337 ps
CPU time 1.2 seconds
Started Jul 18 07:26:36 PM PDT 24
Finished Jul 18 07:26:46 PM PDT 24
Peak memory 218944 kb
Host smart-115fcd80-6e03-4c0d-8bc3-af368c5549fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262493297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2262493297
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.2031173514
Short name T483
Test name
Test status
Simulation time 25104895 ps
CPU time 1.16 seconds
Started Jul 18 07:26:35 PM PDT 24
Finished Jul 18 07:26:44 PM PDT 24
Peak memory 219132 kb
Host smart-93ff137b-f974-4ee8-9ef3-9da6079e70da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031173514 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.2031173514
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.2383221275
Short name T565
Test name
Test status
Simulation time 82752132 ps
CPU time 1 seconds
Started Jul 18 07:26:35 PM PDT 24
Finished Jul 18 07:26:45 PM PDT 24
Peak memory 217408 kb
Host smart-5367e5fc-5778-4dbb-8639-b071c7ba2551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383221275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.2383221275
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.1161655838
Short name T917
Test name
Test status
Simulation time 187996791 ps
CPU time 1.26 seconds
Started Jul 18 07:26:37 PM PDT 24
Finished Jul 18 07:26:46 PM PDT 24
Peak memory 218828 kb
Host smart-02ec4b64-77b9-49c2-b2ad-58fb942a8c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161655838 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.1161655838
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.1988125336
Short name T885
Test name
Test status
Simulation time 29695995 ps
CPU time 1.28 seconds
Started Jul 18 07:26:36 PM PDT 24
Finished Jul 18 07:26:46 PM PDT 24
Peak memory 217864 kb
Host smart-74e3f393-818f-4f02-a78a-4eeae18b8e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988125336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.1988125336
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.4135962060
Short name T289
Test name
Test status
Simulation time 144731052 ps
CPU time 1.19 seconds
Started Jul 18 07:26:35 PM PDT 24
Finished Jul 18 07:26:45 PM PDT 24
Peak memory 220396 kb
Host smart-e05d26a1-d158-4165-8336-3c429af3ccc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135962060 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.4135962060
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.2910440946
Short name T759
Test name
Test status
Simulation time 76192040 ps
CPU time 1.37 seconds
Started Jul 18 07:26:37 PM PDT 24
Finished Jul 18 07:26:46 PM PDT 24
Peak memory 215572 kb
Host smart-d402b4ff-d101-4b86-996f-bcc14114d266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910440946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.2910440946
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.3749123164
Short name T889
Test name
Test status
Simulation time 88425942 ps
CPU time 1.43 seconds
Started Jul 18 07:26:36 PM PDT 24
Finished Jul 18 07:26:46 PM PDT 24
Peak memory 219020 kb
Host smart-291db6f2-47fb-4202-8f5a-17eaaffcaedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749123164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.3749123164
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.3381761353
Short name T591
Test name
Test status
Simulation time 45121500 ps
CPU time 1.2 seconds
Started Jul 18 07:26:36 PM PDT 24
Finished Jul 18 07:26:46 PM PDT 24
Peak memory 219064 kb
Host smart-1abb7830-5926-465b-8804-542ff5e5b479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381761353 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.3381761353
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.4196140898
Short name T898
Test name
Test status
Simulation time 90782184 ps
CPU time 1.99 seconds
Started Jul 18 07:26:36 PM PDT 24
Finished Jul 18 07:26:46 PM PDT 24
Peak memory 220552 kb
Host smart-168213a4-11ad-4830-96a4-1a3a453e5ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196140898 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.4196140898
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.2322009680
Short name T481
Test name
Test status
Simulation time 271857545 ps
CPU time 1.25 seconds
Started Jul 18 07:21:30 PM PDT 24
Finished Jul 18 07:21:36 PM PDT 24
Peak memory 218844 kb
Host smart-6038cbf1-a3b9-44d0-a5d9-939bf520d186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322009680 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.2322009680
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.3975411944
Short name T948
Test name
Test status
Simulation time 48288364 ps
CPU time 0.94 seconds
Started Jul 18 07:21:27 PM PDT 24
Finished Jul 18 07:21:32 PM PDT 24
Peak memory 207068 kb
Host smart-e293b059-7155-4b37-830b-fa4d5d1bead5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975411944 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3975411944
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.2516028323
Short name T157
Test name
Test status
Simulation time 31718691 ps
CPU time 0.84 seconds
Started Jul 18 07:21:30 PM PDT 24
Finished Jul 18 07:21:36 PM PDT 24
Peak memory 216600 kb
Host smart-a1ae630e-1587-4b77-8043-d6d2a38eaf82
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516028323 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2516028323
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_err.4208362990
Short name T163
Test name
Test status
Simulation time 23218932 ps
CPU time 1.06 seconds
Started Jul 18 07:21:30 PM PDT 24
Finished Jul 18 07:21:36 PM PDT 24
Peak memory 224300 kb
Host smart-d7847adf-95db-49fe-8c64-130ddbf82997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208362990 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.4208362990
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.1382851392
Short name T857
Test name
Test status
Simulation time 119215381 ps
CPU time 2.56 seconds
Started Jul 18 07:21:28 PM PDT 24
Finished Jul 18 07:21:35 PM PDT 24
Peak memory 220136 kb
Host smart-94570fa1-bdf7-47a3-92f2-9009896dbc39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382851392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1382851392
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.3481237998
Short name T32
Test name
Test status
Simulation time 21069293 ps
CPU time 1.09 seconds
Started Jul 18 07:21:30 PM PDT 24
Finished Jul 18 07:21:36 PM PDT 24
Peak memory 216264 kb
Host smart-7fb7206f-0d4e-4412-9d98-aaec53f60ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481237998 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.3481237998
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.3363967108
Short name T24
Test name
Test status
Simulation time 18158330 ps
CPU time 1.03 seconds
Started Jul 18 07:21:30 PM PDT 24
Finished Jul 18 07:21:36 PM PDT 24
Peak memory 207368 kb
Host smart-b7ad1b69-d11a-4eae-9822-a28a32c8c6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363967108 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3363967108
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.1922229199
Short name T63
Test name
Test status
Simulation time 6907591302 ps
CPU time 10.29 seconds
Started Jul 18 07:21:28 PM PDT 24
Finished Jul 18 07:21:43 PM PDT 24
Peak memory 239508 kb
Host smart-2289c0dd-c44a-487c-b683-6c2510af0e66
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922229199 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1922229199
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.2355309513
Short name T458
Test name
Test status
Simulation time 44722612 ps
CPU time 0.94 seconds
Started Jul 18 07:21:32 PM PDT 24
Finished Jul 18 07:21:38 PM PDT 24
Peak memory 215552 kb
Host smart-409ee2e2-b605-47a3-a13d-61d104fac88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355309513 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.2355309513
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.1522752295
Short name T526
Test name
Test status
Simulation time 122217409 ps
CPU time 2.74 seconds
Started Jul 18 07:21:28 PM PDT 24
Finished Jul 18 07:21:36 PM PDT 24
Peak memory 217452 kb
Host smart-2f0880ed-cc9a-4ceb-b16b-41a86fb9c2b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522752295 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.1522752295
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.375615995
Short name T219
Test name
Test status
Simulation time 995296351008 ps
CPU time 1851.92 seconds
Started Jul 18 07:21:28 PM PDT 24
Finished Jul 18 07:52:25 PM PDT 24
Peak memory 225528 kb
Host smart-831f3637-4fff-4f29-a882-e849fffe4d84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375615995 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.375615995
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.3055887978
Short name T624
Test name
Test status
Simulation time 81142617 ps
CPU time 1.16 seconds
Started Jul 18 07:23:18 PM PDT 24
Finished Jul 18 07:23:22 PM PDT 24
Peak memory 220164 kb
Host smart-5ce84a6f-d0f2-4b86-baa0-4df4191926c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055887978 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.3055887978
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.3950504656
Short name T551
Test name
Test status
Simulation time 32697299 ps
CPU time 1 seconds
Started Jul 18 07:23:20 PM PDT 24
Finished Jul 18 07:23:24 PM PDT 24
Peak memory 215220 kb
Host smart-86f2f58f-c1aa-4a41-83c1-1cd6d2b7ad62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950504656 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.3950504656
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.692884271
Short name T912
Test name
Test status
Simulation time 104611608 ps
CPU time 0.86 seconds
Started Jul 18 07:23:18 PM PDT 24
Finished Jul 18 07:23:22 PM PDT 24
Peak memory 216488 kb
Host smart-737fd054-3311-47cc-b091-c1693a8c1e94
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692884271 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.692884271
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.954881324
Short name T196
Test name
Test status
Simulation time 67229212 ps
CPU time 1.1 seconds
Started Jul 18 07:23:19 PM PDT 24
Finished Jul 18 07:23:24 PM PDT 24
Peak memory 217220 kb
Host smart-43224216-5986-4d6c-99c9-239fa6ff3fa5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954881324 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_di
sable_auto_req_mode.954881324
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.2480010225
Short name T198
Test name
Test status
Simulation time 19457821 ps
CPU time 0.98 seconds
Started Jul 18 07:23:17 PM PDT 24
Finished Jul 18 07:23:19 PM PDT 24
Peak memory 218812 kb
Host smart-e693dbb5-6edb-471b-9bec-19c21a2ad2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480010225 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2480010225
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.535913267
Short name T562
Test name
Test status
Simulation time 46323389 ps
CPU time 1.19 seconds
Started Jul 18 07:23:19 PM PDT 24
Finished Jul 18 07:23:24 PM PDT 24
Peak memory 217612 kb
Host smart-ea96c25e-c569-48bb-a02d-f2a94bfc5a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535913267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.535913267
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.1514538529
Short name T187
Test name
Test status
Simulation time 23519700 ps
CPU time 1.01 seconds
Started Jul 18 07:23:16 PM PDT 24
Finished Jul 18 07:23:19 PM PDT 24
Peak memory 215760 kb
Host smart-4bb811d4-f425-45c0-a2ba-68c735975606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514538529 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1514538529
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.2768720762
Short name T424
Test name
Test status
Simulation time 23484449 ps
CPU time 0.95 seconds
Started Jul 18 07:23:17 PM PDT 24
Finished Jul 18 07:23:20 PM PDT 24
Peak memory 215544 kb
Host smart-ff78b754-e691-4786-a99c-99dcbb9b752a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768720762 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.2768720762
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.3030789131
Short name T359
Test name
Test status
Simulation time 415749786 ps
CPU time 8.02 seconds
Started Jul 18 07:23:18 PM PDT 24
Finished Jul 18 07:23:29 PM PDT 24
Peak memory 217864 kb
Host smart-123db730-170e-4c16-a047-16cc4e1efcf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030789131 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3030789131
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2117880691
Short name T618
Test name
Test status
Simulation time 295908402313 ps
CPU time 865.96 seconds
Started Jul 18 07:23:18 PM PDT 24
Finished Jul 18 07:37:47 PM PDT 24
Peak memory 222492 kb
Host smart-308e4986-3382-42a5-9022-9f7c440fe365
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117880691 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.2117880691
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.106038431
Short name T820
Test name
Test status
Simulation time 37480961 ps
CPU time 1.5 seconds
Started Jul 18 07:26:37 PM PDT 24
Finished Jul 18 07:26:46 PM PDT 24
Peak memory 217752 kb
Host smart-8821c65f-ad79-4c2e-8817-2884f8a1949f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106038431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.106038431
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.1465896451
Short name T550
Test name
Test status
Simulation time 63040100 ps
CPU time 2.14 seconds
Started Jul 18 07:26:39 PM PDT 24
Finished Jul 18 07:26:48 PM PDT 24
Peak memory 220268 kb
Host smart-c027102c-7e4b-4e4c-ac2d-50bac55ad049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465896451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.1465896451
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.476474863
Short name T349
Test name
Test status
Simulation time 51927286 ps
CPU time 1.38 seconds
Started Jul 18 07:26:36 PM PDT 24
Finished Jul 18 07:26:46 PM PDT 24
Peak memory 217532 kb
Host smart-85b868f1-ebe9-44b1-9f18-da6f52937423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476474863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.476474863
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.21102311
Short name T235
Test name
Test status
Simulation time 47366555 ps
CPU time 1.6 seconds
Started Jul 18 07:26:33 PM PDT 24
Finished Jul 18 07:26:41 PM PDT 24
Peak memory 215576 kb
Host smart-111e408a-fe30-49e0-b298-b4cb2ad72142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21102311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.21102311
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.662245175
Short name T340
Test name
Test status
Simulation time 32875456 ps
CPU time 1.3 seconds
Started Jul 18 07:26:33 PM PDT 24
Finished Jul 18 07:26:41 PM PDT 24
Peak memory 218912 kb
Host smart-279dcd65-d7f1-4267-9010-3dcc2bf5f79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662245175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.662245175
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.1039122664
Short name T684
Test name
Test status
Simulation time 31400042 ps
CPU time 1.4 seconds
Started Jul 18 07:26:39 PM PDT 24
Finished Jul 18 07:26:47 PM PDT 24
Peak memory 218724 kb
Host smart-5c2d9a68-72e0-4058-b68d-7772dc97bd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039122664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1039122664
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.1658204827
Short name T48
Test name
Test status
Simulation time 70179874 ps
CPU time 1.25 seconds
Started Jul 18 07:26:39 PM PDT 24
Finished Jul 18 07:26:47 PM PDT 24
Peak memory 220028 kb
Host smart-a267a9f8-f38d-41a5-bd1e-7f592cab8a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658204827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.1658204827
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.2834650871
Short name T569
Test name
Test status
Simulation time 225249985 ps
CPU time 1.14 seconds
Started Jul 18 07:26:34 PM PDT 24
Finished Jul 18 07:26:44 PM PDT 24
Peak memory 217536 kb
Host smart-db154e3e-5ade-4649-8bcc-f4325a36a0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834650871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.2834650871
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.325304847
Short name T628
Test name
Test status
Simulation time 39189737 ps
CPU time 1.49 seconds
Started Jul 18 07:26:37 PM PDT 24
Finished Jul 18 07:26:46 PM PDT 24
Peak memory 218624 kb
Host smart-50adf3f6-e13a-4ac1-8c75-586e19996451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325304847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.325304847
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.3860795634
Short name T747
Test name
Test status
Simulation time 59635934 ps
CPU time 1.28 seconds
Started Jul 18 07:26:39 PM PDT 24
Finished Jul 18 07:26:47 PM PDT 24
Peak memory 217420 kb
Host smart-a203e8e5-0ba5-4ba0-baa2-eb5d09921dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860795634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.3860795634
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3872818846
Short name T981
Test name
Test status
Simulation time 87607776 ps
CPU time 1.23 seconds
Started Jul 18 07:23:18 PM PDT 24
Finished Jul 18 07:23:22 PM PDT 24
Peak memory 218732 kb
Host smart-4b3facf8-3343-4e20-9b43-15cb2ac41fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872818846 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3872818846
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.3098225272
Short name T673
Test name
Test status
Simulation time 45740540 ps
CPU time 0.89 seconds
Started Jul 18 07:23:19 PM PDT 24
Finished Jul 18 07:23:23 PM PDT 24
Peak memory 215348 kb
Host smart-b30249f0-88c2-4dc5-a6f0-d0f4b08faab2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098225272 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.3098225272
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.3534205305
Short name T78
Test name
Test status
Simulation time 20945730 ps
CPU time 0.89 seconds
Started Jul 18 07:23:20 PM PDT 24
Finished Jul 18 07:23:25 PM PDT 24
Peak memory 216536 kb
Host smart-df28e1ab-13cf-43a6-852c-8337b92a4889
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534205305 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.3534205305
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.2618449685
Short name T931
Test name
Test status
Simulation time 30979401 ps
CPU time 1.09 seconds
Started Jul 18 07:23:19 PM PDT 24
Finished Jul 18 07:23:23 PM PDT 24
Peak memory 218528 kb
Host smart-41cfac85-6c43-4601-81f7-d0fd2f1c5d4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618449685 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.2618449685
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.2132478636
Short name T463
Test name
Test status
Simulation time 21419689 ps
CPU time 0.91 seconds
Started Jul 18 07:23:20 PM PDT 24
Finished Jul 18 07:23:25 PM PDT 24
Peak memory 218980 kb
Host smart-206c3d38-7d92-4eaf-ba18-0a1997b950a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132478636 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.2132478636
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.3299339658
Short name T768
Test name
Test status
Simulation time 36031046 ps
CPU time 1.35 seconds
Started Jul 18 07:23:19 PM PDT 24
Finished Jul 18 07:23:24 PM PDT 24
Peak memory 218700 kb
Host smart-f1b60e08-130d-42b7-b14a-39dc057c8f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299339658 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.3299339658
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.1307977929
Short name T945
Test name
Test status
Simulation time 30090636 ps
CPU time 0.92 seconds
Started Jul 18 07:23:18 PM PDT 24
Finished Jul 18 07:23:21 PM PDT 24
Peak memory 216248 kb
Host smart-2ea256bf-a78f-4678-9e52-5de2bb9d0cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307977929 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.1307977929
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.3532245876
Short name T605
Test name
Test status
Simulation time 24355353 ps
CPU time 0.91 seconds
Started Jul 18 07:23:18 PM PDT 24
Finished Jul 18 07:23:22 PM PDT 24
Peak memory 215568 kb
Host smart-6197f216-1d18-4110-8436-70dcfa5e8dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532245876 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.3532245876
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.4003152503
Short name T978
Test name
Test status
Simulation time 209698104 ps
CPU time 2.84 seconds
Started Jul 18 07:23:20 PM PDT 24
Finished Jul 18 07:23:27 PM PDT 24
Peak memory 219968 kb
Host smart-3bcdddfd-c1a7-493c-96cf-012ff37c8103
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003152503 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.4003152503
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.168603417
Short name T504
Test name
Test status
Simulation time 28916695585 ps
CPU time 486.05 seconds
Started Jul 18 07:23:18 PM PDT 24
Finished Jul 18 07:31:27 PM PDT 24
Peak memory 223948 kb
Host smart-fef01267-fd15-4e8f-80a2-7eceedebff92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168603417 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.168603417
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.24922955
Short name T469
Test name
Test status
Simulation time 71857160 ps
CPU time 1.11 seconds
Started Jul 18 07:26:33 PM PDT 24
Finished Jul 18 07:26:42 PM PDT 24
Peak memory 217788 kb
Host smart-d8c5e786-24b2-4c91-b397-96ac4f912c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24922955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.24922955
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.3515271664
Short name T232
Test name
Test status
Simulation time 56555954 ps
CPU time 1.49 seconds
Started Jul 18 07:26:32 PM PDT 24
Finished Jul 18 07:26:38 PM PDT 24
Peak memory 218780 kb
Host smart-a3a1a8b0-322e-4947-b033-8fac43f82992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515271664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.3515271664
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.868228423
Short name T853
Test name
Test status
Simulation time 41716741 ps
CPU time 1.49 seconds
Started Jul 18 07:26:47 PM PDT 24
Finished Jul 18 07:26:53 PM PDT 24
Peak memory 218876 kb
Host smart-80147aae-1eaa-4624-bb29-1a3a8bbceac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868228423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.868228423
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3688722238
Short name T523
Test name
Test status
Simulation time 69735232 ps
CPU time 1.4 seconds
Started Jul 18 07:26:49 PM PDT 24
Finished Jul 18 07:26:55 PM PDT 24
Peak memory 219012 kb
Host smart-7c9f55d5-e13b-49ed-b3e1-37a475b11107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688722238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3688722238
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.4269632649
Short name T634
Test name
Test status
Simulation time 67745693 ps
CPU time 1.81 seconds
Started Jul 18 07:26:45 PM PDT 24
Finished Jul 18 07:26:52 PM PDT 24
Peak memory 220368 kb
Host smart-b74cd47c-ba02-4ca7-a165-befdaf52435b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269632649 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.4269632649
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.3910335059
Short name T95
Test name
Test status
Simulation time 34266657 ps
CPU time 1.33 seconds
Started Jul 18 07:26:51 PM PDT 24
Finished Jul 18 07:26:56 PM PDT 24
Peak memory 217600 kb
Host smart-db86be8b-801f-4301-9be6-91c20ba21119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910335059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.3910335059
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.1742981842
Short name T75
Test name
Test status
Simulation time 61859656 ps
CPU time 1.15 seconds
Started Jul 18 07:26:45 PM PDT 24
Finished Jul 18 07:26:51 PM PDT 24
Peak memory 217696 kb
Host smart-f15610f2-a5cc-4294-8e19-22d92f4d27e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742981842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1742981842
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.2682889514
Short name T471
Test name
Test status
Simulation time 83499277 ps
CPU time 1.41 seconds
Started Jul 18 07:26:52 PM PDT 24
Finished Jul 18 07:26:57 PM PDT 24
Peak memory 219112 kb
Host smart-480b312e-7ce1-4d06-8a94-d7d5c3bb84f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682889514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.2682889514
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.549538946
Short name T619
Test name
Test status
Simulation time 57594338 ps
CPU time 1.3 seconds
Started Jul 18 07:26:46 PM PDT 24
Finished Jul 18 07:26:52 PM PDT 24
Peak memory 219992 kb
Host smart-99be9493-b791-4334-8631-c2856eb5b28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549538946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.549538946
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.3472950153
Short name T645
Test name
Test status
Simulation time 41600738 ps
CPU time 1.23 seconds
Started Jul 18 07:26:45 PM PDT 24
Finished Jul 18 07:26:51 PM PDT 24
Peak memory 220256 kb
Host smart-ef72f9a5-4330-432a-b836-ea56e2d0fb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472950153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.3472950153
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.1071744554
Short name T924
Test name
Test status
Simulation time 29609054 ps
CPU time 1.38 seconds
Started Jul 18 07:23:20 PM PDT 24
Finished Jul 18 07:23:26 PM PDT 24
Peak memory 218924 kb
Host smart-ddd9c186-19e8-4c49-9f2a-7c26f3280b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071744554 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.1071744554
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.1252083850
Short name T722
Test name
Test status
Simulation time 31307346 ps
CPU time 0.92 seconds
Started Jul 18 07:23:22 PM PDT 24
Finished Jul 18 07:23:27 PM PDT 24
Peak memory 207056 kb
Host smart-9b193e88-7820-4ca9-9945-e71191f0869b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252083850 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1252083850
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.2808430556
Short name T810
Test name
Test status
Simulation time 26670318 ps
CPU time 1.12 seconds
Started Jul 18 07:23:20 PM PDT 24
Finished Jul 18 07:23:26 PM PDT 24
Peak memory 218636 kb
Host smart-2eb125f2-4213-4b51-ba3a-117c640a5c70
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808430556 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.2808430556
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.1323201804
Short name T137
Test name
Test status
Simulation time 23708599 ps
CPU time 0.98 seconds
Started Jul 18 07:23:22 PM PDT 24
Finished Jul 18 07:23:27 PM PDT 24
Peak memory 219128 kb
Host smart-c698a795-7d4f-4ccc-934c-aed2273d3796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323201804 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.1323201804
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.3613516122
Short name T801
Test name
Test status
Simulation time 39721671 ps
CPU time 1.42 seconds
Started Jul 18 07:23:20 PM PDT 24
Finished Jul 18 07:23:24 PM PDT 24
Peak memory 218980 kb
Host smart-2b95f30e-e551-4a03-aca4-3ab29b71b94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613516122 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.3613516122
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.3477196954
Short name T503
Test name
Test status
Simulation time 56305439 ps
CPU time 0.89 seconds
Started Jul 18 07:23:19 PM PDT 24
Finished Jul 18 07:23:23 PM PDT 24
Peak memory 215632 kb
Host smart-bcd80026-108f-4ac7-99a0-989f1b39fdc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477196954 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.3477196954
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.67904211
Short name T510
Test name
Test status
Simulation time 27238810 ps
CPU time 1.03 seconds
Started Jul 18 07:23:19 PM PDT 24
Finished Jul 18 07:23:24 PM PDT 24
Peak memory 215544 kb
Host smart-3e3805a3-e694-4176-8a62-49ffd8d6991f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67904211 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.67904211
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2349887046
Short name T572
Test name
Test status
Simulation time 180853836 ps
CPU time 3.88 seconds
Started Jul 18 07:23:20 PM PDT 24
Finished Jul 18 07:23:28 PM PDT 24
Peak memory 215612 kb
Host smart-a815d8c8-c607-425e-b3d2-d200d26d2ff4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349887046 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2349887046
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3194689205
Short name T676
Test name
Test status
Simulation time 105896209757 ps
CPU time 1387.78 seconds
Started Jul 18 07:23:22 PM PDT 24
Finished Jul 18 07:46:34 PM PDT 24
Peak memory 226516 kb
Host smart-7620c6e4-25ac-4656-afdb-7f59131f987b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194689205 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3194689205
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.2567021063
Short name T913
Test name
Test status
Simulation time 316516502 ps
CPU time 1.23 seconds
Started Jul 18 07:26:49 PM PDT 24
Finished Jul 18 07:26:55 PM PDT 24
Peak memory 217560 kb
Host smart-a6db1e37-a491-4e9b-89d4-aa7833d46752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567021063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.2567021063
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.3136328569
Short name T9
Test name
Test status
Simulation time 44068467 ps
CPU time 1.57 seconds
Started Jul 18 07:26:48 PM PDT 24
Finished Jul 18 07:26:54 PM PDT 24
Peak memory 220104 kb
Host smart-3f3075d4-e0b3-4f35-824c-fdb673711fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136328569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3136328569
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.2167716842
Short name T383
Test name
Test status
Simulation time 59463227 ps
CPU time 1.39 seconds
Started Jul 18 07:26:47 PM PDT 24
Finished Jul 18 07:26:52 PM PDT 24
Peak memory 219072 kb
Host smart-ec834a3f-8e36-4b8f-9ed0-68ddfdebcb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167716842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.2167716842
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.1566216542
Short name T727
Test name
Test status
Simulation time 41071315 ps
CPU time 1.14 seconds
Started Jul 18 07:26:49 PM PDT 24
Finished Jul 18 07:26:55 PM PDT 24
Peak memory 217560 kb
Host smart-86ab05da-6c3c-4601-a31a-09fcf13c7969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566216542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.1566216542
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.1409526982
Short name T439
Test name
Test status
Simulation time 70886308 ps
CPU time 2.61 seconds
Started Jul 18 07:26:50 PM PDT 24
Finished Jul 18 07:26:58 PM PDT 24
Peak memory 218820 kb
Host smart-7e233ee8-c318-4bd0-b6f9-0eefd944b1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409526982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.1409526982
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.3210592593
Short name T855
Test name
Test status
Simulation time 75827725 ps
CPU time 2.63 seconds
Started Jul 18 07:26:50 PM PDT 24
Finished Jul 18 07:26:57 PM PDT 24
Peak memory 220448 kb
Host smart-9a2316ae-dd4f-4ffc-9dbf-963563755aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210592593 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3210592593
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.3616560814
Short name T909
Test name
Test status
Simulation time 58382079 ps
CPU time 1.24 seconds
Started Jul 18 07:26:44 PM PDT 24
Finished Jul 18 07:26:50 PM PDT 24
Peak memory 217452 kb
Host smart-3cd78842-ca4f-4036-8beb-aa839a68bd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616560814 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3616560814
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.360440828
Short name T840
Test name
Test status
Simulation time 97100586 ps
CPU time 1.99 seconds
Started Jul 18 07:26:47 PM PDT 24
Finished Jul 18 07:26:53 PM PDT 24
Peak memory 215572 kb
Host smart-9b5e54fc-8ab7-4b70-9fe3-62ceb8b25336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360440828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.360440828
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.1591824342
Short name T704
Test name
Test status
Simulation time 92640683 ps
CPU time 1.52 seconds
Started Jul 18 07:26:50 PM PDT 24
Finished Jul 18 07:26:56 PM PDT 24
Peak memory 219180 kb
Host smart-21b2506c-0d48-49f3-89a2-ea6b13e1fb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591824342 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1591824342
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.35350861
Short name T941
Test name
Test status
Simulation time 44549723 ps
CPU time 1.19 seconds
Started Jul 18 07:23:36 PM PDT 24
Finished Jul 18 07:23:40 PM PDT 24
Peak memory 219908 kb
Host smart-ab3a1dc9-a67f-454b-bde4-f49779f8e5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35350861 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.35350861
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.483972347
Short name T949
Test name
Test status
Simulation time 27867486 ps
CPU time 0.96 seconds
Started Jul 18 07:23:38 PM PDT 24
Finished Jul 18 07:23:42 PM PDT 24
Peak memory 215244 kb
Host smart-27e308f6-f37d-4811-9c30-10ddf97f13fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483972347 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.483972347
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.1930863819
Short name T868
Test name
Test status
Simulation time 82394799 ps
CPU time 0.81 seconds
Started Jul 18 07:23:37 PM PDT 24
Finished Jul 18 07:23:41 PM PDT 24
Peak memory 216504 kb
Host smart-c2007f67-3296-4757-b84d-2cdc1b9caa82
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930863819 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.1930863819
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3803945050
Short name T806
Test name
Test status
Simulation time 99465472 ps
CPU time 0.99 seconds
Started Jul 18 07:23:31 PM PDT 24
Finished Jul 18 07:23:33 PM PDT 24
Peak memory 217276 kb
Host smart-618ec8a0-4421-498b-b34c-5891b294ffa8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803945050 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3803945050
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.2893924272
Short name T601
Test name
Test status
Simulation time 39329663 ps
CPU time 0.87 seconds
Started Jul 18 07:23:33 PM PDT 24
Finished Jul 18 07:23:36 PM PDT 24
Peak memory 218468 kb
Host smart-1b86cd31-b26e-43d5-a107-d20f29ded246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893924272 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.2893924272
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.1618481578
Short name T960
Test name
Test status
Simulation time 110956996 ps
CPU time 1.58 seconds
Started Jul 18 07:23:21 PM PDT 24
Finished Jul 18 07:23:27 PM PDT 24
Peak memory 219388 kb
Host smart-b30da8d0-f7df-492d-85f4-1e3d10923970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618481578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.1618481578
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.1940884127
Short name T561
Test name
Test status
Simulation time 40363748 ps
CPU time 0.94 seconds
Started Jul 18 07:23:32 PM PDT 24
Finished Jul 18 07:23:35 PM PDT 24
Peak memory 215748 kb
Host smart-aa9ab75a-badd-456c-8760-ddc8808580d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940884127 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.1940884127
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.1465250928
Short name T741
Test name
Test status
Simulation time 15152423 ps
CPU time 0.98 seconds
Started Jul 18 07:23:22 PM PDT 24
Finished Jul 18 07:23:27 PM PDT 24
Peak memory 215660 kb
Host smart-e5efb9cf-41bc-4046-a777-13ec24053fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465250928 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.1465250928
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.509522975
Short name T341
Test name
Test status
Simulation time 69311493 ps
CPU time 1.32 seconds
Started Jul 18 07:23:20 PM PDT 24
Finished Jul 18 07:23:25 PM PDT 24
Peak memory 217444 kb
Host smart-2faa7966-ab8c-4e53-ac87-d4893e5ff67a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509522975 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.509522975
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2595957241
Short name T743
Test name
Test status
Simulation time 16566325761 ps
CPU time 431.74 seconds
Started Jul 18 07:23:21 PM PDT 24
Finished Jul 18 07:30:37 PM PDT 24
Peak memory 218388 kb
Host smart-a3014834-df1d-4286-8daa-46f8eefff6af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595957241 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2595957241
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.3331939865
Short name T881
Test name
Test status
Simulation time 145761378 ps
CPU time 3.12 seconds
Started Jul 18 07:26:50 PM PDT 24
Finished Jul 18 07:26:58 PM PDT 24
Peak memory 220040 kb
Host smart-ab0866c3-c1cf-47e6-918f-9901f91ac4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331939865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.3331939865
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.3845508691
Short name T350
Test name
Test status
Simulation time 187248286 ps
CPU time 2.4 seconds
Started Jul 18 07:26:47 PM PDT 24
Finished Jul 18 07:26:53 PM PDT 24
Peak memory 220116 kb
Host smart-693c6366-c5a0-47ab-9d5a-1ec5317aa943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845508691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3845508691
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.3049766838
Short name T430
Test name
Test status
Simulation time 177426443 ps
CPU time 1.06 seconds
Started Jul 18 07:26:51 PM PDT 24
Finished Jul 18 07:26:56 PM PDT 24
Peak memory 217632 kb
Host smart-b9f57c99-d3f4-4de6-b092-e3f1f6129d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049766838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.3049766838
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.3426683787
Short name T784
Test name
Test status
Simulation time 46382388 ps
CPU time 1.68 seconds
Started Jul 18 07:26:46 PM PDT 24
Finished Jul 18 07:26:53 PM PDT 24
Peak memory 218584 kb
Host smart-9938f81b-9a9a-4e78-9ce7-2fc21601b017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426683787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3426683787
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.1395701206
Short name T355
Test name
Test status
Simulation time 94100839 ps
CPU time 1.46 seconds
Started Jul 18 07:26:48 PM PDT 24
Finished Jul 18 07:26:54 PM PDT 24
Peak memory 218852 kb
Host smart-318890df-7ea2-4ea1-a5df-c7d480ca0a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395701206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.1395701206
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.98852499
Short name T782
Test name
Test status
Simulation time 71167810 ps
CPU time 1.39 seconds
Started Jul 18 07:26:50 PM PDT 24
Finished Jul 18 07:26:56 PM PDT 24
Peak memory 217636 kb
Host smart-1c8e8313-62f6-4fc5-87a2-ee04dca5e94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98852499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.98852499
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.481807888
Short name T312
Test name
Test status
Simulation time 187195863 ps
CPU time 1.3 seconds
Started Jul 18 07:26:46 PM PDT 24
Finished Jul 18 07:26:52 PM PDT 24
Peak memory 220264 kb
Host smart-8eb16b0f-4ee2-4fc1-b2df-f12b2d677b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481807888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.481807888
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.2372615399
Short name T39
Test name
Test status
Simulation time 40038359 ps
CPU time 1.09 seconds
Started Jul 18 07:26:48 PM PDT 24
Finished Jul 18 07:26:54 PM PDT 24
Peak memory 217624 kb
Host smart-59afceeb-e89d-44d5-a4a2-17524fbc234f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372615399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.2372615399
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.1918633388
Short name T929
Test name
Test status
Simulation time 78489109 ps
CPU time 1.44 seconds
Started Jul 18 07:26:48 PM PDT 24
Finished Jul 18 07:26:54 PM PDT 24
Peak memory 217608 kb
Host smart-4c2345a2-1f92-46d4-ae16-57a8d1765c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918633388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.1918633388
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.128418456
Short name T301
Test name
Test status
Simulation time 188670943 ps
CPU time 2.82 seconds
Started Jul 18 07:26:45 PM PDT 24
Finished Jul 18 07:26:53 PM PDT 24
Peak memory 219688 kb
Host smart-6064af31-6aeb-4049-8ee8-5277948d19c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128418456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.128418456
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.3585133257
Short name T426
Test name
Test status
Simulation time 45656675 ps
CPU time 1.29 seconds
Started Jul 18 07:23:34 PM PDT 24
Finished Jul 18 07:23:38 PM PDT 24
Peak memory 220456 kb
Host smart-a31bd792-e1e6-4750-8ae6-2fc0662c645b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585133257 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.3585133257
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.2398030129
Short name T61
Test name
Test status
Simulation time 40105215 ps
CPU time 1.29 seconds
Started Jul 18 07:23:34 PM PDT 24
Finished Jul 18 07:23:38 PM PDT 24
Peak memory 207156 kb
Host smart-bb3c34ae-59b5-488a-a4a8-20d5b0eea7f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398030129 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.2398030129
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.1154153541
Short name T848
Test name
Test status
Simulation time 13820331 ps
CPU time 0.95 seconds
Started Jul 18 07:23:32 PM PDT 24
Finished Jul 18 07:23:35 PM PDT 24
Peak memory 216776 kb
Host smart-38f73d7e-b52d-46d5-9afd-0de2bada7cde
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154153541 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1154153541
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.3095418818
Short name T643
Test name
Test status
Simulation time 55870576 ps
CPU time 1.18 seconds
Started Jul 18 07:23:32 PM PDT 24
Finished Jul 18 07:23:35 PM PDT 24
Peak memory 220100 kb
Host smart-bc2812a9-be84-4a59-942c-09afab3c7356
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095418818 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.3095418818
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.623237694
Short name T347
Test name
Test status
Simulation time 28350576 ps
CPU time 0.92 seconds
Started Jul 18 07:23:32 PM PDT 24
Finished Jul 18 07:23:34 PM PDT 24
Peak memory 218696 kb
Host smart-0aa9017b-8d57-48e3-9902-67ca3d0e5a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623237694 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.623237694
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.394943035
Short name T384
Test name
Test status
Simulation time 49295080 ps
CPU time 1.22 seconds
Started Jul 18 07:23:31 PM PDT 24
Finished Jul 18 07:23:33 PM PDT 24
Peak memory 219796 kb
Host smart-95cdd357-32e4-4537-8483-935de7448171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394943035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.394943035
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.2343074597
Short name T749
Test name
Test status
Simulation time 20437897 ps
CPU time 1.11 seconds
Started Jul 18 07:23:34 PM PDT 24
Finished Jul 18 07:23:37 PM PDT 24
Peak memory 215844 kb
Host smart-d9aaebf9-004f-4bab-a63a-a2767e3ccac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343074597 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.2343074597
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.2628628262
Short name T548
Test name
Test status
Simulation time 51373637 ps
CPU time 0.93 seconds
Started Jul 18 07:23:31 PM PDT 24
Finished Jul 18 07:23:33 PM PDT 24
Peak memory 215560 kb
Host smart-406b6f33-e258-4dfd-b772-d5c6c3c682a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628628262 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.2628628262
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.912126044
Short name T698
Test name
Test status
Simulation time 199247584 ps
CPU time 4.17 seconds
Started Jul 18 07:23:34 PM PDT 24
Finished Jul 18 07:23:40 PM PDT 24
Peak memory 217660 kb
Host smart-46b39180-0a34-4c1f-ae9a-57e04b65506c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912126044 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.912126044
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.155357343
Short name T230
Test name
Test status
Simulation time 304103674179 ps
CPU time 1727 seconds
Started Jul 18 07:23:33 PM PDT 24
Finished Jul 18 07:52:23 PM PDT 24
Peak memory 225540 kb
Host smart-daf40b01-51d1-478e-8afe-c4df81e7a311
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155357343 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.155357343
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.2747162051
Short name T720
Test name
Test status
Simulation time 77638509 ps
CPU time 1.1 seconds
Started Jul 18 07:26:48 PM PDT 24
Finished Jul 18 07:26:54 PM PDT 24
Peak memory 217540 kb
Host smart-efc02ece-7996-49c8-80a4-9b9c4fd8e9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747162051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.2747162051
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.3200775794
Short name T496
Test name
Test status
Simulation time 127200008 ps
CPU time 1.19 seconds
Started Jul 18 07:26:47 PM PDT 24
Finished Jul 18 07:26:52 PM PDT 24
Peak memory 219092 kb
Host smart-c7e2a480-42db-4d97-b82d-b9d507239610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200775794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.3200775794
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.3479794005
Short name T631
Test name
Test status
Simulation time 60210511 ps
CPU time 1.53 seconds
Started Jul 18 07:26:45 PM PDT 24
Finished Jul 18 07:26:52 PM PDT 24
Peak memory 218760 kb
Host smart-12d326a4-1422-4a25-9eaf-0c3689f63f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479794005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.3479794005
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.1143711674
Short name T380
Test name
Test status
Simulation time 41399461 ps
CPU time 1.09 seconds
Started Jul 18 07:26:48 PM PDT 24
Finished Jul 18 07:26:54 PM PDT 24
Peak memory 217624 kb
Host smart-0d93323f-eacf-4f64-94d6-81d2326ecaff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143711674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.1143711674
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.547937562
Short name T1
Test name
Test status
Simulation time 31224639 ps
CPU time 1.23 seconds
Started Jul 18 07:26:48 PM PDT 24
Finished Jul 18 07:26:53 PM PDT 24
Peak memory 220224 kb
Host smart-109ca6fb-82cf-43c1-9e83-e165ba003e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547937562 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.547937562
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.3257301411
Short name T577
Test name
Test status
Simulation time 143914456 ps
CPU time 1.6 seconds
Started Jul 18 07:26:47 PM PDT 24
Finished Jul 18 07:26:52 PM PDT 24
Peak memory 219068 kb
Host smart-e78f6603-7a2e-45ea-9610-39e2f6c90b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257301411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.3257301411
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.1730486787
Short name T543
Test name
Test status
Simulation time 21483699 ps
CPU time 1.08 seconds
Started Jul 18 07:26:48 PM PDT 24
Finished Jul 18 07:26:53 PM PDT 24
Peak memory 217560 kb
Host smart-57f23d10-3497-445e-9c3a-d30742eb0e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730486787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1730486787
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.3072804530
Short name T746
Test name
Test status
Simulation time 29459956 ps
CPU time 1.17 seconds
Started Jul 18 07:26:48 PM PDT 24
Finished Jul 18 07:26:54 PM PDT 24
Peak memory 220180 kb
Host smart-01a536d2-4fc2-4737-869c-f6e564e6d634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072804530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.3072804530
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.625064994
Short name T632
Test name
Test status
Simulation time 82305931 ps
CPU time 1.13 seconds
Started Jul 18 07:26:47 PM PDT 24
Finished Jul 18 07:26:52 PM PDT 24
Peak memory 217540 kb
Host smart-1ee5b3f8-e98f-4292-a2cf-7ffee1d08ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625064994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.625064994
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1006322175
Short name T895
Test name
Test status
Simulation time 50998451 ps
CPU time 1.32 seconds
Started Jul 18 07:26:48 PM PDT 24
Finished Jul 18 07:26:54 PM PDT 24
Peak memory 217572 kb
Host smart-c61a3909-ef30-4582-9e78-5d07362d6cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006322175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1006322175
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.64360910
Short name T243
Test name
Test status
Simulation time 26365689 ps
CPU time 1.27 seconds
Started Jul 18 07:23:33 PM PDT 24
Finished Jul 18 07:23:36 PM PDT 24
Peak memory 219900 kb
Host smart-cc9c4749-5eaa-4799-bf6a-bae2be4faeec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64360910 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.64360910
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.2930516363
Short name T58
Test name
Test status
Simulation time 68751910 ps
CPU time 0.92 seconds
Started Jul 18 07:23:36 PM PDT 24
Finished Jul 18 07:23:40 PM PDT 24
Peak memory 207060 kb
Host smart-71cc248b-2dc2-4efe-b0d1-498cdc2e1457
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930516363 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2930516363
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.2692059878
Short name T962
Test name
Test status
Simulation time 41462634 ps
CPU time 0.86 seconds
Started Jul 18 07:23:33 PM PDT 24
Finished Jul 18 07:23:36 PM PDT 24
Peak memory 215688 kb
Host smart-6cd53f39-3d36-4dcb-8875-a05e9352fe60
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692059878 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2692059878
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.1913213942
Short name T326
Test name
Test status
Simulation time 34215711 ps
CPU time 1.08 seconds
Started Jul 18 07:23:31 PM PDT 24
Finished Jul 18 07:23:32 PM PDT 24
Peak memory 217220 kb
Host smart-92748fad-61df-4cfc-bfe9-82aefcaead4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913213942 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.1913213942
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.3627097770
Short name T161
Test name
Test status
Simulation time 26357331 ps
CPU time 0.95 seconds
Started Jul 18 07:23:35 PM PDT 24
Finished Jul 18 07:23:40 PM PDT 24
Peak memory 218684 kb
Host smart-75e68aa5-35f0-4f5e-9d42-ecf9cc4db5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627097770 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.3627097770
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.1757100653
Short name T692
Test name
Test status
Simulation time 90716761 ps
CPU time 1.04 seconds
Started Jul 18 07:23:32 PM PDT 24
Finished Jul 18 07:23:34 PM PDT 24
Peak memory 219720 kb
Host smart-c56d3d6e-1753-431a-a8cf-757e93891667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757100653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1757100653
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.146620337
Short name T653
Test name
Test status
Simulation time 36438405 ps
CPU time 0.9 seconds
Started Jul 18 07:23:32 PM PDT 24
Finished Jul 18 07:23:35 PM PDT 24
Peak memory 215668 kb
Host smart-c73b37da-21e2-4482-9801-869d9a3b4f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146620337 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.146620337
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.686694742
Short name T769
Test name
Test status
Simulation time 57600867 ps
CPU time 0.92 seconds
Started Jul 18 07:23:31 PM PDT 24
Finished Jul 18 07:23:33 PM PDT 24
Peak memory 215556 kb
Host smart-b3b68410-7b3f-4f00-bbe2-4027e3793bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686694742 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.686694742
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.1220390585
Short name T103
Test name
Test status
Simulation time 273341455 ps
CPU time 5.13 seconds
Started Jul 18 07:23:35 PM PDT 24
Finished Jul 18 07:23:44 PM PDT 24
Peak memory 217644 kb
Host smart-0fdb264f-2592-451e-b151-9afca65c0da2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220390585 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1220390585
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.182139867
Short name T228
Test name
Test status
Simulation time 24530533426 ps
CPU time 505.28 seconds
Started Jul 18 07:23:37 PM PDT 24
Finished Jul 18 07:32:06 PM PDT 24
Peak memory 217940 kb
Host smart-e32ae7c2-5c90-498b-b60e-6f3505c1e948
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182139867 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.182139867
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.3318167969
Short name T478
Test name
Test status
Simulation time 66786413 ps
CPU time 1.18 seconds
Started Jul 18 07:26:51 PM PDT 24
Finished Jul 18 07:26:57 PM PDT 24
Peak memory 220084 kb
Host smart-e6e017a6-28bb-4bfd-a985-166e70317f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318167969 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3318167969
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.717864884
Short name T554
Test name
Test status
Simulation time 193238094 ps
CPU time 1.67 seconds
Started Jul 18 07:26:48 PM PDT 24
Finished Jul 18 07:26:54 PM PDT 24
Peak memory 218844 kb
Host smart-f695887b-e278-4368-8ed7-55a113b9c75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717864884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.717864884
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.4055771008
Short name T795
Test name
Test status
Simulation time 46726416 ps
CPU time 1.48 seconds
Started Jul 18 07:26:47 PM PDT 24
Finished Jul 18 07:26:52 PM PDT 24
Peak memory 218920 kb
Host smart-cabfe012-bdd2-49a2-8774-3d7eedb419e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055771008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.4055771008
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.272347363
Short name T583
Test name
Test status
Simulation time 57814910 ps
CPU time 1.35 seconds
Started Jul 18 07:26:46 PM PDT 24
Finished Jul 18 07:26:52 PM PDT 24
Peak memory 217680 kb
Host smart-20a867bc-25a0-4ef3-bfcd-6c3abfda59d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272347363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.272347363
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.1391331568
Short name T683
Test name
Test status
Simulation time 53973042 ps
CPU time 1.23 seconds
Started Jul 18 07:26:46 PM PDT 24
Finished Jul 18 07:26:52 PM PDT 24
Peak memory 220216 kb
Host smart-8e9cfe99-51ea-4cec-8843-2b3bfacc57df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391331568 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.1391331568
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.4156053667
Short name T498
Test name
Test status
Simulation time 46229466 ps
CPU time 1.6 seconds
Started Jul 18 07:26:45 PM PDT 24
Finished Jul 18 07:26:52 PM PDT 24
Peak memory 217580 kb
Host smart-11eb63b6-56c3-485d-96db-540f5dd0ceb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156053667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.4156053667
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.3815346554
Short name T794
Test name
Test status
Simulation time 116571156 ps
CPU time 1.17 seconds
Started Jul 18 07:27:24 PM PDT 24
Finished Jul 18 07:27:33 PM PDT 24
Peak memory 217728 kb
Host smart-7b0126bf-2a42-49e2-bb70-efadfd7a09ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815346554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.3815346554
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.1720766421
Short name T994
Test name
Test status
Simulation time 37425494 ps
CPU time 1.17 seconds
Started Jul 18 07:27:20 PM PDT 24
Finished Jul 18 07:27:26 PM PDT 24
Peak memory 220228 kb
Host smart-09640774-01c4-4876-8224-626d97412a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720766421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1720766421
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.3641255962
Short name T488
Test name
Test status
Simulation time 68688347 ps
CPU time 1.16 seconds
Started Jul 18 07:27:19 PM PDT 24
Finished Jul 18 07:27:22 PM PDT 24
Peak memory 217564 kb
Host smart-e4a3c02e-e934-4418-9990-427c044d98a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641255962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.3641255962
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.356928583
Short name T475
Test name
Test status
Simulation time 168313253 ps
CPU time 1.04 seconds
Started Jul 18 07:23:37 PM PDT 24
Finished Jul 18 07:23:41 PM PDT 24
Peak memory 219864 kb
Host smart-50e23335-2688-44b4-9cc4-e1e952409610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356928583 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.356928583
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.3864514529
Short name T70
Test name
Test status
Simulation time 15402776 ps
CPU time 0.92 seconds
Started Jul 18 07:23:36 PM PDT 24
Finished Jul 18 07:23:41 PM PDT 24
Peak memory 207040 kb
Host smart-afedd785-ad71-401b-93a2-77af52694ac2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864514529 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.3864514529
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.588643643
Short name T750
Test name
Test status
Simulation time 12902815 ps
CPU time 0.91 seconds
Started Jul 18 07:23:33 PM PDT 24
Finished Jul 18 07:23:37 PM PDT 24
Peak memory 216644 kb
Host smart-46435180-633a-4360-b784-016d6f3f4f18
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588643643 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.588643643
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_err.274766987
Short name T489
Test name
Test status
Simulation time 23345299 ps
CPU time 1.21 seconds
Started Jul 18 07:23:34 PM PDT 24
Finished Jul 18 07:23:39 PM PDT 24
Peak memory 224268 kb
Host smart-db58f15d-bc0f-4b41-b5f9-e2322c21bd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274766987 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.274766987
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.3840454720
Short name T346
Test name
Test status
Simulation time 137460258 ps
CPU time 2.07 seconds
Started Jul 18 07:23:34 PM PDT 24
Finished Jul 18 07:23:40 PM PDT 24
Peak memory 217820 kb
Host smart-d82d12cf-8cb5-47f1-af42-c01d31f83504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840454720 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3840454720
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.404418367
Short name T890
Test name
Test status
Simulation time 23546723 ps
CPU time 0.93 seconds
Started Jul 18 07:23:32 PM PDT 24
Finished Jul 18 07:23:35 PM PDT 24
Peak memory 216100 kb
Host smart-f6326ef3-cc9a-441b-8735-dee669b24ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404418367 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.404418367
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.1524537945
Short name T846
Test name
Test status
Simulation time 22387412 ps
CPU time 0.93 seconds
Started Jul 18 07:23:36 PM PDT 24
Finished Jul 18 07:23:41 PM PDT 24
Peak memory 215560 kb
Host smart-faa1a483-57e0-4237-a705-fa390ae1c4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524537945 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.1524537945
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.866746631
Short name T668
Test name
Test status
Simulation time 489806202 ps
CPU time 3.25 seconds
Started Jul 18 07:23:33 PM PDT 24
Finished Jul 18 07:23:38 PM PDT 24
Peak memory 220144 kb
Host smart-eea794fc-040c-48b4-a02a-66f0adb3fb8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866746631 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.866746631
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.364181581
Short name T603
Test name
Test status
Simulation time 709085566932 ps
CPU time 2184.26 seconds
Started Jul 18 07:23:39 PM PDT 24
Finished Jul 18 08:00:06 PM PDT 24
Peak memory 226544 kb
Host smart-3e3ea39e-ec8f-4064-80db-14aa9bfbb59b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364181581 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.364181581
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.965836166
Short name T495
Test name
Test status
Simulation time 56533027 ps
CPU time 1.16 seconds
Started Jul 18 07:27:25 PM PDT 24
Finished Jul 18 07:27:34 PM PDT 24
Peak memory 218868 kb
Host smart-02194659-6677-4d9e-97bb-e3037fdef613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965836166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.965836166
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.3747419755
Short name T695
Test name
Test status
Simulation time 47981117 ps
CPU time 1.51 seconds
Started Jul 18 07:27:18 PM PDT 24
Finished Jul 18 07:27:22 PM PDT 24
Peak memory 217412 kb
Host smart-af0ea786-db50-4163-87eb-40d7105ef16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747419755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.3747419755
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.1719674086
Short name T389
Test name
Test status
Simulation time 167323407 ps
CPU time 1.54 seconds
Started Jul 18 07:27:25 PM PDT 24
Finished Jul 18 07:27:34 PM PDT 24
Peak memory 219012 kb
Host smart-9889bba9-617a-4c02-b8d3-c0924e88c02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719674086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1719674086
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.4141393083
Short name T969
Test name
Test status
Simulation time 86314683 ps
CPU time 1.18 seconds
Started Jul 18 07:27:23 PM PDT 24
Finished Jul 18 07:27:32 PM PDT 24
Peak memory 217564 kb
Host smart-e9365832-5e10-4d7d-81af-df35e6dbc104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141393083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.4141393083
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.858106688
Short name T447
Test name
Test status
Simulation time 47372470 ps
CPU time 1.55 seconds
Started Jul 18 07:27:20 PM PDT 24
Finished Jul 18 07:27:27 PM PDT 24
Peak memory 218572 kb
Host smart-2bc17f25-53d0-49e5-b816-df178b3a4266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858106688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.858106688
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.2221792877
Short name T870
Test name
Test status
Simulation time 62028378 ps
CPU time 1.14 seconds
Started Jul 18 07:27:20 PM PDT 24
Finished Jul 18 07:27:27 PM PDT 24
Peak memory 218692 kb
Host smart-3ccc7ab6-2c91-45af-8de4-d79af8a1bd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221792877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2221792877
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.1988017175
Short name T479
Test name
Test status
Simulation time 34763086 ps
CPU time 1.32 seconds
Started Jul 18 07:27:20 PM PDT 24
Finished Jul 18 07:27:27 PM PDT 24
Peak memory 218916 kb
Host smart-c512c08d-5de8-462c-8db3-1cd6c9620441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988017175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.1988017175
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.382515591
Short name T658
Test name
Test status
Simulation time 92760295 ps
CPU time 1.95 seconds
Started Jul 18 07:27:25 PM PDT 24
Finished Jul 18 07:27:35 PM PDT 24
Peak memory 217860 kb
Host smart-ecadf742-eaad-449f-9896-4ba3b62e28c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382515591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.382515591
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.2352338819
Short name T506
Test name
Test status
Simulation time 35971945 ps
CPU time 1.24 seconds
Started Jul 18 07:27:19 PM PDT 24
Finished Jul 18 07:27:24 PM PDT 24
Peak memory 217584 kb
Host smart-c047b3ba-07a9-4ff0-9c75-ebf92f04f1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352338819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.2352338819
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.2545591469
Short name T586
Test name
Test status
Simulation time 50043217 ps
CPU time 1.26 seconds
Started Jul 18 07:23:32 PM PDT 24
Finished Jul 18 07:23:35 PM PDT 24
Peak memory 220872 kb
Host smart-47383daa-d0ed-4084-96f1-a5d2c3482e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545591469 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.2545591469
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.3089462320
Short name T685
Test name
Test status
Simulation time 35951308 ps
CPU time 1.01 seconds
Started Jul 18 07:23:33 PM PDT 24
Finished Jul 18 07:23:36 PM PDT 24
Peak memory 207224 kb
Host smart-a2b8456d-cc19-4a13-b373-d621c1eb5d6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089462320 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.3089462320
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.442936834
Short name T666
Test name
Test status
Simulation time 20340375 ps
CPU time 0.86 seconds
Started Jul 18 07:23:34 PM PDT 24
Finished Jul 18 07:23:37 PM PDT 24
Peak memory 216444 kb
Host smart-6b73dd2e-fb60-4876-973c-fbc75e4b5ba0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442936834 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.442936834
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_err.2427437346
Short name T53
Test name
Test status
Simulation time 27299709 ps
CPU time 1.12 seconds
Started Jul 18 07:23:37 PM PDT 24
Finished Jul 18 07:23:41 PM PDT 24
Peak memory 229808 kb
Host smart-52d6455a-5340-4897-8b9f-03fcfca2b210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427437346 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2427437346
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.1369900840
Short name T306
Test name
Test status
Simulation time 47906626 ps
CPU time 1.18 seconds
Started Jul 18 07:23:32 PM PDT 24
Finished Jul 18 07:23:35 PM PDT 24
Peak memory 219800 kb
Host smart-e0aebb45-ba56-4473-b9af-36c662340bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369900840 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.1369900840
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.3481773180
Short name T709
Test name
Test status
Simulation time 21638720 ps
CPU time 1.08 seconds
Started Jul 18 07:23:34 PM PDT 24
Finished Jul 18 07:23:39 PM PDT 24
Peak memory 216172 kb
Host smart-c3b76ba4-b6a5-4d38-80ad-b1376e1579e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481773180 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.3481773180
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.2036831818
Short name T440
Test name
Test status
Simulation time 18119910 ps
CPU time 0.99 seconds
Started Jul 18 07:23:35 PM PDT 24
Finished Jul 18 07:23:39 PM PDT 24
Peak memory 207460 kb
Host smart-9b4686b3-021d-4d00-b702-41832e302d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036831818 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.2036831818
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.3554157443
Short name T576
Test name
Test status
Simulation time 549681807 ps
CPU time 3.19 seconds
Started Jul 18 07:23:38 PM PDT 24
Finished Jul 18 07:23:44 PM PDT 24
Peak memory 215568 kb
Host smart-29b9d9cf-1965-432a-a819-239b2640389e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554157443 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3554157443
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.1093106581
Short name T444
Test name
Test status
Simulation time 401537583694 ps
CPU time 2754.51 seconds
Started Jul 18 07:23:36 PM PDT 24
Finished Jul 18 08:09:35 PM PDT 24
Peak memory 233352 kb
Host smart-8fac8334-212b-4e58-b4e3-969ed955d60e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093106581 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.1093106581
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.2829482692
Short name T621
Test name
Test status
Simulation time 63231808 ps
CPU time 1.33 seconds
Started Jul 18 07:27:20 PM PDT 24
Finished Jul 18 07:27:24 PM PDT 24
Peak memory 218796 kb
Host smart-ce4de45f-8d53-4016-80e0-92cbf850e902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829482692 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2829482692
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.1729748091
Short name T875
Test name
Test status
Simulation time 62003925 ps
CPU time 2.12 seconds
Started Jul 18 07:27:20 PM PDT 24
Finished Jul 18 07:27:25 PM PDT 24
Peak memory 218832 kb
Host smart-aa0164ab-6704-4fa9-a615-59539d35a8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729748091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.1729748091
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.3218366129
Short name T803
Test name
Test status
Simulation time 53136929 ps
CPU time 1.04 seconds
Started Jul 18 07:27:21 PM PDT 24
Finished Jul 18 07:27:29 PM PDT 24
Peak memory 218624 kb
Host smart-a4f21dad-4468-4cac-a1d3-6e533a00fe34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218366129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.3218366129
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.2633544964
Short name T910
Test name
Test status
Simulation time 51841382 ps
CPU time 1.46 seconds
Started Jul 18 07:27:19 PM PDT 24
Finished Jul 18 07:27:23 PM PDT 24
Peak memory 218768 kb
Host smart-b3e5e121-eea4-4c48-b058-a52ef41894ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633544964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2633544964
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.3035403267
Short name T587
Test name
Test status
Simulation time 72240446 ps
CPU time 1.15 seconds
Started Jul 18 07:27:18 PM PDT 24
Finished Jul 18 07:27:22 PM PDT 24
Peak memory 217528 kb
Host smart-e66e9660-1e27-4bcc-91a9-7584086ea42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035403267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3035403267
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.294358138
Short name T592
Test name
Test status
Simulation time 37570318 ps
CPU time 1.18 seconds
Started Jul 18 07:27:24 PM PDT 24
Finished Jul 18 07:27:33 PM PDT 24
Peak memory 218576 kb
Host smart-e723c017-6fd5-442f-8d28-82e8435f8513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294358138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.294358138
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.1180093352
Short name T983
Test name
Test status
Simulation time 71784469 ps
CPU time 1.37 seconds
Started Jul 18 07:27:21 PM PDT 24
Finished Jul 18 07:27:28 PM PDT 24
Peak memory 218736 kb
Host smart-0ff1efc0-81af-4da8-8062-f1988c8750f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180093352 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.1180093352
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.768708416
Short name T714
Test name
Test status
Simulation time 37855169 ps
CPU time 1.38 seconds
Started Jul 18 07:27:20 PM PDT 24
Finished Jul 18 07:27:24 PM PDT 24
Peak memory 218820 kb
Host smart-1efc0045-9342-4b86-b85d-d003d67294e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768708416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.768708416
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.2318440618
Short name T559
Test name
Test status
Simulation time 66040741 ps
CPU time 1.31 seconds
Started Jul 18 07:27:18 PM PDT 24
Finished Jul 18 07:27:21 PM PDT 24
Peak memory 218756 kb
Host smart-925a971f-7c9a-49bf-b9a6-773430cc442e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318440618 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.2318440618
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.2566313447
Short name T491
Test name
Test status
Simulation time 43604207 ps
CPU time 1.17 seconds
Started Jul 18 07:23:35 PM PDT 24
Finished Jul 18 07:23:39 PM PDT 24
Peak memory 220068 kb
Host smart-1b2e659b-7f6d-47bc-9582-c4c68cac1e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566313447 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2566313447
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.3296006870
Short name T654
Test name
Test status
Simulation time 127201956 ps
CPU time 0.87 seconds
Started Jul 18 07:23:35 PM PDT 24
Finished Jul 18 07:23:39 PM PDT 24
Peak memory 215484 kb
Host smart-0175019c-03b1-4af2-999a-fdb366c91a5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296006870 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3296006870
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.3945878059
Short name T817
Test name
Test status
Simulation time 157934924 ps
CPU time 0.85 seconds
Started Jul 18 07:23:36 PM PDT 24
Finished Jul 18 07:23:40 PM PDT 24
Peak memory 216480 kb
Host smart-e2ec395c-dc30-450f-aae2-e532b815f33d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945878059 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.3945878059
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.2181720825
Short name T958
Test name
Test status
Simulation time 69059219 ps
CPU time 0.95 seconds
Started Jul 18 07:23:37 PM PDT 24
Finished Jul 18 07:23:41 PM PDT 24
Peak memory 218560 kb
Host smart-c52cb3c1-da3d-42f4-ae25-585d8e913552
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181720825 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.2181720825
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.3912061681
Short name T965
Test name
Test status
Simulation time 21974900 ps
CPU time 1.01 seconds
Started Jul 18 07:23:35 PM PDT 24
Finished Jul 18 07:23:40 PM PDT 24
Peak memory 219056 kb
Host smart-94217fa4-9233-45c8-8306-319c0e95ab0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912061681 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.3912061681
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.350213098
Short name T321
Test name
Test status
Simulation time 35372184 ps
CPU time 1.61 seconds
Started Jul 18 07:23:36 PM PDT 24
Finished Jul 18 07:23:41 PM PDT 24
Peak memory 218824 kb
Host smart-04f8aeef-7c63-4056-b0ce-ba97072f0626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350213098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.350213098
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.1230528758
Short name T608
Test name
Test status
Simulation time 63343012 ps
CPU time 0.84 seconds
Started Jul 18 07:23:34 PM PDT 24
Finished Jul 18 07:23:37 PM PDT 24
Peak memory 215560 kb
Host smart-caa1cb00-41c3-478d-bd13-6fbb087fd631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230528758 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.1230528758
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.1173405379
Short name T433
Test name
Test status
Simulation time 43175533 ps
CPU time 0.91 seconds
Started Jul 18 07:23:35 PM PDT 24
Finished Jul 18 07:23:39 PM PDT 24
Peak memory 215488 kb
Host smart-1f0fac22-b715-4494-aa64-09df532db92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173405379 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.1173405379
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.1391658044
Short name T73
Test name
Test status
Simulation time 351596783 ps
CPU time 3.95 seconds
Started Jul 18 07:23:36 PM PDT 24
Finished Jul 18 07:23:44 PM PDT 24
Peak memory 215524 kb
Host smart-1556d056-8157-44e9-ad21-1db511bb3714
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391658044 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.1391658044
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.374897896
Short name T819
Test name
Test status
Simulation time 32754187950 ps
CPU time 201.71 seconds
Started Jul 18 07:23:36 PM PDT 24
Finished Jul 18 07:27:01 PM PDT 24
Peak memory 223088 kb
Host smart-da1884e5-6535-4fbf-8775-379e96f2b082
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374897896 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.374897896
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.164557105
Short name T46
Test name
Test status
Simulation time 215864780 ps
CPU time 2.95 seconds
Started Jul 18 07:27:20 PM PDT 24
Finished Jul 18 07:27:27 PM PDT 24
Peak memory 220168 kb
Host smart-fab5dbbc-6da3-49d8-8233-067c497c2555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164557105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.164557105
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.2010473665
Short name T416
Test name
Test status
Simulation time 57115167 ps
CPU time 1.04 seconds
Started Jul 18 07:27:20 PM PDT 24
Finished Jul 18 07:27:26 PM PDT 24
Peak memory 217568 kb
Host smart-228b95a3-876c-4c8a-8529-2dbc4e5150a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010473665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.2010473665
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.3971275832
Short name T315
Test name
Test status
Simulation time 35449877 ps
CPU time 1.4 seconds
Started Jul 18 07:27:23 PM PDT 24
Finished Jul 18 07:27:33 PM PDT 24
Peak memory 218908 kb
Host smart-b29400ea-bb09-459a-b385-025bee739650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971275832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.3971275832
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.240629801
Short name T799
Test name
Test status
Simulation time 40890338 ps
CPU time 1.64 seconds
Started Jul 18 07:27:25 PM PDT 24
Finished Jul 18 07:27:35 PM PDT 24
Peak memory 217736 kb
Host smart-9df244d3-4f0f-439d-a1ae-463537c200d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240629801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.240629801
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.3969997861
Short name T91
Test name
Test status
Simulation time 129453010 ps
CPU time 1.32 seconds
Started Jul 18 07:27:23 PM PDT 24
Finished Jul 18 07:27:32 PM PDT 24
Peak memory 217544 kb
Host smart-102d2e4d-69fd-4d7f-a465-205013db5abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969997861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3969997861
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.1175445412
Short name T861
Test name
Test status
Simulation time 72751004 ps
CPU time 1.09 seconds
Started Jul 18 07:27:24 PM PDT 24
Finished Jul 18 07:27:33 PM PDT 24
Peak memory 217248 kb
Host smart-d1e9d192-d003-47dd-aa41-630307690b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175445412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.1175445412
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.57246822
Short name T822
Test name
Test status
Simulation time 45643050 ps
CPU time 1.26 seconds
Started Jul 18 07:27:21 PM PDT 24
Finished Jul 18 07:27:28 PM PDT 24
Peak memory 217492 kb
Host smart-05f574bf-8eac-48aa-b289-5c55c8cce337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57246822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.57246822
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.1953950152
Short name T943
Test name
Test status
Simulation time 55720672 ps
CPU time 1.95 seconds
Started Jul 18 07:27:21 PM PDT 24
Finished Jul 18 07:27:30 PM PDT 24
Peak memory 219196 kb
Host smart-b6efed40-eb7b-4f79-b907-6f46b6fcca96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953950152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.1953950152
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.3384415368
Short name T465
Test name
Test status
Simulation time 79896914 ps
CPU time 1.41 seconds
Started Jul 18 07:27:24 PM PDT 24
Finished Jul 18 07:27:33 PM PDT 24
Peak memory 217492 kb
Host smart-db364c33-384b-4fe7-8af9-2448435ee9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384415368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3384415368
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.525229550
Short name T753
Test name
Test status
Simulation time 110863977 ps
CPU time 1.67 seconds
Started Jul 18 07:27:24 PM PDT 24
Finished Jul 18 07:27:33 PM PDT 24
Peak memory 219504 kb
Host smart-42520479-f4c0-4b08-8baf-be561660c6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525229550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.525229550
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.3624546092
Short name T851
Test name
Test status
Simulation time 250791798 ps
CPU time 1.34 seconds
Started Jul 18 07:23:51 PM PDT 24
Finished Jul 18 07:23:54 PM PDT 24
Peak memory 215992 kb
Host smart-75fda110-778a-4a00-94a2-eab35a9d4b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624546092 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.3624546092
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.3057033004
Short name T423
Test name
Test status
Simulation time 17744669 ps
CPU time 0.98 seconds
Started Jul 18 07:23:49 PM PDT 24
Finished Jul 18 07:23:51 PM PDT 24
Peak memory 207232 kb
Host smart-2044a629-6d6c-4624-9541-babf0d30c190
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057033004 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3057033004
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.1675462197
Short name T148
Test name
Test status
Simulation time 80242522 ps
CPU time 1.3 seconds
Started Jul 18 07:23:50 PM PDT 24
Finished Jul 18 07:23:54 PM PDT 24
Peak memory 217232 kb
Host smart-fd158ef8-4f24-4aca-bcc7-72052dfa24ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675462197 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.1675462197
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_genbits.3878369087
Short name T574
Test name
Test status
Simulation time 56066210 ps
CPU time 1.41 seconds
Started Jul 18 07:23:36 PM PDT 24
Finished Jul 18 07:23:41 PM PDT 24
Peak memory 219100 kb
Host smart-11902f16-3274-4e56-a4fd-7290d087a9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878369087 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3878369087
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_smoke.2330505474
Short name T485
Test name
Test status
Simulation time 32847348 ps
CPU time 0.94 seconds
Started Jul 18 07:23:33 PM PDT 24
Finished Jul 18 07:23:36 PM PDT 24
Peak memory 215572 kb
Host smart-e2770050-2eaf-4a54-a41c-bc11ae20665f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330505474 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.2330505474
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.1085121853
Short name T920
Test name
Test status
Simulation time 412696189 ps
CPU time 7.72 seconds
Started Jul 18 07:23:33 PM PDT 24
Finished Jul 18 07:23:42 PM PDT 24
Peak memory 217328 kb
Host smart-87bb25b5-0024-4589-8c38-d1ea25cfc997
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085121853 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1085121853
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.1937043639
Short name T995
Test name
Test status
Simulation time 251927641000 ps
CPU time 509.26 seconds
Started Jul 18 07:23:50 PM PDT 24
Finished Jul 18 07:32:22 PM PDT 24
Peak memory 219608 kb
Host smart-05128065-c79f-47ea-8c10-e9ab320d399c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937043639 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.1937043639
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.2293763108
Short name T500
Test name
Test status
Simulation time 76838896 ps
CPU time 1.17 seconds
Started Jul 18 07:27:22 PM PDT 24
Finished Jul 18 07:27:31 PM PDT 24
Peak memory 217536 kb
Host smart-ecedd71c-359b-4535-9fea-088a5942f0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293763108 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.2293763108
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.1767595688
Short name T635
Test name
Test status
Simulation time 37377642 ps
CPU time 1.27 seconds
Started Jul 18 07:27:25 PM PDT 24
Finished Jul 18 07:27:34 PM PDT 24
Peak memory 218852 kb
Host smart-75955627-35ad-4462-bbc6-c37e9f04bbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767595688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.1767595688
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.3251423035
Short name T767
Test name
Test status
Simulation time 133341753 ps
CPU time 1.27 seconds
Started Jul 18 07:27:24 PM PDT 24
Finished Jul 18 07:27:33 PM PDT 24
Peak memory 220192 kb
Host smart-06887b3f-180d-467c-9e31-0829a8797480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251423035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.3251423035
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2673572392
Short name T502
Test name
Test status
Simulation time 103544240 ps
CPU time 1.13 seconds
Started Jul 18 07:27:23 PM PDT 24
Finished Jul 18 07:27:32 PM PDT 24
Peak memory 217540 kb
Host smart-64cf7243-5990-477d-8b17-596e016d3e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673572392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2673572392
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3041641635
Short name T308
Test name
Test status
Simulation time 64292716 ps
CPU time 1.05 seconds
Started Jul 18 07:27:23 PM PDT 24
Finished Jul 18 07:27:33 PM PDT 24
Peak memory 218556 kb
Host smart-fa1d0cec-3b71-4f63-8219-70289003ce68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041641635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3041641635
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3951381502
Short name T854
Test name
Test status
Simulation time 81243950 ps
CPU time 1.17 seconds
Started Jul 18 07:27:22 PM PDT 24
Finished Jul 18 07:27:32 PM PDT 24
Peak memory 220212 kb
Host smart-bbb75217-ee22-4685-be38-8022950fd4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951381502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3951381502
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.2499502222
Short name T675
Test name
Test status
Simulation time 32743995 ps
CPU time 1.26 seconds
Started Jul 18 07:27:25 PM PDT 24
Finished Jul 18 07:27:34 PM PDT 24
Peak memory 217480 kb
Host smart-14853655-440a-4bf4-bf2c-5f325ec25471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499502222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.2499502222
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.323780425
Short name T888
Test name
Test status
Simulation time 68652766 ps
CPU time 2.14 seconds
Started Jul 18 07:27:25 PM PDT 24
Finished Jul 18 07:27:35 PM PDT 24
Peak memory 219880 kb
Host smart-32caebfb-50fb-4960-b2d6-241b43a0541a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323780425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.323780425
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.3510662161
Short name T985
Test name
Test status
Simulation time 99712978 ps
CPU time 1.14 seconds
Started Jul 18 07:27:22 PM PDT 24
Finished Jul 18 07:27:32 PM PDT 24
Peak memory 217684 kb
Host smart-e5f48376-cede-43a7-9ad2-19fb7c329438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510662161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3510662161
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.2062492553
Short name T153
Test name
Test status
Simulation time 23567237 ps
CPU time 1.17 seconds
Started Jul 18 07:21:45 PM PDT 24
Finished Jul 18 07:21:49 PM PDT 24
Peak memory 220244 kb
Host smart-0fc7ca0f-0830-4916-b0dd-4429e64ae6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062492553 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.2062492553
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.3965187648
Short name T351
Test name
Test status
Simulation time 15106038 ps
CPU time 0.95 seconds
Started Jul 18 07:21:43 PM PDT 24
Finished Jul 18 07:21:47 PM PDT 24
Peak memory 207060 kb
Host smart-a38edfae-52e2-45a9-938d-59e76473dad3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965187648 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3965187648
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.932973130
Short name T934
Test name
Test status
Simulation time 13807255 ps
CPU time 0.9 seconds
Started Jul 18 07:21:42 PM PDT 24
Finished Jul 18 07:21:45 PM PDT 24
Peak memory 216648 kb
Host smart-136ceb4b-bcdf-47a1-b8b4-3e962f1516bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932973130 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.932973130
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.3821233134
Short name T205
Test name
Test status
Simulation time 47348127 ps
CPU time 1.12 seconds
Started Jul 18 07:21:46 PM PDT 24
Finished Jul 18 07:21:49 PM PDT 24
Peak memory 217248 kb
Host smart-52a6708d-2b91-4eb7-846e-c080e969b1a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821233134 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.3821233134
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.2715930917
Short name T81
Test name
Test status
Simulation time 22497286 ps
CPU time 0.9 seconds
Started Jul 18 07:21:45 PM PDT 24
Finished Jul 18 07:21:49 PM PDT 24
Peak memory 218508 kb
Host smart-d19a1291-7b83-4982-a409-ff59b65265ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715930917 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2715930917
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.3111714689
Short name T309
Test name
Test status
Simulation time 37063698 ps
CPU time 1.62 seconds
Started Jul 18 07:21:43 PM PDT 24
Finished Jul 18 07:21:47 PM PDT 24
Peak memory 218888 kb
Host smart-32de0042-5f34-4361-88bd-2c57c8f38e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111714689 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.3111714689
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.3691432311
Short name T31
Test name
Test status
Simulation time 34084273 ps
CPU time 0.91 seconds
Started Jul 18 07:21:42 PM PDT 24
Finished Jul 18 07:21:44 PM PDT 24
Peak memory 215984 kb
Host smart-4de02dde-b35a-4a44-9189-55697a068a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691432311 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.3691432311
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.1232308569
Short name T974
Test name
Test status
Simulation time 91676876 ps
CPU time 0.93 seconds
Started Jul 18 07:21:44 PM PDT 24
Finished Jul 18 07:21:48 PM PDT 24
Peak memory 207376 kb
Host smart-bbe15b7d-4610-425a-9453-7417ba645441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232308569 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1232308569
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.2825328123
Short name T633
Test name
Test status
Simulation time 20521571 ps
CPU time 1 seconds
Started Jul 18 07:21:29 PM PDT 24
Finished Jul 18 07:21:35 PM PDT 24
Peak memory 215552 kb
Host smart-0ed87f87-90d1-436d-a8ba-17684fda9c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825328123 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2825328123
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.2135714925
Short name T365
Test name
Test status
Simulation time 278100566 ps
CPU time 5.83 seconds
Started Jul 18 07:21:45 PM PDT 24
Finished Jul 18 07:21:53 PM PDT 24
Peak memory 217596 kb
Host smart-ebf505c3-c7d8-4f83-88bc-5c1e51ab8b3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135714925 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2135714925
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_alert.743444654
Short name T816
Test name
Test status
Simulation time 69924122 ps
CPU time 1.14 seconds
Started Jul 18 07:23:50 PM PDT 24
Finished Jul 18 07:23:54 PM PDT 24
Peak memory 219708 kb
Host smart-86759313-c72a-4417-bec4-30436eedeff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743444654 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.743444654
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.2015189379
Short name T651
Test name
Test status
Simulation time 55217229 ps
CPU time 0.96 seconds
Started Jul 18 07:23:48 PM PDT 24
Finished Jul 18 07:23:51 PM PDT 24
Peak memory 215496 kb
Host smart-2760dcdd-b7df-4ff2-b0db-837af78ebe42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015189379 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.2015189379
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.2820284749
Short name T150
Test name
Test status
Simulation time 37606816 ps
CPU time 0.81 seconds
Started Jul 18 07:23:49 PM PDT 24
Finished Jul 18 07:23:51 PM PDT 24
Peak memory 215680 kb
Host smart-a0f5dd9a-122f-4cd1-8c75-43c3146dd066
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820284749 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.2820284749
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.2845087563
Short name T422
Test name
Test status
Simulation time 23513924 ps
CPU time 1.05 seconds
Started Jul 18 07:23:49 PM PDT 24
Finished Jul 18 07:23:52 PM PDT 24
Peak memory 218820 kb
Host smart-eef7e83f-7302-474e-9a3c-906f00f07ce6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845087563 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.2845087563
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.2984135655
Short name T168
Test name
Test status
Simulation time 36395100 ps
CPU time 0.84 seconds
Started Jul 18 07:23:50 PM PDT 24
Finished Jul 18 07:23:53 PM PDT 24
Peak memory 218532 kb
Host smart-54f7b55f-f7b6-4569-95c8-0a33bdac9f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984135655 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.2984135655
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.3249346249
Short name T593
Test name
Test status
Simulation time 86818652 ps
CPU time 1.21 seconds
Started Jul 18 07:23:47 PM PDT 24
Finished Jul 18 07:23:49 PM PDT 24
Peak memory 217476 kb
Host smart-58a8b4e5-50b7-46f9-bac9-be95987bba69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249346249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3249346249
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.1149697132
Short name T385
Test name
Test status
Simulation time 37145236 ps
CPU time 0.93 seconds
Started Jul 18 07:23:49 PM PDT 24
Finished Jul 18 07:23:52 PM PDT 24
Peak memory 215940 kb
Host smart-4e766dbd-166a-4d0a-b900-8b678f067554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149697132 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.1149697132
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.197732180
Short name T395
Test name
Test status
Simulation time 25522732 ps
CPU time 0.94 seconds
Started Jul 18 07:23:49 PM PDT 24
Finished Jul 18 07:23:52 PM PDT 24
Peak memory 215524 kb
Host smart-c90bfe12-491a-4a72-b100-e286c5520bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197732180 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.197732180
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.2009949904
Short name T353
Test name
Test status
Simulation time 53068156 ps
CPU time 1.55 seconds
Started Jul 18 07:23:50 PM PDT 24
Finished Jul 18 07:23:54 PM PDT 24
Peak memory 218536 kb
Host smart-5b19901e-d73c-489a-a701-5ff504617ce8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009949904 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.2009949904
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.83936422
Short name T830
Test name
Test status
Simulation time 259017792624 ps
CPU time 1894.59 seconds
Started Jul 18 07:23:50 PM PDT 24
Finished Jul 18 07:55:27 PM PDT 24
Peak memory 226240 kb
Host smart-6ee4ae87-abb5-4b0c-8d84-418f6f259d2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83936422 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.83936422
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.662807336
Short name T956
Test name
Test status
Simulation time 97598502 ps
CPU time 1.25 seconds
Started Jul 18 07:23:50 PM PDT 24
Finished Jul 18 07:23:54 PM PDT 24
Peak memory 222152 kb
Host smart-68c1caee-b6de-40a4-8cb3-89e78b41516a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662807336 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.662807336
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.3940227899
Short name T745
Test name
Test status
Simulation time 69752361 ps
CPU time 0.94 seconds
Started Jul 18 07:24:09 PM PDT 24
Finished Jul 18 07:24:13 PM PDT 24
Peak memory 207032 kb
Host smart-02de1631-93e2-40ba-a6a7-7fec90fb3085
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940227899 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3940227899
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.3145159956
Short name T595
Test name
Test status
Simulation time 18782583 ps
CPU time 0.93 seconds
Started Jul 18 07:23:49 PM PDT 24
Finished Jul 18 07:23:52 PM PDT 24
Peak memory 216592 kb
Host smart-a16a5c59-aa7d-4379-b6f6-60ea126d85c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145159956 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3145159956
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.527037520
Short name T135
Test name
Test status
Simulation time 38265688 ps
CPU time 1.24 seconds
Started Jul 18 07:24:07 PM PDT 24
Finished Jul 18 07:24:11 PM PDT 24
Peak memory 219716 kb
Host smart-63ca004a-795f-4839-baf8-5ae19799146b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527037520 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_di
sable_auto_req_mode.527037520
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.2027009780
Short name T937
Test name
Test status
Simulation time 38077684 ps
CPU time 0.93 seconds
Started Jul 18 07:23:50 PM PDT 24
Finished Jul 18 07:23:53 PM PDT 24
Peak memory 218772 kb
Host smart-35e1aeeb-67a1-4b6e-88ed-d16f8b080ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027009780 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.2027009780
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.457986979
Short name T239
Test name
Test status
Simulation time 30287845 ps
CPU time 1.34 seconds
Started Jul 18 07:23:48 PM PDT 24
Finished Jul 18 07:23:51 PM PDT 24
Peak memory 218836 kb
Host smart-5f73ec1b-3da5-4ad4-81c1-0d5d3b50bc85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457986979 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.457986979
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.203718667
Short name T594
Test name
Test status
Simulation time 20980544 ps
CPU time 1.17 seconds
Started Jul 18 07:23:50 PM PDT 24
Finished Jul 18 07:23:53 PM PDT 24
Peak memory 215860 kb
Host smart-87c6913e-b7b3-49f2-a84d-a0b98d663201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203718667 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.203718667
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.3141581483
Short name T669
Test name
Test status
Simulation time 42455015 ps
CPU time 0.94 seconds
Started Jul 18 07:23:48 PM PDT 24
Finished Jul 18 07:23:50 PM PDT 24
Peak memory 215668 kb
Host smart-a65aa505-6355-4826-90cb-286e61ad6091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141581483 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.3141581483
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.4021147467
Short name T971
Test name
Test status
Simulation time 216827332 ps
CPU time 4.72 seconds
Started Jul 18 07:23:50 PM PDT 24
Finished Jul 18 07:23:57 PM PDT 24
Peak memory 217632 kb
Host smart-ba6b1b4d-d152-4931-9c2f-ecc31e11ec0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021147467 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.4021147467
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.4222905100
Short name T293
Test name
Test status
Simulation time 215721447580 ps
CPU time 1288.6 seconds
Started Jul 18 07:23:49 PM PDT 24
Finished Jul 18 07:45:19 PM PDT 24
Peak memory 225572 kb
Host smart-bf374444-e1b2-4963-a023-6a3a20e2e910
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222905100 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.4222905100
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.3031144113
Short name T284
Test name
Test status
Simulation time 65401658 ps
CPU time 1.09 seconds
Started Jul 18 07:24:06 PM PDT 24
Finished Jul 18 07:24:08 PM PDT 24
Peak memory 219072 kb
Host smart-143daa81-29ea-4076-9297-a6306718258c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031144113 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.3031144113
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.1110126816
Short name T979
Test name
Test status
Simulation time 35538900 ps
CPU time 0.99 seconds
Started Jul 18 07:24:10 PM PDT 24
Finished Jul 18 07:24:14 PM PDT 24
Peak memory 215220 kb
Host smart-090d841c-d696-4fe5-b1a0-927de7112b4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110126816 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.1110126816
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.2365256771
Short name T211
Test name
Test status
Simulation time 16933926 ps
CPU time 0.85 seconds
Started Jul 18 07:24:09 PM PDT 24
Finished Jul 18 07:24:12 PM PDT 24
Peak memory 216616 kb
Host smart-da0b9ca3-4abe-44db-80cf-9964d4bd4afe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365256771 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.2365256771
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.1071401297
Short name T813
Test name
Test status
Simulation time 68006782 ps
CPU time 0.98 seconds
Started Jul 18 07:24:10 PM PDT 24
Finished Jul 18 07:24:14 PM PDT 24
Peak memory 218752 kb
Host smart-5a8f5199-2883-4405-a1a8-65443c955de6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071401297 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.1071401297
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.316214909
Short name T811
Test name
Test status
Simulation time 41867180 ps
CPU time 0.88 seconds
Started Jul 18 07:24:08 PM PDT 24
Finished Jul 18 07:24:11 PM PDT 24
Peak memory 215640 kb
Host smart-da0114db-ebb7-47ee-9f4a-aecaac47aae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316214909 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.316214909
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.3412777302
Short name T76
Test name
Test status
Simulation time 49927164 ps
CPU time 1.11 seconds
Started Jul 18 07:24:08 PM PDT 24
Finished Jul 18 07:24:12 PM PDT 24
Peak memory 217504 kb
Host smart-fff54207-c219-4232-821b-a5255064e451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412777302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3412777302
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.2314660317
Short name T966
Test name
Test status
Simulation time 21500140 ps
CPU time 0.99 seconds
Started Jul 18 07:24:09 PM PDT 24
Finished Jul 18 07:24:13 PM PDT 24
Peak memory 215792 kb
Host smart-d059de77-f652-4d03-a6ee-7f91be69cce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314660317 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.2314660317
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.1381427119
Short name T529
Test name
Test status
Simulation time 40109547 ps
CPU time 0.94 seconds
Started Jul 18 07:24:09 PM PDT 24
Finished Jul 18 07:24:12 PM PDT 24
Peak memory 215564 kb
Host smart-7e817941-3792-4cf0-b90f-9dc9e53a7e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381427119 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.1381427119
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.2518823655
Short name T525
Test name
Test status
Simulation time 303993482 ps
CPU time 6 seconds
Started Jul 18 07:24:08 PM PDT 24
Finished Jul 18 07:24:17 PM PDT 24
Peak memory 215496 kb
Host smart-0c75fc72-fb7d-4918-97c6-7b6b232eba65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518823655 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.2518823655
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1582393068
Short name T783
Test name
Test status
Simulation time 163937910397 ps
CPU time 1852.24 seconds
Started Jul 18 07:24:10 PM PDT 24
Finished Jul 18 07:55:05 PM PDT 24
Peak memory 227060 kb
Host smart-c0a91ce7-f769-4488-a68e-6237894e0216
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582393068 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1582393068
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.1727045178
Short name T290
Test name
Test status
Simulation time 43928330 ps
CPU time 1.2 seconds
Started Jul 18 07:24:09 PM PDT 24
Finished Jul 18 07:24:13 PM PDT 24
Peak memory 218732 kb
Host smart-475a463b-bcea-44d4-a951-2cfcff7284fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727045178 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.1727045178
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.3104398713
Short name T367
Test name
Test status
Simulation time 22410937 ps
CPU time 0.89 seconds
Started Jul 18 07:24:08 PM PDT 24
Finished Jul 18 07:24:11 PM PDT 24
Peak memory 207048 kb
Host smart-868039de-46fa-4505-ab04-aa60147426db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104398713 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.3104398713
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.288142517
Short name T397
Test name
Test status
Simulation time 23985306 ps
CPU time 0.91 seconds
Started Jul 18 07:24:10 PM PDT 24
Finished Jul 18 07:24:14 PM PDT 24
Peak memory 216192 kb
Host smart-4571ef00-264d-4aa9-9650-6e1df6c10406
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288142517 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.288142517
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.129829972
Short name T540
Test name
Test status
Simulation time 98487516 ps
CPU time 1.1 seconds
Started Jul 18 07:24:07 PM PDT 24
Finished Jul 18 07:24:10 PM PDT 24
Peak memory 220056 kb
Host smart-ce439d88-3c79-4ae0-96fa-ab4983cb5d3c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129829972 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_di
sable_auto_req_mode.129829972
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.3967472295
Short name T57
Test name
Test status
Simulation time 29615252 ps
CPU time 0.99 seconds
Started Jul 18 07:24:09 PM PDT 24
Finished Jul 18 07:24:13 PM PDT 24
Peak memory 224108 kb
Host smart-27023cb1-ea00-4fd1-8845-098e55225e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967472295 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.3967472295
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.113326031
Short name T484
Test name
Test status
Simulation time 61312548 ps
CPU time 1.19 seconds
Started Jul 18 07:24:10 PM PDT 24
Finished Jul 18 07:24:14 PM PDT 24
Peak memory 220188 kb
Host smart-30276333-6976-4817-8d56-b4cd7857dd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113326031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.113326031
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.2829262057
Short name T100
Test name
Test status
Simulation time 23750204 ps
CPU time 0.99 seconds
Started Jul 18 07:24:09 PM PDT 24
Finished Jul 18 07:24:12 PM PDT 24
Peak memory 216208 kb
Host smart-3a80e8c5-a521-4f36-8f5f-8eac24f33c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829262057 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.2829262057
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.1706606574
Short name T887
Test name
Test status
Simulation time 94419145 ps
CPU time 0.93 seconds
Started Jul 18 07:24:09 PM PDT 24
Finished Jul 18 07:24:13 PM PDT 24
Peak memory 215368 kb
Host smart-e05b1097-1cab-4bd4-90ac-46a94e8d5734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706606574 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.1706606574
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3520709597
Short name T431
Test name
Test status
Simulation time 59938494 ps
CPU time 1.68 seconds
Started Jul 18 07:24:07 PM PDT 24
Finished Jul 18 07:24:11 PM PDT 24
Peak memory 218636 kb
Host smart-2b524c46-9ecf-4052-81d7-481ef8434f76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520709597 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3520709597
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_alert.543859028
Short name T787
Test name
Test status
Simulation time 26539954 ps
CPU time 1.27 seconds
Started Jul 18 07:24:08 PM PDT 24
Finished Jul 18 07:24:12 PM PDT 24
Peak memory 219552 kb
Host smart-a93481ad-9991-482b-a33f-4d8d540c88a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543859028 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.543859028
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.1929416500
Short name T865
Test name
Test status
Simulation time 16821027 ps
CPU time 0.96 seconds
Started Jul 18 07:24:09 PM PDT 24
Finished Jul 18 07:24:12 PM PDT 24
Peak memory 206768 kb
Host smart-9cb56f55-ac8b-48ee-acec-813f933902aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929416500 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1929416500
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.1905178262
Short name T213
Test name
Test status
Simulation time 13528395 ps
CPU time 0.94 seconds
Started Jul 18 07:24:09 PM PDT 24
Finished Jul 18 07:24:13 PM PDT 24
Peak memory 215456 kb
Host smart-02bf4abd-0333-498c-80ed-e435285a4bb5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905178262 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1905178262
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.3762321296
Short name T838
Test name
Test status
Simulation time 30797966 ps
CPU time 1.18 seconds
Started Jul 18 07:24:08 PM PDT 24
Finished Jul 18 07:24:11 PM PDT 24
Peak memory 218912 kb
Host smart-7f633a22-efaf-4186-9a09-c75d3c5757f3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762321296 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.3762321296
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.1461255523
Short name T486
Test name
Test status
Simulation time 27714083 ps
CPU time 0.87 seconds
Started Jul 18 07:24:10 PM PDT 24
Finished Jul 18 07:24:14 PM PDT 24
Peak memory 218384 kb
Host smart-71623ba7-efd7-4929-93a6-c2d3bf9e5808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461255523 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.1461255523
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.3520895433
Short name T368
Test name
Test status
Simulation time 69762634 ps
CPU time 1.4 seconds
Started Jul 18 07:24:10 PM PDT 24
Finished Jul 18 07:24:15 PM PDT 24
Peak memory 217584 kb
Host smart-2caa28e9-c762-4405-9b14-0384b2457f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520895433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.3520895433
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.627053331
Short name T450
Test name
Test status
Simulation time 38672452 ps
CPU time 0.92 seconds
Started Jul 18 07:24:08 PM PDT 24
Finished Jul 18 07:24:11 PM PDT 24
Peak memory 215868 kb
Host smart-f31724d4-5ea8-425c-8122-7cf8eeab83e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627053331 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.627053331
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.2752487780
Short name T505
Test name
Test status
Simulation time 88905626 ps
CPU time 0.91 seconds
Started Jul 18 07:24:07 PM PDT 24
Finished Jul 18 07:24:09 PM PDT 24
Peak memory 215388 kb
Host smart-cb388078-dc05-4dd4-812d-8b7c2b1cda53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752487780 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.2752487780
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.3840671275
Short name T338
Test name
Test status
Simulation time 357480961 ps
CPU time 2.78 seconds
Started Jul 18 07:24:07 PM PDT 24
Finished Jul 18 07:24:12 PM PDT 24
Peak memory 217608 kb
Host smart-e2559081-619a-47bc-b6bf-f616118deb0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840671275 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3840671275
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.589593682
Short name T513
Test name
Test status
Simulation time 105765344102 ps
CPU time 596.82 seconds
Started Jul 18 07:24:08 PM PDT 24
Finished Jul 18 07:34:07 PM PDT 24
Peak memory 220080 kb
Host smart-4556edd1-c228-437d-ae8f-a37f807de666
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589593682 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.589593682
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.2881189861
Short name T896
Test name
Test status
Simulation time 90138918 ps
CPU time 1.22 seconds
Started Jul 18 07:24:25 PM PDT 24
Finished Jul 18 07:24:28 PM PDT 24
Peak memory 218936 kb
Host smart-2a4bf2bd-fe91-4e7b-9fce-dbc4943df8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881189861 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.2881189861
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.979149070
Short name T921
Test name
Test status
Simulation time 254836724 ps
CPU time 1.13 seconds
Started Jul 18 07:24:24 PM PDT 24
Finished Jul 18 07:24:27 PM PDT 24
Peak memory 207076 kb
Host smart-4eed9219-6b25-4f22-a6c0-946bfe0320c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979149070 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.979149070
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.961719851
Short name T179
Test name
Test status
Simulation time 39699260 ps
CPU time 0.85 seconds
Started Jul 18 07:26:14 PM PDT 24
Finished Jul 18 07:26:17 PM PDT 24
Peak memory 216532 kb
Host smart-74a94d52-65c9-4dc0-a0a4-cd593e1a739b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961719851 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.961719851
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.3953822557
Short name T19
Test name
Test status
Simulation time 53787942 ps
CPU time 1.2 seconds
Started Jul 18 07:24:28 PM PDT 24
Finished Jul 18 07:24:36 PM PDT 24
Peak memory 218460 kb
Host smart-e0a7b882-883e-42e4-88e9-ac823e22d1aa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953822557 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.3953822557
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.1326032641
Short name T8
Test name
Test status
Simulation time 49161244 ps
CPU time 1.03 seconds
Started Jul 18 07:24:28 PM PDT 24
Finished Jul 18 07:24:34 PM PDT 24
Peak memory 221136 kb
Host smart-c693d823-e908-45b8-a2ed-8efc55923b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326032641 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.1326032641
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.1460947156
Short name T43
Test name
Test status
Simulation time 61666883 ps
CPU time 1.83 seconds
Started Jul 18 07:24:09 PM PDT 24
Finished Jul 18 07:24:15 PM PDT 24
Peak memory 219168 kb
Host smart-9b4f3b8f-3b03-47fa-86bc-56a0cb79395f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460947156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.1460947156
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.281497650
Short name T35
Test name
Test status
Simulation time 29422360 ps
CPU time 0.94 seconds
Started Jul 18 07:24:25 PM PDT 24
Finished Jul 18 07:24:28 PM PDT 24
Peak memory 216184 kb
Host smart-d9c8d77f-9fdd-4180-888a-c54a09da2b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281497650 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.281497650
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.3566443999
Short name T428
Test name
Test status
Simulation time 18981016 ps
CPU time 1.01 seconds
Started Jul 18 07:24:08 PM PDT 24
Finished Jul 18 07:24:11 PM PDT 24
Peak memory 215564 kb
Host smart-606db869-b5d2-42e2-a0b5-ade6e9a00ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566443999 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.3566443999
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.3895888806
Short name T726
Test name
Test status
Simulation time 888426667 ps
CPU time 5.14 seconds
Started Jul 18 07:24:09 PM PDT 24
Finished Jul 18 07:24:17 PM PDT 24
Peak memory 220880 kb
Host smart-29e1c301-74ef-403b-9edf-8c73b72921d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895888806 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.3895888806
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.3423402666
Short name T225
Test name
Test status
Simulation time 21005690186 ps
CPU time 486.46 seconds
Started Jul 18 07:24:08 PM PDT 24
Finished Jul 18 07:32:17 PM PDT 24
Peak memory 224000 kb
Host smart-ee957258-7a80-442f-8ebf-455e71525188
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423402666 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.3423402666
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.505706232
Short name T182
Test name
Test status
Simulation time 31158050 ps
CPU time 1.32 seconds
Started Jul 18 07:24:29 PM PDT 24
Finished Jul 18 07:24:36 PM PDT 24
Peak memory 220088 kb
Host smart-220f06cd-621b-47c9-b6cc-d3d830737378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505706232 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.505706232
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.99525153
Short name T386
Test name
Test status
Simulation time 27336421 ps
CPU time 0.92 seconds
Started Jul 18 07:24:26 PM PDT 24
Finished Jul 18 07:24:31 PM PDT 24
Peak memory 207276 kb
Host smart-b6a665e6-3654-4c7f-b75c-678117d40915
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99525153 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.99525153
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.2128779131
Short name T847
Test name
Test status
Simulation time 29040157 ps
CPU time 0.81 seconds
Started Jul 18 07:24:24 PM PDT 24
Finished Jul 18 07:24:26 PM PDT 24
Peak memory 215668 kb
Host smart-717f20b0-31d5-403e-bb39-4256891eddeb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128779131 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2128779131
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.3304325024
Short name T238
Test name
Test status
Simulation time 43934250 ps
CPU time 1.09 seconds
Started Jul 18 07:24:25 PM PDT 24
Finished Jul 18 07:24:30 PM PDT 24
Peak memory 218468 kb
Host smart-c7d3787c-a2f4-43e6-93b5-b7839bff16cf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304325024 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.3304325024
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.1334723815
Short name T13
Test name
Test status
Simulation time 36481410 ps
CPU time 0.96 seconds
Started Jul 18 07:24:26 PM PDT 24
Finished Jul 18 07:24:30 PM PDT 24
Peak memory 224124 kb
Host smart-5cb6976f-3f2d-4250-8a55-622acebc5841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334723815 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1334723815
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.1927330526
Short name T589
Test name
Test status
Simulation time 297284810 ps
CPU time 1.28 seconds
Started Jul 18 07:24:26 PM PDT 24
Finished Jul 18 07:24:31 PM PDT 24
Peak memory 217484 kb
Host smart-b449589a-65af-44a8-8290-b12bd54909a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927330526 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1927330526
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.3836474665
Short name T597
Test name
Test status
Simulation time 21822082 ps
CPU time 1.08 seconds
Started Jul 18 07:24:24 PM PDT 24
Finished Jul 18 07:24:28 PM PDT 24
Peak memory 215864 kb
Host smart-457a90cb-badf-4cd6-87c4-0abba906d558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836474665 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.3836474665
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.2493683603
Short name T864
Test name
Test status
Simulation time 23613251 ps
CPU time 0.92 seconds
Started Jul 18 07:24:29 PM PDT 24
Finished Jul 18 07:24:36 PM PDT 24
Peak memory 215564 kb
Host smart-4f0bed6a-97c3-4112-bc7f-febe0288659f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493683603 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.2493683603
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.3883563877
Short name T702
Test name
Test status
Simulation time 514624274 ps
CPU time 3.2 seconds
Started Jul 18 07:24:24 PM PDT 24
Finished Jul 18 07:24:30 PM PDT 24
Peak memory 215576 kb
Host smart-21cc135e-3beb-4747-a5c7-3c3d23c3b594
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883563877 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.3883563877
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.649827933
Short name T992
Test name
Test status
Simulation time 151135502896 ps
CPU time 1985.62 seconds
Started Jul 18 07:24:26 PM PDT 24
Finished Jul 18 07:57:36 PM PDT 24
Peak memory 229888 kb
Host smart-fce83669-d856-450a-b993-ce9667abddf2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649827933 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.649827933
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.2928622708
Short name T246
Test name
Test status
Simulation time 92845677 ps
CPU time 1.29 seconds
Started Jul 18 07:24:25 PM PDT 24
Finished Jul 18 07:24:29 PM PDT 24
Peak memory 220988 kb
Host smart-183b29fe-c979-4c76-8b8c-99b31601ec0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928622708 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.2928622708
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.628344685
Short name T612
Test name
Test status
Simulation time 39382065 ps
CPU time 0.84 seconds
Started Jul 18 07:24:26 PM PDT 24
Finished Jul 18 07:24:31 PM PDT 24
Peak memory 206872 kb
Host smart-46f0e867-3893-4ad7-8eac-dfa185d0b44d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628344685 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.628344685
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.1009324809
Short name T195
Test name
Test status
Simulation time 10931589 ps
CPU time 0.88 seconds
Started Jul 18 07:24:25 PM PDT 24
Finished Jul 18 07:24:29 PM PDT 24
Peak memory 216528 kb
Host smart-27f183ac-4689-4eb2-976d-8ce9740cbcf5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009324809 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1009324809
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.186404686
Short name T514
Test name
Test status
Simulation time 55722039 ps
CPU time 1.29 seconds
Started Jul 18 07:24:26 PM PDT 24
Finished Jul 18 07:24:31 PM PDT 24
Peak memory 217224 kb
Host smart-03d146f9-418b-47eb-8919-9cb2742f6ab7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186404686 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_di
sable_auto_req_mode.186404686
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.3537348336
Short name T200
Test name
Test status
Simulation time 79787182 ps
CPU time 1.04 seconds
Started Jul 18 07:24:27 PM PDT 24
Finished Jul 18 07:24:33 PM PDT 24
Peak memory 219828 kb
Host smart-a47f3708-0a63-42c0-b61e-18ed25c72dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537348336 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.3537348336
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.2480406348
Short name T615
Test name
Test status
Simulation time 41491589 ps
CPU time 1.47 seconds
Started Jul 18 07:24:24 PM PDT 24
Finished Jul 18 07:24:28 PM PDT 24
Peak memory 220324 kb
Host smart-a290b7bb-fd5c-4684-a96a-a72cb412ffa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480406348 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.2480406348
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.4257610646
Short name T711
Test name
Test status
Simulation time 21686762 ps
CPU time 1.09 seconds
Started Jul 18 07:24:25 PM PDT 24
Finished Jul 18 07:24:30 PM PDT 24
Peak memory 216124 kb
Host smart-2dd56105-3cf4-45da-af54-dbdb5e446fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257610646 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.4257610646
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.1960628258
Short name T902
Test name
Test status
Simulation time 121179892 ps
CPU time 0.95 seconds
Started Jul 18 07:24:23 PM PDT 24
Finished Jul 18 07:24:24 PM PDT 24
Peak memory 215560 kb
Host smart-74e66ea1-c933-489b-9445-e12c3d9a6748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960628258 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.1960628258
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.967108210
Short name T575
Test name
Test status
Simulation time 113460805 ps
CPU time 2.57 seconds
Started Jul 18 07:24:28 PM PDT 24
Finished Jul 18 07:24:37 PM PDT 24
Peak memory 215756 kb
Host smart-94145bf1-2f15-462d-b555-620f7d76bebd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967108210 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.967108210
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.1371787037
Short name T508
Test name
Test status
Simulation time 102762802971 ps
CPU time 2057.27 seconds
Started Jul 18 07:24:26 PM PDT 24
Finished Jul 18 07:58:48 PM PDT 24
Peak memory 230428 kb
Host smart-f7acdb47-ff1d-4df0-97c9-36bb78949c54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371787037 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.1371787037
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.3082644706
Short name T445
Test name
Test status
Simulation time 22627658 ps
CPU time 1.27 seconds
Started Jul 18 07:24:26 PM PDT 24
Finished Jul 18 07:24:32 PM PDT 24
Peak memory 219812 kb
Host smart-5e105a1f-cbcc-47e1-9f62-413ba7002020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082644706 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3082644706
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.187803087
Short name T790
Test name
Test status
Simulation time 12582387 ps
CPU time 0.89 seconds
Started Jul 18 07:24:26 PM PDT 24
Finished Jul 18 07:24:32 PM PDT 24
Peak memory 215472 kb
Host smart-c466c01a-fe29-40a2-a2a8-5cf4b2e5a183
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187803087 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.187803087
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.625643043
Short name T961
Test name
Test status
Simulation time 40112532 ps
CPU time 0.84 seconds
Started Jul 18 07:24:27 PM PDT 24
Finished Jul 18 07:24:33 PM PDT 24
Peak memory 215676 kb
Host smart-094aee1b-7aa6-4210-b585-f7452e565520
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625643043 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.625643043
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.3334340669
Short name T797
Test name
Test status
Simulation time 46441407 ps
CPU time 1.1 seconds
Started Jul 18 07:24:25 PM PDT 24
Finished Jul 18 07:24:29 PM PDT 24
Peak memory 218720 kb
Host smart-97640510-8d0e-462d-89d2-d14ab7d8eda5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334340669 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.3334340669
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.1874562099
Short name T154
Test name
Test status
Simulation time 33637767 ps
CPU time 0.84 seconds
Started Jul 18 07:24:25 PM PDT 24
Finished Jul 18 07:24:29 PM PDT 24
Peak memory 218664 kb
Host smart-b3de73d5-0b07-435f-8ea0-a472fca86da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874562099 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.1874562099
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.2581534493
Short name T334
Test name
Test status
Simulation time 53468727 ps
CPU time 1.58 seconds
Started Jul 18 07:24:29 PM PDT 24
Finished Jul 18 07:24:37 PM PDT 24
Peak memory 218828 kb
Host smart-7d08d69d-f85e-4769-bb24-18040c3ef9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581534493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2581534493
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.4201971615
Short name T99
Test name
Test status
Simulation time 28934316 ps
CPU time 0.9 seconds
Started Jul 18 07:24:23 PM PDT 24
Finished Jul 18 07:24:25 PM PDT 24
Peak memory 216280 kb
Host smart-af9bfe11-a033-4abd-ac36-718ca64404a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201971615 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.4201971615
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.2139112434
Short name T345
Test name
Test status
Simulation time 70487499 ps
CPU time 0.92 seconds
Started Jul 18 07:24:27 PM PDT 24
Finished Jul 18 07:24:33 PM PDT 24
Peak memory 215588 kb
Host smart-7acecf69-c66c-415d-843a-4ecb6592a70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139112434 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.2139112434
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.4060116355
Short name T333
Test name
Test status
Simulation time 105310395 ps
CPU time 2.68 seconds
Started Jul 18 07:24:26 PM PDT 24
Finished Jul 18 07:24:32 PM PDT 24
Peak memory 215564 kb
Host smart-3f663ec0-7d82-496c-9e89-cfffcd0ffeca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060116355 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.4060116355
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.2868288585
Short name T988
Test name
Test status
Simulation time 76772841624 ps
CPU time 866.27 seconds
Started Jul 18 07:24:28 PM PDT 24
Finished Jul 18 07:39:00 PM PDT 24
Peak memory 223976 kb
Host smart-7063f061-18d3-48ae-8b7f-4cded86fbf09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868288585 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.2868288585
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.4099027282
Short name T451
Test name
Test status
Simulation time 49199691 ps
CPU time 1.27 seconds
Started Jul 18 07:24:25 PM PDT 24
Finished Jul 18 07:24:29 PM PDT 24
Peak memory 219056 kb
Host smart-8a4ca339-62f2-4b65-8411-b43449c10b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099027282 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.4099027282
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.964701486
Short name T393
Test name
Test status
Simulation time 27360748 ps
CPU time 1.02 seconds
Started Jul 18 07:24:28 PM PDT 24
Finished Jul 18 07:24:36 PM PDT 24
Peak memory 207072 kb
Host smart-b17bddc1-01f9-4058-8bc0-43c7d7cdf274
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964701486 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.964701486
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.3625461024
Short name T429
Test name
Test status
Simulation time 32410107 ps
CPU time 0.84 seconds
Started Jul 18 07:24:23 PM PDT 24
Finished Jul 18 07:24:26 PM PDT 24
Peak memory 216240 kb
Host smart-767df609-897e-4f36-8723-1581dfa791f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625461024 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.3625461024
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.116295096
Short name T272
Test name
Test status
Simulation time 46327905 ps
CPU time 1.17 seconds
Started Jul 18 07:24:28 PM PDT 24
Finished Jul 18 07:24:36 PM PDT 24
Peak memory 220012 kb
Host smart-5363c901-50e5-4a66-98c7-88845e8fce61
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116295096 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_di
sable_auto_req_mode.116295096
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.2310311175
Short name T886
Test name
Test status
Simulation time 25227308 ps
CPU time 1.02 seconds
Started Jul 18 07:24:24 PM PDT 24
Finished Jul 18 07:24:27 PM PDT 24
Peak memory 220216 kb
Host smart-9df0c01b-df13-4dfe-b6e6-85106eeca4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310311175 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.2310311175
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.4105379857
Short name T448
Test name
Test status
Simulation time 42893932 ps
CPU time 1.3 seconds
Started Jul 18 07:24:29 PM PDT 24
Finished Jul 18 07:24:36 PM PDT 24
Peak memory 218756 kb
Host smart-32ad0507-d964-4f09-a783-2bf70f4067fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105379857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.4105379857
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.533051179
Short name T36
Test name
Test status
Simulation time 36269369 ps
CPU time 0.92 seconds
Started Jul 18 07:24:28 PM PDT 24
Finished Jul 18 07:24:34 PM PDT 24
Peak memory 215920 kb
Host smart-3ea62862-6bf3-459d-8e9f-9500730bb733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533051179 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.533051179
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.1198614647
Short name T421
Test name
Test status
Simulation time 38626677 ps
CPU time 0.89 seconds
Started Jul 18 07:24:28 PM PDT 24
Finished Jul 18 07:24:34 PM PDT 24
Peak memory 215728 kb
Host smart-64ecb078-9b14-424b-936f-e6da766485fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198614647 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1198614647
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.3393449773
Short name T425
Test name
Test status
Simulation time 723159800 ps
CPU time 4.21 seconds
Started Jul 18 07:24:26 PM PDT 24
Finished Jul 18 07:24:33 PM PDT 24
Peak memory 217588 kb
Host smart-c194c04b-40cd-4dbc-9fd5-9d08e9c823e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393449773 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3393449773
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.1270985479
Short name T738
Test name
Test status
Simulation time 46356806567 ps
CPU time 1230.44 seconds
Started Jul 18 07:24:25 PM PDT 24
Finished Jul 18 07:44:59 PM PDT 24
Peak memory 221696 kb
Host smart-4f43a4d5-e0ca-4352-9a79-b38881854117
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270985479 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.1270985479
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.1574295696
Short name T106
Test name
Test status
Simulation time 62864392 ps
CPU time 1.12 seconds
Started Jul 18 07:21:43 PM PDT 24
Finished Jul 18 07:21:47 PM PDT 24
Peak memory 220964 kb
Host smart-87cb5c82-4feb-4c00-ae1b-35e430c1aff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574295696 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.1574295696
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.1536235660
Short name T735
Test name
Test status
Simulation time 26181932 ps
CPU time 0.95 seconds
Started Jul 18 07:21:43 PM PDT 24
Finished Jul 18 07:21:47 PM PDT 24
Peak memory 215220 kb
Host smart-b30e5c4f-acae-4b3b-b561-1e68aa418f8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536235660 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.1536235660
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.2000913918
Short name T557
Test name
Test status
Simulation time 12395556 ps
CPU time 0.86 seconds
Started Jul 18 07:21:42 PM PDT 24
Finished Jul 18 07:21:44 PM PDT 24
Peak memory 216684 kb
Host smart-acaaccb2-014a-4b4a-bc53-862dbe7dc7ab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000913918 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.2000913918
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.701130756
Short name T828
Test name
Test status
Simulation time 44944614 ps
CPU time 1.14 seconds
Started Jul 18 07:21:45 PM PDT 24
Finished Jul 18 07:21:49 PM PDT 24
Peak memory 220012 kb
Host smart-d62cd51c-83d4-4c5d-be4d-071b8b7461d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701130756 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_dis
able_auto_req_mode.701130756
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.4227594282
Short name T185
Test name
Test status
Simulation time 24683923 ps
CPU time 1.06 seconds
Started Jul 18 07:21:48 PM PDT 24
Finished Jul 18 07:21:51 PM PDT 24
Peak memory 229844 kb
Host smart-fbba8cd9-8136-4306-8dd1-a6f985edc9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227594282 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.4227594282
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.2854510669
Short name T414
Test name
Test status
Simulation time 32642924 ps
CPU time 1.31 seconds
Started Jul 18 07:21:43 PM PDT 24
Finished Jul 18 07:21:47 PM PDT 24
Peak memory 217572 kb
Host smart-e2b27f36-532a-42e3-aec3-3473697bd265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854510669 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.2854510669
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.2914049240
Short name T56
Test name
Test status
Simulation time 33320910 ps
CPU time 1 seconds
Started Jul 18 07:21:44 PM PDT 24
Finished Jul 18 07:21:48 PM PDT 24
Peak memory 224368 kb
Host smart-5d7d3bb3-56cc-4bc6-9f2a-52fda5f820ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914049240 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.2914049240
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.135123571
Short name T23
Test name
Test status
Simulation time 23054193 ps
CPU time 0.95 seconds
Started Jul 18 07:21:42 PM PDT 24
Finished Jul 18 07:21:45 PM PDT 24
Peak memory 207384 kb
Host smart-10cfa296-a4d6-4889-ad2a-9c4f5f9c06e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135123571 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.135123571
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.3649959892
Short name T17
Test name
Test status
Simulation time 416823295 ps
CPU time 4 seconds
Started Jul 18 07:21:42 PM PDT 24
Finished Jul 18 07:21:48 PM PDT 24
Peak memory 235612 kb
Host smart-2500bca8-ef2b-4d12-bae4-47e2e965463e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649959892 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.3649959892
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.2904403344
Short name T732
Test name
Test status
Simulation time 24861244 ps
CPU time 0.91 seconds
Started Jul 18 07:21:44 PM PDT 24
Finished Jul 18 07:21:48 PM PDT 24
Peak memory 207372 kb
Host smart-abfa7772-5a9e-4d1c-9536-47824fae5caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904403344 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.2904403344
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.4257374285
Short name T72
Test name
Test status
Simulation time 66383979 ps
CPU time 1.04 seconds
Started Jul 18 07:21:48 PM PDT 24
Finished Jul 18 07:21:51 PM PDT 24
Peak memory 207176 kb
Host smart-5faa2f58-ba88-4e49-9b6d-ff996b17fcfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257374285 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.4257374285
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.778550198
Short name T400
Test name
Test status
Simulation time 164663040554 ps
CPU time 960.48 seconds
Started Jul 18 07:21:42 PM PDT 24
Finished Jul 18 07:37:44 PM PDT 24
Peak memory 222704 kb
Host smart-767426bc-2425-4059-b309-5b3231362e5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778550198 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.778550198
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.418226372
Short name T918
Test name
Test status
Simulation time 49741173 ps
CPU time 1.19 seconds
Started Jul 18 07:24:27 PM PDT 24
Finished Jul 18 07:24:33 PM PDT 24
Peak memory 220408 kb
Host smart-a6e08416-1cf4-4f86-ad20-4b960360ca34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418226372 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.418226372
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.2041762610
Short name T946
Test name
Test status
Simulation time 15521545 ps
CPU time 0.93 seconds
Started Jul 18 07:24:26 PM PDT 24
Finished Jul 18 07:24:32 PM PDT 24
Peak memory 207064 kb
Host smart-32e39d56-52dd-4398-8b0c-ea204b861c70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041762610 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.2041762610
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.82137266
Short name T432
Test name
Test status
Simulation time 74863938 ps
CPU time 0.79 seconds
Started Jul 18 07:24:27 PM PDT 24
Finished Jul 18 07:24:32 PM PDT 24
Peak memory 216136 kb
Host smart-29add329-7a73-4dbd-8815-9b86c424d138
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82137266 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.82137266
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.2010578988
Short name T537
Test name
Test status
Simulation time 51321644 ps
CPU time 1.04 seconds
Started Jul 18 07:24:26 PM PDT 24
Finished Jul 18 07:24:31 PM PDT 24
Peak memory 218552 kb
Host smart-0da74421-147a-425e-8f7b-c802ddb476fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010578988 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.2010578988
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.2872625899
Short name T52
Test name
Test status
Simulation time 20019254 ps
CPU time 1.14 seconds
Started Jul 18 07:24:28 PM PDT 24
Finished Jul 18 07:24:35 PM PDT 24
Peak memory 224296 kb
Host smart-d2b76a74-9d9a-44ed-8836-b8705ccd3776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872625899 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.2872625899
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.3200780025
Short name T49
Test name
Test status
Simulation time 63570289 ps
CPU time 1.23 seconds
Started Jul 18 07:24:29 PM PDT 24
Finished Jul 18 07:24:36 PM PDT 24
Peak memory 217644 kb
Host smart-5a8e7101-be34-4a82-b172-7ba66a72dfec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200780025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.3200780025
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.838286666
Short name T723
Test name
Test status
Simulation time 22103722 ps
CPU time 1.15 seconds
Started Jul 18 07:24:26 PM PDT 24
Finished Jul 18 07:24:32 PM PDT 24
Peak memory 215704 kb
Host smart-efece17e-8795-4de5-95c8-e8329fe4ddc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838286666 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.838286666
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.2591951543
Short name T818
Test name
Test status
Simulation time 16792030 ps
CPU time 1 seconds
Started Jul 18 07:24:24 PM PDT 24
Finished Jul 18 07:24:27 PM PDT 24
Peak memory 215568 kb
Host smart-3e7e790c-951a-4081-9b78-fba2bfeb4f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591951543 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.2591951543
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.999376826
Short name T298
Test name
Test status
Simulation time 843483385 ps
CPU time 4.31 seconds
Started Jul 18 07:24:26 PM PDT 24
Finished Jul 18 07:24:34 PM PDT 24
Peak memory 215628 kb
Host smart-32a594df-d6c2-43d1-8b0a-5c33b1a58700
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999376826 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.999376826
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2240485606
Short name T102
Test name
Test status
Simulation time 68938326638 ps
CPU time 844.02 seconds
Started Jul 18 07:24:25 PM PDT 24
Finished Jul 18 07:38:33 PM PDT 24
Peak memory 221152 kb
Host smart-c281e71a-00c3-47e3-ad55-0cd93d74eda2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240485606 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.2240485606
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.1813725579
Short name T174
Test name
Test status
Simulation time 47225667 ps
CPU time 1.13 seconds
Started Jul 18 07:24:25 PM PDT 24
Finished Jul 18 07:24:30 PM PDT 24
Peak memory 219480 kb
Host smart-2865530a-6c59-4ecf-b133-080e5ede32ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813725579 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.1813725579
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.3217677454
Short name T51
Test name
Test status
Simulation time 22924283 ps
CPU time 0.84 seconds
Started Jul 18 07:24:28 PM PDT 24
Finished Jul 18 07:24:34 PM PDT 24
Peak memory 207060 kb
Host smart-9f482ec6-663a-45d8-8ef1-55206a5abc2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217677454 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.3217677454
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.1767807218
Short name T204
Test name
Test status
Simulation time 65612791 ps
CPU time 0.87 seconds
Started Jul 18 07:24:28 PM PDT 24
Finished Jul 18 07:24:34 PM PDT 24
Peak memory 216488 kb
Host smart-cea4c44c-9584-4bb2-8921-d6324aa47cfc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767807218 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.1767807218
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.2310602829
Short name T982
Test name
Test status
Simulation time 86063900 ps
CPU time 1.03 seconds
Started Jul 18 07:24:28 PM PDT 24
Finished Jul 18 07:24:35 PM PDT 24
Peak memory 217192 kb
Host smart-fbd4eb05-c8ba-4d79-8d69-69875ad2cd13
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310602829 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.2310602829
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.200072256
Short name T194
Test name
Test status
Simulation time 18286074 ps
CPU time 1.04 seconds
Started Jul 18 07:24:28 PM PDT 24
Finished Jul 18 07:24:34 PM PDT 24
Peak memory 218564 kb
Host smart-a310f116-1c06-42a3-a8a4-b875c03a04d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200072256 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.200072256
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.409339869
Short name T689
Test name
Test status
Simulation time 131881326 ps
CPU time 1.49 seconds
Started Jul 18 07:24:25 PM PDT 24
Finished Jul 18 07:24:29 PM PDT 24
Peak memory 220256 kb
Host smart-6ab31be5-e1e7-4cc2-a24b-ac6880c87eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409339869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.409339869
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.2777466819
Short name T29
Test name
Test status
Simulation time 23265364 ps
CPU time 0.94 seconds
Started Jul 18 07:24:27 PM PDT 24
Finished Jul 18 07:24:32 PM PDT 24
Peak memory 216156 kb
Host smart-b373b78b-73e8-463b-832c-e52a2ad97eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777466819 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2777466819
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.305108783
Short name T827
Test name
Test status
Simulation time 52001617 ps
CPU time 0.95 seconds
Started Jul 18 07:24:24 PM PDT 24
Finished Jul 18 07:24:27 PM PDT 24
Peak memory 215580 kb
Host smart-dc21e139-e692-4f7b-ad64-0d99b2e6df83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305108783 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.305108783
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.3646379054
Short name T936
Test name
Test status
Simulation time 495359000 ps
CPU time 5.46 seconds
Started Jul 18 07:24:28 PM PDT 24
Finished Jul 18 07:24:39 PM PDT 24
Peak memory 215664 kb
Host smart-5e3dda01-5ea0-474e-b1f7-fe68a438ad58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646379054 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3646379054
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.89702747
Short name T224
Test name
Test status
Simulation time 288957544456 ps
CPU time 1320.33 seconds
Started Jul 18 07:24:28 PM PDT 24
Finished Jul 18 07:46:35 PM PDT 24
Peak memory 224288 kb
Host smart-b743036d-5946-42cb-81d3-af6ff02ee9aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89702747 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.89702747
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.2475832071
Short name T935
Test name
Test status
Simulation time 88790563 ps
CPU time 1.29 seconds
Started Jul 18 07:24:27 PM PDT 24
Finished Jul 18 07:24:33 PM PDT 24
Peak memory 219988 kb
Host smart-54c1ec2b-2ede-4d86-bcbb-bd6693765986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475832071 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.2475832071
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.3792079063
Short name T497
Test name
Test status
Simulation time 186678373 ps
CPU time 0.92 seconds
Started Jul 18 07:24:39 PM PDT 24
Finished Jul 18 07:24:42 PM PDT 24
Peak memory 207040 kb
Host smart-5cfcfbfb-3571-40ab-8fce-0b28ef85c883
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792079063 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.3792079063
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.1360307614
Short name T119
Test name
Test status
Simulation time 74684991 ps
CPU time 0.99 seconds
Started Jul 18 07:24:28 PM PDT 24
Finished Jul 18 07:24:34 PM PDT 24
Peak memory 217128 kb
Host smart-03cbd02c-7560-45a5-9577-f1a367525e4c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360307614 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.1360307614
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.1813712329
Short name T114
Test name
Test status
Simulation time 30983135 ps
CPU time 1.13 seconds
Started Jul 18 07:24:28 PM PDT 24
Finished Jul 18 07:24:35 PM PDT 24
Peak memory 230212 kb
Host smart-74e101a9-7b9f-450f-b546-91b6addeb24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813712329 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.1813712329
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.4111333767
Short name T399
Test name
Test status
Simulation time 33210794 ps
CPU time 1.31 seconds
Started Jul 18 07:24:27 PM PDT 24
Finished Jul 18 07:24:33 PM PDT 24
Peak memory 218832 kb
Host smart-0d96ea4c-643d-495d-9b69-935ad1624c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111333767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.4111333767
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.1101280778
Short name T664
Test name
Test status
Simulation time 20035132 ps
CPU time 1.15 seconds
Started Jul 18 07:24:28 PM PDT 24
Finished Jul 18 07:24:34 PM PDT 24
Peak memory 216172 kb
Host smart-82de1815-b35a-423f-aeba-1374e89973d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101280778 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.1101280778
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.3767223714
Short name T777
Test name
Test status
Simulation time 15127493 ps
CPU time 0.96 seconds
Started Jul 18 07:24:27 PM PDT 24
Finished Jul 18 07:24:33 PM PDT 24
Peak memory 207288 kb
Host smart-5b104bb3-9af7-4669-a7c7-edb7d7cd0d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767223714 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3767223714
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.2392943832
Short name T5
Test name
Test status
Simulation time 610306302 ps
CPU time 3.54 seconds
Started Jul 18 07:24:26 PM PDT 24
Finished Jul 18 07:24:34 PM PDT 24
Peak memory 219936 kb
Host smart-32425b44-0b65-417c-bfc2-2c50e6e55c9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392943832 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2392943832
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.382383357
Short name T226
Test name
Test status
Simulation time 70175470878 ps
CPU time 1572 seconds
Started Jul 18 07:24:28 PM PDT 24
Finished Jul 18 07:50:45 PM PDT 24
Peak memory 224244 kb
Host smart-2dfc6f3f-cdd1-42e8-8a18-8fc4478c97a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382383357 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.382383357
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.187340709
Short name T785
Test name
Test status
Simulation time 86866662 ps
CPU time 1.04 seconds
Started Jul 18 07:24:42 PM PDT 24
Finished Jul 18 07:24:45 PM PDT 24
Peak memory 219104 kb
Host smart-5516c160-79bb-40e9-a374-aa018e88e4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187340709 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.187340709
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.4025274373
Short name T652
Test name
Test status
Simulation time 14729622 ps
CPU time 0.86 seconds
Started Jul 18 07:24:42 PM PDT 24
Finished Jul 18 07:24:45 PM PDT 24
Peak memory 207036 kb
Host smart-ca87ccd2-d08d-4275-afa3-42c39a97d8ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025274373 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.4025274373
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.2896100693
Short name T170
Test name
Test status
Simulation time 12039827 ps
CPU time 0.87 seconds
Started Jul 18 07:24:41 PM PDT 24
Finished Jul 18 07:24:44 PM PDT 24
Peak memory 216696 kb
Host smart-a7de47bb-6742-4efc-9b72-4eef716c260f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896100693 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2896100693
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_err.3404125952
Short name T678
Test name
Test status
Simulation time 19846324 ps
CPU time 1.16 seconds
Started Jul 18 07:24:43 PM PDT 24
Finished Jul 18 07:24:46 PM PDT 24
Peak memory 224364 kb
Host smart-0fc653e3-ef2b-4731-a09e-e6862cbb05ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404125952 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.3404125952
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.1270735427
Short name T776
Test name
Test status
Simulation time 66488413 ps
CPU time 1.24 seconds
Started Jul 18 07:24:37 PM PDT 24
Finished Jul 18 07:24:41 PM PDT 24
Peak memory 218928 kb
Host smart-c9dff198-023c-4f1c-828c-7c2ace2cb3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270735427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.1270735427
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.304238637
Short name T98
Test name
Test status
Simulation time 27831162 ps
CPU time 0.85 seconds
Started Jul 18 07:24:39 PM PDT 24
Finished Jul 18 07:24:42 PM PDT 24
Peak memory 216000 kb
Host smart-42cdc38c-f83a-48b8-adc3-d36417eda7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304238637 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.304238637
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.3610566533
Short name T705
Test name
Test status
Simulation time 115502620 ps
CPU time 0.96 seconds
Started Jul 18 07:24:38 PM PDT 24
Finished Jul 18 07:24:42 PM PDT 24
Peak memory 215528 kb
Host smart-6694efbd-4e9e-469e-a9bb-22284e5bafab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610566533 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.3610566533
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.754809529
Short name T241
Test name
Test status
Simulation time 472181629 ps
CPU time 2.87 seconds
Started Jul 18 07:24:38 PM PDT 24
Finished Jul 18 07:24:44 PM PDT 24
Peak memory 215508 kb
Host smart-d4bb380d-68ff-44b9-9f72-83e477fd1da3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754809529 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.754809529
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.120930088
Short name T221
Test name
Test status
Simulation time 79740055810 ps
CPU time 885.16 seconds
Started Jul 18 07:24:41 PM PDT 24
Finished Jul 18 07:39:28 PM PDT 24
Peak memory 224052 kb
Host smart-41aa7874-6ca0-40c5-a88b-f77d9d2b47c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120930088 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.120930088
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.656249663
Short name T973
Test name
Test status
Simulation time 40506965 ps
CPU time 1.16 seconds
Started Jul 18 07:24:39 PM PDT 24
Finished Jul 18 07:24:43 PM PDT 24
Peak memory 220544 kb
Host smart-1a8c0388-a3b0-4a57-bae6-2530b04c4878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656249663 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.656249663
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.733344173
Short name T339
Test name
Test status
Simulation time 35936621 ps
CPU time 0.87 seconds
Started Jul 18 07:24:43 PM PDT 24
Finished Jul 18 07:24:47 PM PDT 24
Peak memory 207020 kb
Host smart-315aaef8-afcc-4460-bfc2-ca7d11d9e694
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733344173 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.733344173
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.4016356832
Short name T207
Test name
Test status
Simulation time 15137934 ps
CPU time 0.86 seconds
Started Jul 18 07:24:38 PM PDT 24
Finished Jul 18 07:24:42 PM PDT 24
Peak memory 215760 kb
Host smart-2af31da6-bf49-4833-b904-960356708486
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016356832 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.4016356832
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.2595081073
Short name T755
Test name
Test status
Simulation time 41812049 ps
CPU time 1.37 seconds
Started Jul 18 07:24:46 PM PDT 24
Finished Jul 18 07:24:51 PM PDT 24
Peak memory 218720 kb
Host smart-e90ca460-8a76-4076-a16e-c82e12518fa0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595081073 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.2595081073
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.232252638
Short name T773
Test name
Test status
Simulation time 23905473 ps
CPU time 0.95 seconds
Started Jul 18 07:24:43 PM PDT 24
Finished Jul 18 07:24:46 PM PDT 24
Peak memory 218900 kb
Host smart-7f16195e-6370-4507-933c-8bb444f63b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232252638 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.232252638
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.4288094181
Short name T823
Test name
Test status
Simulation time 80520423 ps
CPU time 1.21 seconds
Started Jul 18 07:24:38 PM PDT 24
Finished Jul 18 07:24:42 PM PDT 24
Peak memory 217668 kb
Host smart-b99bee2d-e520-48b1-ab9a-d373c62fbd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288094181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.4288094181
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.3183919619
Short name T381
Test name
Test status
Simulation time 67142724 ps
CPU time 0.83 seconds
Started Jul 18 07:24:46 PM PDT 24
Finished Jul 18 07:24:50 PM PDT 24
Peak memory 215696 kb
Host smart-ef5283db-cd2d-4bc7-adb2-792a6f142c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183919619 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.3183919619
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.519851041
Short name T826
Test name
Test status
Simulation time 51068170 ps
CPU time 0.91 seconds
Started Jul 18 07:24:37 PM PDT 24
Finished Jul 18 07:24:41 PM PDT 24
Peak memory 215560 kb
Host smart-2819f225-e41a-4fe2-a96b-0a2888334405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519851041 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.519851041
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.1589148406
Short name T834
Test name
Test status
Simulation time 368513330 ps
CPU time 2.37 seconds
Started Jul 18 07:24:43 PM PDT 24
Finished Jul 18 07:24:47 PM PDT 24
Peak memory 215540 kb
Host smart-151ead2c-f71f-4dea-8803-b705617544f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589148406 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1589148406
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2159628607
Short name T218
Test name
Test status
Simulation time 48247602818 ps
CPU time 1234.8 seconds
Started Jul 18 07:24:41 PM PDT 24
Finished Jul 18 07:45:18 PM PDT 24
Peak memory 221632 kb
Host smart-9784a3ab-87f7-4804-b8a1-5e586aa4b614
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159628607 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2159628607
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.1460253103
Short name T214
Test name
Test status
Simulation time 98541507 ps
CPU time 1.32 seconds
Started Jul 18 07:24:44 PM PDT 24
Finished Jul 18 07:24:48 PM PDT 24
Peak memory 220224 kb
Host smart-580c6f90-960b-4e64-a8dc-c32cae7776f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460253103 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.1460253103
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.1983943666
Short name T517
Test name
Test status
Simulation time 59975691 ps
CPU time 1.03 seconds
Started Jul 18 07:24:43 PM PDT 24
Finished Jul 18 07:24:47 PM PDT 24
Peak memory 207152 kb
Host smart-8224e146-2a2f-457c-87b0-8a3794f462ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983943666 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.1983943666
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.13193487
Short name T725
Test name
Test status
Simulation time 13537206 ps
CPU time 1 seconds
Started Jul 18 07:24:44 PM PDT 24
Finished Jul 18 07:24:47 PM PDT 24
Peak memory 216544 kb
Host smart-5269be95-c877-4f0e-a13d-cf738883d96f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13193487 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.13193487
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.2674416232
Short name T203
Test name
Test status
Simulation time 34785768 ps
CPU time 1.11 seconds
Started Jul 18 07:24:37 PM PDT 24
Finished Jul 18 07:24:41 PM PDT 24
Peak memory 217036 kb
Host smart-b969ff19-8125-476d-9226-30aa8d756c07
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674416232 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.2674416232
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.2479831896
Short name T177
Test name
Test status
Simulation time 22654856 ps
CPU time 1.06 seconds
Started Jul 18 07:24:44 PM PDT 24
Finished Jul 18 07:24:47 PM PDT 24
Peak memory 224368 kb
Host smart-6f38e443-d8da-4690-b065-9748cc244def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479831896 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.2479831896
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.4174073543
Short name T86
Test name
Test status
Simulation time 59878270 ps
CPU time 1.33 seconds
Started Jul 18 07:24:39 PM PDT 24
Finished Jul 18 07:24:44 PM PDT 24
Peak memory 218856 kb
Host smart-1f1ad74c-5079-4e83-8b50-d8972efbe5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174073543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.4174073543
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.3085115201
Short name T580
Test name
Test status
Simulation time 20359530 ps
CPU time 1.11 seconds
Started Jul 18 07:24:37 PM PDT 24
Finished Jul 18 07:24:41 PM PDT 24
Peak memory 216240 kb
Host smart-0c2ccf28-cfbb-40fd-898c-e55c1ef667f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085115201 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.3085115201
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.606612327
Short name T623
Test name
Test status
Simulation time 39674443 ps
CPU time 0.91 seconds
Started Jul 18 07:24:41 PM PDT 24
Finished Jul 18 07:24:44 PM PDT 24
Peak memory 215560 kb
Host smart-ee4dbbb2-5358-468a-b7a3-ad7f690513ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606612327 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.606612327
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.3628431072
Short name T878
Test name
Test status
Simulation time 1016877428 ps
CPU time 5.67 seconds
Started Jul 18 07:24:38 PM PDT 24
Finished Jul 18 07:24:46 PM PDT 24
Peak memory 217628 kb
Host smart-d093c2f5-589a-40d9-8156-9bf8c8d67918
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628431072 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.3628431072
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.908290051
Short name T418
Test name
Test status
Simulation time 151111966436 ps
CPU time 860.68 seconds
Started Jul 18 07:24:38 PM PDT 24
Finished Jul 18 07:39:01 PM PDT 24
Peak memory 223332 kb
Host smart-c5ecf189-8087-4453-b263-610acd5dcaa8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908290051 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.908290051
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.2710542719
Short name T247
Test name
Test status
Simulation time 56185028 ps
CPU time 1.3 seconds
Started Jul 18 07:24:38 PM PDT 24
Finished Jul 18 07:24:42 PM PDT 24
Peak memory 220072 kb
Host smart-a363f1e3-7fc0-427f-b408-6f40cc71c692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710542719 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.2710542719
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.2347964372
Short name T691
Test name
Test status
Simulation time 16253424 ps
CPU time 0.94 seconds
Started Jul 18 07:24:42 PM PDT 24
Finished Jul 18 07:24:45 PM PDT 24
Peak memory 215220 kb
Host smart-362a7b7b-7f87-40e5-98d2-86f226c944a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347964372 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2347964372
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.1860343854
Short name T815
Test name
Test status
Simulation time 12744451 ps
CPU time 0.89 seconds
Started Jul 18 07:24:42 PM PDT 24
Finished Jul 18 07:24:45 PM PDT 24
Peak memory 216376 kb
Host smart-198600dd-e536-402a-a7a5-952487398fb9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860343854 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.1860343854
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.2733955975
Short name T791
Test name
Test status
Simulation time 139859997 ps
CPU time 0.97 seconds
Started Jul 18 07:24:38 PM PDT 24
Finished Jul 18 07:24:42 PM PDT 24
Peak memory 217148 kb
Host smart-85626d78-99df-48fa-ade6-437511b6cdf3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733955975 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.2733955975
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.3625587966
Short name T378
Test name
Test status
Simulation time 18662042 ps
CPU time 1.07 seconds
Started Jul 18 07:24:41 PM PDT 24
Finished Jul 18 07:24:44 PM PDT 24
Peak memory 218828 kb
Host smart-129e773f-af29-49a0-bdc9-ac60707c7532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625587966 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.3625587966
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.3705172498
Short name T452
Test name
Test status
Simulation time 134641230 ps
CPU time 2.92 seconds
Started Jul 18 07:24:41 PM PDT 24
Finished Jul 18 07:24:46 PM PDT 24
Peak memory 220656 kb
Host smart-fd64cefd-c2ea-4382-b386-dffd1c736770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705172498 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.3705172498
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.889696403
Short name T361
Test name
Test status
Simulation time 26916617 ps
CPU time 0.98 seconds
Started Jul 18 07:24:46 PM PDT 24
Finished Jul 18 07:24:50 PM PDT 24
Peak memory 215740 kb
Host smart-5a40ee53-d7f0-457f-87f2-ff90160052cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889696403 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.889696403
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.2423483363
Short name T661
Test name
Test status
Simulation time 16872546 ps
CPU time 1.01 seconds
Started Jul 18 07:24:46 PM PDT 24
Finished Jul 18 07:24:50 PM PDT 24
Peak memory 215572 kb
Host smart-b8f516bd-1b96-40ea-a15f-a371f6aa4fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423483363 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.2423483363
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.1875575621
Short name T390
Test name
Test status
Simulation time 255716267 ps
CPU time 5.02 seconds
Started Jul 18 07:24:46 PM PDT 24
Finished Jul 18 07:24:54 PM PDT 24
Peak memory 215528 kb
Host smart-3c672bde-9dce-4dce-824d-4f84e740750d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875575621 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1875575621
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.146214878
Short name T786
Test name
Test status
Simulation time 55444590780 ps
CPU time 1281.74 seconds
Started Jul 18 07:24:43 PM PDT 24
Finished Jul 18 07:46:06 PM PDT 24
Peak memory 224072 kb
Host smart-09eaa282-9cc6-4fde-b1bf-e9d0a40df385
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146214878 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.146214878
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.2104015918
Short name T492
Test name
Test status
Simulation time 68670079 ps
CPU time 1.12 seconds
Started Jul 18 07:24:42 PM PDT 24
Finished Jul 18 07:24:45 PM PDT 24
Peak memory 219172 kb
Host smart-7c0b6c9a-d021-41c1-97e9-4ed8bdae7dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104015918 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2104015918
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.2830662976
Short name T527
Test name
Test status
Simulation time 51833330 ps
CPU time 0.91 seconds
Started Jul 18 07:24:38 PM PDT 24
Finished Jul 18 07:24:42 PM PDT 24
Peak memory 207068 kb
Host smart-f491cccd-e082-4cef-bffe-7558b8f3a6f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830662976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.2830662976
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.1390888003
Short name T88
Test name
Test status
Simulation time 40836499 ps
CPU time 0.84 seconds
Started Jul 18 07:24:39 PM PDT 24
Finished Jul 18 07:24:43 PM PDT 24
Peak memory 215692 kb
Host smart-f26aa6e0-ceda-4a21-8317-074bd938565f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390888003 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1390888003
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.2062917931
Short name T928
Test name
Test status
Simulation time 156931318 ps
CPU time 1.15 seconds
Started Jul 18 07:24:45 PM PDT 24
Finished Jul 18 07:24:49 PM PDT 24
Peak memory 215892 kb
Host smart-ed1972fa-dfae-4cfe-877d-0ce2039986c7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062917931 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.2062917931
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.3029100953
Short name T206
Test name
Test status
Simulation time 31201869 ps
CPU time 1.25 seconds
Started Jul 18 07:24:38 PM PDT 24
Finished Jul 18 07:24:42 PM PDT 24
Peak memory 220044 kb
Host smart-cb87e464-8403-4ce5-9ad8-d3ad5123efa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029100953 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3029100953
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.3867548934
Short name T947
Test name
Test status
Simulation time 38367459 ps
CPU time 1.37 seconds
Started Jul 18 07:24:45 PM PDT 24
Finished Jul 18 07:24:50 PM PDT 24
Peak memory 218632 kb
Host smart-744d4ecb-8cba-48dd-99fb-9434edddcfc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867548934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3867548934
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.776644127
Short name T476
Test name
Test status
Simulation time 23529709 ps
CPU time 1.19 seconds
Started Jul 18 07:24:39 PM PDT 24
Finished Jul 18 07:24:43 PM PDT 24
Peak memory 224444 kb
Host smart-4a33f160-7b38-4756-a84b-ad81962ade91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776644127 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.776644127
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.1291791125
Short name T850
Test name
Test status
Simulation time 42767588 ps
CPU time 0.88 seconds
Started Jul 18 07:24:38 PM PDT 24
Finished Jul 18 07:24:41 PM PDT 24
Peak memory 215556 kb
Host smart-9a9239fe-2b7f-4d62-9b3a-eff7594543f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291791125 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.1291791125
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.278510480
Short name T829
Test name
Test status
Simulation time 473174094 ps
CPU time 8.39 seconds
Started Jul 18 07:24:39 PM PDT 24
Finished Jul 18 07:24:51 PM PDT 24
Peak memory 218936 kb
Host smart-a255242b-e9d1-495c-ad5a-2f43440b2bb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278510480 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.278510480
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3509376555
Short name T703
Test name
Test status
Simulation time 80664855846 ps
CPU time 694.8 seconds
Started Jul 18 07:24:38 PM PDT 24
Finished Jul 18 07:36:16 PM PDT 24
Peak memory 220276 kb
Host smart-2ce9e6b1-3d1d-4cd1-ba22-cb6a4a1aaa63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509376555 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3509376555
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.3031950269
Short name T160
Test name
Test status
Simulation time 22898687 ps
CPU time 1.15 seconds
Started Jul 18 07:24:46 PM PDT 24
Finished Jul 18 07:24:50 PM PDT 24
Peak memory 218848 kb
Host smart-fd6e9a37-36b7-43f0-8baf-f08d2f4a2582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031950269 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.3031950269
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.1139164446
Short name T409
Test name
Test status
Simulation time 22604310 ps
CPU time 0.93 seconds
Started Jul 18 07:24:52 PM PDT 24
Finished Jul 18 07:24:55 PM PDT 24
Peak memory 215228 kb
Host smart-c191db1c-61da-4525-9c9e-21133c889eaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139164446 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1139164446
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.103445552
Short name T751
Test name
Test status
Simulation time 27963414 ps
CPU time 0.82 seconds
Started Jul 18 07:24:43 PM PDT 24
Finished Jul 18 07:24:46 PM PDT 24
Peak memory 215684 kb
Host smart-0d719174-ea28-4897-bbc2-378ff856c413
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103445552 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.103445552
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.2240968175
Short name T147
Test name
Test status
Simulation time 39486667 ps
CPU time 1.34 seconds
Started Jul 18 07:24:51 PM PDT 24
Finished Jul 18 07:24:53 PM PDT 24
Peak memory 217192 kb
Host smart-72e34cfd-5583-4630-8ab3-31a2e5412412
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240968175 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.2240968175
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.894330415
Short name T201
Test name
Test status
Simulation time 24828972 ps
CPU time 0.95 seconds
Started Jul 18 07:24:46 PM PDT 24
Finished Jul 18 07:24:50 PM PDT 24
Peak memory 219060 kb
Host smart-f06497c0-bd22-4137-a7c9-b90fcd9fbdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894330415 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.894330415
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.1748536461
Short name T877
Test name
Test status
Simulation time 53594207 ps
CPU time 1.35 seconds
Started Jul 18 07:24:37 PM PDT 24
Finished Jul 18 07:24:42 PM PDT 24
Peak memory 217768 kb
Host smart-a77062e5-4152-47ae-bb5b-87fc2cb650f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748536461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1748536461
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.476011980
Short name T188
Test name
Test status
Simulation time 37917141 ps
CPU time 0.87 seconds
Started Jul 18 07:24:43 PM PDT 24
Finished Jul 18 07:24:45 PM PDT 24
Peak memory 215748 kb
Host smart-53178725-701e-416e-b655-5dbddbfd301d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476011980 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.476011980
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.3090728086
Short name T899
Test name
Test status
Simulation time 17451865 ps
CPU time 1.04 seconds
Started Jul 18 07:24:46 PM PDT 24
Finished Jul 18 07:24:51 PM PDT 24
Peak memory 215572 kb
Host smart-6a1988be-445e-49b4-96e3-93c9b55613c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090728086 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.3090728086
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.833792791
Short name T532
Test name
Test status
Simulation time 378297287 ps
CPU time 1.59 seconds
Started Jul 18 07:24:46 PM PDT 24
Finished Jul 18 07:24:51 PM PDT 24
Peak memory 217328 kb
Host smart-ac75b728-9277-457a-b723-c258824ad10f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833792791 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.833792791
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_alert.1606727591
Short name T105
Test name
Test status
Simulation time 191084146 ps
CPU time 1.22 seconds
Started Jul 18 07:24:51 PM PDT 24
Finished Jul 18 07:24:53 PM PDT 24
Peak memory 220020 kb
Host smart-82cd67ec-9a16-452e-b2de-5422e9e0da25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606727591 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.1606727591
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.4203053486
Short name T549
Test name
Test status
Simulation time 27673066 ps
CPU time 0.93 seconds
Started Jul 18 07:25:06 PM PDT 24
Finished Jul 18 07:25:11 PM PDT 24
Peak memory 207140 kb
Host smart-1a3817d2-31fb-4e45-a1f6-7bc2f98b187e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203053486 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.4203053486
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.1544775329
Short name T922
Test name
Test status
Simulation time 31100468 ps
CPU time 0.84 seconds
Started Jul 18 07:24:51 PM PDT 24
Finished Jul 18 07:24:53 PM PDT 24
Peak memory 216484 kb
Host smart-f9d6f19b-6c13-4cae-b2a3-ffa43edc1a46
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544775329 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.1544775329
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.2338058140
Short name T120
Test name
Test status
Simulation time 32559596 ps
CPU time 1.11 seconds
Started Jul 18 07:25:03 PM PDT 24
Finished Jul 18 07:25:06 PM PDT 24
Peak memory 217228 kb
Host smart-67d6d88d-ebf4-4122-92ff-81a5f6be6207
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338058140 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.2338058140
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.4243147412
Short name T178
Test name
Test status
Simulation time 19053571 ps
CPU time 1.05 seconds
Started Jul 18 07:24:52 PM PDT 24
Finished Jul 18 07:24:55 PM PDT 24
Peak memory 218740 kb
Host smart-4d8a41c0-97e6-4cb3-a12b-90552d44ccce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243147412 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.4243147412
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.2252504
Short name T322
Test name
Test status
Simulation time 82171671 ps
CPU time 2.12 seconds
Started Jul 18 07:24:51 PM PDT 24
Finished Jul 18 07:24:54 PM PDT 24
Peak memory 220472 kb
Host smart-87fda3da-6936-4fd2-ab9a-71f430b04634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2252504
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.883605128
Short name T342
Test name
Test status
Simulation time 60269467 ps
CPU time 0.88 seconds
Started Jul 18 07:24:51 PM PDT 24
Finished Jul 18 07:24:54 PM PDT 24
Peak memory 215648 kb
Host smart-23263f43-28cc-4026-ab4a-b520a50a7cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883605128 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.883605128
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.4230360762
Short name T715
Test name
Test status
Simulation time 33305034 ps
CPU time 1.01 seconds
Started Jul 18 07:24:51 PM PDT 24
Finished Jul 18 07:24:53 PM PDT 24
Peak memory 215580 kb
Host smart-9f73d47b-6035-497e-9c88-0bb634214617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230360762 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.4230360762
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.113881914
Short name T688
Test name
Test status
Simulation time 3003667894 ps
CPU time 5.09 seconds
Started Jul 18 07:24:51 PM PDT 24
Finished Jul 18 07:24:58 PM PDT 24
Peak memory 217808 kb
Host smart-9532264f-eb21-45fd-8371-a5e8192011f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113881914 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.113881914
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.2486805916
Short name T764
Test name
Test status
Simulation time 108730148930 ps
CPU time 1252.87 seconds
Started Jul 18 07:24:51 PM PDT 24
Finished Jul 18 07:45:45 PM PDT 24
Peak memory 225516 kb
Host smart-945b06db-b0d8-4eb4-bc8a-88085f9d9689
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486805916 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.2486805916
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert_test.2955075763
Short name T833
Test name
Test status
Simulation time 99403540 ps
CPU time 0.92 seconds
Started Jul 18 07:22:02 PM PDT 24
Finished Jul 18 07:22:05 PM PDT 24
Peak memory 207040 kb
Host smart-65fee767-98fe-4617-b962-1a1317e58893
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955075763 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2955075763
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.4113886182
Short name T60
Test name
Test status
Simulation time 35657376 ps
CPU time 0.88 seconds
Started Jul 18 07:22:04 PM PDT 24
Finished Jul 18 07:22:07 PM PDT 24
Peak memory 216572 kb
Host smart-71fb82cd-754d-4177-bd41-db639d8f9aeb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113886182 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.4113886182
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.797748158
Short name T736
Test name
Test status
Simulation time 59456337 ps
CPU time 1.17 seconds
Started Jul 18 07:22:04 PM PDT 24
Finished Jul 18 07:22:07 PM PDT 24
Peak memory 217244 kb
Host smart-349137e0-88d1-4032-a2b3-553d3d971e28
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797748158 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_dis
able_auto_req_mode.797748158
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.1612314107
Short name T139
Test name
Test status
Simulation time 19268663 ps
CPU time 1.12 seconds
Started Jul 18 07:22:01 PM PDT 24
Finished Jul 18 07:22:03 PM PDT 24
Peak memory 218868 kb
Host smart-1212d632-2619-429d-9c23-e2965614ee08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612314107 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.1612314107
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.1503533048
Short name T637
Test name
Test status
Simulation time 132857978 ps
CPU time 1.24 seconds
Started Jul 18 07:22:03 PM PDT 24
Finished Jul 18 07:22:06 PM PDT 24
Peak memory 218892 kb
Host smart-578bf6d5-3970-46b3-9ff0-c6d252d54fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503533048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1503533048
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.3339994581
Short name T546
Test name
Test status
Simulation time 50101814 ps
CPU time 1 seconds
Started Jul 18 07:22:01 PM PDT 24
Finished Jul 18 07:22:03 PM PDT 24
Peak memory 224160 kb
Host smart-18195452-b4b0-4eba-beb1-e24735118c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339994581 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.3339994581
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.1057449107
Short name T547
Test name
Test status
Simulation time 70809998 ps
CPU time 0.95 seconds
Started Jul 18 07:22:02 PM PDT 24
Finished Jul 18 07:22:05 PM PDT 24
Peak memory 207348 kb
Host smart-5fb3f639-9ef9-40c2-a9d9-473374a01ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057449107 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.1057449107
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.1511547713
Short name T780
Test name
Test status
Simulation time 18721370 ps
CPU time 1 seconds
Started Jul 18 07:21:43 PM PDT 24
Finished Jul 18 07:21:47 PM PDT 24
Peak memory 215564 kb
Host smart-41369c8b-4a5f-42c0-8a5e-aa7c28a3b61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511547713 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.1511547713
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.3307135209
Short name T713
Test name
Test status
Simulation time 326862524 ps
CPU time 2.91 seconds
Started Jul 18 07:22:01 PM PDT 24
Finished Jul 18 07:22:06 PM PDT 24
Peak memory 215584 kb
Host smart-a178dbb3-7105-4e4d-a756-026cd7566746
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307135209 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.3307135209
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.994032667
Short name T927
Test name
Test status
Simulation time 18579137941 ps
CPU time 441.2 seconds
Started Jul 18 07:22:01 PM PDT 24
Finished Jul 18 07:29:24 PM PDT 24
Peak memory 224032 kb
Host smart-8e1a6040-35ca-4b4c-8ae2-e3aeeaa5db16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994032667 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.994032667
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.3968628209
Short name T892
Test name
Test status
Simulation time 31738117 ps
CPU time 1.4 seconds
Started Jul 18 07:25:05 PM PDT 24
Finished Jul 18 07:25:10 PM PDT 24
Peak memory 216016 kb
Host smart-cdc3beed-da84-4ff8-94b1-4a88c98f9498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968628209 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.3968628209
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.3285292732
Short name T202
Test name
Test status
Simulation time 25453688 ps
CPU time 0.97 seconds
Started Jul 18 07:25:03 PM PDT 24
Finished Jul 18 07:25:06 PM PDT 24
Peak memory 219976 kb
Host smart-75d1f830-90f9-4d20-bec2-de4031954062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285292732 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.3285292732
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.2066122737
Short name T362
Test name
Test status
Simulation time 57539493 ps
CPU time 2.36 seconds
Started Jul 18 07:25:01 PM PDT 24
Finished Jul 18 07:25:05 PM PDT 24
Peak memory 217828 kb
Host smart-897bf7b2-a630-4d98-807d-2b4f84b90ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066122737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2066122737
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.1030252630
Short name T598
Test name
Test status
Simulation time 37442034 ps
CPU time 1.13 seconds
Started Jul 18 07:25:06 PM PDT 24
Finished Jul 18 07:25:11 PM PDT 24
Peak memory 219128 kb
Host smart-bd664e9f-5e7d-403b-b6be-66dfb20e8781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030252630 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.1030252630
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.2940593813
Short name T158
Test name
Test status
Simulation time 29278102 ps
CPU time 1.26 seconds
Started Jul 18 07:25:04 PM PDT 24
Finished Jul 18 07:25:09 PM PDT 24
Peak memory 219856 kb
Host smart-0c2b85d6-f7d6-4de1-93fa-2d838c34928e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940593813 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.2940593813
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.3575994846
Short name T354
Test name
Test status
Simulation time 69020960 ps
CPU time 1.46 seconds
Started Jul 18 07:25:05 PM PDT 24
Finished Jul 18 07:25:10 PM PDT 24
Peak memory 218888 kb
Host smart-2480a92a-f0f1-49a1-be60-e95fcac7ab9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575994846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.3575994846
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.3713830623
Short name T809
Test name
Test status
Simulation time 49325370 ps
CPU time 1.21 seconds
Started Jul 18 07:25:05 PM PDT 24
Finished Jul 18 07:25:10 PM PDT 24
Peak memory 219200 kb
Host smart-214575b1-832c-4c62-aa49-c4183d20001f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713830623 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.3713830623
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.3919805959
Short name T729
Test name
Test status
Simulation time 73030665 ps
CPU time 0.85 seconds
Started Jul 18 07:25:04 PM PDT 24
Finished Jul 18 07:25:08 PM PDT 24
Peak memory 218660 kb
Host smart-a659c443-388a-4e88-8bc9-a2986516f8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919805959 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.3919805959
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.2175161766
Short name T12
Test name
Test status
Simulation time 35783586 ps
CPU time 1.42 seconds
Started Jul 18 07:25:04 PM PDT 24
Finished Jul 18 07:25:09 PM PDT 24
Peak memory 220156 kb
Host smart-b667020e-0aa5-4574-9669-8c23ce0af548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175161766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.2175161766
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.2637782832
Short name T581
Test name
Test status
Simulation time 65831488 ps
CPU time 1.19 seconds
Started Jul 18 07:25:05 PM PDT 24
Finished Jul 18 07:25:10 PM PDT 24
Peak memory 220084 kb
Host smart-332d0a55-5aae-43e9-9c91-4fdde2601a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637782832 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.2637782832
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.2714801895
Short name T616
Test name
Test status
Simulation time 24012302 ps
CPU time 1.04 seconds
Started Jul 18 07:25:03 PM PDT 24
Finished Jul 18 07:25:06 PM PDT 24
Peak memory 224256 kb
Host smart-e8ce2a94-f247-439d-a165-98627e80c951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714801895 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2714801895
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.3437857569
Short name T860
Test name
Test status
Simulation time 105394801 ps
CPU time 1.82 seconds
Started Jul 18 07:25:06 PM PDT 24
Finished Jul 18 07:25:12 PM PDT 24
Peak memory 219324 kb
Host smart-8932983e-2e20-4d6f-b5b6-21a3afc60632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437857569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.3437857569
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.2620274279
Short name T919
Test name
Test status
Simulation time 69893608 ps
CPU time 1.18 seconds
Started Jul 18 07:25:05 PM PDT 24
Finished Jul 18 07:25:11 PM PDT 24
Peak memory 220036 kb
Host smart-0454191b-7145-4bae-a6a2-5003693a1037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620274279 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.2620274279
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.1076655887
Short name T55
Test name
Test status
Simulation time 32123043 ps
CPU time 1.01 seconds
Started Jul 18 07:25:05 PM PDT 24
Finished Jul 18 07:25:10 PM PDT 24
Peak memory 224076 kb
Host smart-0b504fdc-b7aa-4c0a-81fb-eeaefddfb32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076655887 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.1076655887
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.1860822719
Short name T307
Test name
Test status
Simulation time 55253551 ps
CPU time 1.36 seconds
Started Jul 18 07:25:05 PM PDT 24
Finished Jul 18 07:25:11 PM PDT 24
Peak memory 217584 kb
Host smart-166f5436-3b99-4c05-9079-11f7a35a35a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860822719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1860822719
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.2522306527
Short name T765
Test name
Test status
Simulation time 24534187 ps
CPU time 1.1 seconds
Started Jul 18 07:25:05 PM PDT 24
Finished Jul 18 07:25:09 PM PDT 24
Peak memory 218792 kb
Host smart-24562397-17a2-425d-a6ea-aa378c932708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522306527 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.2522306527
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.3666995996
Short name T679
Test name
Test status
Simulation time 20542765 ps
CPU time 1.1 seconds
Started Jul 18 07:25:03 PM PDT 24
Finished Jul 18 07:25:07 PM PDT 24
Peak memory 218744 kb
Host smart-f9e9b0b1-ed3e-4c15-9cc0-5932652867c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666995996 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.3666995996
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.1327677306
Short name T721
Test name
Test status
Simulation time 72647063 ps
CPU time 1.21 seconds
Started Jul 18 07:25:03 PM PDT 24
Finished Jul 18 07:25:06 PM PDT 24
Peak memory 219188 kb
Host smart-e538926a-ab74-4417-a0df-1335bd527697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327677306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.1327677306
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.3132284665
Short name T867
Test name
Test status
Simulation time 39587791 ps
CPU time 1.09 seconds
Started Jul 18 07:25:03 PM PDT 24
Finished Jul 18 07:25:07 PM PDT 24
Peak memory 220212 kb
Host smart-f3e505b8-3153-41b9-b4e2-697cf7bdea6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132284665 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.3132284665
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.1637966878
Short name T79
Test name
Test status
Simulation time 31537224 ps
CPU time 0.85 seconds
Started Jul 18 07:25:08 PM PDT 24
Finished Jul 18 07:25:12 PM PDT 24
Peak memory 215496 kb
Host smart-e05f967c-73d0-4d75-a53f-ca2ac5d87fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637966878 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.1637966878
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.34544547
Short name T697
Test name
Test status
Simulation time 89257209 ps
CPU time 1.18 seconds
Started Jul 18 07:25:07 PM PDT 24
Finished Jul 18 07:25:12 PM PDT 24
Peak memory 217544 kb
Host smart-00db35e0-6fac-4c00-8314-612a0b387684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34544547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.34544547
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.1328789461
Short name T604
Test name
Test status
Simulation time 92620053 ps
CPU time 1.22 seconds
Started Jul 18 07:25:04 PM PDT 24
Finished Jul 18 07:25:09 PM PDT 24
Peak memory 218796 kb
Host smart-b6231bfd-6ec5-47d3-83a4-10a50d92b79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328789461 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.1328789461
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_genbits.3368421853
Short name T991
Test name
Test status
Simulation time 119781374 ps
CPU time 1.01 seconds
Started Jul 18 07:25:05 PM PDT 24
Finished Jul 18 07:25:10 PM PDT 24
Peak memory 217676 kb
Host smart-abca7e3d-f9a9-4ee7-9410-87dbaccf47cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368421853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3368421853
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.3653784580
Short name T474
Test name
Test status
Simulation time 100938612 ps
CPU time 1.29 seconds
Started Jul 18 07:25:03 PM PDT 24
Finished Jul 18 07:25:07 PM PDT 24
Peak memory 221252 kb
Host smart-dfcab8dd-ae9d-47fe-b432-b002511ae69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653784580 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.3653784580
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_genbits.336539583
Short name T871
Test name
Test status
Simulation time 339413030 ps
CPU time 1.33 seconds
Started Jul 18 07:25:04 PM PDT 24
Finished Jul 18 07:25:08 PM PDT 24
Peak memory 217624 kb
Host smart-1f41547d-5d70-4fed-af77-51659af6c598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336539583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.336539583
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.121276700
Short name T90
Test name
Test status
Simulation time 29916598 ps
CPU time 1.31 seconds
Started Jul 18 07:25:05 PM PDT 24
Finished Jul 18 07:25:11 PM PDT 24
Peak memory 218896 kb
Host smart-fdb95bb6-bbb6-4980-961e-e70bbf7355c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121276700 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.121276700
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.71369352
Short name T460
Test name
Test status
Simulation time 55554447 ps
CPU time 0.89 seconds
Started Jul 18 07:25:04 PM PDT 24
Finished Jul 18 07:25:09 PM PDT 24
Peak memory 218720 kb
Host smart-94ad52e6-2846-43dc-8de0-0d3eb7ed1e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71369352 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.71369352
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.995413097
Short name T84
Test name
Test status
Simulation time 39993871 ps
CPU time 1.4 seconds
Started Jul 18 07:25:03 PM PDT 24
Finished Jul 18 07:25:06 PM PDT 24
Peak memory 218948 kb
Host smart-5a4efdad-35b1-4553-8e94-9f3f02bb0fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995413097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.995413097
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.103756060
Short name T744
Test name
Test status
Simulation time 25175731 ps
CPU time 1.26 seconds
Started Jul 18 07:22:02 PM PDT 24
Finished Jul 18 07:22:05 PM PDT 24
Peak memory 220264 kb
Host smart-d97f7d33-3b8f-4632-956e-5f8b1a86cf4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103756060 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.103756060
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.815268244
Short name T541
Test name
Test status
Simulation time 46161388 ps
CPU time 1 seconds
Started Jul 18 07:22:17 PM PDT 24
Finished Jul 18 07:22:21 PM PDT 24
Peak memory 207072 kb
Host smart-3345a313-7da6-4676-a2fa-5a683689570f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815268244 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.815268244
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.2478381230
Short name T542
Test name
Test status
Simulation time 17140023 ps
CPU time 0.94 seconds
Started Jul 18 07:22:17 PM PDT 24
Finished Jul 18 07:22:20 PM PDT 24
Peak memory 216492 kb
Host smart-9397f8a6-4f4f-403b-8f97-158ecf149c0b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478381230 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.2478381230
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.1292663314
Short name T707
Test name
Test status
Simulation time 108249955 ps
CPU time 1.07 seconds
Started Jul 18 07:22:15 PM PDT 24
Finished Jul 18 07:22:18 PM PDT 24
Peak memory 217148 kb
Host smart-ddce3d0e-20f3-41fe-b531-464e4cbe0b10
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292663314 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.1292663314
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.407188939
Short name T54
Test name
Test status
Simulation time 26928055 ps
CPU time 1.18 seconds
Started Jul 18 07:22:03 PM PDT 24
Finished Jul 18 07:22:07 PM PDT 24
Peak memory 224332 kb
Host smart-adfdf12b-903d-4bee-99c9-36a079e23479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407188939 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.407188939
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.1979512868
Short name T536
Test name
Test status
Simulation time 70907836 ps
CPU time 1.32 seconds
Started Jul 18 07:22:04 PM PDT 24
Finished Jul 18 07:22:07 PM PDT 24
Peak memory 217768 kb
Host smart-5addb4d8-18bb-46fd-bb79-a03b16694e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979512868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.1979512868
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.1012101866
Short name T539
Test name
Test status
Simulation time 23995876 ps
CPU time 1.04 seconds
Started Jul 18 07:22:01 PM PDT 24
Finished Jul 18 07:22:04 PM PDT 24
Peak memory 215852 kb
Host smart-9cdaec9c-7924-402d-bf83-aad6395580fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012101866 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.1012101866
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.919480522
Short name T617
Test name
Test status
Simulation time 31243381 ps
CPU time 0.99 seconds
Started Jul 18 07:22:03 PM PDT 24
Finished Jul 18 07:22:06 PM PDT 24
Peak memory 207444 kb
Host smart-2b00bb75-f641-49f1-b7bb-285796f1f67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919480522 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.919480522
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.2070699804
Short name T599
Test name
Test status
Simulation time 28999050 ps
CPU time 1.01 seconds
Started Jul 18 07:22:02 PM PDT 24
Finished Jul 18 07:22:05 PM PDT 24
Peak memory 215560 kb
Host smart-b67c1a89-5b1e-4cce-bed5-201534ec33a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070699804 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.2070699804
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.3504855181
Short name T67
Test name
Test status
Simulation time 678099590 ps
CPU time 3.91 seconds
Started Jul 18 07:22:03 PM PDT 24
Finished Jul 18 07:22:09 PM PDT 24
Peak memory 217440 kb
Host smart-ac140a51-17d3-403c-8250-66ea9d2b89c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504855181 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.3504855181
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.2591943243
Short name T942
Test name
Test status
Simulation time 47735832748 ps
CPU time 1203.74 seconds
Started Jul 18 07:22:01 PM PDT 24
Finished Jul 18 07:42:07 PM PDT 24
Peak memory 221656 kb
Host smart-ebb2a98e-3729-4e4c-a18d-51219b3ef203
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591943243 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.2591943243
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.2101558693
Short name T699
Test name
Test status
Simulation time 47652455 ps
CPU time 1.18 seconds
Started Jul 18 07:25:17 PM PDT 24
Finished Jul 18 07:25:20 PM PDT 24
Peak memory 220180 kb
Host smart-bc92437d-d868-42fc-b840-fc68adc50760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101558693 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.2101558693
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.2946698456
Short name T662
Test name
Test status
Simulation time 30044832 ps
CPU time 1.39 seconds
Started Jul 18 07:25:19 PM PDT 24
Finished Jul 18 07:25:24 PM PDT 24
Peak memory 226164 kb
Host smart-c7dfae75-05ae-4f2a-996f-3cb6cd2465f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946698456 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.2946698456
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.2493894701
Short name T415
Test name
Test status
Simulation time 117467534 ps
CPU time 1.43 seconds
Started Jul 18 07:25:03 PM PDT 24
Finished Jul 18 07:25:06 PM PDT 24
Peak memory 220324 kb
Host smart-30f007bf-90a0-4a92-8329-0ee30ed14e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493894701 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.2493894701
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.1143514080
Short name T413
Test name
Test status
Simulation time 35716830 ps
CPU time 1.16 seconds
Started Jul 18 07:25:19 PM PDT 24
Finished Jul 18 07:25:23 PM PDT 24
Peak memory 219856 kb
Host smart-0a662d7c-ab13-459f-8b20-1f9b98854798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143514080 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.1143514080
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.3297328742
Short name T117
Test name
Test status
Simulation time 26394418 ps
CPU time 1.28 seconds
Started Jul 18 07:25:17 PM PDT 24
Finished Jul 18 07:25:19 PM PDT 24
Peak memory 220784 kb
Host smart-2e2b3801-7824-4fc9-9235-aa75a3eaf5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297328742 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.3297328742
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.1054152433
Short name T318
Test name
Test status
Simulation time 51084465 ps
CPU time 1.42 seconds
Started Jul 18 07:25:20 PM PDT 24
Finished Jul 18 07:25:27 PM PDT 24
Peak memory 220276 kb
Host smart-15a9aff2-f075-470c-9bd0-0415f9a9a547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054152433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.1054152433
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.3694506086
Short name T109
Test name
Test status
Simulation time 54302530 ps
CPU time 1 seconds
Started Jul 18 07:25:19 PM PDT 24
Finished Jul 18 07:25:25 PM PDT 24
Peak memory 220168 kb
Host smart-0b3fe75d-f040-4651-9bdc-0097299ed276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694506086 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.3694506086
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.714023816
Short name T900
Test name
Test status
Simulation time 202036525 ps
CPU time 2.97 seconds
Started Jul 18 07:25:20 PM PDT 24
Finished Jul 18 07:25:30 PM PDT 24
Peak memory 220792 kb
Host smart-2f243edb-93f2-44f5-92f8-1a29a378e4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714023816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.714023816
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.2459312573
Short name T528
Test name
Test status
Simulation time 48553714 ps
CPU time 1.25 seconds
Started Jul 18 07:25:19 PM PDT 24
Finished Jul 18 07:25:25 PM PDT 24
Peak memory 214800 kb
Host smart-7d87cd02-b15f-4161-9a8d-9cd7784b018a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459312573 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.2459312573
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.3744252796
Short name T516
Test name
Test status
Simulation time 19553256 ps
CPU time 1.01 seconds
Started Jul 18 07:25:19 PM PDT 24
Finished Jul 18 07:25:25 PM PDT 24
Peak memory 218672 kb
Host smart-6c382356-dce9-483b-8795-8477e269997b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744252796 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.3744252796
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/64.edn_alert.475831324
Short name T511
Test name
Test status
Simulation time 55067828 ps
CPU time 1.21 seconds
Started Jul 18 07:25:20 PM PDT 24
Finished Jul 18 07:25:27 PM PDT 24
Peak memory 220436 kb
Host smart-3330f572-b84f-45b9-87ad-46066d22c448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475831324 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.475831324
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.803223290
Short name T191
Test name
Test status
Simulation time 30146362 ps
CPU time 0.92 seconds
Started Jul 18 07:25:18 PM PDT 24
Finished Jul 18 07:25:20 PM PDT 24
Peak memory 218856 kb
Host smart-d22fe6d3-9e7c-4b5d-89a8-0b6f5047a3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803223290 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.803223290
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.978462194
Short name T472
Test name
Test status
Simulation time 283818165 ps
CPU time 3.06 seconds
Started Jul 18 07:25:20 PM PDT 24
Finished Jul 18 07:25:29 PM PDT 24
Peak memory 220432 kb
Host smart-d1bb293b-3f84-4c22-b5c1-9cb70b1f8384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978462194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.978462194
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.4216618862
Short name T122
Test name
Test status
Simulation time 45451397 ps
CPU time 1.19 seconds
Started Jul 18 07:25:19 PM PDT 24
Finished Jul 18 07:25:24 PM PDT 24
Peak memory 220084 kb
Host smart-7cb31fc6-553f-41cc-b033-eeee3ec42b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216618862 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.4216618862
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.2294376418
Short name T411
Test name
Test status
Simulation time 28399628 ps
CPU time 1.3 seconds
Started Jul 18 07:25:18 PM PDT 24
Finished Jul 18 07:25:21 PM PDT 24
Peak memory 225968 kb
Host smart-f69bf51c-7a27-446c-954f-bbbbb480d073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294376418 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.2294376418
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.4171714454
Short name T370
Test name
Test status
Simulation time 220539377 ps
CPU time 1.05 seconds
Started Jul 18 07:25:16 PM PDT 24
Finished Jul 18 07:25:18 PM PDT 24
Peak memory 217460 kb
Host smart-01db749a-d1bb-442c-a746-770d12cc451e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171714454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.4171714454
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.3827057640
Short name T771
Test name
Test status
Simulation time 69019540 ps
CPU time 1.08 seconds
Started Jul 18 07:25:20 PM PDT 24
Finished Jul 18 07:25:26 PM PDT 24
Peak memory 219308 kb
Host smart-209e2da4-7de2-44f4-b642-fbecaaf0e7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827057640 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.3827057640
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.4232147151
Short name T518
Test name
Test status
Simulation time 24832099 ps
CPU time 1.03 seconds
Started Jul 18 07:25:17 PM PDT 24
Finished Jul 18 07:25:19 PM PDT 24
Peak memory 224080 kb
Host smart-45fb1fc5-b056-423a-a4f3-32db36c71e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232147151 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.4232147151
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.792811417
Short name T627
Test name
Test status
Simulation time 29323725 ps
CPU time 1.19 seconds
Started Jul 18 07:25:20 PM PDT 24
Finished Jul 18 07:25:27 PM PDT 24
Peak memory 217864 kb
Host smart-b8bb944e-51fd-4fc6-a35a-e21ed01f011d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792811417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.792811417
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.2803850551
Short name T143
Test name
Test status
Simulation time 289120481 ps
CPU time 1.49 seconds
Started Jul 18 07:25:18 PM PDT 24
Finished Jul 18 07:25:22 PM PDT 24
Peak memory 218744 kb
Host smart-52c63827-7a96-4d9b-821b-96049db0502e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803850551 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.2803850551
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.55977612
Short name T649
Test name
Test status
Simulation time 73684763 ps
CPU time 1.29 seconds
Started Jul 18 07:25:17 PM PDT 24
Finished Jul 18 07:25:19 PM PDT 24
Peak memory 225952 kb
Host smart-f0d4b88c-e6cd-4179-b87b-a3b079c57a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55977612 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.55977612
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.3783055009
Short name T538
Test name
Test status
Simulation time 62435498 ps
CPU time 1.31 seconds
Started Jul 18 07:25:20 PM PDT 24
Finished Jul 18 07:25:27 PM PDT 24
Peak memory 220112 kb
Host smart-109c6667-5612-487c-811c-eee6c1ab62cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783055009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3783055009
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.1024461979
Short name T849
Test name
Test status
Simulation time 132669474 ps
CPU time 1.12 seconds
Started Jul 18 07:25:20 PM PDT 24
Finished Jul 18 07:25:28 PM PDT 24
Peak memory 220012 kb
Host smart-e5fca6b7-6b16-4ba2-abfa-1d143dc9847d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024461979 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.1024461979
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.790576269
Short name T189
Test name
Test status
Simulation time 19190156 ps
CPU time 1.08 seconds
Started Jul 18 07:25:19 PM PDT 24
Finished Jul 18 07:25:24 PM PDT 24
Peak memory 218684 kb
Host smart-90f95f64-4c7c-412a-8556-236edde40a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790576269 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.790576269
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.2179499121
Short name T535
Test name
Test status
Simulation time 53926955 ps
CPU time 1.2 seconds
Started Jul 18 07:25:19 PM PDT 24
Finished Jul 18 07:25:24 PM PDT 24
Peak memory 218892 kb
Host smart-9e894f8a-53f9-452d-b3a6-9b38724111ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179499121 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.2179499121
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.4258304791
Short name T520
Test name
Test status
Simulation time 27838154 ps
CPU time 1.18 seconds
Started Jul 18 07:25:19 PM PDT 24
Finished Jul 18 07:25:25 PM PDT 24
Peak memory 219248 kb
Host smart-9fbd60cf-3a29-4be4-a981-31a39f81c528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258304791 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.4258304791
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.889456139
Short name T394
Test name
Test status
Simulation time 24803512 ps
CPU time 0.87 seconds
Started Jul 18 07:25:20 PM PDT 24
Finished Jul 18 07:25:27 PM PDT 24
Peak memory 218328 kb
Host smart-9e5e3bbb-9a40-4a02-9257-e33e380d34c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889456139 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.889456139
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.2605240654
Short name T710
Test name
Test status
Simulation time 54364158 ps
CPU time 1.29 seconds
Started Jul 18 07:25:21 PM PDT 24
Finished Jul 18 07:25:29 PM PDT 24
Peak memory 220028 kb
Host smart-852e7590-038f-4433-b6c9-4a824242d910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605240654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.2605240654
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.14931340
Short name T882
Test name
Test status
Simulation time 23497800 ps
CPU time 1.19 seconds
Started Jul 18 07:22:16 PM PDT 24
Finished Jul 18 07:22:20 PM PDT 24
Peak memory 220156 kb
Host smart-cf033270-04d6-4bcf-8478-b7a164a3f614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14931340 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.14931340
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.921094619
Short name T21
Test name
Test status
Simulation time 29767513 ps
CPU time 0.93 seconds
Started Jul 18 07:22:17 PM PDT 24
Finished Jul 18 07:22:20 PM PDT 24
Peak memory 207156 kb
Host smart-fb39c9a5-6de6-434e-be14-b7d68ba51230
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921094619 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.921094619
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.2258931022
Short name T880
Test name
Test status
Simulation time 11982344 ps
CPU time 0.92 seconds
Started Jul 18 07:22:15 PM PDT 24
Finished Jul 18 07:22:18 PM PDT 24
Peak memory 216376 kb
Host smart-596a5fcf-8c21-44e3-95d6-b8f318bf6fce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258931022 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.2258931022
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.1428029879
Short name T884
Test name
Test status
Simulation time 69074237 ps
CPU time 1.29 seconds
Started Jul 18 07:22:16 PM PDT 24
Finished Jul 18 07:22:20 PM PDT 24
Peak memory 217064 kb
Host smart-22eec6ab-4e13-4ba0-bc2c-61f991790ed1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428029879 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.1428029879
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.2467454641
Short name T131
Test name
Test status
Simulation time 32006066 ps
CPU time 1.04 seconds
Started Jul 18 07:22:15 PM PDT 24
Finished Jul 18 07:22:18 PM PDT 24
Peak memory 220032 kb
Host smart-6cfc51ee-5dd1-4a8c-bbd0-06fcf0ea3564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467454641 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.2467454641
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.1058010808
Short name T835
Test name
Test status
Simulation time 85053505 ps
CPU time 1.2 seconds
Started Jul 18 07:22:15 PM PDT 24
Finished Jul 18 07:22:18 PM PDT 24
Peak memory 217528 kb
Host smart-ed0b2234-7c84-4675-807b-2c0af7689e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058010808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1058010808
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.1117199004
Short name T630
Test name
Test status
Simulation time 31508007 ps
CPU time 0.98 seconds
Started Jul 18 07:22:16 PM PDT 24
Finished Jul 18 07:22:19 PM PDT 24
Peak memory 215872 kb
Host smart-5a39e136-2779-43a5-bbeb-7d63f289ab77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117199004 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.1117199004
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_smoke.2426785838
Short name T660
Test name
Test status
Simulation time 17893488 ps
CPU time 1.05 seconds
Started Jul 18 07:22:17 PM PDT 24
Finished Jul 18 07:22:20 PM PDT 24
Peak memory 215584 kb
Host smart-3f80a574-dbad-4b5d-8319-ce285c762fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426785838 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.2426785838
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.1240677899
Short name T916
Test name
Test status
Simulation time 647742356 ps
CPU time 1.99 seconds
Started Jul 18 07:22:15 PM PDT 24
Finished Jul 18 07:22:19 PM PDT 24
Peak memory 215564 kb
Host smart-8a9e4e74-e455-4d76-8bd3-61c8b8bd10ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240677899 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1240677899
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2298515573
Short name T231
Test name
Test status
Simulation time 15965661064 ps
CPU time 368.85 seconds
Started Jul 18 07:22:15 PM PDT 24
Finished Jul 18 07:28:26 PM PDT 24
Peak memory 223352 kb
Host smart-fe69de87-0315-4739-8d03-4bbbdd143b7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298515573 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.2298515573
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.2961869722
Short name T292
Test name
Test status
Simulation time 89104899 ps
CPU time 1.17 seconds
Started Jul 18 07:25:19 PM PDT 24
Finished Jul 18 07:25:25 PM PDT 24
Peak memory 219336 kb
Host smart-699465a9-5a30-4425-a778-e0c4054f1e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961869722 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.2961869722
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.1317800672
Short name T986
Test name
Test status
Simulation time 32604985 ps
CPU time 0.87 seconds
Started Jul 18 07:25:20 PM PDT 24
Finished Jul 18 07:25:26 PM PDT 24
Peak memory 218508 kb
Host smart-3bae5c44-bf32-421d-a18a-08adcf890012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317800672 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.1317800672
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.2081837233
Short name T802
Test name
Test status
Simulation time 54340676 ps
CPU time 2.13 seconds
Started Jul 18 07:25:17 PM PDT 24
Finished Jul 18 07:25:21 PM PDT 24
Peak memory 220544 kb
Host smart-ec4ceab2-0dd7-4cd9-b784-897dee2a5a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081837233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.2081837233
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.3268625140
Short name T83
Test name
Test status
Simulation time 82125266 ps
CPU time 1.23 seconds
Started Jul 18 07:25:18 PM PDT 24
Finished Jul 18 07:25:21 PM PDT 24
Peak memory 219996 kb
Host smart-69b0edeb-d472-4b9d-8ebb-19db217ba26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268625140 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.3268625140
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.3012459481
Short name T950
Test name
Test status
Simulation time 33665360 ps
CPU time 1.22 seconds
Started Jul 18 07:25:19 PM PDT 24
Finished Jul 18 07:25:23 PM PDT 24
Peak memory 220000 kb
Host smart-9d55df57-211a-4870-b6bb-6650d0ce96c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012459481 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.3012459481
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.2189221283
Short name T911
Test name
Test status
Simulation time 154560641 ps
CPU time 1.61 seconds
Started Jul 18 07:25:20 PM PDT 24
Finished Jul 18 07:25:28 PM PDT 24
Peak memory 219056 kb
Host smart-acc02bea-e344-4e09-9139-2e2955cbc627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189221283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.2189221283
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.808888236
Short name T800
Test name
Test status
Simulation time 86099336 ps
CPU time 1.19 seconds
Started Jul 18 07:25:18 PM PDT 24
Finished Jul 18 07:25:21 PM PDT 24
Peak memory 220640 kb
Host smart-0aca2051-1a33-43cd-bc58-0832c7107336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808888236 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.808888236
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.368763095
Short name T132
Test name
Test status
Simulation time 59700384 ps
CPU time 0.96 seconds
Started Jul 18 07:25:20 PM PDT 24
Finished Jul 18 07:25:27 PM PDT 24
Peak memory 219900 kb
Host smart-b16b3730-e117-441a-a68e-a11c3350fd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368763095 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.368763095
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.1102488746
Short name T588
Test name
Test status
Simulation time 98721019 ps
CPU time 1.54 seconds
Started Jul 18 07:25:20 PM PDT 24
Finished Jul 18 07:25:28 PM PDT 24
Peak memory 220200 kb
Host smart-c5ca7e94-6448-4e27-8fad-e7121c4a4184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102488746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.1102488746
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.1699724950
Short name T976
Test name
Test status
Simulation time 23678707 ps
CPU time 1.14 seconds
Started Jul 18 07:25:19 PM PDT 24
Finished Jul 18 07:25:26 PM PDT 24
Peak memory 218692 kb
Host smart-b7aaf3fb-2687-4c33-ad25-76b0e059bd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699724950 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.1699724950
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.2356062604
Short name T145
Test name
Test status
Simulation time 39107509 ps
CPU time 1.26 seconds
Started Jul 18 07:25:20 PM PDT 24
Finished Jul 18 07:25:27 PM PDT 24
Peak memory 230008 kb
Host smart-cf18acb0-2270-4b35-b264-1635dce860aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356062604 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.2356062604
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1971583419
Short name T320
Test name
Test status
Simulation time 68516811 ps
CPU time 1.17 seconds
Started Jul 18 07:25:19 PM PDT 24
Finished Jul 18 07:25:24 PM PDT 24
Peak memory 219432 kb
Host smart-1dd28cbb-a175-4df8-9aab-b79bffb7b19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971583419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1971583419
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.1799398569
Short name T110
Test name
Test status
Simulation time 34476642 ps
CPU time 1.06 seconds
Started Jul 18 07:25:18 PM PDT 24
Finished Jul 18 07:25:20 PM PDT 24
Peak memory 220264 kb
Host smart-e25d45c3-284e-4593-bf1b-c7f4f9e0f451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799398569 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.1799398569
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.918562958
Short name T862
Test name
Test status
Simulation time 48077311 ps
CPU time 1.69 seconds
Started Jul 18 07:25:20 PM PDT 24
Finished Jul 18 07:25:27 PM PDT 24
Peak memory 217536 kb
Host smart-0dd28473-cb08-44ae-bb03-b03465b92376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918562958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.918562958
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.2712890622
Short name T824
Test name
Test status
Simulation time 49605029 ps
CPU time 1.19 seconds
Started Jul 18 07:25:19 PM PDT 24
Finished Jul 18 07:25:24 PM PDT 24
Peak memory 215992 kb
Host smart-943d7072-4c1f-45f6-8e59-859c1dbfb2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712890622 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.2712890622
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.362937565
Short name T781
Test name
Test status
Simulation time 33984427 ps
CPU time 1.06 seconds
Started Jul 18 07:25:15 PM PDT 24
Finished Jul 18 07:25:17 PM PDT 24
Peak memory 220992 kb
Host smart-a19de66d-84c9-45ed-876f-9efcfe3acc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362937565 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.362937565
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.942908313
Short name T304
Test name
Test status
Simulation time 55333336 ps
CPU time 1.41 seconds
Started Jul 18 07:25:21 PM PDT 24
Finished Jul 18 07:25:29 PM PDT 24
Peak memory 218820 kb
Host smart-d2eb70bc-16cc-4c33-b7a6-82ad1ca8cb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942908313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.942908313
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.937244042
Short name T596
Test name
Test status
Simulation time 68213663 ps
CPU time 1.17 seconds
Started Jul 18 07:25:17 PM PDT 24
Finished Jul 18 07:25:20 PM PDT 24
Peak memory 219004 kb
Host smart-dfd40877-da33-40c8-9e23-4307ef3dc9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937244042 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.937244042
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.3718332522
Short name T493
Test name
Test status
Simulation time 23138346 ps
CPU time 0.99 seconds
Started Jul 18 07:25:20 PM PDT 24
Finished Jul 18 07:25:28 PM PDT 24
Peak memory 224300 kb
Host smart-bd10bd32-3625-4710-9bb6-4bfba8fd45eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718332522 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.3718332522
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.1583192967
Short name T748
Test name
Test status
Simulation time 86298136 ps
CPU time 1.15 seconds
Started Jul 18 07:25:20 PM PDT 24
Finished Jul 18 07:25:27 PM PDT 24
Peak memory 217792 kb
Host smart-e0f63ed0-af7c-4252-ad87-f5bb04bdbd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583192967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.1583192967
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.251255863
Short name T672
Test name
Test status
Simulation time 68907181 ps
CPU time 1.13 seconds
Started Jul 18 07:25:18 PM PDT 24
Finished Jul 18 07:25:23 PM PDT 24
Peak memory 220004 kb
Host smart-3f58cd82-b94b-44ac-8fb9-b2c5405c91d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251255863 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.251255863
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.1790040183
Short name T613
Test name
Test status
Simulation time 40083229 ps
CPU time 1.05 seconds
Started Jul 18 07:25:17 PM PDT 24
Finished Jul 18 07:25:19 PM PDT 24
Peak memory 219536 kb
Host smart-b17a3f14-62fb-4395-9a06-f5f2daa96394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790040183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.1790040183
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.1316707485
Short name T20
Test name
Test status
Simulation time 45261084 ps
CPU time 1.2 seconds
Started Jul 18 07:25:20 PM PDT 24
Finished Jul 18 07:25:27 PM PDT 24
Peak memory 219764 kb
Host smart-a9363e39-d694-4604-b8b7-4608f052d46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316707485 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.1316707485
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.185986242
Short name T162
Test name
Test status
Simulation time 48747713 ps
CPU time 0.91 seconds
Started Jul 18 07:25:19 PM PDT 24
Finished Jul 18 07:25:26 PM PDT 24
Peak memory 218656 kb
Host smart-63bb98a6-06a0-4412-be0f-559f8f90b841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185986242 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.185986242
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.1073130607
Short name T382
Test name
Test status
Simulation time 1303324864 ps
CPU time 9.48 seconds
Started Jul 18 07:25:20 PM PDT 24
Finished Jul 18 07:25:35 PM PDT 24
Peak memory 217852 kb
Host smart-5e447720-bd0e-43cd-8568-ede3a1a429f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073130607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.1073130607
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.1076407579
Short name T118
Test name
Test status
Simulation time 26578359 ps
CPU time 1.12 seconds
Started Jul 18 07:25:21 PM PDT 24
Finished Jul 18 07:25:29 PM PDT 24
Peak memory 229888 kb
Host smart-8ea5f32f-efb6-475d-92c0-8278852c308f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076407579 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.1076407579
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.2283023721
Short name T940
Test name
Test status
Simulation time 54220480 ps
CPU time 1.58 seconds
Started Jul 18 07:25:20 PM PDT 24
Finished Jul 18 07:25:27 PM PDT 24
Peak memory 218756 kb
Host smart-e80230f0-eced-4961-9d2e-bb778da2da28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283023721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.2283023721
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.1200776299
Short name T686
Test name
Test status
Simulation time 45158505 ps
CPU time 1.15 seconds
Started Jul 18 07:22:16 PM PDT 24
Finished Jul 18 07:22:20 PM PDT 24
Peak memory 219848 kb
Host smart-8da04664-3586-4c2d-863e-506e1b7c9353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200776299 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.1200776299
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.504335392
Short name T901
Test name
Test status
Simulation time 50108091 ps
CPU time 0.89 seconds
Started Jul 18 07:22:16 PM PDT 24
Finished Jul 18 07:22:20 PM PDT 24
Peak memory 207060 kb
Host smart-b20a04cd-77f2-469f-ab98-64c3c4ea8e5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504335392 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.504335392
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.2368778774
Short name T210
Test name
Test status
Simulation time 11984875 ps
CPU time 0.89 seconds
Started Jul 18 07:22:17 PM PDT 24
Finished Jul 18 07:22:21 PM PDT 24
Peak memory 216484 kb
Host smart-66adc5e6-5f69-452e-8887-24f4cfd934c3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368778774 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.2368778774
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.670213730
Short name T134
Test name
Test status
Simulation time 18334988 ps
CPU time 1.03 seconds
Started Jul 18 07:22:17 PM PDT 24
Finished Jul 18 07:22:20 PM PDT 24
Peak memory 217256 kb
Host smart-af2abcca-1a65-4347-b2dd-2261e3ba551f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670213730 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_dis
able_auto_req_mode.670213730
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.3313403647
Short name T26
Test name
Test status
Simulation time 19264006 ps
CPU time 1.1 seconds
Started Jul 18 07:22:15 PM PDT 24
Finished Jul 18 07:22:18 PM PDT 24
Peak memory 218880 kb
Host smart-544b52d4-a470-4e9e-98eb-b47e7742621e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313403647 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3313403647
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_intr.2431436807
Short name T872
Test name
Test status
Simulation time 23822861 ps
CPU time 1.05 seconds
Started Jul 18 07:22:18 PM PDT 24
Finished Jul 18 07:22:22 PM PDT 24
Peak memory 216088 kb
Host smart-43f26f09-835c-4602-a3b4-c103aff18069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431436807 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2431436807
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.1946211763
Short name T657
Test name
Test status
Simulation time 43028851 ps
CPU time 0.91 seconds
Started Jul 18 07:22:14 PM PDT 24
Finished Jul 18 07:22:16 PM PDT 24
Peak memory 207548 kb
Host smart-ab3097fd-7e3f-42dd-9938-2521bebc7e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946211763 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.1946211763
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.3806208748
Short name T379
Test name
Test status
Simulation time 29107021 ps
CPU time 0.97 seconds
Started Jul 18 07:22:16 PM PDT 24
Finished Jul 18 07:22:20 PM PDT 24
Peak memory 215584 kb
Host smart-879639bb-5e21-4ed9-a04b-d78e279bb5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806208748 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.3806208748
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.3925239867
Short name T456
Test name
Test status
Simulation time 972187321 ps
CPU time 5.42 seconds
Started Jul 18 07:22:17 PM PDT 24
Finished Jul 18 07:22:25 PM PDT 24
Peak memory 215556 kb
Host smart-dedb99f3-a301-4005-baa2-51472ff4e117
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925239867 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.3925239867
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.2157936149
Short name T462
Test name
Test status
Simulation time 212298940753 ps
CPU time 984.19 seconds
Started Jul 18 07:22:16 PM PDT 24
Finished Jul 18 07:38:43 PM PDT 24
Peak memory 223684 kb
Host smart-595e7893-dd13-4436-af6f-bb9261444262
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157936149 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.2157936149
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.512845159
Short name T94
Test name
Test status
Simulation time 101812936 ps
CPU time 1.11 seconds
Started Jul 18 07:25:18 PM PDT 24
Finished Jul 18 07:25:22 PM PDT 24
Peak memory 218916 kb
Host smart-b7c00615-7acf-47a8-ad16-910f21e49f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512845159 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.512845159
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.1173154030
Short name T80
Test name
Test status
Simulation time 33420518 ps
CPU time 0.91 seconds
Started Jul 18 07:25:20 PM PDT 24
Finished Jul 18 07:25:27 PM PDT 24
Peak memory 218604 kb
Host smart-10ad341e-86dd-4e50-878a-ff565b9db0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173154030 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.1173154030
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.3075507935
Short name T408
Test name
Test status
Simulation time 85668775 ps
CPU time 1.16 seconds
Started Jul 18 07:25:18 PM PDT 24
Finished Jul 18 07:25:21 PM PDT 24
Peak memory 217564 kb
Host smart-699425bf-0012-4c5b-811f-2e7dd86f8a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075507935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.3075507935
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.1340247876
Short name T401
Test name
Test status
Simulation time 265507697 ps
CPU time 1.26 seconds
Started Jul 18 07:25:30 PM PDT 24
Finished Jul 18 07:25:33 PM PDT 24
Peak memory 216112 kb
Host smart-542b6c9a-25ed-4b89-ab78-b82c256cd49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340247876 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.1340247876
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.2768961193
Short name T807
Test name
Test status
Simulation time 66962455 ps
CPU time 1.39 seconds
Started Jul 18 07:25:32 PM PDT 24
Finished Jul 18 07:25:35 PM PDT 24
Peak memory 225864 kb
Host smart-9e8850cb-9a10-4a64-9857-9fc396979382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768961193 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.2768961193
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.3783663906
Short name T435
Test name
Test status
Simulation time 163155810 ps
CPU time 1.45 seconds
Started Jul 18 07:25:33 PM PDT 24
Finished Jul 18 07:25:36 PM PDT 24
Peak memory 219100 kb
Host smart-d549e732-a7b2-4ab4-be51-30885365fe29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783663906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3783663906
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.3290418860
Short name T967
Test name
Test status
Simulation time 25053263 ps
CPU time 1.3 seconds
Started Jul 18 07:25:31 PM PDT 24
Finished Jul 18 07:25:33 PM PDT 24
Peak memory 220244 kb
Host smart-68bfea90-b99d-4064-8c88-1273d04eb709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290418860 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.3290418860
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.4283214938
Short name T567
Test name
Test status
Simulation time 52053133 ps
CPU time 1.02 seconds
Started Jul 18 07:25:38 PM PDT 24
Finished Jul 18 07:25:42 PM PDT 24
Peak memory 221008 kb
Host smart-1017df21-75e9-4462-b206-c5d666ba83c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283214938 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.4283214938
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.708853660
Short name T845
Test name
Test status
Simulation time 27281526 ps
CPU time 1.34 seconds
Started Jul 18 07:25:40 PM PDT 24
Finished Jul 18 07:25:44 PM PDT 24
Peak memory 218864 kb
Host smart-5756987d-0222-4030-8ea2-e1f5e4339a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708853660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.708853660
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.3629067406
Short name T667
Test name
Test status
Simulation time 24791078 ps
CPU time 1.16 seconds
Started Jul 18 07:25:36 PM PDT 24
Finished Jul 18 07:25:41 PM PDT 24
Peak memory 220172 kb
Host smart-ea70c300-19fc-4d52-bcfe-2218b5b63dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629067406 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.3629067406
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.2072481448
Short name T858
Test name
Test status
Simulation time 24319633 ps
CPU time 0.98 seconds
Started Jul 18 07:25:34 PM PDT 24
Finished Jul 18 07:25:38 PM PDT 24
Peak memory 218980 kb
Host smart-569968ce-88ee-4a1f-829a-0a8a0484c70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072481448 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.2072481448
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.1763417013
Short name T544
Test name
Test status
Simulation time 47684917 ps
CPU time 1.38 seconds
Started Jul 18 07:25:33 PM PDT 24
Finished Jul 18 07:25:36 PM PDT 24
Peak memory 218684 kb
Host smart-3c287fe2-0440-4a23-a5bb-ce119399f320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763417013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.1763417013
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.2399748429
Short name T212
Test name
Test status
Simulation time 49013123 ps
CPU time 1.15 seconds
Started Jul 18 07:25:32 PM PDT 24
Finished Jul 18 07:25:34 PM PDT 24
Peak memory 220356 kb
Host smart-bae5306f-da30-4633-8029-aff7afe49a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399748429 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.2399748429
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.1827532813
Short name T14
Test name
Test status
Simulation time 30943386 ps
CPU time 1 seconds
Started Jul 18 07:25:35 PM PDT 24
Finished Jul 18 07:25:38 PM PDT 24
Peak memory 224112 kb
Host smart-a3f02f67-57ed-4c8c-9a7e-098f842f2ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827532813 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.1827532813
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.1238509533
Short name T509
Test name
Test status
Simulation time 35490012 ps
CPU time 1.33 seconds
Started Jul 18 07:25:33 PM PDT 24
Finished Jul 18 07:25:36 PM PDT 24
Peak memory 217540 kb
Host smart-f3fa101e-d746-4779-8586-ba353fb07790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238509533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.1238509533
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.214558471
Short name T167
Test name
Test status
Simulation time 23631273 ps
CPU time 1.06 seconds
Started Jul 18 07:25:27 PM PDT 24
Finished Jul 18 07:25:31 PM PDT 24
Peak memory 224248 kb
Host smart-0ab7504e-88d9-40b7-85c0-2eddb2db688c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214558471 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.214558471
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.1439378370
Short name T644
Test name
Test status
Simulation time 196316790 ps
CPU time 1.42 seconds
Started Jul 18 07:25:34 PM PDT 24
Finished Jul 18 07:25:38 PM PDT 24
Peak memory 220440 kb
Host smart-c52b2d0a-9c86-4e27-8e4b-026560fcbde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439378370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.1439378370
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.757302844
Short name T839
Test name
Test status
Simulation time 235057115 ps
CPU time 1.4 seconds
Started Jul 18 07:25:33 PM PDT 24
Finished Jul 18 07:25:36 PM PDT 24
Peak memory 219824 kb
Host smart-f5c6ec4a-0920-4d7c-9b2d-29c86492292f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757302844 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.757302844
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.2041396442
Short name T209
Test name
Test status
Simulation time 45893463 ps
CPU time 1.16 seconds
Started Jul 18 07:25:32 PM PDT 24
Finished Jul 18 07:25:34 PM PDT 24
Peak memory 219948 kb
Host smart-5c33f0b6-7a33-4a0e-9577-e8cbc76321de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041396442 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2041396442
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.666353510
Short name T482
Test name
Test status
Simulation time 64458865 ps
CPU time 1.3 seconds
Started Jul 18 07:25:38 PM PDT 24
Finished Jul 18 07:25:42 PM PDT 24
Peak memory 218864 kb
Host smart-ff64763e-4349-469d-b92f-80d21c7dba35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666353510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.666353510
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.1605350046
Short name T181
Test name
Test status
Simulation time 81219607 ps
CPU time 1.16 seconds
Started Jul 18 07:25:34 PM PDT 24
Finished Jul 18 07:25:37 PM PDT 24
Peak memory 219956 kb
Host smart-da2589f2-9225-4964-ac39-df6d84c437b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605350046 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.1605350046
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.4271245236
Short name T841
Test name
Test status
Simulation time 64990227 ps
CPU time 1.06 seconds
Started Jul 18 07:25:32 PM PDT 24
Finished Jul 18 07:25:35 PM PDT 24
Peak memory 215688 kb
Host smart-173dccc9-c44d-4b73-9ff1-3c1fae181d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271245236 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.4271245236
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.3838130301
Short name T487
Test name
Test status
Simulation time 80153152 ps
CPU time 1.2 seconds
Started Jul 18 07:25:34 PM PDT 24
Finished Jul 18 07:25:38 PM PDT 24
Peak memory 219508 kb
Host smart-1294447e-16fd-4767-a92e-b9d843229400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838130301 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.3838130301
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.251001612
Short name T571
Test name
Test status
Simulation time 84200763 ps
CPU time 1.1 seconds
Started Jul 18 07:25:34 PM PDT 24
Finished Jul 18 07:25:38 PM PDT 24
Peak memory 218720 kb
Host smart-159a9749-bbb6-4a22-834c-a4d212e2a0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251001612 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.251001612
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.2642388399
Short name T866
Test name
Test status
Simulation time 86324962 ps
CPU time 1.08 seconds
Started Jul 18 07:25:34 PM PDT 24
Finished Jul 18 07:25:38 PM PDT 24
Peak memory 220036 kb
Host smart-390e71f9-e530-42a2-b673-a8cc41c22244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642388399 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.2642388399
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.4128854652
Short name T706
Test name
Test status
Simulation time 39400488 ps
CPU time 1.3 seconds
Started Jul 18 07:25:38 PM PDT 24
Finished Jul 18 07:25:43 PM PDT 24
Peak memory 217620 kb
Host smart-3d7fd3c1-9172-4dc8-a1ca-7e27edfe8606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128854652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.4128854652
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.2280832507
Short name T129
Test name
Test status
Simulation time 31082355 ps
CPU time 1.28 seconds
Started Jul 18 07:25:33 PM PDT 24
Finished Jul 18 07:25:36 PM PDT 24
Peak memory 216040 kb
Host smart-087fc370-4047-4a76-8a2b-4d12e1e7cea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280832507 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.2280832507
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.4114825761
Short name T863
Test name
Test status
Simulation time 29333374 ps
CPU time 0.92 seconds
Started Jul 18 07:25:36 PM PDT 24
Finished Jul 18 07:25:41 PM PDT 24
Peak memory 218316 kb
Host smart-9c6ed86b-6d46-4161-b941-c9e131e605ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114825761 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.4114825761
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.2655257514
Short name T10
Test name
Test status
Simulation time 432650241 ps
CPU time 1.28 seconds
Started Jul 18 07:25:35 PM PDT 24
Finished Jul 18 07:25:39 PM PDT 24
Peak memory 220252 kb
Host smart-f1d20252-a5dd-42ef-ad42-bc3bf82832d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655257514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.2655257514
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.4266084876
Short name T107
Test name
Test status
Simulation time 68542339 ps
CPU time 1.06 seconds
Started Jul 18 07:22:30 PM PDT 24
Finished Jul 18 07:22:34 PM PDT 24
Peak memory 218724 kb
Host smart-c71008d4-0497-4fe9-b918-c7d27ff08fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266084876 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.4266084876
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.4076479290
Short name T330
Test name
Test status
Simulation time 47640790 ps
CPU time 0.93 seconds
Started Jul 18 07:22:29 PM PDT 24
Finished Jul 18 07:22:32 PM PDT 24
Peak memory 215512 kb
Host smart-abce921f-0226-4fff-94e6-41a34998da37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076479290 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.4076479290
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.2869181222
Short name T171
Test name
Test status
Simulation time 15240626 ps
CPU time 0.91 seconds
Started Jul 18 07:22:30 PM PDT 24
Finished Jul 18 07:22:34 PM PDT 24
Peak memory 216768 kb
Host smart-c6103c9a-4366-4a0b-b35c-0dec89a17102
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869181222 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.2869181222
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1808589193
Short name T641
Test name
Test status
Simulation time 128207165 ps
CPU time 1.09 seconds
Started Jul 18 07:22:33 PM PDT 24
Finished Jul 18 07:22:37 PM PDT 24
Peak memory 218716 kb
Host smart-8682f818-d7db-455e-9141-9f77393f3755
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808589193 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1808589193
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.1988954088
Short name T626
Test name
Test status
Simulation time 22990355 ps
CPU time 0.95 seconds
Started Jul 18 07:22:30 PM PDT 24
Finished Jul 18 07:22:33 PM PDT 24
Peak memory 218920 kb
Host smart-2cfc6a80-e44c-43a5-88d6-dea1dd1fa3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988954088 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1988954088
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.1899660446
Short name T620
Test name
Test status
Simulation time 28927213 ps
CPU time 1.25 seconds
Started Jul 18 07:22:15 PM PDT 24
Finished Jul 18 07:22:19 PM PDT 24
Peak memory 218948 kb
Host smart-75e4a351-d7be-459b-8e4a-196780784d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899660446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1899660446
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2510066566
Short name T522
Test name
Test status
Simulation time 37920491 ps
CPU time 0.85 seconds
Started Jul 18 07:22:33 PM PDT 24
Finished Jul 18 07:22:37 PM PDT 24
Peak memory 215752 kb
Host smart-0deb31e8-baf2-493c-b3c0-5cb3c6c2ded2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510066566 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2510066566
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.1422829014
Short name T25
Test name
Test status
Simulation time 17806435 ps
CPU time 0.96 seconds
Started Jul 18 07:22:16 PM PDT 24
Finished Jul 18 07:22:19 PM PDT 24
Peak memory 207372 kb
Host smart-714a53b0-1e92-4f47-babd-2135d71aea38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422829014 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.1422829014
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.2332608631
Short name T731
Test name
Test status
Simulation time 38328999 ps
CPU time 0.91 seconds
Started Jul 18 07:22:13 PM PDT 24
Finished Jul 18 07:22:15 PM PDT 24
Peak memory 215572 kb
Host smart-99f1d112-2cf2-4fac-991d-aba9d423fd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332608631 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2332608631
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.2398251143
Short name T772
Test name
Test status
Simulation time 1965673275 ps
CPU time 4.58 seconds
Started Jul 18 07:22:15 PM PDT 24
Finished Jul 18 07:22:23 PM PDT 24
Peak memory 217672 kb
Host smart-073e4c4d-9ef0-4607-94e4-8b2078e1cac2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398251143 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2398251143
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.2283438021
Short name T788
Test name
Test status
Simulation time 150582274810 ps
CPU time 330.15 seconds
Started Jul 18 07:22:15 PM PDT 24
Finished Jul 18 07:27:47 PM PDT 24
Peak memory 224080 kb
Host smart-a7a081ef-8705-484e-820b-119a3b282d50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283438021 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.2283438021
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.3409038057
Short name T165
Test name
Test status
Simulation time 419779251 ps
CPU time 1.14 seconds
Started Jul 18 07:25:35 PM PDT 24
Finished Jul 18 07:25:39 PM PDT 24
Peak memory 216020 kb
Host smart-a211d7dc-77fe-480d-9964-bb9b87fcdd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409038057 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.3409038057
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.2668688643
Short name T113
Test name
Test status
Simulation time 27640986 ps
CPU time 1.22 seconds
Started Jul 18 07:25:40 PM PDT 24
Finished Jul 18 07:25:43 PM PDT 24
Peak memory 220936 kb
Host smart-0002e73d-f91b-4696-949f-85dfa4d268b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668688643 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.2668688643
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.2931517400
Short name T515
Test name
Test status
Simulation time 179426685 ps
CPU time 1.39 seconds
Started Jul 18 07:25:36 PM PDT 24
Finished Jul 18 07:25:40 PM PDT 24
Peak memory 217988 kb
Host smart-8d722e5f-732b-4da1-8007-ae5c0b636317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931517400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.2931517400
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.2544014090
Short name T852
Test name
Test status
Simulation time 47590611 ps
CPU time 1.2 seconds
Started Jul 18 07:25:39 PM PDT 24
Finished Jul 18 07:25:43 PM PDT 24
Peak memory 216000 kb
Host smart-5b3e937e-7fb6-4d37-8ecd-906335b4799f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544014090 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.2544014090
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.905360645
Short name T760
Test name
Test status
Simulation time 23702529 ps
CPU time 0.97 seconds
Started Jul 18 07:25:30 PM PDT 24
Finished Jul 18 07:25:32 PM PDT 24
Peak memory 218828 kb
Host smart-ddc42af0-39d6-4796-92b1-25bc71c56110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905360645 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.905360645
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.2634980841
Short name T299
Test name
Test status
Simulation time 98705459 ps
CPU time 1.41 seconds
Started Jul 18 07:25:34 PM PDT 24
Finished Jul 18 07:25:37 PM PDT 24
Peak memory 218872 kb
Host smart-458e0a89-cc28-44dc-817f-1e727a7d35bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634980841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.2634980841
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.2136622334
Short name T821
Test name
Test status
Simulation time 24609662 ps
CPU time 1.13 seconds
Started Jul 18 07:25:33 PM PDT 24
Finished Jul 18 07:25:36 PM PDT 24
Peak memory 218924 kb
Host smart-66136cc4-f3d2-41cd-9a39-d8f35f3d9d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136622334 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.2136622334
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.2883698764
Short name T756
Test name
Test status
Simulation time 22621653 ps
CPU time 1.04 seconds
Started Jul 18 07:25:37 PM PDT 24
Finished Jul 18 07:25:41 PM PDT 24
Peak memory 224452 kb
Host smart-5dfa0d9d-5166-47ac-a50c-5ed236339dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883698764 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.2883698764
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.1997054469
Short name T614
Test name
Test status
Simulation time 58589199 ps
CPU time 2.28 seconds
Started Jul 18 07:25:37 PM PDT 24
Finished Jul 18 07:25:43 PM PDT 24
Peak memory 220344 kb
Host smart-d64d688a-1343-4a9f-81c5-41aca558e769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997054469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1997054469
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.126336769
Short name T140
Test name
Test status
Simulation time 32008346 ps
CPU time 1.26 seconds
Started Jul 18 07:25:38 PM PDT 24
Finished Jul 18 07:25:42 PM PDT 24
Peak memory 219976 kb
Host smart-f3821002-eefd-47d9-afd5-1f6bba9be65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126336769 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.126336769
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.2478123167
Short name T507
Test name
Test status
Simulation time 19308954 ps
CPU time 1.11 seconds
Started Jul 18 07:25:31 PM PDT 24
Finished Jul 18 07:25:33 PM PDT 24
Peak memory 219036 kb
Host smart-12a86923-4883-443c-b166-3d5c9c79af36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478123167 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.2478123167
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.387361291
Short name T442
Test name
Test status
Simulation time 47241435 ps
CPU time 1.33 seconds
Started Jul 18 07:25:37 PM PDT 24
Finished Jul 18 07:25:42 PM PDT 24
Peak memory 218872 kb
Host smart-149921d4-db24-44a4-b9a2-585c9f94af5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387361291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.387361291
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.3007253013
Short name T172
Test name
Test status
Simulation time 24299587 ps
CPU time 1.14 seconds
Started Jul 18 07:25:35 PM PDT 24
Finished Jul 18 07:25:39 PM PDT 24
Peak memory 218856 kb
Host smart-55c1c7f2-2f54-43f3-8ae2-f7dba2f2606c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007253013 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.3007253013
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.169057481
Short name T793
Test name
Test status
Simulation time 27563387 ps
CPU time 1 seconds
Started Jul 18 07:25:32 PM PDT 24
Finished Jul 18 07:25:34 PM PDT 24
Peak memory 224096 kb
Host smart-3a3cbee7-62c8-4a1b-916f-67d67abdcb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169057481 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.169057481
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.3181469630
Short name T499
Test name
Test status
Simulation time 56819043 ps
CPU time 2.27 seconds
Started Jul 18 07:25:34 PM PDT 24
Finished Jul 18 07:25:38 PM PDT 24
Peak memory 217760 kb
Host smart-246a9a93-4960-456b-ba60-11d6c10b5aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181469630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.3181469630
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.3543766779
Short name T558
Test name
Test status
Simulation time 274658259 ps
CPU time 1.34 seconds
Started Jul 18 07:25:36 PM PDT 24
Finished Jul 18 07:25:41 PM PDT 24
Peak memory 220156 kb
Host smart-ae199807-619f-4a03-b2c6-81552d4a7238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543766779 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.3543766779
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.1410513318
Short name T155
Test name
Test status
Simulation time 92378863 ps
CPU time 1.01 seconds
Started Jul 18 07:25:33 PM PDT 24
Finished Jul 18 07:25:35 PM PDT 24
Peak memory 224096 kb
Host smart-9d395898-9c76-4c11-98c7-b7ca2279a3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410513318 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.1410513318
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.292939211
Short name T313
Test name
Test status
Simulation time 46005362 ps
CPU time 1.51 seconds
Started Jul 18 07:25:35 PM PDT 24
Finished Jul 18 07:25:39 PM PDT 24
Peak memory 217448 kb
Host smart-3fe7af24-30b4-419d-8627-37648328b18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292939211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.292939211
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.2132222820
Short name T108
Test name
Test status
Simulation time 74146308 ps
CPU time 1.11 seconds
Started Jul 18 07:25:37 PM PDT 24
Finished Jul 18 07:25:41 PM PDT 24
Peak memory 220220 kb
Host smart-99015c95-dcb8-4609-9ee1-5e3d256d694e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132222820 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.2132222820
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.492395042
Short name T419
Test name
Test status
Simulation time 19694503 ps
CPU time 0.95 seconds
Started Jul 18 07:25:36 PM PDT 24
Finished Jul 18 07:25:40 PM PDT 24
Peak memory 218752 kb
Host smart-54f821a6-44da-4602-aaf1-bcf8d12e3d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492395042 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.492395042
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.3894260978
Short name T671
Test name
Test status
Simulation time 58919246 ps
CPU time 1.36 seconds
Started Jul 18 07:25:31 PM PDT 24
Finished Jul 18 07:25:33 PM PDT 24
Peak memory 217816 kb
Host smart-f58e4f6a-bb35-4576-9dac-f732caa127ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894260978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.3894260978
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.432712583
Short name T208
Test name
Test status
Simulation time 20008183 ps
CPU time 1.12 seconds
Started Jul 18 07:25:36 PM PDT 24
Finished Jul 18 07:25:40 PM PDT 24
Peak memory 218992 kb
Host smart-ae28e9f8-495f-4462-a098-608736ad3c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432712583 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.432712583
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.2135479224
Short name T836
Test name
Test status
Simulation time 202214152 ps
CPU time 1.45 seconds
Started Jul 18 07:25:32 PM PDT 24
Finished Jul 18 07:25:35 PM PDT 24
Peak memory 218968 kb
Host smart-ba3fb24c-451d-47e0-80e9-88a77eaa2fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135479224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.2135479224
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.3822070623
Short name T904
Test name
Test status
Simulation time 217531303 ps
CPU time 1.33 seconds
Started Jul 18 07:25:33 PM PDT 24
Finished Jul 18 07:25:37 PM PDT 24
Peak memory 221204 kb
Host smart-9e4a2c8c-8499-4473-ab4f-e65596bbb096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822070623 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.3822070623
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.1941002159
Short name T138
Test name
Test status
Simulation time 56097502 ps
CPU time 1.06 seconds
Started Jul 18 07:25:34 PM PDT 24
Finished Jul 18 07:25:38 PM PDT 24
Peak memory 219024 kb
Host smart-3862e457-fe72-4810-807f-1e3b8e682d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941002159 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1941002159
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2494002562
Short name T374
Test name
Test status
Simulation time 38877226 ps
CPU time 1.22 seconds
Started Jul 18 07:25:38 PM PDT 24
Finished Jul 18 07:25:43 PM PDT 24
Peak memory 218736 kb
Host smart-3d07f4a0-0659-479f-a9ba-f1253a71dc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494002562 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2494002562
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.281877404
Short name T808
Test name
Test status
Simulation time 83787718 ps
CPU time 1.21 seconds
Started Jul 18 07:25:36 PM PDT 24
Finished Jul 18 07:25:40 PM PDT 24
Peak memory 218876 kb
Host smart-ed782773-99f5-45b4-ad98-825ec16982be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281877404 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.281877404
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.1400809007
Short name T116
Test name
Test status
Simulation time 31970309 ps
CPU time 0.96 seconds
Started Jul 18 07:25:40 PM PDT 24
Finished Jul 18 07:25:43 PM PDT 24
Peak memory 219864 kb
Host smart-c72aa826-a890-44d8-a206-f6f0948095a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400809007 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.1400809007
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.2766657487
Short name T680
Test name
Test status
Simulation time 46666853 ps
CPU time 1.58 seconds
Started Jul 18 07:25:34 PM PDT 24
Finished Jul 18 07:25:37 PM PDT 24
Peak memory 217724 kb
Host smart-f1c8c189-f80e-410f-9693-41916b9fce5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766657487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.2766657487
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%