Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	2	0	2	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_intr

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

7817

1

T4

7

T5

21

T47

8

all_values[1]

7817

1

T4

7

T5

21

T47

8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7944

1

T4

3

T5

15

T47

13

auto[1]

7690

1

T4

11

T5

27

T47

3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6218

1

T4

4

T5

18

T47

2

auto[1]

9416

1

T4

10

T5

24

T47

14

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9248

1

T4

6

T5

24

T47

9

auto[1]

6386

1

T4

8

T5

18

T47

7

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	12	0	12	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

1522

1

T5

2

T47

1

T72

2

all_values[0]

auto[0]

auto[0]

auto[1]

765

1

T5

1

T47

3

T72

1

all_values[0]

auto[0]

auto[1]

auto[0]

1552

1

T4

1

T5

7

T34

17

all_values[0]

auto[0]

auto[1]

auto[1]

769

1

T4

1

T5

3

T47

1

all_values[0]

auto[1]

auto[0]

auto[1]

1647

1

T4

1

T5

4

T47

3

all_values[0]

auto[1]

auto[1]

auto[1]

1562

1

T4

4

T5

4

T34

13

all_values[1]

auto[0]

auto[0]

auto[0]

1622

1

T4

1

T5

3

T34

18

all_values[1]

auto[0]

auto[0]

auto[1]

745

1

T5

1

T47

3

T34

17

all_values[1]

auto[0]

auto[1]

auto[0]

1522

1

T4

2

T5

6

T47

1

all_values[1]

auto[0]

auto[1]

auto[1]

751

1

T4

1

T5

1

T72

1

all_values[1]

auto[1]

auto[0]

auto[1]

1643

1

T4

1

T5

4

T47

3

all_values[1]

auto[1]

auto[1]

auto[1]

1534

1

T4

2

T5

6

T47

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal