Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.53 98.25 93.97 97.02 91.28 96.37 99.77 92.08


Total test records in report: 1130
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T1021 /workspace/coverage/cover_reg_top/36.edn_intr_test.1293526524 Jul 19 04:39:40 PM PDT 24 Jul 19 04:40:05 PM PDT 24 47033307 ps
T1022 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2339484440 Jul 19 04:39:28 PM PDT 24 Jul 19 04:39:56 PM PDT 24 24517791 ps
T1023 /workspace/coverage/cover_reg_top/42.edn_intr_test.3939448844 Jul 19 04:39:43 PM PDT 24 Jul 19 04:40:05 PM PDT 24 44191904 ps
T278 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2408951425 Jul 19 04:39:18 PM PDT 24 Jul 19 04:39:47 PM PDT 24 33798815 ps
T1024 /workspace/coverage/cover_reg_top/20.edn_intr_test.3545594364 Jul 19 04:39:35 PM PDT 24 Jul 19 04:40:01 PM PDT 24 44526057 ps
T1025 /workspace/coverage/cover_reg_top/39.edn_intr_test.4249651195 Jul 19 04:39:43 PM PDT 24 Jul 19 04:40:05 PM PDT 24 35376072 ps
T1026 /workspace/coverage/cover_reg_top/6.edn_tl_errors.3493881267 Jul 19 04:39:29 PM PDT 24 Jul 19 04:39:57 PM PDT 24 42428608 ps
T299 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2841794715 Jul 19 04:39:19 PM PDT 24 Jul 19 04:39:49 PM PDT 24 94797675 ps
T1027 /workspace/coverage/cover_reg_top/18.edn_intr_test.3112261826 Jul 19 04:39:42 PM PDT 24 Jul 19 04:40:05 PM PDT 24 12270821 ps
T1028 /workspace/coverage/cover_reg_top/19.edn_tl_errors.1808540350 Jul 19 04:39:44 PM PDT 24 Jul 19 04:40:08 PM PDT 24 1583463991 ps
T1029 /workspace/coverage/cover_reg_top/14.edn_tl_errors.1330057609 Jul 19 04:39:31 PM PDT 24 Jul 19 04:40:00 PM PDT 24 225889387 ps
T1030 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2068039092 Jul 19 04:39:30 PM PDT 24 Jul 19 04:39:57 PM PDT 24 48746156 ps
T1031 /workspace/coverage/cover_reg_top/31.edn_intr_test.1710625465 Jul 19 04:39:37 PM PDT 24 Jul 19 04:40:02 PM PDT 24 37331576 ps
T1032 /workspace/coverage/cover_reg_top/3.edn_tl_errors.1563427658 Jul 19 04:39:17 PM PDT 24 Jul 19 04:39:49 PM PDT 24 84607112 ps
T279 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1736435751 Jul 19 04:39:29 PM PDT 24 Jul 19 04:39:57 PM PDT 24 29987475 ps
T1033 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.4196918744 Jul 19 04:39:27 PM PDT 24 Jul 19 04:39:57 PM PDT 24 111627507 ps
T1034 /workspace/coverage/cover_reg_top/9.edn_csr_rw.2039831530 Jul 19 04:39:27 PM PDT 24 Jul 19 04:39:55 PM PDT 24 27281538 ps
T280 /workspace/coverage/cover_reg_top/12.edn_csr_rw.4001188909 Jul 19 04:39:29 PM PDT 24 Jul 19 04:39:56 PM PDT 24 39411973 ps
T1035 /workspace/coverage/cover_reg_top/4.edn_intr_test.1222890998 Jul 19 04:39:28 PM PDT 24 Jul 19 04:39:55 PM PDT 24 19547085 ps
T1036 /workspace/coverage/cover_reg_top/47.edn_intr_test.3256342133 Jul 19 04:39:36 PM PDT 24 Jul 19 04:40:02 PM PDT 24 29847596 ps
T1037 /workspace/coverage/cover_reg_top/18.edn_tl_errors.1581822381 Jul 19 04:39:38 PM PDT 24 Jul 19 04:40:04 PM PDT 24 26954405 ps
T1038 /workspace/coverage/cover_reg_top/22.edn_intr_test.2997177477 Jul 19 04:39:35 PM PDT 24 Jul 19 04:40:01 PM PDT 24 14698946 ps
T281 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2781557921 Jul 19 04:39:28 PM PDT 24 Jul 19 04:39:56 PM PDT 24 32949901 ps
T1039 /workspace/coverage/cover_reg_top/2.edn_tl_errors.3516414498 Jul 19 04:39:15 PM PDT 24 Jul 19 04:39:49 PM PDT 24 79914484 ps
T1040 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.4278242973 Jul 19 04:39:36 PM PDT 24 Jul 19 04:40:02 PM PDT 24 374451363 ps
T1041 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3418149737 Jul 19 04:39:26 PM PDT 24 Jul 19 04:39:56 PM PDT 24 588133067 ps
T1042 /workspace/coverage/cover_reg_top/11.edn_intr_test.2320182671 Jul 19 04:39:28 PM PDT 24 Jul 19 04:39:56 PM PDT 24 47244546 ps
T1043 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.526678597 Jul 19 04:39:17 PM PDT 24 Jul 19 04:39:51 PM PDT 24 699954500 ps
T1044 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.221330078 Jul 19 04:39:27 PM PDT 24 Jul 19 04:39:57 PM PDT 24 283286151 ps
T1045 /workspace/coverage/cover_reg_top/30.edn_intr_test.1093882791 Jul 19 04:39:43 PM PDT 24 Jul 19 04:40:05 PM PDT 24 132292121 ps
T1046 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.973184562 Jul 19 04:39:27 PM PDT 24 Jul 19 04:39:56 PM PDT 24 29976922 ps
T1047 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1523570202 Jul 19 04:39:37 PM PDT 24 Jul 19 04:40:02 PM PDT 24 151773879 ps
T1048 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1151720635 Jul 19 04:39:35 PM PDT 24 Jul 19 04:40:02 PM PDT 24 68788264 ps
T301 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3302519638 Jul 19 04:39:16 PM PDT 24 Jul 19 04:39:47 PM PDT 24 162103164 ps
T1049 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3956858519 Jul 19 04:39:18 PM PDT 24 Jul 19 04:39:48 PM PDT 24 33844600 ps
T1050 /workspace/coverage/cover_reg_top/24.edn_intr_test.430398371 Jul 19 04:39:36 PM PDT 24 Jul 19 04:40:02 PM PDT 24 21737917 ps
T1051 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.789855405 Jul 19 04:39:29 PM PDT 24 Jul 19 04:39:57 PM PDT 24 78521669 ps
T263 /workspace/coverage/cover_reg_top/17.edn_csr_rw.2155033042 Jul 19 04:39:36 PM PDT 24 Jul 19 04:40:02 PM PDT 24 54407219 ps
T1052 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3550124427 Jul 19 04:39:29 PM PDT 24 Jul 19 04:39:57 PM PDT 24 33633852 ps
T1053 /workspace/coverage/cover_reg_top/43.edn_intr_test.3012591190 Jul 19 04:39:43 PM PDT 24 Jul 19 04:40:05 PM PDT 24 52238134 ps
T1054 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.403752268 Jul 19 04:39:30 PM PDT 24 Jul 19 04:39:57 PM PDT 24 24538480 ps
T1055 /workspace/coverage/cover_reg_top/5.edn_intr_test.3208257569 Jul 19 04:39:26 PM PDT 24 Jul 19 04:39:55 PM PDT 24 20424684 ps
T1056 /workspace/coverage/cover_reg_top/45.edn_intr_test.2693954678 Jul 19 04:39:36 PM PDT 24 Jul 19 04:40:02 PM PDT 24 38955786 ps
T1057 /workspace/coverage/cover_reg_top/37.edn_intr_test.1730905795 Jul 19 04:39:36 PM PDT 24 Jul 19 04:40:02 PM PDT 24 29000389 ps
T1058 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1496864503 Jul 19 04:39:16 PM PDT 24 Jul 19 04:39:47 PM PDT 24 28584019 ps
T1059 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1997970474 Jul 19 04:39:37 PM PDT 24 Jul 19 04:40:03 PM PDT 24 72092694 ps
T1060 /workspace/coverage/cover_reg_top/14.edn_csr_rw.976741829 Jul 19 04:39:28 PM PDT 24 Jul 19 04:39:56 PM PDT 24 43880238 ps
T1061 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2044136089 Jul 19 04:39:36 PM PDT 24 Jul 19 04:40:02 PM PDT 24 87293054 ps
T1062 /workspace/coverage/cover_reg_top/10.edn_intr_test.2656703217 Jul 19 04:39:30 PM PDT 24 Jul 19 04:39:56 PM PDT 24 12577921 ps
T1063 /workspace/coverage/cover_reg_top/8.edn_intr_test.489845349 Jul 19 04:39:26 PM PDT 24 Jul 19 04:39:55 PM PDT 24 44320730 ps
T1064 /workspace/coverage/cover_reg_top/15.edn_tl_errors.1262549261 Jul 19 04:39:29 PM PDT 24 Jul 19 04:39:59 PM PDT 24 223164241 ps
T1065 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.283393766 Jul 19 04:39:29 PM PDT 24 Jul 19 04:39:58 PM PDT 24 137927718 ps
T264 /workspace/coverage/cover_reg_top/11.edn_csr_rw.2204972871 Jul 19 04:39:30 PM PDT 24 Jul 19 04:39:57 PM PDT 24 11971015 ps
T1066 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.4117721204 Jul 19 04:39:18 PM PDT 24 Jul 19 04:39:48 PM PDT 24 114326693 ps
T1067 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3994453333 Jul 19 04:39:27 PM PDT 24 Jul 19 04:39:56 PM PDT 24 15378869 ps
T1068 /workspace/coverage/cover_reg_top/46.edn_intr_test.757782861 Jul 19 04:39:37 PM PDT 24 Jul 19 04:40:02 PM PDT 24 75020358 ps
T1069 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3772828936 Jul 19 04:39:16 PM PDT 24 Jul 19 04:39:47 PM PDT 24 219769741 ps
T1070 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.857566439 Jul 19 04:39:44 PM PDT 24 Jul 19 04:40:07 PM PDT 24 68034485 ps
T265 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1849343709 Jul 19 04:39:18 PM PDT 24 Jul 19 04:39:47 PM PDT 24 80680960 ps
T266 /workspace/coverage/cover_reg_top/18.edn_csr_rw.1835437691 Jul 19 04:39:40 PM PDT 24 Jul 19 04:40:05 PM PDT 24 43622327 ps
T1071 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.418048882 Jul 19 04:39:35 PM PDT 24 Jul 19 04:40:01 PM PDT 24 39200224 ps
T1072 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.859091465 Jul 19 04:39:31 PM PDT 24 Jul 19 04:39:57 PM PDT 24 70383917 ps
T267 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.457206734 Jul 19 04:39:17 PM PDT 24 Jul 19 04:39:47 PM PDT 24 23602553 ps
T1073 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3721156563 Jul 19 04:39:29 PM PDT 24 Jul 19 04:39:57 PM PDT 24 63191760 ps
T268 /workspace/coverage/cover_reg_top/16.edn_csr_rw.4041891825 Jul 19 04:39:36 PM PDT 24 Jul 19 04:40:02 PM PDT 24 19034559 ps
T1074 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3224666959 Jul 19 04:39:33 PM PDT 24 Jul 19 04:40:00 PM PDT 24 51568018 ps
T1075 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2459129701 Jul 19 04:39:35 PM PDT 24 Jul 19 04:40:01 PM PDT 24 17479842 ps
T1076 /workspace/coverage/cover_reg_top/11.edn_tl_errors.2031017798 Jul 19 04:39:28 PM PDT 24 Jul 19 04:39:56 PM PDT 24 23637413 ps
T1077 /workspace/coverage/cover_reg_top/1.edn_csr_rw.3789484507 Jul 19 04:39:20 PM PDT 24 Jul 19 04:39:47 PM PDT 24 36068514 ps
T1078 /workspace/coverage/cover_reg_top/2.edn_csr_rw.3467084326 Jul 19 04:39:15 PM PDT 24 Jul 19 04:39:47 PM PDT 24 15052272 ps
T1079 /workspace/coverage/cover_reg_top/40.edn_intr_test.2035803717 Jul 19 04:39:36 PM PDT 24 Jul 19 04:40:02 PM PDT 24 11680807 ps
T1080 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1368486572 Jul 19 04:39:17 PM PDT 24 Jul 19 04:39:47 PM PDT 24 209574834 ps
T1081 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2138569701 Jul 19 04:39:30 PM PDT 24 Jul 19 04:39:58 PM PDT 24 121340338 ps
T269 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.852670934 Jul 19 04:39:21 PM PDT 24 Jul 19 04:39:48 PM PDT 24 55399867 ps
T1082 /workspace/coverage/cover_reg_top/12.edn_intr_test.3979755497 Jul 19 04:39:30 PM PDT 24 Jul 19 04:39:56 PM PDT 24 53256333 ps
T1083 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1451662036 Jul 19 04:39:39 PM PDT 24 Jul 19 04:40:04 PM PDT 24 40205076 ps
T270 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2270568952 Jul 19 04:39:17 PM PDT 24 Jul 19 04:39:47 PM PDT 24 38525781 ps
T1084 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2929098812 Jul 19 04:39:16 PM PDT 24 Jul 19 04:39:47 PM PDT 24 388904886 ps
T1085 /workspace/coverage/cover_reg_top/13.edn_intr_test.2397712720 Jul 19 04:39:30 PM PDT 24 Jul 19 04:39:56 PM PDT 24 28873370 ps
T300 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1870806709 Jul 19 04:39:26 PM PDT 24 Jul 19 04:39:56 PM PDT 24 670887084 ps
T1086 /workspace/coverage/cover_reg_top/9.edn_tl_errors.1244401870 Jul 19 04:39:25 PM PDT 24 Jul 19 04:39:57 PM PDT 24 163668181 ps
T1087 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3017113531 Jul 19 04:39:40 PM PDT 24 Jul 19 04:40:05 PM PDT 24 27963566 ps
T1088 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2460339842 Jul 19 04:39:30 PM PDT 24 Jul 19 04:39:57 PM PDT 24 607934488 ps
T271 /workspace/coverage/cover_reg_top/13.edn_csr_rw.243121227 Jul 19 04:39:30 PM PDT 24 Jul 19 04:39:56 PM PDT 24 37587386 ps
T272 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3462736164 Jul 19 04:39:27 PM PDT 24 Jul 19 04:39:58 PM PDT 24 134835844 ps
T1089 /workspace/coverage/cover_reg_top/19.edn_csr_rw.2337679633 Jul 19 04:39:39 PM PDT 24 Jul 19 04:40:05 PM PDT 24 38369116 ps
T1090 /workspace/coverage/cover_reg_top/0.edn_tl_errors.3520383855 Jul 19 04:39:15 PM PDT 24 Jul 19 04:39:50 PM PDT 24 544792942 ps
T1091 /workspace/coverage/cover_reg_top/15.edn_intr_test.4073203878 Jul 19 04:39:35 PM PDT 24 Jul 19 04:40:01 PM PDT 24 13098121 ps
T1092 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3383820161 Jul 19 04:39:27 PM PDT 24 Jul 19 04:39:56 PM PDT 24 54586084 ps
T1093 /workspace/coverage/cover_reg_top/1.edn_intr_test.343932497 Jul 19 04:39:17 PM PDT 24 Jul 19 04:39:47 PM PDT 24 22358901 ps
T1094 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2393482769 Jul 19 04:39:28 PM PDT 24 Jul 19 04:39:56 PM PDT 24 50927143 ps
T1095 /workspace/coverage/cover_reg_top/6.edn_intr_test.2067163217 Jul 19 04:39:32 PM PDT 24 Jul 19 04:39:58 PM PDT 24 47725185 ps
T1096 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2178881595 Jul 19 04:39:31 PM PDT 24 Jul 19 04:39:58 PM PDT 24 382109361 ps
T302 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2515935406 Jul 19 04:39:28 PM PDT 24 Jul 19 04:39:57 PM PDT 24 90998327 ps
T1097 /workspace/coverage/cover_reg_top/7.edn_intr_test.3127296275 Jul 19 04:39:32 PM PDT 24 Jul 19 04:39:58 PM PDT 24 13560761 ps
T1098 /workspace/coverage/cover_reg_top/1.edn_tl_errors.3725049787 Jul 19 04:39:17 PM PDT 24 Jul 19 04:39:49 PM PDT 24 356287213 ps
T1099 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.181958500 Jul 19 04:39:17 PM PDT 24 Jul 19 04:39:47 PM PDT 24 16429838 ps
T273 /workspace/coverage/cover_reg_top/6.edn_csr_rw.1434656743 Jul 19 04:39:28 PM PDT 24 Jul 19 04:39:55 PM PDT 24 57145521 ps
T1100 /workspace/coverage/cover_reg_top/27.edn_intr_test.2842176655 Jul 19 04:39:40 PM PDT 24 Jul 19 04:40:05 PM PDT 24 14012779 ps
T1101 /workspace/coverage/cover_reg_top/16.edn_intr_test.3977439621 Jul 19 04:39:39 PM PDT 24 Jul 19 04:40:05 PM PDT 24 14310602 ps
T1102 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2179057327 Jul 19 04:39:31 PM PDT 24 Jul 19 04:39:58 PM PDT 24 93963394 ps
T1103 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2309355713 Jul 19 04:39:29 PM PDT 24 Jul 19 04:39:57 PM PDT 24 77954288 ps
T1104 /workspace/coverage/cover_reg_top/14.edn_intr_test.553121970 Jul 19 04:39:29 PM PDT 24 Jul 19 04:39:56 PM PDT 24 52580131 ps
T1105 /workspace/coverage/cover_reg_top/0.edn_intr_test.111254891 Jul 19 04:39:18 PM PDT 24 Jul 19 04:39:47 PM PDT 24 42419673 ps
T1106 /workspace/coverage/cover_reg_top/10.edn_tl_errors.3215646067 Jul 19 04:39:29 PM PDT 24 Jul 19 04:39:59 PM PDT 24 115612253 ps
T1107 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.4263526799 Jul 19 04:39:27 PM PDT 24 Jul 19 04:39:55 PM PDT 24 214365761 ps
T1108 /workspace/coverage/cover_reg_top/3.edn_csr_rw.3789514909 Jul 19 04:39:17 PM PDT 24 Jul 19 04:39:47 PM PDT 24 25294279 ps
T1109 /workspace/coverage/cover_reg_top/7.edn_tl_errors.3280616701 Jul 19 04:39:30 PM PDT 24 Jul 19 04:39:58 PM PDT 24 294330094 ps
T1110 /workspace/coverage/cover_reg_top/4.edn_csr_rw.4012095666 Jul 19 04:39:28 PM PDT 24 Jul 19 04:39:56 PM PDT 24 112808377 ps
T1111 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.607120508 Jul 19 04:39:27 PM PDT 24 Jul 19 04:39:55 PM PDT 24 29545010 ps
T1112 /workspace/coverage/cover_reg_top/13.edn_tl_errors.2145097000 Jul 19 04:39:30 PM PDT 24 Jul 19 04:39:58 PM PDT 24 64760689 ps
T1113 /workspace/coverage/cover_reg_top/8.edn_tl_errors.709880829 Jul 19 04:39:26 PM PDT 24 Jul 19 04:39:57 PM PDT 24 151669108 ps
T1114 /workspace/coverage/cover_reg_top/9.edn_intr_test.2009904740 Jul 19 04:39:26 PM PDT 24 Jul 19 04:39:55 PM PDT 24 32263883 ps
T1115 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1616457578 Jul 19 04:39:18 PM PDT 24 Jul 19 04:39:47 PM PDT 24 32536823 ps
T1116 /workspace/coverage/cover_reg_top/34.edn_intr_test.3328863640 Jul 19 04:39:43 PM PDT 24 Jul 19 04:40:06 PM PDT 24 45829151 ps
T1117 /workspace/coverage/cover_reg_top/35.edn_intr_test.91295192 Jul 19 04:39:36 PM PDT 24 Jul 19 04:40:02 PM PDT 24 41164218 ps
T1118 /workspace/coverage/cover_reg_top/7.edn_csr_rw.218611529 Jul 19 04:39:30 PM PDT 24 Jul 19 04:39:56 PM PDT 24 36026457 ps
T1119 /workspace/coverage/cover_reg_top/38.edn_intr_test.578256559 Jul 19 04:39:39 PM PDT 24 Jul 19 04:40:04 PM PDT 24 26124457 ps
T1120 /workspace/coverage/cover_reg_top/0.edn_csr_rw.2743079316 Jul 19 04:39:17 PM PDT 24 Jul 19 04:39:47 PM PDT 24 15378834 ps
T1121 /workspace/coverage/cover_reg_top/10.edn_csr_rw.2407322031 Jul 19 04:39:26 PM PDT 24 Jul 19 04:39:55 PM PDT 24 13729944 ps
T1122 /workspace/coverage/cover_reg_top/5.edn_tl_errors.53903755 Jul 19 04:39:27 PM PDT 24 Jul 19 04:39:59 PM PDT 24 623537766 ps
T274 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.4160691816 Jul 19 04:39:19 PM PDT 24 Jul 19 04:39:53 PM PDT 24 2087690823 ps
T1123 /workspace/coverage/cover_reg_top/4.edn_tl_errors.3016967430 Jul 19 04:39:28 PM PDT 24 Jul 19 04:39:59 PM PDT 24 103533050 ps
T1124 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3518358726 Jul 19 04:39:28 PM PDT 24 Jul 19 04:39:56 PM PDT 24 41193826 ps
T1125 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2998521308 Jul 19 04:39:37 PM PDT 24 Jul 19 04:40:02 PM PDT 24 35888659 ps
T1126 /workspace/coverage/cover_reg_top/32.edn_intr_test.818889780 Jul 19 04:39:35 PM PDT 24 Jul 19 04:40:01 PM PDT 24 24038201 ps
T1127 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2248502618 Jul 19 04:39:30 PM PDT 24 Jul 19 04:39:57 PM PDT 24 34558987 ps
T1128 /workspace/coverage/cover_reg_top/8.edn_csr_rw.3033293146 Jul 19 04:39:31 PM PDT 24 Jul 19 04:39:58 PM PDT 24 18431315 ps
T1129 /workspace/coverage/cover_reg_top/12.edn_tl_errors.3475572077 Jul 19 04:39:28 PM PDT 24 Jul 19 04:39:57 PM PDT 24 33799145 ps
T1130 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3024883503 Jul 19 04:39:19 PM PDT 24 Jul 19 04:39:47 PM PDT 24 36416386 ps

Test location /workspace/coverage/default/236.edn_genbits.1775018167
Short name T10
Test name
Test status
Simulation time 45929350 ps
CPU time 1.86 seconds
Started Jul 19 06:30:04 PM PDT 24
Finished Jul 19 06:30:13 PM PDT 24
Peak memory 218868 kb
Host smart-462233e9-3764-440e-aa5c-512b479cea9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775018167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.1775018167
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.1038507113
Short name T3
Test name
Test status
Simulation time 27186630 ps
CPU time 1.22 seconds
Started Jul 19 06:29:49 PM PDT 24
Finished Jul 19 06:29:55 PM PDT 24
Peak memory 219056 kb
Host smart-2ec1f7e7-22cc-4c53-8e2a-b89e717e02fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038507113 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.1038507113
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.2167132039
Short name T34
Test name
Test status
Simulation time 89467275137 ps
CPU time 1061.38 seconds
Started Jul 19 06:28:40 PM PDT 24
Finished Jul 19 06:46:23 PM PDT 24
Peak memory 221556 kb
Host smart-78b3da8f-85ad-4d63-87e2-ecfc49e3dcdd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167132039 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.2167132039
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_intr.2675976224
Short name T58
Test name
Test status
Simulation time 37039866 ps
CPU time 0.98 seconds
Started Jul 19 06:28:36 PM PDT 24
Finished Jul 19 06:28:39 PM PDT 24
Peak memory 215732 kb
Host smart-c8927b8f-1cef-4424-9346-84a0bd3e37f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675976224 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.2675976224
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/1.edn_sec_cm.780691207
Short name T61
Test name
Test status
Simulation time 1943976589 ps
CPU time 8.55 seconds
Started Jul 19 06:27:05 PM PDT 24
Finished Jul 19 06:27:14 PM PDT 24
Peak memory 237836 kb
Host smart-ed63b49b-8c6e-4e04-a4c2-4852df440794
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780691207 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.780691207
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/13.edn_err.3551217153
Short name T31
Test name
Test status
Simulation time 32323603 ps
CPU time 0.94 seconds
Started Jul 19 06:27:45 PM PDT 24
Finished Jul 19 06:27:47 PM PDT 24
Peak memory 218800 kb
Host smart-75fac629-b0ef-4f74-b495-9a55206df166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551217153 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.3551217153
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.1774261106
Short name T96
Test name
Test status
Simulation time 100377420 ps
CPU time 1.06 seconds
Started Jul 19 06:27:57 PM PDT 24
Finished Jul 19 06:27:59 PM PDT 24
Peak memory 218608 kb
Host smart-5c46638e-e9d8-4d44-9737-5d5734893fb7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774261106 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.1774261106
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/143.edn_alert.1017995001
Short name T23
Test name
Test status
Simulation time 21853827 ps
CPU time 1.11 seconds
Started Jul 19 06:29:33 PM PDT 24
Finished Jul 19 06:29:41 PM PDT 24
Peak memory 220092 kb
Host smart-d11dc791-f9a9-481d-81be-6a86c1365476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017995001 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.1017995001
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/178.edn_alert.2529799888
Short name T1
Test name
Test status
Simulation time 294488324 ps
CPU time 1.64 seconds
Started Jul 19 06:30:02 PM PDT 24
Finished Jul 19 06:30:11 PM PDT 24
Peak memory 218884 kb
Host smart-08bfdd4d-b3a3-4b25-a9a9-a37b9c43518d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529799888 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.2529799888
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/7.edn_regwen.4116007761
Short name T24
Test name
Test status
Simulation time 19790304 ps
CPU time 0.97 seconds
Started Jul 19 06:27:23 PM PDT 24
Finished Jul 19 06:27:25 PM PDT 24
Peak memory 207368 kb
Host smart-88e5e73c-a51c-468c-86a6-07a244edf775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116007761 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.4116007761
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/40.edn_err.1081317306
Short name T15
Test name
Test status
Simulation time 54161941 ps
CPU time 1.64 seconds
Started Jul 19 06:28:35 PM PDT 24
Finished Jul 19 06:28:38 PM PDT 24
Peak memory 229804 kb
Host smart-e14682d5-4e34-4bfe-9985-3d3dca268f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081317306 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.1081317306
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.1945550130
Short name T12
Test name
Test status
Simulation time 131964085 ps
CPU time 1.58 seconds
Started Jul 19 06:28:54 PM PDT 24
Finished Jul 19 06:28:58 PM PDT 24
Peak memory 220140 kb
Host smart-1b6817fc-665d-4eba-b593-42ac3f8f422b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945550130 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1945550130
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.1102288250
Short name T56
Test name
Test status
Simulation time 178555189 ps
CPU time 1.26 seconds
Started Jul 19 06:29:19 PM PDT 24
Finished Jul 19 06:29:26 PM PDT 24
Peak memory 218904 kb
Host smart-76e42755-1bdc-4349-b85c-88b862676668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102288250 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.1102288250
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/36.edn_disable.328595011
Short name T92
Test name
Test status
Simulation time 13608443 ps
CPU time 0.91 seconds
Started Jul 19 06:28:33 PM PDT 24
Finished Jul 19 06:28:36 PM PDT 24
Peak memory 216660 kb
Host smart-8556e945-3711-47a1-9322-7ff1ee70f36e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328595011 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.328595011
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2178743703
Short name T291
Test name
Test status
Simulation time 75122769 ps
CPU time 1.49 seconds
Started Jul 19 04:39:18 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 214972 kb
Host smart-632dd6e7-bf77-485a-9b2b-a0afc71d3fd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178743703 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.2178743703
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/default/2.edn_intr.4237320825
Short name T99
Test name
Test status
Simulation time 21577464 ps
CPU time 1.07 seconds
Started Jul 19 06:27:10 PM PDT 24
Finished Jul 19 06:27:11 PM PDT 24
Peak memory 216168 kb
Host smart-93566d20-454d-402f-b94b-4f97a72a4eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237320825 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.4237320825
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.562378189
Short name T109
Test name
Test status
Simulation time 198442445271 ps
CPU time 2286.37 seconds
Started Jul 19 06:27:09 PM PDT 24
Finished Jul 19 07:05:16 PM PDT 24
Peak memory 228064 kb
Host smart-7dadd8c5-e4a9-4a1e-9ede-ee05deb880ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562378189 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.562378189
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.edn_disable.2491972223
Short name T199
Test name
Test status
Simulation time 17201392 ps
CPU time 0.82 seconds
Started Jul 19 06:27:54 PM PDT 24
Finished Jul 19 06:27:58 PM PDT 24
Peak memory 216484 kb
Host smart-b4acfbb7-0c1d-4daf-aa06-b3beaa7ee766
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491972223 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2491972223
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.419305581
Short name T225
Test name
Test status
Simulation time 80848884 ps
CPU time 1.1 seconds
Started Jul 19 06:27:00 PM PDT 24
Finished Jul 19 06:27:02 PM PDT 24
Peak memory 217184 kb
Host smart-d4585454-43a5-4595-a035-f903ed9459a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419305581 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_dis
able_auto_req_mode.419305581
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.4045209690
Short name T156
Test name
Test status
Simulation time 31047262 ps
CPU time 1.2 seconds
Started Jul 19 06:28:18 PM PDT 24
Finished Jul 19 06:28:20 PM PDT 24
Peak memory 217020 kb
Host smart-42c485e0-f490-4ae4-bd77-a8148afc782a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045209690 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.4045209690
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/55.edn_alert.1628189111
Short name T115
Test name
Test status
Simulation time 107722595 ps
CPU time 1.34 seconds
Started Jul 19 06:29:04 PM PDT 24
Finished Jul 19 06:29:07 PM PDT 24
Peak memory 220320 kb
Host smart-ed2932fe-b5a7-423e-96fb-1b271fc30e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628189111 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.1628189111
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2270568952
Short name T270
Test name
Test status
Simulation time 38525781 ps
CPU time 0.94 seconds
Started Jul 19 04:39:17 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 206720 kb
Host smart-bcf23a02-08d3-47c8-bad3-97edaa09e40c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270568952 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.2270568952
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/default/147.edn_alert.915863225
Short name T142
Test name
Test status
Simulation time 264475784 ps
CPU time 1.25 seconds
Started Jul 19 06:29:41 PM PDT 24
Finished Jul 19 06:29:49 PM PDT 24
Peak memory 218940 kb
Host smart-19d069d0-0561-41bb-a721-f115e1965727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915863225 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.915863225
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/195.edn_alert.1516992360
Short name T201
Test name
Test status
Simulation time 40796359 ps
CPU time 1.17 seconds
Started Jul 19 06:30:00 PM PDT 24
Finished Jul 19 06:30:10 PM PDT 24
Peak memory 220476 kb
Host smart-0fae8954-fa50-47f4-87eb-31d068d85911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516992360 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.1516992360
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/126.edn_alert.1857722262
Short name T137
Test name
Test status
Simulation time 107070332 ps
CPU time 1.24 seconds
Started Jul 19 06:29:33 PM PDT 24
Finished Jul 19 06:29:42 PM PDT 24
Peak memory 218740 kb
Host smart-0f5c4699-5906-4f47-a22d-9661096defe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857722262 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.1857722262
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/299.edn_genbits.2521885427
Short name T20
Test name
Test status
Simulation time 244101840 ps
CPU time 1.99 seconds
Started Jul 19 06:30:14 PM PDT 24
Finished Jul 19 06:30:24 PM PDT 24
Peak memory 218900 kb
Host smart-8aa1fcc7-2a58-4896-ab5d-afdab4064e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521885427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.2521885427
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.3096225275
Short name T638
Test name
Test status
Simulation time 81191160 ps
CPU time 1.15 seconds
Started Jul 19 06:29:07 PM PDT 24
Finished Jul 19 06:29:09 PM PDT 24
Peak memory 220776 kb
Host smart-1e823ecd-3a34-4a23-941c-328f6040162b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096225275 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.3096225275
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/217.edn_genbits.2852315819
Short name T95
Test name
Test status
Simulation time 83995827 ps
CPU time 1.37 seconds
Started Jul 19 06:30:07 PM PDT 24
Finished Jul 19 06:30:16 PM PDT 24
Peak memory 219060 kb
Host smart-b7a9ae22-d159-443f-99d1-6f02577036b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852315819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.2852315819
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.1146541851
Short name T580
Test name
Test status
Simulation time 25574488 ps
CPU time 1.19 seconds
Started Jul 19 06:29:37 PM PDT 24
Finished Jul 19 06:29:45 PM PDT 24
Peak memory 220060 kb
Host smart-13941c56-067f-42ed-83ab-e983c18a7f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146541851 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.1146541851
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert.1698370705
Short name T295
Test name
Test status
Simulation time 38334584 ps
CPU time 1.09 seconds
Started Jul 19 06:28:25 PM PDT 24
Finished Jul 19 06:28:28 PM PDT 24
Peak memory 219512 kb
Host smart-e72ab08e-26ec-4d01-aeaa-5ee66f2f57e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698370705 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1698370705
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.1789715767
Short name T163
Test name
Test status
Simulation time 49718206 ps
CPU time 1.21 seconds
Started Jul 19 06:28:22 PM PDT 24
Finished Jul 19 06:28:24 PM PDT 24
Peak memory 217224 kb
Host smart-cd3641d8-d7ac-4148-a470-d0230eb8e504
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789715767 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.1789715767
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_disable.2200970218
Short name T98
Test name
Test status
Simulation time 65049736 ps
CPU time 0.83 seconds
Started Jul 19 06:28:30 PM PDT 24
Finished Jul 19 06:28:32 PM PDT 24
Peak memory 216496 kb
Host smart-c0fdd449-35ba-4cd2-9e1b-9c4e07340e15
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200970218 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2200970218
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/40.edn_alert.159616460
Short name T150
Test name
Test status
Simulation time 30235261 ps
CPU time 1.22 seconds
Started Jul 19 06:28:38 PM PDT 24
Finished Jul 19 06:28:41 PM PDT 24
Peak memory 220916 kb
Host smart-db2bb01b-4a5c-47ba-bc76-bee40a032338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159616460 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.159616460
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.618488589
Short name T148
Test name
Test status
Simulation time 74889676 ps
CPU time 1.02 seconds
Started Jul 19 06:28:43 PM PDT 24
Finished Jul 19 06:28:45 PM PDT 24
Peak memory 218792 kb
Host smart-a1564d9f-bfda-48c8-9e8b-ff053600e5c8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618488589 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_di
sable_auto_req_mode.618488589
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/63.edn_alert.2443976856
Short name T192
Test name
Test status
Simulation time 45217925 ps
CPU time 1.22 seconds
Started Jul 19 06:29:09 PM PDT 24
Finished Jul 19 06:29:12 PM PDT 24
Peak memory 220120 kb
Host smart-2540d792-97c7-4796-a373-8b9a671ad493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443976856 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.2443976856
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/8.edn_intr.2948134486
Short name T28
Test name
Test status
Simulation time 21714024 ps
CPU time 1.16 seconds
Started Jul 19 06:27:30 PM PDT 24
Finished Jul 19 06:27:33 PM PDT 24
Peak memory 216272 kb
Host smart-a0a03868-f299-4f1d-ac67-2f237483b4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948134486 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2948134486
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/161.edn_genbits.2705868118
Short name T55
Test name
Test status
Simulation time 59049009 ps
CPU time 1.1 seconds
Started Jul 19 06:29:52 PM PDT 24
Finished Jul 19 06:29:57 PM PDT 24
Peak memory 215544 kb
Host smart-5401a5c3-a511-4fbf-9819-168e03c109f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705868118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.2705868118
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_disable.1344956926
Short name T692
Test name
Test status
Simulation time 70779293 ps
CPU time 0.84 seconds
Started Jul 19 06:27:36 PM PDT 24
Finished Jul 19 06:27:38 PM PDT 24
Peak memory 215660 kb
Host smart-e9e83a69-bf98-49b1-ba37-5213c30b636c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344956926 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.1344956926
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable.16755502
Short name T658
Test name
Test status
Simulation time 10425592 ps
CPU time 0.89 seconds
Started Jul 19 06:27:46 PM PDT 24
Finished Jul 19 06:27:48 PM PDT 24
Peak memory 216584 kb
Host smart-2d0e7a89-bc45-4164-8606-4fe37d12297d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16755502 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.16755502
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/0.edn_alert.529672391
Short name T183
Test name
Test status
Simulation time 22250768 ps
CPU time 1.15 seconds
Started Jul 19 06:27:05 PM PDT 24
Finished Jul 19 06:27:06 PM PDT 24
Peak memory 219036 kb
Host smart-4b4bfbc6-dc08-46e4-89b0-d4ce6075b6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529672391 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.529672391
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.2548024011
Short name T135
Test name
Test status
Simulation time 169919723 ps
CPU time 1.21 seconds
Started Jul 19 06:27:36 PM PDT 24
Finished Jul 19 06:27:39 PM PDT 24
Peak memory 217252 kb
Host smart-97f59c0c-5d51-49aa-bc69-1d61c2b96c42
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548024011 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.2548024011
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/118.edn_alert.629385410
Short name T611
Test name
Test status
Simulation time 119932892 ps
CPU time 1.05 seconds
Started Jul 19 06:29:24 PM PDT 24
Finished Jul 19 06:29:32 PM PDT 24
Peak memory 220956 kb
Host smart-5fd19f24-e9ba-4064-b51c-d63de7cf260c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629385410 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.629385410
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert.1665792337
Short name T196
Test name
Test status
Simulation time 29580714 ps
CPU time 1.12 seconds
Started Jul 19 06:27:45 PM PDT 24
Finished Jul 19 06:27:48 PM PDT 24
Peak memory 220084 kb
Host smart-b3ecfbc1-a73f-44be-9bb1-07af00073541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665792337 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.1665792337
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_disable.2714766114
Short name T993
Test name
Test status
Simulation time 40823204 ps
CPU time 0.82 seconds
Started Jul 19 06:27:44 PM PDT 24
Finished Jul 19 06:27:46 PM PDT 24
Peak memory 216520 kb
Host smart-22de7b74-1b4e-4ff1-b1ec-6d078b489424
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714766114 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.2714766114
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/17.edn_err.787318139
Short name T976
Test name
Test status
Simulation time 19789938 ps
CPU time 1.07 seconds
Started Jul 19 06:27:52 PM PDT 24
Finished Jul 19 06:27:55 PM PDT 24
Peak memory 219716 kb
Host smart-495f909f-4795-4114-83d7-d4db2a67d91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787318139 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.787318139
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.615259145
Short name T229
Test name
Test status
Simulation time 51607796 ps
CPU time 1.2 seconds
Started Jul 19 06:28:00 PM PDT 24
Finished Jul 19 06:28:02 PM PDT 24
Peak memory 217128 kb
Host smart-5fd0c0fe-22e3-435c-8746-72be0808c934
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615259145 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_di
sable_auto_req_mode.615259145
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_disable.2213051412
Short name T736
Test name
Test status
Simulation time 14206652 ps
CPU time 0.94 seconds
Started Jul 19 06:28:19 PM PDT 24
Finished Jul 19 06:28:21 PM PDT 24
Peak memory 216672 kb
Host smart-86a6abfc-e6ab-40d1-bf45-a2fdbbe440fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213051412 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.2213051412
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_err.4125730698
Short name T194
Test name
Test status
Simulation time 34176286 ps
CPU time 0.89 seconds
Started Jul 19 06:28:17 PM PDT 24
Finished Jul 19 06:28:19 PM PDT 24
Peak memory 215500 kb
Host smart-03899c00-6675-4b4f-a4b5-f17ed8f75942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125730698 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.4125730698
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/30.edn_disable.413384456
Short name T86
Test name
Test status
Simulation time 32263446 ps
CPU time 0.88 seconds
Started Jul 19 06:28:22 PM PDT 24
Finished Jul 19 06:28:23 PM PDT 24
Peak memory 216520 kb
Host smart-e0986d93-8821-46ad-9c12-47bbf1b6aeaf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413384456 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.413384456
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/1.edn_alert_test.1520410002
Short name T403
Test name
Test status
Simulation time 14355856 ps
CPU time 0.89 seconds
Started Jul 19 06:27:01 PM PDT 24
Finished Jul 19 06:27:02 PM PDT 24
Peak memory 207012 kb
Host smart-530f7dfb-4bcc-4f50-ad31-096b17d147c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520410002 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1520410002
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/107.edn_alert.1612853625
Short name T565
Test name
Test status
Simulation time 24561950 ps
CPU time 1.19 seconds
Started Jul 19 06:29:24 PM PDT 24
Finished Jul 19 06:29:32 PM PDT 24
Peak memory 218992 kb
Host smart-66336b87-4da4-409e-856e-dada7d7e9e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612853625 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.1612853625
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/1.edn_genbits.951214567
Short name T87
Test name
Test status
Simulation time 66109041 ps
CPU time 1.5 seconds
Started Jul 19 06:27:02 PM PDT 24
Finished Jul 19 06:27:04 PM PDT 24
Peak memory 217444 kb
Host smart-ae13e0de-409d-4936-ae06-c1888c329765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951214567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.951214567
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.3715512894
Short name T38
Test name
Test status
Simulation time 39029303 ps
CPU time 1.4 seconds
Started Jul 19 06:30:16 PM PDT 24
Finished Jul 19 06:30:24 PM PDT 24
Peak memory 217596 kb
Host smart-01aa1652-99a7-455e-9ea8-213ec65b4303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715512894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.3715512894
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.3647782684
Short name T324
Test name
Test status
Simulation time 66709681 ps
CPU time 1.13 seconds
Started Jul 19 06:29:26 PM PDT 24
Finished Jul 19 06:29:33 PM PDT 24
Peak memory 217588 kb
Host smart-e9b289f6-ebff-4a5d-a24f-63072762a1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647782684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3647782684
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_genbits.475153382
Short name T350
Test name
Test status
Simulation time 95373160 ps
CPU time 2.17 seconds
Started Jul 19 06:29:11 PM PDT 24
Finished Jul 19 06:29:18 PM PDT 24
Peak memory 219120 kb
Host smart-01bccbae-7903-4204-b126-95cda44dbfb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475153382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.475153382
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.2801886644
Short name T16
Test name
Test status
Simulation time 22596015 ps
CPU time 1.11 seconds
Started Jul 19 06:27:08 PM PDT 24
Finished Jul 19 06:27:10 PM PDT 24
Peak memory 216176 kb
Host smart-0eacf6a9-4b36-4b29-9805-3124831a3d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801886644 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.2801886644
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2408951425
Short name T278
Test name
Test status
Simulation time 33798815 ps
CPU time 1.15 seconds
Started Jul 19 04:39:18 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 206844 kb
Host smart-ee75d542-19a8-463d-9a07-d34fbc5d3eb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408951425 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.2408951425
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3302519638
Short name T301
Test name
Test status
Simulation time 162103164 ps
CPU time 1.54 seconds
Started Jul 19 04:39:16 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 215076 kb
Host smart-396d935e-18e9-47bd-8021-e9930d5bfea8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302519638 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.3302519638
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_regwen.728504555
Short name T25
Test name
Test status
Simulation time 14383804 ps
CPU time 0.97 seconds
Started Jul 19 06:27:02 PM PDT 24
Finished Jul 19 06:27:04 PM PDT 24
Peak memory 207372 kb
Host smart-f79715d0-c382-4e0a-a955-ebed3f22b21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728504555 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.728504555
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/11.edn_genbits.2976330267
Short name T337
Test name
Test status
Simulation time 54172908 ps
CPU time 1.92 seconds
Started Jul 19 06:27:38 PM PDT 24
Finished Jul 19 06:27:41 PM PDT 24
Peak memory 218696 kb
Host smart-80783b08-365d-41fc-bd09-ac74ec81b7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976330267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2976330267
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.3501532233
Short name T330
Test name
Test status
Simulation time 23735200 ps
CPU time 1.11 seconds
Started Jul 19 06:29:25 PM PDT 24
Finished Jul 19 06:29:33 PM PDT 24
Peak memory 217456 kb
Host smart-5f60b7b4-152e-4e65-accf-f450f828b29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501532233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.3501532233
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.1138710781
Short name T344
Test name
Test status
Simulation time 125068323 ps
CPU time 1.15 seconds
Started Jul 19 06:29:33 PM PDT 24
Finished Jul 19 06:29:41 PM PDT 24
Peak memory 220068 kb
Host smart-1fcef2f2-2114-4444-87db-aa2547cf1e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138710781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.1138710781
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.3002715724
Short name T321
Test name
Test status
Simulation time 95821440 ps
CPU time 1.39 seconds
Started Jul 19 06:29:43 PM PDT 24
Finished Jul 19 06:29:50 PM PDT 24
Peak memory 218844 kb
Host smart-069645f3-8657-45eb-828a-cfe449a50293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002715724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3002715724
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.988515317
Short name T331
Test name
Test status
Simulation time 57228006 ps
CPU time 1.54 seconds
Started Jul 19 06:29:42 PM PDT 24
Finished Jul 19 06:29:50 PM PDT 24
Peak memory 219208 kb
Host smart-68d2e856-f5b8-48e1-ac26-e88cf08026c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988515317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.988515317
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.2164801554
Short name T323
Test name
Test status
Simulation time 26150245 ps
CPU time 1.35 seconds
Started Jul 19 06:29:40 PM PDT 24
Finished Jul 19 06:29:48 PM PDT 24
Peak memory 219812 kb
Host smart-a1a295bb-9924-4e07-b34e-781edd7a34e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164801554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.2164801554
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.410317585
Short name T305
Test name
Test status
Simulation time 81242659 ps
CPU time 2.99 seconds
Started Jul 19 06:29:50 PM PDT 24
Finished Jul 19 06:29:57 PM PDT 24
Peak memory 220348 kb
Host smart-44d05fb8-fa45-4c15-8c54-3ef16290b558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410317585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.410317585
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/210.edn_genbits.2615478205
Short name T340
Test name
Test status
Simulation time 51416757 ps
CPU time 1.75 seconds
Started Jul 19 06:30:07 PM PDT 24
Finished Jul 19 06:30:17 PM PDT 24
Peak memory 219600 kb
Host smart-a7463afd-9e78-4337-8095-6a87047ba118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615478205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.2615478205
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_genbits.35356552
Short name T327
Test name
Test status
Simulation time 73261466 ps
CPU time 1.63 seconds
Started Jul 19 06:28:01 PM PDT 24
Finished Jul 19 06:28:04 PM PDT 24
Peak memory 218716 kb
Host smart-55de406e-b43a-40bc-ae5f-98041bc179bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35356552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.35356552
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.2908096811
Short name T322
Test name
Test status
Simulation time 53617067 ps
CPU time 1.34 seconds
Started Jul 19 06:30:04 PM PDT 24
Finished Jul 19 06:30:13 PM PDT 24
Peak memory 219020 kb
Host smart-e0b62801-7337-465f-959a-24e2994603ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908096811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2908096811
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.1342222633
Short name T103
Test name
Test status
Simulation time 21600259 ps
CPU time 1.08 seconds
Started Jul 19 06:27:53 PM PDT 24
Finished Jul 19 06:27:57 PM PDT 24
Peak memory 216252 kb
Host smart-dbd91037-b6bd-4a29-acfb-dc897976c947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342222633 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.1342222633
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/193.edn_alert.1175893010
Short name T125
Test name
Test status
Simulation time 44604726 ps
CPU time 1.24 seconds
Started Jul 19 06:30:02 PM PDT 24
Finished Jul 19 06:30:11 PM PDT 24
Peak memory 219760 kb
Host smart-6133476d-bba8-4d7e-aaa1-dba3268656d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175893010 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.1175893010
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.4189346741
Short name T941
Test name
Test status
Simulation time 67509080 ps
CPU time 1.58 seconds
Started Jul 19 06:30:03 PM PDT 24
Finished Jul 19 06:30:12 PM PDT 24
Peak memory 220552 kb
Host smart-a615f78c-0605-41ac-84bb-f1cd3b95de05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189346741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.4189346741
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_err.1905835618
Short name T6
Test name
Test status
Simulation time 20883811 ps
CPU time 1.25 seconds
Started Jul 19 06:28:00 PM PDT 24
Finished Jul 19 06:28:02 PM PDT 24
Peak memory 230040 kb
Host smart-4a3d0c61-0bca-4e58-a7ed-7c0856b84b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905835618 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.1905835618
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1496864503
Short name T1058
Test name
Test status
Simulation time 28584019 ps
CPU time 1.03 seconds
Started Jul 19 04:39:16 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 206756 kb
Host smart-53ddca02-f429-4275-9a94-93923ef3dc27
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496864503 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1496864503
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1780742173
Short name T1001
Test name
Test status
Simulation time 36663761 ps
CPU time 1.99 seconds
Started Jul 19 04:39:19 PM PDT 24
Finished Jul 19 04:39:48 PM PDT 24
Peak memory 206832 kb
Host smart-fbc12c1c-0c02-4775-8cfd-153a4ee32c90
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780742173 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.1780742173
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1368486572
Short name T1080
Test name
Test status
Simulation time 209574834 ps
CPU time 1.24 seconds
Started Jul 19 04:39:17 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 215100 kb
Host smart-4ca24eba-b139-49ff-999d-49d95e508a14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368486572 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.1368486572
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2743079316
Short name T1120
Test name
Test status
Simulation time 15378834 ps
CPU time 0.88 seconds
Started Jul 19 04:39:17 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 206708 kb
Host smart-fbf941bc-55a2-4fb8-9ba0-d0088f7bb590
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743079316 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2743079316
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.111254891
Short name T1105
Test name
Test status
Simulation time 42419673 ps
CPU time 0.8 seconds
Started Jul 19 04:39:18 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 206564 kb
Host smart-00d420c3-6cf2-47dc-bc29-3d334ee1959b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111254891 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.111254891
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3520383855
Short name T1090
Test name
Test status
Simulation time 544792942 ps
CPU time 4.6 seconds
Started Jul 19 04:39:15 PM PDT 24
Finished Jul 19 04:39:50 PM PDT 24
Peak memory 215136 kb
Host smart-0c155ac4-4450-476b-9cc6-5bddd5ebb684
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520383855 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3520383855
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.4117721204
Short name T1066
Test name
Test status
Simulation time 114326693 ps
CPU time 1.41 seconds
Started Jul 19 04:39:18 PM PDT 24
Finished Jul 19 04:39:48 PM PDT 24
Peak memory 206900 kb
Host smart-63867167-fb51-4ccd-889a-a4455549114e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117721204 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.4117721204
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1329907290
Short name T1007
Test name
Test status
Simulation time 24494547 ps
CPU time 1.17 seconds
Started Jul 19 04:39:21 PM PDT 24
Finished Jul 19 04:39:48 PM PDT 24
Peak memory 206800 kb
Host smart-2d265d86-1189-4a69-93ab-9da14fc02f1c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329907290 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1329907290
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3956858519
Short name T1049
Test name
Test status
Simulation time 33844600 ps
CPU time 1.98 seconds
Started Jul 19 04:39:18 PM PDT 24
Finished Jul 19 04:39:48 PM PDT 24
Peak memory 206716 kb
Host smart-3274180a-b2e7-44db-b6e7-295589a48da0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956858519 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.3956858519
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.852670934
Short name T269
Test name
Test status
Simulation time 55399867 ps
CPU time 0.89 seconds
Started Jul 19 04:39:21 PM PDT 24
Finished Jul 19 04:39:48 PM PDT 24
Peak memory 206748 kb
Host smart-a7fd2383-cdd1-45f7-bcb9-7f780402ce4f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852670934 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.852670934
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3772828936
Short name T1069
Test name
Test status
Simulation time 219769741 ps
CPU time 1.32 seconds
Started Jul 19 04:39:16 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 218872 kb
Host smart-3dac1f22-efc9-48f9-bd6b-352c5c4c5546
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772828936 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3772828936
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.3789484507
Short name T1077
Test name
Test status
Simulation time 36068514 ps
CPU time 0.86 seconds
Started Jul 19 04:39:20 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 206716 kb
Host smart-48841b22-dcec-41f8-8667-d59aa01d4269
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789484507 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3789484507
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.343932497
Short name T1093
Test name
Test status
Simulation time 22358901 ps
CPU time 0.85 seconds
Started Jul 19 04:39:17 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 206776 kb
Host smart-6cba328a-16e0-414b-8787-8c324bff0ae8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343932497 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.343932497
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2929098812
Short name T1084
Test name
Test status
Simulation time 388904886 ps
CPU time 1.57 seconds
Started Jul 19 04:39:16 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 206784 kb
Host smart-a4ea82d3-6769-4219-9713-d24d5321f68a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929098812 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.2929098812
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.3725049787
Short name T1098
Test name
Test status
Simulation time 356287213 ps
CPU time 2.64 seconds
Started Jul 19 04:39:17 PM PDT 24
Finished Jul 19 04:39:49 PM PDT 24
Peak memory 215096 kb
Host smart-8019d392-69eb-47ae-8e53-2c01751812af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725049787 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3725049787
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3550124427
Short name T1052
Test name
Test status
Simulation time 33633852 ps
CPU time 1.23 seconds
Started Jul 19 04:39:29 PM PDT 24
Finished Jul 19 04:39:57 PM PDT 24
Peak memory 215056 kb
Host smart-e3283467-83bc-467a-9877-14a3564e342c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550124427 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.3550124427
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.2407322031
Short name T1121
Test name
Test status
Simulation time 13729944 ps
CPU time 0.89 seconds
Started Jul 19 04:39:26 PM PDT 24
Finished Jul 19 04:39:55 PM PDT 24
Peak memory 206760 kb
Host smart-6888c5a7-ebd6-4327-ae03-56bde1374040
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407322031 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.2407322031
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2656703217
Short name T1062
Test name
Test status
Simulation time 12577921 ps
CPU time 0.86 seconds
Started Jul 19 04:39:30 PM PDT 24
Finished Jul 19 04:39:56 PM PDT 24
Peak memory 206744 kb
Host smart-bd7d6d58-8771-442e-a021-9852749c5e94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656703217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2656703217
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2460339842
Short name T1088
Test name
Test status
Simulation time 607934488 ps
CPU time 1.53 seconds
Started Jul 19 04:39:30 PM PDT 24
Finished Jul 19 04:39:57 PM PDT 24
Peak memory 206804 kb
Host smart-b1127572-1649-4e6e-80ed-b1debfec07ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460339842 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2460339842
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.3215646067
Short name T1106
Test name
Test status
Simulation time 115612253 ps
CPU time 3.5 seconds
Started Jul 19 04:39:29 PM PDT 24
Finished Jul 19 04:39:59 PM PDT 24
Peak memory 215052 kb
Host smart-5f985fa6-5b9e-47b7-9889-bb980b57a944
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215646067 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.3215646067
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.221330078
Short name T1044
Test name
Test status
Simulation time 283286151 ps
CPU time 2.34 seconds
Started Jul 19 04:39:27 PM PDT 24
Finished Jul 19 04:39:57 PM PDT 24
Peak memory 207036 kb
Host smart-932457eb-48b0-43db-94fc-2fa328d19ed9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221330078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.221330078
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.269077407
Short name T1019
Test name
Test status
Simulation time 55245307 ps
CPU time 1.11 seconds
Started Jul 19 04:39:27 PM PDT 24
Finished Jul 19 04:39:56 PM PDT 24
Peak memory 215120 kb
Host smart-94af72d8-e13e-4e11-880e-ea1d552662de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269077407 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.269077407
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.2204972871
Short name T264
Test name
Test status
Simulation time 11971015 ps
CPU time 0.89 seconds
Started Jul 19 04:39:30 PM PDT 24
Finished Jul 19 04:39:57 PM PDT 24
Peak memory 206712 kb
Host smart-0532d824-1847-4431-9984-724c7d581ac6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204972871 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.2204972871
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.2320182671
Short name T1042
Test name
Test status
Simulation time 47244546 ps
CPU time 0.83 seconds
Started Jul 19 04:39:28 PM PDT 24
Finished Jul 19 04:39:56 PM PDT 24
Peak memory 206756 kb
Host smart-8b439703-f2ed-4368-8470-87dd8e53a74f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320182671 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2320182671
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.919282870
Short name T260
Test name
Test status
Simulation time 160799344 ps
CPU time 1.56 seconds
Started Jul 19 04:39:30 PM PDT 24
Finished Jul 19 04:39:57 PM PDT 24
Peak memory 206796 kb
Host smart-b4cb1a95-9144-4c99-a172-f52adcf80a5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919282870 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_ou
tstanding.919282870
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.2031017798
Short name T1076
Test name
Test status
Simulation time 23637413 ps
CPU time 1.61 seconds
Started Jul 19 04:39:28 PM PDT 24
Finished Jul 19 04:39:56 PM PDT 24
Peak memory 223284 kb
Host smart-18240a66-a8ed-4d38-81e3-175756b3f97c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031017798 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2031017798
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2178881595
Short name T1096
Test name
Test status
Simulation time 382109361 ps
CPU time 1.5 seconds
Started Jul 19 04:39:31 PM PDT 24
Finished Jul 19 04:39:58 PM PDT 24
Peak memory 206928 kb
Host smart-6ae8174f-9f2f-4edf-ac86-9aa6ed106162
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178881595 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.2178881595
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.403752268
Short name T1054
Test name
Test status
Simulation time 24538480 ps
CPU time 1.16 seconds
Started Jul 19 04:39:30 PM PDT 24
Finished Jul 19 04:39:57 PM PDT 24
Peak memory 215212 kb
Host smart-f8f29a45-70c1-4b83-88fa-5d2a43bc9f0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403752268 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.403752268
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.4001188909
Short name T280
Test name
Test status
Simulation time 39411973 ps
CPU time 0.85 seconds
Started Jul 19 04:39:29 PM PDT 24
Finished Jul 19 04:39:56 PM PDT 24
Peak memory 206752 kb
Host smart-11bb0080-e9e0-4a2a-8a91-41f1109b2957
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001188909 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.4001188909
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.3979755497
Short name T1082
Test name
Test status
Simulation time 53256333 ps
CPU time 0.91 seconds
Started Jul 19 04:39:30 PM PDT 24
Finished Jul 19 04:39:56 PM PDT 24
Peak memory 206772 kb
Host smart-3f919833-488e-433a-91e8-3ec3bd07ef41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979755497 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.3979755497
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3383820161
Short name T1092
Test name
Test status
Simulation time 54586084 ps
CPU time 1.29 seconds
Started Jul 19 04:39:27 PM PDT 24
Finished Jul 19 04:39:56 PM PDT 24
Peak memory 206848 kb
Host smart-977d43ef-f627-4c5a-be38-d18d19aef942
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383820161 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.3383820161
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3475572077
Short name T1129
Test name
Test status
Simulation time 33799145 ps
CPU time 2.15 seconds
Started Jul 19 04:39:28 PM PDT 24
Finished Jul 19 04:39:57 PM PDT 24
Peak memory 214628 kb
Host smart-efe834eb-60f9-400c-a19b-ad6d095bcf4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475572077 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3475572077
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1870806709
Short name T300
Test name
Test status
Simulation time 670887084 ps
CPU time 1.59 seconds
Started Jul 19 04:39:26 PM PDT 24
Finished Jul 19 04:39:56 PM PDT 24
Peak memory 206728 kb
Host smart-7a2e6790-f9fd-41db-875c-3ee80b370715
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870806709 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.1870806709
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.789855405
Short name T1051
Test name
Test status
Simulation time 78521669 ps
CPU time 1.53 seconds
Started Jul 19 04:39:29 PM PDT 24
Finished Jul 19 04:39:57 PM PDT 24
Peak memory 215180 kb
Host smart-a70ed2f8-c667-4c04-88ff-dcdbb2e1522c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789855405 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.789855405
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.243121227
Short name T271
Test name
Test status
Simulation time 37587386 ps
CPU time 0.86 seconds
Started Jul 19 04:39:30 PM PDT 24
Finished Jul 19 04:39:56 PM PDT 24
Peak memory 206812 kb
Host smart-b2950cf5-e7ba-4cd8-adaa-e91b289bbd66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243121227 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.243121227
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.2397712720
Short name T1085
Test name
Test status
Simulation time 28873370 ps
CPU time 0.79 seconds
Started Jul 19 04:39:30 PM PDT 24
Finished Jul 19 04:39:56 PM PDT 24
Peak memory 206608 kb
Host smart-dd6002f2-256c-4dba-854a-c1bfdaeb8ed2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397712720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.2397712720
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3721156563
Short name T1073
Test name
Test status
Simulation time 63191760 ps
CPU time 1.2 seconds
Started Jul 19 04:39:29 PM PDT 24
Finished Jul 19 04:39:57 PM PDT 24
Peak memory 206808 kb
Host smart-cff28b19-c34b-431b-8c61-d8cfcf5f5f9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721156563 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.3721156563
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.2145097000
Short name T1112
Test name
Test status
Simulation time 64760689 ps
CPU time 2.68 seconds
Started Jul 19 04:39:30 PM PDT 24
Finished Jul 19 04:39:58 PM PDT 24
Peak memory 218908 kb
Host smart-1e6c719a-6763-46fc-94ed-79f61cfb69f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145097000 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2145097000
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2118105369
Short name T292
Test name
Test status
Simulation time 83179122 ps
CPU time 1.47 seconds
Started Jul 19 04:39:29 PM PDT 24
Finished Jul 19 04:39:57 PM PDT 24
Peak memory 206844 kb
Host smart-2bcf3a18-f178-4358-9ae1-1f5e148580ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118105369 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.2118105369
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1204916287
Short name T999
Test name
Test status
Simulation time 30643303 ps
CPU time 1.36 seconds
Started Jul 19 04:39:31 PM PDT 24
Finished Jul 19 04:39:57 PM PDT 24
Peak memory 215092 kb
Host smart-c10e3a57-a6a7-4793-8593-8ffd0e2f13c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204916287 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1204916287
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.976741829
Short name T1060
Test name
Test status
Simulation time 43880238 ps
CPU time 0.89 seconds
Started Jul 19 04:39:28 PM PDT 24
Finished Jul 19 04:39:56 PM PDT 24
Peak memory 206820 kb
Host smart-00994aa1-f34e-4ab0-bb14-bf7e1ad39c47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976741829 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.976741829
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.553121970
Short name T1104
Test name
Test status
Simulation time 52580131 ps
CPU time 0.85 seconds
Started Jul 19 04:39:29 PM PDT 24
Finished Jul 19 04:39:56 PM PDT 24
Peak memory 206736 kb
Host smart-7e66d484-22d4-4a72-8d0a-077390d177e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553121970 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.553121970
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1427997355
Short name T259
Test name
Test status
Simulation time 21426398 ps
CPU time 1.28 seconds
Started Jul 19 04:39:29 PM PDT 24
Finished Jul 19 04:39:56 PM PDT 24
Peak memory 206788 kb
Host smart-8aa4cfef-0899-4696-9d1f-8a5f5ac9a720
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427997355 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.1427997355
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.1330057609
Short name T1029
Test name
Test status
Simulation time 225889387 ps
CPU time 3.84 seconds
Started Jul 19 04:39:31 PM PDT 24
Finished Jul 19 04:40:00 PM PDT 24
Peak memory 215060 kb
Host smart-db8bb50f-93b1-4ab2-8b45-31906383e461
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330057609 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1330057609
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2393482769
Short name T1094
Test name
Test status
Simulation time 50927143 ps
CPU time 1.58 seconds
Started Jul 19 04:39:28 PM PDT 24
Finished Jul 19 04:39:56 PM PDT 24
Peak memory 206804 kb
Host smart-bf832fb8-5cc3-4c86-b9ce-2f5ef0e6b2de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393482769 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.2393482769
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3017113531
Short name T1087
Test name
Test status
Simulation time 27963566 ps
CPU time 1 seconds
Started Jul 19 04:39:40 PM PDT 24
Finished Jul 19 04:40:05 PM PDT 24
Peak memory 206880 kb
Host smart-613ba846-a895-4d23-8142-f9a54ac924b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017113531 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.3017113531
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.2415348479
Short name T261
Test name
Test status
Simulation time 14877476 ps
CPU time 0.95 seconds
Started Jul 19 04:39:36 PM PDT 24
Finished Jul 19 04:40:02 PM PDT 24
Peak memory 206756 kb
Host smart-1ea39159-0162-4f0c-8cc0-95e2c4835fdf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415348479 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2415348479
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.4073203878
Short name T1091
Test name
Test status
Simulation time 13098121 ps
CPU time 0.84 seconds
Started Jul 19 04:39:35 PM PDT 24
Finished Jul 19 04:40:01 PM PDT 24
Peak memory 206816 kb
Host smart-d0ba737c-d524-4f3e-8a98-87acd5cbfde7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073203878 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.4073203878
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2459129701
Short name T1075
Test name
Test status
Simulation time 17479842 ps
CPU time 1.05 seconds
Started Jul 19 04:39:35 PM PDT 24
Finished Jul 19 04:40:01 PM PDT 24
Peak memory 206808 kb
Host smart-02232759-ff14-4596-a729-3d006b3b9cd5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459129701 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.2459129701
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.1262549261
Short name T1064
Test name
Test status
Simulation time 223164241 ps
CPU time 3.55 seconds
Started Jul 19 04:39:29 PM PDT 24
Finished Jul 19 04:39:59 PM PDT 24
Peak memory 215076 kb
Host smart-8c0a0558-bf3a-4489-8411-b32bc3cc8aa6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262549261 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.1262549261
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2515935406
Short name T302
Test name
Test status
Simulation time 90998327 ps
CPU time 2.53 seconds
Started Jul 19 04:39:28 PM PDT 24
Finished Jul 19 04:39:57 PM PDT 24
Peak memory 215016 kb
Host smart-855486e7-9fb2-4075-b25c-f73ccf03560a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515935406 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2515935406
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1451662036
Short name T1083
Test name
Test status
Simulation time 40205076 ps
CPU time 1.13 seconds
Started Jul 19 04:39:39 PM PDT 24
Finished Jul 19 04:40:04 PM PDT 24
Peak memory 215072 kb
Host smart-1ef105e4-c1e0-4e20-a0fb-d2c7b2904314
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451662036 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.1451662036
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.4041891825
Short name T268
Test name
Test status
Simulation time 19034559 ps
CPU time 0.85 seconds
Started Jul 19 04:39:36 PM PDT 24
Finished Jul 19 04:40:02 PM PDT 24
Peak memory 206596 kb
Host smart-a42dc8f2-e602-4d46-988d-415b71a96701
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041891825 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.4041891825
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3977439621
Short name T1101
Test name
Test status
Simulation time 14310602 ps
CPU time 0.87 seconds
Started Jul 19 04:39:39 PM PDT 24
Finished Jul 19 04:40:05 PM PDT 24
Peak memory 206836 kb
Host smart-4dee9f29-568a-4d26-b09b-0958c930c94d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977439621 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3977439621
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1997970474
Short name T1059
Test name
Test status
Simulation time 72092694 ps
CPU time 1.51 seconds
Started Jul 19 04:39:37 PM PDT 24
Finished Jul 19 04:40:03 PM PDT 24
Peak memory 206792 kb
Host smart-12e10b2f-dc36-4428-8ba7-4f01fc643879
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997970474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.1997970474
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.4044821883
Short name T1015
Test name
Test status
Simulation time 66204526 ps
CPU time 2.5 seconds
Started Jul 19 04:39:39 PM PDT 24
Finished Jul 19 04:40:06 PM PDT 24
Peak memory 215160 kb
Host smart-e71bc066-909f-4b2d-96f0-7d991c4cab7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044821883 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.4044821883
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2044136089
Short name T1061
Test name
Test status
Simulation time 87293054 ps
CPU time 1.55 seconds
Started Jul 19 04:39:36 PM PDT 24
Finished Jul 19 04:40:02 PM PDT 24
Peak memory 215032 kb
Host smart-f06619ab-327e-45cc-8981-d64112906691
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044136089 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.2044136089
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2998521308
Short name T1125
Test name
Test status
Simulation time 35888659 ps
CPU time 1.07 seconds
Started Jul 19 04:39:37 PM PDT 24
Finished Jul 19 04:40:02 PM PDT 24
Peak memory 216980 kb
Host smart-9fbf6ea1-72e7-43ef-aed2-7a9dba41de85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998521308 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2998521308
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.2155033042
Short name T263
Test name
Test status
Simulation time 54407219 ps
CPU time 0.89 seconds
Started Jul 19 04:39:36 PM PDT 24
Finished Jul 19 04:40:02 PM PDT 24
Peak memory 206792 kb
Host smart-e0ccae4c-e834-402f-8a3e-9bfbbb992c1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155033042 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2155033042
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.1282277504
Short name T1009
Test name
Test status
Simulation time 23208071 ps
CPU time 0.82 seconds
Started Jul 19 04:39:38 PM PDT 24
Finished Jul 19 04:40:02 PM PDT 24
Peak memory 206840 kb
Host smart-eca20f29-ef45-4228-a8b5-2cd7007d57e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282277504 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1282277504
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2894797179
Short name T275
Test name
Test status
Simulation time 44957092 ps
CPU time 1.28 seconds
Started Jul 19 04:39:37 PM PDT 24
Finished Jul 19 04:40:02 PM PDT 24
Peak memory 206804 kb
Host smart-03d38997-527f-4084-8a4d-02f61f5eae20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894797179 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.2894797179
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.1830211186
Short name T1016
Test name
Test status
Simulation time 111441008 ps
CPU time 2.39 seconds
Started Jul 19 04:39:36 PM PDT 24
Finished Jul 19 04:40:03 PM PDT 24
Peak memory 215140 kb
Host smart-a99ce966-433c-4717-b602-3c6226b0140e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830211186 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.1830211186
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.900434382
Short name T293
Test name
Test status
Simulation time 78712113 ps
CPU time 1.58 seconds
Started Jul 19 04:39:35 PM PDT 24
Finished Jul 19 04:40:02 PM PDT 24
Peak memory 206840 kb
Host smart-dd2bf563-3dbb-4a7e-a17d-0a424c266221
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900434382 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.900434382
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3224666959
Short name T1074
Test name
Test status
Simulation time 51568018 ps
CPU time 1 seconds
Started Jul 19 04:39:33 PM PDT 24
Finished Jul 19 04:40:00 PM PDT 24
Peak memory 206868 kb
Host smart-8f37cfe1-70cb-4465-a634-3dc54bb373b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224666959 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3224666959
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1835437691
Short name T266
Test name
Test status
Simulation time 43622327 ps
CPU time 0.86 seconds
Started Jul 19 04:39:40 PM PDT 24
Finished Jul 19 04:40:05 PM PDT 24
Peak memory 206740 kb
Host smart-4ccc5d31-07b7-441b-ac22-013910e6159c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835437691 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1835437691
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.3112261826
Short name T1027
Test name
Test status
Simulation time 12270821 ps
CPU time 0.85 seconds
Started Jul 19 04:39:42 PM PDT 24
Finished Jul 19 04:40:05 PM PDT 24
Peak memory 206740 kb
Host smart-a46372a4-0185-4ace-98b7-baa95f41f882
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112261826 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.3112261826
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.418048882
Short name T1071
Test name
Test status
Simulation time 39200224 ps
CPU time 0.97 seconds
Started Jul 19 04:39:35 PM PDT 24
Finished Jul 19 04:40:01 PM PDT 24
Peak memory 206844 kb
Host smart-c097a3dc-60dd-4a3b-867d-3a9ca41531ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418048882 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_ou
tstanding.418048882
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.1581822381
Short name T1037
Test name
Test status
Simulation time 26954405 ps
CPU time 1.68 seconds
Started Jul 19 04:39:38 PM PDT 24
Finished Jul 19 04:40:04 PM PDT 24
Peak memory 215120 kb
Host smart-bd2e39bd-b6a8-4ae8-8ba0-34f661f1d2b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581822381 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.1581822381
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.857566439
Short name T1070
Test name
Test status
Simulation time 68034485 ps
CPU time 1.88 seconds
Started Jul 19 04:39:44 PM PDT 24
Finished Jul 19 04:40:07 PM PDT 24
Peak memory 215136 kb
Host smart-82709473-d6c7-4e4d-b930-20fee160ea48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857566439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.857566439
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1523570202
Short name T1047
Test name
Test status
Simulation time 151773879 ps
CPU time 1.33 seconds
Started Jul 19 04:39:37 PM PDT 24
Finished Jul 19 04:40:02 PM PDT 24
Peak memory 215160 kb
Host smart-f0082ccb-b33e-4f12-8c6b-6723c7f7cc24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523570202 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.1523570202
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2337679633
Short name T1089
Test name
Test status
Simulation time 38369116 ps
CPU time 0.81 seconds
Started Jul 19 04:39:39 PM PDT 24
Finished Jul 19 04:40:05 PM PDT 24
Peak memory 206564 kb
Host smart-a15398fb-1823-4194-9d2e-af96981f86d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337679633 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2337679633
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.946828025
Short name T1013
Test name
Test status
Simulation time 142098296 ps
CPU time 0.78 seconds
Started Jul 19 04:39:35 PM PDT 24
Finished Jul 19 04:40:01 PM PDT 24
Peak memory 206544 kb
Host smart-612f1fee-6668-46c5-8ffd-f5638bd5163e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946828025 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.946828025
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1151720635
Short name T1048
Test name
Test status
Simulation time 68788264 ps
CPU time 1.36 seconds
Started Jul 19 04:39:35 PM PDT 24
Finished Jul 19 04:40:02 PM PDT 24
Peak memory 206812 kb
Host smart-dfc0f991-004b-4ade-85a4-61a1920573a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151720635 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.1151720635
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1808540350
Short name T1028
Test name
Test status
Simulation time 1583463991 ps
CPU time 3.61 seconds
Started Jul 19 04:39:44 PM PDT 24
Finished Jul 19 04:40:08 PM PDT 24
Peak memory 215048 kb
Host smart-c01d114f-64fa-4177-9580-c28866e249a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808540350 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1808540350
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.4278242973
Short name T1040
Test name
Test status
Simulation time 374451363 ps
CPU time 1.55 seconds
Started Jul 19 04:39:36 PM PDT 24
Finished Jul 19 04:40:02 PM PDT 24
Peak memory 207032 kb
Host smart-0ad8d9ec-65e8-481b-a729-8097483529fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278242973 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.4278242973
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2584659859
Short name T262
Test name
Test status
Simulation time 203459198 ps
CPU time 1.51 seconds
Started Jul 19 04:39:18 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 206820 kb
Host smart-f797c11f-4dfe-46ca-8e2e-31755d326d50
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584659859 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.2584659859
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.526678597
Short name T1043
Test name
Test status
Simulation time 699954500 ps
CPU time 5.07 seconds
Started Jul 19 04:39:17 PM PDT 24
Finished Jul 19 04:39:51 PM PDT 24
Peak memory 206756 kb
Host smart-dce7cc61-3551-4541-b6fd-ca6b2659f98a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526678597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.526678597
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.457206734
Short name T267
Test name
Test status
Simulation time 23602553 ps
CPU time 1.02 seconds
Started Jul 19 04:39:17 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 206756 kb
Host smart-0be61b17-f5eb-45c5-8bcb-981c22fc730d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457206734 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.457206734
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3024883503
Short name T1130
Test name
Test status
Simulation time 36416386 ps
CPU time 1.17 seconds
Started Jul 19 04:39:19 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 215168 kb
Host smart-db573191-ceb5-493c-b577-f1a63a31f326
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024883503 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3024883503
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.3467084326
Short name T1078
Test name
Test status
Simulation time 15052272 ps
CPU time 0.92 seconds
Started Jul 19 04:39:15 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 206816 kb
Host smart-d92525b6-d88d-45e5-8681-db20673b87f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467084326 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3467084326
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1182780527
Short name T1000
Test name
Test status
Simulation time 53001120 ps
CPU time 0.83 seconds
Started Jul 19 04:39:21 PM PDT 24
Finished Jul 19 04:39:48 PM PDT 24
Peak memory 206748 kb
Host smart-f37723d0-fcb4-408f-8022-03eeea9e2695
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182780527 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1182780527
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3430627804
Short name T277
Test name
Test status
Simulation time 41450724 ps
CPU time 1.56 seconds
Started Jul 19 04:39:17 PM PDT 24
Finished Jul 19 04:39:48 PM PDT 24
Peak memory 206812 kb
Host smart-85e86332-5967-43e6-a2b5-e2695098181f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430627804 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.3430627804
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.3516414498
Short name T1039
Test name
Test status
Simulation time 79914484 ps
CPU time 2.88 seconds
Started Jul 19 04:39:15 PM PDT 24
Finished Jul 19 04:39:49 PM PDT 24
Peak memory 215092 kb
Host smart-90cfb3c7-f34a-4b11-acdd-a2acfc7c35dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516414498 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.3516414498
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.3545594364
Short name T1024
Test name
Test status
Simulation time 44526057 ps
CPU time 0.83 seconds
Started Jul 19 04:39:35 PM PDT 24
Finished Jul 19 04:40:01 PM PDT 24
Peak memory 206716 kb
Host smart-ecd220ee-9337-4499-a383-6a9d8c3d7c6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545594364 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3545594364
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.1166145752
Short name T1003
Test name
Test status
Simulation time 39902099 ps
CPU time 0.79 seconds
Started Jul 19 04:39:40 PM PDT 24
Finished Jul 19 04:40:05 PM PDT 24
Peak memory 206572 kb
Host smart-f817927e-decb-42cf-a686-5363d7282751
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166145752 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.1166145752
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.2997177477
Short name T1038
Test name
Test status
Simulation time 14698946 ps
CPU time 0.9 seconds
Started Jul 19 04:39:35 PM PDT 24
Finished Jul 19 04:40:01 PM PDT 24
Peak memory 206728 kb
Host smart-33375d14-1480-44bc-9015-d36fe9e01428
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997177477 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2997177477
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.3853228582
Short name T1010
Test name
Test status
Simulation time 58546791 ps
CPU time 0.9 seconds
Started Jul 19 04:39:36 PM PDT 24
Finished Jul 19 04:40:02 PM PDT 24
Peak memory 206700 kb
Host smart-9e8d7c8d-daa6-422d-a699-9c6d4b6664e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853228582 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3853228582
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.430398371
Short name T1050
Test name
Test status
Simulation time 21737917 ps
CPU time 0.87 seconds
Started Jul 19 04:39:36 PM PDT 24
Finished Jul 19 04:40:02 PM PDT 24
Peak memory 206760 kb
Host smart-6eae404e-97c9-4ab7-b301-87a3079c356c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430398371 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.430398371
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.2734632199
Short name T1018
Test name
Test status
Simulation time 15714075 ps
CPU time 1 seconds
Started Jul 19 04:39:40 PM PDT 24
Finished Jul 19 04:40:05 PM PDT 24
Peak memory 206760 kb
Host smart-f5b8b615-453a-48fa-b3d7-b324d11bae9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734632199 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.2734632199
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.1681340341
Short name T1005
Test name
Test status
Simulation time 55711508 ps
CPU time 0.93 seconds
Started Jul 19 04:39:36 PM PDT 24
Finished Jul 19 04:40:02 PM PDT 24
Peak memory 206708 kb
Host smart-8678d669-d575-4a8e-8e67-284ff94bc1a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681340341 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.1681340341
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.2842176655
Short name T1100
Test name
Test status
Simulation time 14012779 ps
CPU time 0.84 seconds
Started Jul 19 04:39:40 PM PDT 24
Finished Jul 19 04:40:05 PM PDT 24
Peak memory 206744 kb
Host smart-56dab980-0619-431f-b2d2-da0f4a9307ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842176655 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.2842176655
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.3734039600
Short name T1004
Test name
Test status
Simulation time 18267887 ps
CPU time 0.83 seconds
Started Jul 19 04:39:42 PM PDT 24
Finished Jul 19 04:40:05 PM PDT 24
Peak memory 206744 kb
Host smart-5670c59e-8eb6-4e62-bb29-89b4c3061934
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734039600 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.3734039600
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.3782612709
Short name T1017
Test name
Test status
Simulation time 36667862 ps
CPU time 0.78 seconds
Started Jul 19 04:39:39 PM PDT 24
Finished Jul 19 04:40:04 PM PDT 24
Peak memory 206656 kb
Host smart-5f483e0c-2722-4d9d-ac75-cabb04f59e94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782612709 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.3782612709
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1849343709
Short name T265
Test name
Test status
Simulation time 80680960 ps
CPU time 1.17 seconds
Started Jul 19 04:39:18 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 206772 kb
Host smart-8131d2bf-4ede-4dd6-990a-0c214c7d0610
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849343709 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.1849343709
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.4160691816
Short name T274
Test name
Test status
Simulation time 2087690823 ps
CPU time 6.73 seconds
Started Jul 19 04:39:19 PM PDT 24
Finished Jul 19 04:39:53 PM PDT 24
Peak memory 206732 kb
Host smart-5b4b416b-0e6f-4920-acb1-4970883373d1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160691816 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.4160691816
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.378351916
Short name T1008
Test name
Test status
Simulation time 16018212 ps
CPU time 0.92 seconds
Started Jul 19 04:39:16 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 206960 kb
Host smart-9bd0d0cb-2ebb-411a-baf2-ee690fdbc3f7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378351916 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.378351916
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1616457578
Short name T1115
Test name
Test status
Simulation time 32536823 ps
CPU time 1.25 seconds
Started Jul 19 04:39:18 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 217632 kb
Host smart-213c52bb-377c-4140-8c6c-b08a9a762d55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616457578 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.1616457578
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.3789514909
Short name T1108
Test name
Test status
Simulation time 25294279 ps
CPU time 0.87 seconds
Started Jul 19 04:39:17 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 206740 kb
Host smart-48836006-4dbc-4d3b-90f9-d27c00b4d9e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789514909 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.3789514909
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.2553300543
Short name T997
Test name
Test status
Simulation time 41102708 ps
CPU time 0.85 seconds
Started Jul 19 04:39:17 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 206736 kb
Host smart-a0d968ff-be67-40f9-85a9-d9e4e7656ea7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553300543 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.2553300543
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.181958500
Short name T1099
Test name
Test status
Simulation time 16429838 ps
CPU time 1.11 seconds
Started Jul 19 04:39:17 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 206820 kb
Host smart-751ce607-444b-4f20-a562-0f61e7c5cc73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181958500 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_out
standing.181958500
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.1563427658
Short name T1032
Test name
Test status
Simulation time 84607112 ps
CPU time 2.73 seconds
Started Jul 19 04:39:17 PM PDT 24
Finished Jul 19 04:39:49 PM PDT 24
Peak memory 215080 kb
Host smart-da14af3f-aa9f-4f7e-b08d-354d78e6f58b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563427658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.1563427658
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2841794715
Short name T299
Test name
Test status
Simulation time 94797675 ps
CPU time 2.41 seconds
Started Jul 19 04:39:19 PM PDT 24
Finished Jul 19 04:39:49 PM PDT 24
Peak memory 206952 kb
Host smart-7c642427-ee24-4e43-afb6-7af6a1e46734
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841794715 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.2841794715
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.1093882791
Short name T1045
Test name
Test status
Simulation time 132292121 ps
CPU time 0.83 seconds
Started Jul 19 04:39:43 PM PDT 24
Finished Jul 19 04:40:05 PM PDT 24
Peak memory 206724 kb
Host smart-86b7e4d9-428f-4397-98c2-e79d53f2f112
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093882791 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.1093882791
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.1710625465
Short name T1031
Test name
Test status
Simulation time 37331576 ps
CPU time 0.76 seconds
Started Jul 19 04:39:37 PM PDT 24
Finished Jul 19 04:40:02 PM PDT 24
Peak memory 206580 kb
Host smart-7b89e1b7-7eda-4ee3-8fce-70a6c8543b00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710625465 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.1710625465
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.818889780
Short name T1126
Test name
Test status
Simulation time 24038201 ps
CPU time 0.82 seconds
Started Jul 19 04:39:35 PM PDT 24
Finished Jul 19 04:40:01 PM PDT 24
Peak memory 206972 kb
Host smart-aa1c4d50-ef93-43ea-8985-f55c6a6b886f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818889780 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.818889780
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.1477490019
Short name T1002
Test name
Test status
Simulation time 100284745 ps
CPU time 0.84 seconds
Started Jul 19 04:39:38 PM PDT 24
Finished Jul 19 04:40:03 PM PDT 24
Peak memory 206592 kb
Host smart-608edd28-dce4-4803-8177-5b9f8c5101b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477490019 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.1477490019
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.3328863640
Short name T1116
Test name
Test status
Simulation time 45829151 ps
CPU time 0.87 seconds
Started Jul 19 04:39:43 PM PDT 24
Finished Jul 19 04:40:06 PM PDT 24
Peak memory 206768 kb
Host smart-fd408973-323e-400a-8aa6-041372c4a323
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328863640 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3328863640
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.91295192
Short name T1117
Test name
Test status
Simulation time 41164218 ps
CPU time 0.93 seconds
Started Jul 19 04:39:36 PM PDT 24
Finished Jul 19 04:40:02 PM PDT 24
Peak memory 206736 kb
Host smart-02e3b6f7-c12b-4cd2-b393-d51447c176dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91295192 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.91295192
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.1293526524
Short name T1021
Test name
Test status
Simulation time 47033307 ps
CPU time 0.86 seconds
Started Jul 19 04:39:40 PM PDT 24
Finished Jul 19 04:40:05 PM PDT 24
Peak memory 206760 kb
Host smart-7ea53410-5765-47f5-9e27-61a4bd741fd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293526524 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.1293526524
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.1730905795
Short name T1057
Test name
Test status
Simulation time 29000389 ps
CPU time 0.78 seconds
Started Jul 19 04:39:36 PM PDT 24
Finished Jul 19 04:40:02 PM PDT 24
Peak memory 206628 kb
Host smart-26f5296a-0909-4b37-978e-24cbfc0251d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730905795 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1730905795
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.578256559
Short name T1119
Test name
Test status
Simulation time 26124457 ps
CPU time 0.8 seconds
Started Jul 19 04:39:39 PM PDT 24
Finished Jul 19 04:40:04 PM PDT 24
Peak memory 206748 kb
Host smart-0c3176f8-d633-4d35-981f-c263d48c9c8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578256559 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.578256559
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.4249651195
Short name T1025
Test name
Test status
Simulation time 35376072 ps
CPU time 0.83 seconds
Started Jul 19 04:39:43 PM PDT 24
Finished Jul 19 04:40:05 PM PDT 24
Peak memory 206720 kb
Host smart-aee2fc13-d33f-4244-b0e8-7ab15a4af458
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249651195 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.4249651195
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2248502618
Short name T1127
Test name
Test status
Simulation time 34558987 ps
CPU time 1.52 seconds
Started Jul 19 04:39:30 PM PDT 24
Finished Jul 19 04:39:57 PM PDT 24
Peak memory 206732 kb
Host smart-23859bcb-e595-4da5-8b4a-a4e18b2bcd2f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248502618 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.2248502618
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3462736164
Short name T272
Test name
Test status
Simulation time 134835844 ps
CPU time 3.65 seconds
Started Jul 19 04:39:27 PM PDT 24
Finished Jul 19 04:39:58 PM PDT 24
Peak memory 206980 kb
Host smart-9bdd0b3d-1fe4-4092-baef-fb42db3e7b3b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462736164 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.3462736164
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3994453333
Short name T1067
Test name
Test status
Simulation time 15378869 ps
CPU time 0.97 seconds
Started Jul 19 04:39:27 PM PDT 24
Finished Jul 19 04:39:56 PM PDT 24
Peak memory 206716 kb
Host smart-f703cae1-1d8f-461d-b243-cbfaaf4b0cfb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994453333 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3994453333
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3518358726
Short name T1124
Test name
Test status
Simulation time 41193826 ps
CPU time 1.35 seconds
Started Jul 19 04:39:28 PM PDT 24
Finished Jul 19 04:39:56 PM PDT 24
Peak memory 215072 kb
Host smart-6b19961a-91e7-45bd-b55a-c07d94a1ed78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518358726 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.3518358726
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.4012095666
Short name T1110
Test name
Test status
Simulation time 112808377 ps
CPU time 0.94 seconds
Started Jul 19 04:39:28 PM PDT 24
Finished Jul 19 04:39:56 PM PDT 24
Peak memory 206788 kb
Host smart-f0a19ada-965d-4d12-8567-432f6009016a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012095666 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.4012095666
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.1222890998
Short name T1035
Test name
Test status
Simulation time 19547085 ps
CPU time 0.79 seconds
Started Jul 19 04:39:28 PM PDT 24
Finished Jul 19 04:39:55 PM PDT 24
Peak memory 206552 kb
Host smart-714e1abf-bfb2-4507-97c5-57dc77839033
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222890998 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1222890998
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.607120508
Short name T1111
Test name
Test status
Simulation time 29545010 ps
CPU time 1.3 seconds
Started Jul 19 04:39:27 PM PDT 24
Finished Jul 19 04:39:55 PM PDT 24
Peak memory 206808 kb
Host smart-4c34b4df-601a-4375-afe0-c0f47f95e3f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607120508 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_out
standing.607120508
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.3016967430
Short name T1123
Test name
Test status
Simulation time 103533050 ps
CPU time 3.72 seconds
Started Jul 19 04:39:28 PM PDT 24
Finished Jul 19 04:39:59 PM PDT 24
Peak memory 215128 kb
Host smart-d5d87308-c725-4e13-bfe0-cd543c2530c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016967430 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.3016967430
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2068039092
Short name T1030
Test name
Test status
Simulation time 48746156 ps
CPU time 1.71 seconds
Started Jul 19 04:39:30 PM PDT 24
Finished Jul 19 04:39:57 PM PDT 24
Peak memory 215024 kb
Host smart-3aab6b5c-cbcd-4377-a625-ae639e1fda63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068039092 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.2068039092
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.2035803717
Short name T1079
Test name
Test status
Simulation time 11680807 ps
CPU time 0.88 seconds
Started Jul 19 04:39:36 PM PDT 24
Finished Jul 19 04:40:02 PM PDT 24
Peak memory 206972 kb
Host smart-6d60d260-96aa-42eb-a040-404ab873e263
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035803717 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.2035803717
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.1329658315
Short name T998
Test name
Test status
Simulation time 18350248 ps
CPU time 0.81 seconds
Started Jul 19 04:39:36 PM PDT 24
Finished Jul 19 04:40:02 PM PDT 24
Peak memory 206760 kb
Host smart-a8988526-b2c9-47c5-af45-d0947dd6f33c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329658315 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1329658315
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.3939448844
Short name T1023
Test name
Test status
Simulation time 44191904 ps
CPU time 0.85 seconds
Started Jul 19 04:39:43 PM PDT 24
Finished Jul 19 04:40:05 PM PDT 24
Peak memory 206688 kb
Host smart-0f552946-f77e-4f56-9877-1f34c2a0e428
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939448844 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3939448844
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.3012591190
Short name T1053
Test name
Test status
Simulation time 52238134 ps
CPU time 0.89 seconds
Started Jul 19 04:39:43 PM PDT 24
Finished Jul 19 04:40:05 PM PDT 24
Peak memory 206716 kb
Host smart-39dbcb50-2052-4a1d-8601-b0da4f498bfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012591190 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.3012591190
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.3548495835
Short name T1006
Test name
Test status
Simulation time 45984646 ps
CPU time 0.85 seconds
Started Jul 19 04:39:35 PM PDT 24
Finished Jul 19 04:40:02 PM PDT 24
Peak memory 206768 kb
Host smart-8ddb1618-0568-4e20-a318-cc53eba0c392
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548495835 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.3548495835
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.2693954678
Short name T1056
Test name
Test status
Simulation time 38955786 ps
CPU time 0.77 seconds
Started Jul 19 04:39:36 PM PDT 24
Finished Jul 19 04:40:02 PM PDT 24
Peak memory 206500 kb
Host smart-4e2dbd05-dd5a-4a16-ae97-5166d4e169ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693954678 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.2693954678
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.757782861
Short name T1068
Test name
Test status
Simulation time 75020358 ps
CPU time 0.9 seconds
Started Jul 19 04:39:37 PM PDT 24
Finished Jul 19 04:40:02 PM PDT 24
Peak memory 206568 kb
Host smart-109ea4a7-b7f5-445d-8300-49ee72cbafd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757782861 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.757782861
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.3256342133
Short name T1036
Test name
Test status
Simulation time 29847596 ps
CPU time 0.83 seconds
Started Jul 19 04:39:36 PM PDT 24
Finished Jul 19 04:40:02 PM PDT 24
Peak memory 206560 kb
Host smart-14dabf7d-314b-49c0-8bdd-5fff07d9e06c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256342133 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.3256342133
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.3643002411
Short name T1020
Test name
Test status
Simulation time 42219666 ps
CPU time 0.93 seconds
Started Jul 19 04:39:37 PM PDT 24
Finished Jul 19 04:40:02 PM PDT 24
Peak memory 206752 kb
Host smart-6fee082a-0503-4751-a9e5-383dfdbde4bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643002411 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3643002411
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.2027591404
Short name T1011
Test name
Test status
Simulation time 61238721 ps
CPU time 0.9 seconds
Started Jul 19 04:39:37 PM PDT 24
Finished Jul 19 04:40:02 PM PDT 24
Peak memory 206728 kb
Host smart-560bb851-a075-4178-9465-2be5a452372c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027591404 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.2027591404
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.859091465
Short name T1072
Test name
Test status
Simulation time 70383917 ps
CPU time 1.08 seconds
Started Jul 19 04:39:31 PM PDT 24
Finished Jul 19 04:39:57 PM PDT 24
Peak memory 216564 kb
Host smart-93d51115-ff13-4289-b4a1-ecd0b34837b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859091465 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.859091465
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.1784627299
Short name T1014
Test name
Test status
Simulation time 20423709 ps
CPU time 0.86 seconds
Started Jul 19 04:39:28 PM PDT 24
Finished Jul 19 04:39:56 PM PDT 24
Peak memory 206172 kb
Host smart-e6ab7389-9642-4436-98d1-624d625c2f4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784627299 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.1784627299
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.3208257569
Short name T1055
Test name
Test status
Simulation time 20424684 ps
CPU time 0.83 seconds
Started Jul 19 04:39:26 PM PDT 24
Finished Jul 19 04:39:55 PM PDT 24
Peak memory 206744 kb
Host smart-0a6e2ad8-4c07-4cd6-8c54-57b4595f2c36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208257569 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.3208257569
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3906198587
Short name T276
Test name
Test status
Simulation time 17516869 ps
CPU time 1.12 seconds
Started Jul 19 04:39:29 PM PDT 24
Finished Jul 19 04:39:56 PM PDT 24
Peak memory 206760 kb
Host smart-5c21ebd0-67a4-4ce1-96d6-bf0803c37629
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906198587 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.3906198587
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.53903755
Short name T1122
Test name
Test status
Simulation time 623537766 ps
CPU time 4.64 seconds
Started Jul 19 04:39:27 PM PDT 24
Finished Jul 19 04:39:59 PM PDT 24
Peak memory 215148 kb
Host smart-59469a2a-6c73-4b46-b4aa-dfb5b4bb9c2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53903755 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.53903755
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2138569701
Short name T1081
Test name
Test status
Simulation time 121340338 ps
CPU time 2.79 seconds
Started Jul 19 04:39:30 PM PDT 24
Finished Jul 19 04:39:58 PM PDT 24
Peak memory 206788 kb
Host smart-ed56916a-a08a-4854-9f4f-a7564a045dd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138569701 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2138569701
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1432752006
Short name T1012
Test name
Test status
Simulation time 20542702 ps
CPU time 1.06 seconds
Started Jul 19 04:39:28 PM PDT 24
Finished Jul 19 04:39:56 PM PDT 24
Peak memory 207028 kb
Host smart-2c231bbb-eab9-4ad3-8c99-a0a818f18db6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432752006 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1432752006
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.1434656743
Short name T273
Test name
Test status
Simulation time 57145521 ps
CPU time 0.82 seconds
Started Jul 19 04:39:28 PM PDT 24
Finished Jul 19 04:39:55 PM PDT 24
Peak memory 206664 kb
Host smart-d47db70b-0feb-4697-80c9-8a9b0bdc6ce2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434656743 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1434656743
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.2067163217
Short name T1095
Test name
Test status
Simulation time 47725185 ps
CPU time 0.88 seconds
Started Jul 19 04:39:32 PM PDT 24
Finished Jul 19 04:39:58 PM PDT 24
Peak memory 206752 kb
Host smart-dace5f50-2ff1-40fe-9514-d30ae29184aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067163217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.2067163217
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1293983571
Short name T258
Test name
Test status
Simulation time 35133622 ps
CPU time 1.4 seconds
Started Jul 19 04:39:29 PM PDT 24
Finished Jul 19 04:39:57 PM PDT 24
Peak memory 206776 kb
Host smart-d1f112a7-7649-4e7d-9a47-cc8cd604c70a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293983571 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.1293983571
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3493881267
Short name T1026
Test name
Test status
Simulation time 42428608 ps
CPU time 1.58 seconds
Started Jul 19 04:39:29 PM PDT 24
Finished Jul 19 04:39:57 PM PDT 24
Peak memory 215256 kb
Host smart-0ad32657-05d6-4531-b0d4-57e8528a9281
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493881267 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3493881267
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2309355713
Short name T1103
Test name
Test status
Simulation time 77954288 ps
CPU time 1.47 seconds
Started Jul 19 04:39:29 PM PDT 24
Finished Jul 19 04:39:57 PM PDT 24
Peak memory 206864 kb
Host smart-2af171c3-e09b-4cdb-800a-7351187af8a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309355713 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.2309355713
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2339484440
Short name T1022
Test name
Test status
Simulation time 24517791 ps
CPU time 1.22 seconds
Started Jul 19 04:39:28 PM PDT 24
Finished Jul 19 04:39:56 PM PDT 24
Peak memory 215136 kb
Host smart-f0cb9cfc-a5c1-494f-bff6-df810276259d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339484440 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2339484440
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.218611529
Short name T1118
Test name
Test status
Simulation time 36026457 ps
CPU time 0.9 seconds
Started Jul 19 04:39:30 PM PDT 24
Finished Jul 19 04:39:56 PM PDT 24
Peak memory 206740 kb
Host smart-bcba061e-25cd-4ac9-a444-817ba8fb3662
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218611529 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.218611529
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.3127296275
Short name T1097
Test name
Test status
Simulation time 13560761 ps
CPU time 0.89 seconds
Started Jul 19 04:39:32 PM PDT 24
Finished Jul 19 04:39:58 PM PDT 24
Peak memory 206772 kb
Host smart-eb6cea6c-06d6-475a-8006-0c62d3a62e67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127296275 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.3127296275
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1736435751
Short name T279
Test name
Test status
Simulation time 29987475 ps
CPU time 1.31 seconds
Started Jul 19 04:39:29 PM PDT 24
Finished Jul 19 04:39:57 PM PDT 24
Peak memory 206836 kb
Host smart-efcd2004-ea9e-4d1f-9afe-e6f8d0bbf54b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736435751 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.1736435751
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.3280616701
Short name T1109
Test name
Test status
Simulation time 294330094 ps
CPU time 2.23 seconds
Started Jul 19 04:39:30 PM PDT 24
Finished Jul 19 04:39:58 PM PDT 24
Peak memory 215064 kb
Host smart-587aaf1c-ed60-401c-b9c7-e6264a05629e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280616701 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.3280616701
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.283393766
Short name T1065
Test name
Test status
Simulation time 137927718 ps
CPU time 2.2 seconds
Started Jul 19 04:39:29 PM PDT 24
Finished Jul 19 04:39:58 PM PDT 24
Peak memory 206792 kb
Host smart-b7ea259a-d4de-4b37-8993-e7ae00abff4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283393766 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.283393766
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.4263526799
Short name T1107
Test name
Test status
Simulation time 214365761 ps
CPU time 1.15 seconds
Started Jul 19 04:39:27 PM PDT 24
Finished Jul 19 04:39:55 PM PDT 24
Peak memory 217060 kb
Host smart-a37fea32-2f9d-4939-89e9-a01ff4f9fc63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263526799 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.4263526799
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.3033293146
Short name T1128
Test name
Test status
Simulation time 18431315 ps
CPU time 0.84 seconds
Started Jul 19 04:39:31 PM PDT 24
Finished Jul 19 04:39:58 PM PDT 24
Peak memory 206564 kb
Host smart-64d27bd3-0898-43d3-be2e-cc1477f671ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033293146 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.3033293146
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.489845349
Short name T1063
Test name
Test status
Simulation time 44320730 ps
CPU time 0.88 seconds
Started Jul 19 04:39:26 PM PDT 24
Finished Jul 19 04:39:55 PM PDT 24
Peak memory 206704 kb
Host smart-5235b379-cd95-4558-bc88-30b11676a89a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489845349 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.489845349
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2179057327
Short name T1102
Test name
Test status
Simulation time 93963394 ps
CPU time 1.57 seconds
Started Jul 19 04:39:31 PM PDT 24
Finished Jul 19 04:39:58 PM PDT 24
Peak memory 206760 kb
Host smart-46fab0d8-84f5-4788-92cb-9f409517600b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179057327 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.2179057327
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.709880829
Short name T1113
Test name
Test status
Simulation time 151669108 ps
CPU time 3.38 seconds
Started Jul 19 04:39:26 PM PDT 24
Finished Jul 19 04:39:57 PM PDT 24
Peak memory 215156 kb
Host smart-abf06c65-b183-4113-a43a-c5bdd3305f31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709880829 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.709880829
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.4196918744
Short name T1033
Test name
Test status
Simulation time 111627507 ps
CPU time 2.75 seconds
Started Jul 19 04:39:27 PM PDT 24
Finished Jul 19 04:39:57 PM PDT 24
Peak memory 215152 kb
Host smart-c60d887e-9012-45aa-b856-3445e1f5cf80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196918744 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.4196918744
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.973184562
Short name T1046
Test name
Test status
Simulation time 29976922 ps
CPU time 1.11 seconds
Started Jul 19 04:39:27 PM PDT 24
Finished Jul 19 04:39:56 PM PDT 24
Peak memory 215216 kb
Host smart-ebc2a81a-44a2-41c4-b4e9-f95b67a0c01e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973184562 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.973184562
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2039831530
Short name T1034
Test name
Test status
Simulation time 27281538 ps
CPU time 0.91 seconds
Started Jul 19 04:39:27 PM PDT 24
Finished Jul 19 04:39:55 PM PDT 24
Peak memory 206688 kb
Host smart-1ebf0d81-adca-45c5-a35f-3c8742f11680
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039831530 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2039831530
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2009904740
Short name T1114
Test name
Test status
Simulation time 32263883 ps
CPU time 0.8 seconds
Started Jul 19 04:39:26 PM PDT 24
Finished Jul 19 04:39:55 PM PDT 24
Peak memory 206572 kb
Host smart-47de96d7-5509-4622-b795-77315f54a6db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009904740 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2009904740
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2781557921
Short name T281
Test name
Test status
Simulation time 32949901 ps
CPU time 1.1 seconds
Started Jul 19 04:39:28 PM PDT 24
Finished Jul 19 04:39:56 PM PDT 24
Peak memory 206884 kb
Host smart-9f280efe-00c5-4f05-b6b3-e41d5ae72e5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781557921 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.2781557921
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.1244401870
Short name T1086
Test name
Test status
Simulation time 163668181 ps
CPU time 3.04 seconds
Started Jul 19 04:39:25 PM PDT 24
Finished Jul 19 04:39:57 PM PDT 24
Peak memory 215248 kb
Host smart-bd281444-7945-48fb-8967-11dc5afbba20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244401870 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1244401870
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3418149737
Short name T1041
Test name
Test status
Simulation time 588133067 ps
CPU time 1.6 seconds
Started Jul 19 04:39:26 PM PDT 24
Finished Jul 19 04:39:56 PM PDT 24
Peak memory 215048 kb
Host smart-f0336bee-0f8f-4808-804d-60170a7aeccf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418149737 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3418149737
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert_test.665445996
Short name T939
Test name
Test status
Simulation time 58920008 ps
CPU time 1 seconds
Started Jul 19 06:27:05 PM PDT 24
Finished Jul 19 06:27:07 PM PDT 24
Peak memory 215496 kb
Host smart-bcd397c4-f476-497f-9e8a-1517fd7cc885
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665445996 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.665445996
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.2614832555
Short name T231
Test name
Test status
Simulation time 31157943 ps
CPU time 0.86 seconds
Started Jul 19 06:27:01 PM PDT 24
Finished Jul 19 06:27:02 PM PDT 24
Peak memory 215672 kb
Host smart-c5b1265c-f3b8-42a9-8646-37dc39f4527a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614832555 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.2614832555
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_err.2039299636
Short name T789
Test name
Test status
Simulation time 19181423 ps
CPU time 1.08 seconds
Started Jul 19 06:27:00 PM PDT 24
Finished Jul 19 06:27:02 PM PDT 24
Peak memory 218684 kb
Host smart-44d75e9e-6606-41d4-8ec2-adbd295b2656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039299636 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.2039299636
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.2941816746
Short name T457
Test name
Test status
Simulation time 46694322 ps
CPU time 1.15 seconds
Started Jul 19 06:27:03 PM PDT 24
Finished Jul 19 06:27:05 PM PDT 24
Peak memory 218584 kb
Host smart-db031aad-a752-4875-863a-956a10f5bce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941816746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2941816746
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.642650555
Short name T406
Test name
Test status
Simulation time 22457281 ps
CPU time 1.09 seconds
Started Jul 19 06:27:03 PM PDT 24
Finished Jul 19 06:27:05 PM PDT 24
Peak memory 215740 kb
Host smart-241a616f-ef9b-4bb7-8e36-f181e291bd19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642650555 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.642650555
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_sec_cm.2532695968
Short name T18
Test name
Test status
Simulation time 265122029 ps
CPU time 4.62 seconds
Started Jul 19 06:27:02 PM PDT 24
Finished Jul 19 06:27:08 PM PDT 24
Peak memory 235560 kb
Host smart-72f6d4e4-c4d8-4ea0-9da2-62534bf10270
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532695968 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.2532695968
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.3816258364
Short name T729
Test name
Test status
Simulation time 39245357 ps
CPU time 0.89 seconds
Started Jul 19 06:26:56 PM PDT 24
Finished Jul 19 06:26:58 PM PDT 24
Peak memory 215568 kb
Host smart-a398ccf0-fb2c-4655-a59f-a5314b1021a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816258364 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.3816258364
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.1542273796
Short name T839
Test name
Test status
Simulation time 222008913 ps
CPU time 2.41 seconds
Started Jul 19 06:27:01 PM PDT 24
Finished Jul 19 06:27:04 PM PDT 24
Peak memory 217580 kb
Host smart-430472d8-c2cb-4afa-aa06-cf110f594e11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542273796 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.1542273796
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.3108268605
Short name T520
Test name
Test status
Simulation time 335046191573 ps
CPU time 2254.29 seconds
Started Jul 19 06:27:01 PM PDT 24
Finished Jul 19 07:04:36 PM PDT 24
Peak memory 230200 kb
Host smart-062e7835-ee3e-4277-a29d-a15f431c80fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108268605 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.3108268605
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.1085556418
Short name T256
Test name
Test status
Simulation time 32267685 ps
CPU time 1.31 seconds
Started Jul 19 06:27:00 PM PDT 24
Finished Jul 19 06:27:02 PM PDT 24
Peak memory 219832 kb
Host smart-22af0051-b33f-4b08-8455-c597de90e8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085556418 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1085556418
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_disable.801679353
Short name T470
Test name
Test status
Simulation time 20483749 ps
CPU time 0.89 seconds
Started Jul 19 06:27:02 PM PDT 24
Finished Jul 19 06:27:04 PM PDT 24
Peak memory 216564 kb
Host smart-bbf5fd58-183e-4a81-a971-8d980590be99
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801679353 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.801679353
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2703006189
Short name T536
Test name
Test status
Simulation time 57072969 ps
CPU time 1.15 seconds
Started Jul 19 06:27:05 PM PDT 24
Finished Jul 19 06:27:06 PM PDT 24
Peak memory 218760 kb
Host smart-61ab07db-e4ce-402a-a0d6-898fcf0b864d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703006189 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2703006189
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.821940748
Short name T617
Test name
Test status
Simulation time 28340885 ps
CPU time 1 seconds
Started Jul 19 06:27:01 PM PDT 24
Finished Jul 19 06:27:03 PM PDT 24
Peak memory 219932 kb
Host smart-571efd9e-56dd-44b9-af92-2e998085629d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821940748 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.821940748
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_intr.63359066
Short name T871
Test name
Test status
Simulation time 35550707 ps
CPU time 1.07 seconds
Started Jul 19 06:27:01 PM PDT 24
Finished Jul 19 06:27:03 PM PDT 24
Peak memory 224164 kb
Host smart-9e0bd44d-d64e-4db8-92b8-4279b0f7a0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63359066 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.63359066
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.2138968382
Short name T904
Test name
Test status
Simulation time 23846160 ps
CPU time 0.96 seconds
Started Jul 19 06:27:00 PM PDT 24
Finished Jul 19 06:27:01 PM PDT 24
Peak memory 207356 kb
Host smart-50bca0e5-1ac2-4a97-926c-c79a7a2789d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138968382 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.2138968382
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_smoke.2339222165
Short name T664
Test name
Test status
Simulation time 25522733 ps
CPU time 0.97 seconds
Started Jul 19 06:27:01 PM PDT 24
Finished Jul 19 06:27:03 PM PDT 24
Peak memory 215532 kb
Host smart-adf95247-d33b-496e-8f1d-6b39c5f23ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339222165 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.2339222165
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.3604637846
Short name T4
Test name
Test status
Simulation time 74021888 ps
CPU time 1.06 seconds
Started Jul 19 06:27:03 PM PDT 24
Finished Jul 19 06:27:04 PM PDT 24
Peak memory 206852 kb
Host smart-5b0a4246-83ac-425c-92e9-0f54496e07cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604637846 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.3604637846
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.505181774
Short name T627
Test name
Test status
Simulation time 250994901721 ps
CPU time 1495.1 seconds
Started Jul 19 06:27:01 PM PDT 24
Finished Jul 19 06:51:58 PM PDT 24
Peak memory 224396 kb
Host smart-f0d3cf57-bae9-483f-985f-990ecde4fdaf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505181774 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.505181774
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.1154243765
Short name T926
Test name
Test status
Simulation time 44070882 ps
CPU time 1.23 seconds
Started Jul 19 06:27:38 PM PDT 24
Finished Jul 19 06:27:40 PM PDT 24
Peak memory 220140 kb
Host smart-8abf2a2d-c2c9-44e7-9800-0888aa5487bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154243765 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.1154243765
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.2949129466
Short name T983
Test name
Test status
Simulation time 39836110 ps
CPU time 0.87 seconds
Started Jul 19 06:27:38 PM PDT 24
Finished Jul 19 06:27:40 PM PDT 24
Peak memory 215304 kb
Host smart-21d923cb-9e16-46b6-a2cc-8bfc98a5e218
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949129466 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2949129466
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.3160828850
Short name T895
Test name
Test status
Simulation time 86595141 ps
CPU time 1.17 seconds
Started Jul 19 06:27:37 PM PDT 24
Finished Jul 19 06:27:39 PM PDT 24
Peak memory 220348 kb
Host smart-bf2d29eb-60c6-4ea7-a321-94f0233d7187
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160828850 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.3160828850
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.3971193244
Short name T217
Test name
Test status
Simulation time 193282709 ps
CPU time 1.06 seconds
Started Jul 19 06:27:37 PM PDT 24
Finished Jul 19 06:27:39 PM PDT 24
Peak memory 220168 kb
Host smart-6285e880-625a-4e40-b11d-21869d696a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971193244 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.3971193244
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.1806946393
Short name T368
Test name
Test status
Simulation time 44916525 ps
CPU time 1.5 seconds
Started Jul 19 06:27:39 PM PDT 24
Finished Jul 19 06:27:41 PM PDT 24
Peak memory 218772 kb
Host smart-a3d9ca96-dae2-41b9-9769-9d6d020e6302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806946393 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.1806946393
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.212430437
Short name T27
Test name
Test status
Simulation time 21807100 ps
CPU time 0.9 seconds
Started Jul 19 06:27:38 PM PDT 24
Finished Jul 19 06:27:39 PM PDT 24
Peak memory 216068 kb
Host smart-75ea4177-f5f6-4f2a-a2cc-56c752f5bab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212430437 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.212430437
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.1097562792
Short name T916
Test name
Test status
Simulation time 43983000 ps
CPU time 0.94 seconds
Started Jul 19 06:27:38 PM PDT 24
Finished Jul 19 06:27:40 PM PDT 24
Peak memory 215348 kb
Host smart-4157486f-e9a4-4c3d-8d9e-1ff5c3c1e932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097562792 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1097562792
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.3194835493
Short name T108
Test name
Test status
Simulation time 169621967 ps
CPU time 2.25 seconds
Started Jul 19 06:27:37 PM PDT 24
Finished Jul 19 06:27:40 PM PDT 24
Peak memory 218744 kb
Host smart-e7cca94d-aa9a-475c-801f-4fed65d2a0b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194835493 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.3194835493
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.2550673145
Short name T624
Test name
Test status
Simulation time 57647561098 ps
CPU time 1543.64 seconds
Started Jul 19 06:27:36 PM PDT 24
Finished Jul 19 06:53:21 PM PDT 24
Peak memory 224908 kb
Host smart-2fe87cf6-fd64-4a13-9fe7-9beebbb1dcec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550673145 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.2550673145
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.2739068361
Short name T436
Test name
Test status
Simulation time 192191373 ps
CPU time 1.15 seconds
Started Jul 19 06:29:19 PM PDT 24
Finished Jul 19 06:29:26 PM PDT 24
Peak memory 219276 kb
Host smart-f40d5da8-8a07-47aa-af7a-90a1e6550b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739068361 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.2739068361
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.2415989493
Short name T893
Test name
Test status
Simulation time 75992127 ps
CPU time 1.52 seconds
Started Jul 19 06:29:18 PM PDT 24
Finished Jul 19 06:29:25 PM PDT 24
Peak memory 219056 kb
Host smart-ab45a7a5-88ef-49c1-8567-4f1d049da52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415989493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2415989493
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.3838432444
Short name T235
Test name
Test status
Simulation time 114657806 ps
CPU time 1.19 seconds
Started Jul 19 06:29:29 PM PDT 24
Finished Jul 19 06:29:36 PM PDT 24
Peak memory 221724 kb
Host smart-c33fe101-f2a6-4f4f-b8ca-f7d10b80e6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838432444 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.3838432444
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.4131498072
Short name T252
Test name
Test status
Simulation time 40232226 ps
CPU time 1.37 seconds
Started Jul 19 06:29:26 PM PDT 24
Finished Jul 19 06:29:34 PM PDT 24
Peak memory 217452 kb
Host smart-8c7c10c8-d19a-4493-89a4-306d4174acb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131498072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.4131498072
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.973456413
Short name T573
Test name
Test status
Simulation time 55078297 ps
CPU time 1.27 seconds
Started Jul 19 06:29:26 PM PDT 24
Finished Jul 19 06:29:34 PM PDT 24
Peak memory 218760 kb
Host smart-c2458de0-2172-4af9-bdea-fc3c3950d4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973456413 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.973456413
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.955495994
Short name T501
Test name
Test status
Simulation time 75147792 ps
CPU time 1.05 seconds
Started Jul 19 06:29:23 PM PDT 24
Finished Jul 19 06:29:32 PM PDT 24
Peak memory 217548 kb
Host smart-45c0f7e2-dafd-4a49-be33-c7aa0774f46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955495994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.955495994
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.747088407
Short name T290
Test name
Test status
Simulation time 96379772 ps
CPU time 1.34 seconds
Started Jul 19 06:29:24 PM PDT 24
Finished Jul 19 06:29:33 PM PDT 24
Peak memory 215976 kb
Host smart-6242590b-3fd9-44e5-8bb8-142c77ee1f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747088407 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.747088407
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/104.edn_alert.2996144114
Short name T312
Test name
Test status
Simulation time 333644019 ps
CPU time 1.31 seconds
Started Jul 19 06:29:27 PM PDT 24
Finished Jul 19 06:29:34 PM PDT 24
Peak memory 220484 kb
Host smart-b4dc187d-d755-49b9-8057-057673a6aa71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996144114 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.2996144114
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.597182816
Short name T592
Test name
Test status
Simulation time 64683568 ps
CPU time 1.14 seconds
Started Jul 19 06:29:25 PM PDT 24
Finished Jul 19 06:29:33 PM PDT 24
Peak memory 217652 kb
Host smart-ab8b2a9d-b337-4e0d-8446-a8ca367e2459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597182816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.597182816
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.814393467
Short name T120
Test name
Test status
Simulation time 30425181 ps
CPU time 1.29 seconds
Started Jul 19 06:29:25 PM PDT 24
Finished Jul 19 06:29:33 PM PDT 24
Peak memory 220232 kb
Host smart-e74e142e-1d4a-4a2b-9aa5-35a2d260b3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814393467 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.814393467
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.4239161659
Short name T13
Test name
Test status
Simulation time 45135286 ps
CPU time 1.53 seconds
Started Jul 19 06:29:28 PM PDT 24
Finished Jul 19 06:29:35 PM PDT 24
Peak memory 219848 kb
Host smart-29d15954-42e2-4cef-9d9c-4bdaf0f65a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239161659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.4239161659
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.638077817
Short name T676
Test name
Test status
Simulation time 30567919 ps
CPU time 1.4 seconds
Started Jul 19 06:29:28 PM PDT 24
Finished Jul 19 06:29:35 PM PDT 24
Peak memory 220756 kb
Host smart-fae03739-7405-4184-9406-1b201cc3bb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638077817 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.638077817
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.2270862460
Short name T68
Test name
Test status
Simulation time 85682492 ps
CPU time 2.28 seconds
Started Jul 19 06:29:29 PM PDT 24
Finished Jul 19 06:29:38 PM PDT 24
Peak memory 220588 kb
Host smart-922f25d7-1e2a-4ce5-a682-c80cf71448a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270862460 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.2270862460
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.1247325256
Short name T845
Test name
Test status
Simulation time 46932786 ps
CPU time 1.82 seconds
Started Jul 19 06:29:26 PM PDT 24
Finished Jul 19 06:29:34 PM PDT 24
Peak memory 218780 kb
Host smart-5c541993-1d62-4bdf-ba14-876804b31953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247325256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.1247325256
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.1722224571
Short name T39
Test name
Test status
Simulation time 75118374 ps
CPU time 1.24 seconds
Started Jul 19 06:29:28 PM PDT 24
Finished Jul 19 06:29:35 PM PDT 24
Peak memory 218880 kb
Host smart-df27f43e-ca87-44b6-967b-81854b8c3139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722224571 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.1722224571
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.4103894774
Short name T575
Test name
Test status
Simulation time 49304253 ps
CPU time 1.75 seconds
Started Jul 19 06:29:29 PM PDT 24
Finished Jul 19 06:29:37 PM PDT 24
Peak memory 218712 kb
Host smart-bc8805e6-d3c4-4f29-888a-187187b5d471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103894774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.4103894774
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.384415416
Short name T529
Test name
Test status
Simulation time 26412906 ps
CPU time 1.24 seconds
Started Jul 19 06:29:26 PM PDT 24
Finished Jul 19 06:29:34 PM PDT 24
Peak memory 219520 kb
Host smart-84f22e8c-d362-477a-961d-7b6ada31b178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384415416 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.384415416
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.943861358
Short name T40
Test name
Test status
Simulation time 44893775 ps
CPU time 1.29 seconds
Started Jul 19 06:29:24 PM PDT 24
Finished Jul 19 06:29:32 PM PDT 24
Peak memory 218860 kb
Host smart-99fdb89e-1b43-4332-a1bd-27ec22db4a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943861358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.943861358
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.762771505
Short name T69
Test name
Test status
Simulation time 67309308 ps
CPU time 1.15 seconds
Started Jul 19 06:27:37 PM PDT 24
Finished Jul 19 06:27:39 PM PDT 24
Peak memory 220072 kb
Host smart-87a2400b-0d01-4d45-b041-345ce38957b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762771505 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.762771505
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.3758796254
Short name T610
Test name
Test status
Simulation time 13481227 ps
CPU time 0.96 seconds
Started Jul 19 06:27:35 PM PDT 24
Finished Jul 19 06:27:37 PM PDT 24
Peak memory 207056 kb
Host smart-5d1008c6-83dd-483b-af5f-276d5d2a5f62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758796254 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.3758796254
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.2834422634
Short name T224
Test name
Test status
Simulation time 11567825 ps
CPU time 0.98 seconds
Started Jul 19 06:27:36 PM PDT 24
Finished Jul 19 06:27:39 PM PDT 24
Peak memory 216516 kb
Host smart-1dcd659a-2825-41ee-b0b2-1df9d144a46d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834422634 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.2834422634
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_err.404386401
Short name T106
Test name
Test status
Simulation time 32687617 ps
CPU time 0.85 seconds
Started Jul 19 06:27:37 PM PDT 24
Finished Jul 19 06:27:39 PM PDT 24
Peak memory 218672 kb
Host smart-463f813e-cea7-436b-abe8-b7f5bb3be0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404386401 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.404386401
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_intr.2604120583
Short name T499
Test name
Test status
Simulation time 25593744 ps
CPU time 0.89 seconds
Started Jul 19 06:27:35 PM PDT 24
Finished Jul 19 06:27:37 PM PDT 24
Peak memory 215748 kb
Host smart-81df85ad-394e-494b-9fea-38d9301eaade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604120583 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.2604120583
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.3245379554
Short name T77
Test name
Test status
Simulation time 97689462 ps
CPU time 0.84 seconds
Started Jul 19 06:27:37 PM PDT 24
Finished Jul 19 06:27:39 PM PDT 24
Peak memory 215340 kb
Host smart-50bd791b-5afd-4ee7-8ae7-acb484bf5b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245379554 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.3245379554
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.2401739283
Short name T804
Test name
Test status
Simulation time 844747060 ps
CPU time 4.53 seconds
Started Jul 19 06:27:35 PM PDT 24
Finished Jul 19 06:27:40 PM PDT 24
Peak memory 217644 kb
Host smart-720522bd-9aff-440a-8e09-9e62d9beebc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401739283 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.2401739283
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.78650590
Short name T984
Test name
Test status
Simulation time 106308110645 ps
CPU time 616.65 seconds
Started Jul 19 06:27:38 PM PDT 24
Finished Jul 19 06:37:56 PM PDT 24
Peak memory 219964 kb
Host smart-528bb676-2885-40d3-b939-d61d1539db66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78650590 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.78650590
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.287830954
Short name T875
Test name
Test status
Simulation time 75768716 ps
CPU time 1.12 seconds
Started Jul 19 06:29:25 PM PDT 24
Finished Jul 19 06:29:33 PM PDT 24
Peak memory 219732 kb
Host smart-58546002-535d-409a-a66c-bd9332387a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287830954 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.287830954
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.747702773
Short name T768
Test name
Test status
Simulation time 46333678 ps
CPU time 1.76 seconds
Started Jul 19 06:29:25 PM PDT 24
Finished Jul 19 06:29:33 PM PDT 24
Peak memory 217864 kb
Host smart-eb0d921c-5af5-405b-972c-41d16859d170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747702773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.747702773
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.4163010809
Short name T603
Test name
Test status
Simulation time 37448253 ps
CPU time 1.13 seconds
Started Jul 19 06:29:25 PM PDT 24
Finished Jul 19 06:29:33 PM PDT 24
Peak memory 221404 kb
Host smart-a992cef8-343c-47a2-a8e2-5eb59eb6749f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163010809 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.4163010809
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.3702754806
Short name T698
Test name
Test status
Simulation time 47987745 ps
CPU time 1.8 seconds
Started Jul 19 06:29:26 PM PDT 24
Finished Jul 19 06:29:34 PM PDT 24
Peak memory 218884 kb
Host smart-81876be4-9128-4a61-8ab3-05041812ac39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702754806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.3702754806
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.3376255298
Short name T944
Test name
Test status
Simulation time 416125198 ps
CPU time 1.65 seconds
Started Jul 19 06:29:29 PM PDT 24
Finished Jul 19 06:29:36 PM PDT 24
Peak memory 222000 kb
Host smart-a7388ed0-6c8f-43b6-8a81-4c4d49259db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376255298 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.3376255298
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.1529676771
Short name T354
Test name
Test status
Simulation time 48834609 ps
CPU time 1.53 seconds
Started Jul 19 06:29:23 PM PDT 24
Finished Jul 19 06:29:32 PM PDT 24
Peak memory 218624 kb
Host smart-ccc86afb-e38b-4b89-941d-77677aec7243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529676771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1529676771
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.2022432630
Short name T494
Test name
Test status
Simulation time 24036560 ps
CPU time 1.27 seconds
Started Jul 19 06:29:26 PM PDT 24
Finished Jul 19 06:29:34 PM PDT 24
Peak memory 220148 kb
Host smart-9e4ed5cb-9d80-4436-9704-1c6c7ddde499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022432630 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.2022432630
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/114.edn_alert.3316116980
Short name T138
Test name
Test status
Simulation time 65002813 ps
CPU time 1.14 seconds
Started Jul 19 06:29:27 PM PDT 24
Finished Jul 19 06:29:34 PM PDT 24
Peak memory 218968 kb
Host smart-4a34a627-50fb-4124-9516-7167fc9cff95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316116980 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.3316116980
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.557895928
Short name T981
Test name
Test status
Simulation time 42813632 ps
CPU time 1.45 seconds
Started Jul 19 06:29:28 PM PDT 24
Finished Jul 19 06:29:35 PM PDT 24
Peak memory 218612 kb
Host smart-db86e89c-ff94-4683-bca7-9b1a9423e648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557895928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.557895928
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.3870167101
Short name T594
Test name
Test status
Simulation time 51399233 ps
CPU time 1.28 seconds
Started Jul 19 06:29:27 PM PDT 24
Finished Jul 19 06:29:34 PM PDT 24
Peak memory 220240 kb
Host smart-1b20057b-fab5-4618-b2ac-2f21096b6726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870167101 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.3870167101
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.1385998233
Short name T616
Test name
Test status
Simulation time 63835644 ps
CPU time 1.54 seconds
Started Jul 19 06:29:27 PM PDT 24
Finished Jul 19 06:29:35 PM PDT 24
Peak memory 218696 kb
Host smart-e261aecd-41d4-4bbc-928f-dc2d9ac656ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385998233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.1385998233
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.176921315
Short name T835
Test name
Test status
Simulation time 315329329 ps
CPU time 1.25 seconds
Started Jul 19 06:29:29 PM PDT 24
Finished Jul 19 06:29:36 PM PDT 24
Peak memory 219016 kb
Host smart-05614d52-68d3-417b-ad8b-d5276c659aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176921315 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.176921315
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.1927866230
Short name T781
Test name
Test status
Simulation time 27986389 ps
CPU time 1.15 seconds
Started Jul 19 06:29:25 PM PDT 24
Finished Jul 19 06:29:33 PM PDT 24
Peak memory 217948 kb
Host smart-aa33dc1b-e6c9-484a-b815-7dfcbfa8f4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927866230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1927866230
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.1061064903
Short name T974
Test name
Test status
Simulation time 25483519 ps
CPU time 1.19 seconds
Started Jul 19 06:29:27 PM PDT 24
Finished Jul 19 06:29:34 PM PDT 24
Peak memory 219168 kb
Host smart-2fe22718-bb50-4c09-ad21-30c4841cf39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061064903 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.1061064903
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.158735735
Short name T679
Test name
Test status
Simulation time 72526027 ps
CPU time 1.02 seconds
Started Jul 19 06:29:30 PM PDT 24
Finished Jul 19 06:29:39 PM PDT 24
Peak memory 217624 kb
Host smart-0205d05b-9a6b-4ab0-8ee3-f5ee194d0039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158735735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.158735735
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.1965853173
Short name T606
Test name
Test status
Simulation time 2219804110 ps
CPU time 68.29 seconds
Started Jul 19 06:29:30 PM PDT 24
Finished Jul 19 06:30:46 PM PDT 24
Peak memory 220632 kb
Host smart-bdd426f1-78a8-46e0-a824-cbfc22a2598a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965853173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1965853173
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.452708201
Short name T722
Test name
Test status
Simulation time 66814035 ps
CPU time 1.19 seconds
Started Jul 19 06:29:27 PM PDT 24
Finished Jul 19 06:29:34 PM PDT 24
Peak memory 219100 kb
Host smart-08a598bf-d2e8-4dda-983c-3ecbafaa1a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452708201 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.452708201
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.241649757
Short name T609
Test name
Test status
Simulation time 54408080 ps
CPU time 1.19 seconds
Started Jul 19 06:29:24 PM PDT 24
Finished Jul 19 06:29:33 PM PDT 24
Peak memory 217476 kb
Host smart-acb4911d-59d3-4612-9b52-ce23bb3b3854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241649757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.241649757
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.4106555204
Short name T656
Test name
Test status
Simulation time 63794585 ps
CPU time 1.08 seconds
Started Jul 19 06:27:47 PM PDT 24
Finished Jul 19 06:27:50 PM PDT 24
Peak memory 219124 kb
Host smart-b4d78c88-2488-4761-ba71-f9e60cfc7da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106555204 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.4106555204
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.4144389421
Short name T391
Test name
Test status
Simulation time 79228891 ps
CPU time 0.97 seconds
Started Jul 19 06:27:43 PM PDT 24
Finished Jul 19 06:27:44 PM PDT 24
Peak memory 207068 kb
Host smart-5a748c7a-f8c9-4088-a29c-b9559e963ced
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144389421 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.4144389421
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.3825287085
Short name T519
Test name
Test status
Simulation time 10064942 ps
CPU time 0.87 seconds
Started Jul 19 06:27:46 PM PDT 24
Finished Jul 19 06:27:48 PM PDT 24
Peak memory 215660 kb
Host smart-0b82a7e4-9a36-4762-87e1-cf0315a8a4b4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825287085 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.3825287085
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.698835831
Short name T699
Test name
Test status
Simulation time 67097549 ps
CPU time 1.04 seconds
Started Jul 19 06:27:44 PM PDT 24
Finished Jul 19 06:27:47 PM PDT 24
Peak memory 217328 kb
Host smart-5e18d6a9-05be-4590-b7a2-1c755d09f521
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698835831 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_di
sable_auto_req_mode.698835831
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.3567268661
Short name T596
Test name
Test status
Simulation time 29931725 ps
CPU time 1.31 seconds
Started Jul 19 06:27:45 PM PDT 24
Finished Jul 19 06:27:48 PM PDT 24
Peak memory 219936 kb
Host smart-993ea5cb-1f49-47db-95a9-d48af40fe861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567268661 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3567268661
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.2180177230
Short name T898
Test name
Test status
Simulation time 97243306 ps
CPU time 1.17 seconds
Started Jul 19 06:27:45 PM PDT 24
Finished Jul 19 06:27:48 PM PDT 24
Peak memory 218960 kb
Host smart-b567e4e6-380d-4fda-bc92-4e03734eef13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180177230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2180177230
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.2004878622
Short name T607
Test name
Test status
Simulation time 21283519 ps
CPU time 1.22 seconds
Started Jul 19 06:27:44 PM PDT 24
Finished Jul 19 06:27:46 PM PDT 24
Peak memory 224400 kb
Host smart-2d569dc5-37ca-4cec-bf0a-fe325de943fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004878622 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.2004878622
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.839014975
Short name T806
Test name
Test status
Simulation time 34760320 ps
CPU time 0.89 seconds
Started Jul 19 06:27:46 PM PDT 24
Finished Jul 19 06:27:48 PM PDT 24
Peak memory 215568 kb
Host smart-e91c4292-e5ef-4c5b-b0e7-105376d0d276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839014975 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.839014975
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.880125677
Short name T812
Test name
Test status
Simulation time 293569684 ps
CPU time 4.08 seconds
Started Jul 19 06:27:46 PM PDT 24
Finished Jul 19 06:27:52 PM PDT 24
Peak memory 218704 kb
Host smart-92c9fe39-3ce3-4069-a2ab-542a7b2b983b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880125677 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.880125677
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.3940708207
Short name T544
Test name
Test status
Simulation time 7443888952 ps
CPU time 164.37 seconds
Started Jul 19 06:27:44 PM PDT 24
Finished Jul 19 06:30:29 PM PDT 24
Peak memory 221768 kb
Host smart-862c7b40-9a67-4265-8dbc-9f2328a686ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940708207 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.3940708207
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.981682570
Short name T553
Test name
Test status
Simulation time 28543665 ps
CPU time 1.16 seconds
Started Jul 19 06:29:27 PM PDT 24
Finished Jul 19 06:29:34 PM PDT 24
Peak memory 219088 kb
Host smart-7f2883c5-9591-4a1f-902a-9f81e883ba16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981682570 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.981682570
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.2643692068
Short name T586
Test name
Test status
Simulation time 45432741 ps
CPU time 1.15 seconds
Started Jul 19 06:29:24 PM PDT 24
Finished Jul 19 06:29:32 PM PDT 24
Peak memory 217604 kb
Host smart-2ce243ff-32ce-45ff-bc61-b58beafb2246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643692068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.2643692068
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.1005030316
Short name T491
Test name
Test status
Simulation time 27701855 ps
CPU time 1.27 seconds
Started Jul 19 06:29:26 PM PDT 24
Finished Jul 19 06:29:33 PM PDT 24
Peak memory 218972 kb
Host smart-169b476e-5b27-4169-8aa3-533d3c6a9ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005030316 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.1005030316
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.2531127160
Short name T978
Test name
Test status
Simulation time 27910425 ps
CPU time 1.41 seconds
Started Jul 19 06:29:28 PM PDT 24
Finished Jul 19 06:29:36 PM PDT 24
Peak memory 218744 kb
Host smart-9f64f4e2-5999-4e5a-97be-d7a93611486e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531127160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.2531127160
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.3496183177
Short name T233
Test name
Test status
Simulation time 49947324 ps
CPU time 1.34 seconds
Started Jul 19 06:29:27 PM PDT 24
Finished Jul 19 06:29:35 PM PDT 24
Peak memory 218860 kb
Host smart-feb0ea1e-b075-4fde-8506-360c981fce4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496183177 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.3496183177
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.711572127
Short name T523
Test name
Test status
Simulation time 48429398 ps
CPU time 1.64 seconds
Started Jul 19 06:29:24 PM PDT 24
Finished Jul 19 06:29:33 PM PDT 24
Peak memory 220184 kb
Host smart-554c040e-10da-4319-9460-bc253cee6cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711572127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.711572127
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.1974357972
Short name T914
Test name
Test status
Simulation time 41480282 ps
CPU time 1.13 seconds
Started Jul 19 06:29:28 PM PDT 24
Finished Jul 19 06:29:36 PM PDT 24
Peak memory 220200 kb
Host smart-d58286ab-1641-4998-81ea-73e1cd49ef3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974357972 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.1974357972
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.2209927590
Short name T920
Test name
Test status
Simulation time 221295997 ps
CPU time 3.84 seconds
Started Jul 19 06:29:26 PM PDT 24
Finished Jul 19 06:29:36 PM PDT 24
Peak memory 219024 kb
Host smart-2f783ee3-1d6d-41ae-b211-9c6d22244428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209927590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2209927590
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.2349722788
Short name T533
Test name
Test status
Simulation time 72948115 ps
CPU time 1.07 seconds
Started Jul 19 06:29:28 PM PDT 24
Finished Jul 19 06:29:36 PM PDT 24
Peak memory 218912 kb
Host smart-64121c76-40ad-4a11-8587-23367211b40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349722788 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.2349722788
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.3023292321
Short name T856
Test name
Test status
Simulation time 51549339 ps
CPU time 1.52 seconds
Started Jul 19 06:29:29 PM PDT 24
Finished Jul 19 06:29:37 PM PDT 24
Peak memory 219572 kb
Host smart-3af2292c-93d5-4aca-9734-76658e57d816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023292321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.3023292321
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.2753362234
Short name T595
Test name
Test status
Simulation time 217073016 ps
CPU time 1.27 seconds
Started Jul 19 06:29:34 PM PDT 24
Finished Jul 19 06:29:42 PM PDT 24
Peak memory 219960 kb
Host smart-ab69ebd8-9fc0-4e7b-8424-d4402bada293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753362234 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.2753362234
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.963824872
Short name T394
Test name
Test status
Simulation time 89398856 ps
CPU time 1.16 seconds
Started Jul 19 06:29:29 PM PDT 24
Finished Jul 19 06:29:37 PM PDT 24
Peak memory 220268 kb
Host smart-8ab6d55b-273b-48ec-b123-3d389e62af5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963824872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.963824872
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.3676643713
Short name T473
Test name
Test status
Simulation time 66933991 ps
CPU time 1.39 seconds
Started Jul 19 06:29:36 PM PDT 24
Finished Jul 19 06:29:44 PM PDT 24
Peak memory 219068 kb
Host smart-55ee1245-199d-41d1-b993-67b196d5c41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676643713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.3676643713
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.453323223
Short name T913
Test name
Test status
Simulation time 27196176 ps
CPU time 1.22 seconds
Started Jul 19 06:29:35 PM PDT 24
Finished Jul 19 06:29:42 PM PDT 24
Peak memory 218980 kb
Host smart-06aad8a5-376a-4618-a41e-b95d094b4ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453323223 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.453323223
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.1186461136
Short name T827
Test name
Test status
Simulation time 76388453 ps
CPU time 1.24 seconds
Started Jul 19 06:29:36 PM PDT 24
Finished Jul 19 06:29:44 PM PDT 24
Peak memory 218836 kb
Host smart-e368de44-5d5c-45e7-80af-8842c0460f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186461136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.1186461136
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.3640918836
Short name T693
Test name
Test status
Simulation time 25409718 ps
CPU time 1.1 seconds
Started Jul 19 06:29:31 PM PDT 24
Finished Jul 19 06:29:39 PM PDT 24
Peak memory 219992 kb
Host smart-dde7cd41-3b88-4c1f-8264-945b7bc1163c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640918836 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.3640918836
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.470770857
Short name T668
Test name
Test status
Simulation time 98656121 ps
CPU time 1.24 seconds
Started Jul 19 06:29:33 PM PDT 24
Finished Jul 19 06:29:41 PM PDT 24
Peak memory 217484 kb
Host smart-80eabe88-d4de-4360-a360-a3d15eb6ab2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470770857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.470770857
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.3956248626
Short name T390
Test name
Test status
Simulation time 45154303 ps
CPU time 1.14 seconds
Started Jul 19 06:29:36 PM PDT 24
Finished Jul 19 06:29:44 PM PDT 24
Peak memory 220104 kb
Host smart-2ae1217b-6efa-4e00-ad95-43fdbeb92c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956248626 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.3956248626
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.2163867003
Short name T408
Test name
Test status
Simulation time 473569355 ps
CPU time 4.96 seconds
Started Jul 19 06:29:35 PM PDT 24
Finished Jul 19 06:29:46 PM PDT 24
Peak memory 219116 kb
Host smart-2710f444-40c5-4059-b1bc-acd7dc56e2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163867003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2163867003
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert_test.1400594713
Short name T813
Test name
Test status
Simulation time 49761530 ps
CPU time 0.8 seconds
Started Jul 19 06:27:44 PM PDT 24
Finished Jul 19 06:27:46 PM PDT 24
Peak memory 206668 kb
Host smart-028af470-8f80-4a15-b72e-d691e118189a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400594713 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.1400594713
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.500824827
Short name T967
Test name
Test status
Simulation time 334707932 ps
CPU time 1.27 seconds
Started Jul 19 06:27:47 PM PDT 24
Finished Jul 19 06:27:50 PM PDT 24
Peak memory 217016 kb
Host smart-1b4707a1-d005-439d-bf35-ccb196486d7b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500824827 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_di
sable_auto_req_mode.500824827
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_genbits.3117064685
Short name T357
Test name
Test status
Simulation time 35023290 ps
CPU time 1.3 seconds
Started Jul 19 06:27:44 PM PDT 24
Finished Jul 19 06:27:46 PM PDT 24
Peak memory 218804 kb
Host smart-9970d0e1-e7a8-4672-b5cf-b28be7dd1361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117064685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.3117064685
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.1141728325
Short name T635
Test name
Test status
Simulation time 22042576 ps
CPU time 1.22 seconds
Started Jul 19 06:27:47 PM PDT 24
Finished Jul 19 06:27:50 PM PDT 24
Peak memory 224312 kb
Host smart-a7b73e29-92b4-4130-8285-95f7b9e79fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141728325 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.1141728325
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.1063349119
Short name T933
Test name
Test status
Simulation time 62232474 ps
CPU time 0.91 seconds
Started Jul 19 06:27:44 PM PDT 24
Finished Jul 19 06:27:46 PM PDT 24
Peak memory 215556 kb
Host smart-c1188daf-5eaf-4846-a595-c5c1f1a58381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063349119 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.1063349119
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.605210879
Short name T360
Test name
Test status
Simulation time 307146572 ps
CPU time 3.35 seconds
Started Jul 19 06:27:45 PM PDT 24
Finished Jul 19 06:27:50 PM PDT 24
Peak memory 217452 kb
Host smart-d0628fa2-3df1-4385-844e-1f54041f9df9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605210879 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.605210879
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2272134707
Short name T242
Test name
Test status
Simulation time 312164756799 ps
CPU time 1893.74 seconds
Started Jul 19 06:27:45 PM PDT 24
Finished Jul 19 06:59:20 PM PDT 24
Peak memory 225424 kb
Host smart-b00c22fe-df6e-4d59-a9f6-22bf6f0e1df3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272134707 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.2272134707
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.2447308128
Short name T413
Test name
Test status
Simulation time 57141857 ps
CPU time 1.32 seconds
Started Jul 19 06:29:32 PM PDT 24
Finished Jul 19 06:29:41 PM PDT 24
Peak memory 221208 kb
Host smart-c5491034-e836-4fb8-8186-bde1e5811c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447308128 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.2447308128
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.2561660454
Short name T861
Test name
Test status
Simulation time 159174063 ps
CPU time 1.29 seconds
Started Jul 19 06:29:34 PM PDT 24
Finished Jul 19 06:29:42 PM PDT 24
Peak memory 217720 kb
Host smart-b3b52d82-0242-49ef-b2f6-fd277b059848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561660454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2561660454
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.1583958948
Short name T940
Test name
Test status
Simulation time 78980663 ps
CPU time 1.13 seconds
Started Jul 19 06:29:33 PM PDT 24
Finished Jul 19 06:29:41 PM PDT 24
Peak memory 219008 kb
Host smart-22ae4127-635e-4351-ac96-7734f0e40100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583958948 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.1583958948
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.2539506816
Short name T37
Test name
Test status
Simulation time 123330785 ps
CPU time 1.06 seconds
Started Jul 19 06:29:32 PM PDT 24
Finished Jul 19 06:29:40 PM PDT 24
Peak memory 217532 kb
Host smart-fe4e1e54-b134-407f-aa02-fe5daaaf18e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539506816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2539506816
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.1543437812
Short name T900
Test name
Test status
Simulation time 95362849 ps
CPU time 1.28 seconds
Started Jul 19 06:29:37 PM PDT 24
Finished Jul 19 06:29:45 PM PDT 24
Peak memory 220492 kb
Host smart-6752a713-67c6-4ead-9881-785d161ec1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543437812 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.1543437812
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.4083578813
Short name T493
Test name
Test status
Simulation time 49412243 ps
CPU time 1.36 seconds
Started Jul 19 06:29:34 PM PDT 24
Finished Jul 19 06:29:43 PM PDT 24
Peak memory 217720 kb
Host smart-8a6e2c9f-9235-43cc-9dae-9219f9ac7066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083578813 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.4083578813
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.3006261117
Short name T443
Test name
Test status
Simulation time 33983967 ps
CPU time 1.44 seconds
Started Jul 19 06:29:33 PM PDT 24
Finished Jul 19 06:29:41 PM PDT 24
Peak memory 216016 kb
Host smart-c06a47ae-7e31-4a7e-9a8a-ded904244191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006261117 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.3006261117
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.2736095301
Short name T878
Test name
Test status
Simulation time 181034915 ps
CPU time 1.25 seconds
Started Jul 19 06:29:33 PM PDT 24
Finished Jul 19 06:29:41 PM PDT 24
Peak memory 220032 kb
Host smart-710d5bdf-dac4-4c9a-b2c2-44f3770729c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736095301 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.2736095301
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.157199805
Short name T177
Test name
Test status
Simulation time 99826583 ps
CPU time 1.38 seconds
Started Jul 19 06:29:33 PM PDT 24
Finished Jul 19 06:29:42 PM PDT 24
Peak memory 215980 kb
Host smart-cffda801-46d0-43b0-a794-3e3e8d99af2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157199805 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.157199805
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.2290897290
Short name T985
Test name
Test status
Simulation time 54821115 ps
CPU time 1.41 seconds
Started Jul 19 06:29:33 PM PDT 24
Finished Jul 19 06:29:41 PM PDT 24
Peak memory 219044 kb
Host smart-9fd2eb9d-ff51-42e8-ba94-02ffae3715f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290897290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2290897290
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.340568675
Short name T304
Test name
Test status
Simulation time 129516086 ps
CPU time 1.17 seconds
Started Jul 19 06:29:37 PM PDT 24
Finished Jul 19 06:29:45 PM PDT 24
Peak memory 219168 kb
Host smart-c8440d48-47c7-4ce7-9e46-ff071bfc1d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340568675 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.340568675
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.2252060062
Short name T890
Test name
Test status
Simulation time 41889943 ps
CPU time 1.52 seconds
Started Jul 19 06:29:35 PM PDT 24
Finished Jul 19 06:29:43 PM PDT 24
Peak memory 218560 kb
Host smart-ade738c4-6772-441e-a162-e2ff5d29c9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252060062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.2252060062
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.2601035834
Short name T689
Test name
Test status
Simulation time 89410968 ps
CPU time 1.16 seconds
Started Jul 19 06:29:33 PM PDT 24
Finished Jul 19 06:29:41 PM PDT 24
Peak memory 219792 kb
Host smart-e5fd0f2b-d28d-4b23-9081-3173f0ce7ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601035834 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.2601035834
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.3764498984
Short name T644
Test name
Test status
Simulation time 57154059 ps
CPU time 1.33 seconds
Started Jul 19 06:29:32 PM PDT 24
Finished Jul 19 06:29:40 PM PDT 24
Peak memory 218796 kb
Host smart-0941b126-17f5-49bb-ac6f-7615947ee3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764498984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.3764498984
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.3681250764
Short name T88
Test name
Test status
Simulation time 132316714 ps
CPU time 1.18 seconds
Started Jul 19 06:29:33 PM PDT 24
Finished Jul 19 06:29:42 PM PDT 24
Peak memory 217488 kb
Host smart-119c7645-6837-42d9-849e-a4859102c046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681250764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.3681250764
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.3041872439
Short name T623
Test name
Test status
Simulation time 70204637 ps
CPU time 1.3 seconds
Started Jul 19 06:29:34 PM PDT 24
Finished Jul 19 06:29:42 PM PDT 24
Peak memory 220852 kb
Host smart-217be512-516a-4ac5-bce6-8365a9c8cf46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041872439 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.3041872439
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.1823895800
Short name T809
Test name
Test status
Simulation time 375243344 ps
CPU time 1.3 seconds
Started Jul 19 06:29:35 PM PDT 24
Finished Jul 19 06:29:43 PM PDT 24
Peak memory 217636 kb
Host smart-a3a77933-41aa-4af9-bcce-939e65f89dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823895800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1823895800
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.205267595
Short name T448
Test name
Test status
Simulation time 24874545 ps
CPU time 1.23 seconds
Started Jul 19 06:29:34 PM PDT 24
Finished Jul 19 06:29:42 PM PDT 24
Peak memory 219856 kb
Host smart-024045cd-7b40-4809-894d-1057628a1368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205267595 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.205267595
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert.3506824092
Short name T819
Test name
Test status
Simulation time 28511601 ps
CPU time 1.34 seconds
Started Jul 19 06:27:45 PM PDT 24
Finished Jul 19 06:27:48 PM PDT 24
Peak memory 220644 kb
Host smart-6f611528-6c67-4e37-aa90-2629f270f573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506824092 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3506824092
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.1914301437
Short name T71
Test name
Test status
Simulation time 73247704 ps
CPU time 0.81 seconds
Started Jul 19 06:27:45 PM PDT 24
Finished Jul 19 06:27:47 PM PDT 24
Peak memory 206664 kb
Host smart-f3c5c8dd-b1b8-4e73-9738-baccd16cd96b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914301437 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1914301437
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.2791895785
Short name T215
Test name
Test status
Simulation time 44410027 ps
CPU time 0.8 seconds
Started Jul 19 06:27:47 PM PDT 24
Finished Jul 19 06:27:49 PM PDT 24
Peak memory 216480 kb
Host smart-5b593d3c-8e7a-413e-b9c1-950e3c687e1a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791895785 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.2791895785
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.1380491144
Short name T764
Test name
Test status
Simulation time 26409261 ps
CPU time 1.04 seconds
Started Jul 19 06:27:45 PM PDT 24
Finished Jul 19 06:27:47 PM PDT 24
Peak memory 217024 kb
Host smart-93e5bdc9-dfb1-46f5-ba1e-d8486b92f71d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380491144 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.1380491144
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.649176258
Short name T54
Test name
Test status
Simulation time 26243162 ps
CPU time 0.95 seconds
Started Jul 19 06:27:48 PM PDT 24
Finished Jul 19 06:27:50 PM PDT 24
Peak memory 224040 kb
Host smart-89c70f6f-51be-4124-91ed-c32b6970ab38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649176258 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.649176258
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.186475265
Short name T867
Test name
Test status
Simulation time 147358567 ps
CPU time 1.3 seconds
Started Jul 19 06:27:46 PM PDT 24
Finished Jul 19 06:27:49 PM PDT 24
Peak memory 217616 kb
Host smart-1e2116bf-468b-4390-89ca-f2c979af0293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186475265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.186475265
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.1687757212
Short name T935
Test name
Test status
Simulation time 27969688 ps
CPU time 1.08 seconds
Started Jul 19 06:27:46 PM PDT 24
Finished Jul 19 06:27:49 PM PDT 24
Peak memory 224344 kb
Host smart-bc4c739a-26c6-4dd5-ac87-856a9f923ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687757212 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.1687757212
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.1719657272
Short name T950
Test name
Test status
Simulation time 21327750 ps
CPU time 0.99 seconds
Started Jul 19 06:27:44 PM PDT 24
Finished Jul 19 06:27:46 PM PDT 24
Peak memory 215512 kb
Host smart-d07efa76-a208-4161-89ae-2f74973495db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719657272 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.1719657272
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.3454096046
Short name T953
Test name
Test status
Simulation time 840468833 ps
CPU time 4.44 seconds
Started Jul 19 06:27:44 PM PDT 24
Finished Jul 19 06:27:49 PM PDT 24
Peak memory 217468 kb
Host smart-5e7b9102-9284-40ba-83cd-575fa10032f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454096046 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3454096046
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.1095741821
Short name T977
Test name
Test status
Simulation time 128196598901 ps
CPU time 1510.58 seconds
Started Jul 19 06:27:46 PM PDT 24
Finished Jul 19 06:52:58 PM PDT 24
Peak memory 224436 kb
Host smart-419a75e5-622e-4d9c-9e65-e508e3d5e2ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095741821 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.1095741821
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.2059619811
Short name T286
Test name
Test status
Simulation time 94479757 ps
CPU time 1.27 seconds
Started Jul 19 06:29:34 PM PDT 24
Finished Jul 19 06:29:42 PM PDT 24
Peak memory 220220 kb
Host smart-02295633-7332-4866-b1bb-17bc4ec5904b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059619811 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.2059619811
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.3296046857
Short name T725
Test name
Test status
Simulation time 32992133 ps
CPU time 1.28 seconds
Started Jul 19 06:29:33 PM PDT 24
Finished Jul 19 06:29:41 PM PDT 24
Peak memory 217596 kb
Host smart-ed495b55-469e-45e6-af98-5015e4e8aabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296046857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.3296046857
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.1082029929
Short name T889
Test name
Test status
Simulation time 88182698 ps
CPU time 1.22 seconds
Started Jul 19 06:29:35 PM PDT 24
Finished Jul 19 06:29:43 PM PDT 24
Peak memory 219736 kb
Host smart-af6bbfc6-7677-4973-95ea-aef48f304f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082029929 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.1082029929
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.335740778
Short name T396
Test name
Test status
Simulation time 140295848 ps
CPU time 1.09 seconds
Started Jul 19 06:29:33 PM PDT 24
Finished Jul 19 06:29:41 PM PDT 24
Peak memory 217588 kb
Host smart-e0f8b907-a211-4c03-909b-d798579f13a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335740778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.335740778
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.2883065457
Short name T417
Test name
Test status
Simulation time 38742012 ps
CPU time 1.14 seconds
Started Jul 19 06:29:32 PM PDT 24
Finished Jul 19 06:29:40 PM PDT 24
Peak memory 220200 kb
Host smart-a5e4d204-5015-4e4d-adab-6789d03ff7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883065457 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.2883065457
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.2764916391
Short name T695
Test name
Test status
Simulation time 97326973 ps
CPU time 1.42 seconds
Started Jul 19 06:29:33 PM PDT 24
Finished Jul 19 06:29:41 PM PDT 24
Peak memory 219100 kb
Host smart-296729ec-8cc4-46bd-bb87-577013faa16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764916391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.2764916391
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.83531635
Short name T677
Test name
Test status
Simulation time 200693132 ps
CPU time 2.6 seconds
Started Jul 19 06:29:33 PM PDT 24
Finished Jul 19 06:29:42 PM PDT 24
Peak memory 220056 kb
Host smart-46b9b187-e0a2-471d-9f32-70e6993ad97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83531635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.83531635
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.628944015
Short name T618
Test name
Test status
Simulation time 59991501 ps
CPU time 1.23 seconds
Started Jul 19 06:29:34 PM PDT 24
Finished Jul 19 06:29:42 PM PDT 24
Peak memory 218752 kb
Host smart-ee0545c8-df6a-4d24-a82c-9a192dd106eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628944015 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.628944015
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.3282127252
Short name T345
Test name
Test status
Simulation time 105132822 ps
CPU time 2.39 seconds
Started Jul 19 06:29:33 PM PDT 24
Finished Jul 19 06:29:42 PM PDT 24
Peak memory 220552 kb
Host smart-c9650ea0-75b4-44f8-984d-c104770f20f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282127252 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.3282127252
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.857273986
Short name T313
Test name
Test status
Simulation time 81526922 ps
CPU time 1.13 seconds
Started Jul 19 06:29:46 PM PDT 24
Finished Jul 19 06:29:52 PM PDT 24
Peak memory 218888 kb
Host smart-6fc73374-5f25-4bc7-b62f-bdc923553362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857273986 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.857273986
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.3194160067
Short name T497
Test name
Test status
Simulation time 87968176 ps
CPU time 1.3 seconds
Started Jul 19 06:29:40 PM PDT 24
Finished Jul 19 06:29:48 PM PDT 24
Peak memory 217568 kb
Host smart-b76daf2b-0c36-4fb4-be13-57c73a2bf2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194160067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.3194160067
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.2496804107
Short name T954
Test name
Test status
Simulation time 181753664 ps
CPU time 1.18 seconds
Started Jul 19 06:29:44 PM PDT 24
Finished Jul 19 06:29:51 PM PDT 24
Peak memory 219832 kb
Host smart-44ed5718-fb51-4cfc-a6e4-a0de0417cb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496804107 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.2496804107
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.1637460034
Short name T572
Test name
Test status
Simulation time 345783123 ps
CPU time 1.1 seconds
Started Jul 19 06:29:46 PM PDT 24
Finished Jul 19 06:29:52 PM PDT 24
Peak memory 217600 kb
Host smart-8595c283-6dad-4e06-9ea4-d7a995255bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637460034 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1637460034
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.4183362637
Short name T521
Test name
Test status
Simulation time 39839770 ps
CPU time 1.25 seconds
Started Jul 19 06:29:40 PM PDT 24
Finished Jul 19 06:29:48 PM PDT 24
Peak memory 219420 kb
Host smart-b881abd2-3d1d-447e-b5a4-80791b257992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183362637 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.4183362637
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.3845441985
Short name T397
Test name
Test status
Simulation time 78188014 ps
CPU time 1.07 seconds
Started Jul 19 06:29:45 PM PDT 24
Finished Jul 19 06:29:51 PM PDT 24
Peak memory 217500 kb
Host smart-dbdb7634-1155-43eb-a8c2-811f575abcd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845441985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.3845441985
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.1341512192
Short name T307
Test name
Test status
Simulation time 24208694 ps
CPU time 1.17 seconds
Started Jul 19 06:29:46 PM PDT 24
Finished Jul 19 06:29:52 PM PDT 24
Peak memory 219000 kb
Host smart-81916a73-2edb-4bf5-9848-9fa134f59404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341512192 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.1341512192
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.315628249
Short name T963
Test name
Test status
Simulation time 46997985 ps
CPU time 1.32 seconds
Started Jul 19 06:29:43 PM PDT 24
Finished Jul 19 06:29:50 PM PDT 24
Peak memory 218760 kb
Host smart-ad8897a6-e929-420e-bc3d-ca0b9a663895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315628249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.315628249
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.2789119429
Short name T818
Test name
Test status
Simulation time 69087139 ps
CPU time 1.05 seconds
Started Jul 19 06:27:46 PM PDT 24
Finished Jul 19 06:27:49 PM PDT 24
Peak memory 219868 kb
Host smart-d3a55666-0753-4011-96ac-42511bf4b08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789119429 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.2789119429
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.479655027
Short name T498
Test name
Test status
Simulation time 23563322 ps
CPU time 1.05 seconds
Started Jul 19 06:27:53 PM PDT 24
Finished Jul 19 06:27:57 PM PDT 24
Peak memory 215216 kb
Host smart-6f756971-5c04-4291-b054-c2a6ff3908e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479655027 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.479655027
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.2823309487
Short name T931
Test name
Test status
Simulation time 38403503 ps
CPU time 1.31 seconds
Started Jul 19 06:27:45 PM PDT 24
Finished Jul 19 06:27:48 PM PDT 24
Peak memory 217280 kb
Host smart-ee2c8228-2b3c-4321-9338-e26bad4f4c28
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823309487 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.2823309487
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.4215442269
Short name T161
Test name
Test status
Simulation time 41174262 ps
CPU time 0.91 seconds
Started Jul 19 06:27:45 PM PDT 24
Finished Jul 19 06:27:48 PM PDT 24
Peak memory 220016 kb
Host smart-21a0b1e2-baff-4801-80b3-a92d8e27160e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215442269 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.4215442269
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.3148740977
Short name T45
Test name
Test status
Simulation time 34906149 ps
CPU time 1.3 seconds
Started Jul 19 06:27:44 PM PDT 24
Finished Jul 19 06:27:46 PM PDT 24
Peak memory 218688 kb
Host smart-752c60ae-eb88-4171-8c6e-5cbd8682f890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148740977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.3148740977
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.2802513922
Short name T844
Test name
Test status
Simulation time 24294760 ps
CPU time 1.06 seconds
Started Jul 19 06:27:45 PM PDT 24
Finished Jul 19 06:27:47 PM PDT 24
Peak memory 224408 kb
Host smart-ec402341-3dfc-4d08-89a7-a4f8b0a7e70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802513922 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2802513922
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.582015312
Short name T449
Test name
Test status
Simulation time 26942621 ps
CPU time 0.96 seconds
Started Jul 19 06:27:44 PM PDT 24
Finished Jul 19 06:27:45 PM PDT 24
Peak memory 215548 kb
Host smart-6dc4da35-cc67-44a8-baf9-3ababe827632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582015312 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.582015312
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.1695361861
Short name T74
Test name
Test status
Simulation time 1179120984 ps
CPU time 6.48 seconds
Started Jul 19 06:27:44 PM PDT 24
Finished Jul 19 06:27:52 PM PDT 24
Peak memory 217552 kb
Host smart-358548ca-5dc5-4f95-8bf8-e4f4b668787a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695361861 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1695361861
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.3803432154
Short name T833
Test name
Test status
Simulation time 22666491250 ps
CPU time 592.71 seconds
Started Jul 19 06:27:48 PM PDT 24
Finished Jul 19 06:37:42 PM PDT 24
Peak memory 222044 kb
Host smart-97cecab9-7979-4fd1-8f30-ebc1c02e9dc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803432154 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.3803432154
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.2486549973
Short name T949
Test name
Test status
Simulation time 236008247 ps
CPU time 1.37 seconds
Started Jul 19 06:29:41 PM PDT 24
Finished Jul 19 06:29:49 PM PDT 24
Peak memory 219976 kb
Host smart-34e65138-733c-415e-a235-324a6d3ce1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486549973 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.2486549973
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.2712255378
Short name T943
Test name
Test status
Simulation time 79562401 ps
CPU time 1.16 seconds
Started Jul 19 06:29:46 PM PDT 24
Finished Jul 19 06:29:52 PM PDT 24
Peak memory 217508 kb
Host smart-4a6ad477-65e7-4025-9e84-9fa4d76d8696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712255378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.2712255378
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.2444643180
Short name T657
Test name
Test status
Simulation time 31434210 ps
CPU time 1.34 seconds
Started Jul 19 06:29:41 PM PDT 24
Finished Jul 19 06:29:49 PM PDT 24
Peak memory 215972 kb
Host smart-e7686d03-242a-45d2-9beb-2920068ab68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444643180 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.2444643180
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.650593975
Short name T755
Test name
Test status
Simulation time 36382169 ps
CPU time 1.5 seconds
Started Jul 19 06:29:40 PM PDT 24
Finished Jul 19 06:29:49 PM PDT 24
Peak memory 218928 kb
Host smart-9eb99986-0e0e-4ec6-960e-efb8dbddf459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650593975 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.650593975
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.2272920571
Short name T139
Test name
Test status
Simulation time 31141938 ps
CPU time 1.35 seconds
Started Jul 19 06:29:41 PM PDT 24
Finished Jul 19 06:29:49 PM PDT 24
Peak memory 219428 kb
Host smart-c4f4979f-610e-4c6f-9242-c9b15dd277b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272920571 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.2272920571
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.2148704873
Short name T348
Test name
Test status
Simulation time 91603295 ps
CPU time 1.05 seconds
Started Jul 19 06:29:40 PM PDT 24
Finished Jul 19 06:29:48 PM PDT 24
Peak memory 217508 kb
Host smart-0913f7fc-1c19-4416-930b-9d5f4866a3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148704873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.2148704873
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.1388382017
Short name T203
Test name
Test status
Simulation time 38780913 ps
CPU time 1.14 seconds
Started Jul 19 06:29:42 PM PDT 24
Finished Jul 19 06:29:49 PM PDT 24
Peak memory 219364 kb
Host smart-01d27eaf-cbae-4e8f-8a7c-0d4221a9ea4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388382017 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.1388382017
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/154.edn_alert.3148572634
Short name T545
Test name
Test status
Simulation time 48407908 ps
CPU time 1.26 seconds
Started Jul 19 06:29:45 PM PDT 24
Finished Jul 19 06:29:52 PM PDT 24
Peak memory 220264 kb
Host smart-7d740ed0-4867-4551-80b1-b310a88d5fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148572634 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.3148572634
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.2529959242
Short name T604
Test name
Test status
Simulation time 178149758 ps
CPU time 1.48 seconds
Started Jul 19 06:29:42 PM PDT 24
Finished Jul 19 06:29:50 PM PDT 24
Peak memory 219204 kb
Host smart-0187ef31-5df0-4daf-8ce1-5edb44efc40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529959242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.2529959242
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.1578480349
Short name T775
Test name
Test status
Simulation time 31046899 ps
CPU time 1.34 seconds
Started Jul 19 06:29:39 PM PDT 24
Finished Jul 19 06:29:47 PM PDT 24
Peak memory 220076 kb
Host smart-15bab1c6-09ba-48d1-a1e0-008a443e305b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578480349 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.1578480349
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.2609882387
Short name T506
Test name
Test status
Simulation time 72164116 ps
CPU time 1.31 seconds
Started Jul 19 06:29:41 PM PDT 24
Finished Jul 19 06:29:49 PM PDT 24
Peak memory 218936 kb
Host smart-8de8745f-21ce-4ff8-8513-a909d067212b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609882387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2609882387
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.2568181754
Short name T975
Test name
Test status
Simulation time 21119288 ps
CPU time 1.06 seconds
Started Jul 19 06:29:46 PM PDT 24
Finished Jul 19 06:29:52 PM PDT 24
Peak memory 218724 kb
Host smart-bb081717-40b7-443f-aad1-37f3c91ea142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568181754 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.2568181754
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/157.edn_alert.1532253824
Short name T236
Test name
Test status
Simulation time 173148135 ps
CPU time 1.25 seconds
Started Jul 19 06:29:39 PM PDT 24
Finished Jul 19 06:29:47 PM PDT 24
Peak memory 218896 kb
Host smart-c4d383d7-c726-4b22-a680-fae832ad22d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532253824 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.1532253824
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.2189110432
Short name T710
Test name
Test status
Simulation time 93898980 ps
CPU time 1.66 seconds
Started Jul 19 06:29:40 PM PDT 24
Finished Jul 19 06:29:49 PM PDT 24
Peak memory 219184 kb
Host smart-e2c36177-6694-427b-aee2-0f28f3fe8b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189110432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.2189110432
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.3423149289
Short name T857
Test name
Test status
Simulation time 76788858 ps
CPU time 1.07 seconds
Started Jul 19 06:29:40 PM PDT 24
Finished Jul 19 06:29:47 PM PDT 24
Peak memory 218708 kb
Host smart-5f8ef1b6-d7ce-407d-8078-ac67d020b1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423149289 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.3423149289
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.3419369244
Short name T733
Test name
Test status
Simulation time 59922754 ps
CPU time 1.19 seconds
Started Jul 19 06:29:41 PM PDT 24
Finished Jul 19 06:29:49 PM PDT 24
Peak memory 218592 kb
Host smart-6187ae60-ea28-409f-8fc9-789ee15ab97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419369244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.3419369244
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.1737453358
Short name T711
Test name
Test status
Simulation time 25848895 ps
CPU time 1.27 seconds
Started Jul 19 06:29:40 PM PDT 24
Finished Jul 19 06:29:47 PM PDT 24
Peak memory 220136 kb
Host smart-7dba3ebf-6ed9-48ac-b897-1219f0717789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737453358 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.1737453358
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.2518743850
Short name T625
Test name
Test status
Simulation time 65537591 ps
CPU time 1.29 seconds
Started Jul 19 06:29:44 PM PDT 24
Finished Jul 19 06:29:51 PM PDT 24
Peak memory 218560 kb
Host smart-3ba38115-8628-4763-b974-c7158e1117c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518743850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.2518743850
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.2855911873
Short name T257
Test name
Test status
Simulation time 57052720 ps
CPU time 1.28 seconds
Started Jul 19 06:27:51 PM PDT 24
Finished Jul 19 06:27:52 PM PDT 24
Peak memory 220684 kb
Host smart-8bbdc5d8-905e-4670-9f29-e3748b555116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855911873 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.2855911873
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.2861320360
Short name T731
Test name
Test status
Simulation time 33371606 ps
CPU time 0.92 seconds
Started Jul 19 06:27:52 PM PDT 24
Finished Jul 19 06:27:55 PM PDT 24
Peak memory 207072 kb
Host smart-1dd243e6-e0c2-4385-8c12-130efb134ddf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861320360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.2861320360
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.2090736150
Short name T200
Test name
Test status
Simulation time 14033552 ps
CPU time 0.92 seconds
Started Jul 19 06:27:52 PM PDT 24
Finished Jul 19 06:27:53 PM PDT 24
Peak memory 216644 kb
Host smart-300595cb-f99e-4249-90fd-17d963d04161
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090736150 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2090736150
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.1888063219
Short name T136
Test name
Test status
Simulation time 25938802 ps
CPU time 1.1 seconds
Started Jul 19 06:27:53 PM PDT 24
Finished Jul 19 06:27:57 PM PDT 24
Peak memory 217232 kb
Host smart-0f9c7bfc-c589-4f13-880e-13a2ee89abad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888063219 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.1888063219
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.1258867700
Short name T947
Test name
Test status
Simulation time 45937947 ps
CPU time 1.03 seconds
Started Jul 19 06:27:51 PM PDT 24
Finished Jul 19 06:27:53 PM PDT 24
Peak memory 220100 kb
Host smart-2235a260-bdfb-46e2-a651-7162b971f80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258867700 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1258867700
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.214006078
Short name T450
Test name
Test status
Simulation time 22567311 ps
CPU time 1.05 seconds
Started Jul 19 06:27:54 PM PDT 24
Finished Jul 19 06:27:57 PM PDT 24
Peak memory 217608 kb
Host smart-b4361482-63b4-4d44-80a3-04b478c53af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214006078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.214006078
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.3012859485
Short name T124
Test name
Test status
Simulation time 23168615 ps
CPU time 0.96 seconds
Started Jul 19 06:27:56 PM PDT 24
Finished Jul 19 06:27:59 PM PDT 24
Peak memory 216152 kb
Host smart-c41a8005-0fbb-447a-9dd7-451a66333bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012859485 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.3012859485
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.2904994627
Short name T404
Test name
Test status
Simulation time 24634136 ps
CPU time 1.01 seconds
Started Jul 19 06:27:53 PM PDT 24
Finished Jul 19 06:27:57 PM PDT 24
Peak memory 215580 kb
Host smart-baaa2dbc-1c82-4fb2-920b-25cf591ad43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904994627 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.2904994627
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.1995454337
Short name T424
Test name
Test status
Simulation time 847293116 ps
CPU time 3.96 seconds
Started Jul 19 06:27:52 PM PDT 24
Finished Jul 19 06:27:59 PM PDT 24
Peak memory 217460 kb
Host smart-cb8fd654-8c43-4892-a0f5-41eede5f6082
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995454337 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.1995454337
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.1762534490
Short name T241
Test name
Test status
Simulation time 368970478149 ps
CPU time 2359.61 seconds
Started Jul 19 06:27:52 PM PDT 24
Finished Jul 19 07:07:14 PM PDT 24
Peak memory 227132 kb
Host smart-98ad8445-1262-4db7-bd05-a14fc4b8779f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762534490 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.1762534490
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.3420283622
Short name T159
Test name
Test status
Simulation time 34740390 ps
CPU time 1.14 seconds
Started Jul 19 06:29:49 PM PDT 24
Finished Jul 19 06:29:54 PM PDT 24
Peak memory 219780 kb
Host smart-bdee1935-9b07-472b-9fed-31c0ff2f6190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420283622 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.3420283622
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.3978108897
Short name T778
Test name
Test status
Simulation time 50863904 ps
CPU time 1.28 seconds
Started Jul 19 06:29:40 PM PDT 24
Finished Jul 19 06:29:48 PM PDT 24
Peak memory 220048 kb
Host smart-0f793c36-7d28-4615-9e7e-97bf48f41a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978108897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.3978108897
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.596367181
Short name T303
Test name
Test status
Simulation time 107529970 ps
CPU time 1.17 seconds
Started Jul 19 06:29:50 PM PDT 24
Finished Jul 19 06:29:55 PM PDT 24
Peak memory 221716 kb
Host smart-3c88e083-f0a5-47c2-a2c1-931612a62dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596367181 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.596367181
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/162.edn_alert.3932272297
Short name T697
Test name
Test status
Simulation time 25724955 ps
CPU time 1.23 seconds
Started Jul 19 06:29:49 PM PDT 24
Finished Jul 19 06:29:54 PM PDT 24
Peak memory 218944 kb
Host smart-19f4dfeb-9738-427e-9099-879dd896e976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932272297 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.3932272297
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.152107180
Short name T296
Test name
Test status
Simulation time 55870337 ps
CPU time 1.06 seconds
Started Jul 19 06:29:51 PM PDT 24
Finished Jul 19 06:29:57 PM PDT 24
Peak memory 217636 kb
Host smart-b04edf98-7a8e-4bb6-b43a-fd0b75166ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152107180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.152107180
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.1765915907
Short name T500
Test name
Test status
Simulation time 278605276 ps
CPU time 1.23 seconds
Started Jul 19 06:29:49 PM PDT 24
Finished Jul 19 06:29:54 PM PDT 24
Peak memory 220184 kb
Host smart-d8361888-62e3-4387-a47d-96256b9a3502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765915907 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.1765915907
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.1984121053
Short name T339
Test name
Test status
Simulation time 38882985 ps
CPU time 1.39 seconds
Started Jul 19 06:29:52 PM PDT 24
Finished Jul 19 06:29:58 PM PDT 24
Peak memory 218800 kb
Host smart-33a4ed39-bbe0-4ac8-bd6a-76a897fdbbad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984121053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.1984121053
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.2667972322
Short name T495
Test name
Test status
Simulation time 34113713 ps
CPU time 1.18 seconds
Started Jul 19 06:29:49 PM PDT 24
Finished Jul 19 06:29:55 PM PDT 24
Peak memory 220348 kb
Host smart-b72a017c-e09e-4f08-924d-a8e7d669eaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667972322 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.2667972322
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.2007710276
Short name T653
Test name
Test status
Simulation time 48817142 ps
CPU time 1.18 seconds
Started Jul 19 06:29:50 PM PDT 24
Finished Jul 19 06:29:55 PM PDT 24
Peak memory 220232 kb
Host smart-75854a80-6849-48bc-beae-6197d075f95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007710276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2007710276
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.2001923728
Short name T250
Test name
Test status
Simulation time 100156912 ps
CPU time 1.29 seconds
Started Jul 19 06:29:48 PM PDT 24
Finished Jul 19 06:29:54 PM PDT 24
Peak memory 219944 kb
Host smart-645e72b8-0b8b-4cc4-915d-7c931386b341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001923728 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.2001923728
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.987112417
Short name T349
Test name
Test status
Simulation time 34305713 ps
CPU time 1.33 seconds
Started Jul 19 06:29:49 PM PDT 24
Finished Jul 19 06:29:54 PM PDT 24
Peak memory 218972 kb
Host smart-035de6fa-d8a1-4a15-9232-856abb59f418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987112417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.987112417
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.393953912
Short name T100
Test name
Test status
Simulation time 74902093 ps
CPU time 1.11 seconds
Started Jul 19 06:29:59 PM PDT 24
Finished Jul 19 06:30:07 PM PDT 24
Peak memory 219068 kb
Host smart-31942239-f99d-4b0c-b7bc-65fa2863d457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393953912 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.393953912
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.3153095326
Short name T338
Test name
Test status
Simulation time 93720676 ps
CPU time 1.26 seconds
Started Jul 19 06:29:50 PM PDT 24
Finished Jul 19 06:29:55 PM PDT 24
Peak memory 219068 kb
Host smart-d6a737c5-f4d4-4a2a-af76-978468ca6fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153095326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.3153095326
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.1458365899
Short name T869
Test name
Test status
Simulation time 29885119 ps
CPU time 1.29 seconds
Started Jul 19 06:29:50 PM PDT 24
Finished Jul 19 06:29:56 PM PDT 24
Peak memory 218908 kb
Host smart-f8b358db-c2b4-40d4-8692-dadd3238471b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458365899 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.1458365899
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.2135345507
Short name T739
Test name
Test status
Simulation time 281793430 ps
CPU time 2.17 seconds
Started Jul 19 06:29:51 PM PDT 24
Finished Jul 19 06:29:58 PM PDT 24
Peak memory 219040 kb
Host smart-4edaa91c-78a6-46fe-a293-dc24a06cb0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135345507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.2135345507
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.960802071
Short name T314
Test name
Test status
Simulation time 30597606 ps
CPU time 1.21 seconds
Started Jul 19 06:29:48 PM PDT 24
Finished Jul 19 06:29:54 PM PDT 24
Peak memory 219908 kb
Host smart-8f10ef4f-21c8-41c5-8020-a7504c5b4cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960802071 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.960802071
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/169.edn_alert.2537889883
Short name T158
Test name
Test status
Simulation time 26049187 ps
CPU time 1.22 seconds
Started Jul 19 06:29:50 PM PDT 24
Finished Jul 19 06:29:56 PM PDT 24
Peak memory 219708 kb
Host smart-2eb1736b-9547-4775-ae2d-1a2c66ea35bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537889883 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.2537889883
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.891942094
Short name T720
Test name
Test status
Simulation time 103293627 ps
CPU time 1.62 seconds
Started Jul 19 06:29:49 PM PDT 24
Finished Jul 19 06:29:55 PM PDT 24
Peak memory 219164 kb
Host smart-99e898dc-64e0-427a-b550-d10950d55445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891942094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.891942094
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.3564911947
Short name T254
Test name
Test status
Simulation time 86702214 ps
CPU time 1.17 seconds
Started Jul 19 06:27:52 PM PDT 24
Finished Jul 19 06:27:55 PM PDT 24
Peak memory 219040 kb
Host smart-4d99070f-a57d-49b9-9892-f1aa62214355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564911947 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.3564911947
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.1445397488
Short name T407
Test name
Test status
Simulation time 16907441 ps
CPU time 0.99 seconds
Started Jul 19 06:27:51 PM PDT 24
Finished Jul 19 06:27:53 PM PDT 24
Peak memory 215216 kb
Host smart-9eb125af-ce59-4764-a0ae-1bd4166caaba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445397488 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.1445397488
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.2768936736
Short name T896
Test name
Test status
Simulation time 32135612 ps
CPU time 0.88 seconds
Started Jul 19 06:27:52 PM PDT 24
Finished Jul 19 06:27:54 PM PDT 24
Peak memory 215652 kb
Host smart-3d6e8444-997c-4f3e-8f1f-e690179ecaa7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768936736 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.2768936736
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_genbits.2072752341
Short name T962
Test name
Test status
Simulation time 45283626 ps
CPU time 1.18 seconds
Started Jul 19 06:27:52 PM PDT 24
Finished Jul 19 06:27:55 PM PDT 24
Peak memory 217656 kb
Host smart-cb081329-3bc6-4e12-8bac-b98806cdb621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072752341 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2072752341
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.948615562
Short name T508
Test name
Test status
Simulation time 38308468 ps
CPU time 0.93 seconds
Started Jul 19 06:27:55 PM PDT 24
Finished Jul 19 06:27:58 PM PDT 24
Peak memory 215864 kb
Host smart-01a56422-079c-4942-910f-30ca50d89c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948615562 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.948615562
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.558900397
Short name T567
Test name
Test status
Simulation time 142823378 ps
CPU time 0.93 seconds
Started Jul 19 06:27:54 PM PDT 24
Finished Jul 19 06:27:57 PM PDT 24
Peak memory 215588 kb
Host smart-2809c028-4cdb-470e-ab96-9dfc31c8e345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558900397 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.558900397
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.891861029
Short name T716
Test name
Test status
Simulation time 1043758107 ps
CPU time 3.9 seconds
Started Jul 19 06:27:55 PM PDT 24
Finished Jul 19 06:28:01 PM PDT 24
Peak memory 217308 kb
Host smart-97079639-4d16-488d-a9ca-5c59430b715f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891861029 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.891861029
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.1517108534
Short name T948
Test name
Test status
Simulation time 92169063982 ps
CPU time 644.16 seconds
Started Jul 19 06:27:52 PM PDT 24
Finished Jul 19 06:38:38 PM PDT 24
Peak memory 222076 kb
Host smart-45a1dd08-e8fd-4438-b1fb-a3b43859451a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517108534 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.1517108534
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.1159682562
Short name T761
Test name
Test status
Simulation time 251359017 ps
CPU time 1.4 seconds
Started Jul 19 06:29:51 PM PDT 24
Finished Jul 19 06:29:57 PM PDT 24
Peak memory 218884 kb
Host smart-44dcd44a-e35f-4bdd-a2a7-fc47f3ce30b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159682562 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.1159682562
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.3608490553
Short name T829
Test name
Test status
Simulation time 50142643 ps
CPU time 1.03 seconds
Started Jul 19 06:29:48 PM PDT 24
Finished Jul 19 06:29:54 PM PDT 24
Peak memory 218908 kb
Host smart-5121584a-627b-4f0a-9018-197a13bf16b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608490553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.3608490553
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.3984654917
Short name T805
Test name
Test status
Simulation time 50793519 ps
CPU time 1.19 seconds
Started Jul 19 06:29:51 PM PDT 24
Finished Jul 19 06:29:57 PM PDT 24
Peak memory 219920 kb
Host smart-31df77c5-4b18-4d74-b0d2-07a44297dfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984654917 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.3984654917
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.3766847182
Short name T707
Test name
Test status
Simulation time 71475818 ps
CPU time 1.3 seconds
Started Jul 19 06:29:47 PM PDT 24
Finished Jul 19 06:29:53 PM PDT 24
Peak memory 218976 kb
Host smart-7ffa68ae-02e0-443f-8948-6cbcad32693e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766847182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.3766847182
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.3225062135
Short name T503
Test name
Test status
Simulation time 42369695 ps
CPU time 1.64 seconds
Started Jul 19 06:29:49 PM PDT 24
Finished Jul 19 06:29:54 PM PDT 24
Peak memory 219464 kb
Host smart-4403717f-37f0-4d73-9f8f-74184b912963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225062135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.3225062135
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.1762699393
Short name T994
Test name
Test status
Simulation time 95468185 ps
CPU time 1.22 seconds
Started Jul 19 06:29:49 PM PDT 24
Finished Jul 19 06:29:54 PM PDT 24
Peak memory 219056 kb
Host smart-e4162883-eae8-4db7-9dc9-3e42716a1524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762699393 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.1762699393
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.3328794525
Short name T820
Test name
Test status
Simulation time 378443048 ps
CPU time 1.17 seconds
Started Jul 19 06:29:51 PM PDT 24
Finished Jul 19 06:29:57 PM PDT 24
Peak memory 217632 kb
Host smart-39a4d673-fc19-4efb-8ec8-27825035c7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328794525 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.3328794525
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.3240756722
Short name T876
Test name
Test status
Simulation time 39639025 ps
CPU time 1.12 seconds
Started Jul 19 06:29:48 PM PDT 24
Finished Jul 19 06:29:53 PM PDT 24
Peak memory 220100 kb
Host smart-7e628d6d-847a-4e2e-ad7f-f871a566c615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240756722 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.3240756722
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.1902440238
Short name T908
Test name
Test status
Simulation time 31348684 ps
CPU time 1.02 seconds
Started Jul 19 06:29:50 PM PDT 24
Finished Jul 19 06:29:55 PM PDT 24
Peak memory 217544 kb
Host smart-e3622ab3-fb5e-4695-8236-5924969301e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902440238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.1902440238
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.1696257501
Short name T621
Test name
Test status
Simulation time 28443832 ps
CPU time 1.23 seconds
Started Jul 19 06:29:59 PM PDT 24
Finished Jul 19 06:30:07 PM PDT 24
Peak memory 216024 kb
Host smart-73f78af2-46f4-429c-a246-3ce3b75fa8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696257501 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.1696257501
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.1677958347
Short name T434
Test name
Test status
Simulation time 63112769 ps
CPU time 1.43 seconds
Started Jul 19 06:29:51 PM PDT 24
Finished Jul 19 06:29:57 PM PDT 24
Peak memory 218596 kb
Host smart-dc4e294d-5b7b-4bd6-8537-421555836c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677958347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.1677958347
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.1948962133
Short name T728
Test name
Test status
Simulation time 37689885 ps
CPU time 1.27 seconds
Started Jul 19 06:29:49 PM PDT 24
Finished Jul 19 06:29:55 PM PDT 24
Peak memory 219864 kb
Host smart-d9ab4dec-6981-477b-9130-80e5de833ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948962133 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.1948962133
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.2837258231
Short name T892
Test name
Test status
Simulation time 54089155 ps
CPU time 1.84 seconds
Started Jul 19 06:29:52 PM PDT 24
Finished Jul 19 06:29:58 PM PDT 24
Peak memory 217724 kb
Host smart-df8febb7-2e04-4c46-8caa-7e059761fcbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837258231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2837258231
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.2250642345
Short name T989
Test name
Test status
Simulation time 66722416 ps
CPU time 1.15 seconds
Started Jul 19 06:29:53 PM PDT 24
Finished Jul 19 06:29:58 PM PDT 24
Peak memory 219032 kb
Host smart-cf380447-f185-4ba3-a16c-fda03a0013c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250642345 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.2250642345
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.3254582544
Short name T502
Test name
Test status
Simulation time 115611855 ps
CPU time 1.68 seconds
Started Jul 19 06:29:50 PM PDT 24
Finished Jul 19 06:29:57 PM PDT 24
Peak memory 219020 kb
Host smart-5283cca2-8a9d-4e41-b315-f4502a2f09e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254582544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.3254582544
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.3782667072
Short name T487
Test name
Test status
Simulation time 86599715 ps
CPU time 1.33 seconds
Started Jul 19 06:29:52 PM PDT 24
Finished Jul 19 06:29:58 PM PDT 24
Peak memory 217560 kb
Host smart-2b4571c7-b5c7-43e9-813b-2e46a7b390b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782667072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3782667072
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.3043982733
Short name T663
Test name
Test status
Simulation time 389413946 ps
CPU time 1.26 seconds
Started Jul 19 06:29:56 PM PDT 24
Finished Jul 19 06:30:01 PM PDT 24
Peak memory 219532 kb
Host smart-f04bf59b-74fc-464e-9035-89933d9c0fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043982733 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.3043982733
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.967243595
Short name T379
Test name
Test status
Simulation time 93547866 ps
CPU time 1.27 seconds
Started Jul 19 06:30:01 PM PDT 24
Finished Jul 19 06:30:11 PM PDT 24
Peak memory 217652 kb
Host smart-56721b6a-ebaa-4b78-b2b0-fb33d472572a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967243595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.967243595
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.908105445
Short name T528
Test name
Test status
Simulation time 25357205 ps
CPU time 1.24 seconds
Started Jul 19 06:27:57 PM PDT 24
Finished Jul 19 06:27:59 PM PDT 24
Peak memory 218928 kb
Host smart-3c23a623-8368-42ae-96cb-9518618b90f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908105445 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.908105445
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.806102399
Short name T870
Test name
Test status
Simulation time 55569468 ps
CPU time 0.88 seconds
Started Jul 19 06:27:54 PM PDT 24
Finished Jul 19 06:27:58 PM PDT 24
Peak memory 207036 kb
Host smart-877cd720-55d6-42c9-bbb5-414651270d90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806102399 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.806102399
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.2974241762
Short name T169
Test name
Test status
Simulation time 17839692 ps
CPU time 0.85 seconds
Started Jul 19 06:27:51 PM PDT 24
Finished Jul 19 06:27:53 PM PDT 24
Peak memory 215664 kb
Host smart-b295661c-8377-4afe-bb27-418e9fa25539
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974241762 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2974241762
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.3651379779
Short name T129
Test name
Test status
Simulation time 29808047 ps
CPU time 1.03 seconds
Started Jul 19 06:27:53 PM PDT 24
Finished Jul 19 06:27:56 PM PDT 24
Peak memory 217120 kb
Host smart-a196fbe3-3c14-4b55-9c89-45a4e1918139
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651379779 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.3651379779
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.1115915882
Short name T864
Test name
Test status
Simulation time 20323426 ps
CPU time 1.02 seconds
Started Jul 19 06:27:54 PM PDT 24
Finished Jul 19 06:27:58 PM PDT 24
Peak memory 219796 kb
Host smart-bd717dac-052f-4d9d-a127-5eb202298dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115915882 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.1115915882
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.3527556589
Short name T320
Test name
Test status
Simulation time 57577049 ps
CPU time 1.07 seconds
Started Jul 19 06:27:51 PM PDT 24
Finished Jul 19 06:27:53 PM PDT 24
Peak memory 217548 kb
Host smart-654ae193-f366-46ec-acb6-cfcbb38d8def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527556589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.3527556589
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.3056730342
Short name T646
Test name
Test status
Simulation time 25457292 ps
CPU time 1.1 seconds
Started Jul 19 06:27:55 PM PDT 24
Finished Jul 19 06:27:58 PM PDT 24
Peak memory 215864 kb
Host smart-aba7e55f-9db8-481c-bb8a-386cec485cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056730342 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.3056730342
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.865440204
Short name T919
Test name
Test status
Simulation time 46727070 ps
CPU time 0.92 seconds
Started Jul 19 06:27:52 PM PDT 24
Finished Jul 19 06:27:54 PM PDT 24
Peak memory 215560 kb
Host smart-c8d434f1-1045-4240-b0f7-99687ffebe03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865440204 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.865440204
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.4091213705
Short name T751
Test name
Test status
Simulation time 1845328621 ps
CPU time 3.36 seconds
Started Jul 19 06:27:55 PM PDT 24
Finished Jul 19 06:28:01 PM PDT 24
Peak memory 220516 kb
Host smart-38bc7afa-8614-4804-a974-546b2b040323
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091213705 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.4091213705
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.3528455950
Short name T36
Test name
Test status
Simulation time 16825279408 ps
CPU time 377.93 seconds
Started Jul 19 06:27:53 PM PDT 24
Finished Jul 19 06:34:13 PM PDT 24
Peak memory 217108 kb
Host smart-9c6dcc89-b390-4fec-8f4c-a8e29d8ece37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528455950 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.3528455950
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.4284216581
Short name T652
Test name
Test status
Simulation time 38927999 ps
CPU time 1.13 seconds
Started Jul 19 06:29:59 PM PDT 24
Finished Jul 19 06:30:07 PM PDT 24
Peak memory 220320 kb
Host smart-9b989782-9e3c-4433-90c6-72c2ee55e7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284216581 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.4284216581
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.3011141796
Short name T42
Test name
Test status
Simulation time 284137081 ps
CPU time 1.15 seconds
Started Jul 19 06:29:57 PM PDT 24
Finished Jul 19 06:30:02 PM PDT 24
Peak memory 217500 kb
Host smart-3dccdd9d-3c57-4254-ab51-529a99ab2e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011141796 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.3011141796
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.2968389533
Short name T872
Test name
Test status
Simulation time 40440855 ps
CPU time 1.16 seconds
Started Jul 19 06:30:10 PM PDT 24
Finished Jul 19 06:30:19 PM PDT 24
Peak memory 220720 kb
Host smart-b7075016-bf6f-46bc-b81b-3faeb6dcf1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968389533 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.2968389533
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.3052870033
Short name T907
Test name
Test status
Simulation time 47088254 ps
CPU time 1.74 seconds
Started Jul 19 06:29:56 PM PDT 24
Finished Jul 19 06:30:01 PM PDT 24
Peak memory 218716 kb
Host smart-bcad0329-ed36-4efb-9351-17c85782cb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052870033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3052870033
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.721913809
Short name T754
Test name
Test status
Simulation time 24779421 ps
CPU time 1.19 seconds
Started Jul 19 06:30:02 PM PDT 24
Finished Jul 19 06:30:11 PM PDT 24
Peak memory 219052 kb
Host smart-1d7b98d1-b738-4e9f-9a91-dcbe4f50bd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721913809 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.721913809
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.2486148717
Short name T97
Test name
Test status
Simulation time 138974450 ps
CPU time 2.92 seconds
Started Jul 19 06:29:57 PM PDT 24
Finished Jul 19 06:30:04 PM PDT 24
Peak memory 219604 kb
Host smart-22bca1b3-a816-4689-aeb9-2ec3f82ef983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486148717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.2486148717
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.751687076
Short name T524
Test name
Test status
Simulation time 88193789 ps
CPU time 1.07 seconds
Started Jul 19 06:29:58 PM PDT 24
Finished Jul 19 06:30:04 PM PDT 24
Peak memory 218628 kb
Host smart-333cfb9e-2496-412f-88a6-d6b2ef9bcd7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751687076 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.751687076
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.780646116
Short name T773
Test name
Test status
Simulation time 93023069 ps
CPU time 1.22 seconds
Started Jul 19 06:29:59 PM PDT 24
Finished Jul 19 06:30:06 PM PDT 24
Peak memory 219876 kb
Host smart-05ac740d-352b-4d96-a43b-29f98cd63563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780646116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.780646116
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.90258868
Short name T474
Test name
Test status
Simulation time 47309870 ps
CPU time 1.26 seconds
Started Jul 19 06:29:59 PM PDT 24
Finished Jul 19 06:30:08 PM PDT 24
Peak memory 219436 kb
Host smart-6425adba-90b3-41fb-a5ed-5fe1ee4aead2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90258868 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.90258868
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.3229411666
Short name T585
Test name
Test status
Simulation time 61697895 ps
CPU time 1.05 seconds
Started Jul 19 06:29:58 PM PDT 24
Finished Jul 19 06:30:04 PM PDT 24
Peak memory 217440 kb
Host smart-8066fd9f-b62d-48e7-bb59-a97bc90ab16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229411666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.3229411666
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.3616353620
Short name T198
Test name
Test status
Simulation time 24083672 ps
CPU time 1.19 seconds
Started Jul 19 06:29:58 PM PDT 24
Finished Jul 19 06:30:03 PM PDT 24
Peak memory 219056 kb
Host smart-fbf03cff-45fc-4c93-8e7f-1a664f41bb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616353620 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.3616353620
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.216384490
Short name T475
Test name
Test status
Simulation time 59303555 ps
CPU time 1.49 seconds
Started Jul 19 06:30:01 PM PDT 24
Finished Jul 19 06:30:11 PM PDT 24
Peak memory 217508 kb
Host smart-5cee857e-2246-48d0-bde0-d5f62a4b195d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216384490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.216384490
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.282993014
Short name T859
Test name
Test status
Simulation time 22840826 ps
CPU time 1.23 seconds
Started Jul 19 06:30:03 PM PDT 24
Finished Jul 19 06:30:11 PM PDT 24
Peak memory 216036 kb
Host smart-e94f633d-7d24-45ec-a82b-e2b0089ab7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282993014 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.282993014
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.2748794289
Short name T748
Test name
Test status
Simulation time 43964732 ps
CPU time 1.63 seconds
Started Jul 19 06:29:58 PM PDT 24
Finished Jul 19 06:30:05 PM PDT 24
Peak memory 218768 kb
Host smart-875ee12e-d17f-480c-910b-fa47c367263b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748794289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.2748794289
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.465364274
Short name T588
Test name
Test status
Simulation time 27507614 ps
CPU time 1.28 seconds
Started Jul 19 06:30:02 PM PDT 24
Finished Jul 19 06:30:11 PM PDT 24
Peak memory 216036 kb
Host smart-faa99005-42f3-4e65-af94-00f6ff791b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465364274 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.465364274
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.3553319693
Short name T44
Test name
Test status
Simulation time 42964952 ps
CPU time 1.2 seconds
Started Jul 19 06:29:58 PM PDT 24
Finished Jul 19 06:30:04 PM PDT 24
Peak memory 217484 kb
Host smart-d71cb5d2-39c6-489c-93f1-a47f836fed14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553319693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.3553319693
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.2058121352
Short name T865
Test name
Test status
Simulation time 26089905 ps
CPU time 1.14 seconds
Started Jul 19 06:30:09 PM PDT 24
Finished Jul 19 06:30:18 PM PDT 24
Peak memory 220024 kb
Host smart-9298a63c-85b9-4c04-be1f-beb8c7ac15d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058121352 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.2058121352
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.2595579500
Short name T665
Test name
Test status
Simulation time 93495488 ps
CPU time 1.2 seconds
Started Jul 19 06:30:10 PM PDT 24
Finished Jul 19 06:30:20 PM PDT 24
Peak memory 217612 kb
Host smart-1fa8ac92-dd7b-4505-9dd4-38f07406afd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595579500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.2595579500
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.2880996728
Short name T849
Test name
Test status
Simulation time 28009956 ps
CPU time 1.23 seconds
Started Jul 19 06:29:57 PM PDT 24
Finished Jul 19 06:30:02 PM PDT 24
Peak memory 218864 kb
Host smart-7419f6ec-d62f-47a1-9d13-2420087d77a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880996728 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.2880996728
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.3785355569
Short name T746
Test name
Test status
Simulation time 143146720 ps
CPU time 3.18 seconds
Started Jul 19 06:30:00 PM PDT 24
Finished Jul 19 06:30:12 PM PDT 24
Peak memory 220504 kb
Host smart-2a5bd0e5-3b62-4e27-869c-f4cc273a2050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785355569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.3785355569
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.2601872219
Short name T743
Test name
Test status
Simulation time 38400190 ps
CPU time 1.03 seconds
Started Jul 19 06:27:55 PM PDT 24
Finished Jul 19 06:27:58 PM PDT 24
Peak memory 219956 kb
Host smart-404d6ae2-f3a1-4d9a-bc14-28df2d0b87f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601872219 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.2601872219
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.150844281
Short name T505
Test name
Test status
Simulation time 76258867 ps
CPU time 0.9 seconds
Started Jul 19 06:27:56 PM PDT 24
Finished Jul 19 06:27:59 PM PDT 24
Peak memory 207056 kb
Host smart-0b4e0e16-7674-4045-8118-50e4337c3b5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150844281 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.150844281
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.2893242226
Short name T858
Test name
Test status
Simulation time 42120723 ps
CPU time 1.32 seconds
Started Jul 19 06:27:53 PM PDT 24
Finished Jul 19 06:27:57 PM PDT 24
Peak memory 217276 kb
Host smart-c149852f-45c9-4683-8cec-bbe4826a6ff7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893242226 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.2893242226
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.1405786194
Short name T208
Test name
Test status
Simulation time 26321124 ps
CPU time 0.98 seconds
Started Jul 19 06:27:56 PM PDT 24
Finished Jul 19 06:27:59 PM PDT 24
Peak memory 219032 kb
Host smart-f07e25e4-af37-4d1f-bb0b-34a4eabdd48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405786194 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.1405786194
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.1904906209
Short name T496
Test name
Test status
Simulation time 24516580 ps
CPU time 1.14 seconds
Started Jul 19 06:27:53 PM PDT 24
Finished Jul 19 06:27:57 PM PDT 24
Peak memory 217616 kb
Host smart-91cfc20f-92e6-46e5-8ce5-16ad8023bbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904906209 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.1904906209
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_smoke.4246084682
Short name T884
Test name
Test status
Simulation time 82460857 ps
CPU time 0.88 seconds
Started Jul 19 06:27:52 PM PDT 24
Finished Jul 19 06:27:55 PM PDT 24
Peak memory 215552 kb
Host smart-62896618-3457-4788-b803-5f64fbf3a557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246084682 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.4246084682
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.254190598
Short name T735
Test name
Test status
Simulation time 260217185 ps
CPU time 4.73 seconds
Started Jul 19 06:27:55 PM PDT 24
Finished Jul 19 06:28:02 PM PDT 24
Peak memory 220788 kb
Host smart-ac6c29fc-dd45-4c37-8839-2774793297a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254190598 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.254190598
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.907265905
Short name T244
Test name
Test status
Simulation time 34902327575 ps
CPU time 383.87 seconds
Started Jul 19 06:27:55 PM PDT 24
Finished Jul 19 06:34:21 PM PDT 24
Peak memory 221912 kb
Host smart-b31d3b1a-f804-48bb-baa6-ceb55d1ad4be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907265905 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.907265905
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.3969818156
Short name T591
Test name
Test status
Simulation time 59287303 ps
CPU time 1.18 seconds
Started Jul 19 06:29:59 PM PDT 24
Finished Jul 19 06:30:06 PM PDT 24
Peak memory 220312 kb
Host smart-95e3baab-71d1-404c-9287-0eda89ea71cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969818156 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.3969818156
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.362330270
Short name T749
Test name
Test status
Simulation time 30571063 ps
CPU time 1.15 seconds
Started Jul 19 06:30:09 PM PDT 24
Finished Jul 19 06:30:18 PM PDT 24
Peak memory 217520 kb
Host smart-5f0bed87-d154-46a9-8966-553904679d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362330270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.362330270
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.4245295657
Short name T713
Test name
Test status
Simulation time 114590343 ps
CPU time 1.02 seconds
Started Jul 19 06:29:59 PM PDT 24
Finished Jul 19 06:30:05 PM PDT 24
Peak memory 218944 kb
Host smart-c726af13-6f58-4f0c-a153-a4f06e4712aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245295657 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.4245295657
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.1723943098
Short name T526
Test name
Test status
Simulation time 41827292 ps
CPU time 1.38 seconds
Started Jul 19 06:29:57 PM PDT 24
Finished Jul 19 06:30:01 PM PDT 24
Peak memory 218640 kb
Host smart-75604fe9-6391-49a1-8149-ffd12d398584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723943098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.1723943098
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.2645755961
Short name T116
Test name
Test status
Simulation time 78470215 ps
CPU time 1.28 seconds
Started Jul 19 06:29:58 PM PDT 24
Finished Jul 19 06:30:03 PM PDT 24
Peak memory 220020 kb
Host smart-6854964d-f5b7-435e-803f-c8060f84b7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645755961 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.2645755961
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.376375044
Short name T297
Test name
Test status
Simulation time 68191933 ps
CPU time 1.09 seconds
Started Jul 19 06:29:58 PM PDT 24
Finished Jul 19 06:30:04 PM PDT 24
Peak memory 217376 kb
Host smart-6dfabdf1-20ec-4e47-9613-dc4688840d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376375044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.376375044
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.126773281
Short name T905
Test name
Test status
Simulation time 35592503 ps
CPU time 1.36 seconds
Started Jul 19 06:29:58 PM PDT 24
Finished Jul 19 06:30:04 PM PDT 24
Peak memory 217664 kb
Host smart-9b0d5712-dc6f-4e0b-986c-f45ceed36956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126773281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.126773281
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.2965944992
Short name T184
Test name
Test status
Simulation time 51245880 ps
CPU time 1.1 seconds
Started Jul 19 06:30:01 PM PDT 24
Finished Jul 19 06:30:11 PM PDT 24
Peak memory 218660 kb
Host smart-6bd2050f-379f-4b1e-a291-17d8430a2118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965944992 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.2965944992
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.595047698
Short name T317
Test name
Test status
Simulation time 90082031 ps
CPU time 2.01 seconds
Started Jul 19 06:29:59 PM PDT 24
Finished Jul 19 06:30:08 PM PDT 24
Peak memory 219064 kb
Host smart-f008359d-200a-43ca-a01b-6bcaf1355f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595047698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.595047698
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.3146559759
Short name T343
Test name
Test status
Simulation time 40563815 ps
CPU time 1.38 seconds
Started Jul 19 06:30:00 PM PDT 24
Finished Jul 19 06:30:10 PM PDT 24
Peak memory 218824 kb
Host smart-87ddb935-713a-4a1a-b00f-f0cd097e0a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146559759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3146559759
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.655095993
Short name T548
Test name
Test status
Simulation time 29181527 ps
CPU time 1.33 seconds
Started Jul 19 06:29:58 PM PDT 24
Finished Jul 19 06:30:04 PM PDT 24
Peak memory 216088 kb
Host smart-7425ddd1-f81e-465f-b6a4-0cabb4a2eb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655095993 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.655095993
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.3329929560
Short name T964
Test name
Test status
Simulation time 41753419 ps
CPU time 1.4 seconds
Started Jul 19 06:29:57 PM PDT 24
Finished Jul 19 06:30:02 PM PDT 24
Peak memory 218772 kb
Host smart-2f6937fa-d26a-404c-b327-3499c1b8dac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329929560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3329929560
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.2073954084
Short name T251
Test name
Test status
Simulation time 24709104 ps
CPU time 1.23 seconds
Started Jul 19 06:29:56 PM PDT 24
Finished Jul 19 06:30:01 PM PDT 24
Peak memory 219124 kb
Host smart-8e858a4d-e655-43d5-ab98-9c24ac48408b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073954084 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.2073954084
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.3866052350
Short name T709
Test name
Test status
Simulation time 73505707 ps
CPU time 1.22 seconds
Started Jul 19 06:30:02 PM PDT 24
Finished Jul 19 06:30:11 PM PDT 24
Peak memory 219084 kb
Host smart-911610ff-1ce2-4511-82b9-4a6f0cf8beb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866052350 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3866052350
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.755529512
Short name T535
Test name
Test status
Simulation time 237900692 ps
CPU time 1.26 seconds
Started Jul 19 06:29:59 PM PDT 24
Finished Jul 19 06:30:08 PM PDT 24
Peak memory 219028 kb
Host smart-c5d95291-12d7-4191-bf09-e0d71170bad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755529512 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.755529512
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.2853387412
Short name T351
Test name
Test status
Simulation time 57010695 ps
CPU time 2.1 seconds
Started Jul 19 06:30:09 PM PDT 24
Finished Jul 19 06:30:20 PM PDT 24
Peak memory 217944 kb
Host smart-ece477b0-c6b2-4b8b-89c8-0ae6eccdfe5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853387412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.2853387412
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.1455852138
Short name T744
Test name
Test status
Simulation time 27773268 ps
CPU time 1.16 seconds
Started Jul 19 06:30:09 PM PDT 24
Finished Jul 19 06:30:19 PM PDT 24
Peak memory 220016 kb
Host smart-3aa83a53-5f86-4e92-b111-eb565ae09602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455852138 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.1455852138
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert.4127078882
Short name T315
Test name
Test status
Simulation time 71775602 ps
CPU time 1.17 seconds
Started Jul 19 06:27:07 PM PDT 24
Finished Jul 19 06:27:10 PM PDT 24
Peak memory 219296 kb
Host smart-7c0fe910-6f86-490d-a482-e6228efd5016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127078882 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.4127078882
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.833525321
Short name T402
Test name
Test status
Simulation time 161511558 ps
CPU time 1.03 seconds
Started Jul 19 06:27:07 PM PDT 24
Finished Jul 19 06:27:09 PM PDT 24
Peak memory 207412 kb
Host smart-7a776071-a914-49b1-84b0-b69bb062f6dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833525321 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.833525321
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.721121950
Short name T170
Test name
Test status
Simulation time 12165865 ps
CPU time 0.86 seconds
Started Jul 19 06:27:12 PM PDT 24
Finished Jul 19 06:27:13 PM PDT 24
Peak memory 215836 kb
Host smart-251467fb-b0e3-4c03-a2d6-3da85ebbfd27
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721121950 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.721121950
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.1076704894
Short name T467
Test name
Test status
Simulation time 38735362 ps
CPU time 1.02 seconds
Started Jul 19 06:27:11 PM PDT 24
Finished Jul 19 06:27:12 PM PDT 24
Peak memory 216968 kb
Host smart-fc95fb2c-872a-4612-a3cd-0fe2aeed1576
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076704894 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.1076704894
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.3373212060
Short name T831
Test name
Test status
Simulation time 31240404 ps
CPU time 0.87 seconds
Started Jul 19 06:27:11 PM PDT 24
Finished Jul 19 06:27:13 PM PDT 24
Peak memory 218496 kb
Host smart-b1fa3292-49d6-47f9-b9ac-1b87bd275f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373212060 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.3373212060
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.3563433874
Short name T684
Test name
Test status
Simulation time 60758299 ps
CPU time 1.31 seconds
Started Jul 19 06:27:07 PM PDT 24
Finished Jul 19 06:27:09 PM PDT 24
Peak memory 217432 kb
Host smart-9e2fc071-bc0a-41af-b590-3aa8f729b533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563433874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3563433874
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_regwen.3271934394
Short name T26
Test name
Test status
Simulation time 45429948 ps
CPU time 0.95 seconds
Started Jul 19 06:27:07 PM PDT 24
Finished Jul 19 06:27:09 PM PDT 24
Peak memory 207380 kb
Host smart-ae5a7bad-dd4a-49e1-9c32-7a544e46e553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271934394 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3271934394
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.3639892905
Short name T17
Test name
Test status
Simulation time 618953261 ps
CPU time 9.44 seconds
Started Jul 19 06:27:08 PM PDT 24
Finished Jul 19 06:27:18 PM PDT 24
Peak memory 236136 kb
Host smart-b09d1f59-96f8-4be4-9f09-03127e00d3a6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639892905 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.3639892905
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.3439188022
Short name T965
Test name
Test status
Simulation time 108032558 ps
CPU time 0.89 seconds
Started Jul 19 06:27:03 PM PDT 24
Finished Jul 19 06:27:05 PM PDT 24
Peak memory 215564 kb
Host smart-4088c1aa-3e06-42c6-8ecb-8b504e16b862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439188022 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.3439188022
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.1674667036
Short name T613
Test name
Test status
Simulation time 363800165 ps
CPU time 5.48 seconds
Started Jul 19 06:27:12 PM PDT 24
Finished Jul 19 06:27:19 PM PDT 24
Peak memory 218764 kb
Host smart-91e146c9-646b-4936-9c50-5cc6a5981590
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674667036 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.1674667036
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1427291964
Short name T682
Test name
Test status
Simulation time 43485830741 ps
CPU time 1194.22 seconds
Started Jul 19 06:27:09 PM PDT 24
Finished Jul 19 06:47:04 PM PDT 24
Peak memory 224060 kb
Host smart-7ee8fbb3-c854-47a3-aa3b-6876dc52a535
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427291964 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1427291964
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.3315671102
Short name T465
Test name
Test status
Simulation time 93159503 ps
CPU time 1.13 seconds
Started Jul 19 06:28:03 PM PDT 24
Finished Jul 19 06:28:06 PM PDT 24
Peak memory 220112 kb
Host smart-9683d5b1-8472-47d2-9325-fa4563e3d54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315671102 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.3315671102
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.748858579
Short name T399
Test name
Test status
Simulation time 15098124 ps
CPU time 0.94 seconds
Started Jul 19 06:28:02 PM PDT 24
Finished Jul 19 06:28:04 PM PDT 24
Peak memory 207044 kb
Host smart-456d8746-abc6-41ef-b2cd-5317f99a900c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748858579 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.748858579
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.4206217105
Short name T678
Test name
Test status
Simulation time 35608737 ps
CPU time 0.83 seconds
Started Jul 19 06:27:59 PM PDT 24
Finished Jul 19 06:28:01 PM PDT 24
Peak memory 216156 kb
Host smart-dbe8bf24-183f-4b91-b8ec-bc481acb7a98
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206217105 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.4206217105
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.2819660413
Short name T791
Test name
Test status
Simulation time 49143643 ps
CPU time 1.09 seconds
Started Jul 19 06:28:02 PM PDT 24
Finished Jul 19 06:28:04 PM PDT 24
Peak memory 217016 kb
Host smart-ab18f090-25e5-4ada-bce9-4238ce64d0bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819660413 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.2819660413
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_genbits.3723693709
Short name T485
Test name
Test status
Simulation time 44034698 ps
CPU time 1.56 seconds
Started Jul 19 06:27:53 PM PDT 24
Finished Jul 19 06:27:57 PM PDT 24
Peak memory 217648 kb
Host smart-e8da1fc3-8a66-493e-9229-7710a4b6c5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723693709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3723693709
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.3065369843
Short name T787
Test name
Test status
Simulation time 106173041 ps
CPU time 0.94 seconds
Started Jul 19 06:27:55 PM PDT 24
Finished Jul 19 06:27:58 PM PDT 24
Peak memory 224172 kb
Host smart-a9276e20-42df-477e-9d21-25ee8baca5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065369843 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.3065369843
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.4275091613
Short name T79
Test name
Test status
Simulation time 46330861 ps
CPU time 0.92 seconds
Started Jul 19 06:27:54 PM PDT 24
Finished Jul 19 06:27:57 PM PDT 24
Peak memory 215556 kb
Host smart-ed9e60eb-2096-48c1-98ba-33c78f191478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275091613 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.4275091613
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.771299307
Short name T362
Test name
Test status
Simulation time 923953939 ps
CPU time 2.66 seconds
Started Jul 19 06:27:56 PM PDT 24
Finished Jul 19 06:28:00 PM PDT 24
Peak memory 215576 kb
Host smart-a5bf5dfc-3165-4972-bc88-05b91c181e9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771299307 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.771299307
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.120770958
Short name T633
Test name
Test status
Simulation time 276260998819 ps
CPU time 1506.09 seconds
Started Jul 19 06:27:52 PM PDT 24
Finished Jul 19 06:53:02 PM PDT 24
Peak memory 223888 kb
Host smart-c035db8c-00e7-4724-809d-8b3515bcfff3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120770958 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.120770958
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.2851644404
Short name T901
Test name
Test status
Simulation time 178917428 ps
CPU time 1.09 seconds
Started Jul 19 06:29:59 PM PDT 24
Finished Jul 19 06:30:07 PM PDT 24
Peak memory 217792 kb
Host smart-bbafabd0-03fc-4b9c-a04a-f16a0c224798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851644404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.2851644404
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.421539735
Short name T546
Test name
Test status
Simulation time 62277717 ps
CPU time 1.45 seconds
Started Jul 19 06:29:59 PM PDT 24
Finished Jul 19 06:30:08 PM PDT 24
Peak memory 218856 kb
Host smart-e55963cf-cce5-4ea1-81a1-7256f996f1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421539735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.421539735
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.1806464344
Short name T564
Test name
Test status
Simulation time 36178000 ps
CPU time 1.36 seconds
Started Jul 19 06:30:09 PM PDT 24
Finished Jul 19 06:30:19 PM PDT 24
Peak memory 217508 kb
Host smart-080fd819-e3b8-40b5-a86b-5aa05e4d5323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806464344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.1806464344
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.3563187294
Short name T902
Test name
Test status
Simulation time 102880993 ps
CPU time 1 seconds
Started Jul 19 06:29:58 PM PDT 24
Finished Jul 19 06:30:04 PM PDT 24
Peak memory 217552 kb
Host smart-b7fb19cf-6087-46af-bbfe-0b3df071d6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563187294 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.3563187294
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.4063077465
Short name T369
Test name
Test status
Simulation time 135305913 ps
CPU time 1.99 seconds
Started Jul 19 06:30:06 PM PDT 24
Finished Jul 19 06:30:15 PM PDT 24
Peak memory 219096 kb
Host smart-e9057040-0843-4593-bea9-8461b8d2932a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063077465 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.4063077465
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.587277631
Short name T626
Test name
Test status
Simulation time 57990890 ps
CPU time 1.48 seconds
Started Jul 19 06:30:07 PM PDT 24
Finished Jul 19 06:30:17 PM PDT 24
Peak memory 217728 kb
Host smart-e82d6957-3088-4cf6-a453-39af1e214417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587277631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.587277631
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2327792953
Short name T651
Test name
Test status
Simulation time 101980763 ps
CPU time 1.21 seconds
Started Jul 19 06:30:10 PM PDT 24
Finished Jul 19 06:30:20 PM PDT 24
Peak memory 220380 kb
Host smart-87a39695-99d6-4504-8973-c849fe2691b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327792953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2327792953
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.3237270797
Short name T478
Test name
Test status
Simulation time 62087531 ps
CPU time 1.04 seconds
Started Jul 19 06:30:07 PM PDT 24
Finished Jul 19 06:30:16 PM PDT 24
Peak memory 217356 kb
Host smart-c8ef57ea-78a8-422b-a77c-7a5168713029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237270797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3237270797
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.2052691575
Short name T551
Test name
Test status
Simulation time 64228799 ps
CPU time 1.06 seconds
Started Jul 19 06:30:07 PM PDT 24
Finished Jul 19 06:30:16 PM PDT 24
Peak memory 217444 kb
Host smart-949f3884-01a1-4bc0-b6e3-aec3742906b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052691575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.2052691575
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.334534825
Short name T824
Test name
Test status
Simulation time 66412008 ps
CPU time 1.27 seconds
Started Jul 19 06:30:04 PM PDT 24
Finished Jul 19 06:30:13 PM PDT 24
Peak memory 220152 kb
Host smart-b246e3ee-285e-4bb5-be3f-8234ba8e8f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334534825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.334534825
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.1041679837
Short name T46
Test name
Test status
Simulation time 35514572 ps
CPU time 1.18 seconds
Started Jul 19 06:28:03 PM PDT 24
Finished Jul 19 06:28:05 PM PDT 24
Peak memory 218744 kb
Host smart-8b603ed4-f5e1-4c83-9437-b60c7dac1bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041679837 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.1041679837
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.4123849161
Short name T456
Test name
Test status
Simulation time 44740961 ps
CPU time 0.91 seconds
Started Jul 19 06:28:03 PM PDT 24
Finished Jul 19 06:28:05 PM PDT 24
Peak memory 207024 kb
Host smart-7e4d34ae-4f04-45ab-b9e9-7ba7f6bc6446
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123849161 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.4123849161
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.1674969637
Short name T721
Test name
Test status
Simulation time 27537224 ps
CPU time 0.85 seconds
Started Jul 19 06:28:01 PM PDT 24
Finished Jul 19 06:28:04 PM PDT 24
Peak memory 216592 kb
Host smart-d4ef2d61-350d-4e84-a08c-71deb677ca57
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674969637 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1674969637
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_err.2696376248
Short name T160
Test name
Test status
Simulation time 24631397 ps
CPU time 1.32 seconds
Started Jul 19 06:28:00 PM PDT 24
Finished Jul 19 06:28:02 PM PDT 24
Peak memory 229980 kb
Host smart-f26ae92e-b51e-4a9f-9d4e-f40da747b6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696376248 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.2696376248
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.4059806534
Short name T441
Test name
Test status
Simulation time 139018573 ps
CPU time 1.41 seconds
Started Jul 19 06:28:02 PM PDT 24
Finished Jul 19 06:28:05 PM PDT 24
Peak memory 219892 kb
Host smart-27b81e01-12e9-490a-b3d9-7c4a7dd2e62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059806534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.4059806534
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.4138338574
Short name T988
Test name
Test status
Simulation time 26037030 ps
CPU time 0.95 seconds
Started Jul 19 06:28:02 PM PDT 24
Finished Jul 19 06:28:05 PM PDT 24
Peak memory 216120 kb
Host smart-2ecd27d3-eefa-4370-89a7-5798913a0dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138338574 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.4138338574
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.3695181322
Short name T525
Test name
Test status
Simulation time 16082011 ps
CPU time 0.93 seconds
Started Jul 19 06:28:05 PM PDT 24
Finished Jul 19 06:28:07 PM PDT 24
Peak memory 215564 kb
Host smart-4673273f-f441-471c-8ea6-10f083c3da7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695181322 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.3695181322
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.743221117
Short name T883
Test name
Test status
Simulation time 159348725 ps
CPU time 3.44 seconds
Started Jul 19 06:28:02 PM PDT 24
Finished Jul 19 06:28:06 PM PDT 24
Peak memory 215656 kb
Host smart-712f049b-bc23-4252-86e2-72087f0af82a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743221117 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.743221117
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.1675197996
Short name T786
Test name
Test status
Simulation time 34071802698 ps
CPU time 392.42 seconds
Started Jul 19 06:28:02 PM PDT 24
Finished Jul 19 06:34:36 PM PDT 24
Peak memory 219312 kb
Host smart-042c1cef-3fb7-4003-9095-ccf131571125
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675197996 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.1675197996
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/211.edn_genbits.1769580163
Short name T877
Test name
Test status
Simulation time 116531849 ps
CPU time 2.71 seconds
Started Jul 19 06:30:05 PM PDT 24
Finished Jul 19 06:30:15 PM PDT 24
Peak memory 218796 kb
Host smart-c739dfc4-7278-4149-a10f-2482dba48c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769580163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.1769580163
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.1801346888
Short name T629
Test name
Test status
Simulation time 189654326 ps
CPU time 1.54 seconds
Started Jul 19 06:30:08 PM PDT 24
Finished Jul 19 06:30:17 PM PDT 24
Peak memory 219380 kb
Host smart-f31ff7b7-d6ec-4d9c-9636-403d249dbe1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801346888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.1801346888
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.2527306506
Short name T771
Test name
Test status
Simulation time 59174451 ps
CPU time 1.51 seconds
Started Jul 19 06:30:09 PM PDT 24
Finished Jul 19 06:30:19 PM PDT 24
Peak memory 218904 kb
Host smart-8389a9cf-e504-4b50-a32a-c23c8b662868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527306506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.2527306506
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.650740616
Short name T576
Test name
Test status
Simulation time 67207360 ps
CPU time 1.31 seconds
Started Jul 19 06:30:09 PM PDT 24
Finished Jul 19 06:30:19 PM PDT 24
Peak memory 218724 kb
Host smart-9a954731-8533-458b-ac87-0526eb10cfd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650740616 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.650740616
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.1495699117
Short name T990
Test name
Test status
Simulation time 69448298 ps
CPU time 1.39 seconds
Started Jul 19 06:30:09 PM PDT 24
Finished Jul 19 06:30:18 PM PDT 24
Peak memory 217612 kb
Host smart-da458795-19a8-46cf-b87d-b8ddb369f79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495699117 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.1495699117
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.2734494570
Short name T541
Test name
Test status
Simulation time 54811595 ps
CPU time 0.94 seconds
Started Jul 19 06:30:05 PM PDT 24
Finished Jul 19 06:30:14 PM PDT 24
Peak memory 217640 kb
Host smart-e369b01e-6f04-4902-8b03-5743018ad3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734494570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2734494570
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.1070574597
Short name T329
Test name
Test status
Simulation time 126311636 ps
CPU time 1.56 seconds
Started Jul 19 06:30:08 PM PDT 24
Finished Jul 19 06:30:17 PM PDT 24
Peak memory 220144 kb
Host smart-93d0bdb8-0a9c-4ecf-87dd-311d7549e849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070574597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.1070574597
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.4229348550
Short name T834
Test name
Test status
Simulation time 167868724 ps
CPU time 1.7 seconds
Started Jul 19 06:30:09 PM PDT 24
Finished Jul 19 06:30:19 PM PDT 24
Peak memory 218776 kb
Host smart-5decc21f-1b67-483f-80a6-5822ce62939d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229348550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.4229348550
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.2508807514
Short name T143
Test name
Test status
Simulation time 25261617 ps
CPU time 1.24 seconds
Started Jul 19 06:28:00 PM PDT 24
Finished Jul 19 06:28:03 PM PDT 24
Peak memory 220208 kb
Host smart-1961e3a3-1898-44dc-bb23-6e34942fe561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508807514 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.2508807514
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.1264078080
Short name T532
Test name
Test status
Simulation time 41097767 ps
CPU time 0.83 seconds
Started Jul 19 06:27:59 PM PDT 24
Finished Jul 19 06:28:01 PM PDT 24
Peak memory 206800 kb
Host smart-d6ec227c-5338-4037-b21a-4f316621840c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264078080 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1264078080
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.1579950764
Short name T222
Test name
Test status
Simulation time 13086396 ps
CPU time 0.88 seconds
Started Jul 19 06:28:06 PM PDT 24
Finished Jul 19 06:28:07 PM PDT 24
Peak memory 216688 kb
Host smart-dfd2dcdf-e216-4393-9905-854e21a0dee7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579950764 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.1579950764
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.2403602587
Short name T226
Test name
Test status
Simulation time 54873833 ps
CPU time 1.17 seconds
Started Jul 19 06:28:02 PM PDT 24
Finished Jul 19 06:28:04 PM PDT 24
Peak memory 217208 kb
Host smart-45574b56-8786-4007-96ed-7d9a4b1b682c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403602587 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.2403602587
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.528372952
Short name T992
Test name
Test status
Simulation time 32429617 ps
CPU time 0.95 seconds
Started Jul 19 06:27:59 PM PDT 24
Finished Jul 19 06:28:01 PM PDT 24
Peak memory 219988 kb
Host smart-371fdf1b-7942-4488-8104-69e39d573383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528372952 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.528372952
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.2082713819
Short name T393
Test name
Test status
Simulation time 63079015 ps
CPU time 1.46 seconds
Started Jul 19 06:28:06 PM PDT 24
Finished Jul 19 06:28:08 PM PDT 24
Peak memory 219228 kb
Host smart-ad90dc26-31e8-4712-a3d4-949211e1aa2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082713819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2082713819
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.3576750347
Short name T33
Test name
Test status
Simulation time 23626123 ps
CPU time 0.97 seconds
Started Jul 19 06:27:59 PM PDT 24
Finished Jul 19 06:28:00 PM PDT 24
Peak memory 216104 kb
Host smart-b6c915fe-02de-414f-af00-39b5ecaf1617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576750347 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.3576750347
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.1268948094
Short name T734
Test name
Test status
Simulation time 15514532 ps
CPU time 0.99 seconds
Started Jul 19 06:27:59 PM PDT 24
Finished Jul 19 06:28:01 PM PDT 24
Peak memory 215604 kb
Host smart-6065f685-8ba1-429b-8d27-c99e97783add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268948094 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.1268948094
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.4217542850
Short name T770
Test name
Test status
Simulation time 280747730 ps
CPU time 5.55 seconds
Started Jul 19 06:28:04 PM PDT 24
Finished Jul 19 06:28:11 PM PDT 24
Peak memory 217380 kb
Host smart-eff78ff2-3dc1-4e88-80b7-6597961e5b77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217542850 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.4217542850
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.4270255108
Short name T245
Test name
Test status
Simulation time 56223606338 ps
CPU time 1112.04 seconds
Started Jul 19 06:28:05 PM PDT 24
Finished Jul 19 06:46:38 PM PDT 24
Peak memory 223936 kb
Host smart-8af31910-fce7-446a-86c0-6082a73aeee2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270255108 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.4270255108
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.3252119515
Short name T401
Test name
Test status
Simulation time 56495298 ps
CPU time 1.1 seconds
Started Jul 19 06:30:09 PM PDT 24
Finished Jul 19 06:30:18 PM PDT 24
Peak memory 217500 kb
Host smart-7824dd28-2497-40f1-b36d-9518758baae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252119515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.3252119515
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.2780106886
Short name T237
Test name
Test status
Simulation time 113067972 ps
CPU time 2.63 seconds
Started Jul 19 06:30:08 PM PDT 24
Finished Jul 19 06:30:18 PM PDT 24
Peak memory 220424 kb
Host smart-7f1e2f43-2c9d-4c1b-9c97-9492c40f8d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780106886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.2780106886
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.1138397392
Short name T828
Test name
Test status
Simulation time 151443480 ps
CPU time 1.66 seconds
Started Jul 19 06:30:09 PM PDT 24
Finished Jul 19 06:30:20 PM PDT 24
Peak memory 215656 kb
Host smart-13a6f7a7-3818-40e3-b15d-534d17384c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138397392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.1138397392
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.3277395868
Short name T346
Test name
Test status
Simulation time 40254025 ps
CPU time 1.55 seconds
Started Jul 19 06:30:08 PM PDT 24
Finished Jul 19 06:30:17 PM PDT 24
Peak memory 219852 kb
Host smart-b83390d7-df81-4f1f-878a-7530e82ecafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277395868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.3277395868
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.2064650124
Short name T461
Test name
Test status
Simulation time 209829927 ps
CPU time 1.06 seconds
Started Jul 19 06:30:08 PM PDT 24
Finished Jul 19 06:30:17 PM PDT 24
Peak memory 217440 kb
Host smart-3cb7e7be-86e8-4582-a9d7-b678b7a847a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064650124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.2064650124
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.3339290914
Short name T814
Test name
Test status
Simulation time 67893552 ps
CPU time 1.22 seconds
Started Jul 19 06:30:05 PM PDT 24
Finished Jul 19 06:30:14 PM PDT 24
Peak memory 217612 kb
Host smart-718ddc58-bc17-42b5-82eb-04f3efa0c59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339290914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.3339290914
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.3736638709
Short name T815
Test name
Test status
Simulation time 32748657 ps
CPU time 1.24 seconds
Started Jul 19 06:30:10 PM PDT 24
Finished Jul 19 06:30:19 PM PDT 24
Peak memory 217568 kb
Host smart-46dd4b94-7f2f-483f-a51f-1d9eceb48ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736638709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3736638709
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.766710467
Short name T453
Test name
Test status
Simulation time 94343545 ps
CPU time 0.94 seconds
Started Jul 19 06:30:08 PM PDT 24
Finished Jul 19 06:30:17 PM PDT 24
Peak memory 217484 kb
Host smart-1105b9bd-290b-40f8-8fe2-372cf86edc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766710467 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.766710467
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.1182908422
Short name T945
Test name
Test status
Simulation time 30511551 ps
CPU time 1.45 seconds
Started Jul 19 06:30:10 PM PDT 24
Finished Jul 19 06:30:20 PM PDT 24
Peak memory 218872 kb
Host smart-c41610d1-e1ba-47cb-a71b-c110fb329af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182908422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.1182908422
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.1250740280
Short name T934
Test name
Test status
Simulation time 41983022 ps
CPU time 1.72 seconds
Started Jul 19 06:30:06 PM PDT 24
Finished Jul 19 06:30:15 PM PDT 24
Peak memory 218884 kb
Host smart-41076171-8ffa-40dd-948c-3531b5ea059b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250740280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1250740280
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.4275607348
Short name T517
Test name
Test status
Simulation time 26015158 ps
CPU time 1.24 seconds
Started Jul 19 06:28:00 PM PDT 24
Finished Jul 19 06:28:02 PM PDT 24
Peak memory 219452 kb
Host smart-8f301634-7efc-45bc-8263-ee52f39243c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275607348 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.4275607348
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.1737364198
Short name T885
Test name
Test status
Simulation time 28000669 ps
CPU time 0.93 seconds
Started Jul 19 06:28:03 PM PDT 24
Finished Jul 19 06:28:05 PM PDT 24
Peak memory 215252 kb
Host smart-57b293e4-c9b4-44c5-901a-bc2586cc202d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737364198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.1737364198
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.1345096035
Short name T602
Test name
Test status
Simulation time 14673314 ps
CPU time 0.93 seconds
Started Jul 19 06:28:02 PM PDT 24
Finished Jul 19 06:28:04 PM PDT 24
Peak memory 216404 kb
Host smart-19417538-1639-49f4-9f88-7cf0e864a157
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345096035 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.1345096035
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3819004739
Short name T615
Test name
Test status
Simulation time 236659487 ps
CPU time 1.36 seconds
Started Jul 19 06:27:59 PM PDT 24
Finished Jul 19 06:28:01 PM PDT 24
Peak memory 217104 kb
Host smart-9d70bbf0-f5f6-4dda-995e-db1c847eb8e0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819004739 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3819004739
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.2492167920
Short name T968
Test name
Test status
Simulation time 23001222 ps
CPU time 0.97 seconds
Started Jul 19 06:28:02 PM PDT 24
Finished Jul 19 06:28:05 PM PDT 24
Peak memory 218812 kb
Host smart-75e12000-ce9c-4b64-a4db-a9c85af26cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492167920 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.2492167920
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_intr.1329654982
Short name T90
Test name
Test status
Simulation time 36139674 ps
CPU time 0.89 seconds
Started Jul 19 06:28:00 PM PDT 24
Finished Jul 19 06:28:02 PM PDT 24
Peak memory 215708 kb
Host smart-cef54fc1-6252-4edf-9809-ab971a23fbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329654982 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.1329654982
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.1673489430
Short name T601
Test name
Test status
Simulation time 16669989 ps
CPU time 0.98 seconds
Started Jul 19 06:28:01 PM PDT 24
Finished Jul 19 06:28:04 PM PDT 24
Peak memory 215564 kb
Host smart-f1c3cc82-099e-4f1e-9341-9513ae198870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673489430 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.1673489430
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.3653742177
Short name T782
Test name
Test status
Simulation time 169288309 ps
CPU time 3.59 seconds
Started Jul 19 06:28:00 PM PDT 24
Finished Jul 19 06:28:05 PM PDT 24
Peak memory 217448 kb
Host smart-95b61eeb-fcec-4819-80e8-c5470e0f0adf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653742177 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3653742177
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.4014248894
Short name T510
Test name
Test status
Simulation time 38544773159 ps
CPU time 1037.09 seconds
Started Jul 19 06:28:03 PM PDT 24
Finished Jul 19 06:45:22 PM PDT 24
Peak memory 220960 kb
Host smart-5536eca9-e1ac-4d3e-9c7c-34e6828e2e9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014248894 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.4014248894
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.2452689408
Short name T63
Test name
Test status
Simulation time 83410620 ps
CPU time 1.26 seconds
Started Jul 19 06:30:08 PM PDT 24
Finished Jul 19 06:30:17 PM PDT 24
Peak memory 218908 kb
Host smart-74ea1f06-fcd5-487f-bd68-8c829fe8e68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452689408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2452689408
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.1138513180
Short name T559
Test name
Test status
Simulation time 37332135 ps
CPU time 1.52 seconds
Started Jul 19 06:30:09 PM PDT 24
Finished Jul 19 06:30:19 PM PDT 24
Peak memory 217660 kb
Host smart-ff1929a6-2e0b-4151-a360-c1ed469b3add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138513180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1138513180
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.1956743482
Short name T589
Test name
Test status
Simulation time 74080671 ps
CPU time 2.53 seconds
Started Jul 19 06:30:09 PM PDT 24
Finished Jul 19 06:30:20 PM PDT 24
Peak memory 220488 kb
Host smart-6dae9279-9f39-4dfa-b097-8cee5dda5612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956743482 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.1956743482
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.2643691185
Short name T415
Test name
Test status
Simulation time 45756733 ps
CPU time 1 seconds
Started Jul 19 06:30:04 PM PDT 24
Finished Jul 19 06:30:13 PM PDT 24
Peak memory 217588 kb
Host smart-42a6dbd2-bd62-4729-afad-f7f526bf0182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643691185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.2643691185
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.3920772183
Short name T543
Test name
Test status
Simulation time 260459367 ps
CPU time 1.87 seconds
Started Jul 19 06:30:09 PM PDT 24
Finished Jul 19 06:30:20 PM PDT 24
Peak memory 219404 kb
Host smart-0286a184-80c7-4e49-b5ac-33b9f243516b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920772183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.3920772183
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.2700236554
Short name T416
Test name
Test status
Simulation time 84279448 ps
CPU time 1.4 seconds
Started Jul 19 06:30:08 PM PDT 24
Finished Jul 19 06:30:17 PM PDT 24
Peak memory 219304 kb
Host smart-6c6456ca-635c-4fc9-8a4f-5996ce908714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700236554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2700236554
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.2263787523
Short name T352
Test name
Test status
Simulation time 50822391 ps
CPU time 2.04 seconds
Started Jul 19 06:30:36 PM PDT 24
Finished Jul 19 06:30:39 PM PDT 24
Peak memory 219452 kb
Host smart-59406995-437f-489c-acbe-274effcf4015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263787523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.2263787523
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.1800857841
Short name T319
Test name
Test status
Simulation time 41287012 ps
CPU time 1.08 seconds
Started Jul 19 06:30:07 PM PDT 24
Finished Jul 19 06:30:17 PM PDT 24
Peak memory 217432 kb
Host smart-fc7714b8-0af9-4e49-b3e7-8cc88b602711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800857841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.1800857841
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.3337946999
Short name T715
Test name
Test status
Simulation time 25590338 ps
CPU time 1.22 seconds
Started Jul 19 06:28:01 PM PDT 24
Finished Jul 19 06:28:04 PM PDT 24
Peak memory 219084 kb
Host smart-6d6853c4-46e1-4e24-8e97-0e36d118644a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337946999 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.3337946999
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.80140724
Short name T479
Test name
Test status
Simulation time 21425635 ps
CPU time 0.86 seconds
Started Jul 19 06:28:08 PM PDT 24
Finished Jul 19 06:28:10 PM PDT 24
Peak memory 206840 kb
Host smart-a7cf98b9-a4eb-4670-98dc-54452dd44a2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80140724 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.80140724
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.769745187
Short name T367
Test name
Test status
Simulation time 33133091 ps
CPU time 0.86 seconds
Started Jul 19 06:28:07 PM PDT 24
Finished Jul 19 06:28:08 PM PDT 24
Peak memory 216592 kb
Host smart-3b10c32d-d7a7-4551-b8f6-03424267eafb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769745187 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.769745187
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.20236621
Short name T922
Test name
Test status
Simulation time 126807312 ps
CPU time 1.19 seconds
Started Jul 19 06:28:09 PM PDT 24
Finished Jul 19 06:28:11 PM PDT 24
Peak memory 217000 kb
Host smart-03dfeb49-0ebe-4da3-8e4b-68f7c09e8c81
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20236621 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_dis
able_auto_req_mode.20236621
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.3161181986
Short name T634
Test name
Test status
Simulation time 24260414 ps
CPU time 1.02 seconds
Started Jul 19 06:28:08 PM PDT 24
Finished Jul 19 06:28:09 PM PDT 24
Peak memory 224272 kb
Host smart-6f488138-8cae-4066-8d5e-7cd3f86c33aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161181986 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.3161181986
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.1110294843
Short name T82
Test name
Test status
Simulation time 37148961 ps
CPU time 1.37 seconds
Started Jul 19 06:28:02 PM PDT 24
Finished Jul 19 06:28:04 PM PDT 24
Peak memory 219516 kb
Host smart-04d4bf57-b0ee-411f-bceb-49dfa0a70801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110294843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1110294843
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.3727593672
Short name T488
Test name
Test status
Simulation time 45618580 ps
CPU time 1.01 seconds
Started Jul 19 06:27:59 PM PDT 24
Finished Jul 19 06:28:01 PM PDT 24
Peak memory 224436 kb
Host smart-920d6d7b-c081-40d2-a07b-826bcfaee5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727593672 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3727593672
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.2190892467
Short name T358
Test name
Test status
Simulation time 14892555 ps
CPU time 1.06 seconds
Started Jul 19 06:28:03 PM PDT 24
Finished Jul 19 06:28:05 PM PDT 24
Peak memory 215688 kb
Host smart-60d1f4de-67fc-499e-a89a-329d09723bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190892467 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.2190892467
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.991904339
Short name T776
Test name
Test status
Simulation time 1143402315 ps
CPU time 5.36 seconds
Started Jul 19 06:28:02 PM PDT 24
Finished Jul 19 06:28:09 PM PDT 24
Peak memory 217628 kb
Host smart-f672b9ff-afa3-44f6-8a7a-cc159320643d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991904339 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.991904339
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1510103991
Short name T792
Test name
Test status
Simulation time 78651315500 ps
CPU time 1844.72 seconds
Started Jul 19 06:27:59 PM PDT 24
Finished Jul 19 06:58:45 PM PDT 24
Peak memory 227656 kb
Host smart-19641f1a-d9c5-47ae-8bc9-d9cf8fcbf805
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510103991 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1510103991
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.965563900
Short name T821
Test name
Test status
Simulation time 258756462 ps
CPU time 3.35 seconds
Started Jul 19 06:30:04 PM PDT 24
Finished Jul 19 06:30:15 PM PDT 24
Peak memory 220460 kb
Host smart-124cfd02-cdc3-4527-9349-e430d11ba348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965563900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.965563900
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.3387863926
Short name T389
Test name
Test status
Simulation time 64062831 ps
CPU time 1.11 seconds
Started Jul 19 06:30:04 PM PDT 24
Finished Jul 19 06:30:13 PM PDT 24
Peak memory 218808 kb
Host smart-7cc00f70-8002-400b-984b-d55a80718895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387863926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.3387863926
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.248667688
Short name T620
Test name
Test status
Simulation time 153671930 ps
CPU time 1.26 seconds
Started Jul 19 06:30:05 PM PDT 24
Finished Jul 19 06:30:14 PM PDT 24
Peak memory 219304 kb
Host smart-cb98a9e7-7dbe-4881-a093-708ba1fe5ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248667688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.248667688
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.3691908979
Short name T361
Test name
Test status
Simulation time 86115584 ps
CPU time 1.3 seconds
Started Jul 19 06:30:05 PM PDT 24
Finished Jul 19 06:30:14 PM PDT 24
Peak memory 219284 kb
Host smart-92bd88a1-fc29-4db1-9ec8-eb3e3098bede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691908979 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3691908979
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.3035557486
Short name T774
Test name
Test status
Simulation time 50494797 ps
CPU time 1.02 seconds
Started Jul 19 06:30:04 PM PDT 24
Finished Jul 19 06:30:13 PM PDT 24
Peak memory 217844 kb
Host smart-851136b9-d619-482a-8b88-fce56c9bc44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035557486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.3035557486
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.1175810521
Short name T795
Test name
Test status
Simulation time 137337838 ps
CPU time 1.12 seconds
Started Jul 19 06:30:10 PM PDT 24
Finished Jul 19 06:30:20 PM PDT 24
Peak memory 217620 kb
Host smart-a1075997-a349-417a-a04d-b4a6d02af83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175810521 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.1175810521
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.558515640
Short name T512
Test name
Test status
Simulation time 82977778 ps
CPU time 1.29 seconds
Started Jul 19 06:30:06 PM PDT 24
Finished Jul 19 06:30:14 PM PDT 24
Peak memory 217476 kb
Host smart-8e93ada8-3583-4b17-a298-c6957f29a7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558515640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.558515640
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.4006217939
Short name T334
Test name
Test status
Simulation time 88707178 ps
CPU time 1.9 seconds
Started Jul 19 06:30:10 PM PDT 24
Finished Jul 19 06:30:21 PM PDT 24
Peak memory 219844 kb
Host smart-102c3c5c-e5ac-4a8d-9080-409e575bb6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006217939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.4006217939
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.374866770
Short name T398
Test name
Test status
Simulation time 54842950 ps
CPU time 1.81 seconds
Started Jul 19 06:30:07 PM PDT 24
Finished Jul 19 06:30:16 PM PDT 24
Peak memory 218912 kb
Host smart-847e30c5-888b-43f5-b6e6-0d7c28239b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374866770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.374866770
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.995337844
Short name T332
Test name
Test status
Simulation time 34911688 ps
CPU time 1.5 seconds
Started Jul 19 06:30:07 PM PDT 24
Finished Jul 19 06:30:17 PM PDT 24
Peak memory 217508 kb
Host smart-3a33a3dc-fddf-42a1-aa3f-81b3421bfa0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995337844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.995337844
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.2516643440
Short name T310
Test name
Test status
Simulation time 77907566 ps
CPU time 1.17 seconds
Started Jul 19 06:28:07 PM PDT 24
Finished Jul 19 06:28:09 PM PDT 24
Peak memory 218840 kb
Host smart-6220db98-8691-4244-8c6b-e64e39cf1e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516643440 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.2516643440
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.1440002182
Short name T719
Test name
Test status
Simulation time 15836850 ps
CPU time 0.98 seconds
Started Jul 19 06:28:07 PM PDT 24
Finished Jul 19 06:28:08 PM PDT 24
Peak memory 215480 kb
Host smart-c4be8fa2-178f-49e0-905c-981b811b9cfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440002182 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.1440002182
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.2142147896
Short name T578
Test name
Test status
Simulation time 36687976 ps
CPU time 0.89 seconds
Started Jul 19 06:28:10 PM PDT 24
Finished Jul 19 06:28:11 PM PDT 24
Peak memory 216512 kb
Host smart-bea8f945-7394-4d0d-a9ae-c29c72781dbe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142147896 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2142147896
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.3609726105
Short name T925
Test name
Test status
Simulation time 35144112 ps
CPU time 1.17 seconds
Started Jul 19 06:28:11 PM PDT 24
Finished Jul 19 06:28:13 PM PDT 24
Peak memory 218608 kb
Host smart-3c3e59db-3bc1-4078-8309-609986edb898
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609726105 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.3609726105
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.3853914516
Short name T227
Test name
Test status
Simulation time 35999694 ps
CPU time 0.89 seconds
Started Jul 19 06:28:09 PM PDT 24
Finished Jul 19 06:28:10 PM PDT 24
Peak memory 218552 kb
Host smart-f6c40e1d-5ebf-4388-ba37-2e22ee8f6c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853914516 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.3853914516
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.1101239213
Short name T284
Test name
Test status
Simulation time 75702067 ps
CPU time 1.13 seconds
Started Jul 19 06:28:06 PM PDT 24
Finished Jul 19 06:28:08 PM PDT 24
Peak memory 217476 kb
Host smart-48502c1f-3863-4d7d-a62a-4a7aedc7ed12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101239213 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1101239213
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.3261398411
Short name T929
Test name
Test status
Simulation time 22954405 ps
CPU time 1.01 seconds
Started Jul 19 06:28:10 PM PDT 24
Finished Jul 19 06:28:12 PM PDT 24
Peak memory 215748 kb
Host smart-5d210e31-3d35-4460-b1da-a2720afcf982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261398411 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.3261398411
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.1755900167
Short name T717
Test name
Test status
Simulation time 22692897 ps
CPU time 0.97 seconds
Started Jul 19 06:28:07 PM PDT 24
Finished Jul 19 06:28:09 PM PDT 24
Peak memory 215480 kb
Host smart-b70d19ca-2b1c-405f-bda3-5776f93fcf69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755900167 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.1755900167
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.1389632571
Short name T574
Test name
Test status
Simulation time 399389182 ps
CPU time 4.32 seconds
Started Jul 19 06:28:07 PM PDT 24
Finished Jul 19 06:28:12 PM PDT 24
Peak memory 215596 kb
Host smart-f24569ac-52a9-4b8f-983d-e2476ccb49fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389632571 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1389632571
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.1227629415
Short name T451
Test name
Test status
Simulation time 238531322262 ps
CPU time 724.95 seconds
Started Jul 19 06:28:10 PM PDT 24
Finished Jul 19 06:40:16 PM PDT 24
Peak memory 230012 kb
Host smart-955fe36e-7f1f-4ac2-bb0d-7c472e363339
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227629415 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.1227629415
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.3866455505
Short name T376
Test name
Test status
Simulation time 68777775 ps
CPU time 1.33 seconds
Started Jul 19 06:30:07 PM PDT 24
Finished Jul 19 06:30:16 PM PDT 24
Peak memory 217484 kb
Host smart-9b7176b1-4df5-4976-bed6-9d608a35897d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866455505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3866455505
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.591511285
Short name T836
Test name
Test status
Simulation time 548765713 ps
CPU time 3.94 seconds
Started Jul 19 06:30:06 PM PDT 24
Finished Jul 19 06:30:17 PM PDT 24
Peak memory 220580 kb
Host smart-28a7354e-1eba-49b2-a280-cff434c41426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591511285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.591511285
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2383716913
Short name T425
Test name
Test status
Simulation time 79103902 ps
CPU time 1.19 seconds
Started Jul 19 06:30:09 PM PDT 24
Finished Jul 19 06:30:19 PM PDT 24
Peak memory 220288 kb
Host smart-8f2726eb-72a6-4eba-96db-8288fd0c2178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383716913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2383716913
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.1321234641
Short name T753
Test name
Test status
Simulation time 84263639 ps
CPU time 1.13 seconds
Started Jul 19 06:30:06 PM PDT 24
Finished Jul 19 06:30:14 PM PDT 24
Peak memory 219004 kb
Host smart-09e27c16-3d0b-4218-b9d6-548a7e9ce351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321234641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.1321234641
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.1214703266
Short name T59
Test name
Test status
Simulation time 39019985 ps
CPU time 1.59 seconds
Started Jul 19 06:30:07 PM PDT 24
Finished Jul 19 06:30:17 PM PDT 24
Peak memory 218576 kb
Host smart-a9c41fed-2264-4fe2-b3a3-1a07024c9e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214703266 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.1214703266
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.2179452550
Short name T542
Test name
Test status
Simulation time 95008934 ps
CPU time 1.26 seconds
Started Jul 19 06:30:05 PM PDT 24
Finished Jul 19 06:30:14 PM PDT 24
Peak memory 217400 kb
Host smart-7edb377b-c0e8-4708-8ff9-fa2e8a62d04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179452550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2179452550
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.1597369343
Short name T412
Test name
Test status
Simulation time 47145205 ps
CPU time 1.25 seconds
Started Jul 19 06:30:07 PM PDT 24
Finished Jul 19 06:30:16 PM PDT 24
Peak memory 219032 kb
Host smart-2bf84ea2-ddea-45ed-ab4d-23817cd0c7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597369343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1597369343
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.439331328
Short name T612
Test name
Test status
Simulation time 96552818 ps
CPU time 1.15 seconds
Started Jul 19 06:30:08 PM PDT 24
Finished Jul 19 06:30:17 PM PDT 24
Peak memory 218928 kb
Host smart-382bb876-0e8c-4ecf-ad16-97e9bf0d1a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439331328 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.439331328
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.1320983701
Short name T371
Test name
Test status
Simulation time 55437409 ps
CPU time 1.82 seconds
Started Jul 19 06:30:06 PM PDT 24
Finished Jul 19 06:30:15 PM PDT 24
Peak memory 220356 kb
Host smart-9c92f080-2340-4155-9a10-53ef3b0e6815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320983701 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1320983701
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.2926698173
Short name T942
Test name
Test status
Simulation time 55411317 ps
CPU time 1.74 seconds
Started Jul 19 06:30:09 PM PDT 24
Finished Jul 19 06:30:19 PM PDT 24
Peak memory 218724 kb
Host smart-606afb4d-abb9-487c-9164-24e71c0bd388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926698173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.2926698173
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.3117835120
Short name T598
Test name
Test status
Simulation time 40752888 ps
CPU time 1.19 seconds
Started Jul 19 06:28:07 PM PDT 24
Finished Jul 19 06:28:08 PM PDT 24
Peak memory 218948 kb
Host smart-2f9bb4c1-52ca-4836-b39f-7ade3b1e4b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117835120 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.3117835120
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.2330605946
Short name T423
Test name
Test status
Simulation time 15801951 ps
CPU time 0.93 seconds
Started Jul 19 06:28:09 PM PDT 24
Finished Jul 19 06:28:10 PM PDT 24
Peak memory 215224 kb
Host smart-9085027d-71a7-4ab1-9cf9-6d834419dca0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330605946 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2330605946
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.2372780396
Short name T480
Test name
Test status
Simulation time 30946073 ps
CPU time 0.84 seconds
Started Jul 19 06:28:10 PM PDT 24
Finished Jul 19 06:28:12 PM PDT 24
Peak memory 216220 kb
Host smart-39df1fd7-39f1-428a-aa03-21514950d3b0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372780396 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.2372780396
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.1800912251
Short name T769
Test name
Test status
Simulation time 110709180 ps
CPU time 1.32 seconds
Started Jul 19 06:28:10 PM PDT 24
Finished Jul 19 06:28:12 PM PDT 24
Peak memory 217188 kb
Host smart-19935051-01a8-49e9-baac-f04778b6924e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800912251 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.1800912251
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.3020670476
Short name T230
Test name
Test status
Simulation time 30086185 ps
CPU time 0.87 seconds
Started Jul 19 06:28:07 PM PDT 24
Finished Jul 19 06:28:08 PM PDT 24
Peak memory 218748 kb
Host smart-adc1eabd-06ca-4735-ab45-9e212ed69a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020670476 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.3020670476
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.775224257
Short name T440
Test name
Test status
Simulation time 33837710 ps
CPU time 1.28 seconds
Started Jul 19 06:28:08 PM PDT 24
Finished Jul 19 06:28:10 PM PDT 24
Peak memory 217616 kb
Host smart-8ffc4ad3-dd2f-48a1-8513-6fca6294cbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775224257 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.775224257
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.2145000927
Short name T102
Test name
Test status
Simulation time 27101171 ps
CPU time 1.01 seconds
Started Jul 19 06:28:06 PM PDT 24
Finished Jul 19 06:28:08 PM PDT 24
Peak memory 216088 kb
Host smart-e6e6313a-51a5-4d87-8493-4f37ea49cf36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145000927 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2145000927
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.3638166818
Short name T742
Test name
Test status
Simulation time 18695254 ps
CPU time 1.01 seconds
Started Jul 19 06:28:08 PM PDT 24
Finished Jul 19 06:28:10 PM PDT 24
Peak memory 215580 kb
Host smart-699af82c-b2bc-4c83-9c2d-85216e0574f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638166818 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.3638166818
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.4130285875
Short name T73
Test name
Test status
Simulation time 99367521 ps
CPU time 1.99 seconds
Started Jul 19 06:28:09 PM PDT 24
Finished Jul 19 06:28:12 PM PDT 24
Peak memory 217608 kb
Host smart-3a539ae1-0d32-4826-ba83-d3883b295647
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130285875 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.4130285875
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.839218846
Short name T750
Test name
Test status
Simulation time 110587530894 ps
CPU time 1355.07 seconds
Started Jul 19 06:28:06 PM PDT 24
Finished Jul 19 06:50:42 PM PDT 24
Peak memory 224076 kb
Host smart-8a6ede7a-34a3-4210-80b4-cbca49b9edbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839218846 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.839218846
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.862639730
Short name T419
Test name
Test status
Simulation time 145233643 ps
CPU time 2.18 seconds
Started Jul 19 06:30:04 PM PDT 24
Finished Jul 19 06:30:15 PM PDT 24
Peak memory 219576 kb
Host smart-e478f637-3465-4140-9c29-11ab90503f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862639730 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.862639730
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.1034073651
Short name T714
Test name
Test status
Simulation time 44577900 ps
CPU time 1.18 seconds
Started Jul 19 06:30:07 PM PDT 24
Finished Jul 19 06:30:15 PM PDT 24
Peak memory 217548 kb
Host smart-519158b6-0a23-4470-b325-f7f68d818778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034073651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1034073651
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.2860857088
Short name T759
Test name
Test status
Simulation time 53019156 ps
CPU time 1.87 seconds
Started Jul 19 06:30:09 PM PDT 24
Finished Jul 19 06:30:19 PM PDT 24
Peak memory 218948 kb
Host smart-65845b15-6e97-47ab-889c-cd90fde961b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860857088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.2860857088
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.245465519
Short name T645
Test name
Test status
Simulation time 31089033 ps
CPU time 1.2 seconds
Started Jul 19 06:30:08 PM PDT 24
Finished Jul 19 06:30:17 PM PDT 24
Peak memory 217432 kb
Host smart-33d8ded1-163d-49cb-94f3-940ef2bcff5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245465519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.245465519
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.1823798289
Short name T359
Test name
Test status
Simulation time 62881073 ps
CPU time 1.48 seconds
Started Jul 19 06:30:11 PM PDT 24
Finished Jul 19 06:30:21 PM PDT 24
Peak memory 218652 kb
Host smart-c5d552b0-81d5-49b2-bb49-000e7abdb571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823798289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.1823798289
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.628473693
Short name T680
Test name
Test status
Simulation time 140459244 ps
CPU time 2.08 seconds
Started Jul 19 06:30:17 PM PDT 24
Finished Jul 19 06:30:25 PM PDT 24
Peak memory 220580 kb
Host smart-5bd18a18-30ad-4d99-a185-95168a3cbf2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628473693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.628473693
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.1100640624
Short name T810
Test name
Test status
Simulation time 50018420 ps
CPU time 1.31 seconds
Started Jul 19 06:30:11 PM PDT 24
Finished Jul 19 06:30:21 PM PDT 24
Peak memory 219220 kb
Host smart-5db92fda-0769-4912-b82b-7b9bcc043388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100640624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.1100640624
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.3950744655
Short name T802
Test name
Test status
Simulation time 57679824 ps
CPU time 1.46 seconds
Started Jul 19 06:30:12 PM PDT 24
Finished Jul 19 06:30:22 PM PDT 24
Peak memory 218992 kb
Host smart-b13e43e2-dc87-4dd3-b6b5-7de43b0e1b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950744655 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.3950744655
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.3774152391
Short name T442
Test name
Test status
Simulation time 77262607 ps
CPU time 2.87 seconds
Started Jul 19 06:30:17 PM PDT 24
Finished Jul 19 06:30:26 PM PDT 24
Peak memory 217820 kb
Host smart-1f3d31bb-301d-421c-9fe6-4120f2f4c86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774152391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.3774152391
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.1064952902
Short name T445
Test name
Test status
Simulation time 112682112 ps
CPU time 1.22 seconds
Started Jul 19 06:30:16 PM PDT 24
Finished Jul 19 06:30:23 PM PDT 24
Peak memory 217640 kb
Host smart-cdb066e0-7516-467f-b0af-6eb7a9da9345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064952902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.1064952902
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.1019114963
Short name T784
Test name
Test status
Simulation time 169305685 ps
CPU time 1.35 seconds
Started Jul 19 06:28:18 PM PDT 24
Finished Jul 19 06:28:20 PM PDT 24
Peak memory 220948 kb
Host smart-d3bafc3b-831c-493a-bc0a-ee7b20875233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019114963 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.1019114963
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.804506004
Short name T674
Test name
Test status
Simulation time 62162711 ps
CPU time 1.03 seconds
Started Jul 19 06:28:15 PM PDT 24
Finished Jul 19 06:28:17 PM PDT 24
Peak memory 207076 kb
Host smart-64efc8a7-9db1-4cae-8b85-6edb2763b589
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804506004 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.804506004
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.306813785
Short name T219
Test name
Test status
Simulation time 105231311 ps
CPU time 1.1 seconds
Started Jul 19 06:28:18 PM PDT 24
Finished Jul 19 06:28:20 PM PDT 24
Peak memory 217200 kb
Host smart-cbb50ad6-0c08-4623-a8a3-f256e169fa1c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306813785 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_di
sable_auto_req_mode.306813785
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_genbits.2082216870
Short name T9
Test name
Test status
Simulation time 650986033 ps
CPU time 6.26 seconds
Started Jul 19 06:28:06 PM PDT 24
Finished Jul 19 06:28:12 PM PDT 24
Peak memory 217676 kb
Host smart-d872aa67-98e5-4d94-ae8e-80c41e35e898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082216870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.2082216870
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.218243999
Short name T563
Test name
Test status
Simulation time 37226715 ps
CPU time 0.87 seconds
Started Jul 19 06:28:17 PM PDT 24
Finished Jul 19 06:28:18 PM PDT 24
Peak memory 215924 kb
Host smart-4c4f4a96-7389-45b9-86fb-943a43d43774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218243999 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.218243999
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.267401639
Short name T439
Test name
Test status
Simulation time 16981858 ps
CPU time 0.99 seconds
Started Jul 19 06:28:11 PM PDT 24
Finished Jul 19 06:28:13 PM PDT 24
Peak memory 215544 kb
Host smart-a72c92a4-ec9e-4415-9499-81b3746e255c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267401639 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.267401639
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.2260629708
Short name T727
Test name
Test status
Simulation time 533936920 ps
CPU time 3.27 seconds
Started Jul 19 06:28:08 PM PDT 24
Finished Jul 19 06:28:12 PM PDT 24
Peak memory 215564 kb
Host smart-45d7cce5-d812-465f-b256-56d82b0e2a65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260629708 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2260629708
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.2136503684
Short name T909
Test name
Test status
Simulation time 183252261933 ps
CPU time 1129.51 seconds
Started Jul 19 06:28:10 PM PDT 24
Finished Jul 19 06:47:00 PM PDT 24
Peak memory 223024 kb
Host smart-8e2594a6-1a39-4334-bfc0-799c9d7040c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136503684 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.2136503684
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.3373232501
Short name T958
Test name
Test status
Simulation time 46764457 ps
CPU time 1.19 seconds
Started Jul 19 06:30:11 PM PDT 24
Finished Jul 19 06:30:21 PM PDT 24
Peak memory 217676 kb
Host smart-0c25c9bb-56d4-41c7-a508-5b6a9371ce9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373232501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.3373232501
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.710942710
Short name T335
Test name
Test status
Simulation time 81860527 ps
CPU time 1.28 seconds
Started Jul 19 06:30:16 PM PDT 24
Finished Jul 19 06:30:24 PM PDT 24
Peak memory 220100 kb
Host smart-a79387a1-76dd-4df2-bd0a-d35996d677cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710942710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.710942710
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.3821636322
Short name T325
Test name
Test status
Simulation time 35871372 ps
CPU time 1.26 seconds
Started Jul 19 06:30:19 PM PDT 24
Finished Jul 19 06:30:25 PM PDT 24
Peak memory 217544 kb
Host smart-2e861247-991c-44b7-98fe-aeaa0c8379ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821636322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.3821636322
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.628049006
Short name T452
Test name
Test status
Simulation time 32845167 ps
CPU time 1.34 seconds
Started Jul 19 06:30:21 PM PDT 24
Finished Jul 19 06:30:25 PM PDT 24
Peak memory 217744 kb
Host smart-578779e8-1f34-473e-a9a8-b78aae6ee6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628049006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.628049006
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.3672541636
Short name T385
Test name
Test status
Simulation time 35605986 ps
CPU time 1.32 seconds
Started Jul 19 06:30:12 PM PDT 24
Finished Jul 19 06:30:22 PM PDT 24
Peak memory 218764 kb
Host smart-1deba72a-dc48-41d8-b3fe-5339557a15fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672541636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3672541636
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.1254153085
Short name T469
Test name
Test status
Simulation time 204757656 ps
CPU time 1.09 seconds
Started Jul 19 06:30:15 PM PDT 24
Finished Jul 19 06:30:23 PM PDT 24
Peak memory 217696 kb
Host smart-455b50a5-ce03-43f3-a5c6-c75813f821c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254153085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.1254153085
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.2821906827
Short name T642
Test name
Test status
Simulation time 48765347 ps
CPU time 1.51 seconds
Started Jul 19 06:30:14 PM PDT 24
Finished Jul 19 06:30:23 PM PDT 24
Peak memory 218544 kb
Host smart-c0af6677-d476-45c4-8e6e-c1f0f639d7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821906827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.2821906827
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.1398910240
Short name T842
Test name
Test status
Simulation time 43428855 ps
CPU time 1.17 seconds
Started Jul 19 06:30:12 PM PDT 24
Finished Jul 19 06:30:21 PM PDT 24
Peak memory 217536 kb
Host smart-c6426734-af72-4bd4-91b3-d2c4d5c91747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398910240 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.1398910240
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.1501609574
Short name T283
Test name
Test status
Simulation time 27303088 ps
CPU time 1.2 seconds
Started Jul 19 06:30:12 PM PDT 24
Finished Jul 19 06:30:22 PM PDT 24
Peak memory 218596 kb
Host smart-34f8d7b2-c499-4514-9206-98863f8ef026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501609574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.1501609574
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.2328495764
Short name T961
Test name
Test status
Simulation time 24085217 ps
CPU time 1.15 seconds
Started Jul 19 06:28:25 PM PDT 24
Finished Jul 19 06:28:28 PM PDT 24
Peak memory 218732 kb
Host smart-751f086d-2397-446c-8c30-749371f00f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328495764 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2328495764
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.3043406668
Short name T649
Test name
Test status
Simulation time 13663762 ps
CPU time 0.95 seconds
Started Jul 19 06:28:17 PM PDT 24
Finished Jul 19 06:28:19 PM PDT 24
Peak memory 215212 kb
Host smart-5bb98038-144f-4584-956d-0123bf3f6cbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043406668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3043406668
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.3904850294
Short name T661
Test name
Test status
Simulation time 13928201 ps
CPU time 0.92 seconds
Started Jul 19 06:28:16 PM PDT 24
Finished Jul 19 06:28:17 PM PDT 24
Peak memory 215868 kb
Host smart-6e05786f-f7a6-4b8c-8c85-0157fc75337b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904850294 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.3904850294
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_err.3243575738
Short name T212
Test name
Test status
Simulation time 28336064 ps
CPU time 1.19 seconds
Started Jul 19 06:28:16 PM PDT 24
Finished Jul 19 06:28:17 PM PDT 24
Peak memory 215824 kb
Host smart-7bde784b-8f95-4b2c-8a94-dfb60100261f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243575738 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.3243575738
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.3150648246
Short name T336
Test name
Test status
Simulation time 37319869 ps
CPU time 1.49 seconds
Started Jul 19 06:28:19 PM PDT 24
Finished Jul 19 06:28:21 PM PDT 24
Peak memory 217444 kb
Host smart-569e8e11-5e2e-4cf2-9752-1c3d1ca7ae0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150648246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3150648246
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.2040067167
Short name T534
Test name
Test status
Simulation time 32674016 ps
CPU time 0.87 seconds
Started Jul 19 06:28:17 PM PDT 24
Finished Jul 19 06:28:19 PM PDT 24
Peak memory 215680 kb
Host smart-5136a0f4-1c63-43cc-8c35-ee8f64b98eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040067167 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.2040067167
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.2857149043
Short name T353
Test name
Test status
Simulation time 57926454 ps
CPU time 0.96 seconds
Started Jul 19 06:28:16 PM PDT 24
Finished Jul 19 06:28:18 PM PDT 24
Peak memory 215692 kb
Host smart-680ab993-4206-407f-9335-62015ae35939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857149043 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.2857149043
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.2737772522
Short name T946
Test name
Test status
Simulation time 281329544 ps
CPU time 2 seconds
Started Jul 19 06:28:16 PM PDT 24
Finished Jul 19 06:28:19 PM PDT 24
Peak memory 220124 kb
Host smart-d208b1a6-77cf-49b7-ad34-f9d88d1c5113
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737772522 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2737772522
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.1172263731
Short name T704
Test name
Test status
Simulation time 84740182772 ps
CPU time 1069.45 seconds
Started Jul 19 06:28:17 PM PDT 24
Finished Jul 19 06:46:08 PM PDT 24
Peak memory 223972 kb
Host smart-30cb4765-f1cb-4185-a459-b39eb9676693
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172263731 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.1172263731
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.1849602328
Short name T504
Test name
Test status
Simulation time 149819818 ps
CPU time 2.49 seconds
Started Jul 19 06:30:12 PM PDT 24
Finished Jul 19 06:30:23 PM PDT 24
Peak memory 220364 kb
Host smart-dbcbe270-8b8e-408d-9c22-a41bdd2a8df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849602328 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.1849602328
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.772144228
Short name T513
Test name
Test status
Simulation time 67281698 ps
CPU time 1.63 seconds
Started Jul 19 06:30:15 PM PDT 24
Finished Jul 19 06:30:24 PM PDT 24
Peak memory 218808 kb
Host smart-db9fb53c-127f-4910-bb34-402780d0fa18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772144228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.772144228
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.1432417493
Short name T825
Test name
Test status
Simulation time 51141959 ps
CPU time 1.27 seconds
Started Jul 19 06:30:16 PM PDT 24
Finished Jul 19 06:30:24 PM PDT 24
Peak memory 220324 kb
Host smart-6f6ddad7-d50a-4f8b-91ca-235d7be4f099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432417493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.1432417493
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.582064065
Short name T429
Test name
Test status
Simulation time 45633858 ps
CPU time 1.76 seconds
Started Jul 19 06:30:11 PM PDT 24
Finished Jul 19 06:30:22 PM PDT 24
Peak memory 217472 kb
Host smart-91e9ae43-1de1-4880-ba5b-345d40095cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582064065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.582064065
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.2602323581
Short name T851
Test name
Test status
Simulation time 37822147 ps
CPU time 1.41 seconds
Started Jul 19 06:30:12 PM PDT 24
Finished Jul 19 06:30:22 PM PDT 24
Peak memory 217644 kb
Host smart-dafeb0fe-947f-4475-96dc-fc7a46841d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602323581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2602323581
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.651163603
Short name T910
Test name
Test status
Simulation time 125514258 ps
CPU time 1.18 seconds
Started Jul 19 06:30:14 PM PDT 24
Finished Jul 19 06:30:23 PM PDT 24
Peak memory 217552 kb
Host smart-fd1f6b6d-849f-4a8a-9257-c9ec31a522c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651163603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.651163603
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.704333022
Short name T476
Test name
Test status
Simulation time 53662968 ps
CPU time 2.03 seconds
Started Jul 19 06:30:13 PM PDT 24
Finished Jul 19 06:30:23 PM PDT 24
Peak memory 220384 kb
Host smart-d3f554fc-ae37-4cee-887f-95ce99f34719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704333022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.704333022
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.1781953417
Short name T826
Test name
Test status
Simulation time 34779629 ps
CPU time 1.46 seconds
Started Jul 19 06:30:14 PM PDT 24
Finished Jul 19 06:30:23 PM PDT 24
Peak memory 218884 kb
Host smart-255fc14f-77bf-49a4-8cab-89a5d23b960c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781953417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.1781953417
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.3695449334
Short name T483
Test name
Test status
Simulation time 51999155 ps
CPU time 1.88 seconds
Started Jul 19 06:30:18 PM PDT 24
Finished Jul 19 06:30:25 PM PDT 24
Peak memory 218712 kb
Host smart-acde99d2-4d22-449b-972a-19717adaf214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695449334 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3695449334
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.184222104
Short name T75
Test name
Test status
Simulation time 39868338 ps
CPU time 1.32 seconds
Started Jul 19 06:30:12 PM PDT 24
Finished Jul 19 06:30:22 PM PDT 24
Peak memory 218712 kb
Host smart-9decde4f-03f7-4654-8c80-b7a4ff586a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184222104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.184222104
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert_test.2878005890
Short name T862
Test name
Test status
Simulation time 15640353 ps
CPU time 0.95 seconds
Started Jul 19 06:28:16 PM PDT 24
Finished Jul 19 06:28:18 PM PDT 24
Peak memory 207084 kb
Host smart-affe68c5-1898-4f4d-9be3-191d3be2b99d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878005890 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.2878005890
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.3897594884
Short name T685
Test name
Test status
Simulation time 12469690 ps
CPU time 0.92 seconds
Started Jul 19 06:28:15 PM PDT 24
Finished Jul 19 06:28:16 PM PDT 24
Peak memory 207656 kb
Host smart-3e120f35-4188-44f6-acb3-cfd04c9f6459
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897594884 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.3897594884
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.1348283645
Short name T460
Test name
Test status
Simulation time 107141054 ps
CPU time 1.08 seconds
Started Jul 19 06:28:25 PM PDT 24
Finished Jul 19 06:28:28 PM PDT 24
Peak memory 217296 kb
Host smart-cb34f9b8-a15f-4507-8942-de975df016e1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348283645 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.1348283645
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.2631614513
Short name T179
Test name
Test status
Simulation time 73146648 ps
CPU time 1.14 seconds
Started Jul 19 06:28:15 PM PDT 24
Finished Jul 19 06:28:17 PM PDT 24
Peak memory 220036 kb
Host smart-af312e22-c2ed-4507-965f-4df51024abba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631614513 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2631614513
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.1635762290
Short name T538
Test name
Test status
Simulation time 60728473 ps
CPU time 1.33 seconds
Started Jul 19 06:28:15 PM PDT 24
Finished Jul 19 06:28:16 PM PDT 24
Peak memory 217524 kb
Host smart-4c94a8be-5594-46e6-98f5-cd0a4367278f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635762290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.1635762290
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.98689646
Short name T838
Test name
Test status
Simulation time 28703898 ps
CPU time 1.09 seconds
Started Jul 19 06:28:16 PM PDT 24
Finished Jul 19 06:28:18 PM PDT 24
Peak memory 224344 kb
Host smart-c36d41d8-49b3-4c03-b0b7-5cb5c4720dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98689646 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.98689646
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.3320178180
Short name T927
Test name
Test status
Simulation time 18185432 ps
CPU time 0.95 seconds
Started Jul 19 06:28:18 PM PDT 24
Finished Jul 19 06:28:20 PM PDT 24
Peak memory 215556 kb
Host smart-d30edd76-9e65-4b25-94a5-ea4964c2432e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320178180 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.3320178180
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.3692040506
Short name T683
Test name
Test status
Simulation time 237649567 ps
CPU time 1.78 seconds
Started Jul 19 06:28:15 PM PDT 24
Finished Jul 19 06:28:17 PM PDT 24
Peak memory 215548 kb
Host smart-1d81e832-0afb-4d75-b495-01abb8dd8d4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692040506 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.3692040506
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.1962791677
Short name T509
Test name
Test status
Simulation time 86064994735 ps
CPU time 2285.09 seconds
Started Jul 19 06:28:18 PM PDT 24
Finished Jul 19 07:06:24 PM PDT 24
Peak memory 230776 kb
Host smart-a24d5c73-8c90-4256-b1c3-a4691b1c6fa9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962791677 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.1962791677
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.698810133
Short name T326
Test name
Test status
Simulation time 100717954 ps
CPU time 1.61 seconds
Started Jul 19 06:30:15 PM PDT 24
Finished Jul 19 06:30:23 PM PDT 24
Peak memory 219148 kb
Host smart-c62c9983-8f70-4146-9db9-76465c589ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698810133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.698810133
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.1922446438
Short name T366
Test name
Test status
Simulation time 50223738 ps
CPU time 1.36 seconds
Started Jul 19 06:30:10 PM PDT 24
Finished Jul 19 06:30:21 PM PDT 24
Peak memory 217932 kb
Host smart-03f843bb-595d-4534-bf60-332a6203b198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922446438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.1922446438
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.332368775
Short name T378
Test name
Test status
Simulation time 61643852 ps
CPU time 1.33 seconds
Started Jul 19 06:30:15 PM PDT 24
Finished Jul 19 06:30:23 PM PDT 24
Peak memory 217700 kb
Host smart-3dd05f1e-d21e-4e5c-b258-a6fc144a5f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332368775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.332368775
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2561850488
Short name T355
Test name
Test status
Simulation time 42546808 ps
CPU time 1.38 seconds
Started Jul 19 06:30:13 PM PDT 24
Finished Jul 19 06:30:22 PM PDT 24
Peak memory 218620 kb
Host smart-5c78cb08-9cff-4eb1-9648-1b98825ec1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561850488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2561850488
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.1980697408
Short name T372
Test name
Test status
Simulation time 82674204 ps
CPU time 1.1 seconds
Started Jul 19 06:30:18 PM PDT 24
Finished Jul 19 06:30:24 PM PDT 24
Peak memory 217548 kb
Host smart-5e775df1-f037-47f1-b776-faae4ad6eee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980697408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.1980697408
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.1695951951
Short name T687
Test name
Test status
Simulation time 29743879 ps
CPU time 1.04 seconds
Started Jul 19 06:30:12 PM PDT 24
Finished Jul 19 06:30:22 PM PDT 24
Peak memory 215560 kb
Host smart-3f52219d-56aa-48a4-8e5b-e96105cd4c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695951951 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.1695951951
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3633389685
Short name T459
Test name
Test status
Simulation time 111033361 ps
CPU time 2.43 seconds
Started Jul 19 06:30:14 PM PDT 24
Finished Jul 19 06:30:24 PM PDT 24
Peak memory 217848 kb
Host smart-d0f3fab9-21af-4f10-95b0-d352f5b386f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633389685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3633389685
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.391055909
Short name T365
Test name
Test status
Simulation time 269009039 ps
CPU time 1.88 seconds
Started Jul 19 06:30:11 PM PDT 24
Finished Jul 19 06:30:21 PM PDT 24
Peak memory 219316 kb
Host smart-9ee30cd9-ec6c-46e4-b8a9-48bbe36023d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391055909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.391055909
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.1763038628
Short name T597
Test name
Test status
Simulation time 91487187 ps
CPU time 1.43 seconds
Started Jul 19 06:30:11 PM PDT 24
Finished Jul 19 06:30:21 PM PDT 24
Peak memory 219084 kb
Host smart-1b1f16c8-31e1-473e-9765-61f1701256c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763038628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.1763038628
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.3229960346
Short name T957
Test name
Test status
Simulation time 33924997 ps
CPU time 1.08 seconds
Started Jul 19 06:27:11 PM PDT 24
Finished Jul 19 06:27:13 PM PDT 24
Peak memory 218916 kb
Host smart-380c7892-4c28-4fc5-80b9-151ccb8e1973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229960346 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.3229960346
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.2503060289
Short name T752
Test name
Test status
Simulation time 19085234 ps
CPU time 0.97 seconds
Started Jul 19 06:27:09 PM PDT 24
Finished Jul 19 06:27:11 PM PDT 24
Peak memory 207012 kb
Host smart-9a6ad1b1-1fa1-4271-af31-ac8c7b2b5088
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503060289 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2503060289
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.2302778950
Short name T783
Test name
Test status
Simulation time 32374746 ps
CPU time 0.86 seconds
Started Jul 19 06:27:13 PM PDT 24
Finished Jul 19 06:27:15 PM PDT 24
Peak memory 216500 kb
Host smart-b39b656c-f215-48c8-8bf3-c9a4c23f187c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302778950 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.2302778950
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.2750754096
Short name T614
Test name
Test status
Simulation time 147976407 ps
CPU time 1.11 seconds
Started Jul 19 06:27:08 PM PDT 24
Finished Jul 19 06:27:10 PM PDT 24
Peak memory 218756 kb
Host smart-53e0ae25-feef-4b48-b933-2f462151d68e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750754096 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.2750754096
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.3714894785
Short name T562
Test name
Test status
Simulation time 19458637 ps
CPU time 1.15 seconds
Started Jul 19 06:27:11 PM PDT 24
Finished Jul 19 06:27:13 PM PDT 24
Peak memory 218680 kb
Host smart-f602d5fc-f799-4147-8b09-f5692844ea9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714894785 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.3714894785
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.1545849368
Short name T282
Test name
Test status
Simulation time 95207581 ps
CPU time 1.36 seconds
Started Jul 19 06:27:10 PM PDT 24
Finished Jul 19 06:27:12 PM PDT 24
Peak memory 219440 kb
Host smart-a279fe58-6284-48bb-9b69-2ff8b02485d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545849368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1545849368
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_regwen.1252442052
Short name T921
Test name
Test status
Simulation time 100850859 ps
CPU time 0.9 seconds
Started Jul 19 06:27:12 PM PDT 24
Finished Jul 19 06:27:13 PM PDT 24
Peak memory 207368 kb
Host smart-2e63d60a-2b82-409a-8402-2785715b9870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252442052 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1252442052
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.3063884885
Short name T62
Test name
Test status
Simulation time 580774400 ps
CPU time 7.17 seconds
Started Jul 19 06:27:08 PM PDT 24
Finished Jul 19 06:27:16 PM PDT 24
Peak memory 236696 kb
Host smart-ac4c8bd7-5443-44a4-bc94-14f47a605ea0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063884885 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.3063884885
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.859559148
Short name T57
Test name
Test status
Simulation time 34596658 ps
CPU time 0.97 seconds
Started Jul 19 06:27:07 PM PDT 24
Finished Jul 19 06:27:08 PM PDT 24
Peak memory 215552 kb
Host smart-7d272b8b-1f1d-456b-bebc-ac59aa5b094c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859559148 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.859559148
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.2275698812
Short name T951
Test name
Test status
Simulation time 67523118 ps
CPU time 1.88 seconds
Started Jul 19 06:27:06 PM PDT 24
Finished Jul 19 06:27:08 PM PDT 24
Peak memory 215580 kb
Host smart-4a490338-16f9-485c-a747-7aa9fe257e51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275698812 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2275698812
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.975636617
Short name T747
Test name
Test status
Simulation time 148749539572 ps
CPU time 1023.91 seconds
Started Jul 19 06:27:09 PM PDT 24
Finished Jul 19 06:44:13 PM PDT 24
Peak memory 224240 kb
Host smart-f6754ae4-25d3-4bb1-93c0-266f2c1458eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975636617 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.975636617
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.1512910911
Short name T202
Test name
Test status
Simulation time 74673764 ps
CPU time 1.19 seconds
Started Jul 19 06:28:16 PM PDT 24
Finished Jul 19 06:28:18 PM PDT 24
Peak memory 220320 kb
Host smart-4f3d099b-ff7c-4a07-8276-92b8eb507253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512910911 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1512910911
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.3689335089
Short name T760
Test name
Test status
Simulation time 52937816 ps
CPU time 0.85 seconds
Started Jul 19 06:28:23 PM PDT 24
Finished Jul 19 06:28:25 PM PDT 24
Peak memory 215052 kb
Host smart-034d0ecf-0910-435c-a13c-4882e26017c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689335089 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3689335089
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.4250351368
Short name T912
Test name
Test status
Simulation time 125846351 ps
CPU time 0.99 seconds
Started Jul 19 06:28:26 PM PDT 24
Finished Jul 19 06:28:29 PM PDT 24
Peak memory 218564 kb
Host smart-f5d68006-87dd-427b-be5e-509881b09f96
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250351368 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.4250351368
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.1995864863
Short name T666
Test name
Test status
Simulation time 54808290 ps
CPU time 1.09 seconds
Started Jul 19 06:28:25 PM PDT 24
Finished Jul 19 06:28:28 PM PDT 24
Peak memory 220080 kb
Host smart-2d7beaab-40d3-4168-8537-03896c8cf608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995864863 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.1995864863
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.1737344869
Short name T662
Test name
Test status
Simulation time 38629217 ps
CPU time 1.45 seconds
Started Jul 19 06:28:16 PM PDT 24
Finished Jul 19 06:28:19 PM PDT 24
Peak memory 215556 kb
Host smart-82a7e71d-1c6a-487a-99d0-cee958490fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737344869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1737344869
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.2160268569
Short name T66
Test name
Test status
Simulation time 38085982 ps
CPU time 1 seconds
Started Jul 19 06:28:18 PM PDT 24
Finished Jul 19 06:28:21 PM PDT 24
Peak memory 224144 kb
Host smart-fa5bb45b-0418-496b-be78-1e6c5f76a8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160268569 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2160268569
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.2629403353
Short name T763
Test name
Test status
Simulation time 52609189 ps
CPU time 0.96 seconds
Started Jul 19 06:28:18 PM PDT 24
Finished Jul 19 06:28:20 PM PDT 24
Peak memory 215708 kb
Host smart-c1e35b13-1ad4-4e29-9975-fb6d08cc3849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629403353 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.2629403353
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.2037960423
Short name T882
Test name
Test status
Simulation time 1027155609 ps
CPU time 4.95 seconds
Started Jul 19 06:28:25 PM PDT 24
Finished Jul 19 06:28:32 PM PDT 24
Peak memory 217416 kb
Host smart-144ff9e5-8f52-467a-8245-d0bed1ede796
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037960423 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.2037960423
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.528044511
Short name T762
Test name
Test status
Simulation time 14180788400 ps
CPU time 292.84 seconds
Started Jul 19 06:28:25 PM PDT 24
Finished Jul 19 06:33:20 PM PDT 24
Peak memory 221076 kb
Host smart-a0c89bd9-80b2-4e26-acad-75be2f4cc730
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528044511 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.528044511
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.4193565138
Short name T141
Test name
Test status
Simulation time 46939273 ps
CPU time 1.17 seconds
Started Jul 19 06:28:24 PM PDT 24
Finished Jul 19 06:28:27 PM PDT 24
Peak memory 219744 kb
Host smart-6d9e5eb6-eb24-4b9e-8fb4-59f7ebfbcad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193565138 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.4193565138
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.1506780529
Short name T414
Test name
Test status
Simulation time 15699439 ps
CPU time 0.94 seconds
Started Jul 19 06:28:24 PM PDT 24
Finished Jul 19 06:28:27 PM PDT 24
Peak memory 207040 kb
Host smart-e7b7fe94-28dd-4d31-a928-8f2e89a55f1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506780529 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.1506780529
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.2201735506
Short name T220
Test name
Test status
Simulation time 21514673 ps
CPU time 0.87 seconds
Started Jul 19 06:28:22 PM PDT 24
Finished Jul 19 06:28:24 PM PDT 24
Peak memory 216516 kb
Host smart-99997bf7-8ac9-42ed-b0e2-32bbb6add446
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201735506 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2201735506
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.1880428040
Short name T147
Test name
Test status
Simulation time 488222783 ps
CPU time 1.38 seconds
Started Jul 19 06:28:21 PM PDT 24
Finished Jul 19 06:28:23 PM PDT 24
Peak memory 215804 kb
Host smart-70c5a48e-4247-41b0-b865-2d165b854fda
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880428040 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.1880428040
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.3670659223
Short name T221
Test name
Test status
Simulation time 75904654 ps
CPU time 1.11 seconds
Started Jul 19 06:28:23 PM PDT 24
Finished Jul 19 06:28:26 PM PDT 24
Peak memory 219948 kb
Host smart-3e42231b-347b-43ab-945e-a04b2cf1cf93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670659223 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.3670659223
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.2391709098
Short name T342
Test name
Test status
Simulation time 78470104 ps
CPU time 1.56 seconds
Started Jul 19 06:28:22 PM PDT 24
Finished Jul 19 06:28:24 PM PDT 24
Peak memory 219012 kb
Host smart-60f71550-16c8-4473-90e2-012a62d16353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391709098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.2391709098
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.3395574336
Short name T101
Test name
Test status
Simulation time 20274573 ps
CPU time 1.06 seconds
Started Jul 19 06:28:23 PM PDT 24
Finished Jul 19 06:28:26 PM PDT 24
Peak memory 216108 kb
Host smart-bc102dfe-3435-4852-9003-9a10f3cf8edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395574336 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.3395574336
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.2916704263
Short name T798
Test name
Test status
Simulation time 24682203 ps
CPU time 0.99 seconds
Started Jul 19 06:28:24 PM PDT 24
Finished Jul 19 06:28:27 PM PDT 24
Peak memory 215548 kb
Host smart-74f7650e-cc57-42c4-81a4-dd107a364796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916704263 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.2916704263
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.3131987335
Short name T446
Test name
Test status
Simulation time 337993161 ps
CPU time 6.24 seconds
Started Jul 19 06:28:22 PM PDT 24
Finished Jul 19 06:28:29 PM PDT 24
Peak memory 217472 kb
Host smart-f1fdc027-a595-406f-9287-a56d1b32cbfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131987335 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.3131987335
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.2576316673
Short name T737
Test name
Test status
Simulation time 212693557481 ps
CPU time 762.02 seconds
Started Jul 19 06:28:26 PM PDT 24
Finished Jul 19 06:41:10 PM PDT 24
Peak memory 220392 kb
Host smart-6bb2ab59-08b3-488a-ae68-4914609b5c0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576316673 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.2576316673
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.688427547
Short name T110
Test name
Test status
Simulation time 92269039 ps
CPU time 1.19 seconds
Started Jul 19 06:28:25 PM PDT 24
Finished Jul 19 06:28:28 PM PDT 24
Peak memory 220040 kb
Host smart-f3145c26-fef0-483f-903e-f3a2df372a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688427547 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.688427547
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.139357762
Short name T560
Test name
Test status
Simulation time 17499280 ps
CPU time 0.79 seconds
Started Jul 19 06:28:25 PM PDT 24
Finished Jul 19 06:28:28 PM PDT 24
Peak memory 206796 kb
Host smart-8dec50a0-80e2-434b-871a-9ae9fcb0ee2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139357762 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.139357762
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.3879620104
Short name T189
Test name
Test status
Simulation time 10777098 ps
CPU time 0.88 seconds
Started Jul 19 06:28:23 PM PDT 24
Finished Jul 19 06:28:25 PM PDT 24
Peak memory 216588 kb
Host smart-66e9c289-424d-4250-acab-40c6a3adadf8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879620104 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3879620104
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_err.2860323718
Short name T146
Test name
Test status
Simulation time 61079531 ps
CPU time 1.21 seconds
Started Jul 19 06:28:23 PM PDT 24
Finished Jul 19 06:28:26 PM PDT 24
Peak memory 230044 kb
Host smart-3c364781-7645-4ee3-856b-a65234622f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860323718 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.2860323718
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.2958356207
Short name T298
Test name
Test status
Simulation time 51459773 ps
CPU time 1.4 seconds
Started Jul 19 06:28:23 PM PDT 24
Finished Jul 19 06:28:26 PM PDT 24
Peak memory 219968 kb
Host smart-d963d548-5bf6-4e35-afd0-673a99f80c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958356207 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2958356207
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.1681270132
Short name T370
Test name
Test status
Simulation time 84771121 ps
CPU time 0.79 seconds
Started Jul 19 06:28:25 PM PDT 24
Finished Jul 19 06:28:27 PM PDT 24
Peak memory 215668 kb
Host smart-21c8a96c-0aef-4efc-87b9-f3cb1c3c132d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681270132 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.1681270132
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.1475102007
Short name T938
Test name
Test status
Simulation time 47150094 ps
CPU time 0.92 seconds
Started Jul 19 06:28:27 PM PDT 24
Finished Jul 19 06:28:29 PM PDT 24
Peak memory 207356 kb
Host smart-2dd347c5-e486-46af-a5db-4a62c705f0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475102007 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.1475102007
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.885273917
Short name T248
Test name
Test status
Simulation time 265840834 ps
CPU time 5.07 seconds
Started Jul 19 06:28:23 PM PDT 24
Finished Jul 19 06:28:29 PM PDT 24
Peak memory 217448 kb
Host smart-309dc4da-5091-4959-98f3-95013338ecb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885273917 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.885273917
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1723896958
Short name T956
Test name
Test status
Simulation time 7012740682 ps
CPU time 156.88 seconds
Started Jul 19 06:28:24 PM PDT 24
Finished Jul 19 06:31:03 PM PDT 24
Peak memory 222088 kb
Host smart-63274165-8c83-45ee-9650-591224756030
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723896958 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1723896958
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.3421952234
Short name T777
Test name
Test status
Simulation time 27200709 ps
CPU time 1.26 seconds
Started Jul 19 06:28:22 PM PDT 24
Finished Jul 19 06:28:24 PM PDT 24
Peak memory 220140 kb
Host smart-ead19480-0464-4219-9624-8989a05a78fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421952234 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3421952234
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.1260547966
Short name T118
Test name
Test status
Simulation time 42798119 ps
CPU time 0.88 seconds
Started Jul 19 06:28:24 PM PDT 24
Finished Jul 19 06:28:27 PM PDT 24
Peak memory 207000 kb
Host smart-787e7476-01cf-4207-b37d-27f1bd83898f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260547966 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.1260547966
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.4177239985
Short name T555
Test name
Test status
Simulation time 41545512 ps
CPU time 0.88 seconds
Started Jul 19 06:28:24 PM PDT 24
Finished Jul 19 06:28:27 PM PDT 24
Peak memory 215628 kb
Host smart-e641be7c-37f2-4171-9f9c-3a2ea706a752
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177239985 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.4177239985
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.3651304729
Short name T85
Test name
Test status
Simulation time 30914973 ps
CPU time 1.13 seconds
Started Jul 19 06:28:27 PM PDT 24
Finished Jul 19 06:28:29 PM PDT 24
Peak memory 217236 kb
Host smart-d301b322-3880-445a-a991-21a652dbe976
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651304729 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.3651304729
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.2258277968
Short name T187
Test name
Test status
Simulation time 108930525 ps
CPU time 0.92 seconds
Started Jul 19 06:28:24 PM PDT 24
Finished Jul 19 06:28:27 PM PDT 24
Peak memory 218620 kb
Host smart-663aaf21-b7c4-411a-8f91-c498ec091d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258277968 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.2258277968
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.1657841590
Short name T915
Test name
Test status
Simulation time 53093297 ps
CPU time 1.17 seconds
Started Jul 19 06:28:24 PM PDT 24
Finished Jul 19 06:28:28 PM PDT 24
Peak memory 217712 kb
Host smart-85409b3a-3799-477a-8062-e56fd7f1fabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657841590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.1657841590
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.1593438298
Short name T718
Test name
Test status
Simulation time 28388808 ps
CPU time 1.1 seconds
Started Jul 19 06:28:23 PM PDT 24
Finished Jul 19 06:28:25 PM PDT 24
Peak memory 224312 kb
Host smart-dbe67aa8-9f8e-4792-a952-f11a92815b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593438298 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.1593438298
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.2731958676
Short name T577
Test name
Test status
Simulation time 19236367 ps
CPU time 1.04 seconds
Started Jul 19 06:28:24 PM PDT 24
Finished Jul 19 06:28:26 PM PDT 24
Peak memory 215548 kb
Host smart-e1cac7b4-7c87-438b-b1ce-93ad112cf84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731958676 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.2731958676
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.283656552
Short name T886
Test name
Test status
Simulation time 428607445 ps
CPU time 7.81 seconds
Started Jul 19 06:28:24 PM PDT 24
Finished Jul 19 06:28:34 PM PDT 24
Peak memory 218728 kb
Host smart-7f5cce2d-fd37-4c15-9d35-3c68b74346c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283656552 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.283656552
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.968319044
Short name T243
Test name
Test status
Simulation time 341509145482 ps
CPU time 866.86 seconds
Started Jul 19 06:28:32 PM PDT 24
Finished Jul 19 06:43:01 PM PDT 24
Peak memory 221644 kb
Host smart-5d4cdf9e-6f6f-4b9c-8244-248d568f4643
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968319044 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.968319044
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.23422985
Short name T153
Test name
Test status
Simulation time 218175892 ps
CPU time 1.22 seconds
Started Jul 19 06:28:30 PM PDT 24
Finished Jul 19 06:28:33 PM PDT 24
Peak memory 218840 kb
Host smart-aa766fcd-480d-4af8-9b64-3190d704c659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23422985 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.23422985
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.3006155058
Short name T790
Test name
Test status
Simulation time 24098856 ps
CPU time 1.07 seconds
Started Jul 19 06:28:30 PM PDT 24
Finished Jul 19 06:28:32 PM PDT 24
Peak memory 207048 kb
Host smart-dcc8b68a-bf96-4148-904b-963b701c4456
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006155058 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.3006155058
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.718626146
Short name T64
Test name
Test status
Simulation time 31549847 ps
CPU time 0.81 seconds
Started Jul 19 06:28:29 PM PDT 24
Finished Jul 19 06:28:32 PM PDT 24
Peak memory 216624 kb
Host smart-869d93de-743d-4d1b-97ad-01e9aa21cebd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718626146 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.718626146
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2692437214
Short name T165
Test name
Test status
Simulation time 41096537 ps
CPU time 1.23 seconds
Started Jul 19 06:28:33 PM PDT 24
Finished Jul 19 06:28:36 PM PDT 24
Peak memory 217132 kb
Host smart-e57cf56b-44d2-4346-977b-3a501391219b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692437214 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2692437214
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.4084520963
Short name T162
Test name
Test status
Simulation time 26865315 ps
CPU time 1.28 seconds
Started Jul 19 06:28:33 PM PDT 24
Finished Jul 19 06:28:36 PM PDT 24
Peak memory 217780 kb
Host smart-0b86f433-0066-414d-ac06-3fa3fd760a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084520963 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.4084520963
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.4280818152
Short name T432
Test name
Test status
Simulation time 110159587 ps
CPU time 1.46 seconds
Started Jul 19 06:28:23 PM PDT 24
Finished Jul 19 06:28:25 PM PDT 24
Peak memory 220580 kb
Host smart-d38b2947-00f6-4c72-af89-24a830bda87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280818152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.4280818152
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.235036084
Short name T50
Test name
Test status
Simulation time 22034615 ps
CPU time 1.18 seconds
Started Jul 19 06:28:31 PM PDT 24
Finished Jul 19 06:28:34 PM PDT 24
Peak memory 224288 kb
Host smart-7681c70f-3ac7-4629-8d6f-65f5b9689608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235036084 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.235036084
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.338828188
Short name T356
Test name
Test status
Simulation time 29094003 ps
CPU time 1.02 seconds
Started Jul 19 06:28:24 PM PDT 24
Finished Jul 19 06:28:27 PM PDT 24
Peak memory 215556 kb
Host smart-64c53fd2-2eb4-4d53-82bf-b87baf3f212a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338828188 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.338828188
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.546658817
Short name T740
Test name
Test status
Simulation time 419062465 ps
CPU time 2.54 seconds
Started Jul 19 06:28:29 PM PDT 24
Finished Jul 19 06:28:33 PM PDT 24
Peak memory 217644 kb
Host smart-b225582e-c534-4555-97ba-44c1a02e71c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546658817 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.546658817
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.3503770072
Short name T238
Test name
Test status
Simulation time 68585128363 ps
CPU time 1889.95 seconds
Started Jul 19 06:28:33 PM PDT 24
Finished Jul 19 07:00:05 PM PDT 24
Peak memory 227180 kb
Host smart-ad2f27e2-f28f-41ac-8988-23c99fa34e52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503770072 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.3503770072
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.2601672526
Short name T22
Test name
Test status
Simulation time 72055537 ps
CPU time 1.18 seconds
Started Jul 19 06:28:33 PM PDT 24
Finished Jul 19 06:28:35 PM PDT 24
Peak memory 220048 kb
Host smart-0716caf3-4c3f-4565-ae35-33004473503c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601672526 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.2601672526
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.645533857
Short name T482
Test name
Test status
Simulation time 26565693 ps
CPU time 0.97 seconds
Started Jul 19 06:28:32 PM PDT 24
Finished Jul 19 06:28:35 PM PDT 24
Peak memory 215228 kb
Host smart-7d261a00-f768-4866-9605-86bb19760a01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645533857 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.645533857
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.3554311667
Short name T960
Test name
Test status
Simulation time 79249315 ps
CPU time 1.3 seconds
Started Jul 19 06:28:32 PM PDT 24
Finished Jul 19 06:28:34 PM PDT 24
Peak memory 217028 kb
Host smart-39eb0264-b373-4dcd-b02c-72559796b2ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554311667 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.3554311667
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.1902218296
Short name T180
Test name
Test status
Simulation time 30045477 ps
CPU time 1.22 seconds
Started Jul 19 06:28:30 PM PDT 24
Finished Jul 19 06:28:33 PM PDT 24
Peak memory 219816 kb
Host smart-672b1efa-9996-411d-bd8a-b887e1429f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902218296 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.1902218296
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.1365781742
Short name T249
Test name
Test status
Simulation time 236246826 ps
CPU time 2.93 seconds
Started Jul 19 06:28:33 PM PDT 24
Finished Jul 19 06:28:37 PM PDT 24
Peak memory 220104 kb
Host smart-02d99497-1593-446b-8d63-56f59dd23f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365781742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.1365781742
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.488734374
Short name T843
Test name
Test status
Simulation time 25754499 ps
CPU time 1.01 seconds
Started Jul 19 06:28:32 PM PDT 24
Finished Jul 19 06:28:34 PM PDT 24
Peak memory 215836 kb
Host smart-eec3d5fd-4323-456e-a35f-113ae31bcd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488734374 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.488734374
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.2545158817
Short name T688
Test name
Test status
Simulation time 16693667 ps
CPU time 0.97 seconds
Started Jul 19 06:28:31 PM PDT 24
Finished Jul 19 06:28:34 PM PDT 24
Peak memory 215540 kb
Host smart-359b8347-2405-4ece-a438-5327256bf17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545158817 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.2545158817
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.2819776805
Short name T381
Test name
Test status
Simulation time 225196222 ps
CPU time 4.55 seconds
Started Jul 19 06:28:29 PM PDT 24
Finished Jul 19 06:28:34 PM PDT 24
Peak memory 217444 kb
Host smart-abe6f69f-edb4-4d2c-8876-8e99c2a1eab9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819776805 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2819776805
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.680083223
Short name T468
Test name
Test status
Simulation time 262326049589 ps
CPU time 1589.27 seconds
Started Jul 19 06:28:29 PM PDT 24
Finished Jul 19 06:54:59 PM PDT 24
Peak memory 226436 kb
Host smart-ca6f7e85-9b9e-47c5-b6b2-9415013068cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680083223 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.680083223
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.1614174825
Short name T122
Test name
Test status
Simulation time 24711489 ps
CPU time 1.24 seconds
Started Jul 19 06:28:32 PM PDT 24
Finished Jul 19 06:28:35 PM PDT 24
Peak memory 221304 kb
Host smart-6be6db61-5e64-4e4a-a2c1-31443d1ea299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614174825 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.1614174825
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.3136814708
Short name T471
Test name
Test status
Simulation time 54422705 ps
CPU time 0.88 seconds
Started Jul 19 06:28:32 PM PDT 24
Finished Jul 19 06:28:34 PM PDT 24
Peak memory 207068 kb
Host smart-97551091-8d3b-4723-89ad-ed38ba149edd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136814708 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3136814708
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.3816659811
Short name T157
Test name
Test status
Simulation time 30076412 ps
CPU time 1.13 seconds
Started Jul 19 06:28:32 PM PDT 24
Finished Jul 19 06:28:35 PM PDT 24
Peak memory 219428 kb
Host smart-b5cc62e1-258e-4750-9e25-27a33ef62a86
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816659811 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.3816659811
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.2723585158
Short name T128
Test name
Test status
Simulation time 20506974 ps
CPU time 1.15 seconds
Started Jul 19 06:28:30 PM PDT 24
Finished Jul 19 06:28:32 PM PDT 24
Peak memory 219880 kb
Host smart-3548f876-8456-4a32-b57b-3170827ade72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723585158 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.2723585158
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.270841779
Short name T550
Test name
Test status
Simulation time 45226018 ps
CPU time 1.05 seconds
Started Jul 19 06:28:33 PM PDT 24
Finished Jul 19 06:28:36 PM PDT 24
Peak memory 218604 kb
Host smart-273c252e-501c-44b3-ad8b-d869da1e826d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270841779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.270841779
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.3273453771
Short name T105
Test name
Test status
Simulation time 31586029 ps
CPU time 0.85 seconds
Started Jul 19 06:28:30 PM PDT 24
Finished Jul 19 06:28:33 PM PDT 24
Peak memory 215996 kb
Host smart-dbc0f937-749f-47b4-94bd-bf6b08663f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273453771 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.3273453771
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.1522012188
Short name T987
Test name
Test status
Simulation time 20089962 ps
CPU time 1.04 seconds
Started Jul 19 06:28:30 PM PDT 24
Finished Jul 19 06:28:33 PM PDT 24
Peak memory 215620 kb
Host smart-3f14404d-7315-4358-9416-5cad34c6a42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522012188 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1522012188
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.4179500486
Short name T431
Test name
Test status
Simulation time 730743267 ps
CPU time 4.01 seconds
Started Jul 19 06:28:30 PM PDT 24
Finished Jul 19 06:28:36 PM PDT 24
Peak memory 217652 kb
Host smart-a780b9d0-ae77-48a1-8e96-f6ee09d7f26c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179500486 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.4179500486
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.725686431
Short name T701
Test name
Test status
Simulation time 102083154288 ps
CPU time 1026.4 seconds
Started Jul 19 06:28:31 PM PDT 24
Finished Jul 19 06:45:39 PM PDT 24
Peak memory 222220 kb
Host smart-90bfdcf4-4462-4efc-ba56-310819e29c8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725686431 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.725686431
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.1350603056
Short name T899
Test name
Test status
Simulation time 24737860 ps
CPU time 1.22 seconds
Started Jul 19 06:28:32 PM PDT 24
Finished Jul 19 06:28:35 PM PDT 24
Peak memory 218924 kb
Host smart-cf233d95-be1e-4ab3-b653-84b4cd596adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350603056 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.1350603056
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.1565327195
Short name T571
Test name
Test status
Simulation time 34851271 ps
CPU time 1.27 seconds
Started Jul 19 06:28:32 PM PDT 24
Finished Jul 19 06:28:35 PM PDT 24
Peak memory 215344 kb
Host smart-15ca38ef-6703-475e-aebc-38f379f86609
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565327195 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.1565327195
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.3244817380
Short name T447
Test name
Test status
Simulation time 13571347 ps
CPU time 0.94 seconds
Started Jul 19 06:28:30 PM PDT 24
Finished Jul 19 06:28:32 PM PDT 24
Peak memory 216640 kb
Host smart-0408f1fe-4341-44cd-a298-ec96f5396248
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244817380 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.3244817380
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.801742758
Short name T211
Test name
Test status
Simulation time 41961265 ps
CPU time 1.31 seconds
Started Jul 19 06:28:30 PM PDT 24
Finished Jul 19 06:28:34 PM PDT 24
Peak memory 217240 kb
Host smart-a0b8e93e-8b49-467f-8fdc-7021235e877c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801742758 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_di
sable_auto_req_mode.801742758
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.4129956984
Short name T223
Test name
Test status
Simulation time 22732779 ps
CPU time 0.94 seconds
Started Jul 19 06:28:29 PM PDT 24
Finished Jul 19 06:28:30 PM PDT 24
Peak memory 218812 kb
Host smart-6a55bc04-7366-465b-a678-6a1d5f0eb8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129956984 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.4129956984
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.4123071740
Short name T454
Test name
Test status
Simulation time 48031741 ps
CPU time 1.13 seconds
Started Jul 19 06:28:31 PM PDT 24
Finished Jul 19 06:28:33 PM PDT 24
Peak memory 218660 kb
Host smart-aff74341-dbfc-437c-a263-a48f31d35016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123071740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.4123071740
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.3867457254
Short name T492
Test name
Test status
Simulation time 30042830 ps
CPU time 1.04 seconds
Started Jul 19 06:28:30 PM PDT 24
Finished Jul 19 06:28:33 PM PDT 24
Peak memory 224288 kb
Host smart-012a1209-6e5a-40d5-a7cc-098de65a6fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867457254 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.3867457254
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.2672301595
Short name T630
Test name
Test status
Simulation time 48323957 ps
CPU time 0.94 seconds
Started Jul 19 06:28:28 PM PDT 24
Finished Jul 19 06:28:30 PM PDT 24
Peak memory 207324 kb
Host smart-d6923c3b-4ca6-4734-9064-00d2f9341b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672301595 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.2672301595
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.3345648435
Short name T374
Test name
Test status
Simulation time 399998185 ps
CPU time 4.42 seconds
Started Jul 19 06:28:28 PM PDT 24
Finished Jul 19 06:28:33 PM PDT 24
Peak memory 215556 kb
Host smart-a709309c-1294-4dab-b0aa-dead8f564d19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345648435 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.3345648435
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.3221034895
Short name T767
Test name
Test status
Simulation time 47952259610 ps
CPU time 1175.28 seconds
Started Jul 19 06:28:33 PM PDT 24
Finished Jul 19 06:48:10 PM PDT 24
Peak memory 223968 kb
Host smart-acbc58cc-9e35-4044-b942-f602eea230d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221034895 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.3221034895
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.3239528076
Short name T149
Test name
Test status
Simulation time 84968273 ps
CPU time 1.12 seconds
Started Jul 19 06:28:33 PM PDT 24
Finished Jul 19 06:28:36 PM PDT 24
Peak memory 219748 kb
Host smart-53100e9a-b2db-470e-b2fc-6a4e0859d6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239528076 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3239528076
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.3149252565
Short name T605
Test name
Test status
Simulation time 47871913 ps
CPU time 0.88 seconds
Started Jul 19 06:28:39 PM PDT 24
Finished Jul 19 06:28:42 PM PDT 24
Peak memory 206992 kb
Host smart-7a058d01-8ded-450e-9c29-1e7c27c62e23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149252565 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3149252565
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.476191247
Short name T852
Test name
Test status
Simulation time 20875961 ps
CPU time 0.9 seconds
Started Jul 19 06:28:39 PM PDT 24
Finished Jul 19 06:28:41 PM PDT 24
Peak memory 215656 kb
Host smart-47c63dc6-c0bf-41be-8c8d-7a57e37b5fa9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476191247 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.476191247
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.1479651091
Short name T164
Test name
Test status
Simulation time 121295618 ps
CPU time 1.26 seconds
Started Jul 19 06:28:37 PM PDT 24
Finished Jul 19 06:28:40 PM PDT 24
Peak memory 217192 kb
Host smart-601b576f-57ad-4389-a658-027eed9dbba8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479651091 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.1479651091
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.3721458635
Short name T807
Test name
Test status
Simulation time 18079705 ps
CPU time 1.11 seconds
Started Jul 19 06:28:36 PM PDT 24
Finished Jul 19 06:28:39 PM PDT 24
Peak memory 218916 kb
Host smart-30e3b18d-3714-4682-8bb3-8a7cf4e58f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721458635 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3721458635
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.2654837822
Short name T552
Test name
Test status
Simulation time 78369473 ps
CPU time 1.38 seconds
Started Jul 19 06:28:39 PM PDT 24
Finished Jul 19 06:28:42 PM PDT 24
Peak memory 219188 kb
Host smart-d4a99717-70b0-463b-b5c8-5489d7a952a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654837822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2654837822
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.3758773079
Short name T104
Test name
Test status
Simulation time 19521085 ps
CPU time 1.05 seconds
Started Jul 19 06:28:35 PM PDT 24
Finished Jul 19 06:28:37 PM PDT 24
Peak memory 216196 kb
Host smart-9a142ce2-8e6e-4a26-8133-e0a0ff879ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758773079 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.3758773079
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1636307106
Short name T671
Test name
Test status
Simulation time 18428511 ps
CPU time 1.05 seconds
Started Jul 19 06:28:28 PM PDT 24
Finished Jul 19 06:28:30 PM PDT 24
Peak memory 215552 kb
Host smart-1100a511-207a-4233-88ce-16faee9b194d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636307106 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1636307106
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.647133002
Short name T209
Test name
Test status
Simulation time 1102939573 ps
CPU time 4.94 seconds
Started Jul 19 06:28:37 PM PDT 24
Finished Jul 19 06:28:44 PM PDT 24
Peak memory 215576 kb
Host smart-732f76c3-4d22-4cd9-ae67-0b2d3e07ed07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647133002 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.647133002
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.597121087
Short name T247
Test name
Test status
Simulation time 55915083624 ps
CPU time 312 seconds
Started Jul 19 06:28:42 PM PDT 24
Finished Jul 19 06:33:55 PM PDT 24
Peak memory 218996 kb
Host smart-f057e36a-0563-4931-a778-2e732966ac4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597121087 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.597121087
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.817220472
Short name T486
Test name
Test status
Simulation time 184223467 ps
CPU time 1.25 seconds
Started Jul 19 06:28:36 PM PDT 24
Finished Jul 19 06:28:39 PM PDT 24
Peak memory 218948 kb
Host smart-be201b51-5dea-4add-8816-7a3f7771851d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817220472 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.817220472
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.4227084207
Short name T537
Test name
Test status
Simulation time 20360344 ps
CPU time 1.03 seconds
Started Jul 19 06:28:36 PM PDT 24
Finished Jul 19 06:28:38 PM PDT 24
Peak memory 207212 kb
Host smart-d0998aef-ccf0-441d-91c1-b95e3664de51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227084207 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.4227084207
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.1648522019
Short name T182
Test name
Test status
Simulation time 58900143 ps
CPU time 0.83 seconds
Started Jul 19 06:28:40 PM PDT 24
Finished Jul 19 06:28:42 PM PDT 24
Peak memory 216592 kb
Host smart-a756bf0a-b5d5-4cfe-852f-d9866847680c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648522019 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1648522019
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.3717665338
Short name T766
Test name
Test status
Simulation time 26181034 ps
CPU time 1.03 seconds
Started Jul 19 06:28:35 PM PDT 24
Finished Jul 19 06:28:37 PM PDT 24
Peak memory 218404 kb
Host smart-90e0466d-fa17-4e9e-a5d4-60b8cb23ca66
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717665338 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.3717665338
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.1343247828
Short name T730
Test name
Test status
Simulation time 34354641 ps
CPU time 0.89 seconds
Started Jul 19 06:28:37 PM PDT 24
Finished Jul 19 06:28:40 PM PDT 24
Peak memory 218432 kb
Host smart-cddccf75-4361-4f64-a581-46ac44553f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343247828 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.1343247828
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.2801311914
Short name T392
Test name
Test status
Simulation time 196147352 ps
CPU time 1.01 seconds
Started Jul 19 06:28:37 PM PDT 24
Finished Jul 19 06:28:40 PM PDT 24
Peak memory 217860 kb
Host smart-af9ae555-7e7c-4e9a-8916-d74a710c05b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801311914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.2801311914
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.361928406
Short name T903
Test name
Test status
Simulation time 27228055 ps
CPU time 1.07 seconds
Started Jul 19 06:28:40 PM PDT 24
Finished Jul 19 06:28:42 PM PDT 24
Peak memory 224348 kb
Host smart-d74e9e9f-85eb-4a49-b093-faae90bbf0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361928406 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.361928406
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.2513414685
Short name T421
Test name
Test status
Simulation time 33629147 ps
CPU time 0.87 seconds
Started Jul 19 06:28:37 PM PDT 24
Finished Jul 19 06:28:40 PM PDT 24
Peak memory 215552 kb
Host smart-45fd6302-0bdc-45df-be10-fd315acbc0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513414685 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.2513414685
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.1738579811
Short name T779
Test name
Test status
Simulation time 1520677486 ps
CPU time 3.74 seconds
Started Jul 19 06:28:37 PM PDT 24
Finished Jul 19 06:28:43 PM PDT 24
Peak memory 217688 kb
Host smart-e061e896-c9ab-46a8-98b5-5a2966ce998a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738579811 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.1738579811
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.3071962237
Short name T246
Test name
Test status
Simulation time 19787467512 ps
CPU time 440.74 seconds
Started Jul 19 06:28:39 PM PDT 24
Finished Jul 19 06:36:02 PM PDT 24
Peak memory 221864 kb
Host smart-e5f6836e-c654-4676-8ef7-00166e259e56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071962237 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.3071962237
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.3747121537
Short name T549
Test name
Test status
Simulation time 39104046 ps
CPU time 1.09 seconds
Started Jul 19 06:27:15 PM PDT 24
Finished Jul 19 06:27:17 PM PDT 24
Peak memory 220016 kb
Host smart-64ee1ee6-7bf9-4cf3-8904-879caeb03a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747121537 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3747121537
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.468539609
Short name T427
Test name
Test status
Simulation time 19861411 ps
CPU time 0.81 seconds
Started Jul 19 06:27:15 PM PDT 24
Finished Jul 19 06:27:16 PM PDT 24
Peak memory 207104 kb
Host smart-21d68bd1-2650-46f8-95da-91eac6e5d5f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468539609 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.468539609
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.3543958106
Short name T587
Test name
Test status
Simulation time 13045209 ps
CPU time 0.89 seconds
Started Jul 19 06:27:15 PM PDT 24
Finished Jul 19 06:27:17 PM PDT 24
Peak memory 215656 kb
Host smart-2fcab22d-eb86-440a-a833-4bbf2069ad6b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543958106 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.3543958106
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.3712705754
Short name T289
Test name
Test status
Simulation time 49583236 ps
CPU time 1.05 seconds
Started Jul 19 06:27:17 PM PDT 24
Finished Jul 19 06:27:19 PM PDT 24
Peak memory 218588 kb
Host smart-c857315c-5be8-4ce8-a36d-a58eb2d875a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712705754 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.3712705754
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.3324334847
Short name T702
Test name
Test status
Simulation time 32422045 ps
CPU time 0.99 seconds
Started Jul 19 06:27:15 PM PDT 24
Finished Jul 19 06:27:17 PM PDT 24
Peak memory 224096 kb
Host smart-fad74c31-3487-4b2b-8941-72437386b879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324334847 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.3324334847
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.1486048823
Short name T11
Test name
Test status
Simulation time 150272462 ps
CPU time 1.28 seconds
Started Jul 19 06:27:11 PM PDT 24
Finished Jul 19 06:27:13 PM PDT 24
Peak memory 217876 kb
Host smart-bec39cca-edff-4761-b578-02e89aa86aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486048823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1486048823
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.3865737128
Short name T53
Test name
Test status
Simulation time 23353318 ps
CPU time 1.19 seconds
Started Jul 19 06:27:18 PM PDT 24
Finished Jul 19 06:27:20 PM PDT 24
Peak memory 224352 kb
Host smart-ea69141a-a9f1-4e5c-9e0c-8ad9f4a05373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865737128 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3865737128
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.3377547601
Short name T547
Test name
Test status
Simulation time 29990621 ps
CPU time 0.97 seconds
Started Jul 19 06:27:10 PM PDT 24
Finished Jul 19 06:27:12 PM PDT 24
Peak memory 207380 kb
Host smart-9cb60637-d26f-4f9c-8a39-34477c1c2417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377547601 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.3377547601
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.1443194411
Short name T19
Test name
Test status
Simulation time 1026792971 ps
CPU time 4.46 seconds
Started Jul 19 06:27:16 PM PDT 24
Finished Jul 19 06:27:22 PM PDT 24
Peak memory 235664 kb
Host smart-01d3f5f7-6ca8-46c4-b862-4d2b5cf043d9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443194411 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.1443194411
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.2647933662
Short name T76
Test name
Test status
Simulation time 60166393 ps
CPU time 0.92 seconds
Started Jul 19 06:27:09 PM PDT 24
Finished Jul 19 06:27:11 PM PDT 24
Peak memory 215568 kb
Host smart-da8cb5d4-8309-470d-b771-7247673389d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647933662 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.2647933662
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.2990231160
Short name T881
Test name
Test status
Simulation time 234662785 ps
CPU time 1.85 seconds
Started Jul 19 06:27:10 PM PDT 24
Finished Jul 19 06:27:13 PM PDT 24
Peak memory 215496 kb
Host smart-81a55c25-8c95-4ae0-b140-51e129a1a73e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990231160 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.2990231160
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_alert_test.109901597
Short name T384
Test name
Test status
Simulation time 41810078 ps
CPU time 0.8 seconds
Started Jul 19 06:28:38 PM PDT 24
Finished Jul 19 06:28:41 PM PDT 24
Peak memory 207012 kb
Host smart-ef3446b8-b77f-46a4-9eb1-3d1d3bd07c83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109901597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.109901597
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.3386645866
Short name T81
Test name
Test status
Simulation time 11613545 ps
CPU time 0.88 seconds
Started Jul 19 06:28:41 PM PDT 24
Finished Jul 19 06:28:43 PM PDT 24
Peak memory 216572 kb
Host smart-3a1e82d1-beea-4f17-b0f7-3280d2b03059
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386645866 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.3386645866
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.3591443446
Short name T799
Test name
Test status
Simulation time 83451322 ps
CPU time 1.04 seconds
Started Jul 19 06:28:37 PM PDT 24
Finished Jul 19 06:28:40 PM PDT 24
Peak memory 217184 kb
Host smart-c20eb0dc-5117-43af-b650-09692826b639
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591443446 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.3591443446
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_genbits.1156938462
Short name T897
Test name
Test status
Simulation time 34724823 ps
CPU time 1.16 seconds
Started Jul 19 06:28:38 PM PDT 24
Finished Jul 19 06:28:41 PM PDT 24
Peak memory 219992 kb
Host smart-b7bf5148-6cfd-43a0-88d0-f8e240d5b04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156938462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1156938462
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.2445160815
Short name T850
Test name
Test status
Simulation time 23327056 ps
CPU time 0.97 seconds
Started Jul 19 06:28:36 PM PDT 24
Finished Jul 19 06:28:38 PM PDT 24
Peak memory 216168 kb
Host smart-83a8d00e-176d-4562-b247-ab5abd4fd062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445160815 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.2445160815
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.1048636940
Short name T584
Test name
Test status
Simulation time 25518287 ps
CPU time 0.95 seconds
Started Jul 19 06:28:36 PM PDT 24
Finished Jul 19 06:28:38 PM PDT 24
Peak memory 215572 kb
Host smart-11d4c3d1-89ad-483f-a077-b194934e89b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048636940 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1048636940
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2669700043
Short name T347
Test name
Test status
Simulation time 1023398760 ps
CPU time 4.52 seconds
Started Jul 19 06:28:36 PM PDT 24
Finished Jul 19 06:28:43 PM PDT 24
Peak memory 217388 kb
Host smart-270eb496-3c75-4547-9f88-1eb6fd3e3ac0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669700043 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2669700043
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.3691229759
Short name T837
Test name
Test status
Simulation time 317829577992 ps
CPU time 1659.07 seconds
Started Jul 19 06:28:39 PM PDT 24
Finished Jul 19 06:56:20 PM PDT 24
Peak memory 223208 kb
Host smart-9c7bd339-76ff-4d4f-b906-db36ca770402
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691229759 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.3691229759
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.604907891
Short name T171
Test name
Test status
Simulation time 68386442 ps
CPU time 1.2 seconds
Started Jul 19 06:28:36 PM PDT 24
Finished Jul 19 06:28:39 PM PDT 24
Peak memory 220068 kb
Host smart-0503ea9d-172c-4541-a93e-b65c0f7edbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604907891 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.604907891
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.4197322152
Short name T667
Test name
Test status
Simulation time 60237469 ps
CPU time 0.95 seconds
Started Jul 19 06:28:38 PM PDT 24
Finished Jul 19 06:28:40 PM PDT 24
Peak memory 206972 kb
Host smart-c43ff7ac-d59c-4ed8-8bb9-b19dd397ba9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197322152 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.4197322152
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.2576762595
Short name T168
Test name
Test status
Simulation time 36406025 ps
CPU time 0.85 seconds
Started Jul 19 06:28:35 PM PDT 24
Finished Jul 19 06:28:37 PM PDT 24
Peak memory 215688 kb
Host smart-7836238c-206a-4b83-b5d6-c17da3bb2a9e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576762595 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2576762595
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.1326080297
Short name T155
Test name
Test status
Simulation time 40581124 ps
CPU time 1.36 seconds
Started Jul 19 06:28:35 PM PDT 24
Finished Jul 19 06:28:38 PM PDT 24
Peak memory 217392 kb
Host smart-49f82ce4-e455-48a0-ae23-f2de6ea1ff50
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326080297 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.1326080297
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.1581324882
Short name T522
Test name
Test status
Simulation time 26747616 ps
CPU time 0.89 seconds
Started Jul 19 06:28:37 PM PDT 24
Finished Jul 19 06:28:40 PM PDT 24
Peak memory 218688 kb
Host smart-7d846d69-85ed-4dcc-ae82-e5070faf6203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581324882 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.1581324882
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.152318683
Short name T906
Test name
Test status
Simulation time 25061323 ps
CPU time 1.11 seconds
Started Jul 19 06:28:42 PM PDT 24
Finished Jul 19 06:28:44 PM PDT 24
Peak memory 217376 kb
Host smart-4b121fed-b525-4218-ab78-d2beacf40000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152318683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.152318683
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.1727468648
Short name T67
Test name
Test status
Simulation time 22633223 ps
CPU time 1.1 seconds
Started Jul 19 06:28:37 PM PDT 24
Finished Jul 19 06:28:40 PM PDT 24
Peak memory 215776 kb
Host smart-7d9ec184-d433-4dbb-85c7-5edc93368180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727468648 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.1727468648
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.2942090737
Short name T593
Test name
Test status
Simulation time 20020990 ps
CPU time 0.96 seconds
Started Jul 19 06:28:38 PM PDT 24
Finished Jul 19 06:28:41 PM PDT 24
Peak memory 215532 kb
Host smart-98d61467-c1b1-4003-9e45-3aa0e3f6d74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942090737 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.2942090737
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.2963856415
Short name T47
Test name
Test status
Simulation time 965188992 ps
CPU time 2.3 seconds
Started Jul 19 06:28:36 PM PDT 24
Finished Jul 19 06:28:40 PM PDT 24
Peak memory 217584 kb
Host smart-2b9ea92c-0dc1-4b48-a2e3-a4bcb786eed7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963856415 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.2963856415
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_alert.505922333
Short name T113
Test name
Test status
Simulation time 39923740 ps
CPU time 1.26 seconds
Started Jul 19 06:28:39 PM PDT 24
Finished Jul 19 06:28:42 PM PDT 24
Peak memory 218888 kb
Host smart-d42466dc-e837-4e85-a8e2-9e66205fc08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505922333 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.505922333
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.490409310
Short name T119
Test name
Test status
Simulation time 22999624 ps
CPU time 1.03 seconds
Started Jul 19 06:28:44 PM PDT 24
Finished Jul 19 06:28:46 PM PDT 24
Peak memory 207000 kb
Host smart-e1a46eb7-c523-4357-840b-170e165c7ee6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490409310 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.490409310
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.1100502957
Short name T971
Test name
Test status
Simulation time 73176623 ps
CPU time 0.82 seconds
Started Jul 19 06:28:38 PM PDT 24
Finished Jul 19 06:28:41 PM PDT 24
Peak memory 216448 kb
Host smart-03a2a725-fcde-4729-a06c-75161bd8c2a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100502957 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1100502957
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.1002316805
Short name T800
Test name
Test status
Simulation time 96445213 ps
CPU time 1.13 seconds
Started Jul 19 06:28:46 PM PDT 24
Finished Jul 19 06:28:49 PM PDT 24
Peak memory 217140 kb
Host smart-e54b233f-1d16-478c-9dc6-4d4e586dcebc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002316805 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.1002316805
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.3511232887
Short name T8
Test name
Test status
Simulation time 24315744 ps
CPU time 0.99 seconds
Started Jul 19 06:28:36 PM PDT 24
Finished Jul 19 06:28:39 PM PDT 24
Peak memory 219820 kb
Host smart-79ed181c-ef2d-46ae-8ed0-deadcf2821ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511232887 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.3511232887
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.3558227917
Short name T672
Test name
Test status
Simulation time 62426758 ps
CPU time 1.1 seconds
Started Jul 19 06:28:42 PM PDT 24
Finished Jul 19 06:28:44 PM PDT 24
Peak memory 220356 kb
Host smart-4e0cbd7e-a3f4-407d-9fe3-61646923d436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558227917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.3558227917
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_smoke.2731673849
Short name T78
Test name
Test status
Simulation time 25650245 ps
CPU time 0.96 seconds
Started Jul 19 06:28:40 PM PDT 24
Finished Jul 19 06:28:42 PM PDT 24
Peak memory 215556 kb
Host smart-441d19fa-e1cc-4352-97ec-cec741af8269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731673849 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.2731673849
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.1549918476
Short name T5
Test name
Test status
Simulation time 357530409 ps
CPU time 6.81 seconds
Started Jul 19 06:28:37 PM PDT 24
Finished Jul 19 06:28:45 PM PDT 24
Peak memory 215552 kb
Host smart-37bff429-8727-453a-ba7a-c0085342a7ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549918476 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1549918476
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.2209049703
Short name T35
Test name
Test status
Simulation time 41339250562 ps
CPU time 526.35 seconds
Started Jul 19 06:28:37 PM PDT 24
Finished Jul 19 06:37:25 PM PDT 24
Peak memory 218652 kb
Host smart-f353f407-701c-4817-8734-129dee4dd820
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209049703 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.2209049703
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.4143030294
Short name T287
Test name
Test status
Simulation time 84670424 ps
CPU time 1.22 seconds
Started Jul 19 06:28:46 PM PDT 24
Finished Jul 19 06:28:49 PM PDT 24
Peak memory 219980 kb
Host smart-18ebf832-2dfb-4522-8c37-1b09816822d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143030294 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.4143030294
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.204451703
Short name T643
Test name
Test status
Simulation time 21035430 ps
CPU time 0.82 seconds
Started Jul 19 06:28:42 PM PDT 24
Finished Jul 19 06:28:44 PM PDT 24
Peak memory 206776 kb
Host smart-a1471483-0659-4d7e-b247-62c583b3ca5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204451703 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.204451703
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.1168173676
Short name T383
Test name
Test status
Simulation time 28200830 ps
CPU time 0.83 seconds
Started Jul 19 06:28:44 PM PDT 24
Finished Jul 19 06:28:46 PM PDT 24
Peak memory 216220 kb
Host smart-2fbe1cac-eee7-4a92-8d95-ad9ed9d94b34
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168173676 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.1168173676
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.181813760
Short name T131
Test name
Test status
Simulation time 156497883 ps
CPU time 1.2 seconds
Started Jul 19 06:28:42 PM PDT 24
Finished Jul 19 06:28:44 PM PDT 24
Peak memory 217160 kb
Host smart-4a4db519-4f72-476e-9004-9eb068960c8d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181813760 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_di
sable_auto_req_mode.181813760
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.3182808027
Short name T186
Test name
Test status
Simulation time 33091207 ps
CPU time 0.98 seconds
Started Jul 19 06:28:43 PM PDT 24
Finished Jul 19 06:28:45 PM PDT 24
Peak memory 218536 kb
Host smart-faa54e86-3507-4939-be0e-538a8d962cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182808027 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.3182808027
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.3085917422
Short name T995
Test name
Test status
Simulation time 37892740 ps
CPU time 1.5 seconds
Started Jul 19 06:28:45 PM PDT 24
Finished Jul 19 06:28:48 PM PDT 24
Peak memory 220212 kb
Host smart-501b2e16-6c83-4fa6-9f42-2a070d6fa387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085917422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.3085917422
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.4188147590
Short name T982
Test name
Test status
Simulation time 27251419 ps
CPU time 0.89 seconds
Started Jul 19 06:28:43 PM PDT 24
Finished Jul 19 06:28:44 PM PDT 24
Peak memory 215928 kb
Host smart-99215f4e-39a4-4108-941a-d1bde540292a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188147590 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.4188147590
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.3444013190
Short name T570
Test name
Test status
Simulation time 51618551 ps
CPU time 0.98 seconds
Started Jul 19 06:28:42 PM PDT 24
Finished Jul 19 06:28:44 PM PDT 24
Peak memory 215560 kb
Host smart-4b6282b9-479e-4459-9dae-e36e4d326ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444013190 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.3444013190
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1290255204
Short name T816
Test name
Test status
Simulation time 393281511 ps
CPU time 7.67 seconds
Started Jul 19 06:28:46 PM PDT 24
Finished Jul 19 06:28:55 PM PDT 24
Peak memory 217324 kb
Host smart-dfe0ac4f-397a-40b5-a471-1367d2efd4e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290255204 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1290255204
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.3459073754
Short name T894
Test name
Test status
Simulation time 291918507957 ps
CPU time 2009.76 seconds
Started Jul 19 06:28:42 PM PDT 24
Finished Jul 19 07:02:13 PM PDT 24
Peak memory 227856 kb
Host smart-a451b6f0-0249-4ba9-977b-bccd203071af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459073754 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.3459073754
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.1607992491
Short name T619
Test name
Test status
Simulation time 139635833 ps
CPU time 1.32 seconds
Started Jul 19 06:28:44 PM PDT 24
Finished Jul 19 06:28:47 PM PDT 24
Peak memory 220128 kb
Host smart-227071b8-5d4b-4125-ae79-802a85e54be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607992491 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.1607992491
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.1181509583
Short name T986
Test name
Test status
Simulation time 73256876 ps
CPU time 1.83 seconds
Started Jul 19 06:28:44 PM PDT 24
Finished Jul 19 06:28:48 PM PDT 24
Peak memory 215260 kb
Host smart-3b48458b-8d7d-499d-be97-7a90f78ec3e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181509583 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.1181509583
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.2170688494
Short name T648
Test name
Test status
Simulation time 75368671 ps
CPU time 0.87 seconds
Started Jul 19 06:28:45 PM PDT 24
Finished Jul 19 06:28:47 PM PDT 24
Peak memory 216184 kb
Host smart-2b660ffd-99bf-4f27-b56c-ad6637077c27
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170688494 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2170688494
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.3032520136
Short name T21
Test name
Test status
Simulation time 167422644 ps
CPU time 1.07 seconds
Started Jul 19 06:28:44 PM PDT 24
Finished Jul 19 06:28:47 PM PDT 24
Peak memory 217036 kb
Host smart-4627635d-1f86-48b2-92a3-c29c95a1a9c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032520136 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.3032520136
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.2831158756
Short name T801
Test name
Test status
Simulation time 128118222 ps
CPU time 1.01 seconds
Started Jul 19 06:28:45 PM PDT 24
Finished Jul 19 06:28:48 PM PDT 24
Peak memory 220884 kb
Host smart-e33b9995-bb46-4d20-8a11-090fc1c0444d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831158756 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.2831158756
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.3145979988
Short name T686
Test name
Test status
Simulation time 34408497 ps
CPU time 1.37 seconds
Started Jul 19 06:28:43 PM PDT 24
Finished Jul 19 06:28:46 PM PDT 24
Peak memory 218932 kb
Host smart-be57c74a-4a18-49c3-bdc3-f829109a6bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145979988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.3145979988
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.300503139
Short name T803
Test name
Test status
Simulation time 25491411 ps
CPU time 1.17 seconds
Started Jul 19 06:28:45 PM PDT 24
Finished Jul 19 06:28:48 PM PDT 24
Peak memory 215864 kb
Host smart-1007c8c3-5ae7-44e0-acad-8c0e5e303acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300503139 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.300503139
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.395844579
Short name T579
Test name
Test status
Simulation time 36172382 ps
CPU time 0.95 seconds
Started Jul 19 06:28:46 PM PDT 24
Finished Jul 19 06:28:49 PM PDT 24
Peak memory 215496 kb
Host smart-e194eba4-c592-4689-abdf-31817aed7dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395844579 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.395844579
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.1062504556
Short name T641
Test name
Test status
Simulation time 244949339 ps
CPU time 5 seconds
Started Jul 19 06:28:45 PM PDT 24
Finished Jul 19 06:28:52 PM PDT 24
Peak memory 215564 kb
Host smart-98f3c0f0-630c-4caa-b1ea-e1d21858aa02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062504556 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1062504556
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.1940100515
Short name T694
Test name
Test status
Simulation time 56694946166 ps
CPU time 1320.82 seconds
Started Jul 19 06:28:44 PM PDT 24
Finished Jul 19 06:50:46 PM PDT 24
Peak memory 221672 kb
Host smart-ba882495-42bb-46c7-a2d6-7ec7934aa298
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940100515 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.1940100515
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.1301976251
Short name T659
Test name
Test status
Simulation time 24161220 ps
CPU time 1.25 seconds
Started Jul 19 06:28:44 PM PDT 24
Finished Jul 19 06:28:48 PM PDT 24
Peak memory 220660 kb
Host smart-16668fd3-c89c-4cbc-b090-405b7b39df3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301976251 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.1301976251
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.1163276413
Short name T690
Test name
Test status
Simulation time 13346723 ps
CPU time 0.89 seconds
Started Jul 19 06:28:44 PM PDT 24
Finished Jul 19 06:28:47 PM PDT 24
Peak memory 207020 kb
Host smart-34c8b48a-6973-42d8-9241-5179425660ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163276413 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.1163276413
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.4107693237
Short name T796
Test name
Test status
Simulation time 23394060 ps
CPU time 0.89 seconds
Started Jul 19 06:28:46 PM PDT 24
Finished Jul 19 06:28:49 PM PDT 24
Peak memory 216584 kb
Host smart-84f5021e-4ac5-4380-b5dc-4366c38987d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107693237 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.4107693237
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_err.1952418452
Short name T863
Test name
Test status
Simulation time 19520126 ps
CPU time 1.2 seconds
Started Jul 19 06:28:43 PM PDT 24
Finished Jul 19 06:28:45 PM PDT 24
Peak memory 229860 kb
Host smart-7928eeeb-2f19-4a13-9ef4-dc7477259cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952418452 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1952418452
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.55188349
Short name T705
Test name
Test status
Simulation time 67573307 ps
CPU time 2.42 seconds
Started Jul 19 06:28:41 PM PDT 24
Finished Jul 19 06:28:45 PM PDT 24
Peak memory 220632 kb
Host smart-b8a44c86-f6bb-420a-ae83-f73f4fccb084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55188349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.55188349
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.1418459675
Short name T841
Test name
Test status
Simulation time 36482066 ps
CPU time 0.87 seconds
Started Jul 19 06:28:45 PM PDT 24
Finished Jul 19 06:28:48 PM PDT 24
Peak memory 215920 kb
Host smart-b807bb57-2ebd-4cdf-8e66-6e2af3d2e2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418459675 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.1418459675
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.3837347736
Short name T363
Test name
Test status
Simulation time 17719333 ps
CPU time 1 seconds
Started Jul 19 06:28:45 PM PDT 24
Finished Jul 19 06:28:47 PM PDT 24
Peak memory 207512 kb
Host smart-ad088f8f-c8c5-4721-80dc-1af21ece30dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837347736 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.3837347736
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.2626985801
Short name T364
Test name
Test status
Simulation time 779910714 ps
CPU time 4.78 seconds
Started Jul 19 06:28:44 PM PDT 24
Finished Jul 19 06:28:51 PM PDT 24
Peak memory 215572 kb
Host smart-63e2f0c3-5583-4e47-9358-606e7c5f695f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626985801 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.2626985801
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.1035406628
Short name T466
Test name
Test status
Simulation time 4260937792 ps
CPU time 95.53 seconds
Started Jul 19 06:28:43 PM PDT 24
Finished Jul 19 06:30:19 PM PDT 24
Peak memory 217388 kb
Host smart-d826579f-d8ef-4fcf-b527-caa5ab19fb2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035406628 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.1035406628
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.1425654766
Short name T253
Test name
Test status
Simulation time 145072389 ps
CPU time 1.29 seconds
Started Jul 19 06:28:44 PM PDT 24
Finished Jul 19 06:28:47 PM PDT 24
Peak memory 219004 kb
Host smart-7b84275b-daa3-406d-9758-6245b0fc7456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425654766 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.1425654766
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.296198745
Short name T700
Test name
Test status
Simulation time 43594941 ps
CPU time 0.94 seconds
Started Jul 19 06:28:53 PM PDT 24
Finished Jul 19 06:28:57 PM PDT 24
Peak memory 207084 kb
Host smart-0b949d22-c6de-42b8-b736-23326efd3937
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296198745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.296198745
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.915578571
Short name T738
Test name
Test status
Simulation time 11778998 ps
CPU time 0.95 seconds
Started Jul 19 06:28:55 PM PDT 24
Finished Jul 19 06:28:58 PM PDT 24
Peak memory 215876 kb
Host smart-2b9bf278-8025-48b8-b24a-6deb916732f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915578571 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.915578571
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.620364943
Short name T952
Test name
Test status
Simulation time 61932740 ps
CPU time 1.01 seconds
Started Jul 19 06:28:53 PM PDT 24
Finished Jul 19 06:28:56 PM PDT 24
Peak memory 219920 kb
Host smart-6a419bd7-5a31-4c1b-be2c-39dfce2171c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620364943 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_di
sable_auto_req_mode.620364943
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.2351254749
Short name T175
Test name
Test status
Simulation time 23158112 ps
CPU time 0.93 seconds
Started Jul 19 06:28:44 PM PDT 24
Finished Jul 19 06:28:46 PM PDT 24
Peak memory 218860 kb
Host smart-24e20b65-050b-4d40-862f-c0318b322758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351254749 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.2351254749
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1330280366
Short name T637
Test name
Test status
Simulation time 52285481 ps
CPU time 1.6 seconds
Started Jul 19 06:28:44 PM PDT 24
Finished Jul 19 06:28:48 PM PDT 24
Peak memory 218824 kb
Host smart-07ba6ab7-fcf5-4165-831f-95b9f68b077a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330280366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1330280366
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.3929553624
Short name T772
Test name
Test status
Simulation time 29654874 ps
CPU time 0.86 seconds
Started Jul 19 06:28:46 PM PDT 24
Finished Jul 19 06:28:48 PM PDT 24
Peak memory 215912 kb
Host smart-286c73aa-fd7d-4bbb-b5c1-61ba1c08820b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929553624 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3929553624
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.1239496573
Short name T65
Test name
Test status
Simulation time 43738933 ps
CPU time 0.94 seconds
Started Jul 19 06:28:43 PM PDT 24
Finished Jul 19 06:28:44 PM PDT 24
Peak memory 215544 kb
Host smart-f8f80035-fa5e-4fce-988f-f9b28f9dfcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239496573 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.1239496573
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.3400513610
Short name T566
Test name
Test status
Simulation time 192244480 ps
CPU time 2.57 seconds
Started Jul 19 06:28:46 PM PDT 24
Finished Jul 19 06:28:50 PM PDT 24
Peak memory 217472 kb
Host smart-97eb35a6-2614-468d-b5db-10dae557dc5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400513610 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.3400513610
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.1675799543
Short name T874
Test name
Test status
Simulation time 56503915559 ps
CPU time 769.73 seconds
Started Jul 19 06:28:45 PM PDT 24
Finished Jul 19 06:41:37 PM PDT 24
Peak memory 219676 kb
Host smart-5520ca5c-dbcc-448d-aa90-9f92df83cf67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675799543 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.1675799543
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.3635307448
Short name T166
Test name
Test status
Simulation time 26103130 ps
CPU time 1.23 seconds
Started Jul 19 06:28:54 PM PDT 24
Finished Jul 19 06:28:57 PM PDT 24
Peak memory 219420 kb
Host smart-092e1b4b-2f39-486b-b81a-1a7f220485e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635307448 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.3635307448
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.1265257262
Short name T765
Test name
Test status
Simulation time 28359540 ps
CPU time 0.98 seconds
Started Jul 19 06:28:53 PM PDT 24
Finished Jul 19 06:28:57 PM PDT 24
Peak memory 215488 kb
Host smart-c1733edc-d3fe-4cae-a0d9-12e86be12f15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265257262 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1265257262
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.3980246998
Short name T712
Test name
Test status
Simulation time 22438842 ps
CPU time 0.86 seconds
Started Jul 19 06:28:52 PM PDT 24
Finished Jul 19 06:28:55 PM PDT 24
Peak memory 215632 kb
Host smart-0d5f5911-e670-4f64-873d-370c7cefdc1e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980246998 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3980246998
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.565806193
Short name T130
Test name
Test status
Simulation time 74326371 ps
CPU time 1.07 seconds
Started Jul 19 06:28:54 PM PDT 24
Finished Jul 19 06:28:57 PM PDT 24
Peak memory 217088 kb
Host smart-0ad9d8d7-df9c-4f33-bd66-617170b75ad2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565806193 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_di
sable_auto_req_mode.565806193
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.1385860044
Short name T873
Test name
Test status
Simulation time 36479156 ps
CPU time 0.88 seconds
Started Jul 19 06:28:53 PM PDT 24
Finished Jul 19 06:28:57 PM PDT 24
Peak memory 219468 kb
Host smart-5dd80860-057d-4cca-a9d1-05365accad19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385860044 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.1385860044
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.1453730840
Short name T481
Test name
Test status
Simulation time 28121777 ps
CPU time 1.21 seconds
Started Jul 19 06:28:51 PM PDT 24
Finished Jul 19 06:28:53 PM PDT 24
Peak memory 217648 kb
Host smart-e3c0cce1-ccfb-4ec8-a631-b0df0d6cfb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453730840 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1453730840
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1735166600
Short name T375
Test name
Test status
Simulation time 40638146 ps
CPU time 0.9 seconds
Started Jul 19 06:28:53 PM PDT 24
Finished Jul 19 06:28:56 PM PDT 24
Peak memory 215648 kb
Host smart-a65aa6c8-a09b-40b7-a409-b90603bb7eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735166600 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1735166600
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.230032833
Short name T395
Test name
Test status
Simulation time 24555514 ps
CPU time 0.95 seconds
Started Jul 19 06:28:51 PM PDT 24
Finished Jul 19 06:28:53 PM PDT 24
Peak memory 215568 kb
Host smart-0e5ff11c-9087-4e2b-b37a-55f74dd5147e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230032833 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.230032833
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.4263292231
Short name T72
Test name
Test status
Simulation time 486835254 ps
CPU time 3.16 seconds
Started Jul 19 06:28:55 PM PDT 24
Finished Jul 19 06:29:00 PM PDT 24
Peak memory 220072 kb
Host smart-f45dfd9c-742c-448d-b455-c6c37dfcb199
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263292231 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.4263292231
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.4092157048
Short name T112
Test name
Test status
Simulation time 32003452472 ps
CPU time 374.34 seconds
Started Jul 19 06:28:53 PM PDT 24
Finished Jul 19 06:35:10 PM PDT 24
Peak memory 224020 kb
Host smart-44d90341-6f3c-4873-bfb8-660b121b876a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092157048 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.4092157048
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.1562236824
Short name T178
Test name
Test status
Simulation time 91654242 ps
CPU time 1.22 seconds
Started Jul 19 06:28:55 PM PDT 24
Finished Jul 19 06:28:58 PM PDT 24
Peak memory 220120 kb
Host smart-4f929ae4-849a-4f42-b808-823414c2c5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562236824 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.1562236824
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.2438071507
Short name T386
Test name
Test status
Simulation time 42660250 ps
CPU time 0.87 seconds
Started Jul 19 06:28:52 PM PDT 24
Finished Jul 19 06:28:54 PM PDT 24
Peak memory 206856 kb
Host smart-46dc2aa1-ff9b-4845-9ab9-abd5a3326061
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438071507 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.2438071507
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.3621514406
Short name T213
Test name
Test status
Simulation time 16968489 ps
CPU time 0.86 seconds
Started Jul 19 06:28:53 PM PDT 24
Finished Jul 19 06:28:56 PM PDT 24
Peak memory 216632 kb
Host smart-53f73875-ef50-48d2-aeae-7ccf4c88e429
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621514406 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3621514406
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.1216248900
Short name T232
Test name
Test status
Simulation time 62364049 ps
CPU time 1.25 seconds
Started Jul 19 06:28:51 PM PDT 24
Finished Jul 19 06:28:53 PM PDT 24
Peak memory 217548 kb
Host smart-6180cabe-6410-4878-a4a3-48aa67a1c4f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216248900 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.1216248900
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.1990050893
Short name T7
Test name
Test status
Simulation time 35234402 ps
CPU time 0.95 seconds
Started Jul 19 06:28:53 PM PDT 24
Finished Jul 19 06:28:56 PM PDT 24
Peak memory 219820 kb
Host smart-f77bb781-667c-4ee7-857c-6610227991d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990050893 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.1990050893
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_intr.2900523623
Short name T29
Test name
Test status
Simulation time 19765339 ps
CPU time 1.13 seconds
Started Jul 19 06:28:54 PM PDT 24
Finished Jul 19 06:28:57 PM PDT 24
Peak memory 216092 kb
Host smart-e5d4ecf3-f453-4fba-9c99-257efdd3d625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900523623 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.2900523623
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.388993618
Short name T631
Test name
Test status
Simulation time 21141716 ps
CPU time 1.09 seconds
Started Jul 19 06:28:51 PM PDT 24
Finished Jul 19 06:28:55 PM PDT 24
Peak memory 215544 kb
Host smart-9b522c67-2767-405a-a115-470d00d71143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388993618 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.388993618
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.1924234323
Short name T932
Test name
Test status
Simulation time 244447816 ps
CPU time 5.06 seconds
Started Jul 19 06:28:55 PM PDT 24
Finished Jul 19 06:29:02 PM PDT 24
Peak memory 217404 kb
Host smart-c2520649-7864-440d-a64f-ba488a39a4a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924234323 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1924234323
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1310998002
Short name T239
Test name
Test status
Simulation time 77360586150 ps
CPU time 1946.5 seconds
Started Jul 19 06:28:51 PM PDT 24
Finished Jul 19 07:01:20 PM PDT 24
Peak memory 225712 kb
Host smart-b5db0616-aed6-481f-b49f-1d423512e995
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310998002 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.1310998002
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.1041009942
Short name T640
Test name
Test status
Simulation time 42518973 ps
CPU time 1.15 seconds
Started Jul 19 06:28:52 PM PDT 24
Finished Jul 19 06:28:55 PM PDT 24
Peak memory 219060 kb
Host smart-d6da9f4e-0284-4b6a-8625-bf910640361c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041009942 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.1041009942
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.3696836823
Short name T514
Test name
Test status
Simulation time 14427415 ps
CPU time 0.89 seconds
Started Jul 19 06:28:52 PM PDT 24
Finished Jul 19 06:28:54 PM PDT 24
Peak memory 215396 kb
Host smart-0ff0f8e0-7bc1-427d-9df3-2c69ac4e6857
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696836823 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.3696836823
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.2639708115
Short name T188
Test name
Test status
Simulation time 11858216 ps
CPU time 0.93 seconds
Started Jul 19 06:28:52 PM PDT 24
Finished Jul 19 06:28:55 PM PDT 24
Peak memory 216744 kb
Host smart-8f805af5-5bf7-4067-a179-5732fd7323fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639708115 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2639708115
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.613269361
Short name T972
Test name
Test status
Simulation time 29682575 ps
CPU time 1.11 seconds
Started Jul 19 06:28:51 PM PDT 24
Finished Jul 19 06:28:54 PM PDT 24
Peak memory 217000 kb
Host smart-aef3810d-25bf-4e50-b328-b8f9ce094131
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613269361 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_di
sable_auto_req_mode.613269361
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.334445839
Short name T887
Test name
Test status
Simulation time 30206873 ps
CPU time 0.85 seconds
Started Jul 19 06:28:55 PM PDT 24
Finished Jul 19 06:28:58 PM PDT 24
Peak memory 218644 kb
Host smart-9f9867b5-b053-4da5-8eaf-cc58f3ac3a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334445839 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.334445839
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.594365137
Short name T794
Test name
Test status
Simulation time 80351246 ps
CPU time 1.16 seconds
Started Jul 19 06:28:52 PM PDT 24
Finished Jul 19 06:28:56 PM PDT 24
Peak memory 217420 kb
Host smart-84f44692-ecac-491f-8e4d-ffe16f98feb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594365137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.594365137
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.4221431065
Short name T123
Test name
Test status
Simulation time 26836448 ps
CPU time 0.97 seconds
Started Jul 19 06:28:52 PM PDT 24
Finished Jul 19 06:28:55 PM PDT 24
Peak memory 216288 kb
Host smart-e2f41b3e-4893-4a44-bfc7-3dc0fce1d547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221431065 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.4221431065
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.2770563781
Short name T556
Test name
Test status
Simulation time 38375466 ps
CPU time 0.9 seconds
Started Jul 19 06:28:51 PM PDT 24
Finished Jul 19 06:28:54 PM PDT 24
Peak memory 215536 kb
Host smart-58a21adc-42be-4fa2-857b-b22de2c3351b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770563781 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.2770563781
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.1363969966
Short name T936
Test name
Test status
Simulation time 421280503 ps
CPU time 4.99 seconds
Started Jul 19 06:28:52 PM PDT 24
Finished Jul 19 06:28:58 PM PDT 24
Peak memory 215624 kb
Host smart-8ccc701e-355a-48c0-af25-8d00787987d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363969966 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.1363969966
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.3191557827
Short name T924
Test name
Test status
Simulation time 10262095754 ps
CPU time 227.11 seconds
Started Jul 19 06:28:53 PM PDT 24
Finished Jul 19 06:32:43 PM PDT 24
Peak memory 218480 kb
Host smart-68ca67d7-0744-4f28-90d3-58d4687cfcd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191557827 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.3191557827
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.2264494137
Short name T132
Test name
Test status
Simulation time 57677962 ps
CPU time 1.31 seconds
Started Jul 19 06:27:16 PM PDT 24
Finished Jul 19 06:27:19 PM PDT 24
Peak memory 216020 kb
Host smart-0ea0088d-4e0d-44ab-ba7b-2e4b58b940ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264494137 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.2264494137
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.2557762859
Short name T855
Test name
Test status
Simulation time 21074282 ps
CPU time 0.83 seconds
Started Jul 19 06:27:15 PM PDT 24
Finished Jul 19 06:27:16 PM PDT 24
Peak memory 207084 kb
Host smart-77ba0b51-f5f8-4b83-9f3a-796aa21978a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557762859 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2557762859
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.827878016
Short name T228
Test name
Test status
Simulation time 22586383 ps
CPU time 0.88 seconds
Started Jul 19 06:27:17 PM PDT 24
Finished Jul 19 06:27:19 PM PDT 24
Peak memory 216600 kb
Host smart-bb6da720-497e-41f1-929d-23d4ac566476
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827878016 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.827878016
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.672282481
Short name T726
Test name
Test status
Simulation time 119675664 ps
CPU time 1.17 seconds
Started Jul 19 06:27:15 PM PDT 24
Finished Jul 19 06:27:17 PM PDT 24
Peak memory 220116 kb
Host smart-8a5899bc-0cdf-473a-85b6-2452a5f0bdbc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672282481 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_dis
able_auto_req_mode.672282481
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.4074411948
Short name T193
Test name
Test status
Simulation time 19436168 ps
CPU time 1.22 seconds
Started Jul 19 06:27:15 PM PDT 24
Finished Jul 19 06:27:18 PM PDT 24
Peak memory 224300 kb
Host smart-431e09c4-dcb9-43e8-8bf0-becbf969e38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074411948 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.4074411948
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.4168119277
Short name T515
Test name
Test status
Simulation time 39945010 ps
CPU time 1.39 seconds
Started Jul 19 06:27:17 PM PDT 24
Finished Jul 19 06:27:19 PM PDT 24
Peak memory 217832 kb
Host smart-654cb237-ea54-40c4-b0ab-e0e2ed419ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168119277 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.4168119277
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.4044937576
Short name T435
Test name
Test status
Simulation time 35143799 ps
CPU time 0.9 seconds
Started Jul 19 06:27:14 PM PDT 24
Finished Jul 19 06:27:16 PM PDT 24
Peak memory 215548 kb
Host smart-118607a4-2a4e-4f01-9a70-122e4e74c05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044937576 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.4044937576
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.990973731
Short name T561
Test name
Test status
Simulation time 54125341 ps
CPU time 0.97 seconds
Started Jul 19 06:27:15 PM PDT 24
Finished Jul 19 06:27:17 PM PDT 24
Peak memory 207452 kb
Host smart-39385ffe-d63a-4d8f-8398-42add6910c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990973731 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.990973731
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.3508899038
Short name T490
Test name
Test status
Simulation time 15805736 ps
CPU time 0.97 seconds
Started Jul 19 06:27:15 PM PDT 24
Finished Jul 19 06:27:17 PM PDT 24
Peak memory 215532 kb
Host smart-672e5fc9-2af1-4430-9262-fa387113c32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508899038 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.3508899038
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.295481816
Short name T531
Test name
Test status
Simulation time 819171783 ps
CPU time 6.53 seconds
Started Jul 19 06:27:15 PM PDT 24
Finished Jul 19 06:27:22 PM PDT 24
Peak memory 217296 kb
Host smart-7cf80be1-061b-4c5c-b457-b1bcfc7ec761
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295481816 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.295481816
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.837064412
Short name T847
Test name
Test status
Simulation time 46213789526 ps
CPU time 1263.57 seconds
Started Jul 19 06:27:15 PM PDT 24
Finished Jul 19 06:48:20 PM PDT 24
Peak memory 222588 kb
Host smart-9170d678-b686-46e1-961c-9905b24d0698
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837064412 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.837064412
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.1606954432
Short name T675
Test name
Test status
Simulation time 369486631 ps
CPU time 1.4 seconds
Started Jul 19 06:28:54 PM PDT 24
Finished Jul 19 06:28:58 PM PDT 24
Peak memory 220028 kb
Host smart-0dd7e436-b97f-43c4-9670-5f4c58520c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606954432 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.1606954432
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.3161954674
Short name T930
Test name
Test status
Simulation time 29780423 ps
CPU time 1.3 seconds
Started Jul 19 06:29:04 PM PDT 24
Finished Jul 19 06:29:07 PM PDT 24
Peak memory 219904 kb
Host smart-6f9f1c52-5af9-4c7b-ae97-05c7ee5ce6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161954674 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.3161954674
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.2307943463
Short name T979
Test name
Test status
Simulation time 60496832 ps
CPU time 1.13 seconds
Started Jul 19 06:28:52 PM PDT 24
Finished Jul 19 06:28:55 PM PDT 24
Peak memory 217652 kb
Host smart-fcd0dba5-028b-4d73-9ff7-f9e86fa0dfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307943463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2307943463
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.1016536187
Short name T151
Test name
Test status
Simulation time 54611685 ps
CPU time 1.28 seconds
Started Jul 19 06:29:00 PM PDT 24
Finished Jul 19 06:29:02 PM PDT 24
Peak memory 219872 kb
Host smart-8ba5b4a4-1f69-4068-9322-7ea8626fe7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016536187 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.1016536187
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.1735278867
Short name T823
Test name
Test status
Simulation time 19422534 ps
CPU time 1.17 seconds
Started Jul 19 06:29:01 PM PDT 24
Finished Jul 19 06:29:04 PM PDT 24
Peak memory 229868 kb
Host smart-62ed720f-09bc-4291-bf29-813e417fe172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735278867 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.1735278867
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.3063432530
Short name T703
Test name
Test status
Simulation time 36774378 ps
CPU time 1.05 seconds
Started Jul 19 06:29:00 PM PDT 24
Finished Jul 19 06:29:02 PM PDT 24
Peak memory 217632 kb
Host smart-6bc9356d-4853-4f7d-a7f0-d551182eaa2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063432530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.3063432530
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.2388799533
Short name T996
Test name
Test status
Simulation time 36642400 ps
CPU time 1.21 seconds
Started Jul 19 06:29:03 PM PDT 24
Finished Jul 19 06:29:05 PM PDT 24
Peak memory 220084 kb
Host smart-74e36f7d-ce74-4601-9b42-3a43d1e4d6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388799533 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.2388799533
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.2346569053
Short name T174
Test name
Test status
Simulation time 35534013 ps
CPU time 1 seconds
Started Jul 19 06:29:01 PM PDT 24
Finished Jul 19 06:29:03 PM PDT 24
Peak memory 224124 kb
Host smart-6d9fde6e-2577-4b68-9d7f-48798ccb4757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346569053 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2346569053
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.2990568654
Short name T444
Test name
Test status
Simulation time 32460033 ps
CPU time 1.31 seconds
Started Jul 19 06:29:03 PM PDT 24
Finished Jul 19 06:29:05 PM PDT 24
Peak memory 220076 kb
Host smart-bcfaeabb-cfe4-4601-ab6e-676db8264338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990568654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.2990568654
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.2414115746
Short name T832
Test name
Test status
Simulation time 28211906 ps
CPU time 1.36 seconds
Started Jul 19 06:29:04 PM PDT 24
Finished Jul 19 06:29:07 PM PDT 24
Peak memory 220100 kb
Host smart-d4e31ec2-d5a5-4986-acac-984bd0afc0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414115746 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.2414115746
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.2799054443
Short name T2
Test name
Test status
Simulation time 33000418 ps
CPU time 0.89 seconds
Started Jul 19 06:29:03 PM PDT 24
Finished Jul 19 06:29:06 PM PDT 24
Peak memory 218532 kb
Host smart-779b3948-6955-4024-88c4-00f487dc6f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799054443 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2799054443
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.2898297216
Short name T558
Test name
Test status
Simulation time 136365703 ps
CPU time 2.73 seconds
Started Jul 19 06:29:03 PM PDT 24
Finished Jul 19 06:29:07 PM PDT 24
Peak memory 218916 kb
Host smart-13a25bd0-8315-49ea-8645-ec9979fb78d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898297216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.2898297216
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.3227097371
Short name T121
Test name
Test status
Simulation time 22961231 ps
CPU time 1.22 seconds
Started Jul 19 06:29:00 PM PDT 24
Finished Jul 19 06:29:02 PM PDT 24
Peak memory 220584 kb
Host smart-e1b919ba-79fc-405c-a227-c812226fad19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227097371 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.3227097371
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.2759016915
Short name T181
Test name
Test status
Simulation time 21386949 ps
CPU time 0.97 seconds
Started Jul 19 06:29:04 PM PDT 24
Finished Jul 19 06:29:07 PM PDT 24
Peak memory 218832 kb
Host smart-844596f5-6c5a-4a69-b59e-ec223439fde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759016915 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.2759016915
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.1728318778
Short name T540
Test name
Test status
Simulation time 43695090 ps
CPU time 1.26 seconds
Started Jul 19 06:29:00 PM PDT 24
Finished Jul 19 06:29:03 PM PDT 24
Peak memory 220140 kb
Host smart-58198432-a77f-4a05-9fc3-d450e0cb8c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728318778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1728318778
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.14201208
Short name T176
Test name
Test status
Simulation time 25066498 ps
CPU time 1.11 seconds
Started Jul 19 06:29:03 PM PDT 24
Finished Jul 19 06:29:05 PM PDT 24
Peak memory 224280 kb
Host smart-76b83f06-17c9-48e8-864e-beb819350179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14201208 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.14201208
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.2507437262
Short name T970
Test name
Test status
Simulation time 67513672 ps
CPU time 2.68 seconds
Started Jul 19 06:29:01 PM PDT 24
Finished Jul 19 06:29:05 PM PDT 24
Peak memory 220028 kb
Host smart-337c960a-260b-4deb-a298-2098e9dbff9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507437262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.2507437262
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.2450296950
Short name T294
Test name
Test status
Simulation time 142701973 ps
CPU time 1.29 seconds
Started Jul 19 06:29:02 PM PDT 24
Finished Jul 19 06:29:05 PM PDT 24
Peak memory 218784 kb
Host smart-c1aa5c83-fa50-4d97-ad34-33c61d52bb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450296950 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.2450296950
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.1937607766
Short name T387
Test name
Test status
Simulation time 32251559 ps
CPU time 0.93 seconds
Started Jul 19 06:29:00 PM PDT 24
Finished Jul 19 06:29:02 PM PDT 24
Peak memory 218460 kb
Host smart-d112d2ff-f8b9-4c8e-a0fc-9b7e8f1c19b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937607766 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.1937607766
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.246964977
Short name T569
Test name
Test status
Simulation time 76943325 ps
CPU time 1.29 seconds
Started Jul 19 06:29:04 PM PDT 24
Finished Jul 19 06:29:07 PM PDT 24
Peak memory 220612 kb
Host smart-968a3563-30ed-45be-b7fd-e974eb009d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246964977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.246964977
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.2208529671
Short name T433
Test name
Test status
Simulation time 44536040 ps
CPU time 1.16 seconds
Started Jul 19 06:29:04 PM PDT 24
Finished Jul 19 06:29:06 PM PDT 24
Peak memory 219904 kb
Host smart-0096116f-da50-4286-bbcd-7c9bc803f123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208529671 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.2208529671
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.1380129568
Short name T30
Test name
Test status
Simulation time 23417976 ps
CPU time 0.97 seconds
Started Jul 19 06:29:02 PM PDT 24
Finished Jul 19 06:29:04 PM PDT 24
Peak memory 218668 kb
Host smart-5095ac59-827c-4673-a7fc-db04fadf7e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380129568 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.1380129568
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.2635736110
Short name T817
Test name
Test status
Simulation time 36279627 ps
CPU time 1.57 seconds
Started Jul 19 06:29:04 PM PDT 24
Finished Jul 19 06:29:07 PM PDT 24
Peak memory 220440 kb
Host smart-6c9615d7-2dd0-413a-a063-a13569dc59a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635736110 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2635736110
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.658508988
Short name T204
Test name
Test status
Simulation time 46362197 ps
CPU time 1.11 seconds
Started Jul 19 06:29:03 PM PDT 24
Finished Jul 19 06:29:06 PM PDT 24
Peak memory 220388 kb
Host smart-776e1681-5015-47c9-8237-aa0bdf189c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658508988 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.658508988
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.4027990968
Short name T632
Test name
Test status
Simulation time 18712453 ps
CPU time 1.23 seconds
Started Jul 19 06:29:02 PM PDT 24
Finished Jul 19 06:29:04 PM PDT 24
Peak memory 224296 kb
Host smart-46484874-c5a5-4312-aae8-22c100bf3bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027990968 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.4027990968
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.1519801913
Short name T464
Test name
Test status
Simulation time 41849532 ps
CPU time 1.53 seconds
Started Jul 19 06:29:01 PM PDT 24
Finished Jul 19 06:29:04 PM PDT 24
Peak memory 217500 kb
Host smart-620bec52-4979-418b-ae21-4676b23b8b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519801913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1519801913
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.3201712407
Short name T489
Test name
Test status
Simulation time 31128143 ps
CPU time 1.31 seconds
Started Jul 19 06:29:03 PM PDT 24
Finished Jul 19 06:29:05 PM PDT 24
Peak memory 220996 kb
Host smart-dedaff2c-d425-4b66-9b5b-0a0a234a1dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201712407 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.3201712407
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.2956758799
Short name T426
Test name
Test status
Simulation time 43069950 ps
CPU time 0.85 seconds
Started Jul 19 06:29:03 PM PDT 24
Finished Jul 19 06:29:05 PM PDT 24
Peak memory 218640 kb
Host smart-f83b8d53-424a-4f69-8e77-22801175535e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956758799 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.2956758799
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.191745672
Short name T318
Test name
Test status
Simulation time 37565758 ps
CPU time 1.7 seconds
Started Jul 19 06:29:04 PM PDT 24
Finished Jul 19 06:29:07 PM PDT 24
Peak memory 218956 kb
Host smart-b206ca80-a2de-47c7-8ae6-fb6f500c5f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191745672 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.191745672
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.2260117990
Short name T477
Test name
Test status
Simulation time 65222112 ps
CPU time 1.18 seconds
Started Jul 19 06:27:22 PM PDT 24
Finished Jul 19 06:27:24 PM PDT 24
Peak memory 220464 kb
Host smart-f11691a1-bdae-4453-8a02-f8319b194d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260117990 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.2260117990
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3382503171
Short name T428
Test name
Test status
Simulation time 56997225 ps
CPU time 1.01 seconds
Started Jul 19 06:27:22 PM PDT 24
Finished Jul 19 06:27:23 PM PDT 24
Peak memory 207064 kb
Host smart-fc487607-1ed4-4b88-b417-5b182213a243
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382503171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3382503171
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.210418473
Short name T214
Test name
Test status
Simulation time 125038059 ps
CPU time 0.84 seconds
Started Jul 19 06:27:21 PM PDT 24
Finished Jul 19 06:27:23 PM PDT 24
Peak memory 216508 kb
Host smart-e1c6a2fa-72a7-462c-bda7-f2a348fb96c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210418473 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.210418473
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.1557808827
Short name T696
Test name
Test status
Simulation time 47880073 ps
CPU time 1.2 seconds
Started Jul 19 06:27:23 PM PDT 24
Finished Jul 19 06:27:25 PM PDT 24
Peak memory 217224 kb
Host smart-2b2eb74a-a320-472d-ab7a-9a7bc6153e92
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557808827 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.1557808827
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.1153817299
Short name T937
Test name
Test status
Simulation time 24690390 ps
CPU time 1.06 seconds
Started Jul 19 06:27:23 PM PDT 24
Finished Jul 19 06:27:25 PM PDT 24
Peak memory 219980 kb
Host smart-b85409f0-6965-43ad-afec-e893b3b3e440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153817299 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.1153817299
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.1561876764
Short name T568
Test name
Test status
Simulation time 96616478 ps
CPU time 1.28 seconds
Started Jul 19 06:27:15 PM PDT 24
Finished Jul 19 06:27:17 PM PDT 24
Peak memory 219092 kb
Host smart-54a0ea54-9a11-4281-907a-d76a12bff6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561876764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.1561876764
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.3935960242
Short name T583
Test name
Test status
Simulation time 34556745 ps
CPU time 0.87 seconds
Started Jul 19 06:27:22 PM PDT 24
Finished Jul 19 06:27:24 PM PDT 24
Peak memory 215680 kb
Host smart-be0d2d17-d8e5-4c3a-96d0-1249bc178c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935960242 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.3935960242
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.2563539682
Short name T830
Test name
Test status
Simulation time 24747058 ps
CPU time 0.94 seconds
Started Jul 19 06:27:15 PM PDT 24
Finished Jul 19 06:27:17 PM PDT 24
Peak memory 207356 kb
Host smart-a5457311-0324-4485-b43a-728906fd767d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563539682 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.2563539682
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.4100710464
Short name T400
Test name
Test status
Simulation time 23091373 ps
CPU time 0.91 seconds
Started Jul 19 06:27:16 PM PDT 24
Finished Jul 19 06:27:18 PM PDT 24
Peak memory 215528 kb
Host smart-cccd3011-ebee-4b71-9bbf-6570d52e58b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100710464 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.4100710464
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.2926914220
Short name T681
Test name
Test status
Simulation time 50013379 ps
CPU time 0.96 seconds
Started Jul 19 06:27:24 PM PDT 24
Finished Jul 19 06:27:26 PM PDT 24
Peak memory 215544 kb
Host smart-a6b3636c-e4ac-47f0-8d87-992a3e732401
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926914220 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2926914220
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.664138118
Short name T980
Test name
Test status
Simulation time 44676100669 ps
CPU time 1046.17 seconds
Started Jul 19 06:27:23 PM PDT 24
Finished Jul 19 06:44:50 PM PDT 24
Peak memory 221000 kb
Host smart-d2a1cf4a-991c-4958-9d90-5d8e8981000c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664138118 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.664138118
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.2205652946
Short name T191
Test name
Test status
Simulation time 65110949 ps
CPU time 1.18 seconds
Started Jul 19 06:29:01 PM PDT 24
Finished Jul 19 06:29:03 PM PDT 24
Peak memory 219956 kb
Host smart-d64f5646-83f3-4aef-a278-8cbb8ad3db93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205652946 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.2205652946
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.3001039270
Short name T154
Test name
Test status
Simulation time 61526342 ps
CPU time 1.16 seconds
Started Jul 19 06:29:02 PM PDT 24
Finished Jul 19 06:29:04 PM PDT 24
Peak memory 219996 kb
Host smart-35bd1723-3475-45e5-bb90-4ff2d4674a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001039270 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.3001039270
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.1268746919
Short name T89
Test name
Test status
Simulation time 64631477 ps
CPU time 2.11 seconds
Started Jul 19 06:29:03 PM PDT 24
Finished Jul 19 06:29:07 PM PDT 24
Peak memory 217992 kb
Host smart-cd0714ee-8f7f-4a6d-846c-a85e91e2d6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268746919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.1268746919
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.2058957908
Short name T917
Test name
Test status
Simulation time 68295821 ps
CPU time 1.16 seconds
Started Jul 19 06:29:02 PM PDT 24
Finished Jul 19 06:29:04 PM PDT 24
Peak memory 220008 kb
Host smart-a7f24bc0-8ac1-40a4-bd6f-9a558dd98c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058957908 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.2058957908
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.1888292763
Short name T48
Test name
Test status
Simulation time 18840964 ps
CPU time 1.15 seconds
Started Jul 19 06:29:01 PM PDT 24
Finished Jul 19 06:29:03 PM PDT 24
Peak memory 224204 kb
Host smart-123291d9-0159-41d1-92c0-544d9ff7d1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888292763 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1888292763
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.2447657052
Short name T458
Test name
Test status
Simulation time 89642055 ps
CPU time 1.53 seconds
Started Jul 19 06:29:01 PM PDT 24
Finished Jul 19 06:29:03 PM PDT 24
Peak memory 218136 kb
Host smart-14a3a82c-f6b6-47df-af9f-3ff9bd182a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447657052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.2447657052
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.3165631794
Short name T311
Test name
Test status
Simulation time 77693912 ps
CPU time 1.18 seconds
Started Jul 19 06:29:01 PM PDT 24
Finished Jul 19 06:29:03 PM PDT 24
Peak memory 220140 kb
Host smart-093a896c-8fc3-4d94-bcba-3d5289f821b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165631794 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.3165631794
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.1045691801
Short name T206
Test name
Test status
Simulation time 29051829 ps
CPU time 0.95 seconds
Started Jul 19 06:29:13 PM PDT 24
Finished Jul 19 06:29:19 PM PDT 24
Peak memory 229648 kb
Host smart-5d1e5407-990b-4fb7-bcca-0003033cc648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045691801 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.1045691801
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.1498853652
Short name T380
Test name
Test status
Simulation time 40794471 ps
CPU time 1.58 seconds
Started Jul 19 06:29:01 PM PDT 24
Finished Jul 19 06:29:04 PM PDT 24
Peak memory 219000 kb
Host smart-41ac3f39-270b-44b4-8e3c-f61affda7d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498853652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.1498853652
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.4012012681
Short name T600
Test name
Test status
Simulation time 125327105 ps
CPU time 1.06 seconds
Started Jul 19 06:29:11 PM PDT 24
Finished Jul 19 06:29:17 PM PDT 24
Peak memory 220056 kb
Host smart-008c26b1-2061-463f-a6d2-2d8cb57e59ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012012681 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.4012012681
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.1756915583
Short name T708
Test name
Test status
Simulation time 205097025 ps
CPU time 1.14 seconds
Started Jul 19 06:29:11 PM PDT 24
Finished Jul 19 06:29:15 PM PDT 24
Peak memory 217544 kb
Host smart-1d40bba0-71e6-4e5e-9a29-2af476d531b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756915583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.1756915583
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.3903056679
Short name T60
Test name
Test status
Simulation time 82815518 ps
CPU time 1.27 seconds
Started Jul 19 06:29:11 PM PDT 24
Finished Jul 19 06:29:16 PM PDT 24
Peak memory 220052 kb
Host smart-1f3befb4-2f88-42bb-8038-27974ea50a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903056679 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.3903056679
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.246042647
Short name T918
Test name
Test status
Simulation time 35062607 ps
CPU time 1.18 seconds
Started Jul 19 06:29:16 PM PDT 24
Finished Jul 19 06:29:22 PM PDT 24
Peak memory 220888 kb
Host smart-621cb0d7-60fe-4dba-a75c-df5bb069e19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246042647 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.246042647
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.1259407745
Short name T93
Test name
Test status
Simulation time 56470173 ps
CPU time 1.35 seconds
Started Jul 19 06:29:11 PM PDT 24
Finished Jul 19 06:29:15 PM PDT 24
Peak memory 218936 kb
Host smart-ada20982-fe23-451e-87fa-977bbfdc747e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259407745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.1259407745
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.1500015544
Short name T308
Test name
Test status
Simulation time 77042584 ps
CPU time 1.2 seconds
Started Jul 19 06:29:13 PM PDT 24
Finished Jul 19 06:29:18 PM PDT 24
Peak memory 218812 kb
Host smart-f0569160-e195-44d2-9977-465193c70951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500015544 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.1500015544
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.1691273173
Short name T628
Test name
Test status
Simulation time 32794960 ps
CPU time 0.98 seconds
Started Jul 19 06:29:10 PM PDT 24
Finished Jul 19 06:29:14 PM PDT 24
Peak memory 224068 kb
Host smart-52608a19-7541-4643-83f5-c5f76c8255c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691273173 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.1691273173
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/66.edn_alert.3993879466
Short name T422
Test name
Test status
Simulation time 32003027 ps
CPU time 1.18 seconds
Started Jul 19 06:29:08 PM PDT 24
Finished Jul 19 06:29:10 PM PDT 24
Peak memory 220348 kb
Host smart-2dd86688-d779-467d-a2df-003af2d23ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993879466 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.3993879466
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.1200492166
Short name T80
Test name
Test status
Simulation time 22813292 ps
CPU time 0.94 seconds
Started Jul 19 06:29:10 PM PDT 24
Finished Jul 19 06:29:14 PM PDT 24
Peak memory 218788 kb
Host smart-76494b34-2be8-45b6-904f-fecf79862daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200492166 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1200492166
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.319101996
Short name T557
Test name
Test status
Simulation time 64186271 ps
CPU time 1.27 seconds
Started Jul 19 06:29:16 PM PDT 24
Finished Jul 19 06:29:22 PM PDT 24
Peak memory 217616 kb
Host smart-b7706b81-fece-4532-88d4-c97cbb390890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319101996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.319101996
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.2017186686
Short name T745
Test name
Test status
Simulation time 202931246 ps
CPU time 1.27 seconds
Started Jul 19 06:29:12 PM PDT 24
Finished Jul 19 06:29:18 PM PDT 24
Peak memory 216000 kb
Host smart-7e8d2fe4-409b-4e8d-be12-f5cece80607e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017186686 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.2017186686
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.1080500795
Short name T866
Test name
Test status
Simulation time 22859612 ps
CPU time 0.97 seconds
Started Jul 19 06:29:12 PM PDT 24
Finished Jul 19 06:29:18 PM PDT 24
Peak memory 219072 kb
Host smart-57bde052-b6c2-44e7-a62b-2ed7b6cbc4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080500795 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1080500795
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.695278391
Short name T438
Test name
Test status
Simulation time 55852255 ps
CPU time 1.29 seconds
Started Jul 19 06:29:13 PM PDT 24
Finished Jul 19 06:29:19 PM PDT 24
Peak memory 217632 kb
Host smart-113cdc8e-774b-4c28-8b91-d61221debf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695278391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.695278391
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.1325444547
Short name T288
Test name
Test status
Simulation time 27526624 ps
CPU time 1.28 seconds
Started Jul 19 06:29:09 PM PDT 24
Finished Jul 19 06:29:12 PM PDT 24
Peak memory 219076 kb
Host smart-88195fb4-6813-4f02-9da2-050d98c47ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325444547 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.1325444547
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.642050542
Short name T144
Test name
Test status
Simulation time 31968172 ps
CPU time 1.14 seconds
Started Jul 19 06:29:11 PM PDT 24
Finished Jul 19 06:29:16 PM PDT 24
Peak memory 220956 kb
Host smart-09aaac2f-97f1-476c-8ec2-1835bddb985a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642050542 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.642050542
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.3258877241
Short name T472
Test name
Test status
Simulation time 49063604 ps
CPU time 0.98 seconds
Started Jul 19 06:29:09 PM PDT 24
Finished Jul 19 06:29:11 PM PDT 24
Peak memory 217544 kb
Host smart-a4e1f20d-bb3d-4cf2-8f84-6c42f817777a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258877241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.3258877241
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.1661158604
Short name T608
Test name
Test status
Simulation time 82837516 ps
CPU time 1.18 seconds
Started Jul 19 06:29:09 PM PDT 24
Finished Jul 19 06:29:12 PM PDT 24
Peak memory 220272 kb
Host smart-c31e2ac3-a5db-464d-99fe-98678df9e191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661158604 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.1661158604
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.3114951722
Short name T741
Test name
Test status
Simulation time 31440388 ps
CPU time 0.96 seconds
Started Jul 19 06:29:09 PM PDT 24
Finished Jul 19 06:29:11 PM PDT 24
Peak memory 218732 kb
Host smart-1808eb0b-d859-432e-b8f5-728b13ea34aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114951722 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.3114951722
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.2484600970
Short name T410
Test name
Test status
Simulation time 49344229 ps
CPU time 1.19 seconds
Started Jul 19 06:29:11 PM PDT 24
Finished Jul 19 06:29:15 PM PDT 24
Peak memory 220280 kb
Host smart-4a1a013a-641a-4958-8fa0-6b9f2446dc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484600970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.2484600970
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.1069747726
Short name T639
Test name
Test status
Simulation time 98068202 ps
CPU time 1.25 seconds
Started Jul 19 06:27:22 PM PDT 24
Finished Jul 19 06:27:24 PM PDT 24
Peak memory 218660 kb
Host smart-eefcbcaf-9648-4039-9061-b313bedd5aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069747726 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1069747726
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.4207374013
Short name T418
Test name
Test status
Simulation time 61834379 ps
CPU time 0.92 seconds
Started Jul 19 06:27:22 PM PDT 24
Finished Jul 19 06:27:23 PM PDT 24
Peak memory 207060 kb
Host smart-2e4b2acb-aea0-4bf2-b466-0c14cbbf76ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207374013 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.4207374013
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.3958341742
Short name T91
Test name
Test status
Simulation time 13831875 ps
CPU time 0.89 seconds
Started Jul 19 06:27:25 PM PDT 24
Finished Jul 19 06:27:26 PM PDT 24
Peak memory 215620 kb
Host smart-4aecfa68-2944-4cac-8493-33746c441e31
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958341742 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3958341742
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.2573923731
Short name T868
Test name
Test status
Simulation time 148582445 ps
CPU time 1 seconds
Started Jul 19 06:27:24 PM PDT 24
Finished Jul 19 06:27:26 PM PDT 24
Peak memory 217064 kb
Host smart-e455cd28-acfa-4196-bff7-60a317cc87fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573923731 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.2573923731
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.3942793167
Short name T437
Test name
Test status
Simulation time 30569900 ps
CPU time 0.85 seconds
Started Jul 19 06:27:24 PM PDT 24
Finished Jul 19 06:27:26 PM PDT 24
Peak memory 218600 kb
Host smart-5018f047-8b42-4ebb-b474-015d2fe04ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942793167 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3942793167
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.1601613210
Short name T516
Test name
Test status
Simulation time 35788204 ps
CPU time 1.36 seconds
Started Jul 19 06:27:23 PM PDT 24
Finished Jul 19 06:27:25 PM PDT 24
Peak memory 220284 kb
Host smart-1e0b1277-4e3b-4495-889f-1ebd970317a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601613210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1601613210
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.881968552
Short name T527
Test name
Test status
Simulation time 24549449 ps
CPU time 1.05 seconds
Started Jul 19 06:27:23 PM PDT 24
Finished Jul 19 06:27:25 PM PDT 24
Peak memory 215724 kb
Host smart-569db4d9-14f7-4172-bbd1-2427ce8672da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881968552 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.881968552
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_smoke.3178265458
Short name T388
Test name
Test status
Simulation time 32650173 ps
CPU time 0.96 seconds
Started Jul 19 06:27:22 PM PDT 24
Finished Jul 19 06:27:23 PM PDT 24
Peak memory 215524 kb
Host smart-2dd54654-7ce2-4857-83c3-1943044eb69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178265458 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.3178265458
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.3943532420
Short name T107
Test name
Test status
Simulation time 229781523 ps
CPU time 1.55 seconds
Started Jul 19 06:27:23 PM PDT 24
Finished Jul 19 06:27:25 PM PDT 24
Peak memory 217484 kb
Host smart-62d62fef-83e8-4463-8b79-d2f43797469d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943532420 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.3943532420
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.1431961523
Short name T240
Test name
Test status
Simulation time 85588490812 ps
CPU time 1043.4 seconds
Started Jul 19 06:27:23 PM PDT 24
Finished Jul 19 06:44:48 PM PDT 24
Peak memory 224128 kb
Host smart-5dd46a37-82f0-48d2-b36e-108ce0af1fbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431961523 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.1431961523
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.3343593156
Short name T84
Test name
Test status
Simulation time 22569875 ps
CPU time 1.25 seconds
Started Jul 19 06:29:12 PM PDT 24
Finished Jul 19 06:29:18 PM PDT 24
Peak memory 219396 kb
Host smart-8a02626a-afe9-42e4-9c5f-2ce6a2b53974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343593156 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.3343593156
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.352907525
Short name T911
Test name
Test status
Simulation time 19504414 ps
CPU time 1.16 seconds
Started Jul 19 06:29:12 PM PDT 24
Finished Jul 19 06:29:18 PM PDT 24
Peak memory 224296 kb
Host smart-984cf3d3-7c70-4b0a-953f-15a4c1c11f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352907525 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.352907525
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.2810962008
Short name T655
Test name
Test status
Simulation time 96516353 ps
CPU time 1.49 seconds
Started Jul 19 06:29:11 PM PDT 24
Finished Jul 19 06:29:17 PM PDT 24
Peak memory 219040 kb
Host smart-41c8edb8-6c4d-4b0f-a106-a45dc703b2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810962008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.2810962008
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.2740283093
Short name T780
Test name
Test status
Simulation time 26954459 ps
CPU time 1.21 seconds
Started Jul 19 06:29:11 PM PDT 24
Finished Jul 19 06:29:16 PM PDT 24
Peak memory 218848 kb
Host smart-ea032124-30e3-4851-ab6f-6db9077760e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740283093 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.2740283093
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.3317828312
Short name T145
Test name
Test status
Simulation time 20753854 ps
CPU time 1.17 seconds
Started Jul 19 06:29:12 PM PDT 24
Finished Jul 19 06:29:18 PM PDT 24
Peak memory 219928 kb
Host smart-12f6d354-908b-4e7f-b2f3-541732df1bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317828312 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.3317828312
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.2384822316
Short name T969
Test name
Test status
Simulation time 172303810 ps
CPU time 1.72 seconds
Started Jul 19 06:29:10 PM PDT 24
Finished Jul 19 06:29:12 PM PDT 24
Peak memory 219112 kb
Host smart-2d80c361-dd2b-4e40-aeb4-7591f124cf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384822316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.2384822316
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.1570772417
Short name T234
Test name
Test status
Simulation time 39846948 ps
CPU time 1.28 seconds
Started Jul 19 06:29:10 PM PDT 24
Finished Jul 19 06:29:14 PM PDT 24
Peak memory 220632 kb
Host smart-c2dd9af3-5b95-4e2b-90fe-d8e9d50cef51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570772417 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.1570772417
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.4263373638
Short name T195
Test name
Test status
Simulation time 18797738 ps
CPU time 1.13 seconds
Started Jul 19 06:29:12 PM PDT 24
Finished Jul 19 06:29:17 PM PDT 24
Peak memory 224428 kb
Host smart-5f017e17-0278-4d3b-8461-098e4a1135d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263373638 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.4263373638
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.1485961750
Short name T636
Test name
Test status
Simulation time 200910939 ps
CPU time 1.65 seconds
Started Jul 19 06:29:12 PM PDT 24
Finished Jul 19 06:29:18 PM PDT 24
Peak memory 218852 kb
Host smart-5cf3a201-30f4-482b-b95a-bf6064f980bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485961750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.1485961750
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.557870092
Short name T70
Test name
Test status
Simulation time 176863437 ps
CPU time 1.13 seconds
Started Jul 19 06:29:13 PM PDT 24
Finished Jul 19 06:29:19 PM PDT 24
Peak memory 218976 kb
Host smart-bddb5d12-cd41-49bd-a102-f3e18b942bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557870092 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.557870092
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.3261115705
Short name T622
Test name
Test status
Simulation time 43443574 ps
CPU time 1.19 seconds
Started Jul 19 06:29:12 PM PDT 24
Finished Jul 19 06:29:18 PM PDT 24
Peak memory 225752 kb
Host smart-a2a9f407-3523-468a-8f21-40b66e6cd615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261115705 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.3261115705
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.779090510
Short name T333
Test name
Test status
Simulation time 40089319 ps
CPU time 1.19 seconds
Started Jul 19 06:29:13 PM PDT 24
Finished Jul 19 06:29:19 PM PDT 24
Peak memory 219064 kb
Host smart-5a436f5e-9729-4bde-b8dd-2b977a805c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779090510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.779090510
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.1490278754
Short name T409
Test name
Test status
Simulation time 23592227 ps
CPU time 1.16 seconds
Started Jul 19 06:29:11 PM PDT 24
Finished Jul 19 06:29:17 PM PDT 24
Peak memory 219068 kb
Host smart-21406baa-801e-4aa5-aee7-6e1a39c94bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490278754 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.1490278754
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.3245199542
Short name T955
Test name
Test status
Simulation time 20344810 ps
CPU time 1.13 seconds
Started Jul 19 06:29:10 PM PDT 24
Finished Jul 19 06:29:14 PM PDT 24
Peak memory 220272 kb
Host smart-f7cab758-fcea-4584-be22-94d6601e9298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245199542 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.3245199542
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.3070681691
Short name T507
Test name
Test status
Simulation time 230424426 ps
CPU time 3.28 seconds
Started Jul 19 06:29:13 PM PDT 24
Finished Jul 19 06:29:21 PM PDT 24
Peak memory 218876 kb
Host smart-6ab6ed1c-34bc-4c90-83a0-470638237f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070681691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.3070681691
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.884742983
Short name T190
Test name
Test status
Simulation time 107281660 ps
CPU time 1.26 seconds
Started Jul 19 06:29:12 PM PDT 24
Finished Jul 19 06:29:17 PM PDT 24
Peak memory 215976 kb
Host smart-88259231-1e21-4e72-8538-50ba8fbd80a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884742983 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.884742983
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.982083084
Short name T581
Test name
Test status
Simulation time 19046814 ps
CPU time 1.06 seconds
Started Jul 19 06:29:12 PM PDT 24
Finished Jul 19 06:29:18 PM PDT 24
Peak memory 218644 kb
Host smart-ac5e2060-8b73-428f-bf90-452e596f0d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982083084 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.982083084
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.4192048049
Short name T860
Test name
Test status
Simulation time 55680325 ps
CPU time 0.99 seconds
Started Jul 19 06:29:13 PM PDT 24
Finished Jul 19 06:29:19 PM PDT 24
Peak memory 217628 kb
Host smart-3b11a4af-477a-4d6c-bb86-b40e30163fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192048049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.4192048049
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.2434859928
Short name T49
Test name
Test status
Simulation time 28688182 ps
CPU time 1.36 seconds
Started Jul 19 06:29:11 PM PDT 24
Finished Jul 19 06:29:16 PM PDT 24
Peak memory 225896 kb
Host smart-6f055b71-4e2e-4240-bffd-fb5f2ee06b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434859928 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.2434859928
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.2665088994
Short name T382
Test name
Test status
Simulation time 67911118 ps
CPU time 1.03 seconds
Started Jul 19 06:29:09 PM PDT 24
Finished Jul 19 06:29:11 PM PDT 24
Peak memory 217724 kb
Host smart-199dda48-8cd5-43dd-9e97-6a863cdc1711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665088994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2665088994
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.3539597379
Short name T114
Test name
Test status
Simulation time 41453221 ps
CPU time 1.11 seconds
Started Jul 19 06:29:12 PM PDT 24
Finished Jul 19 06:29:18 PM PDT 24
Peak memory 218840 kb
Host smart-1dd6de8d-8fd6-4df1-b03d-5acbdc3183e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539597379 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.3539597379
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.774570805
Short name T216
Test name
Test status
Simulation time 20355127 ps
CPU time 1.07 seconds
Started Jul 19 06:29:12 PM PDT 24
Finished Jul 19 06:29:18 PM PDT 24
Peak memory 224400 kb
Host smart-71538fbd-5d5b-487d-ae8c-627f722a5a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774570805 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.774570805
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.1869398949
Short name T822
Test name
Test status
Simulation time 222736311 ps
CPU time 1.02 seconds
Started Jul 19 06:29:11 PM PDT 24
Finished Jul 19 06:29:16 PM PDT 24
Peak memory 217568 kb
Host smart-e0d16e83-0237-4a04-800a-831467838b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869398949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.1869398949
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.1392121269
Short name T94
Test name
Test status
Simulation time 29783319 ps
CPU time 1.29 seconds
Started Jul 19 06:29:09 PM PDT 24
Finished Jul 19 06:29:12 PM PDT 24
Peak memory 219100 kb
Host smart-a268e158-27a2-4419-8114-c2d1e88eb482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392121269 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.1392121269
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.923758832
Short name T732
Test name
Test status
Simulation time 40947459 ps
CPU time 0.84 seconds
Started Jul 19 06:29:14 PM PDT 24
Finished Jul 19 06:29:19 PM PDT 24
Peak memory 215632 kb
Host smart-eb062489-3a3c-4e6c-90b6-8bb43d80b0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923758832 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.923758832
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.3931165781
Short name T706
Test name
Test status
Simulation time 42231188 ps
CPU time 1.61 seconds
Started Jul 19 06:29:12 PM PDT 24
Finished Jul 19 06:29:18 PM PDT 24
Peak memory 218888 kb
Host smart-321f8c9e-48cc-4c95-ba94-deabe028d0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931165781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.3931165781
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.3284927165
Short name T788
Test name
Test status
Simulation time 27217667 ps
CPU time 1.29 seconds
Started Jul 19 06:29:08 PM PDT 24
Finished Jul 19 06:29:09 PM PDT 24
Peak memory 220220 kb
Host smart-c0898202-230d-4866-a090-328aa4c41dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284927165 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.3284927165
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.3120995472
Short name T185
Test name
Test status
Simulation time 36164488 ps
CPU time 0.86 seconds
Started Jul 19 06:29:09 PM PDT 24
Finished Jul 19 06:29:11 PM PDT 24
Peak memory 218252 kb
Host smart-ca5700cf-277a-47d6-9023-dfe2d4e58fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120995472 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.3120995472
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.3864395934
Short name T923
Test name
Test status
Simulation time 197201482 ps
CPU time 2.95 seconds
Started Jul 19 06:29:09 PM PDT 24
Finished Jul 19 06:29:13 PM PDT 24
Peak memory 220512 kb
Host smart-536277cb-361b-4dd6-bef5-a284f43c13dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864395934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3864395934
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.2513903801
Short name T673
Test name
Test status
Simulation time 136221330 ps
CPU time 1.27 seconds
Started Jul 19 06:27:30 PM PDT 24
Finished Jul 19 06:27:33 PM PDT 24
Peak memory 220028 kb
Host smart-593ee736-bc3a-4fd9-b4a9-8abfcb7e104b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513903801 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.2513903801
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.1205817545
Short name T411
Test name
Test status
Simulation time 91181199 ps
CPU time 0.91 seconds
Started Jul 19 06:27:30 PM PDT 24
Finished Jul 19 06:27:32 PM PDT 24
Peak memory 206996 kb
Host smart-4331f244-2e4f-4ad6-bc19-ac4545f5988c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205817545 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.1205817545
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.4040735979
Short name T462
Test name
Test status
Simulation time 37882856 ps
CPU time 0.87 seconds
Started Jul 19 06:27:30 PM PDT 24
Finished Jul 19 06:27:32 PM PDT 24
Peak memory 216288 kb
Host smart-bedea7b1-49bc-4834-8002-23b58961cb87
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040735979 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.4040735979
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.1643709635
Short name T43
Test name
Test status
Simulation time 32335547 ps
CPU time 1.11 seconds
Started Jul 19 06:27:30 PM PDT 24
Finished Jul 19 06:27:32 PM PDT 24
Peak memory 215852 kb
Host smart-a612a6e7-cf2d-469c-9287-869649ba6dc3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643709635 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.1643709635
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.3412032138
Short name T167
Test name
Test status
Simulation time 23991973 ps
CPU time 0.99 seconds
Started Jul 19 06:27:29 PM PDT 24
Finished Jul 19 06:27:31 PM PDT 24
Peak memory 218840 kb
Host smart-09986167-f45d-4fc9-a463-7a6a01c27b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412032138 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3412032138
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.3630015290
Short name T285
Test name
Test status
Simulation time 49824743 ps
CPU time 1.35 seconds
Started Jul 19 06:27:29 PM PDT 24
Finished Jul 19 06:27:31 PM PDT 24
Peak memory 217532 kb
Host smart-8067572d-7d46-4826-85fe-15070b784bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630015290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3630015290
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_regwen.80322867
Short name T306
Test name
Test status
Simulation time 17509653 ps
CPU time 0.97 seconds
Started Jul 19 06:27:29 PM PDT 24
Finished Jul 19 06:27:31 PM PDT 24
Peak memory 207368 kb
Host smart-cfee67f3-5159-4997-b778-1315e09788c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80322867 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.80322867
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.1823877695
Short name T511
Test name
Test status
Simulation time 36883733 ps
CPU time 0.96 seconds
Started Jul 19 06:27:23 PM PDT 24
Finished Jul 19 06:27:25 PM PDT 24
Peak memory 215560 kb
Host smart-a176b034-1239-45ab-af66-ba45a9e51c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823877695 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1823877695
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.384883655
Short name T111
Test name
Test status
Simulation time 550919452 ps
CPU time 5.8 seconds
Started Jul 19 06:27:29 PM PDT 24
Finished Jul 19 06:27:35 PM PDT 24
Peak memory 217540 kb
Host smart-9c29e578-5e54-4fca-a8a3-a7b2531b0fcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384883655 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.384883655
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.3620423716
Short name T811
Test name
Test status
Simulation time 45205385601 ps
CPU time 697.85 seconds
Started Jul 19 06:27:29 PM PDT 24
Finished Jul 19 06:39:08 PM PDT 24
Peak memory 218668 kb
Host smart-8caea88f-6d69-43f3-b497-5e780bf4ff02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620423716 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3620423716
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.3882954519
Short name T316
Test name
Test status
Simulation time 48256754 ps
CPU time 1.29 seconds
Started Jul 19 06:29:10 PM PDT 24
Finished Jul 19 06:29:14 PM PDT 24
Peak memory 219036 kb
Host smart-277d7125-919f-433a-8590-616e65c42409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882954519 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.3882954519
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.3487873635
Short name T405
Test name
Test status
Simulation time 27187684 ps
CPU time 0.84 seconds
Started Jul 19 06:29:17 PM PDT 24
Finished Jul 19 06:29:24 PM PDT 24
Peak memory 218556 kb
Host smart-301680cd-7969-49ef-9688-8aa05364c1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487873635 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.3487873635
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.1930566085
Short name T373
Test name
Test status
Simulation time 37724720 ps
CPU time 1.4 seconds
Started Jul 19 06:29:10 PM PDT 24
Finished Jul 19 06:29:12 PM PDT 24
Peak memory 215564 kb
Host smart-30133b96-244c-407b-a5a2-5d3506765c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930566085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.1930566085
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.3178042589
Short name T582
Test name
Test status
Simulation time 42322754 ps
CPU time 1.2 seconds
Started Jul 19 06:29:17 PM PDT 24
Finished Jul 19 06:29:23 PM PDT 24
Peak memory 220456 kb
Host smart-caa8fabd-72cf-4e1c-a1d2-611e2a98577a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178042589 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.3178042589
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.2952577717
Short name T152
Test name
Test status
Simulation time 41015566 ps
CPU time 1 seconds
Started Jul 19 06:29:19 PM PDT 24
Finished Jul 19 06:29:26 PM PDT 24
Peak memory 224276 kb
Host smart-f9d6c700-102a-48e8-8660-ddd49aca3431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952577717 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.2952577717
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.1054599794
Short name T83
Test name
Test status
Simulation time 99105247 ps
CPU time 1.22 seconds
Started Jul 19 06:29:18 PM PDT 24
Finished Jul 19 06:29:25 PM PDT 24
Peak memory 217500 kb
Host smart-f8b52790-5020-4a15-9bd7-6ed9be5e0bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054599794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.1054599794
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.3039939605
Short name T172
Test name
Test status
Simulation time 23350545 ps
CPU time 1.13 seconds
Started Jul 19 06:29:19 PM PDT 24
Finished Jul 19 06:29:26 PM PDT 24
Peak memory 216016 kb
Host smart-9605f38f-88b6-479c-9bb2-47e0006cb4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039939605 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.3039939605
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.106135155
Short name T647
Test name
Test status
Simulation time 34058077 ps
CPU time 0.99 seconds
Started Jul 19 06:29:17 PM PDT 24
Finished Jul 19 06:29:23 PM PDT 24
Peak memory 224076 kb
Host smart-dde47250-a701-499f-9d52-283f5d5c23ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106135155 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.106135155
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.2820654290
Short name T650
Test name
Test status
Simulation time 120106846 ps
CPU time 1.58 seconds
Started Jul 19 06:29:17 PM PDT 24
Finished Jul 19 06:29:24 PM PDT 24
Peak memory 220208 kb
Host smart-58223167-eb82-4d3e-bdcb-81b7d2c58638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820654290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.2820654290
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.3370764734
Short name T484
Test name
Test status
Simulation time 88788640 ps
CPU time 1.29 seconds
Started Jul 19 06:29:19 PM PDT 24
Finished Jul 19 06:29:27 PM PDT 24
Peak memory 220304 kb
Host smart-33b68355-2f77-493c-97c2-2389a79eb0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370764734 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.3370764734
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.406999303
Short name T785
Test name
Test status
Simulation time 198956479 ps
CPU time 1.04 seconds
Started Jul 19 06:29:20 PM PDT 24
Finished Jul 19 06:29:28 PM PDT 24
Peak memory 219860 kb
Host smart-08245c76-52a7-4df1-aa0e-b59bd5db64ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406999303 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.406999303
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.4108287484
Short name T691
Test name
Test status
Simulation time 104298477 ps
CPU time 1.21 seconds
Started Jul 19 06:29:18 PM PDT 24
Finished Jul 19 06:29:25 PM PDT 24
Peak memory 217516 kb
Host smart-ccc93404-9c4d-47d5-af71-49762167b29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108287484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.4108287484
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.72422522
Short name T879
Test name
Test status
Simulation time 79987144 ps
CPU time 1.13 seconds
Started Jul 19 06:29:18 PM PDT 24
Finished Jul 19 06:29:25 PM PDT 24
Peak memory 220232 kb
Host smart-6401e9d1-e0e9-44b1-9bea-60ed1b102ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72422522 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.72422522
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.2058825729
Short name T51
Test name
Test status
Simulation time 105058880 ps
CPU time 1.36 seconds
Started Jul 19 06:29:19 PM PDT 24
Finished Jul 19 06:29:26 PM PDT 24
Peak memory 225868 kb
Host smart-1ae51674-c2af-4696-98f1-fbad14fa3c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058825729 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.2058825729
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.2824969229
Short name T891
Test name
Test status
Simulation time 39689284 ps
CPU time 1.44 seconds
Started Jul 19 06:29:22 PM PDT 24
Finished Jul 19 06:29:31 PM PDT 24
Peak memory 215604 kb
Host smart-332b2e1f-3385-41e6-a402-cdf395b201af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824969229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.2824969229
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.3785608748
Short name T793
Test name
Test status
Simulation time 24487649 ps
CPU time 1.17 seconds
Started Jul 19 06:29:16 PM PDT 24
Finished Jul 19 06:29:22 PM PDT 24
Peak memory 218908 kb
Host smart-9eb1d6b5-06fb-4d00-a992-d5b5dcc471e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785608748 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.3785608748
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.431781758
Short name T14
Test name
Test status
Simulation time 21303006 ps
CPU time 1.03 seconds
Started Jul 19 06:29:20 PM PDT 24
Finished Jul 19 06:29:28 PM PDT 24
Peak memory 224260 kb
Host smart-40db0f26-f265-471b-b86d-68fc9dfd3d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431781758 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.431781758
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.4074050033
Short name T756
Test name
Test status
Simulation time 45069213 ps
CPU time 1.54 seconds
Started Jul 19 06:29:18 PM PDT 24
Finished Jul 19 06:29:24 PM PDT 24
Peak memory 218716 kb
Host smart-6b8fafc8-37f6-4308-ad6b-ad7cf934ffdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074050033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.4074050033
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.1884365236
Short name T853
Test name
Test status
Simulation time 28653569 ps
CPU time 1.29 seconds
Started Jul 19 06:29:16 PM PDT 24
Finished Jul 19 06:29:23 PM PDT 24
Peak memory 221388 kb
Host smart-8cad25d5-4db6-47a3-8ffb-0632af73921e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884365236 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.1884365236
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.3367407044
Short name T126
Test name
Test status
Simulation time 20364381 ps
CPU time 1.11 seconds
Started Jul 19 06:29:21 PM PDT 24
Finished Jul 19 06:29:29 PM PDT 24
Peak memory 219892 kb
Host smart-ac5a393f-f0f3-4704-bc25-1fe80704dd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367407044 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.3367407044
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.1992456184
Short name T757
Test name
Test status
Simulation time 158107395 ps
CPU time 1.12 seconds
Started Jul 19 06:29:18 PM PDT 24
Finished Jul 19 06:29:25 PM PDT 24
Peak memory 217784 kb
Host smart-db6aabc7-70fa-422e-bfd5-adabf7b23fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992456184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.1992456184
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.1348700949
Short name T173
Test name
Test status
Simulation time 30525968 ps
CPU time 1.34 seconds
Started Jul 19 06:29:17 PM PDT 24
Finished Jul 19 06:29:23 PM PDT 24
Peak memory 216008 kb
Host smart-c92c35f5-4ed6-4a4a-b118-93aba3751943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348700949 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.1348700949
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.3767701849
Short name T133
Test name
Test status
Simulation time 30958692 ps
CPU time 1.43 seconds
Started Jul 19 06:29:18 PM PDT 24
Finished Jul 19 06:29:25 PM PDT 24
Peak memory 229832 kb
Host smart-f7bac923-acba-4aa7-b7d9-8d785afc9408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767701849 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3767701849
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.825206116
Short name T530
Test name
Test status
Simulation time 45179064 ps
CPU time 1.7 seconds
Started Jul 19 06:29:20 PM PDT 24
Finished Jul 19 06:29:29 PM PDT 24
Peak memory 217736 kb
Host smart-362b5a82-aaef-4d3f-8c64-ab45d2472889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825206116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.825206116
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.933099276
Short name T599
Test name
Test status
Simulation time 72211835 ps
CPU time 1.16 seconds
Started Jul 19 06:29:22 PM PDT 24
Finished Jul 19 06:29:30 PM PDT 24
Peak memory 218880 kb
Host smart-edfdbaba-d2f6-430e-ab8b-8c9c59c9a3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933099276 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.933099276
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.2584959750
Short name T973
Test name
Test status
Simulation time 31211750 ps
CPU time 1.02 seconds
Started Jul 19 06:29:16 PM PDT 24
Finished Jul 19 06:29:22 PM PDT 24
Peak memory 218776 kb
Host smart-48d25213-570c-4da4-8e7c-96cd01ca3320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584959750 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.2584959750
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1880576954
Short name T518
Test name
Test status
Simulation time 35774357 ps
CPU time 1.36 seconds
Started Jul 19 06:29:17 PM PDT 24
Finished Jul 19 06:29:23 PM PDT 24
Peak memory 217552 kb
Host smart-3aadac2a-0fce-481c-aa39-141abc455cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880576954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1880576954
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.571584365
Short name T255
Test name
Test status
Simulation time 31323518 ps
CPU time 1.28 seconds
Started Jul 19 06:29:18 PM PDT 24
Finished Jul 19 06:29:25 PM PDT 24
Peak memory 219844 kb
Host smart-d6f61338-b5cc-4b3e-baf5-fed3c7f53205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571584365 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.571584365
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.2283279741
Short name T848
Test name
Test status
Simulation time 40052869 ps
CPU time 1.31 seconds
Started Jul 19 06:29:19 PM PDT 24
Finished Jul 19 06:29:26 PM PDT 24
Peak memory 225804 kb
Host smart-00bfa7cb-2b45-4cd8-9aa3-4f29817b4313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283279741 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.2283279741
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.3876744009
Short name T341
Test name
Test status
Simulation time 50590341 ps
CPU time 1.11 seconds
Started Jul 19 06:29:21 PM PDT 24
Finished Jul 19 06:29:28 PM PDT 24
Peak memory 220116 kb
Host smart-ff70077a-2e76-40c3-8c4f-0e386d90c508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876744009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.3876744009
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.3216177379
Short name T723
Test name
Test status
Simulation time 148049315 ps
CPU time 1.16 seconds
Started Jul 19 06:27:30 PM PDT 24
Finished Jul 19 06:27:33 PM PDT 24
Peak memory 219600 kb
Host smart-710c5b8b-45ff-490a-a403-bb5e8883f947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216177379 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.3216177379
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.3281383217
Short name T554
Test name
Test status
Simulation time 68056161 ps
CPU time 0.92 seconds
Started Jul 19 06:27:36 PM PDT 24
Finished Jul 19 06:27:38 PM PDT 24
Peak memory 207176 kb
Host smart-2120e844-e9ce-4a33-9219-758e79a9bda6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281383217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.3281383217
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.3291824369
Short name T430
Test name
Test status
Simulation time 55616099 ps
CPU time 0.85 seconds
Started Jul 19 06:27:30 PM PDT 24
Finished Jul 19 06:27:32 PM PDT 24
Peak memory 216536 kb
Host smart-56bf314b-ccc0-49bd-a303-f2f6cade1073
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291824369 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.3291824369
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.817921576
Short name T840
Test name
Test status
Simulation time 42639548 ps
CPU time 1.28 seconds
Started Jul 19 06:27:39 PM PDT 24
Finished Jul 19 06:27:41 PM PDT 24
Peak memory 218568 kb
Host smart-cbad1c8d-91c6-4ea1-90cb-4a42cf4b3b98
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817921576 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_dis
able_auto_req_mode.817921576
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.3409835957
Short name T52
Test name
Test status
Simulation time 95803607 ps
CPU time 1.36 seconds
Started Jul 19 06:27:28 PM PDT 24
Finished Jul 19 06:27:30 PM PDT 24
Peak memory 226036 kb
Host smart-a97a07dc-664e-4edc-8941-51bfe7495233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409835957 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.3409835957
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.598519302
Short name T880
Test name
Test status
Simulation time 95738546 ps
CPU time 1.08 seconds
Started Jul 19 06:27:30 PM PDT 24
Finished Jul 19 06:27:32 PM PDT 24
Peak memory 217676 kb
Host smart-b91824ca-812c-42db-9f9e-daddb331a23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598519302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.598519302
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.98892497
Short name T32
Test name
Test status
Simulation time 26365227 ps
CPU time 1.04 seconds
Started Jul 19 06:27:30 PM PDT 24
Finished Jul 19 06:27:32 PM PDT 24
Peak memory 216260 kb
Host smart-71598e1f-b2d6-4fd9-9b76-4f6664a3ceb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98892497 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.98892497
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.3997990657
Short name T758
Test name
Test status
Simulation time 56733089 ps
CPU time 1.02 seconds
Started Jul 19 06:27:30 PM PDT 24
Finished Jul 19 06:27:32 PM PDT 24
Peak memory 207376 kb
Host smart-84df1a21-6a5c-48bd-ae99-3af0aa2d4816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997990657 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.3997990657
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.217850444
Short name T724
Test name
Test status
Simulation time 34579278 ps
CPU time 0.92 seconds
Started Jul 19 06:27:30 PM PDT 24
Finished Jul 19 06:27:32 PM PDT 24
Peak memory 215556 kb
Host smart-ce1ee428-2481-4b94-8a79-7866f70aa44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217850444 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.217850444
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1457357876
Short name T797
Test name
Test status
Simulation time 311797802 ps
CPU time 5.85 seconds
Started Jul 19 06:27:29 PM PDT 24
Finished Jul 19 06:27:36 PM PDT 24
Peak memory 218704 kb
Host smart-004d31c1-11b4-4c75-8f20-9a1ca2034d59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457357876 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1457357876
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.3905427768
Short name T669
Test name
Test status
Simulation time 84794159732 ps
CPU time 1206.89 seconds
Started Jul 19 06:27:28 PM PDT 24
Finished Jul 19 06:47:36 PM PDT 24
Peak memory 224604 kb
Host smart-ee900b24-f0c0-465e-9ac8-28302fe3d1f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905427768 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.3905427768
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.888708425
Short name T463
Test name
Test status
Simulation time 69599296 ps
CPU time 1.08 seconds
Started Jul 19 06:29:22 PM PDT 24
Finished Jul 19 06:29:30 PM PDT 24
Peak memory 219844 kb
Host smart-8075aa12-02d3-4308-95ad-923cfdae85ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888708425 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.888708425
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.3579748671
Short name T205
Test name
Test status
Simulation time 20656519 ps
CPU time 1.06 seconds
Started Jul 19 06:29:23 PM PDT 24
Finished Jul 19 06:29:31 PM PDT 24
Peak memory 219812 kb
Host smart-c8264c7f-a78e-44c0-9a38-6ec88237dad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579748671 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.3579748671
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.1326501329
Short name T670
Test name
Test status
Simulation time 134619240 ps
CPU time 1.07 seconds
Started Jul 19 06:29:18 PM PDT 24
Finished Jul 19 06:29:25 PM PDT 24
Peak memory 217696 kb
Host smart-6312e9a9-8eff-4d36-b1be-317bde1ab4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326501329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1326501329
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.2676674783
Short name T197
Test name
Test status
Simulation time 45049469 ps
CPU time 1.2 seconds
Started Jul 19 06:29:19 PM PDT 24
Finished Jul 19 06:29:27 PM PDT 24
Peak memory 218996 kb
Host smart-506a04d3-99c8-4dc6-b348-9646468b4b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676674783 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.2676674783
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.1863528126
Short name T218
Test name
Test status
Simulation time 44586446 ps
CPU time 0.86 seconds
Started Jul 19 06:29:19 PM PDT 24
Finished Jul 19 06:29:26 PM PDT 24
Peak memory 218852 kb
Host smart-9ae28c69-8c07-40a9-93e9-bb12d1c720ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863528126 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.1863528126
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.3190406662
Short name T959
Test name
Test status
Simulation time 99718996 ps
CPU time 1.26 seconds
Started Jul 19 06:29:19 PM PDT 24
Finished Jul 19 06:29:26 PM PDT 24
Peak memory 218900 kb
Host smart-4d84a104-60ca-4069-be1d-0486bd4327e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190406662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.3190406662
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.4088865270
Short name T854
Test name
Test status
Simulation time 68548131 ps
CPU time 1.25 seconds
Started Jul 19 06:29:16 PM PDT 24
Finished Jul 19 06:29:23 PM PDT 24
Peak memory 220136 kb
Host smart-19065060-0a23-4c13-a602-ea2fa4d61c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088865270 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.4088865270
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.4148436639
Short name T846
Test name
Test status
Simulation time 20054522 ps
CPU time 1.11 seconds
Started Jul 19 06:29:18 PM PDT 24
Finished Jul 19 06:29:25 PM PDT 24
Peak memory 218868 kb
Host smart-a0393f9e-fd98-4213-b250-5de4a966b472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148436639 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.4148436639
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.1232549627
Short name T660
Test name
Test status
Simulation time 39155683 ps
CPU time 1.29 seconds
Started Jul 19 06:29:17 PM PDT 24
Finished Jul 19 06:29:24 PM PDT 24
Peak memory 218940 kb
Host smart-7842a15c-a0d6-4b86-832c-4cafafb8d042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232549627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1232549627
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.3986025788
Short name T590
Test name
Test status
Simulation time 54499025 ps
CPU time 1.21 seconds
Started Jul 19 06:29:22 PM PDT 24
Finished Jul 19 06:29:31 PM PDT 24
Peak memory 219680 kb
Host smart-d5615099-4c48-4e54-ac09-3207360579af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986025788 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.3986025788
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.3445973331
Short name T127
Test name
Test status
Simulation time 24278545 ps
CPU time 1.04 seconds
Started Jul 19 06:29:22 PM PDT 24
Finished Jul 19 06:29:30 PM PDT 24
Peak memory 219988 kb
Host smart-4365b23c-f273-4a1f-b1f0-aeb6b50956fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445973331 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3445973331
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.3916677601
Short name T888
Test name
Test status
Simulation time 37448397 ps
CPU time 1.36 seconds
Started Jul 19 06:29:20 PM PDT 24
Finished Jul 19 06:29:29 PM PDT 24
Peak memory 215600 kb
Host smart-3532ff14-7a26-4173-9a3a-b55424dfe9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916677601 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.3916677601
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.1802368026
Short name T309
Test name
Test status
Simulation time 37003523 ps
CPU time 1.06 seconds
Started Jul 19 06:29:22 PM PDT 24
Finished Jul 19 06:29:30 PM PDT 24
Peak memory 218656 kb
Host smart-7c19cfb6-75d2-4cf0-8eb9-bb728920d8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802368026 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.1802368026
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.1582341919
Short name T966
Test name
Test status
Simulation time 44386806 ps
CPU time 1.25 seconds
Started Jul 19 06:29:19 PM PDT 24
Finished Jul 19 06:29:26 PM PDT 24
Peak memory 226092 kb
Host smart-f68a7413-b5df-4ce8-bdbb-6950103a2062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582341919 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.1582341919
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.4195254735
Short name T455
Test name
Test status
Simulation time 135929783 ps
CPU time 2.38 seconds
Started Jul 19 06:29:17 PM PDT 24
Finished Jul 19 06:29:25 PM PDT 24
Peak memory 219128 kb
Host smart-fe0de089-f5d6-49f8-a675-3660b2f3d92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195254735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.4195254735
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.2360065603
Short name T117
Test name
Test status
Simulation time 201852113 ps
CPU time 1.42 seconds
Started Jul 19 06:29:16 PM PDT 24
Finished Jul 19 06:29:22 PM PDT 24
Peak memory 219936 kb
Host smart-3de5d609-1555-416e-8abc-367f4dc4b063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360065603 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.2360065603
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.2220697988
Short name T134
Test name
Test status
Simulation time 26505118 ps
CPU time 1.24 seconds
Started Jul 19 06:29:21 PM PDT 24
Finished Jul 19 06:29:28 PM PDT 24
Peak memory 217520 kb
Host smart-f4f28c36-45ef-4b66-9cd2-caeddbd6c010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220697988 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2220697988
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.1171348439
Short name T539
Test name
Test status
Simulation time 40178929 ps
CPU time 1.17 seconds
Started Jul 19 06:29:16 PM PDT 24
Finished Jul 19 06:29:22 PM PDT 24
Peak memory 218968 kb
Host smart-7715f039-6ea8-4ede-bbb7-ba22a1891f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171348439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.1171348439
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.3403226892
Short name T140
Test name
Test status
Simulation time 24905274 ps
CPU time 1 seconds
Started Jul 19 06:29:19 PM PDT 24
Finished Jul 19 06:29:26 PM PDT 24
Peak memory 220068 kb
Host smart-2facb7ce-a0af-49c4-886d-ce4ab009a573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403226892 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3403226892
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.1002852003
Short name T328
Test name
Test status
Simulation time 63989273 ps
CPU time 2.32 seconds
Started Jul 19 06:29:15 PM PDT 24
Finished Jul 19 06:29:22 PM PDT 24
Peak memory 220228 kb
Host smart-83a54740-c4f5-49f3-920e-be166c7bbe98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002852003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.1002852003
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.1695219530
Short name T654
Test name
Test status
Simulation time 37303382 ps
CPU time 1.17 seconds
Started Jul 19 06:29:18 PM PDT 24
Finished Jul 19 06:29:25 PM PDT 24
Peak memory 220616 kb
Host smart-078b042e-25b8-4328-8c2b-a66c9f1c4570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695219530 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.1695219530
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.3929250895
Short name T207
Test name
Test status
Simulation time 19796821 ps
CPU time 1.1 seconds
Started Jul 19 06:29:17 PM PDT 24
Finished Jul 19 06:29:24 PM PDT 24
Peak memory 219796 kb
Host smart-df7db5cd-0586-4b5c-a869-6785822e19fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929250895 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.3929250895
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.3767538774
Short name T377
Test name
Test status
Simulation time 110915623 ps
CPU time 1.6 seconds
Started Jul 19 06:29:17 PM PDT 24
Finished Jul 19 06:29:23 PM PDT 24
Peak memory 219192 kb
Host smart-e9aac4e3-d369-4982-b789-237762e6f7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767538774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.3767538774
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.1368756962
Short name T991
Test name
Test status
Simulation time 28278115 ps
CPU time 1.2 seconds
Started Jul 19 06:29:18 PM PDT 24
Finished Jul 19 06:29:25 PM PDT 24
Peak memory 218928 kb
Host smart-1f819333-6210-4dee-8ae5-e248d1a7ca72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368756962 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.1368756962
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.4198553478
Short name T808
Test name
Test status
Simulation time 46719056 ps
CPU time 0.93 seconds
Started Jul 19 06:29:15 PM PDT 24
Finished Jul 19 06:29:21 PM PDT 24
Peak memory 218768 kb
Host smart-2a49dfdc-63e1-4119-9430-713e0d21b28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198553478 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.4198553478
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.20859136
Short name T41
Test name
Test status
Simulation time 94915252 ps
CPU time 1.34 seconds
Started Jul 19 06:29:22 PM PDT 24
Finished Jul 19 06:29:31 PM PDT 24
Peak memory 219176 kb
Host smart-c314d282-b843-4c81-aa29-3ef6010e696d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20859136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.20859136
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.3433676677
Short name T928
Test name
Test status
Simulation time 96995602 ps
CPU time 1.12 seconds
Started Jul 19 06:29:17 PM PDT 24
Finished Jul 19 06:29:23 PM PDT 24
Peak memory 218904 kb
Host smart-23a331cb-298b-4a25-87e3-670083548f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433676677 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.3433676677
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.1428317223
Short name T210
Test name
Test status
Simulation time 19436085 ps
CPU time 1.12 seconds
Started Jul 19 06:29:17 PM PDT 24
Finished Jul 19 06:29:24 PM PDT 24
Peak memory 218900 kb
Host smart-b8f98d44-f399-4963-8640-af7bd131ac2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428317223 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.1428317223
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.2826219613
Short name T420
Test name
Test status
Simulation time 31802858 ps
CPU time 1.32 seconds
Started Jul 19 06:29:17 PM PDT 24
Finished Jul 19 06:29:24 PM PDT 24
Peak memory 217832 kb
Host smart-34c39c16-8dee-4851-ab11-685f3cf2cda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826219613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.2826219613
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%