Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.69 98.25 93.91 97.02 92.44 96.37 99.77 92.08


Total test records in report: 1130
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T267 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1918616869 Jul 20 05:53:36 PM PDT 24 Jul 20 05:53:38 PM PDT 24 141629432 ps
T1017 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1965670948 Jul 20 05:53:40 PM PDT 24 Jul 20 05:53:42 PM PDT 24 37684054 ps
T281 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3609026231 Jul 20 05:53:19 PM PDT 24 Jul 20 05:53:22 PM PDT 24 267533944 ps
T1018 /workspace/coverage/cover_reg_top/37.edn_intr_test.1661538173 Jul 20 05:53:43 PM PDT 24 Jul 20 05:53:45 PM PDT 24 15273812 ps
T1019 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1822312666 Jul 20 05:53:19 PM PDT 24 Jul 20 05:53:22 PM PDT 24 18715076 ps
T1020 /workspace/coverage/cover_reg_top/36.edn_intr_test.628205857 Jul 20 05:53:48 PM PDT 24 Jul 20 05:53:50 PM PDT 24 22282583 ps
T1021 /workspace/coverage/cover_reg_top/31.edn_intr_test.1407511100 Jul 20 05:53:47 PM PDT 24 Jul 20 05:53:49 PM PDT 24 16225007 ps
T1022 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1611062616 Jul 20 05:53:00 PM PDT 24 Jul 20 05:53:02 PM PDT 24 68331258 ps
T1023 /workspace/coverage/cover_reg_top/32.edn_intr_test.2724313048 Jul 20 05:53:46 PM PDT 24 Jul 20 05:53:48 PM PDT 24 40466676 ps
T1024 /workspace/coverage/cover_reg_top/2.edn_tl_errors.210441488 Jul 20 05:53:01 PM PDT 24 Jul 20 05:53:05 PM PDT 24 87804840 ps
T1025 /workspace/coverage/cover_reg_top/16.edn_tl_errors.322269439 Jul 20 05:53:35 PM PDT 24 Jul 20 05:53:39 PM PDT 24 48353153 ps
T1026 /workspace/coverage/cover_reg_top/10.edn_intr_test.1251921095 Jul 20 05:53:16 PM PDT 24 Jul 20 05:53:19 PM PDT 24 240496336 ps
T1027 /workspace/coverage/cover_reg_top/34.edn_intr_test.680837943 Jul 20 05:53:44 PM PDT 24 Jul 20 05:53:46 PM PDT 24 61242340 ps
T1028 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1327955979 Jul 20 05:53:37 PM PDT 24 Jul 20 05:53:39 PM PDT 24 62267363 ps
T1029 /workspace/coverage/cover_reg_top/5.edn_intr_test.612643431 Jul 20 05:53:14 PM PDT 24 Jul 20 05:53:15 PM PDT 24 30532682 ps
T250 /workspace/coverage/cover_reg_top/10.edn_csr_rw.430424 Jul 20 05:53:22 PM PDT 24 Jul 20 05:53:25 PM PDT 24 58256947 ps
T1030 /workspace/coverage/cover_reg_top/42.edn_intr_test.391233116 Jul 20 05:53:46 PM PDT 24 Jul 20 05:53:48 PM PDT 24 14927808 ps
T1031 /workspace/coverage/cover_reg_top/7.edn_csr_rw.1727906734 Jul 20 05:53:22 PM PDT 24 Jul 20 05:53:25 PM PDT 24 14488770 ps
T1032 /workspace/coverage/cover_reg_top/40.edn_intr_test.3157964294 Jul 20 05:53:44 PM PDT 24 Jul 20 05:53:46 PM PDT 24 138699773 ps
T1033 /workspace/coverage/cover_reg_top/15.edn_intr_test.3538257236 Jul 20 05:53:36 PM PDT 24 Jul 20 05:53:37 PM PDT 24 49343164 ps
T1034 /workspace/coverage/cover_reg_top/18.edn_csr_rw.511164727 Jul 20 05:53:38 PM PDT 24 Jul 20 05:53:40 PM PDT 24 26351855 ps
T1035 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3033606270 Jul 20 05:53:43 PM PDT 24 Jul 20 05:53:45 PM PDT 24 33510900 ps
T251 /workspace/coverage/cover_reg_top/6.edn_csr_rw.450836061 Jul 20 05:53:20 PM PDT 24 Jul 20 05:53:23 PM PDT 24 29397067 ps
T1036 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1603371055 Jul 20 05:53:04 PM PDT 24 Jul 20 05:53:07 PM PDT 24 183591188 ps
T1037 /workspace/coverage/cover_reg_top/2.edn_intr_test.1059522869 Jul 20 05:53:08 PM PDT 24 Jul 20 05:53:10 PM PDT 24 49217121 ps
T1038 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.33615211 Jul 20 05:53:07 PM PDT 24 Jul 20 05:53:10 PM PDT 24 44812988 ps
T1039 /workspace/coverage/cover_reg_top/15.edn_csr_rw.535370826 Jul 20 05:53:36 PM PDT 24 Jul 20 05:53:37 PM PDT 24 15512234 ps
T1040 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3259064156 Jul 20 05:53:11 PM PDT 24 Jul 20 05:53:13 PM PDT 24 42244824 ps
T282 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3010492244 Jul 20 05:53:36 PM PDT 24 Jul 20 05:53:40 PM PDT 24 100125187 ps
T1041 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2041461023 Jul 20 05:53:38 PM PDT 24 Jul 20 05:53:40 PM PDT 24 16319681 ps
T1042 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1868435886 Jul 20 05:53:13 PM PDT 24 Jul 20 05:53:16 PM PDT 24 70443561 ps
T1043 /workspace/coverage/cover_reg_top/7.edn_intr_test.293772155 Jul 20 05:53:19 PM PDT 24 Jul 20 05:53:22 PM PDT 24 14671583 ps
T1044 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2740248829 Jul 20 05:53:17 PM PDT 24 Jul 20 05:53:19 PM PDT 24 100328632 ps
T252 /workspace/coverage/cover_reg_top/4.edn_csr_rw.2001409371 Jul 20 05:53:17 PM PDT 24 Jul 20 05:53:19 PM PDT 24 13966529 ps
T1045 /workspace/coverage/cover_reg_top/16.edn_csr_rw.1432679754 Jul 20 05:53:36 PM PDT 24 Jul 20 05:53:38 PM PDT 24 13103788 ps
T1046 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1169019329 Jul 20 05:53:44 PM PDT 24 Jul 20 05:53:46 PM PDT 24 69935983 ps
T1047 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2434072873 Jul 20 05:53:27 PM PDT 24 Jul 20 05:53:29 PM PDT 24 75900806 ps
T1048 /workspace/coverage/cover_reg_top/9.edn_csr_rw.3201123707 Jul 20 05:53:17 PM PDT 24 Jul 20 05:53:19 PM PDT 24 34364037 ps
T1049 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.352854816 Jul 20 05:53:02 PM PDT 24 Jul 20 05:53:08 PM PDT 24 180931032 ps
T1050 /workspace/coverage/cover_reg_top/44.edn_intr_test.403992119 Jul 20 05:53:42 PM PDT 24 Jul 20 05:53:43 PM PDT 24 12952346 ps
T1051 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3305550227 Jul 20 05:53:36 PM PDT 24 Jul 20 05:53:38 PM PDT 24 66508194 ps
T1052 /workspace/coverage/cover_reg_top/38.edn_intr_test.3443946529 Jul 20 05:53:45 PM PDT 24 Jul 20 05:53:47 PM PDT 24 23662820 ps
T1053 /workspace/coverage/cover_reg_top/28.edn_intr_test.67826210 Jul 20 05:53:46 PM PDT 24 Jul 20 05:53:49 PM PDT 24 15073200 ps
T1054 /workspace/coverage/cover_reg_top/8.edn_csr_rw.342866727 Jul 20 05:53:20 PM PDT 24 Jul 20 05:53:23 PM PDT 24 38417553 ps
T1055 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.4228816118 Jul 20 05:53:32 PM PDT 24 Jul 20 05:53:34 PM PDT 24 23827288 ps
T1056 /workspace/coverage/cover_reg_top/10.edn_tl_errors.429278911 Jul 20 05:53:22 PM PDT 24 Jul 20 05:53:27 PM PDT 24 45077389 ps
T1057 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.34044336 Jul 20 05:53:20 PM PDT 24 Jul 20 05:53:23 PM PDT 24 244846265 ps
T1058 /workspace/coverage/cover_reg_top/12.edn_tl_errors.3147988383 Jul 20 05:53:36 PM PDT 24 Jul 20 05:53:41 PM PDT 24 222340774 ps
T1059 /workspace/coverage/cover_reg_top/18.edn_tl_errors.3771629049 Jul 20 05:53:36 PM PDT 24 Jul 20 05:53:41 PM PDT 24 818156640 ps
T279 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3163648124 Jul 20 05:53:28 PM PDT 24 Jul 20 05:53:31 PM PDT 24 80315213 ps
T1060 /workspace/coverage/cover_reg_top/41.edn_intr_test.1102347319 Jul 20 05:53:48 PM PDT 24 Jul 20 05:53:50 PM PDT 24 12900402 ps
T1061 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.4098403215 Jul 20 05:53:13 PM PDT 24 Jul 20 05:53:15 PM PDT 24 44192434 ps
T1062 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3289977425 Jul 20 05:53:01 PM PDT 24 Jul 20 05:53:03 PM PDT 24 58366120 ps
T1063 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3880558465 Jul 20 05:53:05 PM PDT 24 Jul 20 05:53:08 PM PDT 24 82898201 ps
T1064 /workspace/coverage/cover_reg_top/5.edn_tl_errors.4575460 Jul 20 05:53:10 PM PDT 24 Jul 20 05:53:14 PM PDT 24 67616693 ps
T1065 /workspace/coverage/cover_reg_top/39.edn_intr_test.2640599251 Jul 20 05:53:43 PM PDT 24 Jul 20 05:53:45 PM PDT 24 32795377 ps
T1066 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3607883708 Jul 20 05:53:12 PM PDT 24 Jul 20 05:53:15 PM PDT 24 131772761 ps
T1067 /workspace/coverage/cover_reg_top/6.edn_tl_errors.1330544293 Jul 20 05:53:19 PM PDT 24 Jul 20 05:53:22 PM PDT 24 130643709 ps
T1068 /workspace/coverage/cover_reg_top/43.edn_intr_test.1583471685 Jul 20 05:53:43 PM PDT 24 Jul 20 05:53:45 PM PDT 24 31596547 ps
T1069 /workspace/coverage/cover_reg_top/19.edn_intr_test.234130554 Jul 20 05:53:43 PM PDT 24 Jul 20 05:53:45 PM PDT 24 44472294 ps
T1070 /workspace/coverage/cover_reg_top/19.edn_csr_rw.4120212696 Jul 20 05:53:45 PM PDT 24 Jul 20 05:53:47 PM PDT 24 15184546 ps
T1071 /workspace/coverage/cover_reg_top/2.edn_csr_rw.1891822846 Jul 20 05:53:03 PM PDT 24 Jul 20 05:53:05 PM PDT 24 26384460 ps
T1072 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1465960017 Jul 20 05:53:14 PM PDT 24 Jul 20 05:53:17 PM PDT 24 126879101 ps
T1073 /workspace/coverage/cover_reg_top/8.edn_tl_errors.132357 Jul 20 05:53:24 PM PDT 24 Jul 20 05:53:27 PM PDT 24 175905243 ps
T1074 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2466156271 Jul 20 05:53:16 PM PDT 24 Jul 20 05:53:20 PM PDT 24 114531469 ps
T1075 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.507243767 Jul 20 05:53:31 PM PDT 24 Jul 20 05:53:33 PM PDT 24 85980222 ps
T1076 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.264391684 Jul 20 05:53:08 PM PDT 24 Jul 20 05:53:14 PM PDT 24 596073628 ps
T253 /workspace/coverage/cover_reg_top/1.edn_csr_rw.1729891287 Jul 20 05:53:03 PM PDT 24 Jul 20 05:53:04 PM PDT 24 67708532 ps
T1077 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3592338060 Jul 20 05:53:36 PM PDT 24 Jul 20 05:53:38 PM PDT 24 72256582 ps
T1078 /workspace/coverage/cover_reg_top/7.edn_tl_errors.531563117 Jul 20 05:53:21 PM PDT 24 Jul 20 05:53:25 PM PDT 24 205225491 ps
T1079 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2911494357 Jul 20 05:53:03 PM PDT 24 Jul 20 05:53:05 PM PDT 24 185672035 ps
T1080 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2605831112 Jul 20 05:53:20 PM PDT 24 Jul 20 05:53:23 PM PDT 24 142377739 ps
T1081 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3394797643 Jul 20 05:53:38 PM PDT 24 Jul 20 05:53:41 PM PDT 24 78626371 ps
T1082 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.4269304313 Jul 20 05:53:30 PM PDT 24 Jul 20 05:53:33 PM PDT 24 174828557 ps
T1083 /workspace/coverage/cover_reg_top/3.edn_tl_errors.2510600014 Jul 20 05:53:08 PM PDT 24 Jul 20 05:53:13 PM PDT 24 184915867 ps
T1084 /workspace/coverage/cover_reg_top/27.edn_intr_test.3043678131 Jul 20 05:53:47 PM PDT 24 Jul 20 05:53:49 PM PDT 24 11935552 ps
T1085 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.4138921921 Jul 20 05:53:20 PM PDT 24 Jul 20 05:53:23 PM PDT 24 52175647 ps
T254 /workspace/coverage/cover_reg_top/12.edn_csr_rw.319651708 Jul 20 05:53:37 PM PDT 24 Jul 20 05:53:38 PM PDT 24 34660208 ps
T1086 /workspace/coverage/cover_reg_top/47.edn_intr_test.4288919411 Jul 20 05:53:42 PM PDT 24 Jul 20 05:53:43 PM PDT 24 18689407 ps
T1087 /workspace/coverage/cover_reg_top/4.edn_intr_test.866258485 Jul 20 05:53:11 PM PDT 24 Jul 20 05:53:13 PM PDT 24 30124936 ps
T1088 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.860418150 Jul 20 05:53:13 PM PDT 24 Jul 20 05:53:16 PM PDT 24 79412221 ps
T1089 /workspace/coverage/cover_reg_top/25.edn_intr_test.2875387803 Jul 20 05:53:44 PM PDT 24 Jul 20 05:53:46 PM PDT 24 107277314 ps
T1090 /workspace/coverage/cover_reg_top/13.edn_tl_errors.889247778 Jul 20 05:53:37 PM PDT 24 Jul 20 05:53:42 PM PDT 24 686427852 ps
T1091 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2464609803 Jul 20 05:53:32 PM PDT 24 Jul 20 05:53:34 PM PDT 24 17790105 ps
T1092 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2591745423 Jul 20 05:53:04 PM PDT 24 Jul 20 05:53:12 PM PDT 24 503787485 ps
T1093 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3753994826 Jul 20 05:53:30 PM PDT 24 Jul 20 05:53:31 PM PDT 24 19089148 ps
T1094 /workspace/coverage/cover_reg_top/12.edn_intr_test.2517090263 Jul 20 05:53:26 PM PDT 24 Jul 20 05:53:28 PM PDT 24 14615128 ps
T1095 /workspace/coverage/cover_reg_top/19.edn_tl_errors.3967234301 Jul 20 05:53:34 PM PDT 24 Jul 20 05:53:38 PM PDT 24 92298551 ps
T255 /workspace/coverage/cover_reg_top/13.edn_csr_rw.2296146227 Jul 20 05:53:31 PM PDT 24 Jul 20 05:53:33 PM PDT 24 79068910 ps
T1096 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1103210829 Jul 20 05:53:26 PM PDT 24 Jul 20 05:53:28 PM PDT 24 21899670 ps
T1097 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1150695562 Jul 20 05:53:11 PM PDT 24 Jul 20 05:53:13 PM PDT 24 25113149 ps
T1098 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.173139792 Jul 20 05:53:20 PM PDT 24 Jul 20 05:53:23 PM PDT 24 223273057 ps
T1099 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.568316705 Jul 20 05:53:24 PM PDT 24 Jul 20 05:53:26 PM PDT 24 23654245 ps
T1100 /workspace/coverage/cover_reg_top/0.edn_intr_test.2875031026 Jul 20 05:53:05 PM PDT 24 Jul 20 05:53:07 PM PDT 24 36001283 ps
T1101 /workspace/coverage/cover_reg_top/11.edn_intr_test.4039276994 Jul 20 05:53:36 PM PDT 24 Jul 20 05:53:38 PM PDT 24 84014144 ps
T1102 /workspace/coverage/cover_reg_top/4.edn_tl_errors.2221686822 Jul 20 05:53:17 PM PDT 24 Jul 20 05:53:21 PM PDT 24 162700456 ps
T1103 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2780300025 Jul 20 05:53:44 PM PDT 24 Jul 20 05:53:46 PM PDT 24 104283326 ps
T1104 /workspace/coverage/cover_reg_top/35.edn_intr_test.2826284551 Jul 20 05:53:42 PM PDT 24 Jul 20 05:53:44 PM PDT 24 51278136 ps
T256 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.313288314 Jul 20 05:53:06 PM PDT 24 Jul 20 05:53:09 PM PDT 24 17933303 ps
T1105 /workspace/coverage/cover_reg_top/20.edn_intr_test.3279126444 Jul 20 05:53:46 PM PDT 24 Jul 20 05:53:48 PM PDT 24 36868381 ps
T1106 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1044634972 Jul 20 05:53:02 PM PDT 24 Jul 20 05:53:03 PM PDT 24 34108989 ps
T257 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2245215983 Jul 20 05:53:16 PM PDT 24 Jul 20 05:53:19 PM PDT 24 139567046 ps
T1107 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2413297903 Jul 20 05:53:19 PM PDT 24 Jul 20 05:53:23 PM PDT 24 332909298 ps
T1108 /workspace/coverage/cover_reg_top/46.edn_intr_test.3107462477 Jul 20 05:53:46 PM PDT 24 Jul 20 05:53:48 PM PDT 24 20428268 ps
T1109 /workspace/coverage/cover_reg_top/11.edn_tl_errors.2029234049 Jul 20 05:53:30 PM PDT 24 Jul 20 05:53:34 PM PDT 24 46612029 ps
T1110 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.168923353 Jul 20 05:53:38 PM PDT 24 Jul 20 05:53:40 PM PDT 24 26759569 ps
T1111 /workspace/coverage/cover_reg_top/0.edn_tl_errors.1939085866 Jul 20 05:53:04 PM PDT 24 Jul 20 05:53:06 PM PDT 24 104516009 ps
T258 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3109908732 Jul 20 05:53:03 PM PDT 24 Jul 20 05:53:10 PM PDT 24 265079757 ps
T1112 /workspace/coverage/cover_reg_top/45.edn_intr_test.3912807070 Jul 20 05:53:47 PM PDT 24 Jul 20 05:53:49 PM PDT 24 12729480 ps
T1113 /workspace/coverage/cover_reg_top/9.edn_intr_test.1346339288 Jul 20 05:53:16 PM PDT 24 Jul 20 05:53:19 PM PDT 24 37563621 ps
T1114 /workspace/coverage/cover_reg_top/14.edn_tl_errors.3061288554 Jul 20 05:53:32 PM PDT 24 Jul 20 05:53:37 PM PDT 24 242845501 ps
T1115 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.4041639180 Jul 20 05:53:23 PM PDT 24 Jul 20 05:53:26 PM PDT 24 70142574 ps
T1116 /workspace/coverage/cover_reg_top/8.edn_intr_test.1181522712 Jul 20 05:53:17 PM PDT 24 Jul 20 05:53:19 PM PDT 24 156060672 ps
T259 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3816352210 Jul 20 05:53:11 PM PDT 24 Jul 20 05:53:13 PM PDT 24 20603716 ps
T1117 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2836233070 Jul 20 05:53:13 PM PDT 24 Jul 20 05:53:14 PM PDT 24 55031809 ps
T1118 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1138991894 Jul 20 05:53:10 PM PDT 24 Jul 20 05:53:15 PM PDT 24 200936116 ps
T1119 /workspace/coverage/cover_reg_top/1.edn_intr_test.664530328 Jul 20 05:53:08 PM PDT 24 Jul 20 05:53:10 PM PDT 24 15241308 ps
T1120 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.668831623 Jul 20 05:53:29 PM PDT 24 Jul 20 05:53:31 PM PDT 24 113343638 ps
T1121 /workspace/coverage/cover_reg_top/26.edn_intr_test.3401863271 Jul 20 05:53:45 PM PDT 24 Jul 20 05:53:47 PM PDT 24 12222019 ps
T1122 /workspace/coverage/cover_reg_top/14.edn_intr_test.1442473693 Jul 20 05:53:29 PM PDT 24 Jul 20 05:53:30 PM PDT 24 34325206 ps
T1123 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2896494262 Jul 20 05:53:20 PM PDT 24 Jul 20 05:53:23 PM PDT 24 218438228 ps
T1124 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1995510870 Jul 20 05:53:29 PM PDT 24 Jul 20 05:53:31 PM PDT 24 48091974 ps
T1125 /workspace/coverage/cover_reg_top/17.edn_csr_rw.1019931616 Jul 20 05:53:40 PM PDT 24 Jul 20 05:53:41 PM PDT 24 19400186 ps
T1126 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1314146297 Jul 20 05:53:37 PM PDT 24 Jul 20 05:53:40 PM PDT 24 232366723 ps
T1127 /workspace/coverage/cover_reg_top/17.edn_tl_errors.3558036846 Jul 20 05:53:36 PM PDT 24 Jul 20 05:53:40 PM PDT 24 42618512 ps
T1128 /workspace/coverage/cover_reg_top/0.edn_csr_rw.2064661674 Jul 20 05:53:04 PM PDT 24 Jul 20 05:53:05 PM PDT 24 29227573 ps
T1129 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1930518160 Jul 20 05:53:11 PM PDT 24 Jul 20 05:53:13 PM PDT 24 215835124 ps
T260 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2193310496 Jul 20 05:53:06 PM PDT 24 Jul 20 05:53:08 PM PDT 24 26479609 ps
T261 /workspace/coverage/cover_reg_top/5.edn_csr_rw.207449460 Jul 20 05:53:11 PM PDT 24 Jul 20 05:53:13 PM PDT 24 74776890 ps
T1130 /workspace/coverage/cover_reg_top/30.edn_intr_test.1966849142 Jul 20 05:53:42 PM PDT 24 Jul 20 05:53:43 PM PDT 24 28722686 ps

Test location /workspace/coverage/default/212.edn_genbits.3898708819
Short name T9
Test name
Test status
Simulation time 41785884 ps
CPU time 1.8 seconds
Started Jul 20 06:51:28 PM PDT 24
Finished Jul 20 06:51:36 PM PDT 24
Peak memory 220336 kb
Host smart-2c7ebba9-b5f0-4a65-9118-3a96965c3908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898708819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.3898708819
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.1434371997
Short name T5
Test name
Test status
Simulation time 110283534233 ps
CPU time 2466.67 seconds
Started Jul 20 06:50:21 PM PDT 24
Finished Jul 20 07:31:29 PM PDT 24
Peak memory 237580 kb
Host smart-82ee816a-c314-4c40-9f33-b77d319c27ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434371997 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.1434371997
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/154.edn_alert.3665729148
Short name T10
Test name
Test status
Simulation time 108433950 ps
CPU time 1.25 seconds
Started Jul 20 06:51:24 PM PDT 24
Finished Jul 20 06:51:30 PM PDT 24
Peak memory 218916 kb
Host smart-98c40bc9-deb5-4523-88c7-508f276f4625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665729148 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.3665729148
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/2.edn_sec_cm.857025032
Short name T16
Test name
Test status
Simulation time 4518371390 ps
CPU time 9.23 seconds
Started Jul 20 06:49:05 PM PDT 24
Finished Jul 20 06:49:16 PM PDT 24
Peak memory 238212 kb
Host smart-7544f3ee-3f84-4720-9bc3-54c7ace992e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857025032 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.857025032
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/129.edn_genbits.823292688
Short name T39
Test name
Test status
Simulation time 231476470 ps
CPU time 1.4 seconds
Started Jul 20 06:51:10 PM PDT 24
Finished Jul 20 06:51:12 PM PDT 24
Peak memory 217704 kb
Host smart-dc1431fb-9c0a-47ab-9d61-a84c967d38de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823292688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.823292688
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.115608158
Short name T65
Test name
Test status
Simulation time 27684000 ps
CPU time 1.06 seconds
Started Jul 20 06:49:53 PM PDT 24
Finished Jul 20 06:49:56 PM PDT 24
Peak memory 218460 kb
Host smart-3dd245cd-39c1-41fa-91eb-063cc4de39bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115608158 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_di
sable_auto_req_mode.115608158
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_sec_cm.226458665
Short name T62
Test name
Test status
Simulation time 446087196 ps
CPU time 4.04 seconds
Started Jul 20 06:49:01 PM PDT 24
Finished Jul 20 06:49:06 PM PDT 24
Peak memory 235624 kb
Host smart-156652db-aaf9-42ea-8e14-2eeedf3e6208
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226458665 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.226458665
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/14.edn_err.359351077
Short name T29
Test name
Test status
Simulation time 25812113 ps
CPU time 0.99 seconds
Started Jul 20 06:49:37 PM PDT 24
Finished Jul 20 06:49:39 PM PDT 24
Peak memory 218480 kb
Host smart-e85df857-8834-4b5c-8c7a-94d97b25c578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359351077 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.359351077
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/158.edn_alert.288638333
Short name T43
Test name
Test status
Simulation time 80993818 ps
CPU time 1.22 seconds
Started Jul 20 06:51:24 PM PDT 24
Finished Jul 20 06:51:30 PM PDT 24
Peak memory 219636 kb
Host smart-db6522d9-a2d1-4508-a3d7-3787626f22e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288638333 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.288638333
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.2967477330
Short name T35
Test name
Test status
Simulation time 48010592422 ps
CPU time 894.41 seconds
Started Jul 20 06:50:07 PM PDT 24
Finished Jul 20 07:05:03 PM PDT 24
Peak memory 219804 kb
Host smart-86e90ec7-d141-4430-be5b-f997a6dff708
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967477330 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.2967477330
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.edn_regwen.1074003519
Short name T23
Test name
Test status
Simulation time 42249036 ps
CPU time 0.88 seconds
Started Jul 20 06:49:22 PM PDT 24
Finished Jul 20 06:49:24 PM PDT 24
Peak memory 207356 kb
Host smart-3334f6a1-71a5-463b-b670-f3b0a21a09a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074003519 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.1074003519
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/29.edn_disable.1498364979
Short name T79
Test name
Test status
Simulation time 40628215 ps
CPU time 0.9 seconds
Started Jul 20 06:49:54 PM PDT 24
Finished Jul 20 06:49:56 PM PDT 24
Peak memory 216500 kb
Host smart-c9cf6e45-5cb8-49d5-8a8a-61b8dd9d96e3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498364979 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1498364979
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/60.edn_alert.621541621
Short name T197
Test name
Test status
Simulation time 249081472 ps
CPU time 1.35 seconds
Started Jul 20 06:50:31 PM PDT 24
Finished Jul 20 06:50:34 PM PDT 24
Peak memory 219996 kb
Host smart-b823621f-c258-4bc7-9ca0-5a57d6f4559f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621541621 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.621541621
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/20.edn_err.3270659375
Short name T15
Test name
Test status
Simulation time 26409767 ps
CPU time 0.99 seconds
Started Jul 20 06:49:44 PM PDT 24
Finished Jul 20 06:49:47 PM PDT 24
Peak memory 224092 kb
Host smart-bcdeacf2-168e-4419-922c-ccf5205ae082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270659375 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.3270659375
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.770028454
Short name T280
Test name
Test status
Simulation time 148983230 ps
CPU time 2.96 seconds
Started Jul 20 05:53:04 PM PDT 24
Finished Jul 20 05:53:08 PM PDT 24
Peak memory 206864 kb
Host smart-1d3e9e2a-868a-4221-9be4-3222e2170d7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770028454 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.770028454
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/default/152.edn_alert.3485519519
Short name T654
Test name
Test status
Simulation time 65874598 ps
CPU time 1.13 seconds
Started Jul 20 06:51:20 PM PDT 24
Finished Jul 20 06:51:23 PM PDT 24
Peak memory 220440 kb
Host smart-2d554ace-64ef-46c6-9258-3e5baccd5010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485519519 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.3485519519
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert.1406754034
Short name T2
Test name
Test status
Simulation time 23292817 ps
CPU time 1.19 seconds
Started Jul 20 06:49:43 PM PDT 24
Finished Jul 20 06:49:47 PM PDT 24
Peak memory 219988 kb
Host smart-98b4ce86-a91f-4339-9dcd-4f0ed4d3b73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406754034 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.1406754034
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.2989431935
Short name T14
Test name
Test status
Simulation time 144426704 ps
CPU time 1.84 seconds
Started Jul 20 06:50:54 PM PDT 24
Finished Jul 20 06:50:57 PM PDT 24
Peak memory 220144 kb
Host smart-c0093a28-54e7-4fac-bd5f-1a0446847ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989431935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.2989431935
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_disable.1351228116
Short name T190
Test name
Test status
Simulation time 20121418 ps
CPU time 0.87 seconds
Started Jul 20 06:50:18 PM PDT 24
Finished Jul 20 06:50:21 PM PDT 24
Peak memory 216588 kb
Host smart-d01f0707-f52b-4c1f-b382-7e0a047793dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351228116 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1351228116
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/40.edn_genbits.159588058
Short name T44
Test name
Test status
Simulation time 48888300 ps
CPU time 1.46 seconds
Started Jul 20 06:50:07 PM PDT 24
Finished Jul 20 06:50:09 PM PDT 24
Peak memory 219108 kb
Host smart-67e6a856-30a0-49f4-8543-e45734eb5442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159588058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.159588058
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.588521503
Short name T968
Test name
Test status
Simulation time 57148409 ps
CPU time 1.26 seconds
Started Jul 20 06:49:02 PM PDT 24
Finished Jul 20 06:49:04 PM PDT 24
Peak memory 216912 kb
Host smart-835e7961-e39d-46d3-8dfe-5d0d5f27ab35
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588521503 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_dis
able_auto_req_mode.588521503
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.969543948
Short name T214
Test name
Test status
Simulation time 51588576 ps
CPU time 1.45 seconds
Started Jul 20 06:50:15 PM PDT 24
Finished Jul 20 06:50:18 PM PDT 24
Peak memory 217228 kb
Host smart-1b1b3093-6a5c-4b8b-bd1b-c59c4beb7e01
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969543948 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_di
sable_auto_req_mode.969543948
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.2296146227
Short name T255
Test name
Test status
Simulation time 79068910 ps
CPU time 0.98 seconds
Started Jul 20 05:53:31 PM PDT 24
Finished Jul 20 05:53:33 PM PDT 24
Peak memory 206820 kb
Host smart-5258deca-9946-4fba-b18d-af5c5c1dd087
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296146227 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.2296146227
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/default/37.edn_alert.4046880319
Short name T121
Test name
Test status
Simulation time 32382595 ps
CPU time 1.31 seconds
Started Jul 20 06:50:07 PM PDT 24
Finished Jul 20 06:50:10 PM PDT 24
Peak memory 220040 kb
Host smart-e0b17a43-f937-4b1d-8556-96ff526221df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046880319 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.4046880319
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1951948610
Short name T495
Test name
Test status
Simulation time 33875251 ps
CPU time 1.14 seconds
Started Jul 20 06:49:21 PM PDT 24
Finished Jul 20 06:49:23 PM PDT 24
Peak memory 217212 kb
Host smart-f10ee0bd-a43a-4938-95c9-277649a99c0d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951948610 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1951948610
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/100.edn_alert.3631800618
Short name T155
Test name
Test status
Simulation time 95235471 ps
CPU time 1.39 seconds
Started Jul 20 06:51:01 PM PDT 24
Finished Jul 20 06:51:04 PM PDT 24
Peak memory 218752 kb
Host smart-5656fb10-d13f-497c-aacc-dddcbd3bc721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631800618 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.3631800618
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/187.edn_alert.3280454021
Short name T148
Test name
Test status
Simulation time 89713283 ps
CPU time 1.27 seconds
Started Jul 20 06:51:29 PM PDT 24
Finished Jul 20 06:51:36 PM PDT 24
Peak memory 219880 kb
Host smart-41857d48-d514-4210-93a6-4e6dbaab638e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280454021 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.3280454021
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/113.edn_alert.4240666707
Short name T561
Test name
Test status
Simulation time 90327088 ps
CPU time 1.46 seconds
Started Jul 20 06:50:54 PM PDT 24
Finished Jul 20 06:50:57 PM PDT 24
Peak memory 220056 kb
Host smart-14226707-ffbe-4511-9d79-731c2994d5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240666707 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.4240666707
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/115.edn_alert.482430853
Short name T289
Test name
Test status
Simulation time 35839262 ps
CPU time 1.23 seconds
Started Jul 20 06:51:02 PM PDT 24
Finished Jul 20 06:51:04 PM PDT 24
Peak memory 221308 kb
Host smart-2384ac19-90e5-4ab8-a3cd-4dfec902a18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482430853 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.482430853
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/121.edn_alert.2945926120
Short name T574
Test name
Test status
Simulation time 42338644 ps
CPU time 1.16 seconds
Started Jul 20 06:50:52 PM PDT 24
Finished Jul 20 06:50:55 PM PDT 24
Peak memory 218836 kb
Host smart-188a7b57-aeb3-4b30-86fb-9a98e12b551c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945926120 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.2945926120
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/143.edn_alert.3427508543
Short name T186
Test name
Test status
Simulation time 63679460 ps
CPU time 1.17 seconds
Started Jul 20 06:51:20 PM PDT 24
Finished Jul 20 06:51:23 PM PDT 24
Peak memory 219928 kb
Host smart-f616cadd-59d3-4a78-aa93-5bf85ffb6ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427508543 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.3427508543
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/15.edn_intr.2106156950
Short name T30
Test name
Test status
Simulation time 27754428 ps
CPU time 0.97 seconds
Started Jul 20 06:49:31 PM PDT 24
Finished Jul 20 06:49:34 PM PDT 24
Peak memory 216204 kb
Host smart-e5b0c88b-b0fe-4808-b867-95a3fb0e5f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106156950 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2106156950
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/146.edn_genbits.2690323306
Short name T328
Test name
Test status
Simulation time 101095754 ps
CPU time 1.26 seconds
Started Jul 20 06:51:25 PM PDT 24
Finished Jul 20 06:51:31 PM PDT 24
Peak memory 220212 kb
Host smart-8dcc4374-8c45-4fb6-b7da-864c4955229a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690323306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2690323306
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_disable.3656683834
Short name T159
Test name
Test status
Simulation time 32491434 ps
CPU time 0.88 seconds
Started Jul 20 06:49:03 PM PDT 24
Finished Jul 20 06:49:05 PM PDT 24
Peak memory 215696 kb
Host smart-53409ed1-139b-4f7d-b886-2ca9efd4b708
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656683834 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3656683834
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/135.edn_alert.4126653653
Short name T942
Test name
Test status
Simulation time 123837084 ps
CPU time 1.36 seconds
Started Jul 20 06:51:01 PM PDT 24
Finished Jul 20 06:51:03 PM PDT 24
Peak memory 220144 kb
Host smart-c953838b-3394-44f8-961d-ae9819d2e357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126653653 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.4126653653
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/84.edn_alert.2374632509
Short name T139
Test name
Test status
Simulation time 87237999 ps
CPU time 1.17 seconds
Started Jul 20 06:50:48 PM PDT 24
Finished Jul 20 06:50:50 PM PDT 24
Peak memory 220112 kb
Host smart-81394ed2-6bbf-4496-bffd-cf51fe66de9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374632509 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.2374632509
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/2.edn_intr.2867310917
Short name T97
Test name
Test status
Simulation time 26884545 ps
CPU time 0.99 seconds
Started Jul 20 06:48:59 PM PDT 24
Finished Jul 20 06:49:02 PM PDT 24
Peak memory 216164 kb
Host smart-d0fb7932-95a4-48a4-8525-00dd513eedbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867310917 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.2867310917
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/112.edn_alert.2634842527
Short name T178
Test name
Test status
Simulation time 30154291 ps
CPU time 1.31 seconds
Started Jul 20 06:50:54 PM PDT 24
Finished Jul 20 06:50:57 PM PDT 24
Peak memory 219884 kb
Host smart-b6c28663-e0c5-4023-a697-aafe76575142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634842527 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.2634842527
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.233206874
Short name T126
Test name
Test status
Simulation time 86310009 ps
CPU time 1.11 seconds
Started Jul 20 06:49:22 PM PDT 24
Finished Jul 20 06:49:24 PM PDT 24
Peak memory 217164 kb
Host smart-85a622be-fd3a-4c02-888e-41f35f93ed77
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233206874 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_di
sable_auto_req_mode.233206874
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.1416574222
Short name T864
Test name
Test status
Simulation time 85134304 ps
CPU time 1.14 seconds
Started Jul 20 06:49:26 PM PDT 24
Finished Jul 20 06:49:28 PM PDT 24
Peak memory 217196 kb
Host smart-d5c98b08-20f6-4e4a-8e53-62a5cecfa609
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416574222 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.1416574222
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/144.edn_alert.566390546
Short name T134
Test name
Test status
Simulation time 23883616 ps
CPU time 1.14 seconds
Started Jul 20 06:51:11 PM PDT 24
Finished Jul 20 06:51:13 PM PDT 24
Peak memory 218920 kb
Host smart-ff6e3753-2216-4fd6-ac93-e77ba10fe46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566390546 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.566390546
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/18.edn_err.3519344876
Short name T198
Test name
Test status
Simulation time 38381792 ps
CPU time 0.86 seconds
Started Jul 20 06:49:31 PM PDT 24
Finished Jul 20 06:49:33 PM PDT 24
Peak memory 219604 kb
Host smart-9760c61a-cb95-4b99-8d26-576c49ac6663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519344876 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.3519344876
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/26.edn_err.2411980589
Short name T195
Test name
Test status
Simulation time 18762736 ps
CPU time 1.1 seconds
Started Jul 20 06:49:50 PM PDT 24
Finished Jul 20 06:49:53 PM PDT 24
Peak memory 218892 kb
Host smart-30f71118-ceb4-487b-87a6-66e8fdf21ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411980589 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.2411980589
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/3.edn_disable.1204729795
Short name T200
Test name
Test status
Simulation time 15358464 ps
CPU time 0.96 seconds
Started Jul 20 06:49:05 PM PDT 24
Finished Jul 20 06:49:08 PM PDT 24
Peak memory 216572 kb
Host smart-231005f8-d426-48d7-9051-f6b8c02abd76
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204729795 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1204729795
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable.2262919709
Short name T206
Test name
Test status
Simulation time 20755773 ps
CPU time 0.88 seconds
Started Jul 20 06:49:51 PM PDT 24
Finished Jul 20 06:49:53 PM PDT 24
Peak memory 216536 kb
Host smart-d7ff4330-46bd-4bb5-822d-ac9eba9064e3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262919709 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.2262919709
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable.1065392775
Short name T182
Test name
Test status
Simulation time 11716813 ps
CPU time 0.93 seconds
Started Jul 20 06:49:58 PM PDT 24
Finished Jul 20 06:50:00 PM PDT 24
Peak memory 216648 kb
Host smart-840605cd-0a34-4e4c-9c0c-c66385eaabd2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065392775 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1065392775
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable.2319933144
Short name T210
Test name
Test status
Simulation time 16915905 ps
CPU time 0.86 seconds
Started Jul 20 06:50:10 PM PDT 24
Finished Jul 20 06:50:12 PM PDT 24
Peak memory 216604 kb
Host smart-a4d58da6-27d1-472c-b571-20005c09e6a0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319933144 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2319933144
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable.602237770
Short name T216
Test name
Test status
Simulation time 12850791 ps
CPU time 0.95 seconds
Started Jul 20 06:50:25 PM PDT 24
Finished Jul 20 06:50:28 PM PDT 24
Peak memory 216776 kb
Host smart-46e8cc8b-27b2-4a15-b329-93d03f7f10f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602237770 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.602237770
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/83.edn_genbits.3113406664
Short name T78
Test name
Test status
Simulation time 37343373 ps
CPU time 1.56 seconds
Started Jul 20 06:50:50 PM PDT 24
Finished Jul 20 06:50:53 PM PDT 24
Peak memory 218868 kb
Host smart-79352f86-b5c2-4968-aa61-1adc16099434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113406664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3113406664
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.45022750
Short name T228
Test name
Test status
Simulation time 28178158788 ps
CPU time 337.86 seconds
Started Jul 20 06:49:32 PM PDT 24
Finished Jul 20 06:55:12 PM PDT 24
Peak memory 218092 kb
Host smart-a7a3df62-c9dd-492d-9ad7-d2e8bc644cd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45022750 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.45022750
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/223.edn_genbits.969879172
Short name T84
Test name
Test status
Simulation time 35191521 ps
CPU time 1.48 seconds
Started Jul 20 06:51:32 PM PDT 24
Finished Jul 20 06:51:38 PM PDT 24
Peak memory 220088 kb
Host smart-773b0660-01b8-4074-b8a7-3302a6671d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969879172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.969879172
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert_test.669823324
Short name T375
Test name
Test status
Simulation time 46376891 ps
CPU time 0.99 seconds
Started Jul 20 06:49:26 PM PDT 24
Finished Jul 20 06:49:28 PM PDT 24
Peak memory 207132 kb
Host smart-cb470f47-f7c5-40e8-bbc2-79f34cfe99a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669823324 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.669823324
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/120.edn_genbits.1762423069
Short name T761
Test name
Test status
Simulation time 59276918 ps
CPU time 1.39 seconds
Started Jul 20 06:50:55 PM PDT 24
Finished Jul 20 06:50:58 PM PDT 24
Peak memory 219556 kb
Host smart-4fd4d664-03a7-4d44-af99-228307193c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762423069 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.1762423069
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.2012492454
Short name T736
Test name
Test status
Simulation time 49845088 ps
CPU time 1.18 seconds
Started Jul 20 06:51:01 PM PDT 24
Finished Jul 20 06:51:02 PM PDT 24
Peak memory 219272 kb
Host smart-42d39281-056c-4eba-9600-b504c0e32263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012492454 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.2012492454
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/3.edn_regwen.442068773
Short name T294
Test name
Test status
Simulation time 19639681 ps
CPU time 1.03 seconds
Started Jul 20 06:49:05 PM PDT 24
Finished Jul 20 06:49:09 PM PDT 24
Peak memory 207416 kb
Host smart-f58de3d4-05de-4e0e-b8e4-6b43a6533441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442068773 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.442068773
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/40.edn_intr.3234635707
Short name T99
Test name
Test status
Simulation time 34355768 ps
CPU time 0.92 seconds
Started Jul 20 06:50:16 PM PDT 24
Finished Jul 20 06:50:18 PM PDT 24
Peak memory 215900 kb
Host smart-43ce6202-7288-4eff-b9c5-90696f1affc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234635707 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.3234635707
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.780118933
Short name T247
Test name
Test status
Simulation time 27136526 ps
CPU time 0.97 seconds
Started Jul 20 05:53:11 PM PDT 24
Finished Jul 20 05:53:13 PM PDT 24
Peak memory 207028 kb
Host smart-79f67ce4-ad35-474f-81f5-87f242502e0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780118933 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_out
standing.780118933
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3163648124
Short name T279
Test name
Test status
Simulation time 80315213 ps
CPU time 2.43 seconds
Started Jul 20 05:53:28 PM PDT 24
Finished Jul 20 05:53:31 PM PDT 24
Peak memory 206888 kb
Host smart-2159856c-60fb-4e71-a42a-c58012f5a2c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163648124 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.3163648124
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/default/105.edn_genbits.2248629913
Short name T314
Test name
Test status
Simulation time 55241150 ps
CPU time 1.57 seconds
Started Jul 20 06:50:57 PM PDT 24
Finished Jul 20 06:51:00 PM PDT 24
Peak memory 218808 kb
Host smart-810d7c20-3af6-4de6-bda4-e9c2b2656c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248629913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.2248629913
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/110.edn_genbits.3401321473
Short name T76
Test name
Test status
Simulation time 69297679 ps
CPU time 1.11 seconds
Started Jul 20 06:50:58 PM PDT 24
Finished Jul 20 06:51:00 PM PDT 24
Peak memory 217664 kb
Host smart-22800add-dc89-43dd-bc00-c31a7877badf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401321473 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.3401321473
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.3162141678
Short name T712
Test name
Test status
Simulation time 87572938 ps
CPU time 1.31 seconds
Started Jul 20 06:50:54 PM PDT 24
Finished Jul 20 06:50:57 PM PDT 24
Peak memory 219528 kb
Host smart-95cf2fdc-0391-4877-8e2d-1acca12efbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162141678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.3162141678
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.2765760651
Short name T298
Test name
Test status
Simulation time 35594457 ps
CPU time 1.29 seconds
Started Jul 20 06:51:03 PM PDT 24
Finished Jul 20 06:51:05 PM PDT 24
Peak memory 217568 kb
Host smart-36aa237a-94f3-4d2e-a031-d334b144036b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765760651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.2765760651
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.3591631687
Short name T659
Test name
Test status
Simulation time 16761840088 ps
CPU time 399.59 seconds
Started Jul 20 06:49:29 PM PDT 24
Finished Jul 20 06:56:09 PM PDT 24
Peak memory 218548 kb
Host smart-1cfb5abf-958b-4e80-a08e-b8c79ffba938
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591631687 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.3591631687
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/148.edn_genbits.2980235790
Short name T11
Test name
Test status
Simulation time 57704551 ps
CPU time 1.36 seconds
Started Jul 20 06:51:14 PM PDT 24
Finished Jul 20 06:51:16 PM PDT 24
Peak memory 218836 kb
Host smart-8864215a-5aee-486f-9f45-d457595cf687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980235790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.2980235790
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2709311110
Short name T322
Test name
Test status
Simulation time 163489933329 ps
CPU time 904.37 seconds
Started Jul 20 06:49:31 PM PDT 24
Finished Jul 20 07:04:37 PM PDT 24
Peak memory 223176 kb
Host smart-a207b749-89eb-4cbf-9e79-df3fa481cfe5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709311110 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2709311110
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/161.edn_genbits.4220653824
Short name T304
Test name
Test status
Simulation time 34510741 ps
CPU time 1.37 seconds
Started Jul 20 06:51:21 PM PDT 24
Finished Jul 20 06:51:27 PM PDT 24
Peak memory 220032 kb
Host smart-be9e568b-16b9-467f-9cfa-f7ea4c619ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220653824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.4220653824
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_genbits.1869688918
Short name T307
Test name
Test status
Simulation time 408849245 ps
CPU time 1.29 seconds
Started Jul 20 06:49:43 PM PDT 24
Finished Jul 20 06:49:46 PM PDT 24
Peak memory 219468 kb
Host smart-76e7db93-c3fa-4d36-9f2c-a7de5e0a9f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869688918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.1869688918
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.532714619
Short name T302
Test name
Test status
Simulation time 168758312 ps
CPU time 1.74 seconds
Started Jul 20 06:51:33 PM PDT 24
Finished Jul 20 06:51:39 PM PDT 24
Peak memory 219088 kb
Host smart-903eec42-e197-4e6e-881c-c6badee36ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532714619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.532714619
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_genbits.3004627593
Short name T309
Test name
Test status
Simulation time 43099593 ps
CPU time 2 seconds
Started Jul 20 06:49:57 PM PDT 24
Finished Jul 20 06:50:01 PM PDT 24
Peak memory 218588 kb
Host smart-9113c00f-2d92-4a1c-ba2d-a7e57bdf51e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004627593 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.3004627593
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.34116009
Short name T951
Test name
Test status
Simulation time 28003121 ps
CPU time 0.97 seconds
Started Jul 20 06:49:01 PM PDT 24
Finished Jul 20 06:49:03 PM PDT 24
Peak memory 216172 kb
Host smart-290d3376-c2b3-42e6-a2ce-747bc445db2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34116009 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.34116009
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/36.edn_err.1002652452
Short name T107
Test name
Test status
Simulation time 25312135 ps
CPU time 1.16 seconds
Started Jul 20 06:50:08 PM PDT 24
Finished Jul 20 06:50:10 PM PDT 24
Peak memory 220176 kb
Host smart-39fdd42a-af09-46f7-9fe3-c34021fc455d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002652452 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1002652452
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/174.edn_alert.758289730
Short name T277
Test name
Test status
Simulation time 34108810 ps
CPU time 1.25 seconds
Started Jul 20 06:51:20 PM PDT 24
Finished Jul 20 06:51:23 PM PDT 24
Peak memory 219048 kb
Host smart-2a8f56f0-a583-44b5-b1b5-99f3583e3e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758289730 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.758289730
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/0.edn_genbits.1115499587
Short name T420
Test name
Test status
Simulation time 60027860 ps
CPU time 2.03 seconds
Started Jul 20 06:49:03 PM PDT 24
Finished Jul 20 06:49:06 PM PDT 24
Peak memory 215576 kb
Host smart-b454cf6e-34ab-4083-a06b-c0a0d04f0872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115499587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.1115499587
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1603371055
Short name T1036
Test name
Test status
Simulation time 183591188 ps
CPU time 1.7 seconds
Started Jul 20 05:53:04 PM PDT 24
Finished Jul 20 05:53:07 PM PDT 24
Peak memory 206820 kb
Host smart-2518d042-093b-424b-a9b3-a9facbca5dd9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603371055 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1603371055
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3109908732
Short name T258
Test name
Test status
Simulation time 265079757 ps
CPU time 6.27 seconds
Started Jul 20 05:53:03 PM PDT 24
Finished Jul 20 05:53:10 PM PDT 24
Peak memory 206820 kb
Host smart-b1449d9a-8539-4210-9a88-4a84d97c7d66
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109908732 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.3109908732
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.4098403215
Short name T1061
Test name
Test status
Simulation time 44192434 ps
CPU time 0.92 seconds
Started Jul 20 05:53:13 PM PDT 24
Finished Jul 20 05:53:15 PM PDT 24
Peak memory 206820 kb
Host smart-157aef00-0490-40d5-8778-2ef9297c8367
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098403215 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.4098403215
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3289977425
Short name T1062
Test name
Test status
Simulation time 58366120 ps
CPU time 1.82 seconds
Started Jul 20 05:53:01 PM PDT 24
Finished Jul 20 05:53:03 PM PDT 24
Peak memory 215324 kb
Host smart-d6329243-f69f-4d34-bfa5-014a615da9be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289977425 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3289977425
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2064661674
Short name T1128
Test name
Test status
Simulation time 29227573 ps
CPU time 0.96 seconds
Started Jul 20 05:53:04 PM PDT 24
Finished Jul 20 05:53:05 PM PDT 24
Peak memory 206828 kb
Host smart-e021cacb-eeaa-4f75-bc04-d28c1ab7dce2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064661674 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2064661674
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.2875031026
Short name T1100
Test name
Test status
Simulation time 36001283 ps
CPU time 0.8 seconds
Started Jul 20 05:53:05 PM PDT 24
Finished Jul 20 05:53:07 PM PDT 24
Peak memory 206628 kb
Host smart-755f379b-01a0-442b-8faf-44584725d6f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875031026 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.2875031026
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.1939085866
Short name T1111
Test name
Test status
Simulation time 104516009 ps
CPU time 1.83 seconds
Started Jul 20 05:53:04 PM PDT 24
Finished Jul 20 05:53:06 PM PDT 24
Peak memory 215160 kb
Host smart-bf6c8542-78cd-4315-835e-c80e86eb5b50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939085866 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.1939085866
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3880558465
Short name T1063
Test name
Test status
Simulation time 82898201 ps
CPU time 2.11 seconds
Started Jul 20 05:53:05 PM PDT 24
Finished Jul 20 05:53:08 PM PDT 24
Peak memory 206868 kb
Host smart-cd12229c-454e-4b28-bc0a-795e17a08cf3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880558465 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3880558465
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1611062616
Short name T1022
Test name
Test status
Simulation time 68331258 ps
CPU time 1.61 seconds
Started Jul 20 05:53:00 PM PDT 24
Finished Jul 20 05:53:02 PM PDT 24
Peak memory 206860 kb
Host smart-020c41a8-3666-470f-aca9-5527f5e51263
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611062616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1611062616
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.352854816
Short name T1049
Test name
Test status
Simulation time 180931032 ps
CPU time 5.19 seconds
Started Jul 20 05:53:02 PM PDT 24
Finished Jul 20 05:53:08 PM PDT 24
Peak memory 206876 kb
Host smart-9f07431c-ebcf-4888-9036-2f0ee18fb383
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352854816 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.352854816
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1044634972
Short name T1106
Test name
Test status
Simulation time 34108989 ps
CPU time 0.9 seconds
Started Jul 20 05:53:02 PM PDT 24
Finished Jul 20 05:53:03 PM PDT 24
Peak memory 206800 kb
Host smart-e2a68b89-8272-4c1a-913d-70bb48809ac4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044634972 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1044634972
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.33615211
Short name T1038
Test name
Test status
Simulation time 44812988 ps
CPU time 1.76 seconds
Started Jul 20 05:53:07 PM PDT 24
Finished Jul 20 05:53:10 PM PDT 24
Peak memory 215200 kb
Host smart-2dc5a86f-93cd-4a5a-91c5-1f3b6110d070
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33615211 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.33615211
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.1729891287
Short name T253
Test name
Test status
Simulation time 67708532 ps
CPU time 0.98 seconds
Started Jul 20 05:53:03 PM PDT 24
Finished Jul 20 05:53:04 PM PDT 24
Peak memory 206784 kb
Host smart-4c6532c8-a71a-49e2-92a9-7ccfd5b58cc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729891287 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.1729891287
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.664530328
Short name T1119
Test name
Test status
Simulation time 15241308 ps
CPU time 0.9 seconds
Started Jul 20 05:53:08 PM PDT 24
Finished Jul 20 05:53:10 PM PDT 24
Peak memory 206844 kb
Host smart-b5e1d58b-67bf-4fcd-847c-eb06fa14f17b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664530328 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.664530328
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.4133378285
Short name T246
Test name
Test status
Simulation time 87787529 ps
CPU time 1 seconds
Started Jul 20 05:53:04 PM PDT 24
Finished Jul 20 05:53:06 PM PDT 24
Peak memory 207012 kb
Host smart-6d5ef035-533e-4d1d-8912-6f19e1ad563f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133378285 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.4133378285
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.2542791452
Short name T1005
Test name
Test status
Simulation time 275530913 ps
CPU time 2.7 seconds
Started Jul 20 05:53:13 PM PDT 24
Finished Jul 20 05:53:16 PM PDT 24
Peak memory 215228 kb
Host smart-2528a2e1-4e20-4cbd-af0b-d10e8944eb92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542791452 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.2542791452
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1103210829
Short name T1096
Test name
Test status
Simulation time 21899670 ps
CPU time 1.28 seconds
Started Jul 20 05:53:26 PM PDT 24
Finished Jul 20 05:53:28 PM PDT 24
Peak memory 215120 kb
Host smart-b8972b97-1f20-48d7-b0ba-c2a442246251
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103210829 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.1103210829
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.430424
Short name T250
Test name
Test status
Simulation time 58256947 ps
CPU time 0.93 seconds
Started Jul 20 05:53:22 PM PDT 24
Finished Jul 20 05:53:25 PM PDT 24
Peak memory 206872 kb
Host smart-3deb7db3-da37-45c8-85dc-d87dba5fa922
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430424 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.430424
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.1251921095
Short name T1026
Test name
Test status
Simulation time 240496336 ps
CPU time 0.93 seconds
Started Jul 20 05:53:16 PM PDT 24
Finished Jul 20 05:53:19 PM PDT 24
Peak memory 206748 kb
Host smart-4bd97a2a-5cf1-41d6-bec9-d5f9e1160e4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251921095 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.1251921095
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3753994826
Short name T1093
Test name
Test status
Simulation time 19089148 ps
CPU time 1.17 seconds
Started Jul 20 05:53:30 PM PDT 24
Finished Jul 20 05:53:31 PM PDT 24
Peak memory 206928 kb
Host smart-dfa50af1-4c03-4885-b965-9ff7216c66e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753994826 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.3753994826
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.429278911
Short name T1056
Test name
Test status
Simulation time 45077389 ps
CPU time 2.91 seconds
Started Jul 20 05:53:22 PM PDT 24
Finished Jul 20 05:53:27 PM PDT 24
Peak memory 215268 kb
Host smart-2c3222f3-ee27-488a-86d3-aff220d0f5af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429278911 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.429278911
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.4041639180
Short name T1115
Test name
Test status
Simulation time 70142574 ps
CPU time 1.46 seconds
Started Jul 20 05:53:23 PM PDT 24
Finished Jul 20 05:53:26 PM PDT 24
Peak memory 215164 kb
Host smart-624df4f2-8354-4301-a46d-4a326613bb54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041639180 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.4041639180
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1719563464
Short name T997
Test name
Test status
Simulation time 201676716 ps
CPU time 1.24 seconds
Started Jul 20 05:53:30 PM PDT 24
Finished Jul 20 05:53:31 PM PDT 24
Peak memory 217196 kb
Host smart-b8cdbfb9-361c-4c63-9b92-54939db3cd1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719563464 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.1719563464
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.136102465
Short name T248
Test name
Test status
Simulation time 174602350 ps
CPU time 0.88 seconds
Started Jul 20 05:53:27 PM PDT 24
Finished Jul 20 05:53:29 PM PDT 24
Peak memory 206616 kb
Host smart-0ff4e0a5-d134-4423-a591-1ce51043f9b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136102465 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.136102465
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.4039276994
Short name T1101
Test name
Test status
Simulation time 84014144 ps
CPU time 0.83 seconds
Started Jul 20 05:53:36 PM PDT 24
Finished Jul 20 05:53:38 PM PDT 24
Peak memory 206552 kb
Host smart-f65aacb7-7fd1-46bb-bc89-8c1a57494a09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039276994 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.4039276994
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1995510870
Short name T1124
Test name
Test status
Simulation time 48091974 ps
CPU time 1.15 seconds
Started Jul 20 05:53:29 PM PDT 24
Finished Jul 20 05:53:31 PM PDT 24
Peak memory 206844 kb
Host smart-4d34626d-0a86-4fef-b67f-7283d83ed7be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995510870 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.1995510870
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.2029234049
Short name T1109
Test name
Test status
Simulation time 46612029 ps
CPU time 3.08 seconds
Started Jul 20 05:53:30 PM PDT 24
Finished Jul 20 05:53:34 PM PDT 24
Peak memory 215144 kb
Host smart-538a4a65-c141-4fe1-917f-603e64ab1304
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029234049 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2029234049
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.668831623
Short name T1120
Test name
Test status
Simulation time 113343638 ps
CPU time 1.59 seconds
Started Jul 20 05:53:29 PM PDT 24
Finished Jul 20 05:53:31 PM PDT 24
Peak memory 206944 kb
Host smart-2478aef6-6b55-46fe-b391-dec2da1062c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668831623 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.668831623
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.4228816118
Short name T1055
Test name
Test status
Simulation time 23827288 ps
CPU time 1.23 seconds
Started Jul 20 05:53:32 PM PDT 24
Finished Jul 20 05:53:34 PM PDT 24
Peak memory 217236 kb
Host smart-582bf965-594a-441e-8b26-fb8359975eae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228816118 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.4228816118
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.319651708
Short name T254
Test name
Test status
Simulation time 34660208 ps
CPU time 0.8 seconds
Started Jul 20 05:53:37 PM PDT 24
Finished Jul 20 05:53:38 PM PDT 24
Peak memory 206540 kb
Host smart-2f16e832-f011-4a55-9c33-07287dc4fee5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319651708 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.319651708
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.2517090263
Short name T1094
Test name
Test status
Simulation time 14615128 ps
CPU time 0.92 seconds
Started Jul 20 05:53:26 PM PDT 24
Finished Jul 20 05:53:28 PM PDT 24
Peak memory 206744 kb
Host smart-bfdd0ce5-774d-4139-9064-039dc0747511
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517090263 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2517090263
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2464609803
Short name T1091
Test name
Test status
Simulation time 17790105 ps
CPU time 1.22 seconds
Started Jul 20 05:53:32 PM PDT 24
Finished Jul 20 05:53:34 PM PDT 24
Peak memory 206892 kb
Host smart-68ce618e-7efe-4c64-a6e6-08350c29f988
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464609803 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.2464609803
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3147988383
Short name T1058
Test name
Test status
Simulation time 222340774 ps
CPU time 3.61 seconds
Started Jul 20 05:53:36 PM PDT 24
Finished Jul 20 05:53:41 PM PDT 24
Peak memory 215060 kb
Host smart-bc2180f4-4661-43bd-90c8-935fe0317b14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147988383 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3147988383
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.507243767
Short name T1075
Test name
Test status
Simulation time 85980222 ps
CPU time 1.56 seconds
Started Jul 20 05:53:31 PM PDT 24
Finished Jul 20 05:53:33 PM PDT 24
Peak memory 206788 kb
Host smart-09b3e1e6-1d67-4b4b-86c3-918290356b4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507243767 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.507243767
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3305550227
Short name T1051
Test name
Test status
Simulation time 66508194 ps
CPU time 1.18 seconds
Started Jul 20 05:53:36 PM PDT 24
Finished Jul 20 05:53:38 PM PDT 24
Peak memory 215048 kb
Host smart-07a598e8-686d-4e11-8d9b-875e9be0f2e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305550227 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.3305550227
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.2629476236
Short name T1009
Test name
Test status
Simulation time 58497484 ps
CPU time 0.91 seconds
Started Jul 20 05:53:30 PM PDT 24
Finished Jul 20 05:53:31 PM PDT 24
Peak memory 206820 kb
Host smart-13da06a3-88a1-4b08-ace0-de8b71191cb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629476236 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.2629476236
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2434072873
Short name T1047
Test name
Test status
Simulation time 75900806 ps
CPU time 1.09 seconds
Started Jul 20 05:53:27 PM PDT 24
Finished Jul 20 05:53:29 PM PDT 24
Peak memory 206872 kb
Host smart-cc1da2ca-e7a1-4ca0-88dd-da5983bf0aa5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434072873 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2434072873
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.889247778
Short name T1090
Test name
Test status
Simulation time 686427852 ps
CPU time 4.28 seconds
Started Jul 20 05:53:37 PM PDT 24
Finished Jul 20 05:53:42 PM PDT 24
Peak memory 215056 kb
Host smart-92af5880-0ad3-44de-a514-523dd7489d1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889247778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.889247778
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.4269304313
Short name T1082
Test name
Test status
Simulation time 174828557 ps
CPU time 1.69 seconds
Started Jul 20 05:53:30 PM PDT 24
Finished Jul 20 05:53:33 PM PDT 24
Peak memory 206880 kb
Host smart-e14bbfff-a852-4f42-92c8-88a6ae17b920
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269304313 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.4269304313
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.168923353
Short name T1110
Test name
Test status
Simulation time 26759569 ps
CPU time 1.59 seconds
Started Jul 20 05:53:38 PM PDT 24
Finished Jul 20 05:53:40 PM PDT 24
Peak memory 219048 kb
Host smart-88775b73-780b-44e7-a05e-3a8177539525
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168923353 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.168923353
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.4204835133
Short name T264
Test name
Test status
Simulation time 75072014 ps
CPU time 0.82 seconds
Started Jul 20 05:53:29 PM PDT 24
Finished Jul 20 05:53:30 PM PDT 24
Peak memory 206636 kb
Host smart-a69a9295-9c63-48d0-b0af-78b663c28071
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204835133 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.4204835133
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.1442473693
Short name T1122
Test name
Test status
Simulation time 34325206 ps
CPU time 0.83 seconds
Started Jul 20 05:53:29 PM PDT 24
Finished Jul 20 05:53:30 PM PDT 24
Peak memory 206840 kb
Host smart-875d4e66-11e7-4b41-8a8c-8c52d4414732
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442473693 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.1442473693
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2041461023
Short name T1041
Test name
Test status
Simulation time 16319681 ps
CPU time 1.12 seconds
Started Jul 20 05:53:38 PM PDT 24
Finished Jul 20 05:53:40 PM PDT 24
Peak memory 206836 kb
Host smart-4b994431-c09f-4405-b469-fd2a1eef75f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041461023 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.2041461023
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.3061288554
Short name T1114
Test name
Test status
Simulation time 242845501 ps
CPU time 3.96 seconds
Started Jul 20 05:53:32 PM PDT 24
Finished Jul 20 05:53:37 PM PDT 24
Peak memory 215164 kb
Host smart-2b03b8d3-0dea-4ec9-9fe9-b0e20fe3f267
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061288554 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3061288554
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1965670948
Short name T1017
Test name
Test status
Simulation time 37684054 ps
CPU time 1.37 seconds
Started Jul 20 05:53:40 PM PDT 24
Finished Jul 20 05:53:42 PM PDT 24
Peak memory 215052 kb
Host smart-4e5f7318-3834-425c-aa53-36474e01ad94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965670948 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1965670948
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.535370826
Short name T1039
Test name
Test status
Simulation time 15512234 ps
CPU time 0.96 seconds
Started Jul 20 05:53:36 PM PDT 24
Finished Jul 20 05:53:37 PM PDT 24
Peak memory 206768 kb
Host smart-a5a62374-0825-491d-9379-8cbb8bb8755a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535370826 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.535370826
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3538257236
Short name T1033
Test name
Test status
Simulation time 49343164 ps
CPU time 0.89 seconds
Started Jul 20 05:53:36 PM PDT 24
Finished Jul 20 05:53:37 PM PDT 24
Peak memory 206760 kb
Host smart-a750d9c2-e5b2-455c-81bd-2ab8c711b077
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538257236 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3538257236
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1169019329
Short name T1046
Test name
Test status
Simulation time 69935983 ps
CPU time 1.18 seconds
Started Jul 20 05:53:44 PM PDT 24
Finished Jul 20 05:53:46 PM PDT 24
Peak memory 206872 kb
Host smart-8af3745a-5933-4954-a343-cc30a60b9fb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169019329 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.1169019329
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.1610205649
Short name T1016
Test name
Test status
Simulation time 116406422 ps
CPU time 2.47 seconds
Started Jul 20 05:53:37 PM PDT 24
Finished Jul 20 05:53:40 PM PDT 24
Peak memory 215144 kb
Host smart-7e42376d-6053-4051-b00d-ac025c96a1b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610205649 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.1610205649
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1314146297
Short name T1126
Test name
Test status
Simulation time 232366723 ps
CPU time 2.34 seconds
Started Jul 20 05:53:37 PM PDT 24
Finished Jul 20 05:53:40 PM PDT 24
Peak memory 215088 kb
Host smart-1e22dff4-faa3-4872-a8bf-f0b77c3e90a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314146297 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1314146297
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3592338060
Short name T1077
Test name
Test status
Simulation time 72256582 ps
CPU time 1.39 seconds
Started Jul 20 05:53:36 PM PDT 24
Finished Jul 20 05:53:38 PM PDT 24
Peak memory 215144 kb
Host smart-ce9df91f-5bd3-4fa8-ade4-4e305676707c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592338060 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.3592338060
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.1432679754
Short name T1045
Test name
Test status
Simulation time 13103788 ps
CPU time 0.85 seconds
Started Jul 20 05:53:36 PM PDT 24
Finished Jul 20 05:53:38 PM PDT 24
Peak memory 206832 kb
Host smart-c116d720-f620-474c-9ff1-fb415eff06fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432679754 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1432679754
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3444257381
Short name T1010
Test name
Test status
Simulation time 42845694 ps
CPU time 0.84 seconds
Started Jul 20 05:53:44 PM PDT 24
Finished Jul 20 05:53:46 PM PDT 24
Peak memory 206644 kb
Host smart-63d5d325-4000-4e1c-96cc-67aa13a8ac20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444257381 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3444257381
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3033606270
Short name T1035
Test name
Test status
Simulation time 33510900 ps
CPU time 1.11 seconds
Started Jul 20 05:53:43 PM PDT 24
Finished Jul 20 05:53:45 PM PDT 24
Peak memory 206784 kb
Host smart-7b1e90ce-867d-4057-ae07-14aeafe2f07f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033606270 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3033606270
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.322269439
Short name T1025
Test name
Test status
Simulation time 48353153 ps
CPU time 3.51 seconds
Started Jul 20 05:53:35 PM PDT 24
Finished Jul 20 05:53:39 PM PDT 24
Peak memory 215152 kb
Host smart-6335b9b9-4bfe-4ad5-84bb-e6c44a316d90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322269439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.322269439
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.539511651
Short name T271
Test name
Test status
Simulation time 219071463 ps
CPU time 1.73 seconds
Started Jul 20 05:53:44 PM PDT 24
Finished Jul 20 05:53:47 PM PDT 24
Peak memory 215068 kb
Host smart-33190fe8-71b8-42b6-a606-f6a44c09dc85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539511651 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.539511651
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2219232931
Short name T1002
Test name
Test status
Simulation time 29691780 ps
CPU time 1.42 seconds
Started Jul 20 05:53:37 PM PDT 24
Finished Jul 20 05:53:39 PM PDT 24
Peak memory 215148 kb
Host smart-3c6c72ed-50da-4309-8838-e1562641cc90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219232931 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2219232931
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.1019931616
Short name T1125
Test name
Test status
Simulation time 19400186 ps
CPU time 0.81 seconds
Started Jul 20 05:53:40 PM PDT 24
Finished Jul 20 05:53:41 PM PDT 24
Peak memory 206548 kb
Host smart-f91c6da5-9098-4b72-b698-e84d7980ed37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019931616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1019931616
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.3084873598
Short name T998
Test name
Test status
Simulation time 34657976 ps
CPU time 0.84 seconds
Started Jul 20 05:53:36 PM PDT 24
Finished Jul 20 05:53:37 PM PDT 24
Peak memory 206640 kb
Host smart-f049fbd4-f9c3-4e64-867a-29de7c1d6fb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084873598 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.3084873598
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2780300025
Short name T1103
Test name
Test status
Simulation time 104283326 ps
CPU time 1.41 seconds
Started Jul 20 05:53:44 PM PDT 24
Finished Jul 20 05:53:46 PM PDT 24
Peak memory 206872 kb
Host smart-fff7acbf-bcdc-4bf3-ad9d-8f82a409319a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780300025 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.2780300025
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.3558036846
Short name T1127
Test name
Test status
Simulation time 42618512 ps
CPU time 3.02 seconds
Started Jul 20 05:53:36 PM PDT 24
Finished Jul 20 05:53:40 PM PDT 24
Peak memory 215212 kb
Host smart-059a568d-a10d-4b55-a776-ee813cd8fe62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558036846 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3558036846
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3104905636
Short name T272
Test name
Test status
Simulation time 317184944 ps
CPU time 2.18 seconds
Started Jul 20 05:53:44 PM PDT 24
Finished Jul 20 05:53:48 PM PDT 24
Peak memory 206872 kb
Host smart-bd77351b-923b-4ef1-81ac-b699750cc034
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104905636 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3104905636
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1327955979
Short name T1028
Test name
Test status
Simulation time 62267363 ps
CPU time 1.12 seconds
Started Jul 20 05:53:37 PM PDT 24
Finished Jul 20 05:53:39 PM PDT 24
Peak memory 215132 kb
Host smart-78b1bba7-11f5-4522-bcc2-6da86771d90e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327955979 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.1327955979
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.511164727
Short name T1034
Test name
Test status
Simulation time 26351855 ps
CPU time 0.97 seconds
Started Jul 20 05:53:38 PM PDT 24
Finished Jul 20 05:53:40 PM PDT 24
Peak memory 206828 kb
Host smart-eb1b3b68-53ff-4c3d-a3f1-e87715943527
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511164727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.511164727
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2419904283
Short name T1012
Test name
Test status
Simulation time 42415577 ps
CPU time 0.86 seconds
Started Jul 20 05:53:38 PM PDT 24
Finished Jul 20 05:53:39 PM PDT 24
Peak memory 206800 kb
Host smart-a1086997-41c7-4c37-b2fa-6a497d7f2f15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419904283 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2419904283
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1918616869
Short name T267
Test name
Test status
Simulation time 141629432 ps
CPU time 0.99 seconds
Started Jul 20 05:53:36 PM PDT 24
Finished Jul 20 05:53:38 PM PDT 24
Peak memory 206912 kb
Host smart-1c846a06-858c-4525-b86e-de2df13e34bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918616869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.1918616869
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3771629049
Short name T1059
Test name
Test status
Simulation time 818156640 ps
CPU time 3.57 seconds
Started Jul 20 05:53:36 PM PDT 24
Finished Jul 20 05:53:41 PM PDT 24
Peak memory 215148 kb
Host smart-85feada2-c557-40b3-a9df-bbe2c5e3cfd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771629049 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3771629049
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3010492244
Short name T282
Test name
Test status
Simulation time 100125187 ps
CPU time 2.26 seconds
Started Jul 20 05:53:36 PM PDT 24
Finished Jul 20 05:53:40 PM PDT 24
Peak memory 215680 kb
Host smart-1fa191e8-5753-48fc-a10a-a8cd4d2d9599
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010492244 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.3010492244
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3029098985
Short name T999
Test name
Test status
Simulation time 42079406 ps
CPU time 1.22 seconds
Started Jul 20 05:53:44 PM PDT 24
Finished Jul 20 05:53:46 PM PDT 24
Peak memory 217712 kb
Host smart-65bb6ea0-edc4-4c7a-a1d7-4ad3060a840a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029098985 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3029098985
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.4120212696
Short name T1070
Test name
Test status
Simulation time 15184546 ps
CPU time 0.97 seconds
Started Jul 20 05:53:45 PM PDT 24
Finished Jul 20 05:53:47 PM PDT 24
Peak memory 206812 kb
Host smart-a77ee654-0fa3-4d44-9736-de3b02a687b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120212696 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.4120212696
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.234130554
Short name T1069
Test name
Test status
Simulation time 44472294 ps
CPU time 0.81 seconds
Started Jul 20 05:53:43 PM PDT 24
Finished Jul 20 05:53:45 PM PDT 24
Peak memory 206728 kb
Host smart-5b90d31d-3ee0-431c-b61e-6df5909af90e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234130554 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.234130554
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.517113910
Short name T265
Test name
Test status
Simulation time 134294509 ps
CPU time 1.08 seconds
Started Jul 20 05:53:46 PM PDT 24
Finished Jul 20 05:53:48 PM PDT 24
Peak memory 206888 kb
Host smart-18ec6441-e22e-47a7-8e0f-b807534ed445
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517113910 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_ou
tstanding.517113910
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.3967234301
Short name T1095
Test name
Test status
Simulation time 92298551 ps
CPU time 3.23 seconds
Started Jul 20 05:53:34 PM PDT 24
Finished Jul 20 05:53:38 PM PDT 24
Peak memory 215200 kb
Host smart-bc349848-3bac-470f-8293-67df6e02eed2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967234301 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.3967234301
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3394797643
Short name T1081
Test name
Test status
Simulation time 78626371 ps
CPU time 2.36 seconds
Started Jul 20 05:53:38 PM PDT 24
Finished Jul 20 05:53:41 PM PDT 24
Peak memory 207080 kb
Host smart-f6db4e02-afe9-42f3-b735-e1de4987e4f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394797643 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3394797643
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.313288314
Short name T256
Test name
Test status
Simulation time 17933303 ps
CPU time 1.28 seconds
Started Jul 20 05:53:06 PM PDT 24
Finished Jul 20 05:53:09 PM PDT 24
Peak memory 206980 kb
Host smart-beeb7669-512b-4297-8355-8eb6e0301937
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313288314 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.313288314
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2591745423
Short name T1092
Test name
Test status
Simulation time 503787485 ps
CPU time 6.66 seconds
Started Jul 20 05:53:04 PM PDT 24
Finished Jul 20 05:53:12 PM PDT 24
Peak memory 206800 kb
Host smart-1740532e-80bf-47b5-8923-e13a27112bee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591745423 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.2591745423
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2193310496
Short name T260
Test name
Test status
Simulation time 26479609 ps
CPU time 1 seconds
Started Jul 20 05:53:06 PM PDT 24
Finished Jul 20 05:53:08 PM PDT 24
Peak memory 206800 kb
Host smart-11e48793-a2c8-46fe-aaef-195a837e4c21
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193310496 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.2193310496
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3101136725
Short name T995
Test name
Test status
Simulation time 20981681 ps
CPU time 1.2 seconds
Started Jul 20 05:53:06 PM PDT 24
Finished Jul 20 05:53:08 PM PDT 24
Peak memory 215232 kb
Host smart-751cf60a-755e-4041-a245-dba50984caf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101136725 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3101136725
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.1891822846
Short name T1071
Test name
Test status
Simulation time 26384460 ps
CPU time 0.94 seconds
Started Jul 20 05:53:03 PM PDT 24
Finished Jul 20 05:53:05 PM PDT 24
Peak memory 206820 kb
Host smart-391847b8-51ed-40d5-b1b4-337cc1391d76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891822846 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.1891822846
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1059522869
Short name T1037
Test name
Test status
Simulation time 49217121 ps
CPU time 0.87 seconds
Started Jul 20 05:53:08 PM PDT 24
Finished Jul 20 05:53:10 PM PDT 24
Peak memory 206836 kb
Host smart-b763ea9a-4b43-478f-beea-f19c04c34180
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059522869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1059522869
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2911494357
Short name T1079
Test name
Test status
Simulation time 185672035 ps
CPU time 1.35 seconds
Started Jul 20 05:53:03 PM PDT 24
Finished Jul 20 05:53:05 PM PDT 24
Peak memory 206968 kb
Host smart-6402fcd5-06e5-4485-91b7-b52b4d113bdf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911494357 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.2911494357
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.210441488
Short name T1024
Test name
Test status
Simulation time 87804840 ps
CPU time 3.42 seconds
Started Jul 20 05:53:01 PM PDT 24
Finished Jul 20 05:53:05 PM PDT 24
Peak memory 215192 kb
Host smart-8e09c376-3295-4b48-bca3-851e0224b34e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210441488 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.210441488
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1868435886
Short name T1042
Test name
Test status
Simulation time 70443561 ps
CPU time 2.32 seconds
Started Jul 20 05:53:13 PM PDT 24
Finished Jul 20 05:53:16 PM PDT 24
Peak memory 206944 kb
Host smart-429879eb-1430-44f7-8b02-9f069c550cc8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868435886 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1868435886
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.3279126444
Short name T1105
Test name
Test status
Simulation time 36868381 ps
CPU time 0.82 seconds
Started Jul 20 05:53:46 PM PDT 24
Finished Jul 20 05:53:48 PM PDT 24
Peak memory 206640 kb
Host smart-438cf57f-8e02-443d-bac0-871c055a4f42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279126444 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3279126444
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.3828429964
Short name T1003
Test name
Test status
Simulation time 40347474 ps
CPU time 0.79 seconds
Started Jul 20 05:53:43 PM PDT 24
Finished Jul 20 05:53:45 PM PDT 24
Peak memory 206768 kb
Host smart-dd5e39bf-23d9-43e0-b161-e3ef8fa31cd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828429964 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.3828429964
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.2532889309
Short name T1015
Test name
Test status
Simulation time 21219443 ps
CPU time 0.87 seconds
Started Jul 20 05:53:46 PM PDT 24
Finished Jul 20 05:53:48 PM PDT 24
Peak memory 206648 kb
Host smart-6045530d-3a3d-4435-bb1d-efd6998d51df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532889309 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2532889309
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.4052599546
Short name T1000
Test name
Test status
Simulation time 57266046 ps
CPU time 0.94 seconds
Started Jul 20 05:53:42 PM PDT 24
Finished Jul 20 05:53:44 PM PDT 24
Peak memory 206760 kb
Host smart-3471b644-3daa-48b3-85e3-455abfc30229
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052599546 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.4052599546
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.944926323
Short name T996
Test name
Test status
Simulation time 63775485 ps
CPU time 0.79 seconds
Started Jul 20 05:53:43 PM PDT 24
Finished Jul 20 05:53:45 PM PDT 24
Peak memory 206660 kb
Host smart-df9f7425-ed64-479a-959f-b8953331231a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944926323 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.944926323
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.2875387803
Short name T1089
Test name
Test status
Simulation time 107277314 ps
CPU time 0.81 seconds
Started Jul 20 05:53:44 PM PDT 24
Finished Jul 20 05:53:46 PM PDT 24
Peak memory 206644 kb
Host smart-3e9d8160-0b18-48df-a791-c4583d9fee18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875387803 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.2875387803
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.3401863271
Short name T1121
Test name
Test status
Simulation time 12222019 ps
CPU time 0.85 seconds
Started Jul 20 05:53:45 PM PDT 24
Finished Jul 20 05:53:47 PM PDT 24
Peak memory 206780 kb
Host smart-5cd3e6aa-de80-4e73-a60a-4edc2dbd0372
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401863271 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.3401863271
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.3043678131
Short name T1084
Test name
Test status
Simulation time 11935552 ps
CPU time 0.85 seconds
Started Jul 20 05:53:47 PM PDT 24
Finished Jul 20 05:53:49 PM PDT 24
Peak memory 206824 kb
Host smart-03079443-4813-4c91-84a2-145c463bfdf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043678131 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3043678131
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.67826210
Short name T1053
Test name
Test status
Simulation time 15073200 ps
CPU time 0.82 seconds
Started Jul 20 05:53:46 PM PDT 24
Finished Jul 20 05:53:49 PM PDT 24
Peak memory 206720 kb
Host smart-ad7dfb2c-c5ae-4775-b384-961ae1720a07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67826210 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.67826210
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.1780250132
Short name T1006
Test name
Test status
Simulation time 21049617 ps
CPU time 0.85 seconds
Started Jul 20 05:53:48 PM PDT 24
Finished Jul 20 05:53:50 PM PDT 24
Peak memory 206840 kb
Host smart-103e74e4-9a4e-4c0c-9f14-eaafc11c69b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780250132 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1780250132
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3259064156
Short name T1040
Test name
Test status
Simulation time 42244824 ps
CPU time 1.24 seconds
Started Jul 20 05:53:11 PM PDT 24
Finished Jul 20 05:53:13 PM PDT 24
Peak memory 206812 kb
Host smart-01dea82e-e5ce-4374-952f-251bf334392b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259064156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3259064156
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3607883708
Short name T1066
Test name
Test status
Simulation time 131772761 ps
CPU time 2.17 seconds
Started Jul 20 05:53:12 PM PDT 24
Finished Jul 20 05:53:15 PM PDT 24
Peak memory 206788 kb
Host smart-0ad8d6f6-5da4-4d63-a6a9-0b9be1fa5d0b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607883708 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3607883708
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2836233070
Short name T1117
Test name
Test status
Simulation time 55031809 ps
CPU time 0.89 seconds
Started Jul 20 05:53:13 PM PDT 24
Finished Jul 20 05:53:14 PM PDT 24
Peak memory 206856 kb
Host smart-acbed308-2a36-4c8f-856d-b188e24323b1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836233070 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2836233070
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2466156271
Short name T1074
Test name
Test status
Simulation time 114531469 ps
CPU time 2.16 seconds
Started Jul 20 05:53:16 PM PDT 24
Finished Jul 20 05:53:20 PM PDT 24
Peak memory 220056 kb
Host smart-2bdba1c0-8f1c-4032-81f4-8632f1a87e4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466156271 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2466156271
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.3986916906
Short name T1004
Test name
Test status
Simulation time 15345167 ps
CPU time 0.93 seconds
Started Jul 20 05:53:16 PM PDT 24
Finished Jul 20 05:53:19 PM PDT 24
Peak memory 206752 kb
Host smart-e2e31ee6-042c-4c02-a1d1-69f81e54f7d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986916906 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.3986916906
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.4149369429
Short name T1014
Test name
Test status
Simulation time 26008340 ps
CPU time 0.87 seconds
Started Jul 20 05:53:15 PM PDT 24
Finished Jul 20 05:53:17 PM PDT 24
Peak memory 206812 kb
Host smart-54fcab89-68c3-406f-9f3b-53218c7066c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149369429 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.4149369429
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1930518160
Short name T1129
Test name
Test status
Simulation time 215835124 ps
CPU time 1 seconds
Started Jul 20 05:53:11 PM PDT 24
Finished Jul 20 05:53:13 PM PDT 24
Peak memory 206912 kb
Host smart-c2e16f7d-b29d-40ca-b71a-cf747cac117e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930518160 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.1930518160
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.2510600014
Short name T1083
Test name
Test status
Simulation time 184915867 ps
CPU time 3.57 seconds
Started Jul 20 05:53:08 PM PDT 24
Finished Jul 20 05:53:13 PM PDT 24
Peak memory 215068 kb
Host smart-135ce691-6311-4d7f-9af8-9c85be6a1500
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510600014 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.2510600014
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1465960017
Short name T1072
Test name
Test status
Simulation time 126879101 ps
CPU time 2.18 seconds
Started Jul 20 05:53:14 PM PDT 24
Finished Jul 20 05:53:17 PM PDT 24
Peak memory 206872 kb
Host smart-806e7240-3d28-4469-b347-989e2fac625e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465960017 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.1465960017
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.1966849142
Short name T1130
Test name
Test status
Simulation time 28722686 ps
CPU time 0.78 seconds
Started Jul 20 05:53:42 PM PDT 24
Finished Jul 20 05:53:43 PM PDT 24
Peak memory 206572 kb
Host smart-58d311ee-e5e3-4d78-92ac-f310efe13bf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966849142 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.1966849142
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.1407511100
Short name T1021
Test name
Test status
Simulation time 16225007 ps
CPU time 0.91 seconds
Started Jul 20 05:53:47 PM PDT 24
Finished Jul 20 05:53:49 PM PDT 24
Peak memory 206812 kb
Host smart-42a14690-852e-4fc7-8816-176c4abc476e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407511100 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.1407511100
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2724313048
Short name T1023
Test name
Test status
Simulation time 40466676 ps
CPU time 0.86 seconds
Started Jul 20 05:53:46 PM PDT 24
Finished Jul 20 05:53:48 PM PDT 24
Peak memory 206644 kb
Host smart-cb0e2f2b-8c06-43c1-bc3c-2aaf231161f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724313048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2724313048
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.2554622545
Short name T1001
Test name
Test status
Simulation time 23715771 ps
CPU time 0.85 seconds
Started Jul 20 05:53:48 PM PDT 24
Finished Jul 20 05:53:50 PM PDT 24
Peak memory 206844 kb
Host smart-c1377f67-c845-46c7-b901-2ef653380725
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554622545 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2554622545
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.680837943
Short name T1027
Test name
Test status
Simulation time 61242340 ps
CPU time 0.86 seconds
Started Jul 20 05:53:44 PM PDT 24
Finished Jul 20 05:53:46 PM PDT 24
Peak memory 206944 kb
Host smart-080ef196-8abd-4d47-a4c5-c81401bcd235
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680837943 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.680837943
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.2826284551
Short name T1104
Test name
Test status
Simulation time 51278136 ps
CPU time 0.89 seconds
Started Jul 20 05:53:42 PM PDT 24
Finished Jul 20 05:53:44 PM PDT 24
Peak memory 206820 kb
Host smart-c909d96e-5be3-4f1c-bd68-cf769ffa4584
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826284551 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.2826284551
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.628205857
Short name T1020
Test name
Test status
Simulation time 22282583 ps
CPU time 0.87 seconds
Started Jul 20 05:53:48 PM PDT 24
Finished Jul 20 05:53:50 PM PDT 24
Peak memory 206824 kb
Host smart-137d3d1b-30bf-4347-9fcb-eb1058d3f6f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628205857 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.628205857
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.1661538173
Short name T1018
Test name
Test status
Simulation time 15273812 ps
CPU time 0.84 seconds
Started Jul 20 05:53:43 PM PDT 24
Finished Jul 20 05:53:45 PM PDT 24
Peak memory 206840 kb
Host smart-88c408e6-d01b-4a4b-b4eb-e92872b387ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661538173 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1661538173
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.3443946529
Short name T1052
Test name
Test status
Simulation time 23662820 ps
CPU time 0.89 seconds
Started Jul 20 05:53:45 PM PDT 24
Finished Jul 20 05:53:47 PM PDT 24
Peak memory 206800 kb
Host smart-4aa767a0-02e3-47bd-a370-6205f8a89537
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443946529 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3443946529
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.2640599251
Short name T1065
Test name
Test status
Simulation time 32795377 ps
CPU time 0.86 seconds
Started Jul 20 05:53:43 PM PDT 24
Finished Jul 20 05:53:45 PM PDT 24
Peak memory 206624 kb
Host smart-b256af4c-b878-4567-84fb-e39ef37e9b2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640599251 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.2640599251
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2245215983
Short name T257
Test name
Test status
Simulation time 139567046 ps
CPU time 1.53 seconds
Started Jul 20 05:53:16 PM PDT 24
Finished Jul 20 05:53:19 PM PDT 24
Peak memory 206940 kb
Host smart-2ca806ba-481d-490f-9edf-fe4c727dd995
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245215983 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.2245215983
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1138991894
Short name T1118
Test name
Test status
Simulation time 200936116 ps
CPU time 3.17 seconds
Started Jul 20 05:53:10 PM PDT 24
Finished Jul 20 05:53:15 PM PDT 24
Peak memory 206852 kb
Host smart-0dd73d50-d149-4108-8cd4-f6ed18aa5543
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138991894 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.1138991894
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3816352210
Short name T259
Test name
Test status
Simulation time 20603716 ps
CPU time 1 seconds
Started Jul 20 05:53:11 PM PDT 24
Finished Jul 20 05:53:13 PM PDT 24
Peak memory 206896 kb
Host smart-ebda5496-30e1-4cf3-a0a3-3992e389fb57
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816352210 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3816352210
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1150695562
Short name T1097
Test name
Test status
Simulation time 25113149 ps
CPU time 1.26 seconds
Started Jul 20 05:53:11 PM PDT 24
Finished Jul 20 05:53:13 PM PDT 24
Peak memory 215160 kb
Host smart-a23b8534-cd16-452b-a104-c6599cd67c83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150695562 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.1150695562
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.2001409371
Short name T252
Test name
Test status
Simulation time 13966529 ps
CPU time 0.9 seconds
Started Jul 20 05:53:17 PM PDT 24
Finished Jul 20 05:53:19 PM PDT 24
Peak memory 206720 kb
Host smart-c117f466-c8ab-4cf9-be4c-e496a60c3345
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001409371 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2001409371
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.866258485
Short name T1087
Test name
Test status
Simulation time 30124936 ps
CPU time 1.1 seconds
Started Jul 20 05:53:11 PM PDT 24
Finished Jul 20 05:53:13 PM PDT 24
Peak memory 206868 kb
Host smart-80a200e5-7712-4f49-89b8-da16ce8a29dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866258485 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.866258485
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3046178231
Short name T262
Test name
Test status
Simulation time 46719560 ps
CPU time 1.14 seconds
Started Jul 20 05:53:14 PM PDT 24
Finished Jul 20 05:53:16 PM PDT 24
Peak memory 206868 kb
Host smart-ad4709b6-7bae-4742-b96d-fcb8c4620cfc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046178231 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.3046178231
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.2221686822
Short name T1102
Test name
Test status
Simulation time 162700456 ps
CPU time 3.26 seconds
Started Jul 20 05:53:17 PM PDT 24
Finished Jul 20 05:53:21 PM PDT 24
Peak memory 215144 kb
Host smart-5b602440-45ed-4038-a23a-39410e1d92ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221686822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2221686822
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.860418150
Short name T1088
Test name
Test status
Simulation time 79412221 ps
CPU time 2.25 seconds
Started Jul 20 05:53:13 PM PDT 24
Finished Jul 20 05:53:16 PM PDT 24
Peak memory 215088 kb
Host smart-15cc20c5-8f73-40f4-9914-4cd07e8ac947
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860418150 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.860418150
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.3157964294
Short name T1032
Test name
Test status
Simulation time 138699773 ps
CPU time 0.91 seconds
Started Jul 20 05:53:44 PM PDT 24
Finished Jul 20 05:53:46 PM PDT 24
Peak memory 206644 kb
Host smart-84a9a9a6-9e8e-478a-8cd6-2b43d597271c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157964294 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.3157964294
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.1102347319
Short name T1060
Test name
Test status
Simulation time 12900402 ps
CPU time 0.86 seconds
Started Jul 20 05:53:48 PM PDT 24
Finished Jul 20 05:53:50 PM PDT 24
Peak memory 206840 kb
Host smart-7eda69f3-5942-43c5-945b-adb2edafff00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102347319 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1102347319
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.391233116
Short name T1030
Test name
Test status
Simulation time 14927808 ps
CPU time 0.94 seconds
Started Jul 20 05:53:46 PM PDT 24
Finished Jul 20 05:53:48 PM PDT 24
Peak memory 206836 kb
Host smart-a323d81c-84fe-4a91-abd6-2ee73b70e6cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391233116 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.391233116
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.1583471685
Short name T1068
Test name
Test status
Simulation time 31596547 ps
CPU time 0.85 seconds
Started Jul 20 05:53:43 PM PDT 24
Finished Jul 20 05:53:45 PM PDT 24
Peak memory 206828 kb
Host smart-3aba08bc-7947-4c5b-9a29-ad382b7eec00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583471685 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.1583471685
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.403992119
Short name T1050
Test name
Test status
Simulation time 12952346 ps
CPU time 0.85 seconds
Started Jul 20 05:53:42 PM PDT 24
Finished Jul 20 05:53:43 PM PDT 24
Peak memory 206844 kb
Host smart-d1e30697-5b66-4cb2-817e-c856d72b1c94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403992119 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.403992119
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.3912807070
Short name T1112
Test name
Test status
Simulation time 12729480 ps
CPU time 0.87 seconds
Started Jul 20 05:53:47 PM PDT 24
Finished Jul 20 05:53:49 PM PDT 24
Peak memory 206816 kb
Host smart-10ac3e88-d34d-4b6b-951e-32f3913e5902
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912807070 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.3912807070
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.3107462477
Short name T1108
Test name
Test status
Simulation time 20428268 ps
CPU time 0.86 seconds
Started Jul 20 05:53:46 PM PDT 24
Finished Jul 20 05:53:48 PM PDT 24
Peak memory 206644 kb
Host smart-4a623d7f-9077-4929-8ff7-a69cf230d42d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107462477 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.3107462477
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.4288919411
Short name T1086
Test name
Test status
Simulation time 18689407 ps
CPU time 0.85 seconds
Started Jul 20 05:53:42 PM PDT 24
Finished Jul 20 05:53:43 PM PDT 24
Peak memory 206696 kb
Host smart-9cc20a0f-1f76-44ba-8d3c-823c7030f2f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288919411 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.4288919411
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.1911050100
Short name T1013
Test name
Test status
Simulation time 23964636 ps
CPU time 0.85 seconds
Started Jul 20 05:53:45 PM PDT 24
Finished Jul 20 05:53:47 PM PDT 24
Peak memory 206796 kb
Host smart-5be26305-52a5-46bf-afc7-3cbc7792b853
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911050100 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.1911050100
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.653930847
Short name T1007
Test name
Test status
Simulation time 13825540 ps
CPU time 0.9 seconds
Started Jul 20 05:53:46 PM PDT 24
Finished Jul 20 05:53:48 PM PDT 24
Peak memory 206820 kb
Host smart-bf58ff06-067e-45e0-ad32-1f8bc3c4ead3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653930847 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.653930847
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.34044336
Short name T1057
Test name
Test status
Simulation time 244846265 ps
CPU time 1.38 seconds
Started Jul 20 05:53:20 PM PDT 24
Finished Jul 20 05:53:23 PM PDT 24
Peak memory 218348 kb
Host smart-bdfc1f91-86b5-4a23-ac4a-3d23b40e9b52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34044336 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.34044336
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.207449460
Short name T261
Test name
Test status
Simulation time 74776890 ps
CPU time 0.88 seconds
Started Jul 20 05:53:11 PM PDT 24
Finished Jul 20 05:53:13 PM PDT 24
Peak memory 206632 kb
Host smart-ce312b29-4ac4-42d7-bdb0-a38df91cce58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207449460 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.207449460
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.612643431
Short name T1029
Test name
Test status
Simulation time 30532682 ps
CPU time 0.96 seconds
Started Jul 20 05:53:14 PM PDT 24
Finished Jul 20 05:53:15 PM PDT 24
Peak memory 206820 kb
Host smart-86cac42a-9007-4f72-9643-abe686dd6d5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612643431 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.612643431
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3733017039
Short name T249
Test name
Test status
Simulation time 22310566 ps
CPU time 1.16 seconds
Started Jul 20 05:53:11 PM PDT 24
Finished Jul 20 05:53:13 PM PDT 24
Peak memory 206940 kb
Host smart-7228f563-bd56-4bba-aa1f-9aa53da5041d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733017039 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.3733017039
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.4575460
Short name T1064
Test name
Test status
Simulation time 67616693 ps
CPU time 2.36 seconds
Started Jul 20 05:53:10 PM PDT 24
Finished Jul 20 05:53:14 PM PDT 24
Peak memory 215128 kb
Host smart-7549e1e0-6d1a-423f-8b7d-dd28d9f5cac5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4575460 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.4575460
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.264391684
Short name T1076
Test name
Test status
Simulation time 596073628 ps
CPU time 5.19 seconds
Started Jul 20 05:53:08 PM PDT 24
Finished Jul 20 05:53:14 PM PDT 24
Peak memory 207044 kb
Host smart-158b4175-e1f8-4f9d-9e61-66db03a89bfc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264391684 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.264391684
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.173139792
Short name T1098
Test name
Test status
Simulation time 223273057 ps
CPU time 1.28 seconds
Started Jul 20 05:53:20 PM PDT 24
Finished Jul 20 05:53:23 PM PDT 24
Peak memory 215124 kb
Host smart-82fae0ce-56fc-4e52-888b-19c662131b52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173139792 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.173139792
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.450836061
Short name T251
Test name
Test status
Simulation time 29397067 ps
CPU time 1.05 seconds
Started Jul 20 05:53:20 PM PDT 24
Finished Jul 20 05:53:23 PM PDT 24
Peak memory 206820 kb
Host smart-e3227847-9bca-4b35-8f59-fc7840d56e74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450836061 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.450836061
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.197526610
Short name T1008
Test name
Test status
Simulation time 18099231 ps
CPU time 0.81 seconds
Started Jul 20 05:53:20 PM PDT 24
Finished Jul 20 05:53:22 PM PDT 24
Peak memory 206632 kb
Host smart-200c506b-25bf-4016-b3d4-8297e62c8ddc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197526610 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.197526610
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.4138921921
Short name T1085
Test name
Test status
Simulation time 52175647 ps
CPU time 1.35 seconds
Started Jul 20 05:53:20 PM PDT 24
Finished Jul 20 05:53:23 PM PDT 24
Peak memory 206792 kb
Host smart-4d7384e6-f0af-4ae3-aacc-4c2bd072cc12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138921921 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.4138921921
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.1330544293
Short name T1067
Test name
Test status
Simulation time 130643709 ps
CPU time 2.01 seconds
Started Jul 20 05:53:19 PM PDT 24
Finished Jul 20 05:53:22 PM PDT 24
Peak memory 215136 kb
Host smart-37a26eca-ebd3-47c7-a2ad-8dea61184a24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330544293 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.1330544293
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2413297903
Short name T1107
Test name
Test status
Simulation time 332909298 ps
CPU time 2.41 seconds
Started Jul 20 05:53:19 PM PDT 24
Finished Jul 20 05:53:23 PM PDT 24
Peak memory 207056 kb
Host smart-d3729523-7080-4978-920f-5a072eeb65f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413297903 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.2413297903
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1822312666
Short name T1019
Test name
Test status
Simulation time 18715076 ps
CPU time 1.28 seconds
Started Jul 20 05:53:19 PM PDT 24
Finished Jul 20 05:53:22 PM PDT 24
Peak memory 215244 kb
Host smart-ed5b282e-be91-4127-9b80-970efb370966
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822312666 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1822312666
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1727906734
Short name T1031
Test name
Test status
Simulation time 14488770 ps
CPU time 0.88 seconds
Started Jul 20 05:53:22 PM PDT 24
Finished Jul 20 05:53:25 PM PDT 24
Peak memory 206824 kb
Host smart-783dd79b-1139-4c4e-91e0-f3dbf5575448
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727906734 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1727906734
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.293772155
Short name T1043
Test name
Test status
Simulation time 14671583 ps
CPU time 0.93 seconds
Started Jul 20 05:53:19 PM PDT 24
Finished Jul 20 05:53:22 PM PDT 24
Peak memory 206824 kb
Host smart-9586e4de-c85e-4930-bf97-fb7798f4d3c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293772155 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.293772155
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.425751895
Short name T266
Test name
Test status
Simulation time 65207268 ps
CPU time 1.2 seconds
Started Jul 20 05:53:20 PM PDT 24
Finished Jul 20 05:53:22 PM PDT 24
Peak memory 206868 kb
Host smart-a9d883d8-9810-47f7-9762-a4be735d061d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425751895 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_out
standing.425751895
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.531563117
Short name T1078
Test name
Test status
Simulation time 205225491 ps
CPU time 2.44 seconds
Started Jul 20 05:53:21 PM PDT 24
Finished Jul 20 05:53:25 PM PDT 24
Peak memory 215208 kb
Host smart-b388db62-6ed8-48dd-abb8-2fe5092203db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531563117 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.531563117
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1501580900
Short name T273
Test name
Test status
Simulation time 92980168 ps
CPU time 2.55 seconds
Started Jul 20 05:53:18 PM PDT 24
Finished Jul 20 05:53:21 PM PDT 24
Peak memory 206900 kb
Host smart-fcb71114-48df-4e7e-9baf-fdba538e6375
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501580900 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.1501580900
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2896494262
Short name T1123
Test name
Test status
Simulation time 218438228 ps
CPU time 1.48 seconds
Started Jul 20 05:53:20 PM PDT 24
Finished Jul 20 05:53:23 PM PDT 24
Peak memory 215108 kb
Host smart-0a6910c4-b327-4688-9b75-d2a18f18f8a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896494262 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.2896494262
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.342866727
Short name T1054
Test name
Test status
Simulation time 38417553 ps
CPU time 0.86 seconds
Started Jul 20 05:53:20 PM PDT 24
Finished Jul 20 05:53:23 PM PDT 24
Peak memory 206628 kb
Host smart-910f3260-010e-4daa-8abf-7aceb490c73b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342866727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.342866727
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.1181522712
Short name T1116
Test name
Test status
Simulation time 156060672 ps
CPU time 0.9 seconds
Started Jul 20 05:53:17 PM PDT 24
Finished Jul 20 05:53:19 PM PDT 24
Peak memory 206620 kb
Host smart-1def2c60-b13e-4887-93f7-1e8fbe60b867
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181522712 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1181522712
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.4158746649
Short name T263
Test name
Test status
Simulation time 23361916 ps
CPU time 1.05 seconds
Started Jul 20 05:53:24 PM PDT 24
Finished Jul 20 05:53:26 PM PDT 24
Peak memory 206912 kb
Host smart-13c7fe97-4923-4e8a-bb01-3a26c731f2bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158746649 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.4158746649
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.132357
Short name T1073
Test name
Test status
Simulation time 175905243 ps
CPU time 2.03 seconds
Started Jul 20 05:53:24 PM PDT 24
Finished Jul 20 05:53:27 PM PDT 24
Peak memory 215104 kb
Host smart-7553227e-2dce-44ee-ad25-a36654744feb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132357 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.132357
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2605831112
Short name T1080
Test name
Test status
Simulation time 142377739 ps
CPU time 1.61 seconds
Started Jul 20 05:53:20 PM PDT 24
Finished Jul 20 05:53:23 PM PDT 24
Peak memory 215212 kb
Host smart-a4551684-072b-4e53-80e7-6683e23cc818
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605831112 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2605831112
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2740248829
Short name T1044
Test name
Test status
Simulation time 100328632 ps
CPU time 1.43 seconds
Started Jul 20 05:53:17 PM PDT 24
Finished Jul 20 05:53:19 PM PDT 24
Peak memory 217908 kb
Host smart-49c99ddb-2873-4eae-9094-db27f4615e41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740248829 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.2740248829
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.3201123707
Short name T1048
Test name
Test status
Simulation time 34364037 ps
CPU time 0.81 seconds
Started Jul 20 05:53:17 PM PDT 24
Finished Jul 20 05:53:19 PM PDT 24
Peak memory 206564 kb
Host smart-ab8f5454-8169-4691-8316-7f56863cc6e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201123707 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3201123707
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.1346339288
Short name T1113
Test name
Test status
Simulation time 37563621 ps
CPU time 0.83 seconds
Started Jul 20 05:53:16 PM PDT 24
Finished Jul 20 05:53:19 PM PDT 24
Peak memory 206560 kb
Host smart-35efbcdd-a930-4b97-b182-bb6d816cbd30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346339288 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.1346339288
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.568316705
Short name T1099
Test name
Test status
Simulation time 23654245 ps
CPU time 0.95 seconds
Started Jul 20 05:53:24 PM PDT 24
Finished Jul 20 05:53:26 PM PDT 24
Peak memory 206836 kb
Host smart-0e83e61f-5c6a-4485-9236-1ec75b23b980
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568316705 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_out
standing.568316705
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.2643419459
Short name T1011
Test name
Test status
Simulation time 96336479 ps
CPU time 1.79 seconds
Started Jul 20 05:53:22 PM PDT 24
Finished Jul 20 05:53:26 PM PDT 24
Peak memory 215240 kb
Host smart-27cdcb07-eab0-4596-b4c3-39549d736869
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643419459 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.2643419459
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3609026231
Short name T281
Test name
Test status
Simulation time 267533944 ps
CPU time 1.56 seconds
Started Jul 20 05:53:19 PM PDT 24
Finished Jul 20 05:53:22 PM PDT 24
Peak memory 215092 kb
Host smart-dbdb4e79-be0e-480a-82bb-ffd7196dca8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609026231 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3609026231
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.3217178971
Short name T937
Test name
Test status
Simulation time 62543411 ps
CPU time 1.12 seconds
Started Jul 20 06:48:59 PM PDT 24
Finished Jul 20 06:49:02 PM PDT 24
Peak memory 221068 kb
Host smart-6187fc07-d540-412e-9b86-e2ede2be34ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217178971 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3217178971
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.2352996215
Short name T548
Test name
Test status
Simulation time 54050550 ps
CPU time 0.94 seconds
Started Jul 20 06:49:02 PM PDT 24
Finished Jul 20 06:49:04 PM PDT 24
Peak memory 207044 kb
Host smart-b6d884ad-b7c7-40e8-8dd0-a0607c978557
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352996215 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2352996215
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.1675574621
Short name T520
Test name
Test status
Simulation time 26499767 ps
CPU time 1.12 seconds
Started Jul 20 06:48:59 PM PDT 24
Finished Jul 20 06:49:02 PM PDT 24
Peak memory 217056 kb
Host smart-80e794bc-f0ab-43f7-ad82-6303019bead1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675574621 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.1675574621
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.2120069718
Short name T596
Test name
Test status
Simulation time 52913085 ps
CPU time 0.84 seconds
Started Jul 20 06:49:00 PM PDT 24
Finished Jul 20 06:49:02 PM PDT 24
Peak memory 218524 kb
Host smart-d7fb49bd-e7bb-4666-a10c-d9485613cab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120069718 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.2120069718
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_regwen.626899879
Short name T820
Test name
Test status
Simulation time 29838129 ps
CPU time 0.96 seconds
Started Jul 20 06:49:00 PM PDT 24
Finished Jul 20 06:49:02 PM PDT 24
Peak memory 207376 kb
Host smart-bbd04fc9-f34a-4d0e-acdf-22f44411a5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626899879 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.626899879
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_smoke.1849118892
Short name T337
Test name
Test status
Simulation time 23761529 ps
CPU time 0.92 seconds
Started Jul 20 06:48:56 PM PDT 24
Finished Jul 20 06:48:59 PM PDT 24
Peak memory 215572 kb
Host smart-44286676-3010-4a78-94fc-2a4b91c33f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849118892 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.1849118892
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.388946015
Short name T738
Test name
Test status
Simulation time 783678289 ps
CPU time 2.7 seconds
Started Jul 20 06:48:59 PM PDT 24
Finished Jul 20 06:49:03 PM PDT 24
Peak memory 217604 kb
Host smart-9a2df2de-7349-43c1-a4a8-b0e4e507f78b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388946015 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.388946015
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.1201357278
Short name T789
Test name
Test status
Simulation time 353281128957 ps
CPU time 2069.62 seconds
Started Jul 20 06:48:57 PM PDT 24
Finished Jul 20 07:23:29 PM PDT 24
Peak memory 227284 kb
Host smart-b9689413-5206-4bfb-9f9f-e8ead056decc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201357278 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.1201357278
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.1967602417
Short name T170
Test name
Test status
Simulation time 84021317 ps
CPU time 1.15 seconds
Started Jul 20 06:48:58 PM PDT 24
Finished Jul 20 06:49:01 PM PDT 24
Peak memory 219960 kb
Host smart-c5c8fea4-a9f3-4d1b-9a0c-2ca53028a4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967602417 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1967602417
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.1300134169
Short name T483
Test name
Test status
Simulation time 33412357 ps
CPU time 0.87 seconds
Started Jul 20 06:49:02 PM PDT 24
Finished Jul 20 06:49:04 PM PDT 24
Peak memory 206856 kb
Host smart-61dc6c31-d9c5-49c3-b91c-45dc41efe2be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300134169 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1300134169
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.3490565663
Short name T373
Test name
Test status
Simulation time 21993634 ps
CPU time 0.9 seconds
Started Jul 20 06:49:02 PM PDT 24
Finished Jul 20 06:49:04 PM PDT 24
Peak memory 216276 kb
Host smart-a0f29fbf-354c-4f7b-94e7-777c3d6f2007
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490565663 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3490565663
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_err.1177054915
Short name T142
Test name
Test status
Simulation time 47902288 ps
CPU time 1.17 seconds
Started Jul 20 06:49:01 PM PDT 24
Finished Jul 20 06:49:03 PM PDT 24
Peak memory 224320 kb
Host smart-80d6aa5f-74fb-48d7-919e-17cc474082fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177054915 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.1177054915
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.694127057
Short name T838
Test name
Test status
Simulation time 166422990 ps
CPU time 1.61 seconds
Started Jul 20 06:49:02 PM PDT 24
Finished Jul 20 06:49:05 PM PDT 24
Peak memory 219092 kb
Host smart-97c6ef1d-7c13-4ec1-ad03-1928836057d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694127057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.694127057
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.4223916519
Short name T446
Test name
Test status
Simulation time 53641065 ps
CPU time 0.94 seconds
Started Jul 20 06:49:02 PM PDT 24
Finished Jul 20 06:49:04 PM PDT 24
Peak memory 215552 kb
Host smart-8aaef061-cd71-426a-a653-904e8e9cc4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223916519 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.4223916519
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.1287289316
Short name T24
Test name
Test status
Simulation time 26550318 ps
CPU time 0.97 seconds
Started Jul 20 06:49:01 PM PDT 24
Finished Jul 20 06:49:03 PM PDT 24
Peak memory 207284 kb
Host smart-3f777b4a-106a-42b1-bfab-4d4663d1b4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287289316 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.1287289316
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.1264823382
Short name T63
Test name
Test status
Simulation time 1089043346 ps
CPU time 8.57 seconds
Started Jul 20 06:49:02 PM PDT 24
Finished Jul 20 06:49:11 PM PDT 24
Peak memory 236632 kb
Host smart-de413560-15d3-4414-b9bc-6ab2f50ef210
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264823382 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.1264823382
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.3107328870
Short name T521
Test name
Test status
Simulation time 18505386 ps
CPU time 1.04 seconds
Started Jul 20 06:48:58 PM PDT 24
Finished Jul 20 06:49:01 PM PDT 24
Peak memory 215572 kb
Host smart-370d3579-a5d9-4ed2-a4aa-3c7acfe8773e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107328870 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.3107328870
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.1026971944
Short name T416
Test name
Test status
Simulation time 53884996 ps
CPU time 1.61 seconds
Started Jul 20 06:49:02 PM PDT 24
Finished Jul 20 06:49:04 PM PDT 24
Peak memory 218548 kb
Host smart-bfe8cb7c-7624-4e1c-b543-a607eb2af927
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026971944 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.1026971944
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.3954617459
Short name T233
Test name
Test status
Simulation time 53822262301 ps
CPU time 1217.56 seconds
Started Jul 20 06:49:00 PM PDT 24
Finished Jul 20 07:09:19 PM PDT 24
Peak memory 223900 kb
Host smart-1853ca22-ca6a-4530-bd05-af399618cd48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954617459 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.3954617459
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.176562058
Short name T972
Test name
Test status
Simulation time 41472677 ps
CPU time 1.2 seconds
Started Jul 20 06:49:26 PM PDT 24
Finished Jul 20 06:49:28 PM PDT 24
Peak memory 220060 kb
Host smart-3268b0d9-4fa7-4380-a546-deac7a0b267f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176562058 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.176562058
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.2223193150
Short name T928
Test name
Test status
Simulation time 40654429 ps
CPU time 0.83 seconds
Started Jul 20 06:49:24 PM PDT 24
Finished Jul 20 06:49:26 PM PDT 24
Peak memory 207096 kb
Host smart-8b40b558-51ee-4c53-8116-1b7fee00229a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223193150 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2223193150
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.3389152282
Short name T527
Test name
Test status
Simulation time 14024695 ps
CPU time 0.96 seconds
Started Jul 20 06:49:27 PM PDT 24
Finished Jul 20 06:49:29 PM PDT 24
Peak memory 216692 kb
Host smart-fd8de00c-b4e3-438e-8c42-fdeaa9063927
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389152282 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.3389152282
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.2018124465
Short name T415
Test name
Test status
Simulation time 40349211 ps
CPU time 1.07 seconds
Started Jul 20 06:49:29 PM PDT 24
Finished Jul 20 06:49:30 PM PDT 24
Peak memory 218740 kb
Host smart-fbf114a4-8fd5-483b-97d3-2da059e7c7bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018124465 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.2018124465
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.4243724796
Short name T442
Test name
Test status
Simulation time 20401917 ps
CPU time 1.1 seconds
Started Jul 20 06:49:23 PM PDT 24
Finished Jul 20 06:49:25 PM PDT 24
Peak memory 219740 kb
Host smart-1153b071-f500-4e54-9380-7e51c433c691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243724796 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.4243724796
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.3531106428
Short name T85
Test name
Test status
Simulation time 125603344 ps
CPU time 1.31 seconds
Started Jul 20 06:49:25 PM PDT 24
Finished Jul 20 06:49:27 PM PDT 24
Peak memory 219108 kb
Host smart-42a75d52-25a0-433b-b72d-01b1820dddf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531106428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3531106428
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.1156553595
Short name T524
Test name
Test status
Simulation time 42752101 ps
CPU time 1.02 seconds
Started Jul 20 06:49:22 PM PDT 24
Finished Jul 20 06:49:24 PM PDT 24
Peak memory 224352 kb
Host smart-d211f2df-4c84-4ae9-b6c7-7ee8e765b38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156553595 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1156553595
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.3449081529
Short name T809
Test name
Test status
Simulation time 58974875 ps
CPU time 0.93 seconds
Started Jul 20 06:49:22 PM PDT 24
Finished Jul 20 06:49:23 PM PDT 24
Peak memory 215564 kb
Host smart-48c4378c-cca9-474f-a0b5-22557af7744b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449081529 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.3449081529
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.837236778
Short name T566
Test name
Test status
Simulation time 195514727 ps
CPU time 4.09 seconds
Started Jul 20 06:49:22 PM PDT 24
Finished Jul 20 06:49:26 PM PDT 24
Peak memory 217664 kb
Host smart-02c4bf79-9268-4058-9abf-9b72aac3ce94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837236778 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.837236778
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.4269578018
Short name T1
Test name
Test status
Simulation time 235368522443 ps
CPU time 474.64 seconds
Started Jul 20 06:49:24 PM PDT 24
Finished Jul 20 06:57:20 PM PDT 24
Peak memory 219716 kb
Host smart-0ce90b57-9cbf-4960-8bae-bb81933653dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269578018 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.4269578018
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.2283813687
Short name T13
Test name
Test status
Simulation time 42075912 ps
CPU time 1.56 seconds
Started Jul 20 06:50:54 PM PDT 24
Finished Jul 20 06:50:58 PM PDT 24
Peak memory 220412 kb
Host smart-74c80023-9332-4a8c-b9a5-b0572778dce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283813687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2283813687
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.757937540
Short name T686
Test name
Test status
Simulation time 87516148 ps
CPU time 1.2 seconds
Started Jul 20 06:50:56 PM PDT 24
Finished Jul 20 06:50:59 PM PDT 24
Peak memory 221120 kb
Host smart-1bcddeff-ae82-418e-bc1e-a93b1b2c574f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757937540 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.757937540
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.1832358349
Short name T717
Test name
Test status
Simulation time 79564105 ps
CPU time 1.5 seconds
Started Jul 20 06:51:02 PM PDT 24
Finished Jul 20 06:51:04 PM PDT 24
Peak memory 219440 kb
Host smart-41351f9b-ca06-439e-a546-8187098ee760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832358349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.1832358349
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.1941430866
Short name T851
Test name
Test status
Simulation time 68626872 ps
CPU time 1.13 seconds
Started Jul 20 06:50:57 PM PDT 24
Finished Jul 20 06:51:00 PM PDT 24
Peak memory 221152 kb
Host smart-f1a4f8ae-4959-4360-9883-09ac73d31f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941430866 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.1941430866
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.40183738
Short name T343
Test name
Test status
Simulation time 45255523 ps
CPU time 1.48 seconds
Started Jul 20 06:50:56 PM PDT 24
Finished Jul 20 06:50:59 PM PDT 24
Peak memory 218644 kb
Host smart-eba16c10-e98d-454c-b017-5951dc11d792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40183738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.40183738
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.887304990
Short name T46
Test name
Test status
Simulation time 24468828 ps
CPU time 1.24 seconds
Started Jul 20 06:50:55 PM PDT 24
Finished Jul 20 06:50:58 PM PDT 24
Peak memory 220276 kb
Host smart-7bc19736-71a7-4ceb-81c3-017707a913a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887304990 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.887304990
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.757409358
Short name T517
Test name
Test status
Simulation time 116324818 ps
CPU time 1.52 seconds
Started Jul 20 06:50:55 PM PDT 24
Finished Jul 20 06:50:58 PM PDT 24
Peak memory 219532 kb
Host smart-7fba523a-6c87-4781-8093-3bcdf8ecf20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757409358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.757409358
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.1792572850
Short name T489
Test name
Test status
Simulation time 185634165 ps
CPU time 1.22 seconds
Started Jul 20 06:50:57 PM PDT 24
Finished Jul 20 06:51:00 PM PDT 24
Peak memory 216124 kb
Host smart-58e01e94-a5e5-4acc-8d8c-e5a6aaff1b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792572850 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.1792572850
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.3500401113
Short name T372
Test name
Test status
Simulation time 54127329 ps
CPU time 1.87 seconds
Started Jul 20 06:51:01 PM PDT 24
Finished Jul 20 06:51:03 PM PDT 24
Peak memory 218552 kb
Host smart-8c5ce1ef-8b8f-4441-a5ca-daa9e10d0c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500401113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.3500401113
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.2719227207
Short name T734
Test name
Test status
Simulation time 178620145 ps
CPU time 1.15 seconds
Started Jul 20 06:50:57 PM PDT 24
Finished Jul 20 06:51:00 PM PDT 24
Peak memory 220088 kb
Host smart-afe3dee9-10ce-42e0-82de-b6958f7e7b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719227207 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.2719227207
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/106.edn_alert.3694442422
Short name T708
Test name
Test status
Simulation time 49119515 ps
CPU time 1.11 seconds
Started Jul 20 06:50:55 PM PDT 24
Finished Jul 20 06:50:58 PM PDT 24
Peak memory 221088 kb
Host smart-0fc467e6-a240-4edb-b32e-e5838be154d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694442422 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.3694442422
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.3488181829
Short name T814
Test name
Test status
Simulation time 48800078 ps
CPU time 1.41 seconds
Started Jul 20 06:50:54 PM PDT 24
Finished Jul 20 06:50:57 PM PDT 24
Peak memory 219020 kb
Host smart-baf80612-c535-4f87-ab49-ed929acc17e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488181829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.3488181829
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.319338611
Short name T274
Test name
Test status
Simulation time 80348406 ps
CPU time 1.26 seconds
Started Jul 20 06:50:56 PM PDT 24
Finished Jul 20 06:50:59 PM PDT 24
Peak memory 219656 kb
Host smart-1fb6a39f-08a0-4887-b707-6aee8703265b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319338611 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.319338611
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.2485952684
Short name T465
Test name
Test status
Simulation time 8743935538 ps
CPU time 117.1 seconds
Started Jul 20 06:51:02 PM PDT 24
Finished Jul 20 06:53:00 PM PDT 24
Peak memory 220636 kb
Host smart-7d4a603c-06d9-4cda-92c0-de5ee9e9a644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485952684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2485952684
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.3950692497
Short name T276
Test name
Test status
Simulation time 94689776 ps
CPU time 1.37 seconds
Started Jul 20 06:50:57 PM PDT 24
Finished Jul 20 06:51:00 PM PDT 24
Peak memory 218924 kb
Host smart-bf588905-7fad-48bf-be92-b9e28d317487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950692497 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.3950692497
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.2916875434
Short name T662
Test name
Test status
Simulation time 180594436 ps
CPU time 1.17 seconds
Started Jul 20 06:50:54 PM PDT 24
Finished Jul 20 06:50:57 PM PDT 24
Peak memory 220292 kb
Host smart-312484a3-6b97-431e-82b1-add9dce5bcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916875434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.2916875434
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.412937942
Short name T824
Test name
Test status
Simulation time 28959273 ps
CPU time 1.31 seconds
Started Jul 20 06:50:55 PM PDT 24
Finished Jul 20 06:50:58 PM PDT 24
Peak memory 218984 kb
Host smart-95307d41-00fe-44c3-b779-c1678a0fa215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412937942 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.412937942
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.3776398694
Short name T891
Test name
Test status
Simulation time 115180922 ps
CPU time 1.75 seconds
Started Jul 20 06:51:01 PM PDT 24
Finished Jul 20 06:51:04 PM PDT 24
Peak memory 218984 kb
Host smart-66c696ec-506d-428f-b23b-1c463ad0dc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776398694 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3776398694
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.3648825830
Short name T286
Test name
Test status
Simulation time 29729459 ps
CPU time 1.28 seconds
Started Jul 20 06:49:26 PM PDT 24
Finished Jul 20 06:49:29 PM PDT 24
Peak memory 219768 kb
Host smart-3b7a161e-9ceb-4620-9177-9cd17c384acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648825830 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.3648825830
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.1030371350
Short name T826
Test name
Test status
Simulation time 33529926 ps
CPU time 0.97 seconds
Started Jul 20 06:49:26 PM PDT 24
Finished Jul 20 06:49:28 PM PDT 24
Peak memory 207048 kb
Host smart-e73778ea-59c6-43ac-9c70-70778111fdcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030371350 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.1030371350
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.2330322651
Short name T901
Test name
Test status
Simulation time 10834724 ps
CPU time 0.94 seconds
Started Jul 20 06:49:24 PM PDT 24
Finished Jul 20 06:49:26 PM PDT 24
Peak memory 215644 kb
Host smart-be055bce-da33-4556-a453-0b58ef23b3a0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330322651 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.2330322651
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.4023804307
Short name T269
Test name
Test status
Simulation time 38251347 ps
CPU time 1.08 seconds
Started Jul 20 06:49:22 PM PDT 24
Finished Jul 20 06:49:24 PM PDT 24
Peak memory 217016 kb
Host smart-12426ddd-746c-41c2-af7a-7102d45cc2d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023804307 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.4023804307
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.2982535886
Short name T132
Test name
Test status
Simulation time 32667850 ps
CPU time 1.27 seconds
Started Jul 20 06:49:22 PM PDT 24
Finished Jul 20 06:49:23 PM PDT 24
Peak memory 229932 kb
Host smart-769b4e0d-1782-4b14-bc14-cf95d627ccba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982535886 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.2982535886
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.1064766233
Short name T428
Test name
Test status
Simulation time 42596415 ps
CPU time 1.17 seconds
Started Jul 20 06:49:25 PM PDT 24
Finished Jul 20 06:49:28 PM PDT 24
Peak memory 217400 kb
Host smart-1e8f0a54-0572-4b90-83a0-a7c64770789d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064766233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1064766233
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.1222636548
Short name T576
Test name
Test status
Simulation time 23271734 ps
CPU time 1.13 seconds
Started Jul 20 06:49:23 PM PDT 24
Finished Jul 20 06:49:26 PM PDT 24
Peak memory 215940 kb
Host smart-be14f942-4a25-49db-b0d9-5f9cda26daa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222636548 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.1222636548
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.1772993808
Short name T351
Test name
Test status
Simulation time 24898835 ps
CPU time 0.98 seconds
Started Jul 20 06:49:29 PM PDT 24
Finished Jul 20 06:49:30 PM PDT 24
Peak memory 215548 kb
Host smart-8820a301-5fe2-4d7a-9c9a-d93cd41bf494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772993808 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.1772993808
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.3529579264
Short name T431
Test name
Test status
Simulation time 289064970 ps
CPU time 5.86 seconds
Started Jul 20 06:49:26 PM PDT 24
Finished Jul 20 06:49:33 PM PDT 24
Peak memory 217484 kb
Host smart-aee0441f-8aaf-4ff2-af7d-a2b1308949bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529579264 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.3529579264
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2040613121
Short name T919
Test name
Test status
Simulation time 52283246608 ps
CPU time 1333.88 seconds
Started Jul 20 06:49:24 PM PDT 24
Finished Jul 20 07:11:40 PM PDT 24
Peak memory 224144 kb
Host smart-49d2b9d1-445c-46df-980e-93f262350f97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040613121 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2040613121
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.3724674559
Short name T60
Test name
Test status
Simulation time 35588881 ps
CPU time 1.35 seconds
Started Jul 20 06:50:56 PM PDT 24
Finished Jul 20 06:50:59 PM PDT 24
Peak memory 220532 kb
Host smart-bf36ee0f-f1d4-44f6-904b-0113395aefbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724674559 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.3724674559
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/111.edn_alert.1450537594
Short name T122
Test name
Test status
Simulation time 90729677 ps
CPU time 1.27 seconds
Started Jul 20 06:51:02 PM PDT 24
Finished Jul 20 06:51:04 PM PDT 24
Peak memory 218724 kb
Host smart-ad563834-d401-4963-82a2-0dfc79addd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450537594 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.1450537594
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.141431875
Short name T365
Test name
Test status
Simulation time 34455609 ps
CPU time 1.55 seconds
Started Jul 20 06:50:56 PM PDT 24
Finished Jul 20 06:51:00 PM PDT 24
Peak memory 218840 kb
Host smart-b937577c-b017-4026-8a11-a7b27951e487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141431875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.141431875
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.1022809773
Short name T417
Test name
Test status
Simulation time 107442631 ps
CPU time 2.28 seconds
Started Jul 20 06:50:54 PM PDT 24
Finished Jul 20 06:50:59 PM PDT 24
Peak memory 215544 kb
Host smart-16984725-7f7b-4d5d-9673-7d825daed9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022809773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.1022809773
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.3085859580
Short name T143
Test name
Test status
Simulation time 49550766 ps
CPU time 1.23 seconds
Started Jul 20 06:50:54 PM PDT 24
Finished Jul 20 06:50:57 PM PDT 24
Peak memory 216000 kb
Host smart-b34f3236-d7b8-4827-88ef-533664c1f7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085859580 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.3085859580
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.3340112572
Short name T818
Test name
Test status
Simulation time 112137112 ps
CPU time 1.41 seconds
Started Jul 20 06:51:01 PM PDT 24
Finished Jul 20 06:51:02 PM PDT 24
Peak memory 219128 kb
Host smart-56da464e-32a2-4e93-a910-d7eff2d2e709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340112572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3340112572
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.76553303
Short name T796
Test name
Test status
Simulation time 70922307 ps
CPU time 1.42 seconds
Started Jul 20 06:50:54 PM PDT 24
Finished Jul 20 06:50:58 PM PDT 24
Peak memory 219184 kb
Host smart-5465e7bf-1c98-4eb8-9f06-a5a1756b65ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76553303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.76553303
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.1868213772
Short name T166
Test name
Test status
Simulation time 29768956 ps
CPU time 1.31 seconds
Started Jul 20 06:50:58 PM PDT 24
Finished Jul 20 06:51:00 PM PDT 24
Peak memory 216024 kb
Host smart-018126d8-5dbc-4166-a54e-6b3557b892b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868213772 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.1868213772
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.3073421566
Short name T325
Test name
Test status
Simulation time 57064070 ps
CPU time 2.06 seconds
Started Jul 20 06:50:54 PM PDT 24
Finished Jul 20 06:50:58 PM PDT 24
Peak memory 219116 kb
Host smart-7b9bb6b6-1a3d-49de-beb1-4dc3596b52a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073421566 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.3073421566
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.2645935796
Short name T638
Test name
Test status
Simulation time 235846785 ps
CPU time 1.21 seconds
Started Jul 20 06:50:57 PM PDT 24
Finished Jul 20 06:51:00 PM PDT 24
Peak memory 219972 kb
Host smart-0496f7a4-f96a-4bfc-9d75-467d08fb6c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645935796 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.2645935796
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.3928073220
Short name T396
Test name
Test status
Simulation time 102275964 ps
CPU time 1.42 seconds
Started Jul 20 06:51:02 PM PDT 24
Finished Jul 20 06:51:05 PM PDT 24
Peak memory 218700 kb
Host smart-873a6ef2-5c7a-4d74-a4b8-d9ef8efcb7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928073220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3928073220
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.2348913399
Short name T402
Test name
Test status
Simulation time 52638370 ps
CPU time 1.34 seconds
Started Jul 20 06:50:54 PM PDT 24
Finished Jul 20 06:50:57 PM PDT 24
Peak memory 215972 kb
Host smart-4d7c4d2b-51fd-4fe2-b7ec-af103633cf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348913399 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.2348913399
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.3334885887
Short name T306
Test name
Test status
Simulation time 127466648 ps
CPU time 1.64 seconds
Started Jul 20 06:50:55 PM PDT 24
Finished Jul 20 06:50:58 PM PDT 24
Peak memory 219040 kb
Host smart-488a38cf-43af-4e98-bf27-c42e5310eaea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334885887 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3334885887
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.4196687409
Short name T183
Test name
Test status
Simulation time 88720314 ps
CPU time 1.26 seconds
Started Jul 20 06:51:02 PM PDT 24
Finished Jul 20 06:51:05 PM PDT 24
Peak memory 221024 kb
Host smart-e3ca664e-69f3-4343-b18f-65f0fbcf8cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196687409 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.4196687409
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.3600816774
Short name T994
Test name
Test status
Simulation time 194065729 ps
CPU time 2.77 seconds
Started Jul 20 06:50:55 PM PDT 24
Finished Jul 20 06:50:59 PM PDT 24
Peak memory 220436 kb
Host smart-56702f2f-c139-4671-8db9-ec19c4457aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600816774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3600816774
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.4187464441
Short name T729
Test name
Test status
Simulation time 312915666 ps
CPU time 1.13 seconds
Started Jul 20 06:49:24 PM PDT 24
Finished Jul 20 06:49:26 PM PDT 24
Peak memory 216056 kb
Host smart-e58978d9-df3b-4d89-b56d-525fdf2833eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187464441 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.4187464441
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_disable.1326996817
Short name T205
Test name
Test status
Simulation time 22913565 ps
CPU time 0.86 seconds
Started Jul 20 06:49:24 PM PDT 24
Finished Jul 20 06:49:27 PM PDT 24
Peak memory 216576 kb
Host smart-0e30755e-c749-4072-a33d-7d2b10317291
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326996817 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.1326996817
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_err.4042244928
Short name T613
Test name
Test status
Simulation time 26031942 ps
CPU time 1.28 seconds
Started Jul 20 06:49:29 PM PDT 24
Finished Jul 20 06:49:31 PM PDT 24
Peak memory 219020 kb
Host smart-5a4761fb-d1c2-4cfd-a95a-91e496b6b25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042244928 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.4042244928
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.2551479739
Short name T913
Test name
Test status
Simulation time 65391283 ps
CPU time 1.41 seconds
Started Jul 20 06:49:24 PM PDT 24
Finished Jul 20 06:49:27 PM PDT 24
Peak memory 217556 kb
Host smart-257e763a-1e51-4a94-a4f8-3ef89a9b5ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551479739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2551479739
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.4042337381
Short name T28
Test name
Test status
Simulation time 20167958 ps
CPU time 1.13 seconds
Started Jul 20 06:49:23 PM PDT 24
Finished Jul 20 06:49:26 PM PDT 24
Peak memory 216276 kb
Host smart-268e5eaf-63f0-41cd-936c-133d372a1828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042337381 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.4042337381
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.1407928184
Short name T350
Test name
Test status
Simulation time 15184154 ps
CPU time 0.99 seconds
Started Jul 20 06:49:23 PM PDT 24
Finished Jul 20 06:49:24 PM PDT 24
Peak memory 215576 kb
Host smart-8e2558e0-2e81-49d8-a56d-2bba4ed93f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407928184 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.1407928184
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.2184177368
Short name T58
Test name
Test status
Simulation time 439804173 ps
CPU time 4.77 seconds
Started Jul 20 06:49:23 PM PDT 24
Finished Jul 20 06:49:28 PM PDT 24
Peak memory 215588 kb
Host smart-94e20673-bc21-4109-a921-307dc1377ef5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184177368 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2184177368
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.4249058406
Short name T570
Test name
Test status
Simulation time 124479759781 ps
CPU time 2417.92 seconds
Started Jul 20 06:49:24 PM PDT 24
Finished Jul 20 07:29:44 PM PDT 24
Peak memory 231596 kb
Host smart-b8b036d0-3d22-4371-8115-9d3485b496f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249058406 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.4249058406
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.4005895393
Short name T41
Test name
Test status
Simulation time 30904760 ps
CPU time 1.31 seconds
Started Jul 20 06:51:02 PM PDT 24
Finished Jul 20 06:51:04 PM PDT 24
Peak memory 219368 kb
Host smart-03cb37c9-6c80-4e78-8a6d-492c0afc3ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005895393 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.4005895393
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/122.edn_alert.2877429262
Short name T866
Test name
Test status
Simulation time 29092298 ps
CPU time 1.25 seconds
Started Jul 20 06:51:01 PM PDT 24
Finished Jul 20 06:51:03 PM PDT 24
Peak memory 218988 kb
Host smart-5e334bc3-c7ff-4dd1-98e7-eac46c3458c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877429262 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.2877429262
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.3476493836
Short name T236
Test name
Test status
Simulation time 51386151 ps
CPU time 1.55 seconds
Started Jul 20 06:51:03 PM PDT 24
Finished Jul 20 06:51:06 PM PDT 24
Peak memory 215560 kb
Host smart-9a77b0b4-bb21-466f-b13e-3500f6c18ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476493836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.3476493836
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.3757675397
Short name T293
Test name
Test status
Simulation time 25338453 ps
CPU time 1.24 seconds
Started Jul 20 06:51:09 PM PDT 24
Finished Jul 20 06:51:11 PM PDT 24
Peak memory 219084 kb
Host smart-ec959b03-0a53-46a6-9348-40c5673fd615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757675397 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.3757675397
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.1798748645
Short name T754
Test name
Test status
Simulation time 89830615 ps
CPU time 1.14 seconds
Started Jul 20 06:51:03 PM PDT 24
Finished Jul 20 06:51:05 PM PDT 24
Peak memory 217604 kb
Host smart-f0f512c2-e529-4261-89eb-58dd8ac3e361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798748645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.1798748645
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.2805143129
Short name T290
Test name
Test status
Simulation time 80567443 ps
CPU time 1.25 seconds
Started Jul 20 06:51:05 PM PDT 24
Finished Jul 20 06:51:07 PM PDT 24
Peak memory 219956 kb
Host smart-2454e7d5-d5d5-455c-9301-ec6ee04bd145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805143129 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.2805143129
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.1842342392
Short name T525
Test name
Test status
Simulation time 93233388 ps
CPU time 1.23 seconds
Started Jul 20 06:51:09 PM PDT 24
Finished Jul 20 06:51:11 PM PDT 24
Peak memory 219668 kb
Host smart-f7f696c4-bf2b-4e64-95ed-fef038482c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842342392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1842342392
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.288791302
Short name T831
Test name
Test status
Simulation time 31758452 ps
CPU time 1.33 seconds
Started Jul 20 06:51:02 PM PDT 24
Finished Jul 20 06:51:04 PM PDT 24
Peak memory 219968 kb
Host smart-84c2f8f0-3e3a-47fc-97ea-2dfc09be1cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288791302 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.288791302
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.492178255
Short name T435
Test name
Test status
Simulation time 85731092 ps
CPU time 1.33 seconds
Started Jul 20 06:51:03 PM PDT 24
Finished Jul 20 06:51:06 PM PDT 24
Peak memory 218608 kb
Host smart-28bfd461-4db4-4459-96c9-caff13793944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492178255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.492178255
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.560334917
Short name T221
Test name
Test status
Simulation time 44470857 ps
CPU time 1.26 seconds
Started Jul 20 06:51:04 PM PDT 24
Finished Jul 20 06:51:06 PM PDT 24
Peak memory 219540 kb
Host smart-127a8448-726d-4022-9e0f-94095fed24fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560334917 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.560334917
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/127.edn_alert.3706879560
Short name T425
Test name
Test status
Simulation time 47424119 ps
CPU time 1.25 seconds
Started Jul 20 06:51:04 PM PDT 24
Finished Jul 20 06:51:07 PM PDT 24
Peak memory 219588 kb
Host smart-05764b66-27ab-4590-853e-7a90dbcd2371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706879560 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.3706879560
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.2940300613
Short name T278
Test name
Test status
Simulation time 45979355 ps
CPU time 1.58 seconds
Started Jul 20 06:51:03 PM PDT 24
Finished Jul 20 06:51:06 PM PDT 24
Peak memory 218584 kb
Host smart-96dbc8e5-7ffb-49d6-8852-792b74cfb6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940300613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.2940300613
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.2972150109
Short name T626
Test name
Test status
Simulation time 39161153 ps
CPU time 1.09 seconds
Started Jul 20 06:51:06 PM PDT 24
Finished Jul 20 06:51:08 PM PDT 24
Peak memory 219024 kb
Host smart-c55f6958-3b5b-42ed-8ee0-4e219ead43a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972150109 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.2972150109
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.437465249
Short name T612
Test name
Test status
Simulation time 32971508 ps
CPU time 1.32 seconds
Started Jul 20 06:51:04 PM PDT 24
Finished Jul 20 06:51:07 PM PDT 24
Peak memory 219056 kb
Host smart-f7a948b8-df27-4170-b388-fc409b344540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437465249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.437465249
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.3949757804
Short name T741
Test name
Test status
Simulation time 149058748 ps
CPU time 1.29 seconds
Started Jul 20 06:51:07 PM PDT 24
Finished Jul 20 06:51:10 PM PDT 24
Peak memory 218668 kb
Host smart-c54a462e-47a9-4002-9a8c-978aee824dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949757804 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.3949757804
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert.3545506952
Short name T740
Test name
Test status
Simulation time 86057947 ps
CPU time 1.13 seconds
Started Jul 20 06:49:23 PM PDT 24
Finished Jul 20 06:49:25 PM PDT 24
Peak memory 219712 kb
Host smart-da53b4b8-6e1d-49c4-8caf-7b9845a921cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545506952 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.3545506952
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.3621110500
Short name T48
Test name
Test status
Simulation time 22498234 ps
CPU time 0.91 seconds
Started Jul 20 06:49:23 PM PDT 24
Finished Jul 20 06:49:26 PM PDT 24
Peak memory 207048 kb
Host smart-27c69ece-27bc-491d-a64f-04e6a9e851cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621110500 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3621110500
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.3616567478
Short name T856
Test name
Test status
Simulation time 12401519 ps
CPU time 0.94 seconds
Started Jul 20 06:49:22 PM PDT 24
Finished Jul 20 06:49:24 PM PDT 24
Peak memory 216644 kb
Host smart-8444c5d5-a20b-4f33-8c9b-520f26b92dc6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616567478 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.3616567478
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_err.2216590777
Short name T54
Test name
Test status
Simulation time 186204969 ps
CPU time 1.19 seconds
Started Jul 20 06:49:24 PM PDT 24
Finished Jul 20 06:49:26 PM PDT 24
Peak memory 229960 kb
Host smart-cdce5351-b1b8-4a2c-8410-49c9b59c0101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216590777 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2216590777
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.1286575532
Short name T619
Test name
Test status
Simulation time 147881722 ps
CPU time 1.56 seconds
Started Jul 20 06:49:23 PM PDT 24
Finished Jul 20 06:49:26 PM PDT 24
Peak memory 219140 kb
Host smart-7f408d3b-3b1c-41c6-a870-1fb37c2054c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286575532 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.1286575532
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.3360896331
Short name T643
Test name
Test status
Simulation time 39143140 ps
CPU time 0.92 seconds
Started Jul 20 06:49:22 PM PDT 24
Finished Jul 20 06:49:24 PM PDT 24
Peak memory 215656 kb
Host smart-5ba89369-a018-44bf-851b-8045c1f106eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360896331 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.3360896331
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.1651165131
Short name T92
Test name
Test status
Simulation time 50652604 ps
CPU time 0.94 seconds
Started Jul 20 06:49:23 PM PDT 24
Finished Jul 20 06:49:26 PM PDT 24
Peak memory 215576 kb
Host smart-b3fb9c34-f723-4e30-907b-2a6ac556544d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651165131 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.1651165131
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.2143902573
Short name T852
Test name
Test status
Simulation time 547776783 ps
CPU time 2.86 seconds
Started Jul 20 06:49:27 PM PDT 24
Finished Jul 20 06:49:31 PM PDT 24
Peak memory 217408 kb
Host smart-c4eabef1-5173-454f-8a09-767f55c4c8ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143902573 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.2143902573
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/130.edn_alert.1145865477
Short name T270
Test name
Test status
Simulation time 136229509 ps
CPU time 1.31 seconds
Started Jul 20 06:51:02 PM PDT 24
Finished Jul 20 06:51:05 PM PDT 24
Peak memory 220740 kb
Host smart-0c4da2bb-1188-4b3f-8815-a256b09179cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145865477 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.1145865477
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.1104728210
Short name T844
Test name
Test status
Simulation time 87953937 ps
CPU time 2.06 seconds
Started Jul 20 06:51:06 PM PDT 24
Finished Jul 20 06:51:08 PM PDT 24
Peak memory 220324 kb
Host smart-b57a1d3e-149b-4ec8-8632-a25a84f6f4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104728210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1104728210
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.3917152386
Short name T711
Test name
Test status
Simulation time 57194545 ps
CPU time 1.43 seconds
Started Jul 20 06:51:01 PM PDT 24
Finished Jul 20 06:51:03 PM PDT 24
Peak memory 218888 kb
Host smart-b80874fa-9789-46f2-9492-8982fd6ac852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917152386 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.3917152386
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.2156963101
Short name T45
Test name
Test status
Simulation time 33249930 ps
CPU time 1.38 seconds
Started Jul 20 06:51:07 PM PDT 24
Finished Jul 20 06:51:10 PM PDT 24
Peak memory 219068 kb
Host smart-f28763d1-2575-4030-a9e6-2b99a9f98157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156963101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2156963101
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.1771826710
Short name T728
Test name
Test status
Simulation time 78558595 ps
CPU time 1.17 seconds
Started Jul 20 06:51:06 PM PDT 24
Finished Jul 20 06:51:08 PM PDT 24
Peak memory 220408 kb
Host smart-9c2faab7-3759-4504-aed4-e85993a15147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771826710 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.1771826710
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.2754623808
Short name T800
Test name
Test status
Simulation time 78640874 ps
CPU time 1.63 seconds
Started Jul 20 06:51:09 PM PDT 24
Finished Jul 20 06:51:12 PM PDT 24
Peak memory 217692 kb
Host smart-351cfede-9b38-47bc-8fbc-d112454d1914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754623808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.2754623808
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.624890585
Short name T386
Test name
Test status
Simulation time 42542110 ps
CPU time 1.47 seconds
Started Jul 20 06:51:07 PM PDT 24
Finished Jul 20 06:51:09 PM PDT 24
Peak memory 218616 kb
Host smart-ffa85b0f-fb7e-4176-9ba0-91edbf6ca399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624890585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.624890585
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.1901419730
Short name T222
Test name
Test status
Simulation time 49157629 ps
CPU time 1.24 seconds
Started Jul 20 06:51:03 PM PDT 24
Finished Jul 20 06:51:06 PM PDT 24
Peak memory 220280 kb
Host smart-27e778bb-3a04-4b15-a329-645135dffa24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901419730 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.1901419730
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.1239347221
Short name T433
Test name
Test status
Simulation time 50762695 ps
CPU time 1 seconds
Started Jul 20 06:51:04 PM PDT 24
Finished Jul 20 06:51:07 PM PDT 24
Peak memory 217600 kb
Host smart-fd536e7d-d03c-4fef-bdf7-47d564666592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239347221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.1239347221
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.2621766575
Short name T753
Test name
Test status
Simulation time 38799335 ps
CPU time 1.05 seconds
Started Jul 20 06:51:04 PM PDT 24
Finished Jul 20 06:51:07 PM PDT 24
Peak memory 217632 kb
Host smart-e2917b78-5ea8-4022-85bc-f12a47c9d804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621766575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.2621766575
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.2917045150
Short name T86
Test name
Test status
Simulation time 46327850 ps
CPU time 1.26 seconds
Started Jul 20 06:51:10 PM PDT 24
Finished Jul 20 06:51:12 PM PDT 24
Peak memory 219792 kb
Host smart-1bf79825-de77-40cc-8cd1-98890f821829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917045150 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.2917045150
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.2629894937
Short name T71
Test name
Test status
Simulation time 86186239 ps
CPU time 1.63 seconds
Started Jul 20 06:51:05 PM PDT 24
Finished Jul 20 06:51:08 PM PDT 24
Peak memory 218980 kb
Host smart-0c0b5d30-d21c-43d8-8421-3caad02db7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629894937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.2629894937
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.3171637720
Short name T283
Test name
Test status
Simulation time 38109949 ps
CPU time 1.17 seconds
Started Jul 20 06:51:07 PM PDT 24
Finished Jul 20 06:51:10 PM PDT 24
Peak memory 220408 kb
Host smart-e846af4f-7de1-4683-a5a7-d4cd4f7e4aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171637720 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.3171637720
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.2930652863
Short name T485
Test name
Test status
Simulation time 109222226 ps
CPU time 1.64 seconds
Started Jul 20 06:51:04 PM PDT 24
Finished Jul 20 06:51:07 PM PDT 24
Peak memory 219092 kb
Host smart-dd1f168d-5b7a-4aca-97e6-8f14033e4854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930652863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.2930652863
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.3225078450
Short name T545
Test name
Test status
Simulation time 39165704 ps
CPU time 1.19 seconds
Started Jul 20 06:51:02 PM PDT 24
Finished Jul 20 06:51:04 PM PDT 24
Peak memory 219168 kb
Host smart-b9dddb0a-bcdc-420d-af41-598f8b037252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225078450 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.3225078450
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.3799645027
Short name T414
Test name
Test status
Simulation time 83148855 ps
CPU time 1.22 seconds
Started Jul 20 06:51:08 PM PDT 24
Finished Jul 20 06:51:11 PM PDT 24
Peak memory 218912 kb
Host smart-40562df8-6310-49dc-9492-2f62a2c08e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799645027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.3799645027
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.3964863986
Short name T171
Test name
Test status
Simulation time 23454541 ps
CPU time 1.17 seconds
Started Jul 20 06:51:03 PM PDT 24
Finished Jul 20 06:51:05 PM PDT 24
Peak memory 218764 kb
Host smart-529d254b-8ceb-401c-9855-b180b5a61d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964863986 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.3964863986
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.949492063
Short name T445
Test name
Test status
Simulation time 151244723 ps
CPU time 1.2 seconds
Started Jul 20 06:51:07 PM PDT 24
Finished Jul 20 06:51:09 PM PDT 24
Peak memory 217508 kb
Host smart-aad4f11a-f311-4ed1-80d4-9cf5ed0f28b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949492063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.949492063
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.38884150
Short name T390
Test name
Test status
Simulation time 76402124 ps
CPU time 1.2 seconds
Started Jul 20 06:49:31 PM PDT 24
Finished Jul 20 06:49:34 PM PDT 24
Peak memory 218788 kb
Host smart-31f4f1a3-2195-4c76-8fa8-77f95e216e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38884150 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.38884150
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.4052146610
Short name T914
Test name
Test status
Simulation time 22644467 ps
CPU time 0.87 seconds
Started Jul 20 06:49:37 PM PDT 24
Finished Jul 20 06:49:39 PM PDT 24
Peak memory 207092 kb
Host smart-df6e487b-cbde-4cb5-bfc6-a5b0a6d58902
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052146610 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.4052146610
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.158796652
Short name T900
Test name
Test status
Simulation time 13645768 ps
CPU time 0.95 seconds
Started Jul 20 06:49:31 PM PDT 24
Finished Jul 20 06:49:33 PM PDT 24
Peak memory 216452 kb
Host smart-2619592c-be3e-40f5-bc18-8e09adae5ebf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158796652 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.158796652
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.3183242729
Short name T926
Test name
Test status
Simulation time 36611832 ps
CPU time 1.35 seconds
Started Jul 20 06:49:32 PM PDT 24
Finished Jul 20 06:49:35 PM PDT 24
Peak memory 217040 kb
Host smart-2361ce98-95b9-4e44-9077-dbc765f8e7b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183242729 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.3183242729
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_genbits.36042
Short name T835
Test name
Test status
Simulation time 94317980 ps
CPU time 1.3 seconds
Started Jul 20 06:49:32 PM PDT 24
Finished Jul 20 06:49:35 PM PDT 24
Peak memory 220084 kb
Host smart-337491d7-adf9-44b2-8e17-ccf042a4b449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.36042
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.2149565651
Short name T725
Test name
Test status
Simulation time 27605632 ps
CPU time 1 seconds
Started Jul 20 06:49:32 PM PDT 24
Finished Jul 20 06:49:35 PM PDT 24
Peak memory 215728 kb
Host smart-d4dac9f0-893e-4bcf-a287-a82424af98c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149565651 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.2149565651
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.439059846
Short name T460
Test name
Test status
Simulation time 24497734 ps
CPU time 0.95 seconds
Started Jul 20 06:49:30 PM PDT 24
Finished Jul 20 06:49:32 PM PDT 24
Peak memory 215548 kb
Host smart-cb036686-d766-4d45-8afb-897dd242fcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439059846 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.439059846
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.3146915193
Short name T653
Test name
Test status
Simulation time 672691193 ps
CPU time 2.04 seconds
Started Jul 20 06:49:31 PM PDT 24
Finished Jul 20 06:49:35 PM PDT 24
Peak memory 215648 kb
Host smart-55edc747-2a70-46af-8f6e-cbba702ddbfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146915193 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3146915193
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/140.edn_alert.422533009
Short name T970
Test name
Test status
Simulation time 36201390 ps
CPU time 1.12 seconds
Started Jul 20 06:51:03 PM PDT 24
Finished Jul 20 06:51:05 PM PDT 24
Peak memory 221068 kb
Host smart-a766ca10-f801-40e4-8740-d9285a1283cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422533009 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.422533009
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.3207966921
Short name T598
Test name
Test status
Simulation time 50599575 ps
CPU time 1.57 seconds
Started Jul 20 06:51:01 PM PDT 24
Finished Jul 20 06:51:04 PM PDT 24
Peak memory 218972 kb
Host smart-d5863053-0ef0-4bc8-b7e3-9802e37f354f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207966921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.3207966921
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.3407327401
Short name T285
Test name
Test status
Simulation time 23642731 ps
CPU time 1.25 seconds
Started Jul 20 06:51:04 PM PDT 24
Finished Jul 20 06:51:07 PM PDT 24
Peak memory 221372 kb
Host smart-4db0b810-9a06-4581-9a12-7d784c5bf7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407327401 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.3407327401
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.2006923961
Short name T349
Test name
Test status
Simulation time 105940838 ps
CPU time 1.23 seconds
Started Jul 20 06:51:00 PM PDT 24
Finished Jul 20 06:51:02 PM PDT 24
Peak memory 218924 kb
Host smart-b8278c95-0f70-4770-aa51-9ad075842915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006923961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.2006923961
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.1282104783
Short name T965
Test name
Test status
Simulation time 74122319 ps
CPU time 1.17 seconds
Started Jul 20 06:51:05 PM PDT 24
Finished Jul 20 06:51:07 PM PDT 24
Peak memory 220240 kb
Host smart-f3f2e58f-6e43-44b5-a3f0-aec788401db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282104783 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.1282104783
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.4089122125
Short name T378
Test name
Test status
Simulation time 97328096 ps
CPU time 1.34 seconds
Started Jul 20 06:51:05 PM PDT 24
Finished Jul 20 06:51:07 PM PDT 24
Peak memory 218916 kb
Host smart-7c72b029-317e-4d8d-b1eb-1f674a338a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089122125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.4089122125
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.1258775624
Short name T418
Test name
Test status
Simulation time 42804115 ps
CPU time 1.22 seconds
Started Jul 20 06:51:04 PM PDT 24
Finished Jul 20 06:51:07 PM PDT 24
Peak memory 219008 kb
Host smart-5c3eca4f-31c9-4019-8537-af41c302d2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258775624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.1258775624
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.3621662629
Short name T432
Test name
Test status
Simulation time 49256327 ps
CPU time 1.55 seconds
Started Jul 20 06:51:13 PM PDT 24
Finished Jul 20 06:51:16 PM PDT 24
Peak memory 219532 kb
Host smart-c46dafa0-dd2f-4c57-a878-ee22b1a88b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621662629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.3621662629
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.3516468148
Short name T632
Test name
Test status
Simulation time 108352760 ps
CPU time 1.36 seconds
Started Jul 20 06:51:21 PM PDT 24
Finished Jul 20 06:51:26 PM PDT 24
Peak memory 220204 kb
Host smart-50cc283d-79d1-45dd-8d71-91816699813f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516468148 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.3516468148
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.4006388459
Short name T384
Test name
Test status
Simulation time 38836133 ps
CPU time 1.36 seconds
Started Jul 20 06:51:21 PM PDT 24
Finished Jul 20 06:51:26 PM PDT 24
Peak memory 218872 kb
Host smart-65d872e4-a8b4-4a2c-8d36-8bc828660993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006388459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.4006388459
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.305850979
Short name T413
Test name
Test status
Simulation time 22510360 ps
CPU time 1.21 seconds
Started Jul 20 06:51:11 PM PDT 24
Finished Jul 20 06:51:14 PM PDT 24
Peak memory 219084 kb
Host smart-9d3f2900-1816-4d13-8e86-bd8b0f586d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305850979 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.305850979
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/147.edn_alert.4284426404
Short name T689
Test name
Test status
Simulation time 72564520 ps
CPU time 1.16 seconds
Started Jul 20 06:51:21 PM PDT 24
Finished Jul 20 06:51:26 PM PDT 24
Peak memory 221884 kb
Host smart-a902aeb9-f4c1-44fc-9997-d85a9b149ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284426404 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.4284426404
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.2971149607
Short name T696
Test name
Test status
Simulation time 41635432 ps
CPU time 1.32 seconds
Started Jul 20 06:51:10 PM PDT 24
Finished Jul 20 06:51:12 PM PDT 24
Peak memory 218724 kb
Host smart-59800045-c67d-47e9-8bda-e83d10c8a008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971149607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.2971149607
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.3424455714
Short name T135
Test name
Test status
Simulation time 47991157 ps
CPU time 1.21 seconds
Started Jul 20 06:51:23 PM PDT 24
Finished Jul 20 06:51:29 PM PDT 24
Peak memory 218984 kb
Host smart-aa81aff1-ef05-40ad-a231-9659be8f5b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424455714 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.3424455714
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/149.edn_alert.2803044134
Short name T111
Test name
Test status
Simulation time 76374987 ps
CPU time 1.19 seconds
Started Jul 20 06:51:12 PM PDT 24
Finished Jul 20 06:51:15 PM PDT 24
Peak memory 219096 kb
Host smart-8440b1fd-7fef-446e-877a-15f6b9271699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803044134 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.2803044134
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.274366834
Short name T832
Test name
Test status
Simulation time 47475197 ps
CPU time 1.51 seconds
Started Jul 20 06:51:27 PM PDT 24
Finished Jul 20 06:51:35 PM PDT 24
Peak memory 218860 kb
Host smart-b6c251fe-bda2-4010-ad42-4fd55e146aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274366834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.274366834
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.3977987143
Short name T47
Test name
Test status
Simulation time 114652008 ps
CPU time 1.12 seconds
Started Jul 20 06:49:35 PM PDT 24
Finished Jul 20 06:49:38 PM PDT 24
Peak memory 218868 kb
Host smart-1feeabf7-ad5e-4608-a9fd-bc91a1ea0cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977987143 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3977987143
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.666310398
Short name T364
Test name
Test status
Simulation time 17666722 ps
CPU time 0.97 seconds
Started Jul 20 06:49:31 PM PDT 24
Finished Jul 20 06:49:33 PM PDT 24
Peak memory 207024 kb
Host smart-7130ffbd-74ee-4cb3-af90-ec0f2100a51a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666310398 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.666310398
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.1158777406
Short name T850
Test name
Test status
Simulation time 12854092 ps
CPU time 0.93 seconds
Started Jul 20 06:49:31 PM PDT 24
Finished Jul 20 06:49:34 PM PDT 24
Peak memory 216404 kb
Host smart-b3684722-409c-44b2-b144-8450c6a8f7d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158777406 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1158777406
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.2314506230
Short name T154
Test name
Test status
Simulation time 99149045 ps
CPU time 1.14 seconds
Started Jul 20 06:49:33 PM PDT 24
Finished Jul 20 06:49:36 PM PDT 24
Peak memory 217292 kb
Host smart-44024315-137a-4b95-af34-5ead1aacd308
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314506230 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.2314506230
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.329812248
Short name T209
Test name
Test status
Simulation time 54022869 ps
CPU time 1.09 seconds
Started Jul 20 06:49:33 PM PDT 24
Finished Jul 20 06:49:36 PM PDT 24
Peak memory 220908 kb
Host smart-92296c6a-a2b3-4822-b73b-e2e2a8de349a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329812248 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.329812248
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.3406810628
Short name T687
Test name
Test status
Simulation time 91806094 ps
CPU time 1.18 seconds
Started Jul 20 06:49:31 PM PDT 24
Finished Jul 20 06:49:34 PM PDT 24
Peak memory 219836 kb
Host smart-849cd913-99bc-468c-b3e5-74cd70d2ae0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406810628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.3406810628
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_smoke.2728026367
Short name T72
Test name
Test status
Simulation time 16746369 ps
CPU time 0.99 seconds
Started Jul 20 06:49:32 PM PDT 24
Finished Jul 20 06:49:35 PM PDT 24
Peak memory 215544 kb
Host smart-989670e9-a62e-433e-a528-e39186033873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728026367 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2728026367
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.2947845994
Short name T504
Test name
Test status
Simulation time 201942272 ps
CPU time 4.2 seconds
Started Jul 20 06:49:31 PM PDT 24
Finished Jul 20 06:49:37 PM PDT 24
Peak memory 217320 kb
Host smart-ba74d4b0-e7f7-485d-b734-c2f069e5f129
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947845994 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.2947845994
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.3866238023
Short name T812
Test name
Test status
Simulation time 57437173133 ps
CPU time 1025.77 seconds
Started Jul 20 06:49:32 PM PDT 24
Finished Jul 20 07:06:40 PM PDT 24
Peak memory 221888 kb
Host smart-08011f9b-c083-4e4f-9b46-c965aaf7fa8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866238023 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.3866238023
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.2481506022
Short name T590
Test name
Test status
Simulation time 27266715 ps
CPU time 1.29 seconds
Started Jul 20 06:51:15 PM PDT 24
Finished Jul 20 06:51:17 PM PDT 24
Peak memory 218992 kb
Host smart-b25b9b52-f834-4d37-84a3-48d90f4cde72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481506022 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.2481506022
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.4111410474
Short name T317
Test name
Test status
Simulation time 109698789 ps
CPU time 1.23 seconds
Started Jul 20 06:51:13 PM PDT 24
Finished Jul 20 06:51:16 PM PDT 24
Peak memory 220312 kb
Host smart-7244f687-56a0-494d-9b3a-a3fb84e0bd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111410474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.4111410474
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.621243985
Short name T910
Test name
Test status
Simulation time 106502867 ps
CPU time 1.25 seconds
Started Jul 20 06:51:22 PM PDT 24
Finished Jul 20 06:51:27 PM PDT 24
Peak memory 220872 kb
Host smart-7e200f76-62b7-4ed1-8509-95b612d65138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621243985 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.621243985
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.964375570
Short name T518
Test name
Test status
Simulation time 43978608 ps
CPU time 1.79 seconds
Started Jul 20 06:51:12 PM PDT 24
Finished Jul 20 06:51:15 PM PDT 24
Peak memory 218636 kb
Host smart-fcb0a552-3259-490c-9769-5fd874faa91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964375570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.964375570
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.3837445096
Short name T807
Test name
Test status
Simulation time 77424268 ps
CPU time 1.9 seconds
Started Jul 20 06:51:10 PM PDT 24
Finished Jul 20 06:51:12 PM PDT 24
Peak memory 219200 kb
Host smart-dfd92da0-f3df-46e0-a9ce-011dceb499f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837445096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.3837445096
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.2070295294
Short name T823
Test name
Test status
Simulation time 22546992 ps
CPU time 1.19 seconds
Started Jul 20 06:51:12 PM PDT 24
Finished Jul 20 06:51:14 PM PDT 24
Peak memory 220236 kb
Host smart-25e73bfa-49d5-4884-a0c9-52601bea6395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070295294 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.2070295294
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.16154446
Short name T815
Test name
Test status
Simulation time 36033515 ps
CPU time 1.14 seconds
Started Jul 20 06:51:13 PM PDT 24
Finished Jul 20 06:51:16 PM PDT 24
Peak memory 217764 kb
Host smart-842c751f-5cc3-4865-9481-34c26471969f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16154446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.16154446
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.3425084442
Short name T778
Test name
Test status
Simulation time 52702861 ps
CPU time 1.48 seconds
Started Jul 20 06:51:11 PM PDT 24
Finished Jul 20 06:51:14 PM PDT 24
Peak memory 218928 kb
Host smart-5ebf57d3-9d09-45c1-94da-36cb808b6cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425084442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.3425084442
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.3568264620
Short name T103
Test name
Test status
Simulation time 48866449 ps
CPU time 1.21 seconds
Started Jul 20 06:51:23 PM PDT 24
Finished Jul 20 06:51:29 PM PDT 24
Peak memory 218996 kb
Host smart-b625e2c3-91c2-4025-abec-d6ec7cbecae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568264620 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.3568264620
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.3212176442
Short name T353
Test name
Test status
Simulation time 55453092 ps
CPU time 1.22 seconds
Started Jul 20 06:51:19 PM PDT 24
Finished Jul 20 06:51:21 PM PDT 24
Peak memory 217656 kb
Host smart-b7a1f92e-384f-4c41-b154-982c2e83fd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212176442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3212176442
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.1179717372
Short name T536
Test name
Test status
Simulation time 76038924 ps
CPU time 1.21 seconds
Started Jul 20 06:51:13 PM PDT 24
Finished Jul 20 06:51:15 PM PDT 24
Peak memory 220592 kb
Host smart-51158e5d-7d8d-4e4f-8621-84cf701425ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179717372 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.1179717372
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.3812292710
Short name T867
Test name
Test status
Simulation time 29393384 ps
CPU time 1.26 seconds
Started Jul 20 06:51:24 PM PDT 24
Finished Jul 20 06:51:30 PM PDT 24
Peak memory 218792 kb
Host smart-04a2fd4c-773f-417f-9358-e1d515c537e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812292710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3812292710
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.2275775350
Short name T878
Test name
Test status
Simulation time 23053588 ps
CPU time 1.18 seconds
Started Jul 20 06:51:12 PM PDT 24
Finished Jul 20 06:51:14 PM PDT 24
Peak memory 218916 kb
Host smart-52eb82ab-1e1b-48b4-9163-2088699b4f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275775350 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.2275775350
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.3529043718
Short name T380
Test name
Test status
Simulation time 54008207 ps
CPU time 1.26 seconds
Started Jul 20 06:51:12 PM PDT 24
Finished Jul 20 06:51:15 PM PDT 24
Peak memory 220100 kb
Host smart-1f913c1a-1f62-4631-a23c-bac5dcf84a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529043718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.3529043718
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.2010692391
Short name T439
Test name
Test status
Simulation time 40760052 ps
CPU time 1.62 seconds
Started Jul 20 06:51:19 PM PDT 24
Finished Jul 20 06:51:22 PM PDT 24
Peak memory 217732 kb
Host smart-9b3eeff0-4330-404b-b150-781ce0c19ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010692391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2010692391
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.695638777
Short name T869
Test name
Test status
Simulation time 71613660 ps
CPU time 1.11 seconds
Started Jul 20 06:51:10 PM PDT 24
Finished Jul 20 06:51:12 PM PDT 24
Peak memory 219436 kb
Host smart-ccfe516b-ffca-481f-808d-e17878d69ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695638777 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.695638777
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.2204122829
Short name T908
Test name
Test status
Simulation time 58211215 ps
CPU time 1.07 seconds
Started Jul 20 06:51:11 PM PDT 24
Finished Jul 20 06:51:12 PM PDT 24
Peak memory 217544 kb
Host smart-b908690e-e5b4-4002-b92f-e1c81109c6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204122829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.2204122829
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.983618083
Short name T698
Test name
Test status
Simulation time 33411340 ps
CPU time 1.34 seconds
Started Jul 20 06:49:36 PM PDT 24
Finished Jul 20 06:49:38 PM PDT 24
Peak memory 220364 kb
Host smart-323b5812-f60c-45b3-ad2a-605d7a51aa32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983618083 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.983618083
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.348903964
Short name T948
Test name
Test status
Simulation time 19422228 ps
CPU time 1.09 seconds
Started Jul 20 06:49:34 PM PDT 24
Finished Jul 20 06:49:36 PM PDT 24
Peak memory 207104 kb
Host smart-b1e85bef-da6e-4afa-905b-2c2a8cbfb059
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348903964 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.348903964
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.3842998559
Short name T3
Test name
Test status
Simulation time 19321841 ps
CPU time 0.86 seconds
Started Jul 20 06:49:30 PM PDT 24
Finished Jul 20 06:49:32 PM PDT 24
Peak memory 216220 kb
Host smart-f003a376-e7cc-404f-adea-1aff08bf7325
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842998559 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.3842998559
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.3134868718
Short name T137
Test name
Test status
Simulation time 28925040 ps
CPU time 1.07 seconds
Started Jul 20 06:49:37 PM PDT 24
Finished Jul 20 06:49:39 PM PDT 24
Peak memory 217116 kb
Host smart-77ee0b63-6b48-412b-b27f-3394d3170629
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134868718 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.3134868718
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.1943192085
Short name T488
Test name
Test status
Simulation time 26184349 ps
CPU time 0.9 seconds
Started Jul 20 06:49:32 PM PDT 24
Finished Jul 20 06:49:34 PM PDT 24
Peak memory 218648 kb
Host smart-81002d3c-0c64-4f84-8f3a-f5f9d89b7608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943192085 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1943192085
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.790323700
Short name T883
Test name
Test status
Simulation time 114390385 ps
CPU time 1.45 seconds
Started Jul 20 06:49:36 PM PDT 24
Finished Jul 20 06:49:39 PM PDT 24
Peak memory 219560 kb
Host smart-e173e9c2-2b92-4cc2-ba5b-670077db3a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790323700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.790323700
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.270178116
Short name T781
Test name
Test status
Simulation time 23529431 ps
CPU time 1.1 seconds
Started Jul 20 06:49:32 PM PDT 24
Finished Jul 20 06:49:34 PM PDT 24
Peak memory 216152 kb
Host smart-d8fb1656-bd49-4449-8012-6bf82ed448f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270178116 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.270178116
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.1021531157
Short name T898
Test name
Test status
Simulation time 57657976 ps
CPU time 0.89 seconds
Started Jul 20 06:49:30 PM PDT 24
Finished Jul 20 06:49:32 PM PDT 24
Peak memory 215456 kb
Host smart-9f990297-c882-483d-bf2d-537242746569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021531157 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1021531157
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.234390437
Short name T487
Test name
Test status
Simulation time 151979335 ps
CPU time 1.44 seconds
Started Jul 20 06:49:37 PM PDT 24
Finished Jul 20 06:49:40 PM PDT 24
Peak memory 217476 kb
Host smart-eb8fac4d-8659-45c3-a20d-2448b052f86e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234390437 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.234390437
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/160.edn_alert.2630203667
Short name T683
Test name
Test status
Simulation time 84141746 ps
CPU time 1.15 seconds
Started Jul 20 06:51:26 PM PDT 24
Finished Jul 20 06:51:32 PM PDT 24
Peak memory 221740 kb
Host smart-9f9df6e2-a091-4536-80ca-e74e4100c397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630203667 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.2630203667
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.1285917773
Short name T944
Test name
Test status
Simulation time 77461703 ps
CPU time 1.39 seconds
Started Jul 20 06:51:20 PM PDT 24
Finished Jul 20 06:51:24 PM PDT 24
Peak memory 218888 kb
Host smart-0038ed20-e97f-42ee-ba25-9e153deb00a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285917773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1285917773
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.2998983102
Short name T268
Test name
Test status
Simulation time 108899255 ps
CPU time 1.16 seconds
Started Jul 20 06:51:12 PM PDT 24
Finished Jul 20 06:51:14 PM PDT 24
Peak memory 220932 kb
Host smart-ff33c180-fec8-442e-981f-2648b342f311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998983102 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.2998983102
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/162.edn_alert.2931964753
Short name T801
Test name
Test status
Simulation time 26728053 ps
CPU time 1.24 seconds
Started Jul 20 06:51:13 PM PDT 24
Finished Jul 20 06:51:15 PM PDT 24
Peak memory 220204 kb
Host smart-8ff786f8-afa4-40c9-8221-7c0fc1b1afd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931964753 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.2931964753
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.3903569038
Short name T511
Test name
Test status
Simulation time 86095898 ps
CPU time 2.97 seconds
Started Jul 20 06:51:24 PM PDT 24
Finished Jul 20 06:51:31 PM PDT 24
Peak memory 218860 kb
Host smart-7c77de47-f190-498f-b0a0-7d8bd0c1f4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903569038 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.3903569038
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.3739846597
Short name T105
Test name
Test status
Simulation time 81364948 ps
CPU time 1.12 seconds
Started Jul 20 06:51:24 PM PDT 24
Finished Jul 20 06:51:29 PM PDT 24
Peak memory 216012 kb
Host smart-6965c28f-cc68-4f73-b4e7-6a123396fb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739846597 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.3739846597
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.1159725566
Short name T81
Test name
Test status
Simulation time 80297772 ps
CPU time 1.46 seconds
Started Jul 20 06:51:27 PM PDT 24
Finished Jul 20 06:51:35 PM PDT 24
Peak memory 218792 kb
Host smart-c0132b2c-9909-4587-bece-c87abc8807ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159725566 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.1159725566
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.1770805110
Short name T614
Test name
Test status
Simulation time 77365503 ps
CPU time 1.24 seconds
Started Jul 20 06:51:13 PM PDT 24
Finished Jul 20 06:51:16 PM PDT 24
Peak memory 220248 kb
Host smart-6e0a5666-4868-4eb2-beaa-07a1866bdbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770805110 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.1770805110
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.2162202915
Short name T344
Test name
Test status
Simulation time 106579288 ps
CPU time 0.99 seconds
Started Jul 20 06:51:11 PM PDT 24
Finished Jul 20 06:51:13 PM PDT 24
Peak memory 217372 kb
Host smart-2ebf561e-a0d0-42eb-8e2b-59d2be5ef5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162202915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2162202915
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.1887208339
Short name T104
Test name
Test status
Simulation time 25522695 ps
CPU time 1.18 seconds
Started Jul 20 06:51:20 PM PDT 24
Finished Jul 20 06:51:23 PM PDT 24
Peak memory 218868 kb
Host smart-48507c56-a241-40df-87a2-ebe19bc1347a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887208339 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.1887208339
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.2958558589
Short name T982
Test name
Test status
Simulation time 30729137 ps
CPU time 1.04 seconds
Started Jul 20 06:51:25 PM PDT 24
Finished Jul 20 06:51:32 PM PDT 24
Peak memory 217520 kb
Host smart-3542b30b-5fb2-4b94-a9f8-87fbb91b9069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958558589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.2958558589
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.1764063123
Short name T474
Test name
Test status
Simulation time 23662149 ps
CPU time 1.2 seconds
Started Jul 20 06:51:22 PM PDT 24
Finished Jul 20 06:51:28 PM PDT 24
Peak memory 218980 kb
Host smart-26c1af6a-f33c-4562-8d04-1c5ec6d198ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764063123 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.1764063123
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.4171114121
Short name T620
Test name
Test status
Simulation time 42791182 ps
CPU time 1.31 seconds
Started Jul 20 06:51:28 PM PDT 24
Finished Jul 20 06:51:35 PM PDT 24
Peak memory 217612 kb
Host smart-879a86b7-4da0-4327-a981-f4700f4d3f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171114121 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.4171114121
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.2565445514
Short name T611
Test name
Test status
Simulation time 25295271 ps
CPU time 1.17 seconds
Started Jul 20 06:51:21 PM PDT 24
Finished Jul 20 06:51:25 PM PDT 24
Peak memory 219940 kb
Host smart-133feb93-2f1d-4640-a3c6-c6efb3d538b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565445514 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.2565445514
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.2671643068
Short name T785
Test name
Test status
Simulation time 95489024 ps
CPU time 1.22 seconds
Started Jul 20 06:51:23 PM PDT 24
Finished Jul 20 06:51:29 PM PDT 24
Peak memory 217576 kb
Host smart-7788a83d-49a5-49c1-86cc-68ac6a0c7056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671643068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.2671643068
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.2644498826
Short name T192
Test name
Test status
Simulation time 41914742 ps
CPU time 1.16 seconds
Started Jul 20 06:51:21 PM PDT 24
Finished Jul 20 06:51:25 PM PDT 24
Peak memory 220128 kb
Host smart-7bed7baf-b550-4be0-ab11-5b26de6fd0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644498826 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.2644498826
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.1216553608
Short name T500
Test name
Test status
Simulation time 70127669 ps
CPU time 1.23 seconds
Started Jul 20 06:51:22 PM PDT 24
Finished Jul 20 06:51:27 PM PDT 24
Peak memory 219228 kb
Host smart-e84dbf29-cf47-4222-88c7-585e05cd96e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216553608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1216553608
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.2891711357
Short name T766
Test name
Test status
Simulation time 79859883 ps
CPU time 1.12 seconds
Started Jul 20 06:51:21 PM PDT 24
Finished Jul 20 06:51:25 PM PDT 24
Peak memory 218904 kb
Host smart-bb713a3b-315e-48e8-bf64-8b9dd77466fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891711357 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.2891711357
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.82750891
Short name T467
Test name
Test status
Simulation time 67747617 ps
CPU time 1.09 seconds
Started Jul 20 06:51:20 PM PDT 24
Finished Jul 20 06:51:24 PM PDT 24
Peak memory 217456 kb
Host smart-40cfeda2-b410-4275-9207-4a36365f20db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82750891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.82750891
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.413544473
Short name T410
Test name
Test status
Simulation time 25532237 ps
CPU time 1.27 seconds
Started Jul 20 06:49:35 PM PDT 24
Finished Jul 20 06:49:38 PM PDT 24
Peak memory 220644 kb
Host smart-03159f0e-7873-452a-9f91-71266b77c587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413544473 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.413544473
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.1052990527
Short name T532
Test name
Test status
Simulation time 18492003 ps
CPU time 0.81 seconds
Started Jul 20 06:49:31 PM PDT 24
Finished Jul 20 06:49:33 PM PDT 24
Peak memory 207016 kb
Host smart-473419c3-5a3d-4835-8887-0a0b5fd90125
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052990527 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.1052990527
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.1632777288
Short name T697
Test name
Test status
Simulation time 21898119 ps
CPU time 0.9 seconds
Started Jul 20 06:49:30 PM PDT 24
Finished Jul 20 06:49:32 PM PDT 24
Peak memory 215704 kb
Host smart-5bb20045-08ff-478a-b2ee-5bcda921641e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632777288 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.1632777288
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.3175286606
Short name T985
Test name
Test status
Simulation time 114425937 ps
CPU time 1.12 seconds
Started Jul 20 06:49:31 PM PDT 24
Finished Jul 20 06:49:33 PM PDT 24
Peak memory 217304 kb
Host smart-206587df-a265-417a-88a3-7e5895b3737e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175286606 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.3175286606
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.1427241599
Short name T175
Test name
Test status
Simulation time 27382982 ps
CPU time 0.96 seconds
Started Jul 20 06:49:35 PM PDT 24
Finished Jul 20 06:49:37 PM PDT 24
Peak memory 224088 kb
Host smart-1b221ca7-59c0-4024-ae23-27f8c3bcc587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427241599 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.1427241599
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.1558794797
Short name T505
Test name
Test status
Simulation time 98225949 ps
CPU time 1.39 seconds
Started Jul 20 06:49:34 PM PDT 24
Finished Jul 20 06:49:37 PM PDT 24
Peak memory 219120 kb
Host smart-a74e6148-4115-4369-bdb8-fb55f29ea280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558794797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1558794797
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3513869887
Short name T980
Test name
Test status
Simulation time 21795970 ps
CPU time 0.94 seconds
Started Jul 20 06:49:35 PM PDT 24
Finished Jul 20 06:49:37 PM PDT 24
Peak memory 216096 kb
Host smart-8485245e-8d25-456c-aed0-4c1e656fdf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513869887 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3513869887
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.4045358435
Short name T404
Test name
Test status
Simulation time 61614212 ps
CPU time 0.99 seconds
Started Jul 20 06:49:32 PM PDT 24
Finished Jul 20 06:49:35 PM PDT 24
Peak memory 215532 kb
Host smart-f13b4af1-8d1b-4592-8714-b2be6df3acea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045358435 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.4045358435
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.2418817075
Short name T950
Test name
Test status
Simulation time 340572008 ps
CPU time 2.47 seconds
Started Jul 20 06:49:31 PM PDT 24
Finished Jul 20 06:49:35 PM PDT 24
Peak memory 215580 kb
Host smart-a974eac9-8111-4b77-94f0-b709ad4db6f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418817075 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.2418817075
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.1526851202
Short name T936
Test name
Test status
Simulation time 1182030538033 ps
CPU time 2579 seconds
Started Jul 20 06:49:30 PM PDT 24
Finished Jul 20 07:32:30 PM PDT 24
Peak memory 229536 kb
Host smart-e8acb699-722c-4a54-bcaa-e9fcec5b2b55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526851202 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.1526851202
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.1545464696
Short name T109
Test name
Test status
Simulation time 62649904 ps
CPU time 1.16 seconds
Started Jul 20 06:51:24 PM PDT 24
Finished Jul 20 06:51:30 PM PDT 24
Peak memory 220060 kb
Host smart-bba498b2-65db-4a92-8548-8ffc23334a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545464696 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.1545464696
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.4175993594
Short name T572
Test name
Test status
Simulation time 33909148 ps
CPU time 1.24 seconds
Started Jul 20 06:51:20 PM PDT 24
Finished Jul 20 06:51:22 PM PDT 24
Peak memory 220000 kb
Host smart-d8bed1d7-9226-4faa-96aa-b8d4c6c84c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175993594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.4175993594
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.1488835113
Short name T551
Test name
Test status
Simulation time 49484853 ps
CPU time 1.18 seconds
Started Jul 20 06:51:21 PM PDT 24
Finished Jul 20 06:51:26 PM PDT 24
Peak memory 218884 kb
Host smart-29f7b65f-26ad-46fd-9619-35bde3d5026a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488835113 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.1488835113
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.790258046
Short name T767
Test name
Test status
Simulation time 37331943 ps
CPU time 1.59 seconds
Started Jul 20 06:51:22 PM PDT 24
Finished Jul 20 06:51:28 PM PDT 24
Peak memory 218984 kb
Host smart-39116962-b8e8-42e4-9b42-a10b05625030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790258046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.790258046
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.2879992980
Short name T762
Test name
Test status
Simulation time 28326167 ps
CPU time 1.2 seconds
Started Jul 20 06:51:20 PM PDT 24
Finished Jul 20 06:51:24 PM PDT 24
Peak memory 219012 kb
Host smart-3526c931-9916-4d5c-9a66-fa018ba3d11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879992980 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.2879992980
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.3422633987
Short name T382
Test name
Test status
Simulation time 50259818 ps
CPU time 1.76 seconds
Started Jul 20 06:51:22 PM PDT 24
Finished Jul 20 06:51:28 PM PDT 24
Peak memory 218544 kb
Host smart-037d1978-4a91-4ce2-a79e-b6013d9e5c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422633987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.3422633987
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.3186374608
Short name T690
Test name
Test status
Simulation time 21571861 ps
CPU time 1.08 seconds
Started Jul 20 06:51:18 PM PDT 24
Finished Jul 20 06:51:20 PM PDT 24
Peak memory 220012 kb
Host smart-c5fbedde-10eb-4728-a9e2-38cc946584be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186374608 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.3186374608
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.1160616377
Short name T580
Test name
Test status
Simulation time 169981622 ps
CPU time 1.1 seconds
Started Jul 20 06:51:19 PM PDT 24
Finished Jul 20 06:51:21 PM PDT 24
Peak memory 217736 kb
Host smart-15a79252-03a6-436e-bdca-d022a97502d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160616377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.1160616377
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.64475714
Short name T296
Test name
Test status
Simulation time 53680458 ps
CPU time 0.96 seconds
Started Jul 20 06:51:20 PM PDT 24
Finished Jul 20 06:51:22 PM PDT 24
Peak memory 217580 kb
Host smart-bd94a824-a07f-4057-bc27-4626de461209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64475714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.64475714
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.1294857741
Short name T128
Test name
Test status
Simulation time 99071929 ps
CPU time 1.22 seconds
Started Jul 20 06:51:20 PM PDT 24
Finished Jul 20 06:51:24 PM PDT 24
Peak memory 220404 kb
Host smart-af0829ad-cf74-4a57-ba45-1424c2f13305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294857741 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.1294857741
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.994533520
Short name T858
Test name
Test status
Simulation time 89531205 ps
CPU time 1.34 seconds
Started Jul 20 06:51:20 PM PDT 24
Finished Jul 20 06:51:24 PM PDT 24
Peak memory 217588 kb
Host smart-6cd5a312-2760-4e16-b935-ed1cc23a55c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994533520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.994533520
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.1212477567
Short name T529
Test name
Test status
Simulation time 26850033 ps
CPU time 1.18 seconds
Started Jul 20 06:51:21 PM PDT 24
Finished Jul 20 06:51:25 PM PDT 24
Peak memory 218924 kb
Host smart-44cad1ec-ac5f-40ff-a6a1-372cc296194b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212477567 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.1212477567
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.192318523
Short name T423
Test name
Test status
Simulation time 149645392 ps
CPU time 1.12 seconds
Started Jul 20 06:51:23 PM PDT 24
Finished Jul 20 06:51:29 PM PDT 24
Peak memory 217568 kb
Host smart-68894174-02bd-4914-81f4-67ca1bea6d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192318523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.192318523
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.237795774
Short name T605
Test name
Test status
Simulation time 27719667 ps
CPU time 1.26 seconds
Started Jul 20 06:51:20 PM PDT 24
Finished Jul 20 06:51:23 PM PDT 24
Peak memory 219480 kb
Host smart-a725285f-d75a-4865-98c2-8745b702499e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237795774 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.237795774
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.3254086044
Short name T780
Test name
Test status
Simulation time 36285949 ps
CPU time 1.44 seconds
Started Jul 20 06:51:22 PM PDT 24
Finished Jul 20 06:51:27 PM PDT 24
Peak memory 218740 kb
Host smart-d6f5c34a-c195-40ba-a804-b1bd35eac573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254086044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.3254086044
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.200254416
Short name T979
Test name
Test status
Simulation time 47984503 ps
CPU time 1.16 seconds
Started Jul 20 06:51:23 PM PDT 24
Finished Jul 20 06:51:29 PM PDT 24
Peak memory 220944 kb
Host smart-3183186f-1c16-43fc-a475-957acfeca15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200254416 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.200254416
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.1439681073
Short name T721
Test name
Test status
Simulation time 36870406 ps
CPU time 1.43 seconds
Started Jul 20 06:51:23 PM PDT 24
Finished Jul 20 06:51:29 PM PDT 24
Peak memory 220056 kb
Host smart-c0406785-149a-46ad-a50b-9dbf340c4c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439681073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1439681073
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.4161260237
Short name T703
Test name
Test status
Simulation time 43496944 ps
CPU time 1.22 seconds
Started Jul 20 06:51:19 PM PDT 24
Finished Jul 20 06:51:22 PM PDT 24
Peak memory 219916 kb
Host smart-1c3eff29-452a-40f2-933c-841d0053361f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161260237 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.4161260237
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.255855231
Short name T12
Test name
Test status
Simulation time 194514509 ps
CPU time 1.21 seconds
Started Jul 20 06:51:29 PM PDT 24
Finished Jul 20 06:51:36 PM PDT 24
Peak memory 217672 kb
Host smart-17fa9667-f30d-467b-b0eb-69d5c61a5fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255855231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.255855231
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.273167602
Short name T90
Test name
Test status
Simulation time 22803081 ps
CPU time 1.18 seconds
Started Jul 20 06:49:36 PM PDT 24
Finished Jul 20 06:49:38 PM PDT 24
Peak memory 218980 kb
Host smart-25359b0b-fc98-45ba-abb4-34e0bcbaf288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273167602 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.273167602
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.3183522447
Short name T603
Test name
Test status
Simulation time 15334988 ps
CPU time 0.96 seconds
Started Jul 20 06:49:33 PM PDT 24
Finished Jul 20 06:49:36 PM PDT 24
Peak memory 207012 kb
Host smart-b2175a48-5cb7-4d8f-bf10-d49aee19cfe2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183522447 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.3183522447
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.3171361304
Short name T470
Test name
Test status
Simulation time 11607728 ps
CPU time 0.88 seconds
Started Jul 20 06:49:36 PM PDT 24
Finished Jul 20 06:49:38 PM PDT 24
Peak memory 215660 kb
Host smart-a2a30008-6e81-4bd6-bc62-a0159d317f22
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171361304 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.3171361304
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.1579905993
Short name T119
Test name
Test status
Simulation time 40027252 ps
CPU time 1.35 seconds
Started Jul 20 06:49:33 PM PDT 24
Finished Jul 20 06:49:36 PM PDT 24
Peak memory 217092 kb
Host smart-e4fd6da7-671c-470c-aa6a-6ad5416ef9bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579905993 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.1579905993
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_genbits.1245873324
Short name T437
Test name
Test status
Simulation time 38004053 ps
CPU time 1.37 seconds
Started Jul 20 06:49:33 PM PDT 24
Finished Jul 20 06:49:36 PM PDT 24
Peak memory 217576 kb
Host smart-83da1f6f-db6c-40fe-928f-8b984b652ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245873324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1245873324
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.1095775769
Short name T939
Test name
Test status
Simulation time 32290222 ps
CPU time 1.06 seconds
Started Jul 20 06:49:30 PM PDT 24
Finished Jul 20 06:49:32 PM PDT 24
Peak memory 224364 kb
Host smart-6cf6d4c8-50c6-419f-9791-6e762beee39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095775769 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1095775769
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.3026832513
Short name T387
Test name
Test status
Simulation time 16846129 ps
CPU time 0.95 seconds
Started Jul 20 06:49:31 PM PDT 24
Finished Jul 20 06:49:33 PM PDT 24
Peak memory 215532 kb
Host smart-9019ea89-679f-44f9-bc47-6cced204e5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026832513 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.3026832513
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.2323002403
Short name T463
Test name
Test status
Simulation time 340790178 ps
CPU time 3.09 seconds
Started Jul 20 06:49:32 PM PDT 24
Finished Jul 20 06:49:37 PM PDT 24
Peak memory 220252 kb
Host smart-da0c8e8a-77e9-43a2-b3f1-d65b281bc3a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323002403 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.2323002403
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2555290664
Short name T877
Test name
Test status
Simulation time 699890426868 ps
CPU time 1090.65 seconds
Started Jul 20 06:49:33 PM PDT 24
Finished Jul 20 07:07:45 PM PDT 24
Peak memory 221412 kb
Host smart-61eebb4c-f247-4aeb-aea3-f9e0d63be2d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555290664 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.2555290664
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.3510591278
Short name T628
Test name
Test status
Simulation time 220824495 ps
CPU time 1.33 seconds
Started Jul 20 06:51:19 PM PDT 24
Finished Jul 20 06:51:22 PM PDT 24
Peak memory 221152 kb
Host smart-39d766ab-3ca7-4a38-87a0-a8ff3d370585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510591278 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.3510591278
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.2258358295
Short name T971
Test name
Test status
Simulation time 74338623 ps
CPU time 2.78 seconds
Started Jul 20 06:51:23 PM PDT 24
Finished Jul 20 06:51:30 PM PDT 24
Peak memory 220296 kb
Host smart-aafee3dc-c9e6-458f-abbf-2a6562cc1116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258358295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.2258358295
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.451293761
Short name T976
Test name
Test status
Simulation time 80385042 ps
CPU time 1.13 seconds
Started Jul 20 06:51:22 PM PDT 24
Finished Jul 20 06:51:27 PM PDT 24
Peak memory 220680 kb
Host smart-edd0e5f8-1daf-44fc-8f37-c5bba1f0c170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451293761 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.451293761
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.184504488
Short name T790
Test name
Test status
Simulation time 48212456 ps
CPU time 1.35 seconds
Started Jul 20 06:51:23 PM PDT 24
Finished Jul 20 06:51:29 PM PDT 24
Peak memory 218856 kb
Host smart-c825eefe-74fe-42b4-8e4c-d78c25501321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184504488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.184504488
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.4284261453
Short name T906
Test name
Test status
Simulation time 40250880 ps
CPU time 1.12 seconds
Started Jul 20 06:51:20 PM PDT 24
Finished Jul 20 06:51:23 PM PDT 24
Peak memory 219976 kb
Host smart-05a3fe95-1ef9-40f3-8c65-71d853a6ae22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284261453 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.4284261453
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.162481170
Short name T312
Test name
Test status
Simulation time 56782643 ps
CPU time 1.69 seconds
Started Jul 20 06:51:22 PM PDT 24
Finished Jul 20 06:51:28 PM PDT 24
Peak memory 218740 kb
Host smart-98aff926-f4ca-4608-a36f-cede35e7289c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162481170 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.162481170
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.668261424
Short name T875
Test name
Test status
Simulation time 28170276 ps
CPU time 1.24 seconds
Started Jul 20 06:51:20 PM PDT 24
Finished Jul 20 06:51:24 PM PDT 24
Peak memory 218912 kb
Host smart-9a20b9a6-a2bc-401f-b357-8ff3cf8a38a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668261424 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.668261424
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.3752059143
Short name T535
Test name
Test status
Simulation time 92513081 ps
CPU time 1.09 seconds
Started Jul 20 06:51:26 PM PDT 24
Finished Jul 20 06:51:32 PM PDT 24
Peak memory 217176 kb
Host smart-d257367c-9d5a-4825-b847-c81fb546608e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752059143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.3752059143
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.2251438245
Short name T776
Test name
Test status
Simulation time 72613054 ps
CPU time 1.2 seconds
Started Jul 20 06:51:22 PM PDT 24
Finished Jul 20 06:51:28 PM PDT 24
Peak memory 219708 kb
Host smart-83ab8795-3c6b-466c-aa7d-68f0ebe42171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251438245 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.2251438245
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.842440191
Short name T77
Test name
Test status
Simulation time 130570438 ps
CPU time 1.29 seconds
Started Jul 20 06:51:24 PM PDT 24
Finished Jul 20 06:51:31 PM PDT 24
Peak memory 217536 kb
Host smart-a88f2bb7-8d3f-48e8-a53f-11092424603b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842440191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.842440191
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.2216184450
Short name T108
Test name
Test status
Simulation time 106862692 ps
CPU time 1.31 seconds
Started Jul 20 06:51:23 PM PDT 24
Finished Jul 20 06:51:29 PM PDT 24
Peak memory 220620 kb
Host smart-df83c8e4-8c9b-4bbf-932a-c18a7213f274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216184450 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.2216184450
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.503491329
Short name T920
Test name
Test status
Simulation time 50374531 ps
CPU time 1.3 seconds
Started Jul 20 06:51:22 PM PDT 24
Finished Jul 20 06:51:28 PM PDT 24
Peak memory 218576 kb
Host smart-a3a4aa64-e942-498f-8318-50d14bfc3df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503491329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.503491329
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.2528080772
Short name T73
Test name
Test status
Simulation time 113175188 ps
CPU time 1.21 seconds
Started Jul 20 06:51:25 PM PDT 24
Finished Jul 20 06:51:32 PM PDT 24
Peak memory 221128 kb
Host smart-59cc0737-15f9-4a24-a1a8-5bf355c8e4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528080772 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.2528080772
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.1443459511
Short name T297
Test name
Test status
Simulation time 48834528 ps
CPU time 1.16 seconds
Started Jul 20 06:51:20 PM PDT 24
Finished Jul 20 06:51:23 PM PDT 24
Peak memory 220288 kb
Host smart-9c51d2d2-a24f-4d35-bbba-e1d03958ef44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443459511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.1443459511
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.3671320739
Short name T95
Test name
Test status
Simulation time 50595173 ps
CPU time 2.24 seconds
Started Jul 20 06:51:22 PM PDT 24
Finished Jul 20 06:51:28 PM PDT 24
Peak memory 217876 kb
Host smart-0e313fa5-851c-479c-b9b7-2d9525a6f060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671320739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.3671320739
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.3981229302
Short name T528
Test name
Test status
Simulation time 85987056 ps
CPU time 1.31 seconds
Started Jul 20 06:51:25 PM PDT 24
Finished Jul 20 06:51:32 PM PDT 24
Peak memory 218740 kb
Host smart-5af7918e-8033-4837-9638-906547665a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981229302 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.3981229302
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.1175832983
Short name T501
Test name
Test status
Simulation time 44375112 ps
CPU time 1.86 seconds
Started Jul 20 06:51:24 PM PDT 24
Finished Jul 20 06:51:32 PM PDT 24
Peak memory 218724 kb
Host smart-767a399b-e8c1-4446-8299-1f1fbf3c980b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175832983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1175832983
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.2414798554
Short name T496
Test name
Test status
Simulation time 305248540 ps
CPU time 1.08 seconds
Started Jul 20 06:51:27 PM PDT 24
Finished Jul 20 06:51:34 PM PDT 24
Peak memory 219916 kb
Host smart-568d6d05-101e-4069-9138-967dc3942fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414798554 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.2414798554
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.969801696
Short name T677
Test name
Test status
Simulation time 63757374 ps
CPU time 2.15 seconds
Started Jul 20 06:51:33 PM PDT 24
Finished Jul 20 06:51:39 PM PDT 24
Peak memory 220376 kb
Host smart-f7d81251-2363-47b9-a2cc-8976db5cb760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969801696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.969801696
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.3231771820
Short name T224
Test name
Test status
Simulation time 66175508 ps
CPU time 1.29 seconds
Started Jul 20 06:49:35 PM PDT 24
Finished Jul 20 06:49:38 PM PDT 24
Peak memory 221576 kb
Host smart-c88567b3-5b39-483b-86b7-2b4c604b2bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231771820 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.3231771820
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.2249275885
Short name T865
Test name
Test status
Simulation time 16523334 ps
CPU time 0.94 seconds
Started Jul 20 06:49:32 PM PDT 24
Finished Jul 20 06:49:35 PM PDT 24
Peak memory 207032 kb
Host smart-43b93c52-d7ba-4118-a02e-ab0273486dd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249275885 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2249275885
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.1946070407
Short name T553
Test name
Test status
Simulation time 11406123 ps
CPU time 0.91 seconds
Started Jul 20 06:49:34 PM PDT 24
Finished Jul 20 06:49:36 PM PDT 24
Peak memory 216628 kb
Host smart-5e67ee33-a3fd-4601-a5d2-3ff3f1d5929a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946070407 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.1946070407
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.589005083
Short name T904
Test name
Test status
Simulation time 48467534 ps
CPU time 1.25 seconds
Started Jul 20 06:49:37 PM PDT 24
Finished Jul 20 06:49:39 PM PDT 24
Peak memory 216748 kb
Host smart-8c372906-5bde-4516-9d98-096fecb4a5d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589005083 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_di
sable_auto_req_mode.589005083
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.2116244196
Short name T141
Test name
Test status
Simulation time 36876240 ps
CPU time 1.51 seconds
Started Jul 20 06:49:37 PM PDT 24
Finished Jul 20 06:49:39 PM PDT 24
Peak memory 225996 kb
Host smart-285626d0-8791-4aae-9634-3ebebbfd1c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116244196 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.2116244196
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.78054338
Short name T370
Test name
Test status
Simulation time 57592932 ps
CPU time 2.1 seconds
Started Jul 20 06:49:35 PM PDT 24
Finished Jul 20 06:49:38 PM PDT 24
Peak memory 218924 kb
Host smart-1f339f60-6d3e-4499-a9a4-65d932047229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78054338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.78054338
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.2163899363
Short name T846
Test name
Test status
Simulation time 21878886 ps
CPU time 1.23 seconds
Started Jul 20 06:49:30 PM PDT 24
Finished Jul 20 06:49:32 PM PDT 24
Peak memory 224320 kb
Host smart-d4fb53d3-0305-4b32-bfed-886797716052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163899363 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.2163899363
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.3378695349
Short name T492
Test name
Test status
Simulation time 20972872 ps
CPU time 0.9 seconds
Started Jul 20 06:49:33 PM PDT 24
Finished Jul 20 06:49:36 PM PDT 24
Peak memory 215596 kb
Host smart-d070329d-4ac7-48d9-baff-e9939a9dbc7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378695349 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.3378695349
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.2505460277
Short name T352
Test name
Test status
Simulation time 244759157 ps
CPU time 5.53 seconds
Started Jul 20 06:49:33 PM PDT 24
Finished Jul 20 06:49:40 PM PDT 24
Peak memory 217472 kb
Host smart-1e6807ce-5c9b-4b6e-ad4a-9a5f9b103718
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505460277 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.2505460277
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.754142896
Short name T695
Test name
Test status
Simulation time 111820349772 ps
CPU time 2660.01 seconds
Started Jul 20 06:49:35 PM PDT 24
Finished Jul 20 07:33:57 PM PDT 24
Peak memory 234600 kb
Host smart-35b7653b-e9be-405a-a59b-54a021bd1550
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754142896 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.754142896
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.2487688202
Short name T680
Test name
Test status
Simulation time 66559568 ps
CPU time 1.2 seconds
Started Jul 20 06:51:25 PM PDT 24
Finished Jul 20 06:51:32 PM PDT 24
Peak memory 218732 kb
Host smart-9840613c-92df-4ecc-ae78-287c9774f1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487688202 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.2487688202
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.530625324
Short name T772
Test name
Test status
Simulation time 81816366 ps
CPU time 1.7 seconds
Started Jul 20 06:51:27 PM PDT 24
Finished Jul 20 06:51:35 PM PDT 24
Peak memory 220404 kb
Host smart-f40f3cc9-e3a3-4b0c-bbdc-3630d33439e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530625324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.530625324
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.765524166
Short name T625
Test name
Test status
Simulation time 45909270 ps
CPU time 1.16 seconds
Started Jul 20 06:51:26 PM PDT 24
Finished Jul 20 06:51:32 PM PDT 24
Peak memory 218828 kb
Host smart-23226f0e-8e6f-4575-9366-ce2a7b69ff74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765524166 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.765524166
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.2863980645
Short name T94
Test name
Test status
Simulation time 67069963 ps
CPU time 1.71 seconds
Started Jul 20 06:51:24 PM PDT 24
Finished Jul 20 06:51:30 PM PDT 24
Peak memory 218992 kb
Host smart-c9f6627f-5204-42bb-9db0-dd3571853110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863980645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2863980645
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.3878530337
Short name T506
Test name
Test status
Simulation time 72970936 ps
CPU time 1.21 seconds
Started Jul 20 06:51:28 PM PDT 24
Finished Jul 20 06:51:35 PM PDT 24
Peak memory 219740 kb
Host smart-5694cb16-5416-4211-ba11-0ba8b53d5537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878530337 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.3878530337
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.859377882
Short name T840
Test name
Test status
Simulation time 180026882 ps
CPU time 1.57 seconds
Started Jul 20 06:51:32 PM PDT 24
Finished Jul 20 06:51:38 PM PDT 24
Peak memory 219116 kb
Host smart-0fcda4e4-79d2-4756-b799-6694d5f020be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859377882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.859377882
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.442816397
Short name T243
Test name
Test status
Simulation time 43005848 ps
CPU time 1.26 seconds
Started Jul 20 06:51:24 PM PDT 24
Finished Jul 20 06:51:31 PM PDT 24
Peak memory 216008 kb
Host smart-9b3db414-b743-4e86-9162-03fe1840960e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442816397 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.442816397
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.703820885
Short name T287
Test name
Test status
Simulation time 53043321 ps
CPU time 1.45 seconds
Started Jul 20 06:51:28 PM PDT 24
Finished Jul 20 06:51:35 PM PDT 24
Peak memory 219088 kb
Host smart-f68d9b7c-c28a-408e-b07b-0b5d42e58530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703820885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.703820885
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.3495975336
Short name T275
Test name
Test status
Simulation time 85176180 ps
CPU time 1.25 seconds
Started Jul 20 06:51:25 PM PDT 24
Finished Jul 20 06:51:32 PM PDT 24
Peak memory 220200 kb
Host smart-81a06bf2-f5e2-4c61-89bb-f86802105edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495975336 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.3495975336
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.1444758864
Short name T974
Test name
Test status
Simulation time 49307750 ps
CPU time 1.28 seconds
Started Jul 20 06:51:28 PM PDT 24
Finished Jul 20 06:51:35 PM PDT 24
Peak memory 217596 kb
Host smart-a830c072-309f-4d2c-9c1c-b61a23232932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444758864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.1444758864
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.2553533416
Short name T586
Test name
Test status
Simulation time 84163422 ps
CPU time 1.05 seconds
Started Jul 20 06:51:33 PM PDT 24
Finished Jul 20 06:51:39 PM PDT 24
Peak memory 219844 kb
Host smart-14c0a9ed-11c0-4439-a299-bfd032517ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553533416 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.2553533416
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.976415269
Short name T466
Test name
Test status
Simulation time 52158479 ps
CPU time 1.92 seconds
Started Jul 20 06:51:25 PM PDT 24
Finished Jul 20 06:51:32 PM PDT 24
Peak memory 218768 kb
Host smart-fd6c8796-2423-43dd-9078-1e1f4bcd7dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976415269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.976415269
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.2123186352
Short name T630
Test name
Test status
Simulation time 141118961 ps
CPU time 1.27 seconds
Started Jul 20 06:51:30 PM PDT 24
Finished Jul 20 06:51:36 PM PDT 24
Peak memory 219044 kb
Host smart-434feaec-b168-41fd-b74d-70824de2febc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123186352 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.2123186352
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.3443970695
Short name T770
Test name
Test status
Simulation time 46213495 ps
CPU time 1.69 seconds
Started Jul 20 06:51:27 PM PDT 24
Finished Jul 20 06:51:35 PM PDT 24
Peak memory 219140 kb
Host smart-d1442468-ae47-4033-be20-1b9d7bf805c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443970695 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3443970695
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.3152094035
Short name T129
Test name
Test status
Simulation time 345740451 ps
CPU time 1.36 seconds
Started Jul 20 06:51:24 PM PDT 24
Finished Jul 20 06:51:31 PM PDT 24
Peak memory 218864 kb
Host smart-cda8fece-903e-4565-bfaa-44247d1cbc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152094035 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.3152094035
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.2782218985
Short name T407
Test name
Test status
Simulation time 58477605 ps
CPU time 2.19 seconds
Started Jul 20 06:51:25 PM PDT 24
Finished Jul 20 06:51:32 PM PDT 24
Peak memory 217704 kb
Host smart-aae2bc24-9a05-4db8-b0c7-2feddd5243c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782218985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.2782218985
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.509193158
Short name T657
Test name
Test status
Simulation time 44723973 ps
CPU time 1.27 seconds
Started Jul 20 06:51:26 PM PDT 24
Finished Jul 20 06:51:33 PM PDT 24
Peak memory 220576 kb
Host smart-e8c69756-5326-460d-a814-91b5e47c0af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509193158 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.509193158
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.565746966
Short name T299
Test name
Test status
Simulation time 137327660 ps
CPU time 1.08 seconds
Started Jul 20 06:51:33 PM PDT 24
Finished Jul 20 06:51:39 PM PDT 24
Peak memory 217516 kb
Host smart-41c8c79d-0af8-4b86-a897-34413009f0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565746966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.565746966
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.2651430554
Short name T184
Test name
Test status
Simulation time 46328241 ps
CPU time 1.12 seconds
Started Jul 20 06:51:28 PM PDT 24
Finished Jul 20 06:51:35 PM PDT 24
Peak memory 218900 kb
Host smart-154e3c1b-69ad-4070-bdca-3803fc8f9790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651430554 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.2651430554
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.1736280374
Short name T310
Test name
Test status
Simulation time 235727109 ps
CPU time 3.21 seconds
Started Jul 20 06:51:30 PM PDT 24
Finished Jul 20 06:51:38 PM PDT 24
Peak memory 218008 kb
Host smart-9d63df03-cd9f-480a-9cf3-8d720641009e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736280374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.1736280374
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.1675213903
Short name T106
Test name
Test status
Simulation time 54681623 ps
CPU time 1.21 seconds
Started Jul 20 06:49:03 PM PDT 24
Finished Jul 20 06:49:06 PM PDT 24
Peak memory 220256 kb
Host smart-6641f5d6-55d7-4038-982b-966490ab02b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675213903 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.1675213903
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.2470551307
Short name T860
Test name
Test status
Simulation time 33607882 ps
CPU time 0.8 seconds
Started Jul 20 06:49:04 PM PDT 24
Finished Jul 20 06:49:06 PM PDT 24
Peak memory 206380 kb
Host smart-f4bf9f0c-c603-45a7-a2d0-dd22bd1bb071
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470551307 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.2470551307
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.3903945167
Short name T791
Test name
Test status
Simulation time 33332816 ps
CPU time 0.87 seconds
Started Jul 20 06:48:56 PM PDT 24
Finished Jul 20 06:48:58 PM PDT 24
Peak memory 215704 kb
Host smart-1e55e017-707c-4956-b557-4b9ab7d885e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903945167 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.3903945167
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.1912734880
Short name T127
Test name
Test status
Simulation time 42649209 ps
CPU time 1.62 seconds
Started Jul 20 06:49:04 PM PDT 24
Finished Jul 20 06:49:08 PM PDT 24
Peak memory 217096 kb
Host smart-83216a5d-194b-4b3c-868c-950345db195c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912734880 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.1912734880
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.934000540
Short name T174
Test name
Test status
Simulation time 19194232 ps
CPU time 1.19 seconds
Started Jul 20 06:48:58 PM PDT 24
Finished Jul 20 06:49:01 PM PDT 24
Peak memory 224272 kb
Host smart-36db26d7-76a7-45ed-a10a-7a4570c20fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934000540 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.934000540
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.677232906
Short name T975
Test name
Test status
Simulation time 75010480 ps
CPU time 1.45 seconds
Started Jul 20 06:49:03 PM PDT 24
Finished Jul 20 06:49:06 PM PDT 24
Peak memory 218628 kb
Host smart-35a6064c-6ae6-43e8-8d69-dee32e55be61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677232906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.677232906
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_smoke.1328040088
Short name T238
Test name
Test status
Simulation time 18012482 ps
CPU time 1.03 seconds
Started Jul 20 06:49:02 PM PDT 24
Finished Jul 20 06:49:04 PM PDT 24
Peak memory 215556 kb
Host smart-c0b01d9b-820a-4c0f-8fc6-c0ce5b40d482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328040088 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.1328040088
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.640865503
Short name T933
Test name
Test status
Simulation time 53162588 ps
CPU time 1.63 seconds
Started Jul 20 06:49:03 PM PDT 24
Finished Jul 20 06:49:07 PM PDT 24
Peak memory 217440 kb
Host smart-5f6019bc-67fe-4354-a618-d7e1c24d49b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640865503 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.640865503
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.2941816448
Short name T475
Test name
Test status
Simulation time 48956203622 ps
CPU time 1045.2 seconds
Started Jul 20 06:48:57 PM PDT 24
Finished Jul 20 07:06:24 PM PDT 24
Peak memory 219396 kb
Host smart-11841f93-4ba8-4921-a7c4-f9b610b63ca7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941816448 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.2941816448
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.3207877614
Short name T509
Test name
Test status
Simulation time 101789461 ps
CPU time 1.23 seconds
Started Jul 20 06:49:41 PM PDT 24
Finished Jul 20 06:49:43 PM PDT 24
Peak memory 219964 kb
Host smart-1eeef73b-00cd-4fd5-afa8-59a4aefd6c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207877614 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.3207877614
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.1029071032
Short name T735
Test name
Test status
Simulation time 15806011 ps
CPU time 0.94 seconds
Started Jul 20 06:49:40 PM PDT 24
Finished Jul 20 06:49:42 PM PDT 24
Peak memory 215488 kb
Host smart-28593bd7-fde0-4e9e-8d03-9d40e59f6c79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029071032 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.1029071032
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.2239876943
Short name T213
Test name
Test status
Simulation time 12351020 ps
CPU time 0.95 seconds
Started Jul 20 06:49:43 PM PDT 24
Finished Jul 20 06:49:46 PM PDT 24
Peak memory 216696 kb
Host smart-2dd65577-00a1-48bc-a002-00f248dee78e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239876943 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.2239876943
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.2818801499
Short name T988
Test name
Test status
Simulation time 62445890 ps
CPU time 1 seconds
Started Jul 20 06:49:41 PM PDT 24
Finished Jul 20 06:49:43 PM PDT 24
Peak memory 218600 kb
Host smart-aae1a996-d2cd-4ff2-a6e8-a9c020224a2c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818801499 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.2818801499
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_genbits.2387693995
Short name T870
Test name
Test status
Simulation time 53533217 ps
CPU time 1.75 seconds
Started Jul 20 06:49:30 PM PDT 24
Finished Jul 20 06:49:32 PM PDT 24
Peak memory 220152 kb
Host smart-5cc98529-e7a6-45e8-a123-15fee576b68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387693995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.2387693995
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.812407518
Short name T874
Test name
Test status
Simulation time 107630954 ps
CPU time 0.87 seconds
Started Jul 20 06:49:41 PM PDT 24
Finished Jul 20 06:49:43 PM PDT 24
Peak memory 215668 kb
Host smart-c7f668c8-1738-49b5-ada8-7c2fc6033694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812407518 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.812407518
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.4272894654
Short name T581
Test name
Test status
Simulation time 32882118 ps
CPU time 0.91 seconds
Started Jul 20 06:49:35 PM PDT 24
Finished Jul 20 06:49:37 PM PDT 24
Peak memory 215548 kb
Host smart-e3d67fed-1ce6-4746-a691-6e687d451c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272894654 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.4272894654
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.1415246888
Short name T810
Test name
Test status
Simulation time 565390943 ps
CPU time 5.98 seconds
Started Jul 20 06:49:42 PM PDT 24
Finished Jul 20 06:49:50 PM PDT 24
Peak memory 217404 kb
Host smart-3ce1289e-7666-4671-b60a-0e5c8b75cd39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415246888 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1415246888
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.3893497290
Short name T59
Test name
Test status
Simulation time 92521559389 ps
CPU time 2051.28 seconds
Started Jul 20 06:49:40 PM PDT 24
Finished Jul 20 07:23:52 PM PDT 24
Peak memory 226916 kb
Host smart-c0a3bb53-610c-4707-9116-85b66018d99f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893497290 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.3893497290
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.73703589
Short name T363
Test name
Test status
Simulation time 35364472 ps
CPU time 1.34 seconds
Started Jul 20 06:51:28 PM PDT 24
Finished Jul 20 06:51:35 PM PDT 24
Peak memory 217592 kb
Host smart-570d2ba9-89b0-484e-b2f4-1befbec3f9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73703589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.73703589
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.3316338858
Short name T367
Test name
Test status
Simulation time 47597987 ps
CPU time 1.4 seconds
Started Jul 20 06:51:27 PM PDT 24
Finished Jul 20 06:51:34 PM PDT 24
Peak memory 219252 kb
Host smart-3312b43a-3d3f-41fd-83e2-7aaae6089535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316338858 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.3316338858
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.454443932
Short name T681
Test name
Test status
Simulation time 55597914 ps
CPU time 1.56 seconds
Started Jul 20 06:51:31 PM PDT 24
Finished Jul 20 06:51:38 PM PDT 24
Peak memory 219172 kb
Host smart-517bb52e-6449-484b-b193-f1be73f26508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454443932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.454443932
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.3257390245
Short name T479
Test name
Test status
Simulation time 67491347 ps
CPU time 1.17 seconds
Started Jul 20 06:51:29 PM PDT 24
Finished Jul 20 06:51:36 PM PDT 24
Peak memory 217676 kb
Host smart-b2a3f51d-480d-4e41-9ff8-a3ad125785fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257390245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.3257390245
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.3434632943
Short name T671
Test name
Test status
Simulation time 61593280 ps
CPU time 1.4 seconds
Started Jul 20 06:51:32 PM PDT 24
Finished Jul 20 06:51:38 PM PDT 24
Peak memory 217556 kb
Host smart-32ebef47-6bca-4a80-9305-0cd1e739d007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434632943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3434632943
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.945800513
Short name T637
Test name
Test status
Simulation time 30719846 ps
CPU time 1.29 seconds
Started Jul 20 06:51:33 PM PDT 24
Finished Jul 20 06:51:39 PM PDT 24
Peak memory 215556 kb
Host smart-4b7edcaa-df42-4188-abdf-6a268bb1a3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945800513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.945800513
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2747972559
Short name T36
Test name
Test status
Simulation time 33006103 ps
CPU time 1.51 seconds
Started Jul 20 06:51:25 PM PDT 24
Finished Jul 20 06:51:32 PM PDT 24
Peak memory 218912 kb
Host smart-6310a27e-ec97-4992-9b62-b71200175c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747972559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2747972559
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.1709869305
Short name T658
Test name
Test status
Simulation time 81769068 ps
CPU time 1.11 seconds
Started Jul 20 06:51:27 PM PDT 24
Finished Jul 20 06:51:35 PM PDT 24
Peak memory 217620 kb
Host smart-8bf09703-0a6c-439a-bf68-d2ca3383dfe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709869305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.1709869305
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.2893703896
Short name T6
Test name
Test status
Simulation time 37055377 ps
CPU time 1.52 seconds
Started Jul 20 06:51:28 PM PDT 24
Finished Jul 20 06:51:35 PM PDT 24
Peak memory 218696 kb
Host smart-b744d14c-5377-44ce-a82f-c3503bf7adfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893703896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.2893703896
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.3057534984
Short name T585
Test name
Test status
Simulation time 50125691 ps
CPU time 1.15 seconds
Started Jul 20 06:51:26 PM PDT 24
Finished Jul 20 06:51:32 PM PDT 24
Peak memory 217532 kb
Host smart-dda4a824-7893-412f-ac2f-96e1c434fef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057534984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.3057534984
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.948632723
Short name T819
Test name
Test status
Simulation time 21415502 ps
CPU time 1.15 seconds
Started Jul 20 06:49:45 PM PDT 24
Finished Jul 20 06:49:48 PM PDT 24
Peak memory 218820 kb
Host smart-7bad0adb-30a3-4dcc-be73-840000c5877e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948632723 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.948632723
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.3131424164
Short name T339
Test name
Test status
Simulation time 48974501 ps
CPU time 0.88 seconds
Started Jul 20 06:49:43 PM PDT 24
Finished Jul 20 06:49:46 PM PDT 24
Peak memory 207004 kb
Host smart-d1092dc3-bc78-4fe0-9f60-c8396ea26931
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131424164 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.3131424164
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.3632560761
Short name T165
Test name
Test status
Simulation time 13081125 ps
CPU time 0.94 seconds
Started Jul 20 06:49:41 PM PDT 24
Finished Jul 20 06:49:43 PM PDT 24
Peak memory 216700 kb
Host smart-11a14ddc-1f3b-4e5b-8cf2-6641b0adacd4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632560761 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.3632560761
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.2475537999
Short name T579
Test name
Test status
Simulation time 24787597 ps
CPU time 1.07 seconds
Started Jul 20 06:49:42 PM PDT 24
Finished Jul 20 06:49:45 PM PDT 24
Peak memory 218568 kb
Host smart-b8368afc-01d6-4abf-a284-edb2c88f2184
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475537999 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.2475537999
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.350806194
Short name T189
Test name
Test status
Simulation time 20077676 ps
CPU time 1.05 seconds
Started Jul 20 06:49:42 PM PDT 24
Finished Jul 20 06:49:45 PM PDT 24
Peak memory 218832 kb
Host smart-b13af877-0991-41e9-9788-5e85b24ca45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350806194 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.350806194
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.3660315439
Short name T773
Test name
Test status
Simulation time 85115134 ps
CPU time 1.11 seconds
Started Jul 20 06:49:40 PM PDT 24
Finished Jul 20 06:49:41 PM PDT 24
Peak memory 217580 kb
Host smart-f0efedde-b60e-43a8-83ca-9b98830c217a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660315439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.3660315439
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.2656348135
Short name T400
Test name
Test status
Simulation time 35316739 ps
CPU time 0.85 seconds
Started Jul 20 06:49:47 PM PDT 24
Finished Jul 20 06:49:49 PM PDT 24
Peak memory 215568 kb
Host smart-832025f4-53fa-4c0c-87fd-1593380f12f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656348135 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.2656348135
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.2058216469
Short name T564
Test name
Test status
Simulation time 43756685 ps
CPU time 0.98 seconds
Started Jul 20 06:49:42 PM PDT 24
Finished Jul 20 06:49:44 PM PDT 24
Peak memory 215548 kb
Host smart-67438d76-c047-4a17-abd0-0bf51d14ab72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058216469 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.2058216469
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.2647796772
Short name T481
Test name
Test status
Simulation time 388775639 ps
CPU time 4.59 seconds
Started Jul 20 06:49:44 PM PDT 24
Finished Jul 20 06:49:51 PM PDT 24
Peak memory 220140 kb
Host smart-1d67d9e2-02ae-419a-a2b9-12566de74e69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647796772 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2647796772
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.4148163384
Short name T230
Test name
Test status
Simulation time 71763182336 ps
CPU time 526.73 seconds
Started Jul 20 06:49:48 PM PDT 24
Finished Jul 20 06:58:35 PM PDT 24
Peak memory 218708 kb
Host smart-468a1ab7-0779-4ea3-a3de-460dc04f4232
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148163384 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.4148163384
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.629634978
Short name T718
Test name
Test status
Simulation time 38285590 ps
CPU time 1.07 seconds
Started Jul 20 06:51:31 PM PDT 24
Finished Jul 20 06:51:37 PM PDT 24
Peak memory 220212 kb
Host smart-afe83a1d-9af0-4f1d-8140-de467ad0014c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629634978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.629634978
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.3904314016
Short name T569
Test name
Test status
Simulation time 43116915 ps
CPU time 1.53 seconds
Started Jul 20 06:51:30 PM PDT 24
Finished Jul 20 06:51:36 PM PDT 24
Peak memory 217424 kb
Host smart-bde2757e-9030-4bab-b7ad-29ced17edf73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904314016 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.3904314016
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3084933027
Short name T701
Test name
Test status
Simulation time 440496524 ps
CPU time 1.21 seconds
Started Jul 20 06:51:26 PM PDT 24
Finished Jul 20 06:51:33 PM PDT 24
Peak memory 217452 kb
Host smart-bd78cff9-e454-4447-a414-eaa9d9b963c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084933027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3084933027
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.355484155
Short name T924
Test name
Test status
Simulation time 57072549 ps
CPU time 1.31 seconds
Started Jul 20 06:51:27 PM PDT 24
Finished Jul 20 06:51:34 PM PDT 24
Peak memory 219056 kb
Host smart-0d7c6e54-e905-439a-9021-2ed20ee1ead2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355484155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.355484155
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.1090303823
Short name T473
Test name
Test status
Simulation time 38923044 ps
CPU time 1.46 seconds
Started Jul 20 06:51:27 PM PDT 24
Finished Jul 20 06:51:35 PM PDT 24
Peak memory 218592 kb
Host smart-53786b41-db76-4472-8dc7-22824f930abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090303823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.1090303823
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.724096146
Short name T80
Test name
Test status
Simulation time 38359332 ps
CPU time 1.31 seconds
Started Jul 20 06:51:26 PM PDT 24
Finished Jul 20 06:51:33 PM PDT 24
Peak memory 217872 kb
Host smart-fe56d45b-e95d-4ed8-92f6-425b41cf356b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724096146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.724096146
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.1643931152
Short name T836
Test name
Test status
Simulation time 51431439 ps
CPU time 1.36 seconds
Started Jul 20 06:51:32 PM PDT 24
Finished Jul 20 06:51:38 PM PDT 24
Peak memory 220380 kb
Host smart-6d6388e3-3839-4ec2-9d7b-0e4df8e1e228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643931152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.1643931152
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.300980231
Short name T688
Test name
Test status
Simulation time 35958898 ps
CPU time 1.43 seconds
Started Jul 20 06:51:30 PM PDT 24
Finished Jul 20 06:51:36 PM PDT 24
Peak memory 218628 kb
Host smart-5e9ca5fd-fb21-4697-8405-5adc65174870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300980231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.300980231
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.3971840954
Short name T486
Test name
Test status
Simulation time 56433351 ps
CPU time 1.46 seconds
Started Jul 20 06:51:27 PM PDT 24
Finished Jul 20 06:51:35 PM PDT 24
Peak memory 218748 kb
Host smart-5c8d4e4e-5000-4325-909f-e1c9d45698df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971840954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.3971840954
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.55235956
Short name T816
Test name
Test status
Simulation time 25304526 ps
CPU time 1.24 seconds
Started Jul 20 06:49:44 PM PDT 24
Finished Jul 20 06:49:47 PM PDT 24
Peak memory 219048 kb
Host smart-e041fe05-2290-4958-951f-b800478a9ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55235956 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.55235956
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.495374594
Short name T930
Test name
Test status
Simulation time 53091303 ps
CPU time 0.87 seconds
Started Jul 20 06:49:44 PM PDT 24
Finished Jul 20 06:49:47 PM PDT 24
Peak memory 207044 kb
Host smart-c3f9686f-ebf3-4cd5-a83d-24e164cc2865
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495374594 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.495374594
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.2996408690
Short name T203
Test name
Test status
Simulation time 12860486 ps
CPU time 0.91 seconds
Started Jul 20 06:49:41 PM PDT 24
Finished Jul 20 06:49:44 PM PDT 24
Peak memory 216680 kb
Host smart-bb13b592-abe9-4479-bc4f-b8641f799ae3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996408690 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2996408690
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.4018031641
Short name T383
Test name
Test status
Simulation time 91980149 ps
CPU time 0.91 seconds
Started Jul 20 06:49:44 PM PDT 24
Finished Jul 20 06:49:46 PM PDT 24
Peak memory 218380 kb
Host smart-868ddae9-33bf-4ab9-8bde-12eaefa18ae7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018031641 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.4018031641
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.4117499104
Short name T412
Test name
Test status
Simulation time 24438724 ps
CPU time 1.23 seconds
Started Jul 20 06:49:43 PM PDT 24
Finished Jul 20 06:49:46 PM PDT 24
Peak memory 219192 kb
Host smart-387f78f0-ca91-4817-99e6-aebb2ba75a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117499104 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.4117499104
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.3631903201
Short name T650
Test name
Test status
Simulation time 79985205 ps
CPU time 2.96 seconds
Started Jul 20 06:49:44 PM PDT 24
Finished Jul 20 06:49:49 PM PDT 24
Peak memory 220532 kb
Host smart-83ad417a-ec4f-4139-944b-eb622b8424ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631903201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.3631903201
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.1528713981
Short name T113
Test name
Test status
Simulation time 34860301 ps
CPU time 0.87 seconds
Started Jul 20 06:49:41 PM PDT 24
Finished Jul 20 06:49:42 PM PDT 24
Peak memory 215928 kb
Host smart-ac42917f-0d49-4f7b-9213-c40c205bab78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528713981 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1528713981
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.4168420647
Short name T455
Test name
Test status
Simulation time 43563763 ps
CPU time 0.92 seconds
Started Jul 20 06:49:42 PM PDT 24
Finished Jul 20 06:49:45 PM PDT 24
Peak memory 215468 kb
Host smart-b32d2e2b-a8c5-4354-ab72-3d1713cb68db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168420647 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.4168420647
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.396733016
Short name T241
Test name
Test status
Simulation time 714309639 ps
CPU time 6.96 seconds
Started Jul 20 06:49:41 PM PDT 24
Finished Jul 20 06:49:49 PM PDT 24
Peak memory 217288 kb
Host smart-69bb8996-959e-4e3c-befc-33244f1bd856
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396733016 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.396733016
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3688587136
Short name T232
Test name
Test status
Simulation time 69363522836 ps
CPU time 755.76 seconds
Started Jul 20 06:49:43 PM PDT 24
Finished Jul 20 07:02:21 PM PDT 24
Peak memory 223944 kb
Host smart-96fade28-1663-4029-8736-4bd9c11bab80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688587136 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3688587136
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.5110172
Short name T715
Test name
Test status
Simulation time 55599371 ps
CPU time 1.62 seconds
Started Jul 20 06:51:27 PM PDT 24
Finished Jul 20 06:51:34 PM PDT 24
Peak memory 218936 kb
Host smart-cc860e9c-5fa6-4caf-aada-320647e780fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5110172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.5110172
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.3921232221
Short name T324
Test name
Test status
Simulation time 107832781 ps
CPU time 1.35 seconds
Started Jul 20 06:51:24 PM PDT 24
Finished Jul 20 06:51:31 PM PDT 24
Peak memory 218784 kb
Host smart-48cdf2f5-cc43-4084-848d-c20bab691b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921232221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3921232221
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.2452883904
Short name T340
Test name
Test status
Simulation time 42342119 ps
CPU time 1.38 seconds
Started Jul 20 06:51:27 PM PDT 24
Finished Jul 20 06:51:34 PM PDT 24
Peak memory 218712 kb
Host smart-f854b395-6163-4680-adb6-f0285b52f1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452883904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.2452883904
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.2290276611
Short name T555
Test name
Test status
Simulation time 187718405 ps
CPU time 1.69 seconds
Started Jul 20 06:51:26 PM PDT 24
Finished Jul 20 06:51:33 PM PDT 24
Peak memory 219052 kb
Host smart-bc68e91d-9e7f-47b8-9991-b88cda1aa70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290276611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.2290276611
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.742711422
Short name T388
Test name
Test status
Simulation time 42274130 ps
CPU time 1.68 seconds
Started Jul 20 06:51:28 PM PDT 24
Finished Jul 20 06:51:35 PM PDT 24
Peak memory 218728 kb
Host smart-693c88ac-2fa1-4171-b700-6c120e53adf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742711422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.742711422
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.1289210757
Short name T313
Test name
Test status
Simulation time 31054005 ps
CPU time 1.27 seconds
Started Jul 20 06:51:27 PM PDT 24
Finished Jul 20 06:51:35 PM PDT 24
Peak memory 218912 kb
Host smart-e9bc198e-f28d-4174-91af-82278ac65fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289210757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.1289210757
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.3899193327
Short name T552
Test name
Test status
Simulation time 51191080 ps
CPU time 1.23 seconds
Started Jul 20 06:51:28 PM PDT 24
Finished Jul 20 06:51:35 PM PDT 24
Peak memory 217476 kb
Host smart-7c51d0ad-2753-42af-ba21-db0e94c9852b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899193327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3899193327
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.177262445
Short name T608
Test name
Test status
Simulation time 46272567 ps
CPU time 1.51 seconds
Started Jul 20 06:51:27 PM PDT 24
Finished Jul 20 06:51:34 PM PDT 24
Peak memory 220280 kb
Host smart-9e4f3d35-afd3-46d7-b96a-074f3fca09c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177262445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.177262445
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.1784344100
Short name T960
Test name
Test status
Simulation time 43649890 ps
CPU time 1.37 seconds
Started Jul 20 06:51:27 PM PDT 24
Finished Jul 20 06:51:34 PM PDT 24
Peak memory 218732 kb
Host smart-f8586678-cfdb-4d60-bf34-547c961e722e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784344100 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1784344100
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert_test.946676143
Short name T393
Test name
Test status
Simulation time 35506316 ps
CPU time 0.82 seconds
Started Jul 20 06:49:41 PM PDT 24
Finished Jul 20 06:49:44 PM PDT 24
Peak memory 215048 kb
Host smart-a56b8009-805a-4fa5-b27c-3f64fbf7a066
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946676143 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.946676143
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.1419046349
Short name T601
Test name
Test status
Simulation time 23855927 ps
CPU time 0.93 seconds
Started Jul 20 06:49:45 PM PDT 24
Finished Jul 20 06:49:48 PM PDT 24
Peak memory 216184 kb
Host smart-3b4b77cf-13c2-4751-9600-2d2674362bf6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419046349 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.1419046349
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3106629936
Short name T992
Test name
Test status
Simulation time 34448514 ps
CPU time 1.32 seconds
Started Jul 20 06:49:41 PM PDT 24
Finished Jul 20 06:49:42 PM PDT 24
Peak memory 217100 kb
Host smart-832dcaeb-2470-4a7f-b14d-1af6e4622cf3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106629936 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3106629936
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.3284820975
Short name T158
Test name
Test status
Simulation time 27507043 ps
CPU time 0.86 seconds
Started Jul 20 06:49:45 PM PDT 24
Finished Jul 20 06:49:47 PM PDT 24
Peak memory 218644 kb
Host smart-0fbf715c-a5e8-4784-92aa-d23f8084723f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284820975 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.3284820975
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_intr.3219187869
Short name T546
Test name
Test status
Simulation time 24311545 ps
CPU time 0.98 seconds
Started Jul 20 06:49:43 PM PDT 24
Finished Jul 20 06:49:46 PM PDT 24
Peak memory 215756 kb
Host smart-53743d1a-79b1-484c-b992-cbc42fa498cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219187869 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3219187869
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.367421568
Short name T457
Test name
Test status
Simulation time 26189011 ps
CPU time 0.92 seconds
Started Jul 20 06:49:44 PM PDT 24
Finished Jul 20 06:49:47 PM PDT 24
Peak memory 215544 kb
Host smart-d69f559b-6d40-4f7f-bcd5-6396bc34c694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367421568 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.367421568
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.2450374181
Short name T237
Test name
Test status
Simulation time 191966562 ps
CPU time 2.38 seconds
Started Jul 20 06:49:42 PM PDT 24
Finished Jul 20 06:49:46 PM PDT 24
Peak memory 217444 kb
Host smart-24e355a1-478a-4c5e-bad5-8340e846a74f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450374181 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.2450374181
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.3692750682
Short name T235
Test name
Test status
Simulation time 121822362859 ps
CPU time 1510.85 seconds
Started Jul 20 06:49:43 PM PDT 24
Finished Jul 20 07:14:56 PM PDT 24
Peak memory 223972 kb
Host smart-5d9edb4f-87db-4c6f-8251-89a96b0210fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692750682 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.3692750682
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.1200668805
Short name T484
Test name
Test status
Simulation time 84398550 ps
CPU time 1.5 seconds
Started Jul 20 06:51:31 PM PDT 24
Finished Jul 20 06:51:38 PM PDT 24
Peak memory 219244 kb
Host smart-1ef532b4-ad1f-4c4a-8a3f-555d4fcb214d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200668805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.1200668805
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.1462262910
Short name T471
Test name
Test status
Simulation time 37098478 ps
CPU time 1.39 seconds
Started Jul 20 06:51:37 PM PDT 24
Finished Jul 20 06:51:41 PM PDT 24
Peak memory 218680 kb
Host smart-46d13178-46dc-4455-a58b-05d4b063b766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462262910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1462262910
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.719932033
Short name T649
Test name
Test status
Simulation time 68812027 ps
CPU time 1.42 seconds
Started Jul 20 06:51:37 PM PDT 24
Finished Jul 20 06:51:42 PM PDT 24
Peak memory 217760 kb
Host smart-f9a72be5-67c8-4bbb-b0f4-6b74086f3966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719932033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.719932033
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.1403843470
Short name T673
Test name
Test status
Simulation time 92067901 ps
CPU time 1.42 seconds
Started Jul 20 06:51:34 PM PDT 24
Finished Jul 20 06:51:39 PM PDT 24
Peak memory 219340 kb
Host smart-582a5af4-0f34-4b95-9ea2-7c43fae8089f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403843470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.1403843470
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.2082960721
Short name T923
Test name
Test status
Simulation time 32553581 ps
CPU time 1.32 seconds
Started Jul 20 06:51:36 PM PDT 24
Finished Jul 20 06:51:41 PM PDT 24
Peak memory 220268 kb
Host smart-5e46e951-555c-49f2-bfc8-85f53f78cffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082960721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2082960721
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.1751001439
Short name T594
Test name
Test status
Simulation time 247159113 ps
CPU time 3.54 seconds
Started Jul 20 06:51:31 PM PDT 24
Finished Jul 20 06:51:40 PM PDT 24
Peak memory 219100 kb
Host smart-7cf28568-c961-4a2b-96ec-717add831939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751001439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.1751001439
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.3821792876
Short name T705
Test name
Test status
Simulation time 39247392 ps
CPU time 1.53 seconds
Started Jul 20 06:51:34 PM PDT 24
Finished Jul 20 06:51:40 PM PDT 24
Peak memory 220468 kb
Host smart-30be2882-a30e-4e88-8799-b43a0f9e3f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821792876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3821792876
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.3832839678
Short name T366
Test name
Test status
Simulation time 31631439 ps
CPU time 1.42 seconds
Started Jul 20 06:51:32 PM PDT 24
Finished Jul 20 06:51:38 PM PDT 24
Peak memory 218788 kb
Host smart-e031485f-db8e-4d56-972c-e5caa361c571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832839678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.3832839678
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.1857160045
Short name T742
Test name
Test status
Simulation time 89904956 ps
CPU time 1.18 seconds
Started Jul 20 06:51:36 PM PDT 24
Finished Jul 20 06:51:41 PM PDT 24
Peak memory 217792 kb
Host smart-f4859cac-cfa1-4885-8784-18a8b1ae4900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857160045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.1857160045
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.1739271559
Short name T295
Test name
Test status
Simulation time 102131044 ps
CPU time 1.12 seconds
Started Jul 20 06:51:37 PM PDT 24
Finished Jul 20 06:51:41 PM PDT 24
Peak memory 217580 kb
Host smart-6e3cba15-2be1-43fc-b6fe-36cbcd901220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739271559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.1739271559
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.57063758
Short name T558
Test name
Test status
Simulation time 71057038 ps
CPU time 1.16 seconds
Started Jul 20 06:49:42 PM PDT 24
Finished Jul 20 06:49:46 PM PDT 24
Peak memory 220000 kb
Host smart-c2a8e15d-f18d-4e96-b28f-d8dc42e5dbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57063758 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.57063758
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.3761462746
Short name T599
Test name
Test status
Simulation time 27239760 ps
CPU time 0.94 seconds
Started Jul 20 06:49:43 PM PDT 24
Finished Jul 20 06:49:46 PM PDT 24
Peak memory 207032 kb
Host smart-e7e19c07-d29e-4d57-8b65-b8eb9cd3e6d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761462746 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.3761462746
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.3341016350
Short name T544
Test name
Test status
Simulation time 37657241 ps
CPU time 0.88 seconds
Started Jul 20 06:49:42 PM PDT 24
Finished Jul 20 06:49:45 PM PDT 24
Peak memory 216404 kb
Host smart-651949f5-9f10-497b-93e9-7b760df9e011
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341016350 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.3341016350
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.2912359070
Short name T952
Test name
Test status
Simulation time 36123386 ps
CPU time 1.29 seconds
Started Jul 20 06:49:42 PM PDT 24
Finished Jul 20 06:49:46 PM PDT 24
Peak memory 217100 kb
Host smart-0f65194e-198e-47a9-95e9-11fb9468dcf5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912359070 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.2912359070
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.417867135
Short name T565
Test name
Test status
Simulation time 22495558 ps
CPU time 0.92 seconds
Started Jul 20 06:49:44 PM PDT 24
Finished Jul 20 06:49:47 PM PDT 24
Peak memory 218548 kb
Host smart-7e1fa4e8-1245-4968-ab8c-87876303b972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417867135 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.417867135
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.917536115
Short name T318
Test name
Test status
Simulation time 45752331 ps
CPU time 1.5 seconds
Started Jul 20 06:49:43 PM PDT 24
Finished Jul 20 06:49:47 PM PDT 24
Peak memory 218696 kb
Host smart-cbc40678-d6f0-4d5d-8511-b464815b2e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917536115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.917536115
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.1936450656
Short name T112
Test name
Test status
Simulation time 31504662 ps
CPU time 0.88 seconds
Started Jul 20 06:49:48 PM PDT 24
Finished Jul 20 06:49:50 PM PDT 24
Peak memory 215912 kb
Host smart-982e250c-0fd7-4553-acec-0f319e2442b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936450656 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.1936450656
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.246174186
Short name T665
Test name
Test status
Simulation time 15543077 ps
CPU time 0.99 seconds
Started Jul 20 06:49:41 PM PDT 24
Finished Jul 20 06:49:44 PM PDT 24
Peak memory 215528 kb
Host smart-fe28d8ca-4d6d-4058-ac81-f0e16ffb7e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246174186 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.246174186
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.2638725074
Short name T745
Test name
Test status
Simulation time 538304942 ps
CPU time 3.34 seconds
Started Jul 20 06:49:44 PM PDT 24
Finished Jul 20 06:49:49 PM PDT 24
Peak memory 217516 kb
Host smart-5e0d0025-b8d8-44a3-87cb-874febcd3e22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638725074 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2638725074
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.999430089
Short name T921
Test name
Test status
Simulation time 106649335501 ps
CPU time 1514.52 seconds
Started Jul 20 06:49:39 PM PDT 24
Finished Jul 20 07:14:54 PM PDT 24
Peak memory 225016 kb
Host smart-91ff1365-fcee-4b66-b6bf-aad644da7e63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999430089 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.999430089
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.2622250834
Short name T788
Test name
Test status
Simulation time 44438348 ps
CPU time 1.69 seconds
Started Jul 20 06:51:37 PM PDT 24
Finished Jul 20 06:51:42 PM PDT 24
Peak memory 218804 kb
Host smart-f6551163-7c96-445b-9fef-8b410eca3f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622250834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.2622250834
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.2919788938
Short name T405
Test name
Test status
Simulation time 143172345 ps
CPU time 1.08 seconds
Started Jul 20 06:51:33 PM PDT 24
Finished Jul 20 06:51:39 PM PDT 24
Peak memory 217548 kb
Host smart-7a94cb97-3987-415c-935a-ac210022b907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919788938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.2919788938
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.4128086836
Short name T663
Test name
Test status
Simulation time 44251143 ps
CPU time 1.76 seconds
Started Jul 20 06:51:31 PM PDT 24
Finished Jul 20 06:51:38 PM PDT 24
Peak memory 217756 kb
Host smart-5cc8c07c-8353-404f-aa3f-e4d9825bd910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128086836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.4128086836
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.1181722889
Short name T38
Test name
Test status
Simulation time 148679059 ps
CPU time 1.63 seconds
Started Jul 20 06:51:34 PM PDT 24
Finished Jul 20 06:51:40 PM PDT 24
Peak memory 218936 kb
Host smart-11f52302-2460-414f-b6dc-b19e8ffe5896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181722889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.1181722889
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.1657478472
Short name T477
Test name
Test status
Simulation time 64177284 ps
CPU time 1.51 seconds
Started Jul 20 06:51:33 PM PDT 24
Finished Jul 20 06:51:39 PM PDT 24
Peak memory 218960 kb
Host smart-cfc77910-950f-4950-a7ff-4e26b35de349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657478472 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.1657478472
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.3545232225
Short name T912
Test name
Test status
Simulation time 58911326 ps
CPU time 1.41 seconds
Started Jul 20 06:51:34 PM PDT 24
Finished Jul 20 06:51:39 PM PDT 24
Peak memory 218564 kb
Host smart-95428a9a-b8f8-459c-a916-9837d000d9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545232225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.3545232225
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.3121068015
Short name T83
Test name
Test status
Simulation time 218701195 ps
CPU time 1.24 seconds
Started Jul 20 06:51:37 PM PDT 24
Finished Jul 20 06:51:42 PM PDT 24
Peak memory 217584 kb
Host smart-ef6a127d-b0be-48fe-9ddd-4f8c82d4bf79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121068015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.3121068015
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.2550421535
Short name T37
Test name
Test status
Simulation time 182353192 ps
CPU time 1.35 seconds
Started Jul 20 06:51:36 PM PDT 24
Finished Jul 20 06:51:41 PM PDT 24
Peak memory 217672 kb
Host smart-ec0e72ba-d4d0-47d8-8ad3-da974f1f07d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550421535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.2550421535
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.1486327516
Short name T526
Test name
Test status
Simulation time 58402839 ps
CPU time 1.15 seconds
Started Jul 20 06:51:37 PM PDT 24
Finished Jul 20 06:51:41 PM PDT 24
Peak memory 217668 kb
Host smart-a414cc14-8232-4725-83eb-776cca1988f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486327516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.1486327516
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.3914001744
Short name T308
Test name
Test status
Simulation time 80121938 ps
CPU time 1.06 seconds
Started Jul 20 06:51:31 PM PDT 24
Finished Jul 20 06:51:37 PM PDT 24
Peak memory 215656 kb
Host smart-be6bfd35-d2d0-4237-b6f7-48b8703530b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914001744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.3914001744
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.2595092553
Short name T74
Test name
Test status
Simulation time 38330074 ps
CPU time 1.21 seconds
Started Jul 20 06:49:50 PM PDT 24
Finished Jul 20 06:49:53 PM PDT 24
Peak memory 219900 kb
Host smart-c2ec3ca4-c3a0-4d75-826b-4268ad108b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595092553 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.2595092553
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.1674128318
Short name T905
Test name
Test status
Simulation time 19746553 ps
CPU time 1.01 seconds
Started Jul 20 06:49:50 PM PDT 24
Finished Jul 20 06:49:53 PM PDT 24
Peak memory 207024 kb
Host smart-381e587d-a89f-438b-9301-f70ec83c5065
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674128318 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.1674128318
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.692692704
Short name T837
Test name
Test status
Simulation time 20573236 ps
CPU time 0.89 seconds
Started Jul 20 06:49:54 PM PDT 24
Finished Jul 20 06:49:56 PM PDT 24
Peak memory 216180 kb
Host smart-0b74f441-14bd-468d-8d68-97a425a9c573
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692692704 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.692692704
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_err.1396089674
Short name T700
Test name
Test status
Simulation time 19418962 ps
CPU time 1.11 seconds
Started Jul 20 06:49:55 PM PDT 24
Finished Jul 20 06:49:57 PM PDT 24
Peak memory 218940 kb
Host smart-ca0ec30b-5f78-492a-8abf-9019a0e129af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396089674 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.1396089674
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.488359037
Short name T925
Test name
Test status
Simulation time 60377549 ps
CPU time 1.23 seconds
Started Jul 20 06:49:47 PM PDT 24
Finished Jul 20 06:49:49 PM PDT 24
Peak memory 219712 kb
Host smart-4bb2afca-b336-4677-9b73-6dd39788bfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488359037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.488359037
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.2255163685
Short name T609
Test name
Test status
Simulation time 26858960 ps
CPU time 0.95 seconds
Started Jul 20 06:49:58 PM PDT 24
Finished Jul 20 06:50:00 PM PDT 24
Peak memory 216096 kb
Host smart-84b7254e-5e6b-4346-a9b8-9e7b37c20bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255163685 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2255163685
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.498900904
Short name T839
Test name
Test status
Simulation time 63141078 ps
CPU time 0.93 seconds
Started Jul 20 06:49:53 PM PDT 24
Finished Jul 20 06:49:56 PM PDT 24
Peak memory 207384 kb
Host smart-fa4d65b7-fbee-4e9e-a469-0d700b63e5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498900904 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.498900904
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.982578784
Short name T333
Test name
Test status
Simulation time 99013245 ps
CPU time 1.81 seconds
Started Jul 20 06:49:53 PM PDT 24
Finished Jul 20 06:49:56 PM PDT 24
Peak memory 215380 kb
Host smart-cc2fdd66-7429-42d7-a0eb-1941446e648c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982578784 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.982578784
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.3415503561
Short name T747
Test name
Test status
Simulation time 507262022255 ps
CPU time 2143.51 seconds
Started Jul 20 06:49:54 PM PDT 24
Finished Jul 20 07:25:39 PM PDT 24
Peak memory 230628 kb
Host smart-e53f4c39-ce17-4b63-958a-dd9f04bdbaf6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415503561 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.3415503561
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.3542900811
Short name T848
Test name
Test status
Simulation time 109290253 ps
CPU time 1.02 seconds
Started Jul 20 06:51:37 PM PDT 24
Finished Jul 20 06:51:41 PM PDT 24
Peak memory 217604 kb
Host smart-52e38da5-0d60-4b2a-a88a-c3e3244ddee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542900811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3542900811
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.174504198
Short name T956
Test name
Test status
Simulation time 101144962 ps
CPU time 1.21 seconds
Started Jul 20 06:51:37 PM PDT 24
Finished Jul 20 06:51:41 PM PDT 24
Peak memory 217468 kb
Host smart-48ce643f-babc-4c8e-95b5-cef1f50fb72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174504198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.174504198
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2747785936
Short name T953
Test name
Test status
Simulation time 54573003 ps
CPU time 1.7 seconds
Started Jul 20 06:51:34 PM PDT 24
Finished Jul 20 06:51:40 PM PDT 24
Peak memory 218608 kb
Host smart-ff4febaa-6595-40e3-92be-8011cae74cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747785936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2747785936
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.112525452
Short name T441
Test name
Test status
Simulation time 26701775 ps
CPU time 1.12 seconds
Started Jul 20 06:51:30 PM PDT 24
Finished Jul 20 06:51:36 PM PDT 24
Peak memory 217356 kb
Host smart-7970194f-d58e-45dc-9dce-4295b80878b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112525452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.112525452
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.2928952778
Short name T381
Test name
Test status
Simulation time 77476898 ps
CPU time 1.41 seconds
Started Jul 20 06:51:31 PM PDT 24
Finished Jul 20 06:51:38 PM PDT 24
Peak memory 218608 kb
Host smart-062e2831-3807-4b57-859f-d20a8ab5c0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928952778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2928952778
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.3434666032
Short name T519
Test name
Test status
Simulation time 41344740 ps
CPU time 1.47 seconds
Started Jul 20 06:51:37 PM PDT 24
Finished Jul 20 06:51:41 PM PDT 24
Peak memory 219792 kb
Host smart-557d7d29-2851-4875-a24c-2bc1d4ce26ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434666032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.3434666032
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.2184463381
Short name T666
Test name
Test status
Simulation time 84182981 ps
CPU time 2.87 seconds
Started Jul 20 06:51:37 PM PDT 24
Finished Jul 20 06:51:43 PM PDT 24
Peak memory 220340 kb
Host smart-84f3d66b-4a62-4de5-8f9b-4f00774681f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184463381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.2184463381
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.4039953784
Short name T989
Test name
Test status
Simulation time 235095440 ps
CPU time 1.16 seconds
Started Jul 20 06:51:33 PM PDT 24
Finished Jul 20 06:51:39 PM PDT 24
Peak memory 217928 kb
Host smart-20c4b668-41cc-4823-ab26-ddcc9ad2153f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039953784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.4039953784
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.1828831536
Short name T315
Test name
Test status
Simulation time 80304670 ps
CPU time 1.57 seconds
Started Jul 20 06:51:33 PM PDT 24
Finished Jul 20 06:51:39 PM PDT 24
Peak memory 218932 kb
Host smart-6c8a20f3-690e-4209-8d04-829c1ed983e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828831536 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.1828831536
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.3356534375
Short name T716
Test name
Test status
Simulation time 23933224 ps
CPU time 1.2 seconds
Started Jul 20 06:49:52 PM PDT 24
Finished Jul 20 06:49:55 PM PDT 24
Peak memory 221192 kb
Host smart-5e4989b7-b02d-4771-9a36-5deb574222d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356534375 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.3356534375
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.1559190540
Short name T675
Test name
Test status
Simulation time 15945778 ps
CPU time 0.97 seconds
Started Jul 20 06:49:57 PM PDT 24
Finished Jul 20 06:50:00 PM PDT 24
Peak memory 207012 kb
Host smart-769c7977-efb3-4b16-9a6e-85c0571c5751
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559190540 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.1559190540
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.1559696741
Short name T376
Test name
Test status
Simulation time 46673392 ps
CPU time 0.84 seconds
Started Jul 20 06:49:49 PM PDT 24
Finished Jul 20 06:49:50 PM PDT 24
Peak memory 216576 kb
Host smart-32efeb5b-9f82-4e99-b928-97fe80d32f34
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559696741 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1559696741
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.3917370118
Short name T147
Test name
Test status
Simulation time 144501348 ps
CPU time 1.09 seconds
Started Jul 20 06:49:51 PM PDT 24
Finished Jul 20 06:49:54 PM PDT 24
Peak memory 217208 kb
Host smart-0e92e534-7bba-48ac-8db8-33f833a6e3cb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917370118 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.3917370118
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_genbits.487974309
Short name T932
Test name
Test status
Simulation time 30743215 ps
CPU time 1.45 seconds
Started Jul 20 06:49:50 PM PDT 24
Finished Jul 20 06:49:53 PM PDT 24
Peak memory 218976 kb
Host smart-77363f6f-9cfc-48b9-9870-bbfac634c88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487974309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.487974309
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.1647683190
Short name T100
Test name
Test status
Simulation time 28632020 ps
CPU time 0.98 seconds
Started Jul 20 06:49:52 PM PDT 24
Finished Jul 20 06:49:54 PM PDT 24
Peak memory 216232 kb
Host smart-ccc433e2-664e-428f-9d5c-b3a4089cdee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647683190 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.1647683190
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.3945789916
Short name T678
Test name
Test status
Simulation time 141316726 ps
CPU time 0.94 seconds
Started Jul 20 06:49:50 PM PDT 24
Finished Jul 20 06:49:52 PM PDT 24
Peak memory 215492 kb
Host smart-506813ac-7daa-4f5e-aa92-7cf0690f7679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945789916 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.3945789916
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.3725055046
Short name T651
Test name
Test status
Simulation time 268221460 ps
CPU time 5.41 seconds
Started Jul 20 06:49:53 PM PDT 24
Finished Jul 20 06:50:00 PM PDT 24
Peak memory 217552 kb
Host smart-886c5c3c-1fe9-4d4a-8b18-2a31f164ac30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725055046 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3725055046
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.553924121
Short name T225
Test name
Test status
Simulation time 13117279115 ps
CPU time 354.78 seconds
Started Jul 20 06:49:50 PM PDT 24
Finished Jul 20 06:55:46 PM PDT 24
Peak memory 218004 kb
Host smart-f0679b89-075a-449b-b6e6-9268bbba8076
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553924121 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.553924121
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.2821260386
Short name T990
Test name
Test status
Simulation time 30539580 ps
CPU time 1.2 seconds
Started Jul 20 06:51:33 PM PDT 24
Finished Jul 20 06:51:39 PM PDT 24
Peak memory 220120 kb
Host smart-4600e9d4-0c76-47ef-974c-6692386123f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821260386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.2821260386
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.1797022876
Short name T22
Test name
Test status
Simulation time 68764871 ps
CPU time 1.07 seconds
Started Jul 20 06:51:34 PM PDT 24
Finished Jul 20 06:51:40 PM PDT 24
Peak memory 217684 kb
Host smart-66436bec-20e6-4808-9042-77edd80e4c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797022876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1797022876
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.1592690850
Short name T887
Test name
Test status
Simulation time 36229634 ps
CPU time 1.51 seconds
Started Jul 20 06:51:35 PM PDT 24
Finished Jul 20 06:51:41 PM PDT 24
Peak memory 218900 kb
Host smart-a85cbfc8-9f28-4e8b-97c1-7a11a11c2458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592690850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.1592690850
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.313031051
Short name T795
Test name
Test status
Simulation time 51809798 ps
CPU time 1.54 seconds
Started Jul 20 06:51:33 PM PDT 24
Finished Jul 20 06:51:39 PM PDT 24
Peak memory 218992 kb
Host smart-d17c5a8e-734a-426d-b5e0-37a1f0574cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313031051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.313031051
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.321721926
Short name T692
Test name
Test status
Simulation time 73525311 ps
CPU time 1.33 seconds
Started Jul 20 06:51:32 PM PDT 24
Finished Jul 20 06:51:38 PM PDT 24
Peak memory 219568 kb
Host smart-9609a704-e251-4af7-a365-855701b1c494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321721926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.321721926
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.3948001563
Short name T945
Test name
Test status
Simulation time 36339183 ps
CPU time 1.51 seconds
Started Jul 20 06:51:36 PM PDT 24
Finished Jul 20 06:51:41 PM PDT 24
Peak memory 217836 kb
Host smart-65f91ebd-d411-47ec-815c-fc2b8cac5d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948001563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.3948001563
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.407281332
Short name T316
Test name
Test status
Simulation time 94286814 ps
CPU time 1.58 seconds
Started Jul 20 06:51:35 PM PDT 24
Finished Jul 20 06:51:40 PM PDT 24
Peak memory 220184 kb
Host smart-e92811dc-ecca-440f-a272-f9c520852376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407281332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.407281332
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.3074068402
Short name T639
Test name
Test status
Simulation time 58358944 ps
CPU time 1.55 seconds
Started Jul 20 06:51:34 PM PDT 24
Finished Jul 20 06:51:39 PM PDT 24
Peak memory 217396 kb
Host smart-2d46a8dd-5886-498d-bf57-80510a6ee759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074068402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.3074068402
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.985555988
Short name T391
Test name
Test status
Simulation time 81863834 ps
CPU time 1.19 seconds
Started Jul 20 06:51:37 PM PDT 24
Finished Jul 20 06:51:41 PM PDT 24
Peak memory 219036 kb
Host smart-c0a01dc5-0fbd-4d67-916e-542b15b48af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985555988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.985555988
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.934921516
Short name T775
Test name
Test status
Simulation time 444482889 ps
CPU time 4.35 seconds
Started Jul 20 06:51:37 PM PDT 24
Finished Jul 20 06:51:45 PM PDT 24
Peak memory 219032 kb
Host smart-8a0a74d1-b06a-4acc-ab09-4cd92f3727a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934921516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.934921516
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.711053789
Short name T880
Test name
Test status
Simulation time 42299343 ps
CPU time 1.1 seconds
Started Jul 20 06:49:48 PM PDT 24
Finished Jul 20 06:49:50 PM PDT 24
Peak memory 220912 kb
Host smart-841171b7-c7c5-42eb-8205-2fb537907301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711053789 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.711053789
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.2021839767
Short name T510
Test name
Test status
Simulation time 16805486 ps
CPU time 0.95 seconds
Started Jul 20 06:49:57 PM PDT 24
Finished Jul 20 06:50:00 PM PDT 24
Peak memory 207028 kb
Host smart-1c953245-6473-451f-820d-5b13783c99a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021839767 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.2021839767
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.3911519239
Short name T458
Test name
Test status
Simulation time 12386405 ps
CPU time 0.91 seconds
Started Jul 20 06:49:57 PM PDT 24
Finished Jul 20 06:49:59 PM PDT 24
Peak memory 216388 kb
Host smart-f4e7cd09-844f-4f3f-9618-aee1ddbced8b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911519239 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3911519239
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.137573763
Short name T987
Test name
Test status
Simulation time 32104402 ps
CPU time 1.12 seconds
Started Jul 20 06:49:54 PM PDT 24
Finished Jul 20 06:49:57 PM PDT 24
Peak memory 215876 kb
Host smart-300f636f-672d-4d5c-af95-174a72f49732
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137573763 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_di
sable_auto_req_mode.137573763
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.420967667
Short name T117
Test name
Test status
Simulation time 24155923 ps
CPU time 1.31 seconds
Started Jul 20 06:49:50 PM PDT 24
Finished Jul 20 06:49:53 PM PDT 24
Peak memory 229884 kb
Host smart-72082c7f-a4bd-4aeb-b959-b286a62d0030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420967667 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.420967667
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.3500953425
Short name T399
Test name
Test status
Simulation time 153909956 ps
CPU time 1.29 seconds
Started Jul 20 06:49:51 PM PDT 24
Finished Jul 20 06:49:54 PM PDT 24
Peak memory 220104 kb
Host smart-2be49ae3-d5d7-44c5-8b39-951e467c3d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500953425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.3500953425
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.234068098
Short name T962
Test name
Test status
Simulation time 28381938 ps
CPU time 0.91 seconds
Started Jul 20 06:49:54 PM PDT 24
Finished Jul 20 06:49:56 PM PDT 24
Peak memory 216120 kb
Host smart-6a657ae0-b926-490d-8604-2c030612ab84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234068098 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.234068098
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.1980302441
Short name T723
Test name
Test status
Simulation time 69285248 ps
CPU time 0.93 seconds
Started Jul 20 06:49:49 PM PDT 24
Finished Jul 20 06:49:50 PM PDT 24
Peak memory 215528 kb
Host smart-b677b1f6-1e17-46a9-a312-1a21a3124564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980302441 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.1980302441
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.89613831
Short name T323
Test name
Test status
Simulation time 806090293 ps
CPU time 4.82 seconds
Started Jul 20 06:49:50 PM PDT 24
Finished Jul 20 06:49:56 PM PDT 24
Peak memory 217416 kb
Host smart-35f35cf4-628f-4eff-86bd-031f2d95695f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89613831 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.89613831
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.466068788
Short name T647
Test name
Test status
Simulation time 73691243604 ps
CPU time 837.83 seconds
Started Jul 20 06:49:48 PM PDT 24
Finished Jul 20 07:03:46 PM PDT 24
Peak memory 221524 kb
Host smart-68493b4d-c624-4e43-85a7-506d77e5d8c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466068788 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.466068788
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.2821587152
Short name T371
Test name
Test status
Simulation time 205066554 ps
CPU time 3.36 seconds
Started Jul 20 06:51:33 PM PDT 24
Finished Jul 20 06:51:40 PM PDT 24
Peak memory 220520 kb
Host smart-52b820a9-21e1-4cad-a22b-2d97f7e516c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821587152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2821587152
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.1942446323
Short name T793
Test name
Test status
Simulation time 46061560 ps
CPU time 1.45 seconds
Started Jul 20 06:51:36 PM PDT 24
Finished Jul 20 06:51:41 PM PDT 24
Peak memory 218688 kb
Host smart-ff560708-7e79-456c-bad0-422603ae124a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942446323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.1942446323
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.2756112221
Short name T341
Test name
Test status
Simulation time 40840511 ps
CPU time 1.41 seconds
Started Jul 20 06:51:32 PM PDT 24
Finished Jul 20 06:51:38 PM PDT 24
Peak memory 218936 kb
Host smart-aaa48f38-621c-4aec-b20f-5aded501ce91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756112221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.2756112221
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.3701032862
Short name T300
Test name
Test status
Simulation time 70368412 ps
CPU time 2.62 seconds
Started Jul 20 06:51:48 PM PDT 24
Finished Jul 20 06:51:51 PM PDT 24
Peak memory 220152 kb
Host smart-cf805161-b8ae-43fe-86cc-89d6e37d036f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701032862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.3701032862
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.2087000704
Short name T782
Test name
Test status
Simulation time 36050221 ps
CPU time 1.46 seconds
Started Jul 20 06:51:40 PM PDT 24
Finished Jul 20 06:51:44 PM PDT 24
Peak memory 218964 kb
Host smart-ad1d6a73-65e4-43f1-bc6b-af9cb4c3c125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087000704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.2087000704
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.1638389943
Short name T42
Test name
Test status
Simulation time 43021758 ps
CPU time 1.56 seconds
Started Jul 20 06:51:40 PM PDT 24
Finished Jul 20 06:51:44 PM PDT 24
Peak memory 218724 kb
Host smart-1a7329c8-f26f-4dfd-afd7-35533ae087c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638389943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.1638389943
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3086518926
Short name T963
Test name
Test status
Simulation time 83651403 ps
CPU time 1.39 seconds
Started Jul 20 06:51:44 PM PDT 24
Finished Jul 20 06:51:47 PM PDT 24
Peak memory 219300 kb
Host smart-479ef617-d5dd-4dbb-901e-2223aeb7a4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086518926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3086518926
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.3128244871
Short name T515
Test name
Test status
Simulation time 39619991 ps
CPU time 1.29 seconds
Started Jul 20 06:51:43 PM PDT 24
Finished Jul 20 06:51:46 PM PDT 24
Peak memory 218760 kb
Host smart-8fed845a-e870-458d-882b-8ca66c36fc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128244871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.3128244871
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.2023124916
Short name T451
Test name
Test status
Simulation time 93015177 ps
CPU time 1.18 seconds
Started Jul 20 06:51:42 PM PDT 24
Finished Jul 20 06:51:45 PM PDT 24
Peak memory 217608 kb
Host smart-238cd8ca-2ce3-4f54-8ca6-66c4f816ad8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023124916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.2023124916
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.143170722
Short name T361
Test name
Test status
Simulation time 103837628 ps
CPU time 1.24 seconds
Started Jul 20 06:51:39 PM PDT 24
Finished Jul 20 06:51:43 PM PDT 24
Peak memory 217520 kb
Host smart-c4f3a63a-0cca-4d18-9502-40571ad5aa5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143170722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.143170722
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.2445090345
Short name T977
Test name
Test status
Simulation time 102156597 ps
CPU time 1.25 seconds
Started Jul 20 06:49:49 PM PDT 24
Finished Jul 20 06:49:51 PM PDT 24
Peak memory 218644 kb
Host smart-ac0c2c0a-0242-4b07-8433-2e1a6d953a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445090345 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2445090345
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.218972261
Short name T444
Test name
Test status
Simulation time 32149175 ps
CPU time 0.98 seconds
Started Jul 20 06:49:50 PM PDT 24
Finished Jul 20 06:49:53 PM PDT 24
Peak memory 215208 kb
Host smart-497a7219-0153-472d-a7c5-ade368394fc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218972261 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.218972261
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.2669120756
Short name T542
Test name
Test status
Simulation time 20175294 ps
CPU time 0.9 seconds
Started Jul 20 06:49:55 PM PDT 24
Finished Jul 20 06:49:57 PM PDT 24
Peak memory 216472 kb
Host smart-b3841468-d1eb-4d93-9bbf-0175b8d13a5b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669120756 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.2669120756
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.2355151327
Short name T438
Test name
Test status
Simulation time 184984712 ps
CPU time 1.05 seconds
Started Jul 20 06:49:51 PM PDT 24
Finished Jul 20 06:49:53 PM PDT 24
Peak memory 217064 kb
Host smart-ce52e020-c80a-46b9-9397-7884e46be53a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355151327 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.2355151327
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.1937952720
Short name T145
Test name
Test status
Simulation time 36687565 ps
CPU time 1.1 seconds
Started Jul 20 06:49:51 PM PDT 24
Finished Jul 20 06:49:53 PM PDT 24
Peak memory 219972 kb
Host smart-7a64c060-d259-42ae-97f8-fccdf4338428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937952720 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.1937952720
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.2625734239
Short name T497
Test name
Test status
Simulation time 99900947 ps
CPU time 1.19 seconds
Started Jul 20 06:49:52 PM PDT 24
Finished Jul 20 06:49:54 PM PDT 24
Peak memory 217672 kb
Host smart-afac90bc-e0bf-4e91-b250-b72cc4f70963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625734239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.2625734239
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.729577946
Short name T52
Test name
Test status
Simulation time 52322831 ps
CPU time 1.01 seconds
Started Jul 20 06:49:52 PM PDT 24
Finished Jul 20 06:49:55 PM PDT 24
Peak memory 224144 kb
Host smart-f2be13d8-6230-42f8-8685-7992db00e5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729577946 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.729577946
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.2205464108
Short name T813
Test name
Test status
Simulation time 48760155 ps
CPU time 0.93 seconds
Started Jul 20 06:49:54 PM PDT 24
Finished Jul 20 06:49:56 PM PDT 24
Peak memory 215672 kb
Host smart-0f0dec9a-c00f-4d56-96bc-cda880ca1b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205464108 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.2205464108
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.3523781692
Short name T401
Test name
Test status
Simulation time 502817689 ps
CPU time 3.05 seconds
Started Jul 20 06:49:49 PM PDT 24
Finished Jul 20 06:49:54 PM PDT 24
Peak memory 217724 kb
Host smart-8265fa28-ecd5-49da-8291-0f23354fed0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523781692 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.3523781692
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.51125813
Short name T537
Test name
Test status
Simulation time 142481410844 ps
CPU time 1576.93 seconds
Started Jul 20 06:49:50 PM PDT 24
Finished Jul 20 07:16:09 PM PDT 24
Peak memory 225500 kb
Host smart-5a9f3aa6-4547-4960-aeaf-bac96e64fb2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51125813 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.51125813
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.2994958543
Short name T709
Test name
Test status
Simulation time 69940114 ps
CPU time 1.46 seconds
Started Jul 20 06:51:40 PM PDT 24
Finished Jul 20 06:51:44 PM PDT 24
Peak memory 217676 kb
Host smart-1dd07e28-daa8-4876-b5e3-676433d46553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994958543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.2994958543
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.2399743930
Short name T21
Test name
Test status
Simulation time 94543741 ps
CPU time 1.58 seconds
Started Jul 20 06:51:39 PM PDT 24
Finished Jul 20 06:51:43 PM PDT 24
Peak memory 218764 kb
Host smart-2bb2c886-507b-4a65-8031-7d3c4fb4ad16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399743930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.2399743930
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.777128057
Short name T346
Test name
Test status
Simulation time 54671958 ps
CPU time 0.99 seconds
Started Jul 20 06:51:40 PM PDT 24
Finished Jul 20 06:51:44 PM PDT 24
Peak memory 217612 kb
Host smart-34f207a1-c8de-4552-9012-b16de08639c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777128057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.777128057
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.2097332826
Short name T531
Test name
Test status
Simulation time 144364548 ps
CPU time 1.1 seconds
Started Jul 20 06:51:48 PM PDT 24
Finished Jul 20 06:51:49 PM PDT 24
Peak memory 217608 kb
Host smart-049a251d-62a3-434a-8268-28975d551a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097332826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.2097332826
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.859827974
Short name T508
Test name
Test status
Simulation time 47555797 ps
CPU time 1.24 seconds
Started Jul 20 06:51:42 PM PDT 24
Finished Jul 20 06:51:45 PM PDT 24
Peak memory 220204 kb
Host smart-10f29ef4-74ac-472a-b745-92e8482fb255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859827974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.859827974
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.3686847557
Short name T321
Test name
Test status
Simulation time 56194769 ps
CPU time 2.19 seconds
Started Jul 20 06:51:41 PM PDT 24
Finished Jul 20 06:51:46 PM PDT 24
Peak memory 219644 kb
Host smart-f419e99c-db4b-4de3-a956-f42c7edace49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686847557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3686847557
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.1331368268
Short name T829
Test name
Test status
Simulation time 56581711 ps
CPU time 1.22 seconds
Started Jul 20 06:51:42 PM PDT 24
Finished Jul 20 06:51:45 PM PDT 24
Peak memory 215500 kb
Host smart-6a2125d1-5499-4b09-9d9b-1f8163eb2ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331368268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.1331368268
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.2992097760
Short name T954
Test name
Test status
Simulation time 185839483 ps
CPU time 1.71 seconds
Started Jul 20 06:51:48 PM PDT 24
Finished Jul 20 06:51:50 PM PDT 24
Peak memory 219020 kb
Host smart-cec77e9f-e4d6-4b5b-9c6f-7c55bff44933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992097760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.2992097760
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.2181067700
Short name T656
Test name
Test status
Simulation time 92186886 ps
CPU time 1.28 seconds
Started Jul 20 06:51:42 PM PDT 24
Finished Jul 20 06:51:45 PM PDT 24
Peak memory 218800 kb
Host smart-80d59b57-72d9-450d-b7ef-05432f4efa5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181067700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.2181067700
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.1449149687
Short name T453
Test name
Test status
Simulation time 38934673 ps
CPU time 1.11 seconds
Started Jul 20 06:51:40 PM PDT 24
Finished Jul 20 06:51:43 PM PDT 24
Peak memory 218708 kb
Host smart-400134b7-bef2-4cc6-a0e8-94437192bc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449149687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1449149687
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.2066630018
Short name T138
Test name
Test status
Simulation time 36646530 ps
CPU time 1.16 seconds
Started Jul 20 06:49:50 PM PDT 24
Finished Jul 20 06:49:53 PM PDT 24
Peak memory 220168 kb
Host smart-30ea1e81-8152-4751-b1b1-545e8fcd3c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066630018 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.2066630018
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.900016583
Short name T746
Test name
Test status
Simulation time 18964892 ps
CPU time 0.85 seconds
Started Jul 20 06:49:53 PM PDT 24
Finished Jul 20 06:49:55 PM PDT 24
Peak memory 206612 kb
Host smart-0219a939-1c7b-40bb-b6a5-8c210375f08a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900016583 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.900016583
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.2811518679
Short name T120
Test name
Test status
Simulation time 57143994 ps
CPU time 1.2 seconds
Started Jul 20 06:49:53 PM PDT 24
Finished Jul 20 06:49:56 PM PDT 24
Peak memory 217212 kb
Host smart-00aebed2-f0c8-4b6e-af02-c02bb0deb4d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811518679 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.2811518679
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.1365670671
Short name T180
Test name
Test status
Simulation time 19457216 ps
CPU time 1.22 seconds
Started Jul 20 06:49:50 PM PDT 24
Finished Jul 20 06:49:53 PM PDT 24
Peak memory 224260 kb
Host smart-2be8005a-eeba-43d2-9c89-723c6eed545d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365670671 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.1365670671
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.1921368812
Short name T319
Test name
Test status
Simulation time 81329171 ps
CPU time 1.44 seconds
Started Jul 20 06:49:53 PM PDT 24
Finished Jul 20 06:49:56 PM PDT 24
Peak memory 219212 kb
Host smart-e7f82cac-771c-4077-babb-22c767910ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921368812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.1921368812
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.697176126
Short name T667
Test name
Test status
Simulation time 22475990 ps
CPU time 1.14 seconds
Started Jul 20 06:49:52 PM PDT 24
Finished Jul 20 06:49:55 PM PDT 24
Peak memory 216068 kb
Host smart-6ac18e0a-230e-4713-88b4-15277475ff9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697176126 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.697176126
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.3164291127
Short name T239
Test name
Test status
Simulation time 30522561 ps
CPU time 1 seconds
Started Jul 20 06:49:51 PM PDT 24
Finished Jul 20 06:49:53 PM PDT 24
Peak memory 215508 kb
Host smart-4194f633-eee5-4e11-9d2f-41fb32892ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164291127 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.3164291127
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.3524506537
Short name T102
Test name
Test status
Simulation time 37738999 ps
CPU time 1.31 seconds
Started Jul 20 06:49:57 PM PDT 24
Finished Jul 20 06:50:00 PM PDT 24
Peak memory 215544 kb
Host smart-f550793b-359c-4c52-a6e3-bc10bc068391
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524506537 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.3524506537
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.3408257663
Short name T669
Test name
Test status
Simulation time 70263447925 ps
CPU time 681.15 seconds
Started Jul 20 06:49:49 PM PDT 24
Finished Jul 20 07:01:12 PM PDT 24
Peak memory 220128 kb
Host smart-4a71c949-3945-492e-ab6b-34407f6cdd16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408257663 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.3408257663
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.2101003113
Short name T329
Test name
Test status
Simulation time 82611055 ps
CPU time 1.88 seconds
Started Jul 20 06:51:41 PM PDT 24
Finished Jul 20 06:51:45 PM PDT 24
Peak memory 220308 kb
Host smart-dcfb99b5-3a0d-4a9a-8dc3-ba919b348632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101003113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.2101003113
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.1490764925
Short name T540
Test name
Test status
Simulation time 47488043 ps
CPU time 1.17 seconds
Started Jul 20 06:51:40 PM PDT 24
Finished Jul 20 06:51:43 PM PDT 24
Peak memory 218636 kb
Host smart-f8c28f46-3cdb-481f-ac6a-4c5dc4a75303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490764925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.1490764925
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.1156552823
Short name T311
Test name
Test status
Simulation time 114685226 ps
CPU time 2.68 seconds
Started Jul 20 06:51:40 PM PDT 24
Finished Jul 20 06:51:46 PM PDT 24
Peak memory 220432 kb
Host smart-408e728a-9fa8-42ad-b1f6-8510f25471f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156552823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.1156552823
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.1770676785
Short name T949
Test name
Test status
Simulation time 34666712 ps
CPU time 1.37 seconds
Started Jul 20 06:51:44 PM PDT 24
Finished Jul 20 06:51:47 PM PDT 24
Peak memory 220236 kb
Host smart-be19804f-b9ad-4bda-8d07-071f64d1e675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770676785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.1770676785
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.995147594
Short name T359
Test name
Test status
Simulation time 29331477 ps
CPU time 1.28 seconds
Started Jul 20 06:51:44 PM PDT 24
Finished Jul 20 06:51:46 PM PDT 24
Peak memory 218856 kb
Host smart-56e4bb12-5b52-4df1-8a30-7775db762c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995147594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.995147594
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.3453098395
Short name T986
Test name
Test status
Simulation time 46910838 ps
CPU time 1.5 seconds
Started Jul 20 06:51:40 PM PDT 24
Finished Jul 20 06:51:44 PM PDT 24
Peak memory 218668 kb
Host smart-ced85489-fd72-4d41-aa52-ce0039c9e14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453098395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.3453098395
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.2333989197
Short name T811
Test name
Test status
Simulation time 29607987 ps
CPU time 1.36 seconds
Started Jul 20 06:51:43 PM PDT 24
Finished Jul 20 06:51:46 PM PDT 24
Peak memory 218736 kb
Host smart-8c663b41-3756-476c-9919-d3e9dee1a2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333989197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.2333989197
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.1062934944
Short name T303
Test name
Test status
Simulation time 73893824 ps
CPU time 1.27 seconds
Started Jul 20 06:51:40 PM PDT 24
Finished Jul 20 06:51:44 PM PDT 24
Peak memory 219236 kb
Host smart-3e7ffb29-99b2-497d-b4fd-a49c053bb21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062934944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1062934944
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.2588639991
Short name T892
Test name
Test status
Simulation time 72991425 ps
CPU time 1.42 seconds
Started Jul 20 06:51:40 PM PDT 24
Finished Jul 20 06:51:44 PM PDT 24
Peak memory 220176 kb
Host smart-703868ef-acf8-4d5d-be9b-0b9c5311864e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588639991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.2588639991
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.3279125815
Short name T845
Test name
Test status
Simulation time 48521761 ps
CPU time 1.38 seconds
Started Jul 20 06:51:41 PM PDT 24
Finished Jul 20 06:51:45 PM PDT 24
Peak memory 218724 kb
Host smart-5de4dbfd-a0d5-4908-908e-ad30214dc68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279125815 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3279125815
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.1430213938
Short name T136
Test name
Test status
Simulation time 24224367 ps
CPU time 1.23 seconds
Started Jul 20 06:49:05 PM PDT 24
Finished Jul 20 06:49:08 PM PDT 24
Peak memory 220188 kb
Host smart-d085c6d3-49fd-4410-8a7a-c565bb967dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430213938 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.1430213938
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.2672316966
Short name T935
Test name
Test status
Simulation time 16305559 ps
CPU time 0.91 seconds
Started Jul 20 06:49:06 PM PDT 24
Finished Jul 20 06:49:09 PM PDT 24
Peak memory 207096 kb
Host smart-2934ce45-070a-4cbf-98d1-d078bac65a47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672316966 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2672316966
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.665483230
Short name T70
Test name
Test status
Simulation time 59643176 ps
CPU time 1.1 seconds
Started Jul 20 06:49:07 PM PDT 24
Finished Jul 20 06:49:10 PM PDT 24
Peak memory 218904 kb
Host smart-160c6732-95ed-4162-92a9-3da24db6cf0b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665483230 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_dis
able_auto_req_mode.665483230
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.326841677
Short name T857
Test name
Test status
Simulation time 19984845 ps
CPU time 1.1 seconds
Started Jul 20 06:49:10 PM PDT 24
Finished Jul 20 06:49:12 PM PDT 24
Peak memory 218984 kb
Host smart-db3c4cbb-c921-4ec4-b1f7-f3a427bd451c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326841677 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.326841677
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.3857358058
Short name T476
Test name
Test status
Simulation time 48985706 ps
CPU time 1.28 seconds
Started Jul 20 06:49:05 PM PDT 24
Finished Jul 20 06:49:09 PM PDT 24
Peak memory 217784 kb
Host smart-2cca7eda-5795-4f29-8d4b-79d3562fb947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857358058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.3857358058
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.2304588796
Short name T408
Test name
Test status
Simulation time 26708443 ps
CPU time 1.12 seconds
Started Jul 20 06:49:07 PM PDT 24
Finished Jul 20 06:49:10 PM PDT 24
Peak memory 224416 kb
Host smart-bff6dc77-0c0e-4f2e-b312-3e9bb04c8a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304588796 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.2304588796
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_sec_cm.3789563547
Short name T19
Test name
Test status
Simulation time 1859782824 ps
CPU time 7.32 seconds
Started Jul 20 06:49:04 PM PDT 24
Finished Jul 20 06:49:14 PM PDT 24
Peak memory 236420 kb
Host smart-1deab9e2-7203-410b-bc82-58b10225dcfd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789563547 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.3789563547
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.615953898
Short name T737
Test name
Test status
Simulation time 95569828 ps
CPU time 0.93 seconds
Started Jul 20 06:49:04 PM PDT 24
Finished Jul 20 06:49:06 PM PDT 24
Peak memory 215360 kb
Host smart-fff9bbaa-07eb-4836-9b0a-40bbc8f0ce0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615953898 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.615953898
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.1569025535
Short name T567
Test name
Test status
Simulation time 1920330004 ps
CPU time 5.72 seconds
Started Jul 20 06:49:05 PM PDT 24
Finished Jul 20 06:49:13 PM PDT 24
Peak memory 217340 kb
Host smart-8f8fa0a5-b926-4d41-b8c6-95119436135f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569025535 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1569025535
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2668503177
Short name T897
Test name
Test status
Simulation time 39069081745 ps
CPU time 871.02 seconds
Started Jul 20 06:49:04 PM PDT 24
Finished Jul 20 07:03:36 PM PDT 24
Peak memory 217960 kb
Host smart-6233f2ce-2739-44b0-90a1-a43f390118bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668503177 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.2668503177
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.1735486740
Short name T641
Test name
Test status
Simulation time 44109265 ps
CPU time 1.25 seconds
Started Jul 20 06:49:50 PM PDT 24
Finished Jul 20 06:49:53 PM PDT 24
Peak memory 218984 kb
Host smart-d23138f4-aaa1-458e-9ff8-4afa9a5a69f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735486740 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1735486740
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.3747028392
Short name T991
Test name
Test status
Simulation time 21725661 ps
CPU time 0.9 seconds
Started Jul 20 06:50:00 PM PDT 24
Finished Jul 20 06:50:03 PM PDT 24
Peak memory 215040 kb
Host smart-21b042fd-6bc2-4f76-9c63-872c7ab8b54a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747028392 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3747028392
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.2046446103
Short name T916
Test name
Test status
Simulation time 29820277 ps
CPU time 1.14 seconds
Started Jul 20 06:50:00 PM PDT 24
Finished Jul 20 06:50:03 PM PDT 24
Peak memory 217176 kb
Host smart-491f26bb-1033-446f-900e-62f11b466b85
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046446103 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.2046446103
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.2460143712
Short name T169
Test name
Test status
Simulation time 116717172 ps
CPU time 1.01 seconds
Started Jul 20 06:49:54 PM PDT 24
Finished Jul 20 06:49:56 PM PDT 24
Peak memory 224100 kb
Host smart-3de90cf9-3e1d-4bd6-8d61-bd86d73ae264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460143712 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.2460143712
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.2320438088
Short name T783
Test name
Test status
Simulation time 143047433 ps
CPU time 1.56 seconds
Started Jul 20 06:49:50 PM PDT 24
Finished Jul 20 06:49:53 PM PDT 24
Peak memory 219048 kb
Host smart-070c8306-272b-430d-b208-7ff6c1b7e052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320438088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.2320438088
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.2122332130
Short name T786
Test name
Test status
Simulation time 27382845 ps
CPU time 0.88 seconds
Started Jul 20 06:49:48 PM PDT 24
Finished Jul 20 06:49:50 PM PDT 24
Peak memory 216028 kb
Host smart-c00340bf-e08e-4076-aae8-914cdb88c0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122332130 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2122332130
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.808209233
Short name T849
Test name
Test status
Simulation time 19041626 ps
CPU time 1.03 seconds
Started Jul 20 06:49:55 PM PDT 24
Finished Jul 20 06:49:57 PM PDT 24
Peak memory 215532 kb
Host smart-7aaec807-1297-4608-91f4-b3ef462eb722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808209233 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.808209233
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.3247551355
Short name T242
Test name
Test status
Simulation time 23034430 ps
CPU time 1.08 seconds
Started Jul 20 06:49:50 PM PDT 24
Finished Jul 20 06:49:52 PM PDT 24
Peak memory 206740 kb
Host smart-ab160f2d-072e-40ad-994e-680a25daad2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247551355 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.3247551355
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.3767056041
Short name T978
Test name
Test status
Simulation time 25638615261 ps
CPU time 605.83 seconds
Started Jul 20 06:49:47 PM PDT 24
Finished Jul 20 06:59:54 PM PDT 24
Peak memory 223944 kb
Host smart-7ab8cdcc-32ae-488a-a56d-9c07441b4f40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767056041 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.3767056041
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.698225149
Short name T110
Test name
Test status
Simulation time 24427355 ps
CPU time 1.19 seconds
Started Jul 20 06:49:58 PM PDT 24
Finished Jul 20 06:50:01 PM PDT 24
Peak memory 220488 kb
Host smart-1d1e451d-65ee-4ed8-8b8c-7266a3a49028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698225149 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.698225149
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.3020576076
Short name T430
Test name
Test status
Simulation time 49772809 ps
CPU time 0.93 seconds
Started Jul 20 06:49:59 PM PDT 24
Finished Jul 20 06:50:01 PM PDT 24
Peak memory 215248 kb
Host smart-bb0c8538-d89d-4917-b4de-eecd402ee72e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020576076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3020576076
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.992997284
Short name T202
Test name
Test status
Simulation time 161938465 ps
CPU time 0.89 seconds
Started Jul 20 06:50:00 PM PDT 24
Finished Jul 20 06:50:03 PM PDT 24
Peak memory 216480 kb
Host smart-597ed07e-fb3d-4658-8ac0-6e0dcc457550
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992997284 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.992997284
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.1041168184
Short name T152
Test name
Test status
Simulation time 31375077 ps
CPU time 1.19 seconds
Started Jul 20 06:50:04 PM PDT 24
Finished Jul 20 06:50:06 PM PDT 24
Peak memory 217188 kb
Host smart-378152bb-4460-4115-b221-96efb92b9962
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041168184 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.1041168184
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.2857888585
Short name T512
Test name
Test status
Simulation time 43303239 ps
CPU time 0.89 seconds
Started Jul 20 06:50:02 PM PDT 24
Finished Jul 20 06:50:04 PM PDT 24
Peak memory 218608 kb
Host smart-b2b6d1b0-c20c-44d6-9b6d-0df3f9b030e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857888585 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.2857888585
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.277331300
Short name T719
Test name
Test status
Simulation time 73126077 ps
CPU time 1.63 seconds
Started Jul 20 06:49:57 PM PDT 24
Finished Jul 20 06:50:00 PM PDT 24
Peak memory 220288 kb
Host smart-dfaca4cb-b799-402f-a237-ecc664d4917d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277331300 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.277331300
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.1886192180
Short name T859
Test name
Test status
Simulation time 27434672 ps
CPU time 0.98 seconds
Started Jul 20 06:50:07 PM PDT 24
Finished Jul 20 06:50:10 PM PDT 24
Peak memory 215732 kb
Host smart-250c4ed8-6b2e-4578-a3d0-99314f044ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886192180 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.1886192180
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.1532790098
Short name T429
Test name
Test status
Simulation time 29887929 ps
CPU time 0.94 seconds
Started Jul 20 06:50:06 PM PDT 24
Finished Jul 20 06:50:07 PM PDT 24
Peak memory 215544 kb
Host smart-5b3f554f-b0df-4615-8d71-f381ee8ff3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532790098 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.1532790098
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.1293482490
Short name T679
Test name
Test status
Simulation time 519690015 ps
CPU time 5.68 seconds
Started Jul 20 06:49:57 PM PDT 24
Finished Jul 20 06:50:04 PM PDT 24
Peak memory 217568 kb
Host smart-b02ae472-49a1-4c48-bf98-7ba38aeae416
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293482490 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1293482490
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.296337028
Short name T642
Test name
Test status
Simulation time 21437878537 ps
CPU time 274.22 seconds
Started Jul 20 06:50:00 PM PDT 24
Finished Jul 20 06:54:36 PM PDT 24
Peak memory 223704 kb
Host smart-fdac05b4-ebd5-40d5-9cd0-66e6085aefe3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296337028 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.296337028
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.856811555
Short name T889
Test name
Test status
Simulation time 101149932 ps
CPU time 1.19 seconds
Started Jul 20 06:50:02 PM PDT 24
Finished Jul 20 06:50:04 PM PDT 24
Peak memory 220092 kb
Host smart-470ae24b-826f-4b8b-8d20-25ef439d1978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856811555 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.856811555
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.294480672
Short name T604
Test name
Test status
Simulation time 35911434 ps
CPU time 0.78 seconds
Started Jul 20 06:49:59 PM PDT 24
Finished Jul 20 06:50:02 PM PDT 24
Peak memory 206692 kb
Host smart-1a4fe936-d128-4c1e-baf4-72a393dc7420
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294480672 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.294480672
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.3233322341
Short name T93
Test name
Test status
Simulation time 13379335 ps
CPU time 0.92 seconds
Started Jul 20 06:49:57 PM PDT 24
Finished Jul 20 06:50:00 PM PDT 24
Peak memory 216776 kb
Host smart-3188c410-c2b9-4e7c-8c3b-3fc3567475ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233322341 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3233322341
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.3276563300
Short name T808
Test name
Test status
Simulation time 36260079 ps
CPU time 1.26 seconds
Started Jul 20 06:50:02 PM PDT 24
Finished Jul 20 06:50:04 PM PDT 24
Peak memory 216976 kb
Host smart-216461ff-eadf-4a57-ac08-ae83878ef402
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276563300 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.3276563300
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.730497309
Short name T151
Test name
Test status
Simulation time 28112082 ps
CPU time 1.28 seconds
Started Jul 20 06:49:58 PM PDT 24
Finished Jul 20 06:50:01 PM PDT 24
Peak memory 221036 kb
Host smart-c5914bd9-9a9b-4383-832a-3a95fb068aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730497309 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.730497309
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.506886721
Short name T327
Test name
Test status
Simulation time 94216804 ps
CPU time 1.01 seconds
Started Jul 20 06:50:06 PM PDT 24
Finished Jul 20 06:50:08 PM PDT 24
Peak memory 217768 kb
Host smart-3f1164fd-fb03-4a98-9cd0-f0696a5588b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506886721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.506886721
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.2400686112
Short name T927
Test name
Test status
Simulation time 26826065 ps
CPU time 0.97 seconds
Started Jul 20 06:50:04 PM PDT 24
Finished Jul 20 06:50:06 PM PDT 24
Peak memory 215880 kb
Host smart-82efdc66-38a4-4e08-af7a-2d55fa93792c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400686112 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.2400686112
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.334204551
Short name T827
Test name
Test status
Simulation time 20559070 ps
CPU time 1.01 seconds
Started Jul 20 06:49:57 PM PDT 24
Finished Jul 20 06:50:00 PM PDT 24
Peak memory 215544 kb
Host smart-95f87ba9-a965-4c23-93b9-fa0f00843d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334204551 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.334204551
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.3590591407
Short name T863
Test name
Test status
Simulation time 61639996 ps
CPU time 1.4 seconds
Started Jul 20 06:50:01 PM PDT 24
Finished Jul 20 06:50:03 PM PDT 24
Peak memory 215608 kb
Host smart-d80dace1-dd72-487f-ba2a-10127e820517
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590591407 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.3590591407
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1986965222
Short name T57
Test name
Test status
Simulation time 48671031719 ps
CPU time 1073.04 seconds
Started Jul 20 06:50:00 PM PDT 24
Finished Jul 20 07:07:55 PM PDT 24
Peak memory 223940 kb
Host smart-f2391d46-3c87-45ef-8ff3-b130f536ce31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986965222 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1986965222
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.1118508416
Short name T758
Test name
Test status
Simulation time 92298587 ps
CPU time 1.32 seconds
Started Jul 20 06:49:57 PM PDT 24
Finished Jul 20 06:50:00 PM PDT 24
Peak memory 218860 kb
Host smart-697f20f3-0148-4da7-87f0-a39d62cfb04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118508416 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.1118508416
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.184118476
Short name T984
Test name
Test status
Simulation time 14813752 ps
CPU time 0.94 seconds
Started Jul 20 06:50:05 PM PDT 24
Finished Jul 20 06:50:06 PM PDT 24
Peak memory 207028 kb
Host smart-9d227c40-0430-4f89-aad8-43fe1971fe0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184118476 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.184118476
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.2235243710
Short name T802
Test name
Test status
Simulation time 98586535 ps
CPU time 1.08 seconds
Started Jul 20 06:50:00 PM PDT 24
Finished Jul 20 06:50:02 PM PDT 24
Peak memory 217044 kb
Host smart-79597c29-2a3d-4baf-885a-9a7d097f4d13
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235243710 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.2235243710
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.2649443075
Short name T61
Test name
Test status
Simulation time 20261010 ps
CPU time 1.19 seconds
Started Jul 20 06:50:00 PM PDT 24
Finished Jul 20 06:50:03 PM PDT 24
Peak memory 218732 kb
Host smart-79514e1c-b3ed-4192-8037-c68e3f9d550a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649443075 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.2649443075
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_intr.2460499533
Short name T588
Test name
Test status
Simulation time 21498865 ps
CPU time 1.16 seconds
Started Jul 20 06:49:59 PM PDT 24
Finished Jul 20 06:50:02 PM PDT 24
Peak memory 216252 kb
Host smart-3d68d934-17d0-4bec-ab01-6e620677413e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460499533 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.2460499533
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.3880629260
Short name T419
Test name
Test status
Simulation time 16715002 ps
CPU time 1.01 seconds
Started Jul 20 06:49:59 PM PDT 24
Finished Jul 20 06:50:01 PM PDT 24
Peak memory 215668 kb
Host smart-ec3c283b-7c05-419d-98d2-cac48dfff75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880629260 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.3880629260
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.776634902
Short name T757
Test name
Test status
Simulation time 389768067 ps
CPU time 4.21 seconds
Started Jul 20 06:49:57 PM PDT 24
Finished Jul 20 06:50:02 PM PDT 24
Peak memory 217636 kb
Host smart-5c4e9aa0-a13f-4dca-a935-e58be30e5a0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776634902 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.776634902
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.4076508780
Short name T894
Test name
Test status
Simulation time 28039603477 ps
CPU time 187.55 seconds
Started Jul 20 06:49:57 PM PDT 24
Finished Jul 20 06:53:06 PM PDT 24
Peak memory 218536 kb
Host smart-cb3dde81-c81a-4e48-b3f4-0ee8870bdc78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076508780 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.4076508780
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.97332771
Short name T903
Test name
Test status
Simulation time 46069120 ps
CPU time 1.12 seconds
Started Jul 20 06:49:57 PM PDT 24
Finished Jul 20 06:50:00 PM PDT 24
Peak memory 219820 kb
Host smart-77e0b321-60a1-4e01-8b9a-66cd26ecd37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97332771 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.97332771
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.3001980913
Short name T787
Test name
Test status
Simulation time 14684476 ps
CPU time 0.95 seconds
Started Jul 20 06:49:56 PM PDT 24
Finished Jul 20 06:49:58 PM PDT 24
Peak memory 215212 kb
Host smart-45378b9d-ed6f-4420-93b8-9c62e582232c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001980913 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.3001980913
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.413671089
Short name T160
Test name
Test status
Simulation time 63914036 ps
CPU time 0.85 seconds
Started Jul 20 06:49:56 PM PDT 24
Finished Jul 20 06:49:58 PM PDT 24
Peak memory 215684 kb
Host smart-4b39f569-7196-4d16-9c03-b5930d782e44
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413671089 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.413671089
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.1020993624
Short name T153
Test name
Test status
Simulation time 45998915 ps
CPU time 1.14 seconds
Started Jul 20 06:49:57 PM PDT 24
Finished Jul 20 06:49:59 PM PDT 24
Peak memory 217152 kb
Host smart-36a8abb5-014b-4684-942c-5a77abf51617
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020993624 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.1020993624
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.4278526782
Short name T208
Test name
Test status
Simulation time 29504799 ps
CPU time 1.22 seconds
Started Jul 20 06:49:59 PM PDT 24
Finished Jul 20 06:50:03 PM PDT 24
Peak memory 219840 kb
Host smart-18439d59-ea04-4911-816e-bd586032e44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278526782 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.4278526782
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.2193511972
Short name T834
Test name
Test status
Simulation time 153694207 ps
CPU time 1.28 seconds
Started Jul 20 06:49:56 PM PDT 24
Finished Jul 20 06:49:59 PM PDT 24
Peak memory 220224 kb
Host smart-c0c2db1e-f709-48e8-a19d-98e760b008fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193511972 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.2193511972
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.1848384421
Short name T33
Test name
Test status
Simulation time 24877137 ps
CPU time 0.94 seconds
Started Jul 20 06:49:59 PM PDT 24
Finished Jul 20 06:50:02 PM PDT 24
Peak memory 216116 kb
Host smart-787c2796-08dd-4433-809d-cdd7401146ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848384421 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1848384421
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.1175928774
Short name T493
Test name
Test status
Simulation time 34354422 ps
CPU time 0.88 seconds
Started Jul 20 06:49:59 PM PDT 24
Finished Jul 20 06:50:01 PM PDT 24
Peak memory 215544 kb
Host smart-d7181066-7dc4-408d-a0f9-fe6cfc397086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175928774 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.1175928774
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.3271254790
Short name T456
Test name
Test status
Simulation time 189489205 ps
CPU time 4.09 seconds
Started Jul 20 06:50:05 PM PDT 24
Finished Jul 20 06:50:10 PM PDT 24
Peak memory 218760 kb
Host smart-988c0a27-28c5-4339-8245-3a2ec6c65a64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271254790 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3271254790
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.1742895141
Short name T868
Test name
Test status
Simulation time 28587602552 ps
CPU time 548.23 seconds
Started Jul 20 06:49:59 PM PDT 24
Finished Jul 20 06:59:09 PM PDT 24
Peak memory 218644 kb
Host smart-082aaf84-db4c-4cda-8a88-6a77db1f5363
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742895141 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.1742895141
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.1563109790
Short name T664
Test name
Test status
Simulation time 25098207 ps
CPU time 1.22 seconds
Started Jul 20 06:49:56 PM PDT 24
Finished Jul 20 06:49:59 PM PDT 24
Peak memory 220360 kb
Host smart-69ee15a8-662e-4817-a332-bbe120476b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563109790 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.1563109790
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.1058933264
Short name T449
Test name
Test status
Simulation time 24283379 ps
CPU time 0.88 seconds
Started Jul 20 06:50:00 PM PDT 24
Finished Jul 20 06:50:02 PM PDT 24
Peak memory 207016 kb
Host smart-d3fa56a4-fc6d-4989-8ff1-8c7fb15dcf34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058933264 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1058933264
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.1320095725
Short name T821
Test name
Test status
Simulation time 49015088 ps
CPU time 0.87 seconds
Started Jul 20 06:49:56 PM PDT 24
Finished Jul 20 06:49:59 PM PDT 24
Peak memory 216592 kb
Host smart-4cebb43f-f535-4277-afac-9901de10d2fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320095725 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1320095725
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.3773228507
Short name T125
Test name
Test status
Simulation time 94846922 ps
CPU time 1.34 seconds
Started Jul 20 06:50:03 PM PDT 24
Finished Jul 20 06:50:05 PM PDT 24
Peak memory 217180 kb
Host smart-62e66e8f-efb1-4c98-a762-9bc29feb35b0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773228507 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.3773228507
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.796379991
Short name T167
Test name
Test status
Simulation time 100736151 ps
CPU time 1.04 seconds
Started Jul 20 06:50:06 PM PDT 24
Finished Jul 20 06:50:08 PM PDT 24
Peak memory 219812 kb
Host smart-8a7108ef-8397-4b49-b8a6-304258c00692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796379991 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.796379991
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.4016048519
Short name T888
Test name
Test status
Simulation time 51951673 ps
CPU time 1.25 seconds
Started Jul 20 06:50:01 PM PDT 24
Finished Jul 20 06:50:03 PM PDT 24
Peak memory 217620 kb
Host smart-114fd5ce-44e5-4828-bcae-d092c0cb0e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016048519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.4016048519
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.2621442864
Short name T918
Test name
Test status
Simulation time 22765241 ps
CPU time 1.15 seconds
Started Jul 20 06:50:04 PM PDT 24
Finished Jul 20 06:50:06 PM PDT 24
Peak memory 216192 kb
Host smart-ee1b6171-7b3d-484c-9ba4-406fef4411c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621442864 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.2621442864
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.2147646508
Short name T348
Test name
Test status
Simulation time 28155048 ps
CPU time 0.97 seconds
Started Jul 20 06:49:58 PM PDT 24
Finished Jul 20 06:50:00 PM PDT 24
Peak memory 215540 kb
Host smart-57527ce1-21ea-48fd-aafe-b2613360dc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147646508 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.2147646508
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.3479014969
Short name T49
Test name
Test status
Simulation time 228597423 ps
CPU time 4.73 seconds
Started Jul 20 06:50:01 PM PDT 24
Finished Jul 20 06:50:07 PM PDT 24
Peak memory 217652 kb
Host smart-064043fe-b15a-4cc4-a62e-991801cd446e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479014969 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.3479014969
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.2746155567
Short name T769
Test name
Test status
Simulation time 28313511755 ps
CPU time 528.31 seconds
Started Jul 20 06:49:59 PM PDT 24
Finished Jul 20 06:58:50 PM PDT 24
Peak memory 218056 kb
Host smart-6efc7f8f-adaf-45e7-9b22-5aaf00cf27a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746155567 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.2746155567
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.3179224223
Short name T406
Test name
Test status
Simulation time 28048501 ps
CPU time 1.22 seconds
Started Jul 20 06:50:07 PM PDT 24
Finished Jul 20 06:50:09 PM PDT 24
Peak memory 218992 kb
Host smart-5ee6e639-7b83-4a08-b6d4-fa76134b1eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179224223 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3179224223
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.455264231
Short name T342
Test name
Test status
Simulation time 23321628 ps
CPU time 0.9 seconds
Started Jul 20 06:50:08 PM PDT 24
Finished Jul 20 06:50:10 PM PDT 24
Peak memory 207068 kb
Host smart-ae230aa1-f070-4ec5-ab04-1994a3ec6873
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455264231 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.455264231
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.3897660660
Short name T409
Test name
Test status
Simulation time 10856632 ps
CPU time 0.89 seconds
Started Jul 20 06:50:07 PM PDT 24
Finished Jul 20 06:50:10 PM PDT 24
Peak memory 216116 kb
Host smart-296c6567-16ea-4ee6-aed7-ad5c70b0f5d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897660660 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3897660660
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.3114529682
Short name T421
Test name
Test status
Simulation time 52742870 ps
CPU time 1.06 seconds
Started Jul 20 06:50:06 PM PDT 24
Finished Jul 20 06:50:08 PM PDT 24
Peak memory 217260 kb
Host smart-98b61331-05c6-42a1-a1bc-5a9cbd6e24d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114529682 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.3114529682
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_genbits.2132400997
Short name T305
Test name
Test status
Simulation time 78861886 ps
CPU time 1.52 seconds
Started Jul 20 06:50:06 PM PDT 24
Finished Jul 20 06:50:08 PM PDT 24
Peak memory 219168 kb
Host smart-d759ed36-fdb4-4a1b-ad46-22a9c7d35ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132400997 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.2132400997
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.3345069762
Short name T443
Test name
Test status
Simulation time 22380017 ps
CPU time 1.24 seconds
Started Jul 20 06:50:09 PM PDT 24
Finished Jul 20 06:50:11 PM PDT 24
Peak memory 224472 kb
Host smart-8446cf83-7476-4858-93e0-1481e6c94884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345069762 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.3345069762
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.829457259
Short name T354
Test name
Test status
Simulation time 36343629 ps
CPU time 0.89 seconds
Started Jul 20 06:50:06 PM PDT 24
Finished Jul 20 06:50:08 PM PDT 24
Peak memory 215544 kb
Host smart-f4a4ac63-1716-447d-88ed-484aff14f4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829457259 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.829457259
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.2125586803
Short name T931
Test name
Test status
Simulation time 201059543 ps
CPU time 4.06 seconds
Started Jul 20 06:50:05 PM PDT 24
Finished Jul 20 06:50:10 PM PDT 24
Peak memory 215600 kb
Host smart-78a525db-3e48-48d1-8375-0e48b15f6164
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125586803 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.2125586803
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.1109939305
Short name T499
Test name
Test status
Simulation time 92047636679 ps
CPU time 268.6 seconds
Started Jul 20 06:50:08 PM PDT 24
Finished Jul 20 06:54:38 PM PDT 24
Peak memory 220324 kb
Host smart-327424cc-0bb3-4bcd-9753-386724bdd2a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109939305 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.1109939305
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert_test.1719431169
Short name T374
Test name
Test status
Simulation time 104443042 ps
CPU time 0.97 seconds
Started Jul 20 06:50:05 PM PDT 24
Finished Jul 20 06:50:06 PM PDT 24
Peak memory 207052 kb
Host smart-4728c576-8d9b-455f-ae1e-65f0447604bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719431169 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.1719431169
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.1675414328
Short name T966
Test name
Test status
Simulation time 13363678 ps
CPU time 0.87 seconds
Started Jul 20 06:50:13 PM PDT 24
Finished Jul 20 06:50:14 PM PDT 24
Peak memory 216356 kb
Host smart-a61ed909-302f-4980-a21f-eacf1e8943e4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675414328 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1675414328
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.1064524728
Short name T91
Test name
Test status
Simulation time 20174121 ps
CPU time 0.98 seconds
Started Jul 20 06:50:16 PM PDT 24
Finished Jul 20 06:50:20 PM PDT 24
Peak memory 217116 kb
Host smart-57e6948c-f614-408c-880d-cccb9f3a6cc0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064524728 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.1064524728
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.3404062599
Short name T732
Test name
Test status
Simulation time 58387823 ps
CPU time 1.09 seconds
Started Jul 20 06:50:18 PM PDT 24
Finished Jul 20 06:50:21 PM PDT 24
Peak memory 224308 kb
Host smart-822412d2-5269-4031-b1b3-1ef9cc1122cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404062599 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.3404062599
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.996531432
Short name T706
Test name
Test status
Simulation time 39247934 ps
CPU time 1.1 seconds
Started Jul 20 06:50:08 PM PDT 24
Finished Jul 20 06:50:11 PM PDT 24
Peak memory 217588 kb
Host smart-09f5ae4c-2985-4e65-a907-1e883a9c5ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996531432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.996531432
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.3246188562
Short name T798
Test name
Test status
Simulation time 26416381 ps
CPU time 1.14 seconds
Started Jul 20 06:50:07 PM PDT 24
Finished Jul 20 06:50:10 PM PDT 24
Peak memory 215780 kb
Host smart-4983b830-af3f-46b8-9eb2-6cf2912100e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246188562 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.3246188562
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.556462774
Short name T75
Test name
Test status
Simulation time 18419947 ps
CPU time 1.01 seconds
Started Jul 20 06:50:08 PM PDT 24
Finished Jul 20 06:50:10 PM PDT 24
Peak memory 215556 kb
Host smart-5b0e167a-d61c-4b54-85fe-38834ae7f74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556462774 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.556462774
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.885707625
Short name T201
Test name
Test status
Simulation time 1598166596 ps
CPU time 4.93 seconds
Started Jul 20 06:50:08 PM PDT 24
Finished Jul 20 06:50:14 PM PDT 24
Peak memory 215564 kb
Host smart-0b4c3126-d573-4192-9c7e-2e5a0a7d3ae0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885707625 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.885707625
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_alert.1195381875
Short name T26
Test name
Test status
Simulation time 27018356 ps
CPU time 1.22 seconds
Started Jul 20 06:50:08 PM PDT 24
Finished Jul 20 06:50:11 PM PDT 24
Peak memory 220320 kb
Host smart-6f41f81b-78c3-4e58-b775-886be8bde879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195381875 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.1195381875
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.60315617
Short name T394
Test name
Test status
Simulation time 22181669 ps
CPU time 1.08 seconds
Started Jul 20 06:50:07 PM PDT 24
Finished Jul 20 06:50:09 PM PDT 24
Peak memory 207088 kb
Host smart-0f559b18-9023-4596-9cdf-213b08009b02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60315617 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.60315617
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.2328943066
Short name T161
Test name
Test status
Simulation time 13454611 ps
CPU time 0.93 seconds
Started Jul 20 06:50:06 PM PDT 24
Finished Jul 20 06:50:08 PM PDT 24
Peak memory 215676 kb
Host smart-cd23ab61-e660-4c19-8462-40e00b80570e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328943066 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.2328943066
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.547005811
Short name T377
Test name
Test status
Simulation time 117837538 ps
CPU time 1.17 seconds
Started Jul 20 06:50:06 PM PDT 24
Finished Jul 20 06:50:08 PM PDT 24
Peak memory 218648 kb
Host smart-a0cf370e-7e13-4c34-a293-4491af9494b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547005811 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_di
sable_auto_req_mode.547005811
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.2772163140
Short name T196
Test name
Test status
Simulation time 44945087 ps
CPU time 0.87 seconds
Started Jul 20 06:50:08 PM PDT 24
Finished Jul 20 06:50:10 PM PDT 24
Peak memory 218640 kb
Host smart-b62192c1-2b64-4bad-b4b8-603bd9b7f856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772163140 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.2772163140
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.2552511420
Short name T514
Test name
Test status
Simulation time 155991574 ps
CPU time 2.59 seconds
Started Jul 20 06:50:06 PM PDT 24
Finished Jul 20 06:50:10 PM PDT 24
Peak memory 217768 kb
Host smart-6fd7adb3-d743-4d80-8974-ac9ac9f72870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552511420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2552511420
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.786263390
Short name T502
Test name
Test status
Simulation time 21510178 ps
CPU time 1.09 seconds
Started Jul 20 06:50:06 PM PDT 24
Finished Jul 20 06:50:08 PM PDT 24
Peak memory 215720 kb
Host smart-25f3d547-5533-4fb8-b5f5-4d7ff0f0cc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786263390 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.786263390
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1753005913
Short name T672
Test name
Test status
Simulation time 19084795 ps
CPU time 0.89 seconds
Started Jul 20 06:50:17 PM PDT 24
Finished Jul 20 06:50:20 PM PDT 24
Peak memory 215560 kb
Host smart-0517368a-1c27-4614-8e1e-aed0b631eddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753005913 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1753005913
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.1966844614
Short name T893
Test name
Test status
Simulation time 1598244978 ps
CPU time 5.34 seconds
Started Jul 20 06:50:07 PM PDT 24
Finished Jul 20 06:50:14 PM PDT 24
Peak memory 215560 kb
Host smart-f50e3198-b7c2-4765-9cba-eef626840d03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966844614 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.1966844614
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.1737395781
Short name T621
Test name
Test status
Simulation time 482132366338 ps
CPU time 2128.56 seconds
Started Jul 20 06:50:18 PM PDT 24
Finished Jul 20 07:25:49 PM PDT 24
Peak memory 230424 kb
Host smart-4a479197-418c-4310-91ab-87eab4002afd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737395781 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.1737395781
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.4085957697
Short name T219
Test name
Test status
Simulation time 24371523 ps
CPU time 1.28 seconds
Started Jul 20 06:50:08 PM PDT 24
Finished Jul 20 06:50:11 PM PDT 24
Peak memory 220320 kb
Host smart-b54c4bdf-e4d7-4d1f-916e-9c3697d421b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085957697 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.4085957697
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.3737227086
Short name T668
Test name
Test status
Simulation time 12462062 ps
CPU time 0.84 seconds
Started Jul 20 06:50:13 PM PDT 24
Finished Jul 20 06:50:14 PM PDT 24
Peak memory 207092 kb
Host smart-9abdb9c6-b13b-40ba-85d4-da04a1149fab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737227086 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3737227086
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.4028536794
Short name T335
Test name
Test status
Simulation time 50528628 ps
CPU time 1.11 seconds
Started Jul 20 06:50:16 PM PDT 24
Finished Jul 20 06:50:20 PM PDT 24
Peak memory 217132 kb
Host smart-2d9d391c-6d7a-4c0b-9d75-3d87049df7ed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028536794 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.4028536794
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.2958019508
Short name T577
Test name
Test status
Simulation time 23309763 ps
CPU time 1.17 seconds
Started Jul 20 06:50:08 PM PDT 24
Finished Jul 20 06:50:11 PM PDT 24
Peak memory 219032 kb
Host smart-dd1a3020-088c-475e-958a-ea120de9e8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958019508 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.2958019508
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.1397431652
Short name T607
Test name
Test status
Simulation time 176349392 ps
CPU time 2.55 seconds
Started Jul 20 06:50:07 PM PDT 24
Finished Jul 20 06:50:11 PM PDT 24
Peak memory 220484 kb
Host smart-5963ac16-4561-4b81-bb5c-49306f5e4fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397431652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1397431652
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.3408419778
Short name T427
Test name
Test status
Simulation time 33597644 ps
CPU time 0.99 seconds
Started Jul 20 06:50:08 PM PDT 24
Finished Jul 20 06:50:10 PM PDT 24
Peak memory 224440 kb
Host smart-9a7f0c57-e29e-4173-bd12-384008880a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408419778 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.3408419778
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.2324653420
Short name T392
Test name
Test status
Simulation time 23168910 ps
CPU time 0.92 seconds
Started Jul 20 06:50:08 PM PDT 24
Finished Jul 20 06:50:11 PM PDT 24
Peak memory 215568 kb
Host smart-97b8cdcd-1d9b-4cb7-bf35-7c61f90face1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324653420 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.2324653420
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.797028072
Short name T362
Test name
Test status
Simulation time 458471143 ps
CPU time 5.01 seconds
Started Jul 20 06:50:10 PM PDT 24
Finished Jul 20 06:50:16 PM PDT 24
Peak memory 217548 kb
Host smart-0bad8033-4e5d-418f-a3eb-e0ab1bb56a22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797028072 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.797028072
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.1640682179
Short name T516
Test name
Test status
Simulation time 35037280641 ps
CPU time 451.5 seconds
Started Jul 20 06:50:05 PM PDT 24
Finished Jul 20 06:57:37 PM PDT 24
Peak memory 217876 kb
Host smart-455db067-fb25-403d-af33-4d5bcd1316f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640682179 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.1640682179
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.423007822
Short name T549
Test name
Test status
Simulation time 108643094 ps
CPU time 1.16 seconds
Started Jul 20 06:49:07 PM PDT 24
Finished Jul 20 06:49:11 PM PDT 24
Peak memory 219512 kb
Host smart-ac578f01-82d6-480a-a6f4-d2bbec3d5b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423007822 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.423007822
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.3287383117
Short name T872
Test name
Test status
Simulation time 13873007 ps
CPU time 0.92 seconds
Started Jul 20 06:49:10 PM PDT 24
Finished Jul 20 06:49:12 PM PDT 24
Peak memory 207044 kb
Host smart-d12a9607-ea29-4afd-bf2a-77dc5d97912a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287383117 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.3287383117
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.157291859
Short name T223
Test name
Test status
Simulation time 11962547 ps
CPU time 0.88 seconds
Started Jul 20 06:49:07 PM PDT 24
Finished Jul 20 06:49:10 PM PDT 24
Peak memory 216584 kb
Host smart-06f722d5-331b-440f-9058-cf482d23ce17
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157291859 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.157291859
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.971374743
Short name T917
Test name
Test status
Simulation time 59745790 ps
CPU time 1.25 seconds
Started Jul 20 06:49:06 PM PDT 24
Finished Jul 20 06:49:10 PM PDT 24
Peak memory 217148 kb
Host smart-79794392-0600-41fb-bf80-dfded9b0a11b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971374743 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_dis
able_auto_req_mode.971374743
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.1109296264
Short name T606
Test name
Test status
Simulation time 23203049 ps
CPU time 1.06 seconds
Started Jul 20 06:49:07 PM PDT 24
Finished Jul 20 06:49:10 PM PDT 24
Peak memory 224256 kb
Host smart-ec403ea1-53e4-4ca9-91b0-8e5eab84803e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109296264 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.1109296264
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.430007790
Short name T482
Test name
Test status
Simulation time 77260779 ps
CPU time 1.18 seconds
Started Jul 20 06:49:06 PM PDT 24
Finished Jul 20 06:49:09 PM PDT 24
Peak memory 218844 kb
Host smart-fda66fe2-fdf4-437a-a30e-a0e701c58a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430007790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.430007790
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.1606310124
Short name T101
Test name
Test status
Simulation time 43625793 ps
CPU time 0.9 seconds
Started Jul 20 06:49:07 PM PDT 24
Finished Jul 20 06:49:10 PM PDT 24
Peak memory 215932 kb
Host smart-f83fc435-1509-4127-9f92-4260b7c50706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606310124 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.1606310124
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.459863989
Short name T713
Test name
Test status
Simulation time 18723502 ps
CPU time 1.05 seconds
Started Jul 20 06:49:05 PM PDT 24
Finished Jul 20 06:49:08 PM PDT 24
Peak memory 207336 kb
Host smart-857445c9-adbd-4bc4-aa53-d65286017408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459863989 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.459863989
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.1814972715
Short name T18
Test name
Test status
Simulation time 1972650397 ps
CPU time 7.88 seconds
Started Jul 20 06:49:07 PM PDT 24
Finished Jul 20 06:49:17 PM PDT 24
Peak memory 237744 kb
Host smart-b6b9878d-54e0-4702-9404-8321db3a14e7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814972715 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.1814972715
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.2210399062
Short name T884
Test name
Test status
Simulation time 49243425 ps
CPU time 0.97 seconds
Started Jul 20 06:49:07 PM PDT 24
Finished Jul 20 06:49:10 PM PDT 24
Peak memory 215544 kb
Host smart-0887eb60-24d9-4c06-9369-65f2174cfe2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210399062 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.2210399062
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1399558214
Short name T899
Test name
Test status
Simulation time 659424771 ps
CPU time 4.61 seconds
Started Jul 20 06:49:05 PM PDT 24
Finished Jul 20 06:49:11 PM PDT 24
Peak memory 217528 kb
Host smart-1b599497-a190-4332-9b92-7fd9bd7f218e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399558214 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1399558214
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2800311395
Short name T902
Test name
Test status
Simulation time 81985712771 ps
CPU time 929.63 seconds
Started Jul 20 06:49:06 PM PDT 24
Finished Jul 20 07:04:38 PM PDT 24
Peak memory 223936 kb
Host smart-cc6fd4fa-ae34-42bd-b15e-6221948edd83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800311395 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.2800311395
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.2807435164
Short name T469
Test name
Test status
Simulation time 97851994 ps
CPU time 1.25 seconds
Started Jul 20 06:50:27 PM PDT 24
Finished Jul 20 06:50:30 PM PDT 24
Peak memory 220896 kb
Host smart-b8cb8b4f-c92a-4e1d-b4a1-c5e3107a4b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807435164 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.2807435164
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.1390380113
Short name T454
Test name
Test status
Simulation time 60426991 ps
CPU time 0.89 seconds
Started Jul 20 06:50:14 PM PDT 24
Finished Jul 20 06:50:15 PM PDT 24
Peak memory 215132 kb
Host smart-564d469e-3ff2-476f-af5e-5f68a6a05e96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390380113 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1390380113
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.3721126771
Short name T583
Test name
Test status
Simulation time 13831832 ps
CPU time 0.88 seconds
Started Jul 20 06:50:15 PM PDT 24
Finished Jul 20 06:50:18 PM PDT 24
Peak memory 216176 kb
Host smart-5cdf8785-1547-494f-b872-f96dd94af983
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721126771 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.3721126771
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_err.628064083
Short name T959
Test name
Test status
Simulation time 124542770 ps
CPU time 1.14 seconds
Started Jul 20 06:50:18 PM PDT 24
Finished Jul 20 06:50:21 PM PDT 24
Peak memory 219092 kb
Host smart-7508abd5-7cfc-43db-88b5-5a1caebc04ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628064083 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.628064083
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_smoke.2678795671
Short name T523
Test name
Test status
Simulation time 26079362 ps
CPU time 0.9 seconds
Started Jul 20 06:50:13 PM PDT 24
Finished Jul 20 06:50:14 PM PDT 24
Peak memory 215544 kb
Host smart-0e7b1efb-0256-426b-a25e-0fc1bff34afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678795671 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.2678795671
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.3930402111
Short name T571
Test name
Test status
Simulation time 339278733 ps
CPU time 6.34 seconds
Started Jul 20 06:50:06 PM PDT 24
Finished Jul 20 06:50:14 PM PDT 24
Peak memory 215560 kb
Host smart-19706582-1643-41d6-9606-2208ec00c807
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930402111 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.3930402111
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.3080149933
Short name T227
Test name
Test status
Simulation time 87798519776 ps
CPU time 1038.17 seconds
Started Jul 20 06:50:14 PM PDT 24
Finished Jul 20 07:07:34 PM PDT 24
Peak memory 223972 kb
Host smart-c0b759a4-9085-4a4f-bb9c-abc8e3a5505a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080149933 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.3080149933
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.1201570181
Short name T284
Test name
Test status
Simulation time 26391537 ps
CPU time 1.23 seconds
Started Jul 20 06:50:14 PM PDT 24
Finished Jul 20 06:50:18 PM PDT 24
Peak memory 220348 kb
Host smart-2b32c804-ac22-4931-8226-5327f0a22cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201570181 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.1201570181
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.2013268425
Short name T332
Test name
Test status
Simulation time 33669115 ps
CPU time 0.95 seconds
Started Jul 20 06:50:16 PM PDT 24
Finished Jul 20 06:50:19 PM PDT 24
Peak memory 215396 kb
Host smart-cc05811f-317c-40d2-bb65-8ab3125772f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013268425 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2013268425
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.2369778604
Short name T211
Test name
Test status
Simulation time 23175489 ps
CPU time 0.93 seconds
Started Jul 20 06:50:15 PM PDT 24
Finished Jul 20 06:50:18 PM PDT 24
Peak memory 216692 kb
Host smart-8c35c9a0-13cf-4c57-bf7b-484a8f0c3c30
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369778604 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2369778604
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.1020727883
Short name T207
Test name
Test status
Simulation time 99505764 ps
CPU time 1.12 seconds
Started Jul 20 06:50:15 PM PDT 24
Finished Jul 20 06:50:18 PM PDT 24
Peak memory 217048 kb
Host smart-e99e203e-626b-4dee-be2f-ab79bb2b852c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020727883 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.1020727883
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.2023704314
Short name T116
Test name
Test status
Simulation time 35935762 ps
CPU time 1.15 seconds
Started Jul 20 06:50:16 PM PDT 24
Finished Jul 20 06:50:19 PM PDT 24
Peak memory 220748 kb
Host smart-10cdfdca-b33d-4749-adc5-23b9ee9ec363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023704314 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2023704314
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.706545510
Short name T240
Test name
Test status
Simulation time 96173625 ps
CPU time 1.18 seconds
Started Jul 20 06:50:14 PM PDT 24
Finished Jul 20 06:50:18 PM PDT 24
Peak memory 217584 kb
Host smart-57ae8996-7bf1-425f-8ad1-2128facb3a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706545510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.706545510
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.483645860
Short name T32
Test name
Test status
Simulation time 26619899 ps
CPU time 0.98 seconds
Started Jul 20 06:50:15 PM PDT 24
Finished Jul 20 06:50:18 PM PDT 24
Peak memory 216116 kb
Host smart-82e9d913-7cce-41ce-b84c-0d74a402b05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483645860 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.483645860
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.3188273667
Short name T379
Test name
Test status
Simulation time 71375534 ps
CPU time 0.87 seconds
Started Jul 20 06:50:16 PM PDT 24
Finished Jul 20 06:50:18 PM PDT 24
Peak memory 207192 kb
Host smart-ee685059-a8be-4064-8e1a-e10c91d51f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188273667 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.3188273667
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.1859292435
Short name T882
Test name
Test status
Simulation time 1267653574 ps
CPU time 4.24 seconds
Started Jul 20 06:50:18 PM PDT 24
Finished Jul 20 06:50:24 PM PDT 24
Peak memory 215628 kb
Host smart-8c40cd8a-e166-4665-ae99-b0dc816c9fa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859292435 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.1859292435
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.392079233
Short name T557
Test name
Test status
Simulation time 309988379546 ps
CPU time 1205.75 seconds
Started Jul 20 06:50:27 PM PDT 24
Finished Jul 20 07:10:35 PM PDT 24
Peak memory 224344 kb
Host smart-dec12c17-21f0-4c0e-9577-bbe97c469482
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392079233 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.392079233
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.1074940458
Short name T644
Test name
Test status
Simulation time 39020941 ps
CPU time 1.17 seconds
Started Jul 20 06:50:16 PM PDT 24
Finished Jul 20 06:50:19 PM PDT 24
Peak memory 219776 kb
Host smart-ddec8dd6-1c7e-4ab6-bc73-61338156d813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074940458 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1074940458
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.3191973529
Short name T64
Test name
Test status
Simulation time 31464704 ps
CPU time 0.98 seconds
Started Jul 20 06:50:17 PM PDT 24
Finished Jul 20 06:50:21 PM PDT 24
Peak memory 207052 kb
Host smart-e06623c9-090c-4b36-a415-bd9dc2933ac2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191973529 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.3191973529
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.2299707030
Short name T67
Test name
Test status
Simulation time 91689451 ps
CPU time 1.21 seconds
Started Jul 20 06:50:16 PM PDT 24
Finished Jul 20 06:50:19 PM PDT 24
Peak memory 218424 kb
Host smart-b73699e5-9ac5-43e4-bd5e-bd487f1d92bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299707030 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.2299707030
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.1986271403
Short name T743
Test name
Test status
Simulation time 23293609 ps
CPU time 0.98 seconds
Started Jul 20 06:50:14 PM PDT 24
Finished Jul 20 06:50:15 PM PDT 24
Peak memory 219112 kb
Host smart-7828fcdb-2164-43be-97c1-47034999b3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986271403 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.1986271403
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.4125016625
Short name T385
Test name
Test status
Simulation time 69926942 ps
CPU time 1.82 seconds
Started Jul 20 06:50:17 PM PDT 24
Finished Jul 20 06:50:21 PM PDT 24
Peak memory 218996 kb
Host smart-2329e24d-731b-466b-9ec5-72b7d6ccddf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125016625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.4125016625
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.3213832297
Short name T50
Test name
Test status
Simulation time 43036836 ps
CPU time 1.01 seconds
Started Jul 20 06:50:27 PM PDT 24
Finished Jul 20 06:50:29 PM PDT 24
Peak memory 224152 kb
Host smart-d0e3ecee-eae5-41c1-b9d5-102e955d563c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213832297 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.3213832297
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.1272296340
Short name T617
Test name
Test status
Simulation time 18281513 ps
CPU time 1.09 seconds
Started Jul 20 06:50:17 PM PDT 24
Finished Jul 20 06:50:20 PM PDT 24
Peak memory 215576 kb
Host smart-1970be63-ff83-4490-b3f6-543af128cbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272296340 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.1272296340
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.1208056423
Short name T879
Test name
Test status
Simulation time 202870762 ps
CPU time 4.33 seconds
Started Jul 20 06:50:15 PM PDT 24
Finished Jul 20 06:50:21 PM PDT 24
Peak memory 215608 kb
Host smart-6c217c5e-bd45-4bed-bfb2-3e367ee19271
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208056423 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1208056423
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.3104289850
Short name T941
Test name
Test status
Simulation time 15960702443 ps
CPU time 194.27 seconds
Started Jul 20 06:50:14 PM PDT 24
Finished Jul 20 06:53:30 PM PDT 24
Peak memory 223996 kb
Host smart-04ac7821-3ce3-4526-890a-1fe3ef623be5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104289850 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.3104289850
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2645494624
Short name T733
Test name
Test status
Simulation time 30848605 ps
CPU time 1.17 seconds
Started Jul 20 06:50:15 PM PDT 24
Finished Jul 20 06:50:18 PM PDT 24
Peak memory 220020 kb
Host smart-5af83c57-7107-4b6c-aefd-5dc8e1610fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645494624 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2645494624
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.817044222
Short name T68
Test name
Test status
Simulation time 48773727 ps
CPU time 0.9 seconds
Started Jul 20 06:50:19 PM PDT 24
Finished Jul 20 06:50:22 PM PDT 24
Peak memory 215420 kb
Host smart-978f42de-fe42-4ce4-af81-45f14cf77922
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817044222 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.817044222
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.3064302227
Short name T369
Test name
Test status
Simulation time 60440803 ps
CPU time 0.83 seconds
Started Jul 20 06:50:18 PM PDT 24
Finished Jul 20 06:50:21 PM PDT 24
Peak memory 216176 kb
Host smart-ec227bba-bb8e-4989-b894-9fac510f314e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064302227 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.3064302227
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.4143470473
Short name T424
Test name
Test status
Simulation time 32120060 ps
CPU time 1.1 seconds
Started Jul 20 06:50:18 PM PDT 24
Finished Jul 20 06:50:21 PM PDT 24
Peak memory 220172 kb
Host smart-f220e301-46ee-4e3a-aea1-ac4e3849fdac
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143470473 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.4143470473
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.3511902746
Short name T907
Test name
Test status
Simulation time 32688495 ps
CPU time 1.1 seconds
Started Jul 20 06:50:27 PM PDT 24
Finished Jul 20 06:50:30 PM PDT 24
Peak memory 220348 kb
Host smart-bef84244-4c3b-4c1d-af89-ccb97319ed69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511902746 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.3511902746
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.990572319
Short name T946
Test name
Test status
Simulation time 65342804 ps
CPU time 1.79 seconds
Started Jul 20 06:50:15 PM PDT 24
Finished Jul 20 06:50:19 PM PDT 24
Peak memory 219148 kb
Host smart-1dc22666-c921-479a-952a-ea9812c4e057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990572319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.990572319
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.3099624892
Short name T559
Test name
Test status
Simulation time 40414676 ps
CPU time 0.86 seconds
Started Jul 20 06:50:15 PM PDT 24
Finished Jul 20 06:50:18 PM PDT 24
Peak memory 215904 kb
Host smart-b0854588-b4da-4216-b483-f71ed01c95f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099624892 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.3099624892
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.2281420510
Short name T336
Test name
Test status
Simulation time 28605455 ps
CPU time 0.99 seconds
Started Jul 20 06:50:19 PM PDT 24
Finished Jul 20 06:50:22 PM PDT 24
Peak memory 215484 kb
Host smart-e4bc8af2-8857-44f7-b0d0-22640a54ea2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281420510 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2281420510
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.3197932823
Short name T330
Test name
Test status
Simulation time 1870719739 ps
CPU time 4.23 seconds
Started Jul 20 06:50:15 PM PDT 24
Finished Jul 20 06:50:21 PM PDT 24
Peak memory 220688 kb
Host smart-8114312e-1018-41ec-b821-b17df591d11f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197932823 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3197932823
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.1189283353
Short name T822
Test name
Test status
Simulation time 306600278499 ps
CPU time 1865.3 seconds
Started Jul 20 06:50:17 PM PDT 24
Finished Jul 20 07:21:25 PM PDT 24
Peak memory 229128 kb
Host smart-c91a762c-ece9-41cb-8553-765cf73c2398
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189283353 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.1189283353
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.332218127
Short name T765
Test name
Test status
Simulation time 29078393 ps
CPU time 1.25 seconds
Started Jul 20 06:50:15 PM PDT 24
Finished Jul 20 06:50:18 PM PDT 24
Peak memory 220012 kb
Host smart-75b5ed0f-2040-45ff-971d-b35af3d0653d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332218127 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.332218127
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.4248863128
Short name T464
Test name
Test status
Simulation time 53042094 ps
CPU time 0.96 seconds
Started Jul 20 06:50:17 PM PDT 24
Finished Jul 20 06:50:21 PM PDT 24
Peak memory 215480 kb
Host smart-20689bb5-bee3-416a-bf6e-bcf318cebaf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248863128 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.4248863128
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.3857598757
Short name T490
Test name
Test status
Simulation time 41992266 ps
CPU time 0.89 seconds
Started Jul 20 06:50:15 PM PDT 24
Finished Jul 20 06:50:18 PM PDT 24
Peak memory 216296 kb
Host smart-2f0ce6d4-5b8d-4fa5-9052-e55dd133390c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857598757 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.3857598757
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.2251205874
Short name T326
Test name
Test status
Simulation time 24769685 ps
CPU time 1.37 seconds
Started Jul 20 06:50:18 PM PDT 24
Finished Jul 20 06:50:22 PM PDT 24
Peak memory 215860 kb
Host smart-02bef1da-2efc-4c81-93df-2cae3010d9fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251205874 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.2251205874
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.1701248388
Short name T212
Test name
Test status
Simulation time 34520598 ps
CPU time 0.87 seconds
Started Jul 20 06:50:14 PM PDT 24
Finished Jul 20 06:50:15 PM PDT 24
Peak memory 218848 kb
Host smart-b3738acc-16d3-4b55-8c4f-f302ca087a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701248388 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.1701248388
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.1766086094
Short name T983
Test name
Test status
Simulation time 57452884 ps
CPU time 1.19 seconds
Started Jul 20 06:50:27 PM PDT 24
Finished Jul 20 06:50:30 PM PDT 24
Peak memory 217624 kb
Host smart-d5b1e5f2-f406-40f5-b0db-953151f23495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766086094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.1766086094
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.2702793986
Short name T31
Test name
Test status
Simulation time 21734085 ps
CPU time 1.08 seconds
Started Jul 20 06:50:14 PM PDT 24
Finished Jul 20 06:50:17 PM PDT 24
Peak memory 216172 kb
Host smart-938f4a4e-0b0e-4beb-b05e-ad456e5951f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702793986 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.2702793986
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.1259029811
Short name T929
Test name
Test status
Simulation time 17135576 ps
CPU time 1.05 seconds
Started Jul 20 06:50:15 PM PDT 24
Finished Jul 20 06:50:18 PM PDT 24
Peak memory 215556 kb
Host smart-9cc1f55e-c54b-4d51-9bf2-daa980e028b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259029811 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.1259029811
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.2409239407
Short name T731
Test name
Test status
Simulation time 224074137 ps
CPU time 4.56 seconds
Started Jul 20 06:50:13 PM PDT 24
Finished Jul 20 06:50:18 PM PDT 24
Peak memory 218700 kb
Host smart-24aa4cd1-3452-4c5a-9982-e1fdabc1f298
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409239407 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.2409239407
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2495493066
Short name T422
Test name
Test status
Simulation time 80022147696 ps
CPU time 2024.26 seconds
Started Jul 20 06:50:15 PM PDT 24
Finished Jul 20 07:24:01 PM PDT 24
Peak memory 230284 kb
Host smart-f48e9f51-6c0a-40a5-b3f5-31104c0333ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495493066 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2495493066
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.3655742779
Short name T862
Test name
Test status
Simulation time 43839036 ps
CPU time 1.15 seconds
Started Jul 20 06:50:25 PM PDT 24
Finished Jul 20 06:50:29 PM PDT 24
Peak memory 218960 kb
Host smart-47f4dc85-3950-47dd-bfeb-d97524810670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655742779 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.3655742779
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.2645578787
Short name T707
Test name
Test status
Simulation time 124218985 ps
CPU time 0.96 seconds
Started Jul 20 06:50:24 PM PDT 24
Finished Jul 20 06:50:27 PM PDT 24
Peak memory 215484 kb
Host smart-cca62a3d-28ac-433f-8d9a-130b344e07c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645578787 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2645578787
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.2066348696
Short name T777
Test name
Test status
Simulation time 16996558 ps
CPU time 0.84 seconds
Started Jul 20 06:50:26 PM PDT 24
Finished Jul 20 06:50:29 PM PDT 24
Peak memory 216480 kb
Host smart-a2b8964a-d9b0-4b59-bd5f-5491ac949a68
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066348696 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2066348696
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.4256339464
Short name T146
Test name
Test status
Simulation time 128629902 ps
CPU time 1.28 seconds
Started Jul 20 06:50:23 PM PDT 24
Finished Jul 20 06:50:26 PM PDT 24
Peak memory 217160 kb
Host smart-16c0badb-220a-439a-9f0e-27232a2bb643
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256339464 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.4256339464
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.3835954072
Short name T842
Test name
Test status
Simulation time 26326878 ps
CPU time 1.23 seconds
Started Jul 20 06:50:24 PM PDT 24
Finished Jul 20 06:50:28 PM PDT 24
Peak memory 220248 kb
Host smart-bdcb0509-b151-4d81-9809-ccafc046c165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835954072 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.3835954072
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.841003824
Short name T938
Test name
Test status
Simulation time 30769112 ps
CPU time 1.29 seconds
Started Jul 20 06:50:19 PM PDT 24
Finished Jul 20 06:50:22 PM PDT 24
Peak memory 217556 kb
Host smart-e585751a-1c69-49ac-a090-fc291e943edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841003824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.841003824
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.2071678881
Short name T51
Test name
Test status
Simulation time 46357318 ps
CPU time 1.03 seconds
Started Jul 20 06:50:22 PM PDT 24
Finished Jul 20 06:50:24 PM PDT 24
Peak memory 224172 kb
Host smart-03adfc6b-1d7b-4f02-ad05-2d2eb0f166f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071678881 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.2071678881
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.3063435910
Short name T691
Test name
Test status
Simulation time 18696976 ps
CPU time 1.06 seconds
Started Jul 20 06:50:17 PM PDT 24
Finished Jul 20 06:50:20 PM PDT 24
Peak memory 215528 kb
Host smart-8add7f8e-d000-474c-b183-c33b45d93adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063435910 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.3063435910
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.2288152014
Short name T355
Test name
Test status
Simulation time 47435370 ps
CPU time 1.13 seconds
Started Jul 20 06:50:17 PM PDT 24
Finished Jul 20 06:50:21 PM PDT 24
Peak memory 215596 kb
Host smart-45754ac8-b3c8-4477-afb9-3e1bd137496f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288152014 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.2288152014
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_alert.2023570966
Short name T909
Test name
Test status
Simulation time 49180647 ps
CPU time 1.1 seconds
Started Jul 20 06:50:25 PM PDT 24
Finished Jul 20 06:50:28 PM PDT 24
Peak memory 218872 kb
Host smart-4a69f81a-73ae-4559-9339-9a18a74778e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023570966 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.2023570966
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.1296766356
Short name T436
Test name
Test status
Simulation time 15455378 ps
CPU time 1 seconds
Started Jul 20 06:50:23 PM PDT 24
Finished Jul 20 06:50:26 PM PDT 24
Peak memory 206976 kb
Host smart-0947d06a-45a1-4053-9918-9b7e7bcca292
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296766356 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.1296766356
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.3673514154
Short name T66
Test name
Test status
Simulation time 50720223 ps
CPU time 1.17 seconds
Started Jul 20 06:50:22 PM PDT 24
Finished Jul 20 06:50:25 PM PDT 24
Peak memory 218708 kb
Host smart-a07a878c-335e-42c4-868a-a3889e17ad4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673514154 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.3673514154
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.868398943
Short name T179
Test name
Test status
Simulation time 19352911 ps
CPU time 1.19 seconds
Started Jul 20 06:50:22 PM PDT 24
Finished Jul 20 06:50:25 PM PDT 24
Peak memory 224284 kb
Host smart-ee3d60f4-2e20-4113-b74a-44caeffb5490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868398943 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.868398943
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1709077566
Short name T633
Test name
Test status
Simulation time 33551213 ps
CPU time 1.27 seconds
Started Jul 20 06:50:22 PM PDT 24
Finished Jul 20 06:50:25 PM PDT 24
Peak memory 218540 kb
Host smart-0afed87a-f9e4-47b1-bcdf-aaebb6adff0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709077566 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1709077566
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.878576505
Short name T618
Test name
Test status
Simulation time 27252110 ps
CPU time 0.83 seconds
Started Jul 20 06:50:22 PM PDT 24
Finished Jul 20 06:50:25 PM PDT 24
Peak memory 215936 kb
Host smart-c8e8ee3d-49d0-45a0-a732-355ddd580019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878576505 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.878576505
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.68592759
Short name T478
Test name
Test status
Simulation time 16513599 ps
CPU time 0.98 seconds
Started Jul 20 06:50:23 PM PDT 24
Finished Jul 20 06:50:25 PM PDT 24
Peak memory 215584 kb
Host smart-3dd0166f-799a-4533-9fa3-a6d859f4e539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68592759 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.68592759
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.2555789889
Short name T873
Test name
Test status
Simulation time 443812410 ps
CPU time 5.02 seconds
Started Jul 20 06:50:24 PM PDT 24
Finished Jul 20 06:50:31 PM PDT 24
Peak memory 215472 kb
Host smart-29660fac-e2a6-4d20-aabe-3f3eb1cdf521
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555789889 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2555789889
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.1388160762
Short name T229
Test name
Test status
Simulation time 30873149093 ps
CPU time 760.3 seconds
Started Jul 20 06:50:24 PM PDT 24
Finished Jul 20 07:03:07 PM PDT 24
Peak memory 219060 kb
Host smart-c4c78a83-cd2d-4498-932b-496506a25cb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388160762 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.1388160762
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.39371965
Short name T461
Test name
Test status
Simulation time 31572330 ps
CPU time 1.16 seconds
Started Jul 20 06:50:26 PM PDT 24
Finished Jul 20 06:50:29 PM PDT 24
Peak memory 219168 kb
Host smart-c4560a3d-6e5e-4d35-b5d3-0c44749c9f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39371965 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.39371965
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.3104891495
Short name T648
Test name
Test status
Simulation time 55645170 ps
CPU time 1.02 seconds
Started Jul 20 06:50:21 PM PDT 24
Finished Jul 20 06:50:24 PM PDT 24
Peak memory 207124 kb
Host smart-8763dc40-fd90-4f24-b6ba-ab1922a38298
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104891495 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.3104891495
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.2433658220
Short name T204
Test name
Test status
Simulation time 20445771 ps
CPU time 0.86 seconds
Started Jul 20 06:50:24 PM PDT 24
Finished Jul 20 06:50:27 PM PDT 24
Peak memory 216524 kb
Host smart-37785feb-b27d-4142-9918-45638646612a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433658220 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.2433658220
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1673114714
Short name T841
Test name
Test status
Simulation time 58772680 ps
CPU time 1.21 seconds
Started Jul 20 06:50:25 PM PDT 24
Finished Jul 20 06:50:29 PM PDT 24
Peak memory 217324 kb
Host smart-47cc74b7-1aac-4a4e-bac2-db2614c83bd7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673114714 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1673114714
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.3182271760
Short name T774
Test name
Test status
Simulation time 33616791 ps
CPU time 1.09 seconds
Started Jul 20 06:50:24 PM PDT 24
Finished Jul 20 06:50:27 PM PDT 24
Peak memory 221188 kb
Host smart-617e7ec1-4044-4daf-9c5e-19c2549ade5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182271760 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3182271760
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.1194355087
Short name T345
Test name
Test status
Simulation time 64898270 ps
CPU time 1.1 seconds
Started Jul 20 06:50:23 PM PDT 24
Finished Jul 20 06:50:27 PM PDT 24
Peak memory 219948 kb
Host smart-76dfcfe9-9da9-43c5-92be-d2f708eab525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194355087 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1194355087
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1073088474
Short name T34
Test name
Test status
Simulation time 27534310 ps
CPU time 0.95 seconds
Started Jul 20 06:50:23 PM PDT 24
Finished Jul 20 06:50:26 PM PDT 24
Peak memory 215960 kb
Host smart-0e70eadc-1534-4269-9115-3b14adf33f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073088474 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1073088474
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.3749127936
Short name T748
Test name
Test status
Simulation time 21218980 ps
CPU time 0.95 seconds
Started Jul 20 06:50:27 PM PDT 24
Finished Jul 20 06:50:29 PM PDT 24
Peak memory 215548 kb
Host smart-9d36c1ff-1ebe-4396-8ae8-0cdc2ec42d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749127936 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.3749127936
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.35341036
Short name T556
Test name
Test status
Simulation time 607684762 ps
CPU time 3.63 seconds
Started Jul 20 06:50:26 PM PDT 24
Finished Jul 20 06:50:32 PM PDT 24
Peak memory 217584 kb
Host smart-6afd0b86-4b58-44d3-b524-c8957497a59e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35341036 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.35341036
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.1129278425
Short name T234
Test name
Test status
Simulation time 35203167115 ps
CPU time 747.76 seconds
Started Jul 20 06:50:25 PM PDT 24
Finished Jul 20 07:02:55 PM PDT 24
Peak memory 223916 kb
Host smart-1827d393-f9a9-4053-86c2-b6227e74c735
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129278425 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.1129278425
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.4206744682
Short name T853
Test name
Test status
Simulation time 24640453 ps
CPU time 1.21 seconds
Started Jul 20 06:50:22 PM PDT 24
Finished Jul 20 06:50:25 PM PDT 24
Peak memory 220948 kb
Host smart-7a5ed750-af4c-437a-b837-fb22fca5c60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206744682 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.4206744682
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.3586434549
Short name T503
Test name
Test status
Simulation time 68955074 ps
CPU time 0.95 seconds
Started Jul 20 06:50:22 PM PDT 24
Finished Jul 20 06:50:24 PM PDT 24
Peak memory 215212 kb
Host smart-1a4b96da-5fcb-431c-aaf5-41075808d6bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586434549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.3586434549
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.743718809
Short name T82
Test name
Test status
Simulation time 29233868 ps
CPU time 0.89 seconds
Started Jul 20 06:50:22 PM PDT 24
Finished Jul 20 06:50:24 PM PDT 24
Peak memory 216488 kb
Host smart-726c3d81-5223-4d5e-a7db-86d5fe9816fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743718809 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.743718809
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.763903100
Short name T118
Test name
Test status
Simulation time 40596248 ps
CPU time 1.14 seconds
Started Jul 20 06:50:23 PM PDT 24
Finished Jul 20 06:50:25 PM PDT 24
Peak memory 217048 kb
Host smart-d2d800ea-331a-4edb-8a71-9e0f155778e5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763903100 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_di
sable_auto_req_mode.763903100
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.3302434977
Short name T7
Test name
Test status
Simulation time 77917898 ps
CPU time 1.05 seconds
Started Jul 20 06:50:22 PM PDT 24
Finished Jul 20 06:50:25 PM PDT 24
Peak memory 219208 kb
Host smart-3d8ecad0-e80f-4fc7-903c-7b35284f8b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302434977 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3302434977
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.2144811545
Short name T472
Test name
Test status
Simulation time 79233922 ps
CPU time 1.29 seconds
Started Jul 20 06:50:24 PM PDT 24
Finished Jul 20 06:50:28 PM PDT 24
Peak memory 217924 kb
Host smart-ca5d5dca-f91b-45fa-a505-19917056ed75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144811545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.2144811545
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.2251148868
Short name T563
Test name
Test status
Simulation time 20617989 ps
CPU time 1.06 seconds
Started Jul 20 06:50:24 PM PDT 24
Finished Jul 20 06:50:27 PM PDT 24
Peak memory 216040 kb
Host smart-89155194-43d8-4565-94b6-3e4df4c24ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251148868 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.2251148868
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.3486864140
Short name T56
Test name
Test status
Simulation time 24268581 ps
CPU time 0.92 seconds
Started Jul 20 06:50:23 PM PDT 24
Finished Jul 20 06:50:26 PM PDT 24
Peak memory 215564 kb
Host smart-48a6169f-15cc-4da0-a8fd-c7e9606fc14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486864140 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.3486864140
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.1143111242
Short name T589
Test name
Test status
Simulation time 335871426 ps
CPU time 3.59 seconds
Started Jul 20 06:50:25 PM PDT 24
Finished Jul 20 06:50:30 PM PDT 24
Peak memory 217420 kb
Host smart-160491a8-aad7-4f0d-98f5-6b5636d89c81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143111242 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1143111242
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.259026971
Short name T231
Test name
Test status
Simulation time 55762767410 ps
CPU time 312.21 seconds
Started Jul 20 06:50:21 PM PDT 24
Finished Jul 20 06:55:34 PM PDT 24
Peak memory 223944 kb
Host smart-d0029318-928a-465b-a746-05917e7eab9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259026971 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.259026971
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.3815682015
Short name T591
Test name
Test status
Simulation time 51367589 ps
CPU time 1.28 seconds
Started Jul 20 06:50:25 PM PDT 24
Finished Jul 20 06:50:28 PM PDT 24
Peak memory 220304 kb
Host smart-bfb7bdb7-6c9a-4e72-9063-a54408bb2969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815682015 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.3815682015
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.1841126918
Short name T389
Test name
Test status
Simulation time 12287898 ps
CPU time 0.88 seconds
Started Jul 20 06:50:32 PM PDT 24
Finished Jul 20 06:50:35 PM PDT 24
Peak memory 207280 kb
Host smart-22f37382-0b81-40f6-b61c-8dfdeb9957d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841126918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.1841126918
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.470969912
Short name T164
Test name
Test status
Simulation time 21870437 ps
CPU time 0.88 seconds
Started Jul 20 06:50:28 PM PDT 24
Finished Jul 20 06:50:30 PM PDT 24
Peak memory 216584 kb
Host smart-6dc9e7ed-1ca1-4d76-8f09-7ea908e89435
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470969912 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.470969912
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.3271905054
Short name T631
Test name
Test status
Simulation time 35257263 ps
CPU time 1.04 seconds
Started Jul 20 06:50:32 PM PDT 24
Finished Jul 20 06:50:36 PM PDT 24
Peak memory 218884 kb
Host smart-c43da6fd-2149-4f64-a06b-d3accab655c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271905054 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.3271905054
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.756805340
Short name T114
Test name
Test status
Simulation time 34308212 ps
CPU time 1.06 seconds
Started Jul 20 06:50:33 PM PDT 24
Finished Jul 20 06:50:36 PM PDT 24
Peak memory 229916 kb
Host smart-a9e653c9-60d0-49f6-9f30-f27829972b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756805340 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.756805340
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.2132869370
Short name T360
Test name
Test status
Simulation time 63634748 ps
CPU time 1.36 seconds
Started Jul 20 06:50:24 PM PDT 24
Finished Jul 20 06:50:28 PM PDT 24
Peak memory 219012 kb
Host smart-a562567d-3731-4d63-a4d4-52de6f3feb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132869370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2132869370
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.1212267236
Short name T96
Test name
Test status
Simulation time 32822218 ps
CPU time 0.93 seconds
Started Jul 20 06:50:22 PM PDT 24
Finished Jul 20 06:50:25 PM PDT 24
Peak memory 216036 kb
Host smart-b87684c5-a095-4b14-883c-b0a5021089c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212267236 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.1212267236
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.2098384537
Short name T538
Test name
Test status
Simulation time 71341879 ps
CPU time 0.9 seconds
Started Jul 20 06:50:26 PM PDT 24
Finished Jul 20 06:50:29 PM PDT 24
Peak memory 215548 kb
Host smart-f76a0810-919d-452c-8398-20db2912e04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098384537 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.2098384537
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.1857927644
Short name T764
Test name
Test status
Simulation time 187810497 ps
CPU time 3.7 seconds
Started Jul 20 06:50:21 PM PDT 24
Finished Jul 20 06:50:26 PM PDT 24
Peak memory 215560 kb
Host smart-fb463fa8-68fd-469c-9b7b-013afd03493b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857927644 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.1857927644
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.3951835863
Short name T806
Test name
Test status
Simulation time 996369609455 ps
CPU time 1468.67 seconds
Started Jul 20 06:50:25 PM PDT 24
Finished Jul 20 07:14:56 PM PDT 24
Peak memory 224096 kb
Host smart-f3bedc3f-4071-4321-bede-da35e310b42c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951835863 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.3951835863
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.3250047776
Short name T640
Test name
Test status
Simulation time 25069002 ps
CPU time 1.35 seconds
Started Jul 20 06:49:10 PM PDT 24
Finished Jul 20 06:49:12 PM PDT 24
Peak memory 220200 kb
Host smart-e5e0f436-7bcf-43d0-a711-45054dbb880a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250047776 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3250047776
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.1209202021
Short name T522
Test name
Test status
Simulation time 13708117 ps
CPU time 0.91 seconds
Started Jul 20 06:49:05 PM PDT 24
Finished Jul 20 06:49:08 PM PDT 24
Peak memory 207276 kb
Host smart-58c4bf1e-0573-4c99-8d27-b087d8dab6b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209202021 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.1209202021
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.4112871055
Short name T825
Test name
Test status
Simulation time 13400601 ps
CPU time 0.96 seconds
Started Jul 20 06:49:06 PM PDT 24
Finished Jul 20 06:49:10 PM PDT 24
Peak memory 216368 kb
Host smart-e11ac93a-647b-491c-ba7f-94d079865e10
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112871055 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.4112871055
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.845323644
Short name T881
Test name
Test status
Simulation time 460701292 ps
CPU time 1.1 seconds
Started Jul 20 06:49:06 PM PDT 24
Finished Jul 20 06:49:10 PM PDT 24
Peak memory 217044 kb
Host smart-1db29cb3-60e5-4071-8d40-585b5a0bf325
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845323644 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_dis
able_auto_req_mode.845323644
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.2383202081
Short name T685
Test name
Test status
Simulation time 76729514 ps
CPU time 1.13 seconds
Started Jul 20 06:49:06 PM PDT 24
Finished Jul 20 06:49:09 PM PDT 24
Peak memory 220080 kb
Host smart-63953f81-55ce-4d66-a5cc-3d0c43209cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383202081 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.2383202081
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.3052169248
Short name T634
Test name
Test status
Simulation time 40155782 ps
CPU time 1.4 seconds
Started Jul 20 06:49:06 PM PDT 24
Finished Jul 20 06:49:09 PM PDT 24
Peak memory 218796 kb
Host smart-6420ee62-2d18-472d-b3d9-4bb63f6f76ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052169248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.3052169248
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.1569680077
Short name T751
Test name
Test status
Simulation time 26018075 ps
CPU time 0.92 seconds
Started Jul 20 06:49:07 PM PDT 24
Finished Jul 20 06:49:10 PM PDT 24
Peak memory 216072 kb
Host smart-408a237a-bc02-4161-bb6e-ef786c2797d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569680077 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1569680077
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.3446599310
Short name T288
Test name
Test status
Simulation time 18385448 ps
CPU time 1.19 seconds
Started Jul 20 06:49:05 PM PDT 24
Finished Jul 20 06:49:08 PM PDT 24
Peak memory 207352 kb
Host smart-d6748dce-be8f-4242-ad64-949f734a0c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446599310 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.3446599310
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.2861180342
Short name T755
Test name
Test status
Simulation time 18977249 ps
CPU time 1.04 seconds
Started Jul 20 06:49:05 PM PDT 24
Finished Jul 20 06:49:07 PM PDT 24
Peak memory 215548 kb
Host smart-15b3765f-999c-48aa-96ba-c869ced915a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861180342 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.2861180342
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.4203221358
Short name T896
Test name
Test status
Simulation time 622451126 ps
CPU time 4.03 seconds
Started Jul 20 06:49:04 PM PDT 24
Finished Jul 20 06:49:10 PM PDT 24
Peak memory 215652 kb
Host smart-0014ded3-9f8a-4f0b-bbfd-0f6eae589b59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203221358 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.4203221358
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.3069112564
Short name T498
Test name
Test status
Simulation time 131616275688 ps
CPU time 1591.59 seconds
Started Jul 20 06:49:05 PM PDT 24
Finished Jul 20 07:15:39 PM PDT 24
Peak memory 225396 kb
Host smart-0a1efa78-92c1-44db-a18a-80c36c179bd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069112564 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.3069112564
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.2040140196
Short name T554
Test name
Test status
Simulation time 37331560 ps
CPU time 1.13 seconds
Started Jul 20 06:50:32 PM PDT 24
Finished Jul 20 06:50:35 PM PDT 24
Peak memory 219716 kb
Host smart-fbcc4b80-9c35-4ae5-a31d-e12d605cf4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040140196 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.2040140196
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.1233232657
Short name T763
Test name
Test status
Simulation time 53530952 ps
CPU time 0.85 seconds
Started Jul 20 06:50:30 PM PDT 24
Finished Jul 20 06:50:33 PM PDT 24
Peak memory 218460 kb
Host smart-01daf6ae-0c42-4fdf-979f-263ba87d563e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233232657 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.1233232657
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.4257405173
Short name T450
Test name
Test status
Simulation time 110336217 ps
CPU time 1.19 seconds
Started Jul 20 06:50:30 PM PDT 24
Finished Jul 20 06:50:33 PM PDT 24
Peak memory 220164 kb
Host smart-2e9e9232-5014-4bfd-956a-48b74271d26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257405173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.4257405173
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.2303168219
Short name T616
Test name
Test status
Simulation time 24466041 ps
CPU time 1.26 seconds
Started Jul 20 06:50:34 PM PDT 24
Finished Jul 20 06:50:38 PM PDT 24
Peak memory 220180 kb
Host smart-c84d3cd0-df01-486b-bc62-d4730e63349e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303168219 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.2303168219
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.2901824816
Short name T534
Test name
Test status
Simulation time 21437374 ps
CPU time 1.04 seconds
Started Jul 20 06:50:32 PM PDT 24
Finished Jul 20 06:50:35 PM PDT 24
Peak memory 224280 kb
Host smart-3d37622a-a70c-4c5d-aee6-4ed1d047b30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901824816 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.2901824816
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.1766754343
Short name T797
Test name
Test status
Simulation time 199055686 ps
CPU time 2.66 seconds
Started Jul 20 06:50:30 PM PDT 24
Finished Jul 20 06:50:34 PM PDT 24
Peak memory 220240 kb
Host smart-cbe8770a-ce7c-4305-b343-9318ce5f833a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766754343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.1766754343
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.1587956429
Short name T568
Test name
Test status
Simulation time 28609551 ps
CPU time 1.26 seconds
Started Jul 20 06:50:33 PM PDT 24
Finished Jul 20 06:50:36 PM PDT 24
Peak memory 216008 kb
Host smart-06bed932-a82c-4c0b-9280-a6cf0191b5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587956429 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.1587956429
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.2643818601
Short name T958
Test name
Test status
Simulation time 20451020 ps
CPU time 1.13 seconds
Started Jul 20 06:50:28 PM PDT 24
Finished Jul 20 06:50:31 PM PDT 24
Peak memory 220048 kb
Host smart-686edae6-61b6-4513-a964-9f47d93780c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643818601 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2643818601
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.1417732947
Short name T655
Test name
Test status
Simulation time 61524876 ps
CPU time 1.19 seconds
Started Jul 20 06:50:34 PM PDT 24
Finished Jul 20 06:50:37 PM PDT 24
Peak memory 217500 kb
Host smart-62eb502f-4e30-4c39-a99c-dc99c60f8dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417732947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.1417732947
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.2212923553
Short name T156
Test name
Test status
Simulation time 177313740 ps
CPU time 1.28 seconds
Started Jul 20 06:50:31 PM PDT 24
Finished Jul 20 06:50:34 PM PDT 24
Peak memory 218860 kb
Host smart-4ba10bb7-f09b-4f36-95e8-786b0c3a1a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212923553 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.2212923553
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.31102615
Short name T682
Test name
Test status
Simulation time 26538313 ps
CPU time 0.94 seconds
Started Jul 20 06:50:30 PM PDT 24
Finished Jul 20 06:50:33 PM PDT 24
Peak memory 219044 kb
Host smart-f6baeff0-ffd3-4e79-92f5-5705ab7d5f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31102615 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.31102615
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.1422755603
Short name T301
Test name
Test status
Simulation time 59206387 ps
CPU time 1.78 seconds
Started Jul 20 06:50:32 PM PDT 24
Finished Jul 20 06:50:36 PM PDT 24
Peak memory 217780 kb
Host smart-8539a6d7-b4ad-447a-99d1-416526893cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422755603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.1422755603
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.377288712
Short name T172
Test name
Test status
Simulation time 29669346 ps
CPU time 1.22 seconds
Started Jul 20 06:50:30 PM PDT 24
Finished Jul 20 06:50:33 PM PDT 24
Peak memory 218776 kb
Host smart-98ba630d-f763-4596-ae39-53eba0e5d72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377288712 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.377288712
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.3637498035
Short name T756
Test name
Test status
Simulation time 19203005 ps
CPU time 1.14 seconds
Started Jul 20 06:50:32 PM PDT 24
Finished Jul 20 06:50:36 PM PDT 24
Peak memory 224248 kb
Host smart-7956d141-2372-465e-95ae-aacd030cbe1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637498035 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.3637498035
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.201681903
Short name T752
Test name
Test status
Simulation time 159764812 ps
CPU time 1.43 seconds
Started Jul 20 06:50:30 PM PDT 24
Finished Jul 20 06:50:34 PM PDT 24
Peak memory 218944 kb
Host smart-a5ecbf50-f452-4741-8632-677bd1a94ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201681903 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.201681903
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.3782507093
Short name T291
Test name
Test status
Simulation time 47558090 ps
CPU time 1.27 seconds
Started Jul 20 06:50:33 PM PDT 24
Finished Jul 20 06:50:36 PM PDT 24
Peak memory 216008 kb
Host smart-4a0e8093-5d91-4c5a-94aa-1e65b00a7135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782507093 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.3782507093
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.3409082030
Short name T188
Test name
Test status
Simulation time 18847543 ps
CPU time 1.15 seconds
Started Jul 20 06:50:30 PM PDT 24
Finished Jul 20 06:50:33 PM PDT 24
Peak memory 224296 kb
Host smart-7d2ce313-3d93-4724-8847-2776dface7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409082030 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.3409082030
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.2140397666
Short name T684
Test name
Test status
Simulation time 73685854 ps
CPU time 1.1 seconds
Started Jul 20 06:50:33 PM PDT 24
Finished Jul 20 06:50:36 PM PDT 24
Peak memory 217636 kb
Host smart-9ea2b262-02b1-4c74-a918-567007d96177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140397666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.2140397666
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.3844697354
Short name T533
Test name
Test status
Simulation time 80129064 ps
CPU time 1.23 seconds
Started Jul 20 06:50:34 PM PDT 24
Finished Jul 20 06:50:37 PM PDT 24
Peak memory 218872 kb
Host smart-3d44d928-2393-43ef-b22c-22432757e34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844697354 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.3844697354
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.3378746461
Short name T4
Test name
Test status
Simulation time 228169270 ps
CPU time 1.02 seconds
Started Jul 20 06:50:30 PM PDT 24
Finished Jul 20 06:50:32 PM PDT 24
Peak memory 220020 kb
Host smart-c596f520-3773-49b3-9c12-779c7634f252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378746461 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.3378746461
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.92281344
Short name T702
Test name
Test status
Simulation time 101629564 ps
CPU time 3.07 seconds
Started Jul 20 06:50:34 PM PDT 24
Finished Jul 20 06:50:39 PM PDT 24
Peak memory 219008 kb
Host smart-67128abc-3409-4bca-97c0-413f05c4ce40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92281344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.92281344
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.1984689624
Short name T543
Test name
Test status
Simulation time 44278611 ps
CPU time 1.19 seconds
Started Jul 20 06:50:31 PM PDT 24
Finished Jul 20 06:50:35 PM PDT 24
Peak memory 219024 kb
Host smart-fe0613bf-98cf-4288-a4ba-ca5d164e129d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984689624 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.1984689624
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.3701382336
Short name T452
Test name
Test status
Simulation time 22158974 ps
CPU time 1.02 seconds
Started Jul 20 06:50:30 PM PDT 24
Finished Jul 20 06:50:32 PM PDT 24
Peak memory 224280 kb
Host smart-c19000e0-692d-499b-9820-5675738f48ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701382336 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.3701382336
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.1543093216
Short name T459
Test name
Test status
Simulation time 53146126 ps
CPU time 1.64 seconds
Started Jul 20 06:50:31 PM PDT 24
Finished Jul 20 06:50:34 PM PDT 24
Peak memory 218684 kb
Host smart-b5fc723a-526a-4bde-8f2e-bd5156a5f701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543093216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.1543093216
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.2082395313
Short name T610
Test name
Test status
Simulation time 77109672 ps
CPU time 1.23 seconds
Started Jul 20 06:50:32 PM PDT 24
Finished Jul 20 06:50:36 PM PDT 24
Peak memory 221068 kb
Host smart-85b16b1d-52ad-4638-be00-420c9db34c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082395313 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.2082395313
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.1781248979
Short name T595
Test name
Test status
Simulation time 30276962 ps
CPU time 0.99 seconds
Started Jul 20 06:50:31 PM PDT 24
Finished Jul 20 06:50:34 PM PDT 24
Peak memory 224088 kb
Host smart-cf5ac6d3-758c-49d8-a601-1203854965fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781248979 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.1781248979
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.1454493548
Short name T578
Test name
Test status
Simulation time 34525576 ps
CPU time 1.51 seconds
Started Jul 20 06:50:34 PM PDT 24
Finished Jul 20 06:50:38 PM PDT 24
Peak memory 217636 kb
Host smart-3866a78f-4ae3-4d0f-b3ae-572c0923416d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454493548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1454493548
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.1320132958
Short name T947
Test name
Test status
Simulation time 27972520 ps
CPU time 1.3 seconds
Started Jul 20 06:50:33 PM PDT 24
Finished Jul 20 06:50:36 PM PDT 24
Peak memory 219900 kb
Host smart-a9665612-7c9c-405c-a046-3cabad79a2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320132958 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.1320132958
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.3045636564
Short name T133
Test name
Test status
Simulation time 20570197 ps
CPU time 1.12 seconds
Started Jul 20 06:50:30 PM PDT 24
Finished Jul 20 06:50:33 PM PDT 24
Peak memory 220068 kb
Host smart-5af48f49-428a-408e-894c-45be32fb90d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045636564 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.3045636564
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.1768258014
Short name T584
Test name
Test status
Simulation time 39610862 ps
CPU time 1.13 seconds
Started Jul 20 06:50:31 PM PDT 24
Finished Jul 20 06:50:34 PM PDT 24
Peak memory 217608 kb
Host smart-297b2e19-74e2-41c0-a1bb-fe9a1109d091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768258014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.1768258014
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.898075454
Short name T177
Test name
Test status
Simulation time 27868617 ps
CPU time 1.22 seconds
Started Jul 20 06:49:05 PM PDT 24
Finished Jul 20 06:49:08 PM PDT 24
Peak memory 218984 kb
Host smart-8e991a0c-51c4-48a3-931c-cec902425c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898075454 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.898075454
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.381966034
Short name T830
Test name
Test status
Simulation time 17479773 ps
CPU time 0.91 seconds
Started Jul 20 06:49:21 PM PDT 24
Finished Jul 20 06:49:23 PM PDT 24
Peak memory 207000 kb
Host smart-1a415dce-8bad-4d4e-b7c4-422a583d3124
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381966034 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.381966034
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.762628922
Short name T88
Test name
Test status
Simulation time 10720386 ps
CPU time 0.94 seconds
Started Jul 20 06:49:07 PM PDT 24
Finished Jul 20 06:49:10 PM PDT 24
Peak memory 216568 kb
Host smart-b2448724-51c9-4857-824a-17faf446883b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762628922 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.762628922
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.2726463301
Short name T961
Test name
Test status
Simulation time 99208130 ps
CPU time 1.09 seconds
Started Jul 20 06:49:19 PM PDT 24
Finished Jul 20 06:49:20 PM PDT 24
Peak memory 217084 kb
Host smart-1d840278-6e97-46a3-b9d0-197f86527659
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726463301 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.2726463301
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.2765841028
Short name T768
Test name
Test status
Simulation time 26585577 ps
CPU time 0.89 seconds
Started Jul 20 06:49:06 PM PDT 24
Finished Jul 20 06:49:09 PM PDT 24
Peak memory 218644 kb
Host smart-4319d636-98f7-496a-9f1b-0de74519eba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765841028 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.2765841028
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.2258559776
Short name T730
Test name
Test status
Simulation time 68102816 ps
CPU time 2.49 seconds
Started Jul 20 06:49:07 PM PDT 24
Finished Jul 20 06:49:11 PM PDT 24
Peak memory 220440 kb
Host smart-1fafb144-124b-41f9-8526-2f03e2aa771b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258559776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.2258559776
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.125790436
Short name T541
Test name
Test status
Simulation time 27382194 ps
CPU time 0.99 seconds
Started Jul 20 06:49:06 PM PDT 24
Finished Jul 20 06:49:09 PM PDT 24
Peak memory 215732 kb
Host smart-7f899d8f-cf72-44f3-bd4d-a24dbf78a177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125790436 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.125790436
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.3146013336
Short name T805
Test name
Test status
Simulation time 17819206 ps
CPU time 0.96 seconds
Started Jul 20 06:49:06 PM PDT 24
Finished Jul 20 06:49:09 PM PDT 24
Peak memory 207344 kb
Host smart-7e975496-5287-43bd-ae68-c7d1cdfe27f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146013336 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.3146013336
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.3517570253
Short name T560
Test name
Test status
Simulation time 18906057 ps
CPU time 1.04 seconds
Started Jul 20 06:49:09 PM PDT 24
Finished Jul 20 06:49:11 PM PDT 24
Peak memory 215596 kb
Host smart-b6f98530-5466-482e-9fe6-3e4862b6e3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517570253 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.3517570253
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.1195077153
Short name T480
Test name
Test status
Simulation time 284898912 ps
CPU time 5.53 seconds
Started Jul 20 06:49:09 PM PDT 24
Finished Jul 20 06:49:16 PM PDT 24
Peak memory 215672 kb
Host smart-be10bd2e-01ac-4f5e-b4dd-637d85df0b76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195077153 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.1195077153
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.391579355
Short name T967
Test name
Test status
Simulation time 26773736452 ps
CPU time 607.19 seconds
Started Jul 20 06:49:07 PM PDT 24
Finished Jul 20 06:59:17 PM PDT 24
Peak memory 218012 kb
Host smart-a6a5ed78-9ead-4d46-ab18-167895d73e7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391579355 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.391579355
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.1182086170
Short name T55
Test name
Test status
Simulation time 25990544 ps
CPU time 1.07 seconds
Started Jul 20 06:50:32 PM PDT 24
Finished Jul 20 06:50:35 PM PDT 24
Peak memory 224256 kb
Host smart-4fcc3e0e-0da6-4818-8adf-86a8ade6b61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182086170 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1182086170
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.1689607244
Short name T771
Test name
Test status
Simulation time 52818824 ps
CPU time 1.11 seconds
Started Jul 20 06:50:32 PM PDT 24
Finished Jul 20 06:50:36 PM PDT 24
Peak memory 220228 kb
Host smart-58c6f517-fd10-4bf5-a802-1b986b50ab6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689607244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.1689607244
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.2575143368
Short name T943
Test name
Test status
Simulation time 42080521 ps
CPU time 1.21 seconds
Started Jul 20 06:50:29 PM PDT 24
Finished Jul 20 06:50:31 PM PDT 24
Peak memory 219500 kb
Host smart-ffa91713-9c17-4644-9e90-94c53a6af2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575143368 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.2575143368
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.3372572725
Short name T779
Test name
Test status
Simulation time 34092573 ps
CPU time 0.96 seconds
Started Jul 20 06:50:28 PM PDT 24
Finished Jul 20 06:50:30 PM PDT 24
Peak memory 218732 kb
Host smart-73075e20-59b6-4c5f-ace1-5473c4fd6f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372572725 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.3372572725
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.2668454016
Short name T890
Test name
Test status
Simulation time 32659319 ps
CPU time 1.44 seconds
Started Jul 20 06:50:30 PM PDT 24
Finished Jul 20 06:50:33 PM PDT 24
Peak memory 218652 kb
Host smart-1611f10a-72b4-4cde-af1a-74c2403c39eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668454016 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.2668454016
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.4235192115
Short name T722
Test name
Test status
Simulation time 23697377 ps
CPU time 1.22 seconds
Started Jul 20 06:50:32 PM PDT 24
Finished Jul 20 06:50:36 PM PDT 24
Peak memory 220120 kb
Host smart-3d717d93-aebc-4030-916d-1a94e83aaa6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235192115 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.4235192115
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.2165795063
Short name T855
Test name
Test status
Simulation time 33408596 ps
CPU time 0.88 seconds
Started Jul 20 06:50:29 PM PDT 24
Finished Jul 20 06:50:31 PM PDT 24
Peak memory 218388 kb
Host smart-5ec937fa-c766-4355-b966-b822ecd71886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165795063 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.2165795063
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.3273652047
Short name T843
Test name
Test status
Simulation time 55387691 ps
CPU time 1.37 seconds
Started Jul 20 06:50:31 PM PDT 24
Finished Jul 20 06:50:35 PM PDT 24
Peak memory 219072 kb
Host smart-7cc8711c-7298-4719-acc5-51aa02e31f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273652047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.3273652047
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.640893770
Short name T218
Test name
Test status
Simulation time 74917098 ps
CPU time 1.18 seconds
Started Jul 20 06:50:29 PM PDT 24
Finished Jul 20 06:50:32 PM PDT 24
Peak memory 220092 kb
Host smart-94115d1c-0d0a-48d4-b7d7-170baaeb9db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640893770 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.640893770
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.1629381890
Short name T163
Test name
Test status
Simulation time 19986338 ps
CPU time 1.01 seconds
Started Jul 20 06:50:32 PM PDT 24
Finished Jul 20 06:50:36 PM PDT 24
Peak memory 218684 kb
Host smart-ee8abfa3-e7b0-4826-871b-5e4ad96a4354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629381890 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1629381890
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.4043475935
Short name T397
Test name
Test status
Simulation time 64383641 ps
CPU time 1.13 seconds
Started Jul 20 06:50:30 PM PDT 24
Finished Jul 20 06:50:32 PM PDT 24
Peak memory 220216 kb
Host smart-e91dc6a0-7a30-40d2-b218-0d4149602bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043475935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.4043475935
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.764311884
Short name T922
Test name
Test status
Simulation time 31218677 ps
CPU time 1.42 seconds
Started Jul 20 06:50:33 PM PDT 24
Finished Jul 20 06:50:37 PM PDT 24
Peak memory 220944 kb
Host smart-b5110eec-836a-429b-9b44-72404a22010d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764311884 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.764311884
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.1699019605
Short name T131
Test name
Test status
Simulation time 51477587 ps
CPU time 1.17 seconds
Started Jul 20 06:50:32 PM PDT 24
Finished Jul 20 06:50:35 PM PDT 24
Peak memory 229820 kb
Host smart-45a7b6d0-2ac5-459b-99be-141058b71be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699019605 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.1699019605
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.1037298080
Short name T587
Test name
Test status
Simulation time 34865578 ps
CPU time 1.28 seconds
Started Jul 20 06:50:32 PM PDT 24
Finished Jul 20 06:50:36 PM PDT 24
Peak memory 217336 kb
Host smart-a533a1f5-9e5f-4dfe-a0c0-f82736981fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037298080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.1037298080
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.1854837800
Short name T193
Test name
Test status
Simulation time 302374909 ps
CPU time 1.37 seconds
Started Jul 20 06:50:29 PM PDT 24
Finished Jul 20 06:50:32 PM PDT 24
Peak memory 219860 kb
Host smart-e19aade4-e8e4-40a9-b35a-c29e5349fc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854837800 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.1854837800
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.4089625518
Short name T803
Test name
Test status
Simulation time 35358901 ps
CPU time 0.89 seconds
Started Jul 20 06:50:33 PM PDT 24
Finished Jul 20 06:50:36 PM PDT 24
Peak memory 218740 kb
Host smart-11a684f6-2e40-4cc7-97c9-30a332f1cd1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089625518 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.4089625518
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.3153229860
Short name T602
Test name
Test status
Simulation time 237531885 ps
CPU time 3.31 seconds
Started Jul 20 06:50:31 PM PDT 24
Finished Jul 20 06:50:36 PM PDT 24
Peak memory 220052 kb
Host smart-a11fa7ee-7d5c-460e-8bde-cba64c0079bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153229860 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.3153229860
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.4004370790
Short name T622
Test name
Test status
Simulation time 28706333 ps
CPU time 1.14 seconds
Started Jul 20 06:50:41 PM PDT 24
Finished Jul 20 06:50:45 PM PDT 24
Peak memory 220064 kb
Host smart-69821753-d777-4115-8954-d23905c56079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004370790 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.4004370790
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.1070135626
Short name T645
Test name
Test status
Simulation time 32639400 ps
CPU time 1.09 seconds
Started Jul 20 06:50:40 PM PDT 24
Finished Jul 20 06:50:45 PM PDT 24
Peak memory 218920 kb
Host smart-3bc2bbd2-6931-4111-aef3-736a083528a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070135626 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1070135626
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.74405684
Short name T726
Test name
Test status
Simulation time 28676962 ps
CPU time 1.31 seconds
Started Jul 20 06:50:34 PM PDT 24
Finished Jul 20 06:50:38 PM PDT 24
Peak memory 217648 kb
Host smart-dc1f5134-5d33-49b8-a797-cfbbf29fe0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74405684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.74405684
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.2415325931
Short name T462
Test name
Test status
Simulation time 101564781 ps
CPU time 1.28 seconds
Started Jul 20 06:50:42 PM PDT 24
Finished Jul 20 06:50:46 PM PDT 24
Peak memory 216024 kb
Host smart-91e02412-3edd-4353-a101-9e623a1cccc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415325931 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.2415325931
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.657589139
Short name T124
Test name
Test status
Simulation time 20509024 ps
CPU time 1.21 seconds
Started Jul 20 06:50:41 PM PDT 24
Finished Jul 20 06:50:45 PM PDT 24
Peak memory 229924 kb
Host smart-8ccc9a3f-5759-4737-9975-14ea14628229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657589139 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.657589139
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.1075614123
Short name T871
Test name
Test status
Simulation time 66064149 ps
CPU time 1.78 seconds
Started Jul 20 06:50:38 PM PDT 24
Finished Jul 20 06:50:42 PM PDT 24
Peak memory 220172 kb
Host smart-ac3cb09a-d683-4f6c-8d89-3ab7ed8c6e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075614123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.1075614123
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.3887344087
Short name T674
Test name
Test status
Simulation time 116490065 ps
CPU time 1.18 seconds
Started Jul 20 06:50:41 PM PDT 24
Finished Jul 20 06:50:45 PM PDT 24
Peak memory 220008 kb
Host smart-969c08c2-eb5e-492c-86eb-282b765e98ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887344087 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.3887344087
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.162451368
Short name T993
Test name
Test status
Simulation time 19522852 ps
CPU time 1.06 seconds
Started Jul 20 06:50:38 PM PDT 24
Finished Jul 20 06:50:41 PM PDT 24
Peak memory 218744 kb
Host smart-539bb39d-7be7-465b-a0b1-f18924346f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162451368 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.162451368
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.2497738673
Short name T784
Test name
Test status
Simulation time 46196493 ps
CPU time 1.55 seconds
Started Jul 20 06:50:41 PM PDT 24
Finished Jul 20 06:50:46 PM PDT 24
Peak memory 218808 kb
Host smart-d9ce5e26-a159-4db2-8cc9-84aa0bcee06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497738673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.2497738673
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.3216980493
Short name T292
Test name
Test status
Simulation time 28608265 ps
CPU time 1.35 seconds
Started Jul 20 06:50:41 PM PDT 24
Finished Jul 20 06:50:45 PM PDT 24
Peak memory 219432 kb
Host smart-c54430dd-15b9-478e-8e9e-c2767f328214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216980493 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.3216980493
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.2857390345
Short name T491
Test name
Test status
Simulation time 25050896 ps
CPU time 0.88 seconds
Started Jul 20 06:50:45 PM PDT 24
Finished Jul 20 06:50:47 PM PDT 24
Peak memory 218640 kb
Host smart-1c39f91f-a999-4cb0-a037-2bcd001f07ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857390345 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2857390345
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.4014214076
Short name T562
Test name
Test status
Simulation time 118834644 ps
CPU time 1.67 seconds
Started Jul 20 06:50:40 PM PDT 24
Finished Jul 20 06:50:44 PM PDT 24
Peak memory 220628 kb
Host smart-441ab58c-5677-46cb-b4e4-9df9f5e01860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014214076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.4014214076
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.3822616391
Short name T600
Test name
Test status
Simulation time 79232640 ps
CPU time 1.18 seconds
Started Jul 20 06:49:12 PM PDT 24
Finished Jul 20 06:49:13 PM PDT 24
Peak memory 220452 kb
Host smart-d9088f80-9f28-4b37-b818-33911bdabd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822616391 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3822616391
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.216140894
Short name T934
Test name
Test status
Simulation time 11294328 ps
CPU time 0.85 seconds
Started Jul 20 06:49:15 PM PDT 24
Finished Jul 20 06:49:16 PM PDT 24
Peak memory 206824 kb
Host smart-90b727b8-e570-4e3e-8c85-282275cf9585
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216140894 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.216140894
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.2206299332
Short name T89
Test name
Test status
Simulation time 21333606 ps
CPU time 0.89 seconds
Started Jul 20 06:49:20 PM PDT 24
Finished Jul 20 06:49:21 PM PDT 24
Peak memory 216540 kb
Host smart-ddb2da02-23c4-4bda-86c7-58c56f41a986
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206299332 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.2206299332
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.2211205189
Short name T828
Test name
Test status
Simulation time 37373032 ps
CPU time 1.33 seconds
Started Jul 20 06:49:13 PM PDT 24
Finished Jul 20 06:49:15 PM PDT 24
Peak memory 217112 kb
Host smart-5843e572-1c4f-4bab-aaa1-e0dade9b5033
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211205189 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.2211205189
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.365110070
Short name T217
Test name
Test status
Simulation time 24938488 ps
CPU time 1.17 seconds
Started Jul 20 06:49:15 PM PDT 24
Finished Jul 20 06:49:17 PM PDT 24
Peak memory 220008 kb
Host smart-4eb43538-519d-421f-b3bf-c125bc215988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365110070 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.365110070
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.3710085033
Short name T582
Test name
Test status
Simulation time 47708770 ps
CPU time 1.16 seconds
Started Jul 20 06:49:19 PM PDT 24
Finished Jul 20 06:49:21 PM PDT 24
Peak memory 217464 kb
Host smart-e45e52bd-2fb1-4757-83e0-6671f580a594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710085033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.3710085033
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.1156476901
Short name T98
Test name
Test status
Simulation time 31832464 ps
CPU time 0.86 seconds
Started Jul 20 06:49:19 PM PDT 24
Finished Jul 20 06:49:21 PM PDT 24
Peak memory 215900 kb
Host smart-47be3fc1-a65f-49e7-8da6-c60f9ba65060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156476901 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.1156476901
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.449693979
Short name T25
Test name
Test status
Simulation time 56641477 ps
CPU time 0.93 seconds
Started Jul 20 06:49:15 PM PDT 24
Finished Jul 20 06:49:16 PM PDT 24
Peak memory 207372 kb
Host smart-5f5a1f84-f469-49fa-9d36-c06476586106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449693979 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.449693979
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.78316898
Short name T955
Test name
Test status
Simulation time 16070678 ps
CPU time 1.03 seconds
Started Jul 20 06:49:14 PM PDT 24
Finished Jul 20 06:49:15 PM PDT 24
Peak memory 215564 kb
Host smart-5276672f-898e-433b-9958-d156af2b1fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78316898 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.78316898
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.3014290037
Short name T652
Test name
Test status
Simulation time 1776534689 ps
CPU time 4.09 seconds
Started Jul 20 06:49:15 PM PDT 24
Finished Jul 20 06:49:20 PM PDT 24
Peak memory 217608 kb
Host smart-bdec126e-23bb-466a-9342-c4f63cec1acd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014290037 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.3014290037
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.3611501398
Short name T964
Test name
Test status
Simulation time 43942434156 ps
CPU time 1125.95 seconds
Started Jul 20 06:49:14 PM PDT 24
Finished Jul 20 07:08:00 PM PDT 24
Peak memory 221836 kb
Host smart-28803761-c76a-4e63-b8ee-eb11e59ce5be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611501398 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.3611501398
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.2022935752
Short name T710
Test name
Test status
Simulation time 44891673 ps
CPU time 1.18 seconds
Started Jul 20 06:50:41 PM PDT 24
Finished Jul 20 06:50:45 PM PDT 24
Peak memory 220672 kb
Host smart-079fcb6a-ccc7-429a-a2b7-bd14776438c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022935752 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.2022935752
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.1371440029
Short name T886
Test name
Test status
Simulation time 18409954 ps
CPU time 1 seconds
Started Jul 20 06:50:40 PM PDT 24
Finished Jul 20 06:50:43 PM PDT 24
Peak memory 218752 kb
Host smart-3a9902f0-1f77-4af3-b387-a49127733cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371440029 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.1371440029
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.4079558403
Short name T724
Test name
Test status
Simulation time 80845303 ps
CPU time 1.23 seconds
Started Jul 20 06:50:45 PM PDT 24
Finished Jul 20 06:50:47 PM PDT 24
Peak memory 217636 kb
Host smart-56768d06-c34a-470d-b07d-aca63bd10e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079558403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.4079558403
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.3360078157
Short name T440
Test name
Test status
Simulation time 99318546 ps
CPU time 1.27 seconds
Started Jul 20 06:50:38 PM PDT 24
Finished Jul 20 06:50:40 PM PDT 24
Peak memory 216092 kb
Host smart-46690625-e87c-41a5-b3fe-10cb119b32f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360078157 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.3360078157
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.341186537
Short name T693
Test name
Test status
Simulation time 50081701 ps
CPU time 0.89 seconds
Started Jul 20 06:50:40 PM PDT 24
Finished Jul 20 06:50:42 PM PDT 24
Peak memory 218520 kb
Host smart-118302ab-d758-4788-9207-470830d195f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341186537 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.341186537
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.2832153765
Short name T885
Test name
Test status
Simulation time 100086412 ps
CPU time 1.75 seconds
Started Jul 20 06:50:45 PM PDT 24
Finished Jul 20 06:50:48 PM PDT 24
Peak memory 220688 kb
Host smart-cdba80f1-a058-496b-93ce-0658720be4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832153765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.2832153765
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.579713481
Short name T245
Test name
Test status
Simulation time 88209326 ps
CPU time 1.19 seconds
Started Jul 20 06:50:44 PM PDT 24
Finished Jul 20 06:50:47 PM PDT 24
Peak memory 218868 kb
Host smart-57b96c79-165b-4b38-b178-1cc56c4217d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579713481 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.579713481
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.3899115418
Short name T426
Test name
Test status
Simulation time 54330733 ps
CPU time 1.27 seconds
Started Jul 20 06:50:42 PM PDT 24
Finished Jul 20 06:50:46 PM PDT 24
Peak memory 219904 kb
Host smart-f7ce6ec0-e4ea-4f1b-a352-1f72fe28b11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899115418 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3899115418
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.749482354
Short name T981
Test name
Test status
Simulation time 216041843 ps
CPU time 3.44 seconds
Started Jul 20 06:50:39 PM PDT 24
Finished Jul 20 06:50:44 PM PDT 24
Peak memory 217924 kb
Host smart-41da1f01-f652-4233-9341-83e5d575b01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749482354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.749482354
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.3710683501
Short name T799
Test name
Test status
Simulation time 153125897 ps
CPU time 1.12 seconds
Started Jul 20 06:50:43 PM PDT 24
Finished Jul 20 06:50:46 PM PDT 24
Peak memory 216012 kb
Host smart-be2f61ad-d661-4d1e-801f-a2e399abf81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710683501 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.3710683501
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.2954202249
Short name T911
Test name
Test status
Simulation time 28378824 ps
CPU time 1.3 seconds
Started Jul 20 06:50:40 PM PDT 24
Finished Jul 20 06:50:44 PM PDT 24
Peak memory 220864 kb
Host smart-418a2208-8fb4-4e3c-abc4-e420a5011f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954202249 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.2954202249
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1321388627
Short name T434
Test name
Test status
Simulation time 39974982 ps
CPU time 1.46 seconds
Started Jul 20 06:50:40 PM PDT 24
Finished Jul 20 06:50:43 PM PDT 24
Peak memory 220096 kb
Host smart-3bffa70a-115a-431e-af34-2cbd2cad59a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321388627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1321388627
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.1531001280
Short name T550
Test name
Test status
Simulation time 30407762 ps
CPU time 1.32 seconds
Started Jul 20 06:50:40 PM PDT 24
Finished Jul 20 06:50:44 PM PDT 24
Peak memory 216004 kb
Host smart-2228a40e-3319-4d50-9e4a-b9e82a84586d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531001280 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.1531001280
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.3332713871
Short name T150
Test name
Test status
Simulation time 26881468 ps
CPU time 1.37 seconds
Started Jul 20 06:50:40 PM PDT 24
Finished Jul 20 06:50:45 PM PDT 24
Peak memory 230028 kb
Host smart-223c8859-23a3-434e-916d-c8e002752430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332713871 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.3332713871
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.1447226208
Short name T398
Test name
Test status
Simulation time 64831040 ps
CPU time 1.57 seconds
Started Jul 20 06:50:38 PM PDT 24
Finished Jul 20 06:50:42 PM PDT 24
Peak memory 218728 kb
Host smart-a4bcfc6e-1121-4479-b82e-266f70bdc3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447226208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.1447226208
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.2567075569
Short name T187
Test name
Test status
Simulation time 25888037 ps
CPU time 1.19 seconds
Started Jul 20 06:50:40 PM PDT 24
Finished Jul 20 06:50:44 PM PDT 24
Peak memory 219284 kb
Host smart-0d3d001f-c8c8-4a32-8560-5f117d6651d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567075569 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.2567075569
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.2837174042
Short name T395
Test name
Test status
Simulation time 18344640 ps
CPU time 1.05 seconds
Started Jul 20 06:50:42 PM PDT 24
Finished Jul 20 06:50:46 PM PDT 24
Peak memory 218844 kb
Host smart-b3e7aced-8619-4565-be62-cdf2845f6a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837174042 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.2837174042
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.3573243174
Short name T739
Test name
Test status
Simulation time 81746192 ps
CPU time 1.28 seconds
Started Jul 20 06:50:42 PM PDT 24
Finished Jul 20 06:50:46 PM PDT 24
Peak memory 218064 kb
Host smart-c699287f-32d9-4cad-9632-db056614fdd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573243174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.3573243174
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.691136951
Short name T140
Test name
Test status
Simulation time 87033489 ps
CPU time 1.23 seconds
Started Jul 20 06:50:42 PM PDT 24
Finished Jul 20 06:50:46 PM PDT 24
Peak memory 219868 kb
Host smart-f08e1ae0-9a6d-467b-a076-842558579a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691136951 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.691136951
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.3453660720
Short name T357
Test name
Test status
Simulation time 23048005 ps
CPU time 0.88 seconds
Started Jul 20 06:50:42 PM PDT 24
Finished Jul 20 06:50:45 PM PDT 24
Peak memory 218488 kb
Host smart-4207d61e-0ba8-4561-97b2-24e49d93fd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453660720 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.3453660720
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.2224176078
Short name T760
Test name
Test status
Simulation time 79263481 ps
CPU time 1.52 seconds
Started Jul 20 06:50:40 PM PDT 24
Finished Jul 20 06:50:45 PM PDT 24
Peak memory 218688 kb
Host smart-6e981912-f060-491f-a6c6-964e117cd82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224176078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2224176078
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.865473020
Short name T530
Test name
Test status
Simulation time 39817069 ps
CPU time 1.18 seconds
Started Jul 20 06:50:38 PM PDT 24
Finished Jul 20 06:50:41 PM PDT 24
Peak memory 218952 kb
Host smart-98d36673-8530-4810-8490-ba49c6483179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865473020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.865473020
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.1003995538
Short name T215
Test name
Test status
Simulation time 34842051 ps
CPU time 1.5 seconds
Started Jul 20 06:50:41 PM PDT 24
Finished Jul 20 06:50:45 PM PDT 24
Peak memory 225828 kb
Host smart-d65e20a7-b832-4dfc-8b22-a7084288eed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003995538 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.1003995538
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.3689604884
Short name T833
Test name
Test status
Simulation time 44733458 ps
CPU time 1.25 seconds
Started Jul 20 06:50:39 PM PDT 24
Finished Jul 20 06:50:42 PM PDT 24
Peak memory 218624 kb
Host smart-8c41cf1c-cc79-4f09-bc3a-b7cb7000c77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689604884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.3689604884
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.1099061944
Short name T749
Test name
Test status
Simulation time 23360065 ps
CPU time 1.21 seconds
Started Jul 20 06:50:40 PM PDT 24
Finished Jul 20 06:50:45 PM PDT 24
Peak memory 220744 kb
Host smart-c915a734-806c-4352-a63b-ac850622ee0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099061944 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.1099061944
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.1782462956
Short name T8
Test name
Test status
Simulation time 35517898 ps
CPU time 1.1 seconds
Started Jul 20 06:50:37 PM PDT 24
Finished Jul 20 06:50:39 PM PDT 24
Peak memory 220920 kb
Host smart-019e60bd-1780-4722-adeb-088eb516bdf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782462956 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.1782462956
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.2951695931
Short name T334
Test name
Test status
Simulation time 67364668 ps
CPU time 1.09 seconds
Started Jul 20 06:50:40 PM PDT 24
Finished Jul 20 06:50:45 PM PDT 24
Peak memory 217700 kb
Host smart-0b986499-70c7-413c-b71b-b9034a759f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951695931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.2951695931
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.155464837
Short name T704
Test name
Test status
Simulation time 47376177 ps
CPU time 1.24 seconds
Started Jul 20 06:50:41 PM PDT 24
Finished Jul 20 06:50:45 PM PDT 24
Peak memory 219668 kb
Host smart-b67b4025-3c92-497e-ac4e-a0fa99964c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155464837 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.155464837
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.3938853992
Short name T403
Test name
Test status
Simulation time 19567488 ps
CPU time 1.1 seconds
Started Jul 20 06:50:42 PM PDT 24
Finished Jul 20 06:50:46 PM PDT 24
Peak memory 218832 kb
Host smart-51222931-2e82-448e-a8a4-e91011707a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938853992 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.3938853992
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.572977371
Short name T347
Test name
Test status
Simulation time 148727889 ps
CPU time 1.28 seconds
Started Jul 20 06:50:40 PM PDT 24
Finished Jul 20 06:50:43 PM PDT 24
Peak memory 217580 kb
Host smart-39c6247b-130a-4c02-b630-90bd9119fbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572977371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.572977371
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.1288407457
Short name T635
Test name
Test status
Simulation time 42532366 ps
CPU time 1.21 seconds
Started Jul 20 06:49:13 PM PDT 24
Finished Jul 20 06:49:14 PM PDT 24
Peak memory 219920 kb
Host smart-8a8b989b-2c10-4d47-a26f-8428653303d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288407457 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.1288407457
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.2560905949
Short name T957
Test name
Test status
Simulation time 39888111 ps
CPU time 0.9 seconds
Started Jul 20 06:49:20 PM PDT 24
Finished Jul 20 06:49:21 PM PDT 24
Peak memory 207156 kb
Host smart-8231f03f-d069-4d82-aa24-df06c17b07c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560905949 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2560905949
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.1282670894
Short name T513
Test name
Test status
Simulation time 120285800 ps
CPU time 0.88 seconds
Started Jul 20 06:49:14 PM PDT 24
Finished Jul 20 06:49:16 PM PDT 24
Peak memory 216540 kb
Host smart-8e13fcd2-a163-4486-b4c7-ac2b5814555a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282670894 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.1282670894
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.2229793757
Short name T714
Test name
Test status
Simulation time 32526469 ps
CPU time 1.25 seconds
Started Jul 20 06:49:19 PM PDT 24
Finished Jul 20 06:49:21 PM PDT 24
Peak memory 217148 kb
Host smart-a7ee3aad-dcf4-4f28-a51a-f54845d1683a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229793757 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.2229793757
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.4244371152
Short name T676
Test name
Test status
Simulation time 120292831 ps
CPU time 1.02 seconds
Started Jul 20 06:49:16 PM PDT 24
Finished Jul 20 06:49:17 PM PDT 24
Peak memory 224056 kb
Host smart-32b510d6-9c83-4504-9995-35013d32724d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244371152 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.4244371152
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.38010139
Short name T615
Test name
Test status
Simulation time 128570331 ps
CPU time 1.03 seconds
Started Jul 20 06:49:11 PM PDT 24
Finished Jul 20 06:49:13 PM PDT 24
Peak memory 217836 kb
Host smart-b9874ea8-1aca-465c-a1b4-d8231ab4337a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38010139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.38010139
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.2501601073
Short name T27
Test name
Test status
Simulation time 22326391 ps
CPU time 1.05 seconds
Started Jul 20 06:49:16 PM PDT 24
Finished Jul 20 06:49:17 PM PDT 24
Peak memory 216988 kb
Host smart-e9ae8709-26be-404a-b13d-45fa3432281e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501601073 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2501601073
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.4089014813
Short name T661
Test name
Test status
Simulation time 20654572 ps
CPU time 1.01 seconds
Started Jul 20 06:49:13 PM PDT 24
Finished Jul 20 06:49:15 PM PDT 24
Peak memory 207360 kb
Host smart-896d0804-c4a5-424e-a3e9-8d960ab98954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089014813 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.4089014813
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.2859724332
Short name T624
Test name
Test status
Simulation time 43222897 ps
CPU time 0.92 seconds
Started Jul 20 06:49:12 PM PDT 24
Finished Jul 20 06:49:13 PM PDT 24
Peak memory 215600 kb
Host smart-62c1b4c6-488b-46f0-8770-1a2ddac266e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859724332 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.2859724332
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.215206824
Short name T969
Test name
Test status
Simulation time 213809282 ps
CPU time 4.3 seconds
Started Jul 20 06:49:14 PM PDT 24
Finished Jul 20 06:49:19 PM PDT 24
Peak memory 217316 kb
Host smart-6c2e18c3-b99d-4a84-ba52-22b1aedcee06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215206824 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.215206824
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.1102000981
Short name T468
Test name
Test status
Simulation time 242142427363 ps
CPU time 1196.66 seconds
Started Jul 20 06:49:13 PM PDT 24
Finished Jul 20 07:09:11 PM PDT 24
Peak memory 221904 kb
Host smart-ee66a3b6-31df-4a7e-8b61-14cb06f96e81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102000981 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.1102000981
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.2574974045
Short name T220
Test name
Test status
Simulation time 88361372 ps
CPU time 1.22 seconds
Started Jul 20 06:50:38 PM PDT 24
Finished Jul 20 06:50:41 PM PDT 24
Peak memory 219276 kb
Host smart-6da3c236-d0a2-42a9-bec6-79f0c7d4f453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574974045 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.2574974045
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.1193788241
Short name T173
Test name
Test status
Simulation time 44560496 ps
CPU time 0.85 seconds
Started Jul 20 06:50:39 PM PDT 24
Finished Jul 20 06:50:42 PM PDT 24
Peak memory 218636 kb
Host smart-38c9969a-d935-41ca-a9de-285a4b695c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193788241 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.1193788241
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.3383564073
Short name T40
Test name
Test status
Simulation time 29656459 ps
CPU time 1.34 seconds
Started Jul 20 06:50:38 PM PDT 24
Finished Jul 20 06:50:40 PM PDT 24
Peak memory 217816 kb
Host smart-da65eaf0-a3ed-4a35-8025-a13232ba452f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383564073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.3383564073
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.1006511897
Short name T176
Test name
Test status
Simulation time 26923365 ps
CPU time 1.26 seconds
Started Jul 20 06:50:42 PM PDT 24
Finished Jul 20 06:50:46 PM PDT 24
Peak memory 216032 kb
Host smart-0dc62dab-85fe-4277-8928-e05a58835b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006511897 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.1006511897
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.4098272867
Short name T636
Test name
Test status
Simulation time 31001347 ps
CPU time 0.88 seconds
Started Jul 20 06:50:42 PM PDT 24
Finished Jul 20 06:50:45 PM PDT 24
Peak memory 218624 kb
Host smart-2762cd8f-e2ac-4aee-a04e-3ff6e3d3170b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098272867 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.4098272867
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.2056472427
Short name T646
Test name
Test status
Simulation time 140733098 ps
CPU time 1.57 seconds
Started Jul 20 06:50:43 PM PDT 24
Finished Jul 20 06:50:47 PM PDT 24
Peak memory 218796 kb
Host smart-faf29307-d63d-4886-a31c-34f0c94831b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056472427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.2056472427
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.3376484337
Short name T847
Test name
Test status
Simulation time 242877076 ps
CPU time 1.21 seconds
Started Jul 20 06:50:39 PM PDT 24
Finished Jul 20 06:50:42 PM PDT 24
Peak memory 219520 kb
Host smart-2aa613ab-0722-4b9a-909f-a417cdfd011a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376484337 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.3376484337
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.383071752
Short name T623
Test name
Test status
Simulation time 75179117 ps
CPU time 0.82 seconds
Started Jul 20 06:50:47 PM PDT 24
Finished Jul 20 06:50:49 PM PDT 24
Peak memory 215608 kb
Host smart-d4f74478-134d-47ae-a516-43eec7e3e3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383071752 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.383071752
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.2116937981
Short name T727
Test name
Test status
Simulation time 34985288 ps
CPU time 1.37 seconds
Started Jul 20 06:50:39 PM PDT 24
Finished Jul 20 06:50:43 PM PDT 24
Peak memory 218728 kb
Host smart-27f283dc-003e-43ff-951e-c1960fcc51c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116937981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.2116937981
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.1083008795
Short name T627
Test name
Test status
Simulation time 23714826 ps
CPU time 1.21 seconds
Started Jul 20 06:50:47 PM PDT 24
Finished Jul 20 06:50:49 PM PDT 24
Peak memory 219072 kb
Host smart-71965a87-2af0-4bc8-9098-78d7415db893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083008795 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.1083008795
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.2291610528
Short name T157
Test name
Test status
Simulation time 81990140 ps
CPU time 1.2 seconds
Started Jul 20 06:50:52 PM PDT 24
Finished Jul 20 06:50:55 PM PDT 24
Peak memory 226100 kb
Host smart-2ddc4b25-3d79-4bac-a2e5-1b60cf1c45f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291610528 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.2291610528
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/84.edn_err.3967848094
Short name T629
Test name
Test status
Simulation time 54950780 ps
CPU time 0.98 seconds
Started Jul 20 06:50:46 PM PDT 24
Finished Jul 20 06:50:48 PM PDT 24
Peak memory 221092 kb
Host smart-e2d2c871-a027-45b0-a3c8-438c615b9bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967848094 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.3967848094
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.93974543
Short name T87
Test name
Test status
Simulation time 88657632 ps
CPU time 1.33 seconds
Started Jul 20 06:50:46 PM PDT 24
Finished Jul 20 06:50:48 PM PDT 24
Peak memory 218940 kb
Host smart-f92badbe-281c-429e-8e7b-37e01a9db10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93974543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.93974543
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.4083935709
Short name T194
Test name
Test status
Simulation time 86310636 ps
CPU time 1.29 seconds
Started Jul 20 06:50:47 PM PDT 24
Finished Jul 20 06:50:49 PM PDT 24
Peak memory 215992 kb
Host smart-86c84136-c53d-4152-93e1-788541f34515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083935709 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.4083935709
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.1323453877
Short name T185
Test name
Test status
Simulation time 21186717 ps
CPU time 1.03 seconds
Started Jul 20 06:50:52 PM PDT 24
Finished Jul 20 06:50:55 PM PDT 24
Peak memory 218924 kb
Host smart-98353d57-a739-40d8-9266-11adeecaa91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323453877 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.1323453877
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.1687596941
Short name T356
Test name
Test status
Simulation time 78441110 ps
CPU time 1.39 seconds
Started Jul 20 06:50:52 PM PDT 24
Finished Jul 20 06:50:55 PM PDT 24
Peak memory 219336 kb
Host smart-073b5db3-03c9-4cba-bd34-c73129f35d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687596941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.1687596941
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.981585291
Short name T448
Test name
Test status
Simulation time 27539228 ps
CPU time 1.26 seconds
Started Jul 20 06:50:48 PM PDT 24
Finished Jul 20 06:50:50 PM PDT 24
Peak memory 220464 kb
Host smart-b4904171-9c9c-4143-b6de-b6d1fea0d4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981585291 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.981585291
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.246709994
Short name T699
Test name
Test status
Simulation time 41049405 ps
CPU time 1.37 seconds
Started Jul 20 06:50:49 PM PDT 24
Finished Jul 20 06:50:51 PM PDT 24
Peak memory 215888 kb
Host smart-67e07422-2fed-43b0-8148-58125f96f582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246709994 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.246709994
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.2595035073
Short name T494
Test name
Test status
Simulation time 104183904 ps
CPU time 1.08 seconds
Started Jul 20 06:50:49 PM PDT 24
Finished Jul 20 06:50:51 PM PDT 24
Peak memory 217516 kb
Host smart-c89240df-7de3-49e8-ba59-dfc84221802c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595035073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.2595035073
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.3510401528
Short name T130
Test name
Test status
Simulation time 29551223 ps
CPU time 1.25 seconds
Started Jul 20 06:50:51 PM PDT 24
Finished Jul 20 06:50:53 PM PDT 24
Peak memory 219928 kb
Host smart-104039af-ab8e-4ed5-9b70-7aa2be8e5955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510401528 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.3510401528
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.1091729678
Short name T573
Test name
Test status
Simulation time 32267790 ps
CPU time 1.45 seconds
Started Jul 20 06:50:49 PM PDT 24
Finished Jul 20 06:50:51 PM PDT 24
Peak memory 225980 kb
Host smart-037dc131-00be-40f7-99b4-bd059775af05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091729678 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.1091729678
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.3305393481
Short name T547
Test name
Test status
Simulation time 43250642 ps
CPU time 1.11 seconds
Started Jul 20 06:50:47 PM PDT 24
Finished Jul 20 06:50:49 PM PDT 24
Peak memory 217544 kb
Host smart-1107a4b8-4e8c-41d1-b152-69a8a0c66145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305393481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.3305393481
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.2399482882
Short name T123
Test name
Test status
Simulation time 40146657 ps
CPU time 1.18 seconds
Started Jul 20 06:50:46 PM PDT 24
Finished Jul 20 06:50:48 PM PDT 24
Peak memory 219776 kb
Host smart-9be592c3-10c0-4941-98bf-9c3cb83db2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399482882 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.2399482882
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.1455378344
Short name T149
Test name
Test status
Simulation time 34014660 ps
CPU time 0.99 seconds
Started Jul 20 06:50:48 PM PDT 24
Finished Jul 20 06:50:50 PM PDT 24
Peak memory 220064 kb
Host smart-404e2783-ce03-4f27-bc1f-b55430194d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455378344 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.1455378344
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.234204252
Short name T368
Test name
Test status
Simulation time 34846012 ps
CPU time 1.58 seconds
Started Jul 20 06:50:50 PM PDT 24
Finished Jul 20 06:50:53 PM PDT 24
Peak memory 218932 kb
Host smart-5029f595-f256-47a3-8a6c-786c6b7956d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234204252 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.234204252
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.3556089287
Short name T575
Test name
Test status
Simulation time 64878571 ps
CPU time 1.1 seconds
Started Jul 20 06:50:51 PM PDT 24
Finished Jul 20 06:50:53 PM PDT 24
Peak memory 220720 kb
Host smart-63ef68f3-de0e-42e7-b8b0-65b4ff628dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556089287 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.3556089287
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.808295594
Short name T592
Test name
Test status
Simulation time 62082451 ps
CPU time 0.88 seconds
Started Jul 20 06:50:46 PM PDT 24
Finished Jul 20 06:50:48 PM PDT 24
Peak memory 218496 kb
Host smart-129edf67-9bf9-4e9d-b736-7f4d08a435c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808295594 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.808295594
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.854738312
Short name T694
Test name
Test status
Simulation time 105008093 ps
CPU time 1.26 seconds
Started Jul 20 06:50:52 PM PDT 24
Finished Jul 20 06:50:54 PM PDT 24
Peak memory 219428 kb
Host smart-a6954b34-6861-4b33-bf00-955fc070d273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854738312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.854738312
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.817253688
Short name T817
Test name
Test status
Simulation time 63392299 ps
CPU time 1.09 seconds
Started Jul 20 06:49:24 PM PDT 24
Finished Jul 20 06:49:26 PM PDT 24
Peak memory 220008 kb
Host smart-f64808be-e487-47e2-b3b3-b5dd83865163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817253688 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.817253688
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.2854355041
Short name T660
Test name
Test status
Simulation time 69029862 ps
CPU time 0.94 seconds
Started Jul 20 06:49:24 PM PDT 24
Finished Jul 20 06:49:27 PM PDT 24
Peak memory 207052 kb
Host smart-dd4cf0d5-f9e0-4e1b-b6e1-e688530d4f02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854355041 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.2854355041
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.4194917618
Short name T191
Test name
Test status
Simulation time 23511162 ps
CPU time 0.91 seconds
Started Jul 20 06:49:26 PM PDT 24
Finished Jul 20 06:49:28 PM PDT 24
Peak memory 216516 kb
Host smart-ba3c34b8-231d-4f90-8bc8-21760bad6421
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194917618 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.4194917618
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_err.3183117160
Short name T53
Test name
Test status
Simulation time 70764420 ps
CPU time 0.98 seconds
Started Jul 20 06:49:24 PM PDT 24
Finished Jul 20 06:49:27 PM PDT 24
Peak memory 224068 kb
Host smart-8b43aae1-4955-43f9-bd4d-6322e7bc52c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183117160 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.3183117160
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.3178103991
Short name T720
Test name
Test status
Simulation time 57605236 ps
CPU time 1.33 seconds
Started Jul 20 06:49:16 PM PDT 24
Finished Jul 20 06:49:19 PM PDT 24
Peak memory 217464 kb
Host smart-84652349-c2d2-410b-a7d7-ba79dfd052a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178103991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.3178103991
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.3362482747
Short name T915
Test name
Test status
Simulation time 27579677 ps
CPU time 1.01 seconds
Started Jul 20 06:49:12 PM PDT 24
Finished Jul 20 06:49:14 PM PDT 24
Peak memory 215756 kb
Host smart-990efff4-1375-4216-b406-2c5e4428fbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362482747 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.3362482747
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.4287507012
Short name T539
Test name
Test status
Simulation time 19159918 ps
CPU time 1.06 seconds
Started Jul 20 06:49:17 PM PDT 24
Finished Jul 20 06:49:18 PM PDT 24
Peak memory 207292 kb
Host smart-aa0bddcd-cd57-4b50-a81c-2232f068b657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287507012 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.4287507012
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.1130407604
Short name T876
Test name
Test status
Simulation time 55487731 ps
CPU time 0.92 seconds
Started Jul 20 06:49:21 PM PDT 24
Finished Jul 20 06:49:22 PM PDT 24
Peak memory 215588 kb
Host smart-29ffa9e4-cdd9-4991-baa4-badca069a27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130407604 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.1130407604
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1105920261
Short name T69
Test name
Test status
Simulation time 333834104 ps
CPU time 2.43 seconds
Started Jul 20 06:49:15 PM PDT 24
Finished Jul 20 06:49:18 PM PDT 24
Peak memory 215592 kb
Host smart-e40bb731-5460-427a-9b64-a4798767721e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105920261 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1105920261
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.649016759
Short name T226
Test name
Test status
Simulation time 111410624801 ps
CPU time 1051.58 seconds
Started Jul 20 06:49:13 PM PDT 24
Finished Jul 20 07:06:45 PM PDT 24
Peak memory 223920 kb
Host smart-909ba792-c4fe-4854-bdf1-5341bd2359a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649016759 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.649016759
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.1140865367
Short name T792
Test name
Test status
Simulation time 41906808 ps
CPU time 1.09 seconds
Started Jul 20 06:50:50 PM PDT 24
Finished Jul 20 06:50:52 PM PDT 24
Peak memory 220000 kb
Host smart-9eb39c45-ca91-4537-9d3b-52609492bf92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140865367 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.1140865367
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.1635813404
Short name T17
Test name
Test status
Simulation time 31360397 ps
CPU time 1.05 seconds
Started Jul 20 06:50:49 PM PDT 24
Finished Jul 20 06:50:51 PM PDT 24
Peak memory 229660 kb
Host smart-a1b74860-7049-4a36-be4a-ef1e0d7dcc02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635813404 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.1635813404
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.2230408098
Short name T861
Test name
Test status
Simulation time 45837124 ps
CPU time 1.29 seconds
Started Jul 20 06:50:52 PM PDT 24
Finished Jul 20 06:50:55 PM PDT 24
Peak memory 217656 kb
Host smart-56ab19ce-42cf-4f1f-b776-938318eb4404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230408098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.2230408098
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.2646688921
Short name T794
Test name
Test status
Simulation time 99615629 ps
CPU time 1.21 seconds
Started Jul 20 06:50:52 PM PDT 24
Finished Jul 20 06:50:55 PM PDT 24
Peak memory 220024 kb
Host smart-a41688a4-c0ca-4eb4-86b7-1291148ad4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646688921 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.2646688921
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.2133114919
Short name T940
Test name
Test status
Simulation time 18350047 ps
CPU time 1.02 seconds
Started Jul 20 06:50:48 PM PDT 24
Finished Jul 20 06:50:50 PM PDT 24
Peak memory 218852 kb
Host smart-8b1526f9-f06c-45d4-9852-18f7b10f3cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133114919 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.2133114919
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.666509893
Short name T447
Test name
Test status
Simulation time 79245779 ps
CPU time 1.39 seconds
Started Jul 20 06:50:47 PM PDT 24
Finished Jul 20 06:50:49 PM PDT 24
Peak memory 219000 kb
Host smart-2ae9bd14-8996-4b91-8f35-f70a67966304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666509893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.666509893
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.103069764
Short name T244
Test name
Test status
Simulation time 94601665 ps
CPU time 1.29 seconds
Started Jul 20 06:50:54 PM PDT 24
Finished Jul 20 06:50:57 PM PDT 24
Peak memory 220072 kb
Host smart-65e17b2f-3bf2-4c7e-815e-8b2e2a82aaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103069764 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.103069764
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.3509972650
Short name T181
Test name
Test status
Simulation time 30096367 ps
CPU time 0.88 seconds
Started Jul 20 06:50:47 PM PDT 24
Finished Jul 20 06:50:49 PM PDT 24
Peak memory 218540 kb
Host smart-c7b545cd-6ab9-4bf0-b0a3-00a2fd51cfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509972650 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3509972650
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.2137624493
Short name T759
Test name
Test status
Simulation time 51201994 ps
CPU time 1.02 seconds
Started Jul 20 06:50:50 PM PDT 24
Finished Jul 20 06:50:52 PM PDT 24
Peak memory 217468 kb
Host smart-38e9da97-8b0b-4c7d-b3a2-cbfccbfede0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137624493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.2137624493
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.281456351
Short name T744
Test name
Test status
Simulation time 234623800 ps
CPU time 1.34 seconds
Started Jul 20 06:50:48 PM PDT 24
Finished Jul 20 06:50:50 PM PDT 24
Peak memory 220428 kb
Host smart-f923b542-c0de-4525-8c0f-0828ba26d200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281456351 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.281456351
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.2364713911
Short name T854
Test name
Test status
Simulation time 22950026 ps
CPU time 1.13 seconds
Started Jul 20 06:50:54 PM PDT 24
Finished Jul 20 06:50:57 PM PDT 24
Peak memory 219048 kb
Host smart-e260efb6-3940-41bf-9d8e-4c9c3d9a2911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364713911 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.2364713911
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.1165283139
Short name T804
Test name
Test status
Simulation time 21640314 ps
CPU time 1.08 seconds
Started Jul 20 06:50:52 PM PDT 24
Finished Jul 20 06:50:55 PM PDT 24
Peak memory 217512 kb
Host smart-5b01ac10-56a6-4be3-8228-c3786658e977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165283139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.1165283139
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.1896060794
Short name T593
Test name
Test status
Simulation time 45954170 ps
CPU time 1.21 seconds
Started Jul 20 06:50:52 PM PDT 24
Finished Jul 20 06:50:55 PM PDT 24
Peak memory 219380 kb
Host smart-2d9ceb62-acd2-4456-ba55-1f205e4dc30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896060794 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.1896060794
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.1984109499
Short name T115
Test name
Test status
Simulation time 26641608 ps
CPU time 1.24 seconds
Started Jul 20 06:50:54 PM PDT 24
Finished Jul 20 06:50:57 PM PDT 24
Peak memory 221048 kb
Host smart-79cafed6-49b8-4149-adf2-6452497a0407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984109499 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.1984109499
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.232100039
Short name T331
Test name
Test status
Simulation time 51861779 ps
CPU time 1.31 seconds
Started Jul 20 06:50:52 PM PDT 24
Finished Jul 20 06:50:54 PM PDT 24
Peak memory 219088 kb
Host smart-3b3004bb-b0a8-4581-ba4a-3c52df2fc524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232100039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.232100039
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.2459067419
Short name T670
Test name
Test status
Simulation time 40171519 ps
CPU time 1.15 seconds
Started Jul 20 06:50:48 PM PDT 24
Finished Jul 20 06:50:50 PM PDT 24
Peak memory 221036 kb
Host smart-f255ae2b-b33a-4927-9c30-d08a01525c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459067419 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.2459067419
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.3846937830
Short name T168
Test name
Test status
Simulation time 23404584 ps
CPU time 0.9 seconds
Started Jul 20 06:50:47 PM PDT 24
Finished Jul 20 06:50:49 PM PDT 24
Peak memory 218932 kb
Host smart-74aca3fb-3f1f-4418-a407-4ecc09a6a3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846937830 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.3846937830
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.154144230
Short name T597
Test name
Test status
Simulation time 48919008 ps
CPU time 1.83 seconds
Started Jul 20 06:50:50 PM PDT 24
Finished Jul 20 06:50:53 PM PDT 24
Peak memory 218720 kb
Host smart-d0f70434-4080-40aa-b9d9-6d791170100b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154144230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.154144230
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.2077021763
Short name T973
Test name
Test status
Simulation time 65358536 ps
CPU time 1.09 seconds
Started Jul 20 06:50:52 PM PDT 24
Finished Jul 20 06:50:54 PM PDT 24
Peak memory 218952 kb
Host smart-3c94b01c-75dd-47f0-8a39-573e756a3855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077021763 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.2077021763
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.1588855207
Short name T144
Test name
Test status
Simulation time 27183694 ps
CPU time 1.39 seconds
Started Jul 20 06:50:50 PM PDT 24
Finished Jul 20 06:50:53 PM PDT 24
Peak memory 230056 kb
Host smart-dbb293c7-3a5b-4790-9c17-5ae66bdeae7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588855207 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.1588855207
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.4174080852
Short name T507
Test name
Test status
Simulation time 65480804 ps
CPU time 1.32 seconds
Started Jul 20 06:50:50 PM PDT 24
Finished Jul 20 06:50:53 PM PDT 24
Peak memory 217780 kb
Host smart-8ea3f517-81a8-4e40-a383-df8db9970735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174080852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.4174080852
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.245611208
Short name T895
Test name
Test status
Simulation time 88921862 ps
CPU time 1.24 seconds
Started Jul 20 06:50:50 PM PDT 24
Finished Jul 20 06:50:52 PM PDT 24
Peak memory 219776 kb
Host smart-ab2581a3-7dea-450c-992d-1a00ae4088e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245611208 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.245611208
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.15367990
Short name T338
Test name
Test status
Simulation time 19716706 ps
CPU time 1.02 seconds
Started Jul 20 06:50:52 PM PDT 24
Finished Jul 20 06:50:54 PM PDT 24
Peak memory 218912 kb
Host smart-3c2857ca-6065-4745-9c2d-703560b211c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15367990 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.15367990
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.3144592212
Short name T20
Test name
Test status
Simulation time 44023056 ps
CPU time 1.25 seconds
Started Jul 20 06:50:52 PM PDT 24
Finished Jul 20 06:50:55 PM PDT 24
Peak memory 220264 kb
Host smart-af8ff1ab-6057-4100-b58a-fb84db754abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144592212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.3144592212
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.958178836
Short name T750
Test name
Test status
Simulation time 89672859 ps
CPU time 1.24 seconds
Started Jul 20 06:50:50 PM PDT 24
Finished Jul 20 06:50:53 PM PDT 24
Peak memory 218884 kb
Host smart-9710125f-bdda-4bd6-b1e5-a5a19794b762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958178836 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.958178836
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.4235768520
Short name T199
Test name
Test status
Simulation time 65480039 ps
CPU time 0.95 seconds
Started Jul 20 06:50:52 PM PDT 24
Finished Jul 20 06:50:54 PM PDT 24
Peak memory 229712 kb
Host smart-75c854cc-3447-44f8-a7ed-911005798db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235768520 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.4235768520
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2980073777
Short name T320
Test name
Test status
Simulation time 112778928 ps
CPU time 1.51 seconds
Started Jul 20 06:50:50 PM PDT 24
Finished Jul 20 06:50:53 PM PDT 24
Peak memory 219452 kb
Host smart-3af65d5e-7d2b-494e-9018-4ee7a3d8cbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980073777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2980073777
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.2619301500
Short name T411
Test name
Test status
Simulation time 76993260 ps
CPU time 1.09 seconds
Started Jul 20 06:50:53 PM PDT 24
Finished Jul 20 06:50:56 PM PDT 24
Peak memory 218912 kb
Host smart-65783acf-6391-4cc4-abeb-87ced506b052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619301500 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.2619301500
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.3584539683
Short name T162
Test name
Test status
Simulation time 18440146 ps
CPU time 1.07 seconds
Started Jul 20 06:50:48 PM PDT 24
Finished Jul 20 06:50:50 PM PDT 24
Peak memory 218616 kb
Host smart-397addc6-ac00-406a-a9af-b073a7640193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584539683 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.3584539683
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.1608610814
Short name T358
Test name
Test status
Simulation time 21412518 ps
CPU time 1.07 seconds
Started Jul 20 06:50:52 PM PDT 24
Finished Jul 20 06:50:54 PM PDT 24
Peak memory 219508 kb
Host smart-59c0f2cd-1543-4501-a83f-37c4d5721611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608610814 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.1608610814
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%