Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.55 98.25 93.91 96.97 91.28 96.37 99.77 92.28


Total test records in report: 1130
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T1026 /workspace/coverage/cover_reg_top/46.edn_intr_test.571884845 Jul 21 06:34:10 PM PDT 24 Jul 21 06:34:15 PM PDT 24 37274694 ps
T264 /workspace/coverage/cover_reg_top/14.edn_csr_rw.1465272164 Jul 21 06:33:54 PM PDT 24 Jul 21 06:34:00 PM PDT 24 101244050 ps
T1027 /workspace/coverage/cover_reg_top/31.edn_intr_test.2004651191 Jul 21 06:33:57 PM PDT 24 Jul 21 06:34:03 PM PDT 24 20163597 ps
T265 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.240600103 Jul 21 06:33:51 PM PDT 24 Jul 21 06:33:58 PM PDT 24 19799085 ps
T1028 /workspace/coverage/cover_reg_top/15.edn_tl_errors.1774614099 Jul 21 06:33:50 PM PDT 24 Jul 21 06:33:58 PM PDT 24 52406177 ps
T266 /workspace/coverage/cover_reg_top/9.edn_csr_rw.764648225 Jul 21 06:33:46 PM PDT 24 Jul 21 06:33:52 PM PDT 24 13305974 ps
T267 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1990866123 Jul 21 06:33:25 PM PDT 24 Jul 21 06:33:28 PM PDT 24 39617004 ps
T286 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.338312319 Jul 21 06:33:33 PM PDT 24 Jul 21 06:33:43 PM PDT 24 170533660 ps
T268 /workspace/coverage/cover_reg_top/4.edn_csr_rw.1279826348 Jul 21 06:33:36 PM PDT 24 Jul 21 06:33:46 PM PDT 24 54509661 ps
T246 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1576070683 Jul 21 06:33:27 PM PDT 24 Jul 21 06:33:31 PM PDT 24 20890997 ps
T1029 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3027237327 Jul 21 06:33:47 PM PDT 24 Jul 21 06:33:55 PM PDT 24 27871396 ps
T1030 /workspace/coverage/cover_reg_top/6.edn_intr_test.2286449600 Jul 21 06:33:45 PM PDT 24 Jul 21 06:33:52 PM PDT 24 15936501 ps
T1031 /workspace/coverage/cover_reg_top/18.edn_intr_test.2919908271 Jul 21 06:33:54 PM PDT 24 Jul 21 06:34:01 PM PDT 24 41134009 ps
T282 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.713296951 Jul 21 06:33:44 PM PDT 24 Jul 21 06:33:53 PM PDT 24 354302429 ps
T1032 /workspace/coverage/cover_reg_top/17.edn_intr_test.1366435585 Jul 21 06:33:54 PM PDT 24 Jul 21 06:34:00 PM PDT 24 11475394 ps
T247 /workspace/coverage/cover_reg_top/8.edn_csr_rw.2924296830 Jul 21 06:33:47 PM PDT 24 Jul 21 06:33:54 PM PDT 24 33696805 ps
T1033 /workspace/coverage/cover_reg_top/9.edn_tl_errors.4163255716 Jul 21 06:33:46 PM PDT 24 Jul 21 06:33:56 PM PDT 24 116453672 ps
T1034 /workspace/coverage/cover_reg_top/30.edn_intr_test.955412501 Jul 21 06:33:58 PM PDT 24 Jul 21 06:34:04 PM PDT 24 15939781 ps
T1035 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2881464897 Jul 21 06:33:46 PM PDT 24 Jul 21 06:33:52 PM PDT 24 39825008 ps
T255 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2644050047 Jul 21 06:33:32 PM PDT 24 Jul 21 06:33:44 PM PDT 24 134258803 ps
T1036 /workspace/coverage/cover_reg_top/38.edn_intr_test.1715362586 Jul 21 06:33:56 PM PDT 24 Jul 21 06:34:03 PM PDT 24 18498109 ps
T1037 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2709033717 Jul 21 06:33:46 PM PDT 24 Jul 21 06:33:53 PM PDT 24 30878603 ps
T1038 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3777148830 Jul 21 06:33:50 PM PDT 24 Jul 21 06:33:57 PM PDT 24 37942799 ps
T1039 /workspace/coverage/cover_reg_top/0.edn_csr_rw.4151094848 Jul 21 06:33:30 PM PDT 24 Jul 21 06:33:34 PM PDT 24 26935320 ps
T283 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2022689947 Jul 21 06:33:36 PM PDT 24 Jul 21 06:33:48 PM PDT 24 106638611 ps
T1040 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.700329401 Jul 21 06:33:44 PM PDT 24 Jul 21 06:33:51 PM PDT 24 76274781 ps
T1041 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1554300660 Jul 21 06:33:57 PM PDT 24 Jul 21 06:34:03 PM PDT 24 68041751 ps
T1042 /workspace/coverage/cover_reg_top/1.edn_intr_test.114128183 Jul 21 06:33:28 PM PDT 24 Jul 21 06:33:31 PM PDT 24 14877179 ps
T1043 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3558161415 Jul 21 06:33:31 PM PDT 24 Jul 21 06:33:38 PM PDT 24 108287910 ps
T1044 /workspace/coverage/cover_reg_top/17.edn_tl_errors.1743233409 Jul 21 06:33:50 PM PDT 24 Jul 21 06:33:58 PM PDT 24 50551299 ps
T1045 /workspace/coverage/cover_reg_top/7.edn_intr_test.1231338444 Jul 21 06:33:45 PM PDT 24 Jul 21 06:33:52 PM PDT 24 28558999 ps
T248 /workspace/coverage/cover_reg_top/19.edn_csr_rw.2120706970 Jul 21 06:33:58 PM PDT 24 Jul 21 06:34:04 PM PDT 24 71651972 ps
T1046 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.302161920 Jul 21 06:33:57 PM PDT 24 Jul 21 06:34:04 PM PDT 24 49047769 ps
T1047 /workspace/coverage/cover_reg_top/33.edn_intr_test.3037926212 Jul 21 06:33:57 PM PDT 24 Jul 21 06:34:03 PM PDT 24 16175264 ps
T1048 /workspace/coverage/cover_reg_top/13.edn_csr_rw.207196902 Jul 21 06:33:55 PM PDT 24 Jul 21 06:34:02 PM PDT 24 31410867 ps
T1049 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2466928282 Jul 21 06:33:43 PM PDT 24 Jul 21 06:33:51 PM PDT 24 41538309 ps
T1050 /workspace/coverage/cover_reg_top/23.edn_intr_test.1413020952 Jul 21 06:33:58 PM PDT 24 Jul 21 06:34:04 PM PDT 24 12625552 ps
T284 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1954915136 Jul 21 06:33:46 PM PDT 24 Jul 21 06:33:53 PM PDT 24 302425447 ps
T1051 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.731893752 Jul 21 06:33:45 PM PDT 24 Jul 21 06:33:53 PM PDT 24 452253175 ps
T1052 /workspace/coverage/cover_reg_top/49.edn_intr_test.332660951 Jul 21 06:34:06 PM PDT 24 Jul 21 06:34:11 PM PDT 24 20587909 ps
T1053 /workspace/coverage/cover_reg_top/34.edn_intr_test.3050218037 Jul 21 06:33:57 PM PDT 24 Jul 21 06:34:04 PM PDT 24 28944560 ps
T1054 /workspace/coverage/cover_reg_top/8.edn_tl_errors.1920402494 Jul 21 06:33:46 PM PDT 24 Jul 21 06:33:54 PM PDT 24 51828738 ps
T1055 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2905241777 Jul 21 06:33:36 PM PDT 24 Jul 21 06:33:47 PM PDT 24 61657178 ps
T1056 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.13063527 Jul 21 06:33:58 PM PDT 24 Jul 21 06:34:05 PM PDT 24 49488478 ps
T1057 /workspace/coverage/cover_reg_top/45.edn_intr_test.3271200349 Jul 21 06:34:05 PM PDT 24 Jul 21 06:34:09 PM PDT 24 89108687 ps
T1058 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2896009690 Jul 21 06:33:47 PM PDT 24 Jul 21 06:33:54 PM PDT 24 27805760 ps
T1059 /workspace/coverage/cover_reg_top/35.edn_intr_test.3971831958 Jul 21 06:33:56 PM PDT 24 Jul 21 06:34:03 PM PDT 24 46259269 ps
T1060 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3950149927 Jul 21 06:33:49 PM PDT 24 Jul 21 06:33:56 PM PDT 24 17151561 ps
T1061 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.304228978 Jul 21 06:33:25 PM PDT 24 Jul 21 06:33:29 PM PDT 24 167169837 ps
T1062 /workspace/coverage/cover_reg_top/19.edn_tl_errors.3434675919 Jul 21 06:33:59 PM PDT 24 Jul 21 06:34:07 PM PDT 24 80336959 ps
T1063 /workspace/coverage/cover_reg_top/43.edn_intr_test.341770907 Jul 21 06:33:58 PM PDT 24 Jul 21 06:34:05 PM PDT 24 18012288 ps
T1064 /workspace/coverage/cover_reg_top/18.edn_tl_errors.126881525 Jul 21 06:33:50 PM PDT 24 Jul 21 06:33:58 PM PDT 24 40190965 ps
T249 /workspace/coverage/cover_reg_top/3.edn_csr_rw.517344537 Jul 21 06:33:38 PM PDT 24 Jul 21 06:33:47 PM PDT 24 48880742 ps
T1065 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1489388659 Jul 21 06:33:57 PM PDT 24 Jul 21 06:34:04 PM PDT 24 49567554 ps
T1066 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2692918527 Jul 21 06:33:56 PM PDT 24 Jul 21 06:34:03 PM PDT 24 37216355 ps
T250 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1380794238 Jul 21 06:33:38 PM PDT 24 Jul 21 06:33:47 PM PDT 24 11385627 ps
T1067 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2546835666 Jul 21 06:33:51 PM PDT 24 Jul 21 06:33:59 PM PDT 24 317439356 ps
T1068 /workspace/coverage/cover_reg_top/12.edn_intr_test.2291960114 Jul 21 06:33:50 PM PDT 24 Jul 21 06:33:56 PM PDT 24 60471789 ps
T1069 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1233640265 Jul 21 06:33:36 PM PDT 24 Jul 21 06:33:47 PM PDT 24 65707538 ps
T1070 /workspace/coverage/cover_reg_top/4.edn_intr_test.4239694239 Jul 21 06:33:40 PM PDT 24 Jul 21 06:33:49 PM PDT 24 12060562 ps
T1071 /workspace/coverage/cover_reg_top/21.edn_intr_test.310615016 Jul 21 06:33:57 PM PDT 24 Jul 21 06:34:04 PM PDT 24 44855992 ps
T1072 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2561702191 Jul 21 06:33:32 PM PDT 24 Jul 21 06:33:41 PM PDT 24 42168589 ps
T1073 /workspace/coverage/cover_reg_top/22.edn_intr_test.1329281773 Jul 21 06:33:56 PM PDT 24 Jul 21 06:34:03 PM PDT 24 37228579 ps
T1074 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.878211241 Jul 21 06:33:55 PM PDT 24 Jul 21 06:34:01 PM PDT 24 25127990 ps
T287 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1468406116 Jul 21 06:33:50 PM PDT 24 Jul 21 06:34:00 PM PDT 24 553777169 ps
T1075 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2858512485 Jul 21 06:33:52 PM PDT 24 Jul 21 06:33:59 PM PDT 24 65113978 ps
T1076 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1967367261 Jul 21 06:33:54 PM PDT 24 Jul 21 06:34:01 PM PDT 24 368717718 ps
T1077 /workspace/coverage/cover_reg_top/11.edn_tl_errors.1400835543 Jul 21 06:33:50 PM PDT 24 Jul 21 06:33:59 PM PDT 24 360059664 ps
T1078 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3402065268 Jul 21 06:33:45 PM PDT 24 Jul 21 06:33:52 PM PDT 24 37579758 ps
T1079 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.480101819 Jul 21 06:33:37 PM PDT 24 Jul 21 06:33:47 PM PDT 24 32896079 ps
T1080 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.443117950 Jul 21 06:33:26 PM PDT 24 Jul 21 06:33:31 PM PDT 24 663478927 ps
T251 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.4258584216 Jul 21 06:33:30 PM PDT 24 Jul 21 06:33:33 PM PDT 24 14139900 ps
T1081 /workspace/coverage/cover_reg_top/25.edn_intr_test.954594091 Jul 21 06:33:57 PM PDT 24 Jul 21 06:34:04 PM PDT 24 176141523 ps
T1082 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.4076959467 Jul 21 06:33:49 PM PDT 24 Jul 21 06:33:56 PM PDT 24 61004298 ps
T1083 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3540846870 Jul 21 06:33:25 PM PDT 24 Jul 21 06:33:29 PM PDT 24 422086862 ps
T1084 /workspace/coverage/cover_reg_top/10.edn_tl_errors.1299694186 Jul 21 06:33:47 PM PDT 24 Jul 21 06:33:57 PM PDT 24 185785497 ps
T1085 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2940621552 Jul 21 06:33:59 PM PDT 24 Jul 21 06:34:05 PM PDT 24 76976826 ps
T252 /workspace/coverage/cover_reg_top/16.edn_csr_rw.2978833343 Jul 21 06:33:51 PM PDT 24 Jul 21 06:33:58 PM PDT 24 11739087 ps
T1086 /workspace/coverage/cover_reg_top/5.edn_intr_test.1289260199 Jul 21 06:33:45 PM PDT 24 Jul 21 06:33:52 PM PDT 24 15504532 ps
T1087 /workspace/coverage/cover_reg_top/4.edn_tl_errors.3861987918 Jul 21 06:33:36 PM PDT 24 Jul 21 06:33:47 PM PDT 24 20712411 ps
T1088 /workspace/coverage/cover_reg_top/8.edn_intr_test.629113721 Jul 21 06:33:47 PM PDT 24 Jul 21 06:33:53 PM PDT 24 61300508 ps
T1089 /workspace/coverage/cover_reg_top/18.edn_csr_rw.215176693 Jul 21 06:33:55 PM PDT 24 Jul 21 06:34:02 PM PDT 24 13462984 ps
T1090 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2301639962 Jul 21 06:33:33 PM PDT 24 Jul 21 06:33:43 PM PDT 24 117145991 ps
T1091 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3994548653 Jul 21 06:33:46 PM PDT 24 Jul 21 06:33:54 PM PDT 24 409558318 ps
T1092 /workspace/coverage/cover_reg_top/10.edn_csr_rw.1231893902 Jul 21 06:33:45 PM PDT 24 Jul 21 06:33:52 PM PDT 24 13089007 ps
T253 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2982066178 Jul 21 06:33:33 PM PDT 24 Jul 21 06:33:43 PM PDT 24 159890292 ps
T1093 /workspace/coverage/cover_reg_top/2.edn_tl_errors.974165341 Jul 21 06:33:31 PM PDT 24 Jul 21 06:33:37 PM PDT 24 176644944 ps
T254 /workspace/coverage/cover_reg_top/11.edn_csr_rw.2754808502 Jul 21 06:33:50 PM PDT 24 Jul 21 06:33:57 PM PDT 24 13045082 ps
T256 /workspace/coverage/cover_reg_top/6.edn_csr_rw.1453505788 Jul 21 06:33:43 PM PDT 24 Jul 21 06:33:51 PM PDT 24 40571164 ps
T1094 /workspace/coverage/cover_reg_top/48.edn_intr_test.2580081618 Jul 21 06:34:03 PM PDT 24 Jul 21 06:34:08 PM PDT 24 52806849 ps
T1095 /workspace/coverage/cover_reg_top/7.edn_tl_errors.1168490561 Jul 21 06:33:45 PM PDT 24 Jul 21 06:33:54 PM PDT 24 282548010 ps
T1096 /workspace/coverage/cover_reg_top/19.edn_intr_test.3394101425 Jul 21 06:33:57 PM PDT 24 Jul 21 06:34:04 PM PDT 24 59441948 ps
T1097 /workspace/coverage/cover_reg_top/16.edn_tl_errors.1700295294 Jul 21 06:33:52 PM PDT 24 Jul 21 06:34:00 PM PDT 24 77548336 ps
T1098 /workspace/coverage/cover_reg_top/47.edn_intr_test.3275955288 Jul 21 06:34:06 PM PDT 24 Jul 21 06:34:10 PM PDT 24 16823852 ps
T1099 /workspace/coverage/cover_reg_top/17.edn_csr_rw.886173975 Jul 21 06:33:51 PM PDT 24 Jul 21 06:33:58 PM PDT 24 77442894 ps
T1100 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.4044625895 Jul 21 06:33:28 PM PDT 24 Jul 21 06:33:34 PM PDT 24 174511425 ps
T1101 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.123111874 Jul 21 06:33:51 PM PDT 24 Jul 21 06:34:01 PM PDT 24 157568464 ps
T1102 /workspace/coverage/cover_reg_top/1.edn_tl_errors.1229475382 Jul 21 06:33:27 PM PDT 24 Jul 21 06:33:33 PM PDT 24 1371308529 ps
T1103 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1278009782 Jul 21 06:33:45 PM PDT 24 Jul 21 06:33:53 PM PDT 24 42073439 ps
T1104 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2997390240 Jul 21 06:33:32 PM PDT 24 Jul 21 06:33:41 PM PDT 24 284688831 ps
T1105 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1191977890 Jul 21 06:33:32 PM PDT 24 Jul 21 06:33:40 PM PDT 24 62821431 ps
T1106 /workspace/coverage/cover_reg_top/9.edn_intr_test.2578249169 Jul 21 06:33:44 PM PDT 24 Jul 21 06:33:51 PM PDT 24 53738582 ps
T1107 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1119096495 Jul 21 06:33:54 PM PDT 24 Jul 21 06:34:01 PM PDT 24 18599588 ps
T1108 /workspace/coverage/cover_reg_top/15.edn_intr_test.1420853885 Jul 21 06:33:53 PM PDT 24 Jul 21 06:33:59 PM PDT 24 27761745 ps
T1109 /workspace/coverage/cover_reg_top/5.edn_csr_rw.2435172824 Jul 21 06:33:46 PM PDT 24 Jul 21 06:33:52 PM PDT 24 36999756 ps
T1110 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3107259016 Jul 21 06:33:47 PM PDT 24 Jul 21 06:33:54 PM PDT 24 61114967 ps
T1111 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1643003751 Jul 21 06:33:45 PM PDT 24 Jul 21 06:33:52 PM PDT 24 17512666 ps
T1112 /workspace/coverage/cover_reg_top/27.edn_intr_test.2868324341 Jul 21 06:33:57 PM PDT 24 Jul 21 06:34:03 PM PDT 24 17433115 ps
T258 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3243725399 Jul 21 06:33:36 PM PDT 24 Jul 21 06:33:47 PM PDT 24 32255801 ps
T285 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3341279149 Jul 21 06:33:51 PM PDT 24 Jul 21 06:33:59 PM PDT 24 145170058 ps
T1113 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2244658760 Jul 21 06:33:51 PM PDT 24 Jul 21 06:33:58 PM PDT 24 62957931 ps
T1114 /workspace/coverage/cover_reg_top/37.edn_intr_test.3991560360 Jul 21 06:33:59 PM PDT 24 Jul 21 06:34:05 PM PDT 24 39104672 ps
T1115 /workspace/coverage/cover_reg_top/2.edn_intr_test.4128871480 Jul 21 06:33:36 PM PDT 24 Jul 21 06:33:46 PM PDT 24 50043764 ps
T1116 /workspace/coverage/cover_reg_top/14.edn_intr_test.2452787327 Jul 21 06:33:52 PM PDT 24 Jul 21 06:33:58 PM PDT 24 23784755 ps
T1117 /workspace/coverage/cover_reg_top/16.edn_intr_test.1402412230 Jul 21 06:33:51 PM PDT 24 Jul 21 06:33:58 PM PDT 24 15524493 ps
T1118 /workspace/coverage/cover_reg_top/28.edn_intr_test.4218962874 Jul 21 06:34:00 PM PDT 24 Jul 21 06:34:05 PM PDT 24 12063229 ps
T1119 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.4083632743 Jul 21 06:33:47 PM PDT 24 Jul 21 06:33:55 PM PDT 24 286904975 ps
T1120 /workspace/coverage/cover_reg_top/20.edn_intr_test.1111523719 Jul 21 06:33:59 PM PDT 24 Jul 21 06:34:05 PM PDT 24 14455770 ps
T1121 /workspace/coverage/cover_reg_top/29.edn_intr_test.947319717 Jul 21 06:33:57 PM PDT 24 Jul 21 06:34:03 PM PDT 24 54132682 ps
T1122 /workspace/coverage/cover_reg_top/36.edn_intr_test.3615837432 Jul 21 06:33:58 PM PDT 24 Jul 21 06:34:04 PM PDT 24 38616636 ps
T1123 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2020288530 Jul 21 06:33:45 PM PDT 24 Jul 21 06:33:52 PM PDT 24 17443059 ps
T1124 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1895124284 Jul 21 06:33:59 PM PDT 24 Jul 21 06:34:05 PM PDT 24 75049364 ps
T259 /workspace/coverage/cover_reg_top/1.edn_csr_rw.3581061252 Jul 21 06:33:31 PM PDT 24 Jul 21 06:33:36 PM PDT 24 16490838 ps
T1125 /workspace/coverage/cover_reg_top/3.edn_tl_errors.2276657527 Jul 21 06:33:32 PM PDT 24 Jul 21 06:33:40 PM PDT 24 78657864 ps
T1126 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.559759286 Jul 21 06:33:36 PM PDT 24 Jul 21 06:33:46 PM PDT 24 82795892 ps
T1127 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3985560922 Jul 21 06:33:44 PM PDT 24 Jul 21 06:33:51 PM PDT 24 85494167 ps
T1128 /workspace/coverage/cover_reg_top/24.edn_intr_test.70167675 Jul 21 06:33:56 PM PDT 24 Jul 21 06:34:02 PM PDT 24 18914212 ps
T1129 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2663418410 Jul 21 06:33:36 PM PDT 24 Jul 21 06:33:48 PM PDT 24 202980946 ps
T257 /workspace/coverage/cover_reg_top/7.edn_csr_rw.304609944 Jul 21 06:33:44 PM PDT 24 Jul 21 06:33:51 PM PDT 24 12532348 ps
T1130 /workspace/coverage/cover_reg_top/6.edn_tl_errors.316460125 Jul 21 06:33:43 PM PDT 24 Jul 21 06:33:52 PM PDT 24 97110256 ps

Test location /workspace/coverage/default/121.edn_genbits.2169736202
Short name T9
Test name
Test status
Simulation time 63904373 ps
CPU time 1.65 seconds
Started Jul 21 06:42:19 PM PDT 24
Finished Jul 21 06:42:23 PM PDT 24
Peak memory 219172 kb
Host smart-0aead272-2383-4d17-8399-88815e18f73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169736202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.2169736202
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.2245625088
Short name T4
Test name
Test status
Simulation time 675243394286 ps
CPU time 2501.02 seconds
Started Jul 21 06:41:17 PM PDT 24
Finished Jul 21 07:22:59 PM PDT 24
Peak memory 227108 kb
Host smart-2e0ca1d6-cb2a-4e15-9926-b19b06820a07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245625088 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.2245625088
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.edn_genbits.3935914472
Short name T39
Test name
Test status
Simulation time 56330810 ps
CPU time 1.44 seconds
Started Jul 21 06:42:03 PM PDT 24
Finished Jul 21 06:42:05 PM PDT 24
Peak memory 219192 kb
Host smart-7e4c9541-b177-418d-85fb-c92ffeb8883a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935914472 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.3935914472
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_err.3174086760
Short name T6
Test name
Test status
Simulation time 25430037 ps
CPU time 1.1 seconds
Started Jul 21 06:41:12 PM PDT 24
Finished Jul 21 06:41:14 PM PDT 24
Peak memory 220244 kb
Host smart-9949e9bf-3db9-49d5-b4f0-e5c5593602d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174086760 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3174086760
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/4.edn_sec_cm.1770887716
Short name T16
Test name
Test status
Simulation time 1185395083 ps
CPU time 5.05 seconds
Started Jul 21 06:40:51 PM PDT 24
Finished Jul 21 06:40:58 PM PDT 24
Peak memory 235540 kb
Host smart-e0b92b97-10ab-4608-aec0-631998aa137b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770887716 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.1770887716
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/116.edn_alert.793003289
Short name T3
Test name
Test status
Simulation time 33912645 ps
CPU time 1.41 seconds
Started Jul 21 06:42:15 PM PDT 24
Finished Jul 21 06:42:18 PM PDT 24
Peak memory 220012 kb
Host smart-239f6894-9e81-464e-8ce2-89d99c0766a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793003289 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.793003289
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.3189815766
Short name T111
Test name
Test status
Simulation time 84839701 ps
CPU time 1.15 seconds
Started Jul 21 06:41:35 PM PDT 24
Finished Jul 21 06:41:38 PM PDT 24
Peak memory 218584 kb
Host smart-12024c02-7c65-4912-b9e3-1f22dbea76f8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189815766 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.3189815766
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_sec_cm.1263944918
Short name T55
Test name
Test status
Simulation time 251693887 ps
CPU time 3.98 seconds
Started Jul 21 06:40:40 PM PDT 24
Finished Jul 21 06:40:45 PM PDT 24
Peak memory 235980 kb
Host smart-be30f6e5-6318-4134-93b1-5f5a3e291364
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263944918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.1263944918
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/55.edn_alert.4113041999
Short name T99
Test name
Test status
Simulation time 29939862 ps
CPU time 1.36 seconds
Started Jul 21 06:41:57 PM PDT 24
Finished Jul 21 06:42:00 PM PDT 24
Peak memory 220212 kb
Host smart-d8480582-e274-425a-9ba7-44917ab61834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113041999 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.4113041999
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/132.edn_alert.4150272968
Short name T79
Test name
Test status
Simulation time 77739116 ps
CPU time 1.1 seconds
Started Jul 21 06:42:47 PM PDT 24
Finished Jul 21 06:42:50 PM PDT 24
Peak memory 219192 kb
Host smart-0888bf8a-6452-46c3-b2be-1a405be30204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150272968 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.4150272968
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/242.edn_genbits.362097141
Short name T11
Test name
Test status
Simulation time 74867299 ps
CPU time 1.47 seconds
Started Jul 21 06:42:56 PM PDT 24
Finished Jul 21 06:42:58 PM PDT 24
Peak memory 220392 kb
Host smart-cb05454d-20bb-4fae-90a1-58d783993f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362097141 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.362097141
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_regwen.4041247858
Short name T24
Test name
Test status
Simulation time 15388007 ps
CPU time 1 seconds
Started Jul 21 06:40:46 PM PDT 24
Finished Jul 21 06:40:48 PM PDT 24
Peak memory 207320 kb
Host smart-197b23ed-cb90-4640-b5ae-51b010127d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041247858 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.4041247858
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.316548828
Short name T96
Test name
Test status
Simulation time 43265758504 ps
CPU time 943.92 seconds
Started Jul 21 06:42:00 PM PDT 24
Finished Jul 21 06:57:45 PM PDT 24
Peak memory 219580 kb
Host smart-c9a6d8c6-9af6-46b6-a60f-9aa1a5d461d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316548828 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.316548828
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.3128589180
Short name T144
Test name
Test status
Simulation time 32016022 ps
CPU time 0.98 seconds
Started Jul 21 06:41:34 PM PDT 24
Finished Jul 21 06:41:37 PM PDT 24
Peak memory 217260 kb
Host smart-4b197978-e2e1-44b8-aaec-18c56ca00fb7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128589180 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.3128589180
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/57.edn_alert.1273132507
Short name T102
Test name
Test status
Simulation time 31482068 ps
CPU time 1.29 seconds
Started Jul 21 06:42:13 PM PDT 24
Finished Jul 21 06:42:15 PM PDT 24
Peak memory 220152 kb
Host smart-f11beb92-3211-44b8-b162-f81d0d9e93cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273132507 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.1273132507
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.713296951
Short name T282
Test name
Test status
Simulation time 354302429 ps
CPU time 2.67 seconds
Started Jul 21 06:33:44 PM PDT 24
Finished Jul 21 06:33:53 PM PDT 24
Peak memory 207084 kb
Host smart-1020cc85-9381-4444-bb47-2145cc89cf53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713296951 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.713296951
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/default/40.edn_disable.3807074876
Short name T87
Test name
Test status
Simulation time 17812895 ps
CPU time 0.87 seconds
Started Jul 21 06:41:37 PM PDT 24
Finished Jul 21 06:41:39 PM PDT 24
Peak memory 216524 kb
Host smart-12b8b728-6ff8-43b9-bbe6-63871fe0b717
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807074876 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.3807074876
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable.293296126
Short name T195
Test name
Test status
Simulation time 18993095 ps
CPU time 0.88 seconds
Started Jul 21 06:40:57 PM PDT 24
Finished Jul 21 06:40:59 PM PDT 24
Peak memory 216572 kb
Host smart-c28d3af1-46d0-4076-a8ab-b5d649f5996c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293296126 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.293296126
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.1141224700
Short name T115
Test name
Test status
Simulation time 70761538 ps
CPU time 1.21 seconds
Started Jul 21 06:40:42 PM PDT 24
Finished Jul 21 06:40:44 PM PDT 24
Peak memory 217148 kb
Host smart-db4f5e51-80fa-496a-ae3d-8f28e2d23ac1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141224700 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.1141224700
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_disable.2136536155
Short name T906
Test name
Test status
Simulation time 41061485 ps
CPU time 0.87 seconds
Started Jul 21 06:41:24 PM PDT 24
Finished Jul 21 06:41:26 PM PDT 24
Peak memory 216436 kb
Host smart-171e3351-c20b-4fd4-a22d-93e38870dd8c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136536155 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.2136536155
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable.946351172
Short name T167
Test name
Test status
Simulation time 13713530 ps
CPU time 0.91 seconds
Started Jul 21 06:40:47 PM PDT 24
Finished Jul 21 06:40:48 PM PDT 24
Peak memory 216660 kb
Host smart-7a96c5aa-47ec-419e-8b9a-7a33ad2dd175
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946351172 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.946351172
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2120706970
Short name T248
Test name
Test status
Simulation time 71651972 ps
CPU time 1 seconds
Started Jul 21 06:33:58 PM PDT 24
Finished Jul 21 06:34:04 PM PDT 24
Peak memory 206776 kb
Host smart-5b5ed0d7-0a48-472c-8073-593a41c0a3cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120706970 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2120706970
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/default/107.edn_alert.1027086548
Short name T238
Test name
Test status
Simulation time 194599392 ps
CPU time 1.08 seconds
Started Jul 21 06:42:21 PM PDT 24
Finished Jul 21 06:42:24 PM PDT 24
Peak memory 220940 kb
Host smart-e74d0d01-3028-4604-a580-6d7b98e1dd0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027086548 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.1027086548
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/122.edn_alert.2791907018
Short name T192
Test name
Test status
Simulation time 79933834 ps
CPU time 1.2 seconds
Started Jul 21 06:42:18 PM PDT 24
Finished Jul 21 06:42:21 PM PDT 24
Peak memory 219956 kb
Host smart-a18165dc-3ce1-48ab-81b1-1c3f1622c866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791907018 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.2791907018
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/108.edn_alert.3045333263
Short name T75
Test name
Test status
Simulation time 92026747 ps
CPU time 1.19 seconds
Started Jul 21 06:42:14 PM PDT 24
Finished Jul 21 06:42:16 PM PDT 24
Peak memory 220080 kb
Host smart-44cdd82b-c1c4-4856-a2ec-b168d265d770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045333263 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.3045333263
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/271.edn_genbits.3710219453
Short name T302
Test name
Test status
Simulation time 48156953 ps
CPU time 1.12 seconds
Started Jul 21 06:43:06 PM PDT 24
Finished Jul 21 06:43:08 PM PDT 24
Peak memory 217484 kb
Host smart-1c582042-2b24-4893-9391-0db4449aa65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710219453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.3710219453
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_err.1800563920
Short name T29
Test name
Test status
Simulation time 30606090 ps
CPU time 0.9 seconds
Started Jul 21 06:41:12 PM PDT 24
Finished Jul 21 06:41:14 PM PDT 24
Peak memory 219444 kb
Host smart-ff23c988-b66b-4e4b-8b2f-4070b2560029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800563920 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.1800563920
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/138.edn_alert.4060615281
Short name T500
Test name
Test status
Simulation time 26241442 ps
CPU time 1.15 seconds
Started Jul 21 06:42:34 PM PDT 24
Finished Jul 21 06:42:37 PM PDT 24
Peak memory 220072 kb
Host smart-d34e7a23-2aa2-4c86-9e66-13db51e552e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060615281 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.4060615281
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/144.edn_alert.317332405
Short name T159
Test name
Test status
Simulation time 105392795 ps
CPU time 1.24 seconds
Started Jul 21 06:42:37 PM PDT 24
Finished Jul 21 06:42:39 PM PDT 24
Peak memory 220868 kb
Host smart-02694fbb-1067-4b6a-8d2c-16cee5fa61f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317332405 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.317332405
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/148.edn_alert.3608870101
Short name T791
Test name
Test status
Simulation time 98544574 ps
CPU time 1.06 seconds
Started Jul 21 06:42:38 PM PDT 24
Finished Jul 21 06:42:39 PM PDT 24
Peak memory 221128 kb
Host smart-e6ed4454-c108-4715-9f80-cbd7f81f3c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608870101 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.3608870101
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/158.edn_alert.1575115404
Short name T149
Test name
Test status
Simulation time 56236432 ps
CPU time 1.31 seconds
Started Jul 21 06:42:36 PM PDT 24
Finished Jul 21 06:42:38 PM PDT 24
Peak memory 220172 kb
Host smart-9f1d9398-adb0-4cbd-b275-f3221f3fd5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575115404 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.1575115404
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/169.edn_alert.3223117291
Short name T298
Test name
Test status
Simulation time 27561948 ps
CPU time 1.29 seconds
Started Jul 21 06:42:36 PM PDT 24
Finished Jul 21 06:42:39 PM PDT 24
Peak memory 220116 kb
Host smart-3a2d9640-5b8e-4c7b-ad2c-caae82330a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223117291 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.3223117291
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert.3416733953
Short name T105
Test name
Test status
Simulation time 30934311 ps
CPU time 1.27 seconds
Started Jul 21 06:41:34 PM PDT 24
Finished Jul 21 06:41:37 PM PDT 24
Peak memory 220048 kb
Host smart-38170c65-581d-4117-88fe-229e7d242c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416733953 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3416733953
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/45.edn_err.1720750352
Short name T180
Test name
Test status
Simulation time 22615454 ps
CPU time 1.07 seconds
Started Jul 21 06:42:12 PM PDT 24
Finished Jul 21 06:42:14 PM PDT 24
Peak memory 224052 kb
Host smart-3d3e4bb6-7b3a-4188-9f32-62a9c2eb6174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720750352 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1720750352
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/0.edn_intr.227919202
Short name T35
Test name
Test status
Simulation time 26954515 ps
CPU time 0.93 seconds
Started Jul 21 06:40:41 PM PDT 24
Finished Jul 21 06:40:43 PM PDT 24
Peak memory 216072 kb
Host smart-5ee16fc6-3fb6-4dc9-914f-518e04a694ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227919202 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.227919202
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/171.edn_alert.1244275698
Short name T966
Test name
Test status
Simulation time 46436428 ps
CPU time 1.15 seconds
Started Jul 21 06:42:43 PM PDT 24
Finished Jul 21 06:42:45 PM PDT 24
Peak memory 220412 kb
Host smart-687b3a67-b82f-4f02-86b9-b41cd63b421b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244275698 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.1244275698
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.3766205783
Short name T122
Test name
Test status
Simulation time 47471820 ps
CPU time 1.43 seconds
Started Jul 21 06:41:33 PM PDT 24
Finished Jul 21 06:41:37 PM PDT 24
Peak memory 217032 kb
Host smart-2fa285b8-2e68-4596-bf59-c180a76b4bd6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766205783 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.3766205783
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_disable.576206215
Short name T218
Test name
Test status
Simulation time 15635796 ps
CPU time 0.87 seconds
Started Jul 21 06:41:54 PM PDT 24
Finished Jul 21 06:41:56 PM PDT 24
Peak memory 215700 kb
Host smart-28b08aea-06ea-471d-aa76-a7e467fa23a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576206215 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.576206215
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.83151362
Short name T69
Test name
Test status
Simulation time 26660248 ps
CPU time 1.14 seconds
Started Jul 21 06:42:02 PM PDT 24
Finished Jul 21 06:42:04 PM PDT 24
Peak memory 220088 kb
Host smart-019822c0-8ffc-4f48-a492-7fb4a48c76f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83151362 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_dis
able_auto_req_mode.83151362
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_intr.4029980786
Short name T31
Test name
Test status
Simulation time 20895096 ps
CPU time 1.11 seconds
Started Jul 21 06:41:03 PM PDT 24
Finished Jul 21 06:41:05 PM PDT 24
Peak memory 216076 kb
Host smart-fdf51ed7-de9c-4e0e-bf1b-877a18b2f3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029980786 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.4029980786
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/1.edn_disable.3671926202
Short name T961
Test name
Test status
Simulation time 10956428 ps
CPU time 0.87 seconds
Started Jul 21 06:40:38 PM PDT 24
Finished Jul 21 06:40:39 PM PDT 24
Peak memory 216456 kb
Host smart-d8e39e97-c841-4e1e-a4bc-d38a16b8f841
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671926202 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3671926202
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable.2047346035
Short name T176
Test name
Test status
Simulation time 18618465 ps
CPU time 0.91 seconds
Started Jul 21 06:40:59 PM PDT 24
Finished Jul 21 06:41:00 PM PDT 24
Peak memory 216444 kb
Host smart-6dedcb97-3e5a-4a27-ae60-737a5f72676d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047346035 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.2047346035
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/111.edn_alert.2137406247
Short name T126
Test name
Test status
Simulation time 31901662 ps
CPU time 1.32 seconds
Started Jul 21 06:42:13 PM PDT 24
Finished Jul 21 06:42:15 PM PDT 24
Peak memory 218868 kb
Host smart-66594f80-6e92-4665-8103-06859b550789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137406247 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.2137406247
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/139.edn_alert.626274121
Short name T104
Test name
Test status
Simulation time 28762445 ps
CPU time 1.3 seconds
Started Jul 21 06:42:34 PM PDT 24
Finished Jul 21 06:42:36 PM PDT 24
Peak memory 219008 kb
Host smart-dd9a67c3-7db2-4359-803d-97c7553c2749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626274121 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.626274121
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/143.edn_alert.1698518924
Short name T177
Test name
Test status
Simulation time 50141806 ps
CPU time 1.13 seconds
Started Jul 21 06:42:43 PM PDT 24
Finished Jul 21 06:42:45 PM PDT 24
Peak memory 218720 kb
Host smart-8b219834-0640-4a11-908d-64e174e0e56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698518924 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.1698518924
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.825764561
Short name T152
Test name
Test status
Simulation time 46597612 ps
CPU time 1.18 seconds
Started Jul 21 06:41:12 PM PDT 24
Finished Jul 21 06:41:14 PM PDT 24
Peak memory 217252 kb
Host smart-303d379e-e14c-4144-b5e5-2b9d8ae0a0f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825764561 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_di
sable_auto_req_mode.825764561
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_disable.94318016
Short name T200
Test name
Test status
Simulation time 39894584 ps
CPU time 0.82 seconds
Started Jul 21 06:41:53 PM PDT 24
Finished Jul 21 06:41:55 PM PDT 24
Peak memory 216468 kb
Host smart-67c41e82-bfda-4149-971d-0eae62144255
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94318016 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.94318016
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/49.edn_err.3188263187
Short name T190
Test name
Test status
Simulation time 33935389 ps
CPU time 1.03 seconds
Started Jul 21 06:42:02 PM PDT 24
Finished Jul 21 06:42:04 PM PDT 24
Peak memory 224088 kb
Host smart-a95622b0-78a3-4870-b820-1a4c22fa573c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188263187 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3188263187
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/9.edn_disable.57684966
Short name T186
Test name
Test status
Simulation time 11473496 ps
CPU time 0.92 seconds
Started Jul 21 06:40:51 PM PDT 24
Finished Jul 21 06:40:54 PM PDT 24
Peak memory 216576 kb
Host smart-3f6af63c-c6f2-4287-a913-4bb859dc7e3a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57684966 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.57684966
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/241.edn_genbits.3392019800
Short name T8
Test name
Test status
Simulation time 54208860 ps
CPU time 2.21 seconds
Started Jul 21 06:43:03 PM PDT 24
Finished Jul 21 06:43:06 PM PDT 24
Peak memory 220292 kb
Host smart-f892c5f8-5a11-443a-bc76-14ec4a86151f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392019800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.3392019800
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert_test.3935929131
Short name T70
Test name
Test status
Simulation time 17950839 ps
CPU time 0.84 seconds
Started Jul 21 06:41:11 PM PDT 24
Finished Jul 21 06:41:12 PM PDT 24
Peak memory 206716 kb
Host smart-16594c03-82c6-4925-8b50-fcb0608ce727
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935929131 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.3935929131
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/123.edn_genbits.3007710395
Short name T337
Test name
Test status
Simulation time 9066704625 ps
CPU time 121.81 seconds
Started Jul 21 06:42:18 PM PDT 24
Finished Jul 21 06:44:22 PM PDT 24
Peak memory 217856 kb
Host smart-7e446e11-2956-4a2d-89d1-78f6fa65a224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007710395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.3007710395
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.2161994852
Short name T300
Test name
Test status
Simulation time 107348497 ps
CPU time 1.64 seconds
Started Jul 21 06:42:48 PM PDT 24
Finished Jul 21 06:42:51 PM PDT 24
Peak memory 218824 kb
Host smart-1e016499-0b4f-4d7b-9f82-752eaf51e2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161994852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2161994852
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_genbits.1157639728
Short name T44
Test name
Test status
Simulation time 115085793 ps
CPU time 1.54 seconds
Started Jul 21 06:41:45 PM PDT 24
Finished Jul 21 06:41:47 PM PDT 24
Peak memory 219376 kb
Host smart-cc58367f-fe52-4135-914b-3fcd4a7a9e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157639728 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.1157639728
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.2507581034
Short name T225
Test name
Test status
Simulation time 154351600555 ps
CPU time 325.35 seconds
Started Jul 21 06:40:55 PM PDT 24
Finished Jul 21 06:46:23 PM PDT 24
Peak memory 219276 kb
Host smart-b3618fb5-5916-4d24-bdf1-d929a5c76b6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507581034 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.2507581034
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_intr.3617854300
Short name T92
Test name
Test status
Simulation time 27235380 ps
CPU time 1.07 seconds
Started Jul 21 06:41:51 PM PDT 24
Finished Jul 21 06:41:52 PM PDT 24
Peak memory 216220 kb
Host smart-c732ce73-c600-4662-8e28-523fa95fcd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617854300 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.3617854300
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/23.edn_genbits.696794643
Short name T818
Test name
Test status
Simulation time 37925430 ps
CPU time 1.4 seconds
Started Jul 21 06:41:14 PM PDT 24
Finished Jul 21 06:41:18 PM PDT 24
Peak memory 220180 kb
Host smart-2a1ce99f-94bb-4d83-adb3-98148e730282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696794643 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.696794643
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1990866123
Short name T267
Test name
Test status
Simulation time 39617004 ps
CPU time 1.53 seconds
Started Jul 21 06:33:25 PM PDT 24
Finished Jul 21 06:33:28 PM PDT 24
Peak memory 206868 kb
Host smart-25360227-3e11-4a44-b792-3bc142578088
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990866123 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.1990866123
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3341279149
Short name T285
Test name
Test status
Simulation time 145170058 ps
CPU time 2.53 seconds
Started Jul 21 06:33:51 PM PDT 24
Finished Jul 21 06:33:59 PM PDT 24
Peak memory 215096 kb
Host smart-20fb80a5-4a17-4387-a3a5-c8af592805df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341279149 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.3341279149
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_genbits.251218911
Short name T314
Test name
Test status
Simulation time 68915252 ps
CPU time 1.17 seconds
Started Jul 21 06:40:42 PM PDT 24
Finished Jul 21 06:40:44 PM PDT 24
Peak memory 219380 kb
Host smart-da69d771-bf58-46c5-a6bc-6b44787a25b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251218911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.251218911
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_stress_all.1149547386
Short name T305
Test name
Test status
Simulation time 399725378 ps
CPU time 4.47 seconds
Started Jul 21 06:40:43 PM PDT 24
Finished Jul 21 06:40:48 PM PDT 24
Peak memory 217588 kb
Host smart-c6d0c2b9-e091-443e-936d-41263bccdb7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149547386 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.1149547386
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/102.edn_genbits.2864679681
Short name T319
Test name
Test status
Simulation time 74096558 ps
CPU time 1.38 seconds
Started Jul 21 06:42:16 PM PDT 24
Finished Jul 21 06:42:19 PM PDT 24
Peak memory 219124 kb
Host smart-6f9cb334-bd37-4e91-9bc9-f146da318d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864679681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.2864679681
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.3894629442
Short name T409
Test name
Test status
Simulation time 45331953 ps
CPU time 1.16 seconds
Started Jul 21 06:42:14 PM PDT 24
Finished Jul 21 06:42:16 PM PDT 24
Peak memory 220064 kb
Host smart-e88f717c-732a-4fcd-92e1-5d210df1e06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894629442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3894629442
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.1830437018
Short name T329
Test name
Test status
Simulation time 30209774 ps
CPU time 1.11 seconds
Started Jul 21 06:42:45 PM PDT 24
Finished Jul 21 06:42:47 PM PDT 24
Peak memory 220248 kb
Host smart-1dc9be82-585b-40c6-a18d-21b7a8854b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830437018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.1830437018
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.1371111213
Short name T799
Test name
Test status
Simulation time 118867234 ps
CPU time 1.31 seconds
Started Jul 21 06:42:24 PM PDT 24
Finished Jul 21 06:42:26 PM PDT 24
Peak memory 217656 kb
Host smart-74b4e875-860c-49a4-a2df-934f809ea0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371111213 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.1371111213
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.3211112197
Short name T509
Test name
Test status
Simulation time 113295298 ps
CPU time 1.51 seconds
Started Jul 21 06:42:22 PM PDT 24
Finished Jul 21 06:42:24 PM PDT 24
Peak memory 219124 kb
Host smart-c6a48211-dc1a-4be6-a21b-897ea7dc7d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211112197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.3211112197
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.1999292842
Short name T324
Test name
Test status
Simulation time 108508435 ps
CPU time 1.22 seconds
Started Jul 21 06:42:39 PM PDT 24
Finished Jul 21 06:42:41 PM PDT 24
Peak memory 218760 kb
Host smart-f15801c7-f399-49ed-b1a0-809aea998e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999292842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.1999292842
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.2350913830
Short name T295
Test name
Test status
Simulation time 164430328 ps
CPU time 1.26 seconds
Started Jul 21 06:42:27 PM PDT 24
Finished Jul 21 06:42:29 PM PDT 24
Peak memory 220100 kb
Host smart-f689f27c-bb9f-484d-ac8a-089b90a33afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350913830 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.2350913830
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.268870456
Short name T317
Test name
Test status
Simulation time 92399021 ps
CPU time 1.55 seconds
Started Jul 21 06:42:46 PM PDT 24
Finished Jul 21 06:42:50 PM PDT 24
Peak memory 217904 kb
Host smart-e28caf86-455a-471b-ba1c-ce1dc5156847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268870456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.268870456
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.3567816712
Short name T310
Test name
Test status
Simulation time 42389712 ps
CPU time 1.61 seconds
Started Jul 21 06:43:14 PM PDT 24
Finished Jul 21 06:43:16 PM PDT 24
Peak memory 218784 kb
Host smart-e5baa217-49de-46f7-9f84-9d60ab69bd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567816712 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.3567816712
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.3151893037
Short name T280
Test name
Test status
Simulation time 164640580 ps
CPU time 1.11 seconds
Started Jul 21 06:41:24 PM PDT 24
Finished Jul 21 06:41:26 PM PDT 24
Peak memory 219968 kb
Host smart-b314b4fe-5f08-4085-a34b-e83c299370c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151893037 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.3151893037
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_intr.625953208
Short name T33
Test name
Test status
Simulation time 34136096 ps
CPU time 0.87 seconds
Started Jul 21 06:40:47 PM PDT 24
Finished Jul 21 06:40:49 PM PDT 24
Peak memory 215948 kb
Host smart-797f7083-9457-4c29-aa99-f52357d1f028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625953208 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.625953208
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/133.edn_alert.4107098661
Short name T147
Test name
Test status
Simulation time 85538321 ps
CPU time 1.26 seconds
Started Jul 21 06:42:23 PM PDT 24
Finished Jul 21 06:42:26 PM PDT 24
Peak memory 218760 kb
Host smart-8283ac28-9787-4539-9b3f-b7418e273017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107098661 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.4107098661
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1576070683
Short name T246
Test name
Test status
Simulation time 20890997 ps
CPU time 1.32 seconds
Started Jul 21 06:33:27 PM PDT 24
Finished Jul 21 06:33:31 PM PDT 24
Peak memory 206840 kb
Host smart-8a53e69e-9b20-41ca-aeef-566778d71572
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576070683 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1576070683
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.4044625895
Short name T1100
Test name
Test status
Simulation time 174511425 ps
CPU time 3 seconds
Started Jul 21 06:33:28 PM PDT 24
Finished Jul 21 06:33:34 PM PDT 24
Peak memory 206900 kb
Host smart-c572715f-3dbb-485f-a639-6efa0b8ee322
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044625895 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.4044625895
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.4258584216
Short name T251
Test name
Test status
Simulation time 14139900 ps
CPU time 0.93 seconds
Started Jul 21 06:33:30 PM PDT 24
Finished Jul 21 06:33:33 PM PDT 24
Peak memory 206912 kb
Host smart-eec575e4-d927-414c-839f-cd33273be790
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258584216 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.4258584216
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.304228978
Short name T1061
Test name
Test status
Simulation time 167169837 ps
CPU time 2.07 seconds
Started Jul 21 06:33:25 PM PDT 24
Finished Jul 21 06:33:29 PM PDT 24
Peak memory 215172 kb
Host smart-9fc0516b-14b7-4dc0-ab29-8cb41cfb7123
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304228978 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.304228978
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.4151094848
Short name T1039
Test name
Test status
Simulation time 26935320 ps
CPU time 0.86 seconds
Started Jul 21 06:33:30 PM PDT 24
Finished Jul 21 06:33:34 PM PDT 24
Peak memory 206848 kb
Host smart-80123fd8-5055-4b4b-92dd-37f6a0fe6759
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151094848 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.4151094848
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1935838130
Short name T1005
Test name
Test status
Simulation time 74210531 ps
CPU time 0.86 seconds
Started Jul 21 06:33:26 PM PDT 24
Finished Jul 21 06:33:28 PM PDT 24
Peak memory 206820 kb
Host smart-a97af60f-2a08-4c82-b0c1-1ae7e0901ca7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935838130 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1935838130
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.1622692725
Short name T1021
Test name
Test status
Simulation time 23261311 ps
CPU time 1.86 seconds
Started Jul 21 06:33:29 PM PDT 24
Finished Jul 21 06:33:34 PM PDT 24
Peak memory 215292 kb
Host smart-3a2b2513-f82e-4176-aa21-e8ad89aa7356
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622692725 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.1622692725
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3540846870
Short name T1083
Test name
Test status
Simulation time 422086862 ps
CPU time 2.71 seconds
Started Jul 21 06:33:25 PM PDT 24
Finished Jul 21 06:33:29 PM PDT 24
Peak memory 207156 kb
Host smart-ecff0570-2ace-42bf-9609-33565fd1097c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540846870 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3540846870
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3697821348
Short name T245
Test name
Test status
Simulation time 152398991 ps
CPU time 1.53 seconds
Started Jul 21 06:33:30 PM PDT 24
Finished Jul 21 06:33:34 PM PDT 24
Peak memory 206772 kb
Host smart-709cce79-856e-4928-9f55-efa979fea3ea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697821348 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.3697821348
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2644050047
Short name T255
Test name
Test status
Simulation time 134258803 ps
CPU time 3.79 seconds
Started Jul 21 06:33:32 PM PDT 24
Finished Jul 21 06:33:44 PM PDT 24
Peak memory 206852 kb
Host smart-11aa1da6-ec62-4bbf-84c4-4f1b45956d31
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644050047 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2644050047
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.443417852
Short name T1018
Test name
Test status
Simulation time 16128869 ps
CPU time 0.95 seconds
Started Jul 21 06:33:31 PM PDT 24
Finished Jul 21 06:33:36 PM PDT 24
Peak memory 206848 kb
Host smart-8213e336-8f39-4f8d-a1c4-cd6a5d06b097
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443417852 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.443417852
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2301639962
Short name T1090
Test name
Test status
Simulation time 117145991 ps
CPU time 1.38 seconds
Started Jul 21 06:33:33 PM PDT 24
Finished Jul 21 06:33:43 PM PDT 24
Peak memory 215220 kb
Host smart-6ae0e1a0-afe3-41c3-ae7e-0f76aa01f465
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301639962 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2301639962
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.3581061252
Short name T259
Test name
Test status
Simulation time 16490838 ps
CPU time 0.95 seconds
Started Jul 21 06:33:31 PM PDT 24
Finished Jul 21 06:33:36 PM PDT 24
Peak memory 206832 kb
Host smart-0fed23d0-99de-4a61-be19-654a543de646
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581061252 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3581061252
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.114128183
Short name T1042
Test name
Test status
Simulation time 14877179 ps
CPU time 0.89 seconds
Started Jul 21 06:33:28 PM PDT 24
Finished Jul 21 06:33:31 PM PDT 24
Peak memory 206808 kb
Host smart-aeb1e982-9c54-41c0-af98-db10c3ecd153
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114128183 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.114128183
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3558161415
Short name T1043
Test name
Test status
Simulation time 108287910 ps
CPU time 1.14 seconds
Started Jul 21 06:33:31 PM PDT 24
Finished Jul 21 06:33:38 PM PDT 24
Peak memory 206880 kb
Host smart-37f5335a-a4fb-4f3c-b780-099db8550a64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558161415 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.3558161415
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.1229475382
Short name T1102
Test name
Test status
Simulation time 1371308529 ps
CPU time 4.37 seconds
Started Jul 21 06:33:27 PM PDT 24
Finished Jul 21 06:33:33 PM PDT 24
Peak memory 215128 kb
Host smart-47651d69-507e-4b16-a974-f81d47076c70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229475382 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.1229475382
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.443117950
Short name T1080
Test name
Test status
Simulation time 663478927 ps
CPU time 2.63 seconds
Started Jul 21 06:33:26 PM PDT 24
Finished Jul 21 06:33:31 PM PDT 24
Peak memory 215060 kb
Host smart-2071b551-9017-4139-8710-c5946a05aa5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443117950 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.443117950
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3107259016
Short name T1110
Test name
Test status
Simulation time 61114967 ps
CPU time 1.42 seconds
Started Jul 21 06:33:47 PM PDT 24
Finished Jul 21 06:33:54 PM PDT 24
Peak memory 215192 kb
Host smart-44409ef8-316b-4a60-8d3d-7cccd24107d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107259016 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.3107259016
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.1231893902
Short name T1092
Test name
Test status
Simulation time 13089007 ps
CPU time 0.9 seconds
Started Jul 21 06:33:45 PM PDT 24
Finished Jul 21 06:33:52 PM PDT 24
Peak memory 206912 kb
Host smart-e9d81778-92ba-4504-befd-a4f2a822c7cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231893902 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1231893902
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.24001047
Short name T1016
Test name
Test status
Simulation time 175301784 ps
CPU time 0.83 seconds
Started Jul 21 06:33:44 PM PDT 24
Finished Jul 21 06:33:51 PM PDT 24
Peak memory 206624 kb
Host smart-2824450f-2c77-43ad-a35a-ae6927e6bef3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24001047 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.24001047
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2158745815
Short name T261
Test name
Test status
Simulation time 138787734 ps
CPU time 1.6 seconds
Started Jul 21 06:33:45 PM PDT 24
Finished Jul 21 06:33:52 PM PDT 24
Peak memory 206948 kb
Host smart-c2575293-7e47-44a6-a1d4-9e732c9233eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158745815 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2158745815
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.1299694186
Short name T1084
Test name
Test status
Simulation time 185785497 ps
CPU time 3.32 seconds
Started Jul 21 06:33:47 PM PDT 24
Finished Jul 21 06:33:57 PM PDT 24
Peak memory 215096 kb
Host smart-d1ed4c92-cd55-4e8c-a143-954abe7b6946
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299694186 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1299694186
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3908322256
Short name T1007
Test name
Test status
Simulation time 25166937 ps
CPU time 1.52 seconds
Started Jul 21 06:33:44 PM PDT 24
Finished Jul 21 06:33:51 PM PDT 24
Peak memory 215184 kb
Host smart-2129bdf6-001f-41a2-86ba-cf3417a9d5ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908322256 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3908322256
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.2754808502
Short name T254
Test name
Test status
Simulation time 13045082 ps
CPU time 0.93 seconds
Started Jul 21 06:33:50 PM PDT 24
Finished Jul 21 06:33:57 PM PDT 24
Peak memory 206804 kb
Host smart-403891a4-20b3-469b-9fea-e4456ef60165
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754808502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.2754808502
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.309040775
Short name T1015
Test name
Test status
Simulation time 16842825 ps
CPU time 0.95 seconds
Started Jul 21 06:33:45 PM PDT 24
Finished Jul 21 06:33:52 PM PDT 24
Peak memory 206892 kb
Host smart-9229f7e5-3958-4302-af6a-65c326029184
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309040775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.309040775
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2020288530
Short name T1123
Test name
Test status
Simulation time 17443059 ps
CPU time 1.11 seconds
Started Jul 21 06:33:45 PM PDT 24
Finished Jul 21 06:33:52 PM PDT 24
Peak memory 206900 kb
Host smart-0450ae2f-a5e8-4329-85c6-382f8dde3af3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020288530 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.2020288530
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.1400835543
Short name T1077
Test name
Test status
Simulation time 360059664 ps
CPU time 3.05 seconds
Started Jul 21 06:33:50 PM PDT 24
Finished Jul 21 06:33:59 PM PDT 24
Peak memory 215180 kb
Host smart-a83734b9-c11a-4728-806f-5232a7cd9167
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400835543 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.1400835543
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.731893752
Short name T1051
Test name
Test status
Simulation time 452253175 ps
CPU time 1.55 seconds
Started Jul 21 06:33:45 PM PDT 24
Finished Jul 21 06:33:53 PM PDT 24
Peak memory 206976 kb
Host smart-8b84e965-86ec-4563-915d-431f014b8542
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731893752 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.731893752
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.815505948
Short name T1011
Test name
Test status
Simulation time 17472142 ps
CPU time 1.08 seconds
Started Jul 21 06:33:51 PM PDT 24
Finished Jul 21 06:33:58 PM PDT 24
Peak memory 206932 kb
Host smart-804cd62e-ff78-4a67-ac92-e09dec6e57c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815505948 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.815505948
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.207605536
Short name T1009
Test name
Test status
Simulation time 40403788 ps
CPU time 0.89 seconds
Started Jul 21 06:33:55 PM PDT 24
Finished Jul 21 06:34:01 PM PDT 24
Peak memory 206820 kb
Host smart-8fd05457-dcd1-44b3-8787-0c769ab9234b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207605536 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.207605536
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.2291960114
Short name T1068
Test name
Test status
Simulation time 60471789 ps
CPU time 0.86 seconds
Started Jul 21 06:33:50 PM PDT 24
Finished Jul 21 06:33:56 PM PDT 24
Peak memory 206772 kb
Host smart-73500497-67e8-47a0-9156-e3bd549fa821
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291960114 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2291960114
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1554300660
Short name T1041
Test name
Test status
Simulation time 68041751 ps
CPU time 1.47 seconds
Started Jul 21 06:33:57 PM PDT 24
Finished Jul 21 06:34:03 PM PDT 24
Peak memory 206948 kb
Host smart-a58ddfbe-342c-4ca4-bc62-757268ab1ad1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554300660 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.1554300660
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.1195429121
Short name T1017
Test name
Test status
Simulation time 894863957 ps
CPU time 3.24 seconds
Started Jul 21 06:33:46 PM PDT 24
Finished Jul 21 06:33:55 PM PDT 24
Peak memory 215160 kb
Host smart-35bf068b-7f79-4387-be86-868fd4b7e546
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195429121 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1195429121
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3301871699
Short name T277
Test name
Test status
Simulation time 78706908 ps
CPU time 2.11 seconds
Started Jul 21 06:33:45 PM PDT 24
Finished Jul 21 06:33:53 PM PDT 24
Peak memory 207016 kb
Host smart-4eebe5e9-de6c-4f5c-b0c0-3059cace1162
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301871699 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3301871699
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2493759795
Short name T1003
Test name
Test status
Simulation time 175632781 ps
CPU time 1.43 seconds
Started Jul 21 06:33:56 PM PDT 24
Finished Jul 21 06:34:03 PM PDT 24
Peak memory 215276 kb
Host smart-23b82d3b-5b3c-4fc2-b51d-7e004b8b4c0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493759795 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2493759795
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.207196902
Short name T1048
Test name
Test status
Simulation time 31410867 ps
CPU time 1.01 seconds
Started Jul 21 06:33:55 PM PDT 24
Finished Jul 21 06:34:02 PM PDT 24
Peak memory 206820 kb
Host smart-2aa697ea-f042-4edc-a77d-55bd3a9448ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207196902 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.207196902
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.3406643342
Short name T1024
Test name
Test status
Simulation time 16578907 ps
CPU time 0.91 seconds
Started Jul 21 06:33:53 PM PDT 24
Finished Jul 21 06:33:59 PM PDT 24
Peak memory 206808 kb
Host smart-9fdc06c6-2789-4743-b4c8-ef7bdfd09c4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406643342 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.3406643342
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.1175930402
Short name T242
Test name
Test status
Simulation time 42164821 ps
CPU time 1.15 seconds
Started Jul 21 06:33:49 PM PDT 24
Finished Jul 21 06:33:56 PM PDT 24
Peak memory 206888 kb
Host smart-7b831dda-4d27-4bea-8dca-c60b1f9b875c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175930402 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.1175930402
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.185961311
Short name T1019
Test name
Test status
Simulation time 35548315 ps
CPU time 1.28 seconds
Started Jul 21 06:33:54 PM PDT 24
Finished Jul 21 06:34:01 PM PDT 24
Peak memory 215152 kb
Host smart-d3810adf-9443-48ea-a34c-f0b9ae298239
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185961311 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.185961311
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3777148830
Short name T1038
Test name
Test status
Simulation time 37942799 ps
CPU time 1.14 seconds
Started Jul 21 06:33:50 PM PDT 24
Finished Jul 21 06:33:57 PM PDT 24
Peak memory 215188 kb
Host smart-4d641930-82aa-4f21-bc71-41e21e5d7094
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777148830 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.3777148830
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.1465272164
Short name T264
Test name
Test status
Simulation time 101244050 ps
CPU time 0.82 seconds
Started Jul 21 06:33:54 PM PDT 24
Finished Jul 21 06:34:00 PM PDT 24
Peak memory 206644 kb
Host smart-7f459a42-5207-4269-8f9e-629cf534eb01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465272164 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1465272164
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.2452787327
Short name T1116
Test name
Test status
Simulation time 23784755 ps
CPU time 0.94 seconds
Started Jul 21 06:33:52 PM PDT 24
Finished Jul 21 06:33:58 PM PDT 24
Peak memory 206840 kb
Host smart-4708a9f0-800f-4273-be19-7890a49bb14c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452787327 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.2452787327
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2244658760
Short name T1113
Test name
Test status
Simulation time 62957931 ps
CPU time 1.32 seconds
Started Jul 21 06:33:51 PM PDT 24
Finished Jul 21 06:33:58 PM PDT 24
Peak memory 206880 kb
Host smart-e19d3bb4-ec75-4726-b346-f4d0929b3dc9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244658760 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.2244658760
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.284018730
Short name T1020
Test name
Test status
Simulation time 34016046 ps
CPU time 1.42 seconds
Started Jul 21 06:33:56 PM PDT 24
Finished Jul 21 06:34:03 PM PDT 24
Peak memory 215164 kb
Host smart-672275af-a0de-4e31-a882-b9cf79c527d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284018730 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.284018730
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1489388659
Short name T1065
Test name
Test status
Simulation time 49567554 ps
CPU time 1.65 seconds
Started Jul 21 06:33:57 PM PDT 24
Finished Jul 21 06:34:04 PM PDT 24
Peak memory 215088 kb
Host smart-6a38a5cb-b9e9-4b58-9694-6a78794fa814
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489388659 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1489388659
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2858512485
Short name T1075
Test name
Test status
Simulation time 65113978 ps
CPU time 1.39 seconds
Started Jul 21 06:33:52 PM PDT 24
Finished Jul 21 06:33:59 PM PDT 24
Peak memory 215132 kb
Host smart-7e5f1787-c4d0-4809-bafc-278266ebe88f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858512485 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2858512485
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.387630254
Short name T263
Test name
Test status
Simulation time 12167770 ps
CPU time 0.84 seconds
Started Jul 21 06:33:50 PM PDT 24
Finished Jul 21 06:33:57 PM PDT 24
Peak memory 206784 kb
Host smart-b3939945-5f55-4c1d-9b89-ef080bbc5b68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387630254 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.387630254
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.1420853885
Short name T1108
Test name
Test status
Simulation time 27761745 ps
CPU time 0.88 seconds
Started Jul 21 06:33:53 PM PDT 24
Finished Jul 21 06:33:59 PM PDT 24
Peak memory 206868 kb
Host smart-dbe3962d-d108-4cf5-873d-a1a4098636e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420853885 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1420853885
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.240600103
Short name T265
Test name
Test status
Simulation time 19799085 ps
CPU time 1.22 seconds
Started Jul 21 06:33:51 PM PDT 24
Finished Jul 21 06:33:58 PM PDT 24
Peak memory 206996 kb
Host smart-ed835228-2d4b-4f2c-b66c-36544b5a29c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240600103 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_ou
tstanding.240600103
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.1774614099
Short name T1028
Test name
Test status
Simulation time 52406177 ps
CPU time 2.09 seconds
Started Jul 21 06:33:50 PM PDT 24
Finished Jul 21 06:33:58 PM PDT 24
Peak memory 215240 kb
Host smart-bba22743-b3c4-4b6f-9b69-82c5306deb80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774614099 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.1774614099
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.123111874
Short name T1101
Test name
Test status
Simulation time 157568464 ps
CPU time 3.82 seconds
Started Jul 21 06:33:51 PM PDT 24
Finished Jul 21 06:34:01 PM PDT 24
Peak memory 206880 kb
Host smart-fa5223b7-3559-4b68-9a0a-209da3fd5e93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123111874 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.123111874
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.4076959467
Short name T1082
Test name
Test status
Simulation time 61004298 ps
CPU time 1.38 seconds
Started Jul 21 06:33:49 PM PDT 24
Finished Jul 21 06:33:56 PM PDT 24
Peak memory 215188 kb
Host smart-907af642-85ab-4537-8e75-490036c694d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076959467 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.4076959467
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.2978833343
Short name T252
Test name
Test status
Simulation time 11739087 ps
CPU time 0.88 seconds
Started Jul 21 06:33:51 PM PDT 24
Finished Jul 21 06:33:58 PM PDT 24
Peak memory 206844 kb
Host smart-9672c642-f74a-4b0c-be5b-760b9903b42b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978833343 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.2978833343
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.1402412230
Short name T1117
Test name
Test status
Simulation time 15524493 ps
CPU time 0.94 seconds
Started Jul 21 06:33:51 PM PDT 24
Finished Jul 21 06:33:58 PM PDT 24
Peak memory 206828 kb
Host smart-b8826be4-e05e-4966-ac10-ad70ede21faa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402412230 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.1402412230
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3950149927
Short name T1060
Test name
Test status
Simulation time 17151561 ps
CPU time 0.96 seconds
Started Jul 21 06:33:49 PM PDT 24
Finished Jul 21 06:33:56 PM PDT 24
Peak memory 206944 kb
Host smart-06dd7ca6-b629-4a88-b515-511134ba59f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950149927 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3950149927
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.1700295294
Short name T1097
Test name
Test status
Simulation time 77548336 ps
CPU time 3.06 seconds
Started Jul 21 06:33:52 PM PDT 24
Finished Jul 21 06:34:00 PM PDT 24
Peak memory 215180 kb
Host smart-1cf4a486-d895-428a-97dd-47ad33281a33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700295294 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.1700295294
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1967367261
Short name T1076
Test name
Test status
Simulation time 368717718 ps
CPU time 1.41 seconds
Started Jul 21 06:33:54 PM PDT 24
Finished Jul 21 06:34:01 PM PDT 24
Peak memory 207000 kb
Host smart-79bf08ac-39b2-4fd2-a043-0dccf10f05ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967367261 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.1967367261
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1119096495
Short name T1107
Test name
Test status
Simulation time 18599588 ps
CPU time 1.44 seconds
Started Jul 21 06:33:54 PM PDT 24
Finished Jul 21 06:34:01 PM PDT 24
Peak memory 215232 kb
Host smart-358b5211-e467-4afd-b05c-4b84c8b66d28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119096495 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.1119096495
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.886173975
Short name T1099
Test name
Test status
Simulation time 77442894 ps
CPU time 0.94 seconds
Started Jul 21 06:33:51 PM PDT 24
Finished Jul 21 06:33:58 PM PDT 24
Peak memory 206848 kb
Host smart-ccc46274-137c-4b8c-ad04-026d0061f7de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886173975 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.886173975
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.1366435585
Short name T1032
Test name
Test status
Simulation time 11475394 ps
CPU time 0.86 seconds
Started Jul 21 06:33:54 PM PDT 24
Finished Jul 21 06:34:00 PM PDT 24
Peak memory 206868 kb
Host smart-65d49327-9cd9-43b5-9aca-273f4aee2648
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366435585 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1366435585
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.878211241
Short name T1074
Test name
Test status
Simulation time 25127990 ps
CPU time 1.14 seconds
Started Jul 21 06:33:55 PM PDT 24
Finished Jul 21 06:34:01 PM PDT 24
Peak memory 206888 kb
Host smart-11545342-8af2-4048-a0ca-51d057da5ada
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878211241 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_ou
tstanding.878211241
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.1743233409
Short name T1044
Test name
Test status
Simulation time 50551299 ps
CPU time 2.64 seconds
Started Jul 21 06:33:50 PM PDT 24
Finished Jul 21 06:33:58 PM PDT 24
Peak memory 215252 kb
Host smart-5f66124e-312f-452e-b333-1692555f5f9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743233409 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.1743233409
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3751306281
Short name T278
Test name
Test status
Simulation time 180346167 ps
CPU time 1.77 seconds
Started Jul 21 06:33:55 PM PDT 24
Finished Jul 21 06:34:03 PM PDT 24
Peak memory 206972 kb
Host smart-814eab43-2a91-45ba-bf74-80e8fdb323c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751306281 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3751306281
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.13063527
Short name T1056
Test name
Test status
Simulation time 49488478 ps
CPU time 1.64 seconds
Started Jul 21 06:33:58 PM PDT 24
Finished Jul 21 06:34:05 PM PDT 24
Peak memory 215156 kb
Host smart-342b04c7-47d9-4639-9818-73f23a9b5b0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13063527 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.13063527
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.215176693
Short name T1089
Test name
Test status
Simulation time 13462984 ps
CPU time 0.93 seconds
Started Jul 21 06:33:55 PM PDT 24
Finished Jul 21 06:34:02 PM PDT 24
Peak memory 206820 kb
Host smart-85d8836b-92b6-4b59-ae82-3d8f9236f2f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215176693 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.215176693
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2919908271
Short name T1031
Test name
Test status
Simulation time 41134009 ps
CPU time 0.82 seconds
Started Jul 21 06:33:54 PM PDT 24
Finished Jul 21 06:34:01 PM PDT 24
Peak memory 206884 kb
Host smart-fa567904-bfbf-4c19-a753-f152d5272f63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919908271 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2919908271
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2692918527
Short name T1066
Test name
Test status
Simulation time 37216355 ps
CPU time 1.39 seconds
Started Jul 21 06:33:56 PM PDT 24
Finished Jul 21 06:34:03 PM PDT 24
Peak memory 206872 kb
Host smart-04180452-744c-44a2-a8d0-857725c13100
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692918527 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.2692918527
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.126881525
Short name T1064
Test name
Test status
Simulation time 40190965 ps
CPU time 1.53 seconds
Started Jul 21 06:33:50 PM PDT 24
Finished Jul 21 06:33:58 PM PDT 24
Peak memory 215232 kb
Host smart-ff5e028e-8324-4a4e-ac76-7fe8ece3f992
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126881525 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.126881525
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2546835666
Short name T1067
Test name
Test status
Simulation time 317439356 ps
CPU time 2 seconds
Started Jul 21 06:33:51 PM PDT 24
Finished Jul 21 06:33:59 PM PDT 24
Peak memory 206956 kb
Host smart-2ec2c995-89c5-48d4-af21-bdc89484bd28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546835666 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.2546835666
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.302161920
Short name T1046
Test name
Test status
Simulation time 49047769 ps
CPU time 1.56 seconds
Started Jul 21 06:33:57 PM PDT 24
Finished Jul 21 06:34:04 PM PDT 24
Peak memory 215164 kb
Host smart-0a0c62f1-718d-4e11-9fd9-6b171fff5a90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302161920 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.302161920
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.3394101425
Short name T1096
Test name
Test status
Simulation time 59441948 ps
CPU time 0.86 seconds
Started Jul 21 06:33:57 PM PDT 24
Finished Jul 21 06:34:04 PM PDT 24
Peak memory 206644 kb
Host smart-e3ce2b84-09be-47f6-a051-e3fd869e3656
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394101425 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.3394101425
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2940621552
Short name T1085
Test name
Test status
Simulation time 76976826 ps
CPU time 0.95 seconds
Started Jul 21 06:33:59 PM PDT 24
Finished Jul 21 06:34:05 PM PDT 24
Peak memory 206864 kb
Host smart-5f8b3aa2-495d-49bd-b4b3-571f43988327
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940621552 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.2940621552
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.3434675919
Short name T1062
Test name
Test status
Simulation time 80336959 ps
CPU time 2.85 seconds
Started Jul 21 06:33:59 PM PDT 24
Finished Jul 21 06:34:07 PM PDT 24
Peak memory 223344 kb
Host smart-80aaa8ca-510f-4b60-9caf-7ce9c6c2d7e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434675919 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.3434675919
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1895124284
Short name T1124
Test name
Test status
Simulation time 75049364 ps
CPU time 1.54 seconds
Started Jul 21 06:33:59 PM PDT 24
Finished Jul 21 06:34:05 PM PDT 24
Peak memory 206932 kb
Host smart-a89aaf8c-9a25-44da-87d5-0398d65f7c1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895124284 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1895124284
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2982066178
Short name T253
Test name
Test status
Simulation time 159890292 ps
CPU time 1.46 seconds
Started Jul 21 06:33:33 PM PDT 24
Finished Jul 21 06:33:43 PM PDT 24
Peak memory 206812 kb
Host smart-41a97cbd-d923-439c-8def-64e560a9bc8d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982066178 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.2982066178
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1191977890
Short name T1105
Test name
Test status
Simulation time 62821431 ps
CPU time 2.03 seconds
Started Jul 21 06:33:32 PM PDT 24
Finished Jul 21 06:33:40 PM PDT 24
Peak memory 206944 kb
Host smart-6ced94d7-3882-49d0-af48-4891c300f72f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191977890 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1191977890
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2561702191
Short name T1072
Test name
Test status
Simulation time 42168589 ps
CPU time 0.96 seconds
Started Jul 21 06:33:32 PM PDT 24
Finished Jul 21 06:33:41 PM PDT 24
Peak memory 206852 kb
Host smart-15abfe01-3520-4769-96cb-fdd55f400e82
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561702191 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.2561702191
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2635190238
Short name T1008
Test name
Test status
Simulation time 48242494 ps
CPU time 1.32 seconds
Started Jul 21 06:33:32 PM PDT 24
Finished Jul 21 06:33:40 PM PDT 24
Peak memory 218000 kb
Host smart-946a08c1-a23d-4bdc-b064-9eb9343c96b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635190238 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.2635190238
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.27966542
Short name T262
Test name
Test status
Simulation time 11706857 ps
CPU time 0.85 seconds
Started Jul 21 06:33:33 PM PDT 24
Finished Jul 21 06:33:42 PM PDT 24
Peak memory 206812 kb
Host smart-204969bf-368b-407c-84db-def6d8fbc3db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27966542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.27966542
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.4128871480
Short name T1115
Test name
Test status
Simulation time 50043764 ps
CPU time 0.86 seconds
Started Jul 21 06:33:36 PM PDT 24
Finished Jul 21 06:33:46 PM PDT 24
Peak memory 206836 kb
Host smart-ac3ab02d-f503-4d5b-ae54-00ce75c07c03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128871480 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.4128871480
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2062108210
Short name T260
Test name
Test status
Simulation time 40830847 ps
CPU time 1.52 seconds
Started Jul 21 06:33:31 PM PDT 24
Finished Jul 21 06:33:37 PM PDT 24
Peak memory 206932 kb
Host smart-7a629045-b10d-41b2-b991-fd637ced94fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062108210 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.2062108210
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.974165341
Short name T1093
Test name
Test status
Simulation time 176644944 ps
CPU time 1.8 seconds
Started Jul 21 06:33:31 PM PDT 24
Finished Jul 21 06:33:37 PM PDT 24
Peak memory 215172 kb
Host smart-944d6137-b68a-428b-8a40-31b12399d5b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974165341 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.974165341
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.338312319
Short name T286
Test name
Test status
Simulation time 170533660 ps
CPU time 1.79 seconds
Started Jul 21 06:33:33 PM PDT 24
Finished Jul 21 06:33:43 PM PDT 24
Peak memory 215044 kb
Host smart-f7b8698c-2d36-4685-8a8e-0b90c83c25fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338312319 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.338312319
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.1111523719
Short name T1120
Test name
Test status
Simulation time 14455770 ps
CPU time 0.87 seconds
Started Jul 21 06:33:59 PM PDT 24
Finished Jul 21 06:34:05 PM PDT 24
Peak memory 206820 kb
Host smart-75a9e1f1-a3af-4780-8a0b-55a2612d2f0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111523719 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.1111523719
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.310615016
Short name T1071
Test name
Test status
Simulation time 44855992 ps
CPU time 0.9 seconds
Started Jul 21 06:33:57 PM PDT 24
Finished Jul 21 06:34:04 PM PDT 24
Peak memory 206876 kb
Host smart-b2a0f8c5-a521-4bd3-a016-bf78c3c857c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310615016 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.310615016
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.1329281773
Short name T1073
Test name
Test status
Simulation time 37228579 ps
CPU time 0.82 seconds
Started Jul 21 06:33:56 PM PDT 24
Finished Jul 21 06:34:03 PM PDT 24
Peak memory 206868 kb
Host smart-a6c075b2-af1b-4360-ae76-1ef211b36968
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329281773 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1329281773
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.1413020952
Short name T1050
Test name
Test status
Simulation time 12625552 ps
CPU time 0.86 seconds
Started Jul 21 06:33:58 PM PDT 24
Finished Jul 21 06:34:04 PM PDT 24
Peak memory 206840 kb
Host smart-5a96c7cc-2197-484d-9876-27f1fee58499
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413020952 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.1413020952
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.70167675
Short name T1128
Test name
Test status
Simulation time 18914212 ps
CPU time 0.83 seconds
Started Jul 21 06:33:56 PM PDT 24
Finished Jul 21 06:34:02 PM PDT 24
Peak memory 206624 kb
Host smart-c409e8d3-db9b-478b-bce7-f6d58d875f07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70167675 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.70167675
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.954594091
Short name T1081
Test name
Test status
Simulation time 176141523 ps
CPU time 0.98 seconds
Started Jul 21 06:33:57 PM PDT 24
Finished Jul 21 06:34:04 PM PDT 24
Peak memory 206672 kb
Host smart-8853827b-a093-4460-ad88-cab29d00173e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954594091 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.954594091
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.3807389838
Short name T1023
Test name
Test status
Simulation time 78503306 ps
CPU time 0.9 seconds
Started Jul 21 06:33:55 PM PDT 24
Finished Jul 21 06:34:01 PM PDT 24
Peak memory 206856 kb
Host smart-5513d388-b2fa-47e1-94e4-bbe2a6b960a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807389838 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.3807389838
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.2868324341
Short name T1112
Test name
Test status
Simulation time 17433115 ps
CPU time 0.83 seconds
Started Jul 21 06:33:57 PM PDT 24
Finished Jul 21 06:34:03 PM PDT 24
Peak memory 206712 kb
Host smart-605696fd-23b1-4225-8a53-d5402bda756c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868324341 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.2868324341
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.4218962874
Short name T1118
Test name
Test status
Simulation time 12063229 ps
CPU time 0.86 seconds
Started Jul 21 06:34:00 PM PDT 24
Finished Jul 21 06:34:05 PM PDT 24
Peak memory 206824 kb
Host smart-c5c75d55-25da-46f4-85f9-77e457ea19ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218962874 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.4218962874
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.947319717
Short name T1121
Test name
Test status
Simulation time 54132682 ps
CPU time 0.87 seconds
Started Jul 21 06:33:57 PM PDT 24
Finished Jul 21 06:34:03 PM PDT 24
Peak memory 206852 kb
Host smart-826ac2ab-6875-4f3c-b7b6-056b0efa28fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947319717 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.947319717
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3243725399
Short name T258
Test name
Test status
Simulation time 32255801 ps
CPU time 1.2 seconds
Started Jul 21 06:33:36 PM PDT 24
Finished Jul 21 06:33:47 PM PDT 24
Peak memory 206832 kb
Host smart-88c78788-f7bb-443a-bc82-b0fae9ffc0ae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243725399 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3243725399
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.770816010
Short name T244
Test name
Test status
Simulation time 153543352 ps
CPU time 1.98 seconds
Started Jul 21 06:33:37 PM PDT 24
Finished Jul 21 06:33:48 PM PDT 24
Peak memory 206804 kb
Host smart-77c3eaa6-8c10-45bd-9bc3-f857c148144a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770816010 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.770816010
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3492430226
Short name T243
Test name
Test status
Simulation time 17392275 ps
CPU time 0.98 seconds
Started Jul 21 06:33:37 PM PDT 24
Finished Jul 21 06:33:47 PM PDT 24
Peak memory 206840 kb
Host smart-9907b6d7-35af-4d72-9667-b882e51526bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492430226 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.3492430226
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3590865662
Short name T1013
Test name
Test status
Simulation time 27431975 ps
CPU time 1.78 seconds
Started Jul 21 06:33:37 PM PDT 24
Finished Jul 21 06:33:48 PM PDT 24
Peak memory 215132 kb
Host smart-b73a2a7b-7fce-48f1-9d68-7d88eb2d7fba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590865662 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3590865662
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.517344537
Short name T249
Test name
Test status
Simulation time 48880742 ps
CPU time 0.83 seconds
Started Jul 21 06:33:38 PM PDT 24
Finished Jul 21 06:33:47 PM PDT 24
Peak memory 206832 kb
Host smart-d37dac0e-5883-4ac9-896f-8bc1a8575fca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517344537 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.517344537
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.617181500
Short name T1014
Test name
Test status
Simulation time 13025998 ps
CPU time 0.86 seconds
Started Jul 21 06:33:36 PM PDT 24
Finished Jul 21 06:33:46 PM PDT 24
Peak memory 206800 kb
Host smart-bad96a78-2bb5-4e63-a165-6909c19402be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617181500 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.617181500
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2905241777
Short name T1055
Test name
Test status
Simulation time 61657178 ps
CPU time 1.57 seconds
Started Jul 21 06:33:36 PM PDT 24
Finished Jul 21 06:33:47 PM PDT 24
Peak memory 206964 kb
Host smart-c5a65722-2737-4634-852e-b0a4435e5274
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905241777 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.2905241777
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.2276657527
Short name T1125
Test name
Test status
Simulation time 78657864 ps
CPU time 1.79 seconds
Started Jul 21 06:33:32 PM PDT 24
Finished Jul 21 06:33:40 PM PDT 24
Peak memory 215076 kb
Host smart-ae06ca7f-d799-4fa4-b620-d4757d203232
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276657527 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.2276657527
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2997390240
Short name T1104
Test name
Test status
Simulation time 284688831 ps
CPU time 2.47 seconds
Started Jul 21 06:33:32 PM PDT 24
Finished Jul 21 06:33:41 PM PDT 24
Peak memory 206924 kb
Host smart-5065fa62-8345-4fcc-9286-5da4defc35d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997390240 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.2997390240
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.955412501
Short name T1034
Test name
Test status
Simulation time 15939781 ps
CPU time 0.92 seconds
Started Jul 21 06:33:58 PM PDT 24
Finished Jul 21 06:34:04 PM PDT 24
Peak memory 206812 kb
Host smart-e0e93a32-98da-423a-bf85-94846c75e051
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955412501 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.955412501
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.2004651191
Short name T1027
Test name
Test status
Simulation time 20163597 ps
CPU time 0.96 seconds
Started Jul 21 06:33:57 PM PDT 24
Finished Jul 21 06:34:03 PM PDT 24
Peak memory 206820 kb
Host smart-135efef8-05a5-433e-839f-0f104f420ebc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004651191 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2004651191
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.1838045583
Short name T1010
Test name
Test status
Simulation time 66430363 ps
CPU time 0.85 seconds
Started Jul 21 06:33:57 PM PDT 24
Finished Jul 21 06:34:03 PM PDT 24
Peak memory 206828 kb
Host smart-afeb4502-f54f-4226-a1ee-36bc1985d701
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838045583 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.1838045583
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.3037926212
Short name T1047
Test name
Test status
Simulation time 16175264 ps
CPU time 0.89 seconds
Started Jul 21 06:33:57 PM PDT 24
Finished Jul 21 06:34:03 PM PDT 24
Peak memory 206816 kb
Host smart-0ee5a2d6-7e8a-4e89-8cea-5c3247f0ff2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037926212 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3037926212
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.3050218037
Short name T1053
Test name
Test status
Simulation time 28944560 ps
CPU time 0.76 seconds
Started Jul 21 06:33:57 PM PDT 24
Finished Jul 21 06:34:04 PM PDT 24
Peak memory 206640 kb
Host smart-3c1eb176-6fc9-4f83-8ec9-8e82a22f0b77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050218037 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3050218037
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.3971831958
Short name T1059
Test name
Test status
Simulation time 46259269 ps
CPU time 0.93 seconds
Started Jul 21 06:33:56 PM PDT 24
Finished Jul 21 06:34:03 PM PDT 24
Peak memory 206836 kb
Host smart-770138d1-5d27-4401-a38e-5588196ff3ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971831958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3971831958
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3615837432
Short name T1122
Test name
Test status
Simulation time 38616636 ps
CPU time 0.81 seconds
Started Jul 21 06:33:58 PM PDT 24
Finished Jul 21 06:34:04 PM PDT 24
Peak memory 206840 kb
Host smart-761dfdb8-0617-463d-8325-e180b0d2212d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615837432 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3615837432
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.3991560360
Short name T1114
Test name
Test status
Simulation time 39104672 ps
CPU time 0.8 seconds
Started Jul 21 06:33:59 PM PDT 24
Finished Jul 21 06:34:05 PM PDT 24
Peak memory 206640 kb
Host smart-61ab85c4-b287-4acd-9b7c-b520c5e279ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991560360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.3991560360
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.1715362586
Short name T1036
Test name
Test status
Simulation time 18498109 ps
CPU time 0.88 seconds
Started Jul 21 06:33:56 PM PDT 24
Finished Jul 21 06:34:03 PM PDT 24
Peak memory 206756 kb
Host smart-ebb310ae-853c-4400-87b3-05396387400d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715362586 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1715362586
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.2233920155
Short name T1006
Test name
Test status
Simulation time 16060060 ps
CPU time 0.92 seconds
Started Jul 21 06:33:56 PM PDT 24
Finished Jul 21 06:34:02 PM PDT 24
Peak memory 206888 kb
Host smart-05fce57e-9421-4e13-a39c-6ffd9fb424ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233920155 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.2233920155
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.559759286
Short name T1126
Test name
Test status
Simulation time 82795892 ps
CPU time 1.17 seconds
Started Jul 21 06:33:36 PM PDT 24
Finished Jul 21 06:33:46 PM PDT 24
Peak memory 206860 kb
Host smart-8ccce358-2054-44a3-a64f-49d20066a72a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559759286 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.559759286
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2663418410
Short name T1129
Test name
Test status
Simulation time 202980946 ps
CPU time 3.02 seconds
Started Jul 21 06:33:36 PM PDT 24
Finished Jul 21 06:33:48 PM PDT 24
Peak memory 206924 kb
Host smart-223455ec-1098-4538-b447-63effa0dc4f4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663418410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2663418410
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1380794238
Short name T250
Test name
Test status
Simulation time 11385627 ps
CPU time 0.87 seconds
Started Jul 21 06:33:38 PM PDT 24
Finished Jul 21 06:33:47 PM PDT 24
Peak memory 206828 kb
Host smart-344e618d-eaca-466c-abaf-bc20c775b9de
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380794238 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.1380794238
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1233640265
Short name T1069
Test name
Test status
Simulation time 65707538 ps
CPU time 1.32 seconds
Started Jul 21 06:33:36 PM PDT 24
Finished Jul 21 06:33:47 PM PDT 24
Peak memory 217528 kb
Host smart-a080d07b-7078-4488-8de3-8feb2001b00e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233640265 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.1233640265
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.1279826348
Short name T268
Test name
Test status
Simulation time 54509661 ps
CPU time 0.91 seconds
Started Jul 21 06:33:36 PM PDT 24
Finished Jul 21 06:33:46 PM PDT 24
Peak memory 206860 kb
Host smart-f3277d6a-5cda-42f3-a560-6799a710c783
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279826348 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.1279826348
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.4239694239
Short name T1070
Test name
Test status
Simulation time 12060562 ps
CPU time 0.85 seconds
Started Jul 21 06:33:40 PM PDT 24
Finished Jul 21 06:33:49 PM PDT 24
Peak memory 206812 kb
Host smart-6d7b49b8-d96d-4301-b075-a7475104aabc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239694239 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.4239694239
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.480101819
Short name T1079
Test name
Test status
Simulation time 32896079 ps
CPU time 1.15 seconds
Started Jul 21 06:33:37 PM PDT 24
Finished Jul 21 06:33:47 PM PDT 24
Peak memory 206968 kb
Host smart-1d7d08bd-ae54-4568-acab-9ca64189ccd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480101819 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_out
standing.480101819
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.3861987918
Short name T1087
Test name
Test status
Simulation time 20712411 ps
CPU time 1.5 seconds
Started Jul 21 06:33:36 PM PDT 24
Finished Jul 21 06:33:47 PM PDT 24
Peak memory 215212 kb
Host smart-801bd2c6-d70c-464f-b410-5a41caa3ad3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861987918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.3861987918
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2022689947
Short name T283
Test name
Test status
Simulation time 106638611 ps
CPU time 2.76 seconds
Started Jul 21 06:33:36 PM PDT 24
Finished Jul 21 06:33:48 PM PDT 24
Peak memory 206904 kb
Host smart-735e7491-91db-4a94-a66a-c3ee0ff82a30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022689947 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.2022689947
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.1314418494
Short name T1012
Test name
Test status
Simulation time 13424799 ps
CPU time 0.89 seconds
Started Jul 21 06:34:01 PM PDT 24
Finished Jul 21 06:34:06 PM PDT 24
Peak memory 206808 kb
Host smart-acf60116-6834-4242-a84f-18ec70936898
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314418494 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1314418494
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.2459427992
Short name T1025
Test name
Test status
Simulation time 32485426 ps
CPU time 0.83 seconds
Started Jul 21 06:33:57 PM PDT 24
Finished Jul 21 06:34:04 PM PDT 24
Peak memory 206572 kb
Host smart-4d3c97c5-31ed-4b4c-91fb-687be0bb1846
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459427992 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.2459427992
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.3688959860
Short name T1002
Test name
Test status
Simulation time 19563509 ps
CPU time 0.85 seconds
Started Jul 21 06:33:56 PM PDT 24
Finished Jul 21 06:34:03 PM PDT 24
Peak memory 206668 kb
Host smart-06a274ad-685a-4de6-ae78-53e779a1aa4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688959860 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3688959860
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.341770907
Short name T1063
Test name
Test status
Simulation time 18012288 ps
CPU time 0.94 seconds
Started Jul 21 06:33:58 PM PDT 24
Finished Jul 21 06:34:05 PM PDT 24
Peak memory 206832 kb
Host smart-35527df0-72b8-4ae6-81fb-d460e6e83157
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341770907 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.341770907
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.53607873
Short name T1022
Test name
Test status
Simulation time 17059076 ps
CPU time 0.79 seconds
Started Jul 21 06:33:57 PM PDT 24
Finished Jul 21 06:34:03 PM PDT 24
Peak memory 206656 kb
Host smart-a91b6dfd-4412-4186-b78a-d572e84ad5ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53607873 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.53607873
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.3271200349
Short name T1057
Test name
Test status
Simulation time 89108687 ps
CPU time 0.81 seconds
Started Jul 21 06:34:05 PM PDT 24
Finished Jul 21 06:34:09 PM PDT 24
Peak memory 206676 kb
Host smart-d0e520d6-2a3d-4f53-bfc3-285be969584f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271200349 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.3271200349
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.571884845
Short name T1026
Test name
Test status
Simulation time 37274694 ps
CPU time 0.8 seconds
Started Jul 21 06:34:10 PM PDT 24
Finished Jul 21 06:34:15 PM PDT 24
Peak memory 206648 kb
Host smart-eb24fba6-5c8d-4f9a-b986-5a1db9bf1d8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571884845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.571884845
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.3275955288
Short name T1098
Test name
Test status
Simulation time 16823852 ps
CPU time 0.96 seconds
Started Jul 21 06:34:06 PM PDT 24
Finished Jul 21 06:34:10 PM PDT 24
Peak memory 206876 kb
Host smart-d1f39630-98d5-41d8-ba5e-b8780a53f101
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275955288 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.3275955288
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.2580081618
Short name T1094
Test name
Test status
Simulation time 52806849 ps
CPU time 0.92 seconds
Started Jul 21 06:34:03 PM PDT 24
Finished Jul 21 06:34:08 PM PDT 24
Peak memory 206796 kb
Host smart-a69da9e0-c177-48ba-9bf0-a349e4488e4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580081618 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.2580081618
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.332660951
Short name T1052
Test name
Test status
Simulation time 20587909 ps
CPU time 0.9 seconds
Started Jul 21 06:34:06 PM PDT 24
Finished Jul 21 06:34:11 PM PDT 24
Peak memory 206728 kb
Host smart-3e7059e3-e6c3-4480-be08-cc272e301667
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332660951 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.332660951
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1643003751
Short name T1111
Test name
Test status
Simulation time 17512666 ps
CPU time 1.21 seconds
Started Jul 21 06:33:45 PM PDT 24
Finished Jul 21 06:33:52 PM PDT 24
Peak memory 215136 kb
Host smart-4419a17a-1111-4f8f-bd96-42dc48232e0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643003751 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1643003751
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.2435172824
Short name T1109
Test name
Test status
Simulation time 36999756 ps
CPU time 0.85 seconds
Started Jul 21 06:33:46 PM PDT 24
Finished Jul 21 06:33:52 PM PDT 24
Peak memory 206660 kb
Host smart-7bdf7827-5b5d-4124-a73d-ec53729f2f3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435172824 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2435172824
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.1289260199
Short name T1086
Test name
Test status
Simulation time 15504532 ps
CPU time 0.91 seconds
Started Jul 21 06:33:45 PM PDT 24
Finished Jul 21 06:33:52 PM PDT 24
Peak memory 206816 kb
Host smart-73dc67e8-73e6-4ea2-87c3-b60eeec46d36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289260199 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1289260199
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3402065268
Short name T1078
Test name
Test status
Simulation time 37579758 ps
CPU time 1.03 seconds
Started Jul 21 06:33:45 PM PDT 24
Finished Jul 21 06:33:52 PM PDT 24
Peak memory 206848 kb
Host smart-9f78fb02-1c0c-470c-b812-6af5a20c5404
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402065268 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.3402065268
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.753646365
Short name T1004
Test name
Test status
Simulation time 509838006 ps
CPU time 4.5 seconds
Started Jul 21 06:33:38 PM PDT 24
Finished Jul 21 06:33:51 PM PDT 24
Peak memory 215112 kb
Host smart-f59dd41b-35ba-40b3-b71f-0771d0834d74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753646365 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.753646365
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3994548653
Short name T1091
Test name
Test status
Simulation time 409558318 ps
CPU time 2.35 seconds
Started Jul 21 06:33:46 PM PDT 24
Finished Jul 21 06:33:54 PM PDT 24
Peak memory 206916 kb
Host smart-f2ea63a4-46ff-4dbf-b96d-54ace31afdc2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994548653 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.3994548653
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3027237327
Short name T1029
Test name
Test status
Simulation time 27871396 ps
CPU time 1.37 seconds
Started Jul 21 06:33:47 PM PDT 24
Finished Jul 21 06:33:55 PM PDT 24
Peak memory 223264 kb
Host smart-ad4e8f9c-4b42-4814-ba37-d2c9f7d0073a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027237327 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3027237327
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.1453505788
Short name T256
Test name
Test status
Simulation time 40571164 ps
CPU time 0.82 seconds
Started Jul 21 06:33:43 PM PDT 24
Finished Jul 21 06:33:51 PM PDT 24
Peak memory 206692 kb
Host smart-b73a0e17-0c32-4004-a7cb-31733a8a7fba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453505788 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1453505788
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.2286449600
Short name T1030
Test name
Test status
Simulation time 15936501 ps
CPU time 0.84 seconds
Started Jul 21 06:33:45 PM PDT 24
Finished Jul 21 06:33:52 PM PDT 24
Peak memory 206808 kb
Host smart-d18b8ded-11a7-49cd-9ec5-904a99bf1347
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286449600 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.2286449600
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2466928282
Short name T1049
Test name
Test status
Simulation time 41538309 ps
CPU time 0.9 seconds
Started Jul 21 06:33:43 PM PDT 24
Finished Jul 21 06:33:51 PM PDT 24
Peak memory 207092 kb
Host smart-3656d2cc-2521-4cc7-a952-546f276950a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466928282 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.2466928282
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.316460125
Short name T1130
Test name
Test status
Simulation time 97110256 ps
CPU time 2.01 seconds
Started Jul 21 06:33:43 PM PDT 24
Finished Jul 21 06:33:52 PM PDT 24
Peak memory 215156 kb
Host smart-86bd03db-5483-4b83-a9a9-692b5f5eedbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316460125 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.316460125
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1468406116
Short name T287
Test name
Test status
Simulation time 553777169 ps
CPU time 3.31 seconds
Started Jul 21 06:33:50 PM PDT 24
Finished Jul 21 06:34:00 PM PDT 24
Peak memory 206928 kb
Host smart-025be17f-e80f-4abd-95ff-fb8376c19bcb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468406116 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.1468406116
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1278009782
Short name T1103
Test name
Test status
Simulation time 42073439 ps
CPU time 1.48 seconds
Started Jul 21 06:33:45 PM PDT 24
Finished Jul 21 06:33:53 PM PDT 24
Peak memory 215176 kb
Host smart-d39e2083-04ce-4275-a8b5-01795dd84d56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278009782 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1278009782
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.304609944
Short name T257
Test name
Test status
Simulation time 12532348 ps
CPU time 0.88 seconds
Started Jul 21 06:33:44 PM PDT 24
Finished Jul 21 06:33:51 PM PDT 24
Peak memory 206800 kb
Host smart-68103315-be04-4c04-ad3b-57573904b84b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304609944 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.304609944
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.1231338444
Short name T1045
Test name
Test status
Simulation time 28558999 ps
CPU time 0.83 seconds
Started Jul 21 06:33:45 PM PDT 24
Finished Jul 21 06:33:52 PM PDT 24
Peak memory 206832 kb
Host smart-26fbe7c7-6d0f-4ced-9cdc-56bece158360
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231338444 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.1231338444
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3985560922
Short name T1127
Test name
Test status
Simulation time 85494167 ps
CPU time 1.1 seconds
Started Jul 21 06:33:44 PM PDT 24
Finished Jul 21 06:33:51 PM PDT 24
Peak memory 206936 kb
Host smart-a6206dca-0386-41d2-9ba6-df8bef732926
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985560922 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.3985560922
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.1168490561
Short name T1095
Test name
Test status
Simulation time 282548010 ps
CPU time 2.87 seconds
Started Jul 21 06:33:45 PM PDT 24
Finished Jul 21 06:33:54 PM PDT 24
Peak memory 215192 kb
Host smart-381ad3f0-b3ec-491c-8bad-3328f5429c90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168490561 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.1168490561
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.4083632743
Short name T1119
Test name
Test status
Simulation time 286904975 ps
CPU time 2.27 seconds
Started Jul 21 06:33:47 PM PDT 24
Finished Jul 21 06:33:55 PM PDT 24
Peak memory 206928 kb
Host smart-8470ee5f-cb23-48b2-a7b1-4d497319875a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083632743 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.4083632743
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.700329401
Short name T1040
Test name
Test status
Simulation time 76274781 ps
CPU time 1.29 seconds
Started Jul 21 06:33:44 PM PDT 24
Finished Jul 21 06:33:51 PM PDT 24
Peak memory 215172 kb
Host smart-ccd0e450-02f2-4bd4-a3e5-2c4a28f01737
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700329401 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.700329401
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.2924296830
Short name T247
Test name
Test status
Simulation time 33696805 ps
CPU time 0.88 seconds
Started Jul 21 06:33:47 PM PDT 24
Finished Jul 21 06:33:54 PM PDT 24
Peak memory 206848 kb
Host smart-68d285e3-8730-485c-924d-376c1416a3fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924296830 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.2924296830
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.629113721
Short name T1088
Test name
Test status
Simulation time 61300508 ps
CPU time 0.81 seconds
Started Jul 21 06:33:47 PM PDT 24
Finished Jul 21 06:33:53 PM PDT 24
Peak memory 206664 kb
Host smart-fc2c30b9-f4f0-43d4-ab1b-627b5cebf957
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629113721 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.629113721
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2881464897
Short name T1035
Test name
Test status
Simulation time 39825008 ps
CPU time 1.06 seconds
Started Jul 21 06:33:46 PM PDT 24
Finished Jul 21 06:33:52 PM PDT 24
Peak memory 206964 kb
Host smart-2a4ab754-6ae4-4007-9987-899591b7ca69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881464897 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.2881464897
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.1920402494
Short name T1054
Test name
Test status
Simulation time 51828738 ps
CPU time 2.03 seconds
Started Jul 21 06:33:46 PM PDT 24
Finished Jul 21 06:33:54 PM PDT 24
Peak memory 223376 kb
Host smart-cfc79542-7b97-430a-aef2-c85ace9e12a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920402494 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.1920402494
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1954915136
Short name T284
Test name
Test status
Simulation time 302425447 ps
CPU time 1.57 seconds
Started Jul 21 06:33:46 PM PDT 24
Finished Jul 21 06:33:53 PM PDT 24
Peak memory 207132 kb
Host smart-bda3e21b-4598-4f90-9354-2fcead801436
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954915136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1954915136
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2896009690
Short name T1058
Test name
Test status
Simulation time 27805760 ps
CPU time 0.94 seconds
Started Jul 21 06:33:47 PM PDT 24
Finished Jul 21 06:33:54 PM PDT 24
Peak memory 206960 kb
Host smart-8cd99b0f-3bc5-4aa9-af26-376119da0691
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896009690 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.2896009690
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.764648225
Short name T266
Test name
Test status
Simulation time 13305974 ps
CPU time 0.88 seconds
Started Jul 21 06:33:46 PM PDT 24
Finished Jul 21 06:33:52 PM PDT 24
Peak memory 206868 kb
Host smart-c17853c8-cd03-4a9c-8d02-ec0807d61a8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764648225 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.764648225
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2578249169
Short name T1106
Test name
Test status
Simulation time 53738582 ps
CPU time 0.9 seconds
Started Jul 21 06:33:44 PM PDT 24
Finished Jul 21 06:33:51 PM PDT 24
Peak memory 206836 kb
Host smart-0885ed7d-96bc-4b21-805a-263109d48d99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578249169 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2578249169
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2709033717
Short name T1037
Test name
Test status
Simulation time 30878603 ps
CPU time 1.11 seconds
Started Jul 21 06:33:46 PM PDT 24
Finished Jul 21 06:33:53 PM PDT 24
Peak memory 206940 kb
Host smart-8ac5fa44-bda4-491b-af38-fe8a728e76a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709033717 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.2709033717
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.4163255716
Short name T1033
Test name
Test status
Simulation time 116453672 ps
CPU time 4.08 seconds
Started Jul 21 06:33:46 PM PDT 24
Finished Jul 21 06:33:56 PM PDT 24
Peak memory 215164 kb
Host smart-a2d8d727-9a01-4ade-8553-758a3af2a44d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163255716 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.4163255716
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.16119380
Short name T276
Test name
Test status
Simulation time 220301553 ps
CPU time 2.33 seconds
Started Jul 21 06:33:45 PM PDT 24
Finished Jul 21 06:33:54 PM PDT 24
Peak memory 215144 kb
Host smart-c0320af3-8d2a-42fa-ba85-37e66aacd613
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16119380 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.16119380
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.569074777
Short name T631
Test name
Test status
Simulation time 35524624 ps
CPU time 1.07 seconds
Started Jul 21 06:40:39 PM PDT 24
Finished Jul 21 06:40:40 PM PDT 24
Peak memory 218924 kb
Host smart-2eacd736-94bc-4076-b9a4-924fdae94fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569074777 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.569074777
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.1515166597
Short name T962
Test name
Test status
Simulation time 14855131 ps
CPU time 0.96 seconds
Started Jul 21 06:40:39 PM PDT 24
Finished Jul 21 06:40:41 PM PDT 24
Peak memory 215404 kb
Host smart-7bce76dd-2091-4e28-a1f8-2d46f81884a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515166597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.1515166597
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.3381230764
Short name T585
Test name
Test status
Simulation time 28485102 ps
CPU time 0.82 seconds
Started Jul 21 06:40:43 PM PDT 24
Finished Jul 21 06:40:45 PM PDT 24
Peak memory 216128 kb
Host smart-5c8f99cd-ce48-427e-b4d6-91377b98aed0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381230764 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3381230764
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_err.1579233076
Short name T742
Test name
Test status
Simulation time 27634960 ps
CPU time 1 seconds
Started Jul 21 06:40:42 PM PDT 24
Finished Jul 21 06:40:43 PM PDT 24
Peak memory 224048 kb
Host smart-e946e001-03fe-4748-8658-7fa0bbd8eec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579233076 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1579233076
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_regwen.2428557861
Short name T729
Test name
Test status
Simulation time 26657202 ps
CPU time 0.89 seconds
Started Jul 21 06:40:40 PM PDT 24
Finished Jul 21 06:40:42 PM PDT 24
Peak memory 207352 kb
Host smart-ca23e488-1afc-4576-8fc0-7c84c8948a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428557861 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.2428557861
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.1488896405
Short name T18
Test name
Test status
Simulation time 550501209 ps
CPU time 4.71 seconds
Started Jul 21 06:40:39 PM PDT 24
Finished Jul 21 06:40:45 PM PDT 24
Peak memory 235596 kb
Host smart-80c68efc-f1ab-49e4-aef5-f11d07e3b7d3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488896405 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1488896405
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.3340160736
Short name T798
Test name
Test status
Simulation time 16649167 ps
CPU time 0.97 seconds
Started Jul 21 06:40:40 PM PDT 24
Finished Jul 21 06:40:42 PM PDT 24
Peak memory 215564 kb
Host smart-49bd9014-375b-4527-9613-38f5c9db67a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340160736 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.3340160736
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.1723005954
Short name T890
Test name
Test status
Simulation time 63144791722 ps
CPU time 655.08 seconds
Started Jul 21 06:40:39 PM PDT 24
Finished Jul 21 06:51:35 PM PDT 24
Peak memory 220656 kb
Host smart-fb0b00a8-bd7d-4407-9396-7252fbedc3b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723005954 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.1723005954
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.1111146865
Short name T822
Test name
Test status
Simulation time 72069397 ps
CPU time 1.1 seconds
Started Jul 21 06:40:38 PM PDT 24
Finished Jul 21 06:40:40 PM PDT 24
Peak memory 219924 kb
Host smart-1eb6ac4b-1b41-474d-8771-7c8b4b267d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111146865 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1111146865
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.1375040522
Short name T952
Test name
Test status
Simulation time 25028767 ps
CPU time 0.91 seconds
Started Jul 21 06:40:42 PM PDT 24
Finished Jul 21 06:40:44 PM PDT 24
Peak memory 215452 kb
Host smart-9b3fdfa0-760f-4f03-a3f2-4e782350be62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375040522 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1375040522
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2311788454
Short name T504
Test name
Test status
Simulation time 88498344 ps
CPU time 1.05 seconds
Started Jul 21 06:40:39 PM PDT 24
Finished Jul 21 06:40:41 PM PDT 24
Peak memory 218532 kb
Host smart-00eea661-74a6-4598-b0c3-382e1cc466a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311788454 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2311788454
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.2700702034
Short name T51
Test name
Test status
Simulation time 24789887 ps
CPU time 1.07 seconds
Started Jul 21 06:40:43 PM PDT 24
Finished Jul 21 06:40:45 PM PDT 24
Peak memory 223896 kb
Host smart-af16ffca-8a5b-4711-8922-9c5632ca9106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700702034 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.2700702034
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.2652295340
Short name T647
Test name
Test status
Simulation time 38781057 ps
CPU time 1.39 seconds
Started Jul 21 06:40:43 PM PDT 24
Finished Jul 21 06:40:45 PM PDT 24
Peak memory 218932 kb
Host smart-56707fed-4fcd-46c7-99ed-610dbd4100cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652295340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2652295340
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.2702692113
Short name T108
Test name
Test status
Simulation time 21928985 ps
CPU time 1.06 seconds
Started Jul 21 06:40:42 PM PDT 24
Finished Jul 21 06:40:44 PM PDT 24
Peak memory 216164 kb
Host smart-d12b96f5-e10a-4ff1-89c8-d1a4e9dadcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702692113 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.2702692113
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.3014011437
Short name T293
Test name
Test status
Simulation time 49338724 ps
CPU time 0.88 seconds
Started Jul 21 06:40:42 PM PDT 24
Finished Jul 21 06:40:43 PM PDT 24
Peak memory 207360 kb
Host smart-f359408e-2ef1-49f9-84ff-4dfde11543b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014011437 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.3014011437
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_smoke.1911745629
Short name T346
Test name
Test status
Simulation time 57053256 ps
CPU time 0.89 seconds
Started Jul 21 06:40:41 PM PDT 24
Finished Jul 21 06:40:43 PM PDT 24
Peak memory 215552 kb
Host smart-5eb58883-e7e8-4430-9040-b175ed66488c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911745629 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1911745629
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.1442664470
Short name T883
Test name
Test status
Simulation time 1736108031 ps
CPU time 2.7 seconds
Started Jul 21 06:40:44 PM PDT 24
Finished Jul 21 06:40:47 PM PDT 24
Peak memory 220036 kb
Host smart-9647000b-2971-48ba-af0e-e58fe5e03cd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442664470 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.1442664470
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.2189917698
Short name T751
Test name
Test status
Simulation time 42465139547 ps
CPU time 479.85 seconds
Started Jul 21 06:40:39 PM PDT 24
Finished Jul 21 06:48:40 PM PDT 24
Peak memory 220464 kb
Host smart-55b097f5-32bf-4577-ac77-7c5a6334aa0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189917698 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.2189917698
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.1648777150
Short name T735
Test name
Test status
Simulation time 45900027 ps
CPU time 1.18 seconds
Started Jul 21 06:40:49 PM PDT 24
Finished Jul 21 06:40:51 PM PDT 24
Peak memory 219080 kb
Host smart-37c02b83-0711-4028-acb3-00ef2f074842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648777150 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.1648777150
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.1829242872
Short name T543
Test name
Test status
Simulation time 45262135 ps
CPU time 0.85 seconds
Started Jul 21 06:40:50 PM PDT 24
Finished Jul 21 06:40:52 PM PDT 24
Peak memory 215172 kb
Host smart-ea428081-f560-4892-a0d1-2a06905bacd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829242872 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.1829242872
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.3555166844
Short name T505
Test name
Test status
Simulation time 13378821 ps
CPU time 0.94 seconds
Started Jul 21 06:40:52 PM PDT 24
Finished Jul 21 06:40:55 PM PDT 24
Peak memory 216544 kb
Host smart-2c90a1bf-9c8f-4415-9ce8-d32c6d61eb00
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555166844 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.3555166844
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.701560621
Short name T587
Test name
Test status
Simulation time 38614157 ps
CPU time 1.04 seconds
Started Jul 21 06:40:48 PM PDT 24
Finished Jul 21 06:40:50 PM PDT 24
Peak memory 215888 kb
Host smart-7d9ef407-34bc-4587-b466-745d299788b6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701560621 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_di
sable_auto_req_mode.701560621
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.59154830
Short name T72
Test name
Test status
Simulation time 26226037 ps
CPU time 1.1 seconds
Started Jul 21 06:40:49 PM PDT 24
Finished Jul 21 06:40:53 PM PDT 24
Peak memory 219844 kb
Host smart-d2fd90f9-689e-4e23-ab7a-67abab6b4a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59154830 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.59154830
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.3113396362
Short name T387
Test name
Test status
Simulation time 26260303 ps
CPU time 1.28 seconds
Started Jul 21 06:40:50 PM PDT 24
Finished Jul 21 06:40:54 PM PDT 24
Peak memory 219088 kb
Host smart-af3ec644-2af3-44a5-a51d-39efd5ef9412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113396362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3113396362
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.3164136888
Short name T109
Test name
Test status
Simulation time 24322234 ps
CPU time 1.01 seconds
Started Jul 21 06:40:49 PM PDT 24
Finished Jul 21 06:40:51 PM PDT 24
Peak memory 216148 kb
Host smart-8468b12c-7b58-44ea-b4e7-28087b5513d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164136888 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3164136888
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.912981632
Short name T591
Test name
Test status
Simulation time 53059928 ps
CPU time 0.94 seconds
Started Jul 21 06:40:49 PM PDT 24
Finished Jul 21 06:40:52 PM PDT 24
Peak memory 215512 kb
Host smart-6ed95124-9c85-4701-807b-d6acb6a918ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912981632 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.912981632
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.141826448
Short name T706
Test name
Test status
Simulation time 341649064 ps
CPU time 7.42 seconds
Started Jul 21 06:40:51 PM PDT 24
Finished Jul 21 06:41:00 PM PDT 24
Peak memory 217432 kb
Host smart-09128fde-0d51-48df-87d5-68a347fd267e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141826448 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.141826448
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/100.edn_alert.3000243704
Short name T240
Test name
Test status
Simulation time 29530729 ps
CPU time 1.38 seconds
Started Jul 21 06:42:13 PM PDT 24
Finished Jul 21 06:42:16 PM PDT 24
Peak memory 219232 kb
Host smart-363637e2-56fb-42c4-a435-e2d607cac269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000243704 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.3000243704
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.49148137
Short name T915
Test name
Test status
Simulation time 77212364 ps
CPU time 1.51 seconds
Started Jul 21 06:42:25 PM PDT 24
Finished Jul 21 06:42:27 PM PDT 24
Peak memory 219000 kb
Host smart-4890100f-d0ff-4ec0-8efd-f930ac678b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49148137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.49148137
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.420574230
Short name T160
Test name
Test status
Simulation time 301600312 ps
CPU time 1.39 seconds
Started Jul 21 06:42:20 PM PDT 24
Finished Jul 21 06:42:23 PM PDT 24
Peak memory 220940 kb
Host smart-7076e91a-f8cb-4151-8146-8478d450f330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420574230 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.420574230
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.2095139722
Short name T896
Test name
Test status
Simulation time 27274374 ps
CPU time 1.24 seconds
Started Jul 21 06:42:33 PM PDT 24
Finished Jul 21 06:42:35 PM PDT 24
Peak memory 217500 kb
Host smart-73880c87-a326-4de0-9042-535ef3a61e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095139722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.2095139722
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.3585440829
Short name T674
Test name
Test status
Simulation time 26724651 ps
CPU time 1.2 seconds
Started Jul 21 06:42:28 PM PDT 24
Finished Jul 21 06:42:30 PM PDT 24
Peak memory 221380 kb
Host smart-1f3d5ba1-83ae-448c-9924-eddf0e2ab01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585440829 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.3585440829
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/103.edn_alert.434692568
Short name T954
Test name
Test status
Simulation time 46820758 ps
CPU time 1.15 seconds
Started Jul 21 06:42:29 PM PDT 24
Finished Jul 21 06:42:31 PM PDT 24
Peak memory 219024 kb
Host smart-fec2b68a-5810-4608-826a-ae4fe6f64156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434692568 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.434692568
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.3433369556
Short name T365
Test name
Test status
Simulation time 39511407 ps
CPU time 1.42 seconds
Started Jul 21 06:42:16 PM PDT 24
Finished Jul 21 06:42:19 PM PDT 24
Peak memory 215520 kb
Host smart-9e057c9e-9cb1-443c-8035-b99dd601a26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433369556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3433369556
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.1583922003
Short name T946
Test name
Test status
Simulation time 101262995 ps
CPU time 1.13 seconds
Started Jul 21 06:42:17 PM PDT 24
Finished Jul 21 06:42:20 PM PDT 24
Peak memory 220412 kb
Host smart-c049e8ab-57e9-4512-966c-262b24fe6802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583922003 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.1583922003
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.2537149772
Short name T616
Test name
Test status
Simulation time 45171306 ps
CPU time 1.35 seconds
Started Jul 21 06:42:31 PM PDT 24
Finished Jul 21 06:42:33 PM PDT 24
Peak memory 220420 kb
Host smart-b6bf151c-5096-417e-8da7-1e0b6d8bc4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537149772 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.2537149772
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.4031536949
Short name T580
Test name
Test status
Simulation time 26173480 ps
CPU time 1.24 seconds
Started Jul 21 06:42:21 PM PDT 24
Finished Jul 21 06:42:23 PM PDT 24
Peak memory 221024 kb
Host smart-49f77755-71af-4028-9882-ec2f022f8c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031536949 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.4031536949
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.1966450342
Short name T847
Test name
Test status
Simulation time 254924111 ps
CPU time 3.4 seconds
Started Jul 21 06:42:15 PM PDT 24
Finished Jul 21 06:42:20 PM PDT 24
Peak memory 217764 kb
Host smart-ddf154b5-7b1e-49e3-a596-def35d994627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966450342 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1966450342
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.2561152756
Short name T814
Test name
Test status
Simulation time 29334905 ps
CPU time 1.32 seconds
Started Jul 21 06:42:16 PM PDT 24
Finished Jul 21 06:42:18 PM PDT 24
Peak memory 221492 kb
Host smart-ea643cd9-069c-4861-87b3-733bc361d9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561152756 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.2561152756
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.3873237957
Short name T322
Test name
Test status
Simulation time 46565933 ps
CPU time 1.28 seconds
Started Jul 21 06:42:21 PM PDT 24
Finished Jul 21 06:42:24 PM PDT 24
Peak memory 220288 kb
Host smart-c257d86e-51d5-4dd3-a804-fea37d5dbb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873237957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.3873237957
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.1739129009
Short name T956
Test name
Test status
Simulation time 47796416 ps
CPU time 1.11 seconds
Started Jul 21 06:42:17 PM PDT 24
Finished Jul 21 06:42:19 PM PDT 24
Peak memory 218852 kb
Host smart-01020c21-e253-4dd3-b701-838d08fe68f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739129009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.1739129009
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.2306367404
Short name T772
Test name
Test status
Simulation time 44141335 ps
CPU time 1.51 seconds
Started Jul 21 06:42:23 PM PDT 24
Finished Jul 21 06:42:26 PM PDT 24
Peak memory 219224 kb
Host smart-b42d0dc2-04c0-4333-9b6e-c5f2e2aa188b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306367404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.2306367404
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.4197369963
Short name T989
Test name
Test status
Simulation time 42404424 ps
CPU time 1.11 seconds
Started Jul 21 06:42:16 PM PDT 24
Finished Jul 21 06:42:18 PM PDT 24
Peak memory 220220 kb
Host smart-e1ce86e1-d317-4b87-b4d9-953ea2d69223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197369963 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.4197369963
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert.2707478620
Short name T933
Test name
Test status
Simulation time 30740791 ps
CPU time 1.24 seconds
Started Jul 21 06:40:58 PM PDT 24
Finished Jul 21 06:41:00 PM PDT 24
Peak memory 221020 kb
Host smart-942be304-89bd-4596-8596-74c2c22f1ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707478620 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.2707478620
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.3919138456
Short name T459
Test name
Test status
Simulation time 33370472 ps
CPU time 0.95 seconds
Started Jul 21 06:40:55 PM PDT 24
Finished Jul 21 06:40:57 PM PDT 24
Peak memory 215196 kb
Host smart-1a0bf8ae-c060-4615-960c-7305fc1bcf19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919138456 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.3919138456
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.2062373059
Short name T789
Test name
Test status
Simulation time 196046433 ps
CPU time 1.17 seconds
Started Jul 21 06:40:55 PM PDT 24
Finished Jul 21 06:40:57 PM PDT 24
Peak memory 217344 kb
Host smart-cce5ed47-156c-4a74-8fde-dd12e40a91b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062373059 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.2062373059
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.3232521509
Short name T732
Test name
Test status
Simulation time 53261053 ps
CPU time 0.82 seconds
Started Jul 21 06:40:55 PM PDT 24
Finished Jul 21 06:40:57 PM PDT 24
Peak memory 218548 kb
Host smart-6fd94758-bb09-480b-b734-35333f96d7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232521509 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.3232521509
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.3073734355
Short name T376
Test name
Test status
Simulation time 65848157 ps
CPU time 1.38 seconds
Started Jul 21 06:40:49 PM PDT 24
Finished Jul 21 06:40:53 PM PDT 24
Peak memory 219072 kb
Host smart-db07caab-a6bf-44a2-b57c-726db7522414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073734355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.3073734355
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.938401257
Short name T837
Test name
Test status
Simulation time 26591993 ps
CPU time 0.98 seconds
Started Jul 21 06:40:53 PM PDT 24
Finished Jul 21 06:40:56 PM PDT 24
Peak memory 215784 kb
Host smart-4949d361-6695-4697-9cd9-ea1acce3494e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938401257 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.938401257
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.1349472871
Short name T424
Test name
Test status
Simulation time 17228108 ps
CPU time 0.99 seconds
Started Jul 21 06:40:49 PM PDT 24
Finished Jul 21 06:40:52 PM PDT 24
Peak memory 215528 kb
Host smart-6cd0891c-eca4-491b-8dc1-bc53cb15ec69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349472871 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.1349472871
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.1869288957
Short name T463
Test name
Test status
Simulation time 34562238 ps
CPU time 1.02 seconds
Started Jul 21 06:40:51 PM PDT 24
Finished Jul 21 06:40:54 PM PDT 24
Peak memory 206604 kb
Host smart-4c7895c3-7a18-49cd-bc17-bde1728b05bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869288957 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1869288957
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.3187647306
Short name T2
Test name
Test status
Simulation time 19602157409 ps
CPU time 478.97 seconds
Started Jul 21 06:40:48 PM PDT 24
Finished Jul 21 06:48:48 PM PDT 24
Peak memory 223936 kb
Host smart-d24e23e5-39ac-49e0-9eb1-69d7edeb9b37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187647306 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.3187647306
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.2661187866
Short name T802
Test name
Test status
Simulation time 76604543 ps
CPU time 1.15 seconds
Started Jul 21 06:42:26 PM PDT 24
Finished Jul 21 06:42:28 PM PDT 24
Peak memory 219684 kb
Host smart-eccc1eb8-9b80-4be3-9a4c-54e66654c70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661187866 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.2661187866
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.3480181346
Short name T391
Test name
Test status
Simulation time 257083761 ps
CPU time 3.01 seconds
Started Jul 21 06:42:24 PM PDT 24
Finished Jul 21 06:42:28 PM PDT 24
Peak memory 218796 kb
Host smart-fa425d79-5407-401c-abfc-03bd58fa6a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480181346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.3480181346
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.2569345618
Short name T612
Test name
Test status
Simulation time 109114986 ps
CPU time 2.24 seconds
Started Jul 21 06:42:22 PM PDT 24
Finished Jul 21 06:42:26 PM PDT 24
Peak memory 219676 kb
Host smart-2397ad73-81e3-4122-a660-b7d4632ab339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569345618 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.2569345618
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.3520589013
Short name T628
Test name
Test status
Simulation time 121356986 ps
CPU time 1.22 seconds
Started Jul 21 06:42:24 PM PDT 24
Finished Jul 21 06:42:27 PM PDT 24
Peak memory 218644 kb
Host smart-d356e176-a594-4dab-9f92-2cb0e4997cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520589013 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.3520589013
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.1246297978
Short name T497
Test name
Test status
Simulation time 94363100 ps
CPU time 1.23 seconds
Started Jul 21 06:42:16 PM PDT 24
Finished Jul 21 06:42:19 PM PDT 24
Peak memory 220368 kb
Host smart-2dc513ae-d02d-47f7-a428-283552137a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246297978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1246297978
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.838390964
Short name T398
Test name
Test status
Simulation time 31174809 ps
CPU time 1.13 seconds
Started Jul 21 06:42:15 PM PDT 24
Finished Jul 21 06:42:17 PM PDT 24
Peak memory 219016 kb
Host smart-98b60616-5fe7-4d9c-b2c0-65fad803f3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838390964 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.838390964
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.1109994469
Short name T875
Test name
Test status
Simulation time 149993712 ps
CPU time 1.65 seconds
Started Jul 21 06:42:15 PM PDT 24
Finished Jul 21 06:42:17 PM PDT 24
Peak memory 217752 kb
Host smart-cb44c084-6156-46c3-b54c-31946508a6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109994469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.1109994469
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.377026277
Short name T856
Test name
Test status
Simulation time 59916988 ps
CPU time 1.23 seconds
Started Jul 21 06:42:21 PM PDT 24
Finished Jul 21 06:42:24 PM PDT 24
Peak memory 219028 kb
Host smart-e7e5dad3-7090-48fd-8292-05d8cc7fd607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377026277 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.377026277
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.1372417207
Short name T42
Test name
Test status
Simulation time 133675765 ps
CPU time 1.75 seconds
Started Jul 21 06:42:17 PM PDT 24
Finished Jul 21 06:42:21 PM PDT 24
Peak memory 219044 kb
Host smart-926ea738-387b-4483-b6df-d9db87943dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372417207 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.1372417207
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.946888653
Short name T887
Test name
Test status
Simulation time 88247962 ps
CPU time 1.13 seconds
Started Jul 21 06:42:23 PM PDT 24
Finished Jul 21 06:42:25 PM PDT 24
Peak memory 218964 kb
Host smart-a590031d-a326-4301-9611-bf5b578f9858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946888653 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.946888653
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.279952167
Short name T574
Test name
Test status
Simulation time 109561969 ps
CPU time 1.56 seconds
Started Jul 21 06:42:15 PM PDT 24
Finished Jul 21 06:42:18 PM PDT 24
Peak memory 219200 kb
Host smart-13e2fb20-036a-4fe1-b0f8-6315faad2cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279952167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.279952167
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.964226177
Short name T929
Test name
Test status
Simulation time 121939998 ps
CPU time 1.26 seconds
Started Jul 21 06:42:20 PM PDT 24
Finished Jul 21 06:42:24 PM PDT 24
Peak memory 221592 kb
Host smart-8fc2727c-db18-4485-adc8-c6a7b4793afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964226177 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.964226177
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/118.edn_alert.4014146556
Short name T239
Test name
Test status
Simulation time 99765979 ps
CPU time 1.12 seconds
Started Jul 21 06:42:24 PM PDT 24
Finished Jul 21 06:42:27 PM PDT 24
Peak memory 220928 kb
Host smart-62c9272b-5844-430a-8c14-770723c4853e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014146556 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.4014146556
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.1971457751
Short name T556
Test name
Test status
Simulation time 32658220 ps
CPU time 1.37 seconds
Started Jul 21 06:42:31 PM PDT 24
Finished Jul 21 06:42:33 PM PDT 24
Peak memory 217416 kb
Host smart-a16f1983-4020-4f11-87a1-1cecc8bea28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971457751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1971457751
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.1641805793
Short name T809
Test name
Test status
Simulation time 27321311 ps
CPU time 1.25 seconds
Started Jul 21 06:42:43 PM PDT 24
Finished Jul 21 06:42:46 PM PDT 24
Peak memory 219016 kb
Host smart-94056a11-e653-4dad-aac3-4b384128bd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641805793 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.1641805793
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.2804153520
Short name T338
Test name
Test status
Simulation time 103375128 ps
CPU time 3.4 seconds
Started Jul 21 06:42:26 PM PDT 24
Finished Jul 21 06:42:30 PM PDT 24
Peak memory 218920 kb
Host smart-7b5de1a0-662e-4c5a-845f-f2a62971fc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804153520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.2804153520
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.1363365824
Short name T101
Test name
Test status
Simulation time 106037390 ps
CPU time 1.09 seconds
Started Jul 21 06:40:55 PM PDT 24
Finished Jul 21 06:40:56 PM PDT 24
Peak memory 220688 kb
Host smart-d9af3ffb-5c30-4dcf-9aa4-262f26c0e44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363365824 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.1363365824
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.3197648012
Short name T642
Test name
Test status
Simulation time 26721960 ps
CPU time 0.89 seconds
Started Jul 21 06:40:54 PM PDT 24
Finished Jul 21 06:40:56 PM PDT 24
Peak memory 207028 kb
Host smart-771a72ac-b611-4131-97a0-462b987b6b94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197648012 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3197648012
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.2165157404
Short name T578
Test name
Test status
Simulation time 85831488 ps
CPU time 1.09 seconds
Started Jul 21 06:41:07 PM PDT 24
Finished Jul 21 06:41:09 PM PDT 24
Peak memory 218708 kb
Host smart-abb68eea-25c3-4f98-906c-22f0cc4b3909
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165157404 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.2165157404
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.2469781764
Short name T938
Test name
Test status
Simulation time 90524404 ps
CPU time 0.92 seconds
Started Jul 21 06:40:55 PM PDT 24
Finished Jul 21 06:40:58 PM PDT 24
Peak memory 219036 kb
Host smart-3a61b030-2748-49f4-baaf-487a15a4cd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469781764 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.2469781764
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.3073258200
Short name T781
Test name
Test status
Simulation time 60272403 ps
CPU time 1.57 seconds
Started Jul 21 06:40:58 PM PDT 24
Finished Jul 21 06:41:01 PM PDT 24
Peak memory 218820 kb
Host smart-5e64a96b-1bcc-4229-9df0-5487c335b2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073258200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.3073258200
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.486420570
Short name T771
Test name
Test status
Simulation time 27321953 ps
CPU time 0.92 seconds
Started Jul 21 06:40:54 PM PDT 24
Finished Jul 21 06:40:56 PM PDT 24
Peak memory 215704 kb
Host smart-e76e85dd-3126-4026-9e04-e9ef326c0a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486420570 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.486420570
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.219699792
Short name T562
Test name
Test status
Simulation time 38482585 ps
CPU time 0.93 seconds
Started Jul 21 06:40:56 PM PDT 24
Finished Jul 21 06:40:58 PM PDT 24
Peak memory 215624 kb
Host smart-093c7d34-68ea-4fa5-82dc-2963f7541af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219699792 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.219699792
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.870837400
Short name T750
Test name
Test status
Simulation time 1015713520 ps
CPU time 5.28 seconds
Started Jul 21 06:40:59 PM PDT 24
Finished Jul 21 06:41:05 PM PDT 24
Peak memory 215520 kb
Host smart-15d311ba-ee62-4aa5-88ea-69c788f0bc69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870837400 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.870837400
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.2661308731
Short name T381
Test name
Test status
Simulation time 26803668002 ps
CPU time 680.37 seconds
Started Jul 21 06:40:55 PM PDT 24
Finished Jul 21 06:52:16 PM PDT 24
Peak memory 218940 kb
Host smart-c042904a-ec24-497b-a40b-7ca3894d6237
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661308731 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.2661308731
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.2685605648
Short name T275
Test name
Test status
Simulation time 42676351 ps
CPU time 1.19 seconds
Started Jul 21 06:42:33 PM PDT 24
Finished Jul 21 06:42:35 PM PDT 24
Peak memory 219036 kb
Host smart-af0773bb-f647-4fc7-8473-8bac73e38358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685605648 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.2685605648
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.867481616
Short name T660
Test name
Test status
Simulation time 24986485 ps
CPU time 1.26 seconds
Started Jul 21 06:42:38 PM PDT 24
Finished Jul 21 06:42:40 PM PDT 24
Peak memory 220064 kb
Host smart-29d9b1c5-a9e5-42fd-90bb-fee4d5bfec01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867481616 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.867481616
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.3965999981
Short name T400
Test name
Test status
Simulation time 27532424 ps
CPU time 1.24 seconds
Started Jul 21 06:42:29 PM PDT 24
Finished Jul 21 06:42:30 PM PDT 24
Peak memory 218764 kb
Host smart-d504c9eb-2bdd-4565-b8d4-f7e171c0c0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965999981 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.3965999981
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.2504297141
Short name T874
Test name
Test status
Simulation time 84237677 ps
CPU time 1.58 seconds
Started Jul 21 06:42:36 PM PDT 24
Finished Jul 21 06:42:39 PM PDT 24
Peak memory 218760 kb
Host smart-a0ef37bd-4dcd-4d45-933f-cb66836a06fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504297141 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.2504297141
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.562511875
Short name T503
Test name
Test status
Simulation time 25423368 ps
CPU time 1.19 seconds
Started Jul 21 06:42:28 PM PDT 24
Finished Jul 21 06:42:30 PM PDT 24
Peak memory 219188 kb
Host smart-ea814653-d31a-4f8c-a8a5-d02eb1ace24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562511875 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.562511875
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/124.edn_alert.1041819530
Short name T455
Test name
Test status
Simulation time 47538987 ps
CPU time 1.14 seconds
Started Jul 21 06:42:22 PM PDT 24
Finished Jul 21 06:42:24 PM PDT 24
Peak memory 218888 kb
Host smart-12cfb106-2d82-4626-b37d-406c92826930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041819530 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.1041819530
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.991996933
Short name T85
Test name
Test status
Simulation time 83999987 ps
CPU time 1.12 seconds
Started Jul 21 06:42:17 PM PDT 24
Finished Jul 21 06:42:20 PM PDT 24
Peak memory 217488 kb
Host smart-919ff9b1-77ea-4357-ba51-f10f6fbd5579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991996933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.991996933
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.1441218296
Short name T613
Test name
Test status
Simulation time 28809509 ps
CPU time 1.23 seconds
Started Jul 21 06:42:17 PM PDT 24
Finished Jul 21 06:42:20 PM PDT 24
Peak memory 220124 kb
Host smart-ec258766-e135-4472-a4ab-40046c34a0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441218296 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.1441218296
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/126.edn_alert.4033640604
Short name T960
Test name
Test status
Simulation time 87467137 ps
CPU time 1.19 seconds
Started Jul 21 06:42:29 PM PDT 24
Finished Jul 21 06:42:31 PM PDT 24
Peak memory 219084 kb
Host smart-fb7b3f51-acda-4de1-a2cb-de88f4064605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033640604 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.4033640604
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/127.edn_alert.348617570
Short name T125
Test name
Test status
Simulation time 49605482 ps
CPU time 1.23 seconds
Started Jul 21 06:42:22 PM PDT 24
Finished Jul 21 06:42:24 PM PDT 24
Peak memory 219984 kb
Host smart-e2b44c3a-d684-4f2b-af3e-59c89cd1a1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348617570 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.348617570
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.2628049470
Short name T724
Test name
Test status
Simulation time 133076752 ps
CPU time 1.54 seconds
Started Jul 21 06:42:27 PM PDT 24
Finished Jul 21 06:42:29 PM PDT 24
Peak memory 219276 kb
Host smart-62b0bf59-bed7-4122-adeb-2807fde8eab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628049470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.2628049470
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.1875545299
Short name T213
Test name
Test status
Simulation time 40177360 ps
CPU time 1.2 seconds
Started Jul 21 06:42:21 PM PDT 24
Finished Jul 21 06:42:24 PM PDT 24
Peak memory 221492 kb
Host smart-9da0bfb0-3638-4409-9007-ae9b4632bb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875545299 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.1875545299
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.2167521237
Short name T584
Test name
Test status
Simulation time 88103618 ps
CPU time 1.61 seconds
Started Jul 21 06:42:22 PM PDT 24
Finished Jul 21 06:42:24 PM PDT 24
Peak memory 219108 kb
Host smart-87db2587-b4cd-4fcc-aa87-9115134bd091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167521237 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.2167521237
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.751489501
Short name T271
Test name
Test status
Simulation time 55523650 ps
CPU time 1.31 seconds
Started Jul 21 06:42:39 PM PDT 24
Finished Jul 21 06:42:41 PM PDT 24
Peak memory 220256 kb
Host smart-0df16d95-1d48-4cda-aeb8-72cc3eda72f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751489501 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.751489501
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.3788099256
Short name T930
Test name
Test status
Simulation time 49405882 ps
CPU time 1.52 seconds
Started Jul 21 06:42:28 PM PDT 24
Finished Jul 21 06:42:30 PM PDT 24
Peak memory 218720 kb
Host smart-3e737776-66dd-4d30-a728-53035eacd3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788099256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.3788099256
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.2341321346
Short name T910
Test name
Test status
Simulation time 39274586 ps
CPU time 1.19 seconds
Started Jul 21 06:40:55 PM PDT 24
Finished Jul 21 06:40:57 PM PDT 24
Peak memory 219500 kb
Host smart-f6773dba-fdea-4eb8-a74f-1baf54dcf97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341321346 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.2341321346
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.3803664736
Short name T685
Test name
Test status
Simulation time 19114599 ps
CPU time 0.95 seconds
Started Jul 21 06:40:55 PM PDT 24
Finished Jul 21 06:40:58 PM PDT 24
Peak memory 207056 kb
Host smart-4bb53125-33b7-41b0-a435-756837716f39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803664736 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3803664736
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.279854615
Short name T63
Test name
Test status
Simulation time 10881103 ps
CPU time 1.04 seconds
Started Jul 21 06:41:07 PM PDT 24
Finished Jul 21 06:41:09 PM PDT 24
Peak memory 216464 kb
Host smart-99356140-3103-482b-bdca-c67f7b46f48a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279854615 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.279854615
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.4176742609
Short name T602
Test name
Test status
Simulation time 21304602 ps
CPU time 1.04 seconds
Started Jul 21 06:40:57 PM PDT 24
Finished Jul 21 06:41:00 PM PDT 24
Peak memory 220052 kb
Host smart-ac5b29df-b7d0-4e23-9c61-6491d7c263e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176742609 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.4176742609
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.3064903391
Short name T53
Test name
Test status
Simulation time 19609477 ps
CPU time 1.26 seconds
Started Jul 21 06:41:07 PM PDT 24
Finished Jul 21 06:41:09 PM PDT 24
Peak memory 224276 kb
Host smart-f00080ea-e326-4a43-ab32-d5be21748aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064903391 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.3064903391
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.746690254
Short name T318
Test name
Test status
Simulation time 61688336 ps
CPU time 1.62 seconds
Started Jul 21 06:40:55 PM PDT 24
Finished Jul 21 06:40:59 PM PDT 24
Peak memory 218748 kb
Host smart-81652971-1c62-4bd8-98d5-fef941043ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746690254 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.746690254
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.1690314283
Short name T863
Test name
Test status
Simulation time 21239964 ps
CPU time 1.13 seconds
Started Jul 21 06:41:07 PM PDT 24
Finished Jul 21 06:41:09 PM PDT 24
Peak memory 215496 kb
Host smart-e68ec78a-4be8-418b-93bc-ef81e555123f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690314283 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.1690314283
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.2747181653
Short name T955
Test name
Test status
Simulation time 32326265 ps
CPU time 1.04 seconds
Started Jul 21 06:40:56 PM PDT 24
Finished Jul 21 06:40:59 PM PDT 24
Peak memory 215528 kb
Host smart-869229b8-993c-4b6d-bea7-346c89ad2b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747181653 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.2747181653
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.3841526133
Short name T95
Test name
Test status
Simulation time 272953640 ps
CPU time 5.38 seconds
Started Jul 21 06:40:56 PM PDT 24
Finished Jul 21 06:41:03 PM PDT 24
Peak memory 215556 kb
Host smart-95cb9b70-e5a6-42c1-9b52-68054d4ab749
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841526133 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3841526133
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.3075098537
Short name T226
Test name
Test status
Simulation time 156396706061 ps
CPU time 969.74 seconds
Started Jul 21 06:40:56 PM PDT 24
Finished Jul 21 06:57:07 PM PDT 24
Peak memory 221956 kb
Host smart-3ebe02f3-444d-46d4-b9f7-d74c86f9f820
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075098537 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.3075098537
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.878671367
Short name T588
Test name
Test status
Simulation time 187610653 ps
CPU time 1.2 seconds
Started Jul 21 06:42:44 PM PDT 24
Finished Jul 21 06:42:46 PM PDT 24
Peak memory 219924 kb
Host smart-31a79dae-938f-4034-8b85-50e463983036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878671367 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.878671367
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.3933205542
Short name T383
Test name
Test status
Simulation time 201557010 ps
CPU time 2.06 seconds
Started Jul 21 06:42:28 PM PDT 24
Finished Jul 21 06:42:30 PM PDT 24
Peak memory 220372 kb
Host smart-e7996d6f-3ae8-46f0-b6b0-968b251fe5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933205542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.3933205542
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.2784019653
Short name T973
Test name
Test status
Simulation time 21992269 ps
CPU time 1.23 seconds
Started Jul 21 06:42:24 PM PDT 24
Finished Jul 21 06:42:26 PM PDT 24
Peak memory 218884 kb
Host smart-17bf7455-302f-433c-bbee-da2d5e7c60cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784019653 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.2784019653
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.2716040083
Short name T695
Test name
Test status
Simulation time 49787937 ps
CPU time 1.58 seconds
Started Jul 21 06:42:25 PM PDT 24
Finished Jul 21 06:42:27 PM PDT 24
Peak memory 218760 kb
Host smart-af07f6e0-092e-4b20-b255-c05ea824d0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716040083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2716040083
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.2785468514
Short name T682
Test name
Test status
Simulation time 53437365 ps
CPU time 1.67 seconds
Started Jul 21 06:42:43 PM PDT 24
Finished Jul 21 06:42:46 PM PDT 24
Peak memory 218704 kb
Host smart-2a816d7c-d0c0-4c6b-a960-d03de6a78ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785468514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.2785468514
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.1946920556
Short name T520
Test name
Test status
Simulation time 65927775 ps
CPU time 1.04 seconds
Started Jul 21 06:42:23 PM PDT 24
Finished Jul 21 06:42:25 PM PDT 24
Peak memory 217568 kb
Host smart-edb203aa-9cbb-4298-89cb-599234c266b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946920556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1946920556
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.590207968
Short name T292
Test name
Test status
Simulation time 116115069 ps
CPU time 1.58 seconds
Started Jul 21 06:42:43 PM PDT 24
Finished Jul 21 06:42:46 PM PDT 24
Peak memory 219232 kb
Host smart-fabfa2cd-a44b-4d2e-bb45-b1821d8c01eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590207968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.590207968
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.3749010022
Short name T432
Test name
Test status
Simulation time 214832641 ps
CPU time 1.32 seconds
Started Jul 21 06:42:26 PM PDT 24
Finished Jul 21 06:42:28 PM PDT 24
Peak memory 221028 kb
Host smart-ace278a6-c4e3-4d31-a0b4-a5c680b005d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749010022 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.3749010022
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.2132919339
Short name T327
Test name
Test status
Simulation time 85259517 ps
CPU time 1.46 seconds
Started Jul 21 06:42:26 PM PDT 24
Finished Jul 21 06:42:29 PM PDT 24
Peak memory 220480 kb
Host smart-6afa5d56-9aa1-49ee-a0e9-2d9437031eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132919339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.2132919339
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.3124857487
Short name T288
Test name
Test status
Simulation time 105433964 ps
CPU time 1.26 seconds
Started Jul 21 06:42:35 PM PDT 24
Finished Jul 21 06:42:37 PM PDT 24
Peak memory 218836 kb
Host smart-cf7e67f5-13be-4957-96a7-ace0a55aeb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124857487 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.3124857487
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.2928486686
Short name T325
Test name
Test status
Simulation time 48960653 ps
CPU time 2.07 seconds
Started Jul 21 06:42:43 PM PDT 24
Finished Jul 21 06:42:47 PM PDT 24
Peak memory 218728 kb
Host smart-827775de-2df6-4af5-b250-18f60b05344f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928486686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.2928486686
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.711459515
Short name T597
Test name
Test status
Simulation time 151778926 ps
CPU time 1.26 seconds
Started Jul 21 06:42:24 PM PDT 24
Finished Jul 21 06:42:27 PM PDT 24
Peak memory 219924 kb
Host smart-5c798c76-6a14-4894-bc2a-88304fd19581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711459515 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.711459515
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.3551491008
Short name T651
Test name
Test status
Simulation time 66074267 ps
CPU time 1.14 seconds
Started Jul 21 06:42:28 PM PDT 24
Finished Jul 21 06:42:30 PM PDT 24
Peak memory 218912 kb
Host smart-8bdd4708-fc4d-4c34-b032-eed7d72d7b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551491008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.3551491008
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.1420234438
Short name T384
Test name
Test status
Simulation time 83026786 ps
CPU time 2.07 seconds
Started Jul 21 06:42:21 PM PDT 24
Finished Jul 21 06:42:24 PM PDT 24
Peak memory 217824 kb
Host smart-abc94ca6-713f-4b5c-a20b-5fd7af866995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420234438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1420234438
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.854162771
Short name T281
Test name
Test status
Simulation time 34536090 ps
CPU time 1.33 seconds
Started Jul 21 06:42:31 PM PDT 24
Finished Jul 21 06:42:32 PM PDT 24
Peak memory 215604 kb
Host smart-cd81de7e-ed27-41a1-b197-395c4b62f1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854162771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.854162771
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.3279404538
Short name T526
Test name
Test status
Simulation time 23390072 ps
CPU time 1.19 seconds
Started Jul 21 06:41:03 PM PDT 24
Finished Jul 21 06:41:05 PM PDT 24
Peak memory 221164 kb
Host smart-8b328906-2883-46f5-b8e2-ef4af35e24a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279404538 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3279404538
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.1575015065
Short name T779
Test name
Test status
Simulation time 19482228 ps
CPU time 0.89 seconds
Started Jul 21 06:41:00 PM PDT 24
Finished Jul 21 06:41:02 PM PDT 24
Peak memory 207000 kb
Host smart-4cb9aa64-44d6-4525-9b6f-5cbaddfca15e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575015065 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1575015065
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.1778504426
Short name T467
Test name
Test status
Simulation time 10850470 ps
CPU time 0.92 seconds
Started Jul 21 06:41:02 PM PDT 24
Finished Jul 21 06:41:03 PM PDT 24
Peak memory 215728 kb
Host smart-3758c933-bcd6-47bf-86f4-b310b7048a39
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778504426 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1778504426
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.3077234742
Short name T145
Test name
Test status
Simulation time 84199816 ps
CPU time 1.04 seconds
Started Jul 21 06:41:04 PM PDT 24
Finished Jul 21 06:41:06 PM PDT 24
Peak memory 217088 kb
Host smart-08447ee0-371e-4d22-8c3e-def9c50ff07c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077234742 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.3077234742
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.886627241
Short name T60
Test name
Test status
Simulation time 19322320 ps
CPU time 1.07 seconds
Started Jul 21 06:41:00 PM PDT 24
Finished Jul 21 06:41:02 PM PDT 24
Peak memory 218792 kb
Host smart-906776cb-7456-44a1-878f-a26b485c429b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886627241 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.886627241
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.1144767518
Short name T939
Test name
Test status
Simulation time 74956330 ps
CPU time 1.48 seconds
Started Jul 21 06:40:56 PM PDT 24
Finished Jul 21 06:41:00 PM PDT 24
Peak memory 220156 kb
Host smart-325f7ceb-3bf0-4711-89e6-c031b10321de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144767518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.1144767518
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.3675707553
Short name T343
Test name
Test status
Simulation time 31380278 ps
CPU time 0.94 seconds
Started Jul 21 06:41:02 PM PDT 24
Finished Jul 21 06:41:04 PM PDT 24
Peak memory 215820 kb
Host smart-7cbbf4d1-74da-45bf-9b7b-4932b831e280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675707553 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3675707553
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.2872490027
Short name T269
Test name
Test status
Simulation time 15085630 ps
CPU time 1.01 seconds
Started Jul 21 06:40:55 PM PDT 24
Finished Jul 21 06:40:58 PM PDT 24
Peak memory 215628 kb
Host smart-7032d4f2-9ff0-4ce0-ad6b-fafe552f1f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872490027 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2872490027
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.1066636049
Short name T982
Test name
Test status
Simulation time 202992047 ps
CPU time 2.25 seconds
Started Jul 21 06:40:54 PM PDT 24
Finished Jul 21 06:40:57 PM PDT 24
Peak memory 215640 kb
Host smart-332b158a-c0f9-4e3c-a695-d9c50b4574ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066636049 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1066636049
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.179534095
Short name T649
Test name
Test status
Simulation time 191268309815 ps
CPU time 1025.5 seconds
Started Jul 21 06:40:57 PM PDT 24
Finished Jul 21 06:58:04 PM PDT 24
Peak memory 222888 kb
Host smart-1f5ae789-a0e7-45f2-b280-8f48342ca218
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179534095 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.179534095
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.1259401959
Short name T510
Test name
Test status
Simulation time 28732280 ps
CPU time 1.25 seconds
Started Jul 21 06:42:41 PM PDT 24
Finished Jul 21 06:42:43 PM PDT 24
Peak memory 219260 kb
Host smart-210ffc47-ce17-4fdb-a010-e9ce02fc0e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259401959 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.1259401959
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.4161730025
Short name T579
Test name
Test status
Simulation time 74372840 ps
CPU time 1.04 seconds
Started Jul 21 06:42:48 PM PDT 24
Finished Jul 21 06:42:51 PM PDT 24
Peak memory 217664 kb
Host smart-6cdf757f-aa89-4e62-b81e-855019e0ffb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161730025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.4161730025
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.2440836708
Short name T169
Test name
Test status
Simulation time 65319387 ps
CPU time 1.03 seconds
Started Jul 21 06:42:34 PM PDT 24
Finished Jul 21 06:42:36 PM PDT 24
Peak memory 218664 kb
Host smart-e01a5a97-16f6-45ca-8b57-635e6500415c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440836708 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.2440836708
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.315516016
Short name T321
Test name
Test status
Simulation time 58497005 ps
CPU time 2.01 seconds
Started Jul 21 06:42:34 PM PDT 24
Finished Jul 21 06:42:38 PM PDT 24
Peak memory 215520 kb
Host smart-6e379f4d-d2e6-490e-b0b3-f3c7ae048e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315516016 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.315516016
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.1158325724
Short name T876
Test name
Test status
Simulation time 48562502 ps
CPU time 1.25 seconds
Started Jul 21 06:42:37 PM PDT 24
Finished Jul 21 06:42:39 PM PDT 24
Peak memory 219320 kb
Host smart-9b3ebaf5-631d-4caf-b78a-942e6f96d7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158325724 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.1158325724
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.4285181909
Short name T972
Test name
Test status
Simulation time 55534091 ps
CPU time 1.9 seconds
Started Jul 21 06:42:36 PM PDT 24
Finished Jul 21 06:42:39 PM PDT 24
Peak memory 218696 kb
Host smart-c56b2242-2172-4630-bf21-07c430f79589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285181909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.4285181909
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.2200538927
Short name T925
Test name
Test status
Simulation time 40966213 ps
CPU time 1.42 seconds
Started Jul 21 06:42:46 PM PDT 24
Finished Jul 21 06:42:50 PM PDT 24
Peak memory 218728 kb
Host smart-9b7ad82c-09a7-4e1d-9d38-885a7c2f47af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200538927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.2200538927
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.1670542866
Short name T237
Test name
Test status
Simulation time 52309809 ps
CPU time 1.65 seconds
Started Jul 21 06:42:33 PM PDT 24
Finished Jul 21 06:42:36 PM PDT 24
Peak memory 218576 kb
Host smart-12121dab-adf8-4cb4-81fa-d1a4f6938f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670542866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.1670542866
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.3880726906
Short name T841
Test name
Test status
Simulation time 43584229 ps
CPU time 1.22 seconds
Started Jul 21 06:42:39 PM PDT 24
Finished Jul 21 06:42:41 PM PDT 24
Peak memory 219700 kb
Host smart-c8bce562-1c2a-4d97-ab4b-86d25c3b39be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880726906 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.3880726906
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.1235360418
Short name T334
Test name
Test status
Simulation time 67296430 ps
CPU time 1.12 seconds
Started Jul 21 06:42:35 PM PDT 24
Finished Jul 21 06:42:37 PM PDT 24
Peak memory 219064 kb
Host smart-17295b89-432c-4eb6-a9b0-cd0cbef0e918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235360418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.1235360418
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.2566133126
Short name T947
Test name
Test status
Simulation time 41801349 ps
CPU time 1.21 seconds
Started Jul 21 06:42:32 PM PDT 24
Finished Jul 21 06:42:34 PM PDT 24
Peak memory 218960 kb
Host smart-00a8d920-d9bd-48bf-bec9-53e9913c6c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566133126 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.2566133126
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.2209534009
Short name T468
Test name
Test status
Simulation time 65474661 ps
CPU time 1.92 seconds
Started Jul 21 06:42:41 PM PDT 24
Finished Jul 21 06:42:44 PM PDT 24
Peak memory 217768 kb
Host smart-7e362035-1f5e-402d-835f-697788d5b0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209534009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2209534009
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.3478748916
Short name T358
Test name
Test status
Simulation time 29569152 ps
CPU time 1.11 seconds
Started Jul 21 06:42:45 PM PDT 24
Finished Jul 21 06:42:48 PM PDT 24
Peak memory 219940 kb
Host smart-8efc534d-2199-4896-964c-d0eea46af67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478748916 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.3478748916
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.3706748413
Short name T912
Test name
Test status
Simulation time 88625073 ps
CPU time 1.65 seconds
Started Jul 21 06:42:32 PM PDT 24
Finished Jul 21 06:42:35 PM PDT 24
Peak memory 218868 kb
Host smart-70f1d4b2-da37-4eec-be59-74a5ec0d184c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706748413 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3706748413
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.3882783062
Short name T430
Test name
Test status
Simulation time 83984608 ps
CPU time 1.33 seconds
Started Jul 21 06:42:32 PM PDT 24
Finished Jul 21 06:42:34 PM PDT 24
Peak memory 219072 kb
Host smart-b29d1f35-26c4-47a7-a7a2-163ae0b17dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882783062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.3882783062
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.3025739816
Short name T529
Test name
Test status
Simulation time 75901514 ps
CPU time 1.21 seconds
Started Jul 21 06:42:32 PM PDT 24
Finished Jul 21 06:42:34 PM PDT 24
Peak memory 219004 kb
Host smart-f42fe5d5-c2c4-4234-b719-6753074ff0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025739816 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.3025739816
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.18231365
Short name T886
Test name
Test status
Simulation time 90608418 ps
CPU time 1.15 seconds
Started Jul 21 06:42:35 PM PDT 24
Finished Jul 21 06:42:37 PM PDT 24
Peak memory 217300 kb
Host smart-fce09a0e-30f3-4ed4-95f2-c3a2a8a4833f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18231365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.18231365
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.2985360611
Short name T20
Test name
Test status
Simulation time 23043264 ps
CPU time 1.16 seconds
Started Jul 21 06:41:00 PM PDT 24
Finished Jul 21 06:41:02 PM PDT 24
Peak memory 220032 kb
Host smart-d8b851eb-8676-4ab4-855b-c386280fe684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985360611 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.2985360611
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.1550423005
Short name T370
Test name
Test status
Simulation time 61557920 ps
CPU time 0.93 seconds
Started Jul 21 06:41:01 PM PDT 24
Finished Jul 21 06:41:02 PM PDT 24
Peak memory 206988 kb
Host smart-841ddc21-9e9d-4500-b01c-a668c2ac2e48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550423005 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.1550423005
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.3777458626
Short name T728
Test name
Test status
Simulation time 17417818 ps
CPU time 0.97 seconds
Started Jul 21 06:41:02 PM PDT 24
Finished Jul 21 06:41:03 PM PDT 24
Peak memory 216252 kb
Host smart-7cec3ee1-ff90-45b3-aacd-da9157f4d6ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777458626 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3777458626
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.818788434
Short name T684
Test name
Test status
Simulation time 36436712 ps
CPU time 1.23 seconds
Started Jul 21 06:41:01 PM PDT 24
Finished Jul 21 06:41:03 PM PDT 24
Peak memory 217096 kb
Host smart-2f03f017-04d3-4de8-8abe-5d814b0cc11e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818788434 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_di
sable_auto_req_mode.818788434
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.2341424052
Short name T120
Test name
Test status
Simulation time 20521988 ps
CPU time 1.14 seconds
Started Jul 21 06:41:04 PM PDT 24
Finished Jul 21 06:41:06 PM PDT 24
Peak memory 219976 kb
Host smart-2e6000a9-6ae6-47a2-9985-9a4f0064c22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341424052 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2341424052
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.693615391
Short name T928
Test name
Test status
Simulation time 70717787 ps
CPU time 1.29 seconds
Started Jul 21 06:41:01 PM PDT 24
Finished Jul 21 06:41:03 PM PDT 24
Peak memory 220216 kb
Host smart-95cf31d0-bccb-48bf-b989-0694d12067ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693615391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.693615391
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_smoke.2773119117
Short name T489
Test name
Test status
Simulation time 19164020 ps
CPU time 1 seconds
Started Jul 21 06:41:02 PM PDT 24
Finished Jul 21 06:41:04 PM PDT 24
Peak memory 215504 kb
Host smart-e689748f-611a-4848-ac7d-dc88d3fceb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773119117 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2773119117
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.873608336
Short name T449
Test name
Test status
Simulation time 253476640 ps
CPU time 1.98 seconds
Started Jul 21 06:41:01 PM PDT 24
Finished Jul 21 06:41:04 PM PDT 24
Peak memory 215652 kb
Host smart-2766b947-ddf8-4ae2-9c13-8e59627a7a5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873608336 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.873608336
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.3316663762
Short name T379
Test name
Test status
Simulation time 436996784973 ps
CPU time 1396.74 seconds
Started Jul 21 06:41:02 PM PDT 24
Finished Jul 21 07:04:20 PM PDT 24
Peak memory 234836 kb
Host smart-b90b618f-9d56-4426-8203-baea962a2432
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316663762 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.3316663762
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.471811270
Short name T270
Test name
Test status
Simulation time 33455009 ps
CPU time 1.38 seconds
Started Jul 21 06:42:36 PM PDT 24
Finished Jul 21 06:42:38 PM PDT 24
Peak memory 216016 kb
Host smart-5d91e2c5-9f5e-4a1d-840c-90c597b4644c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471811270 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.471811270
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.480818087
Short name T355
Test name
Test status
Simulation time 69078455 ps
CPU time 1.15 seconds
Started Jul 21 06:42:58 PM PDT 24
Finished Jul 21 06:43:01 PM PDT 24
Peak memory 218884 kb
Host smart-a76da0f4-1d3d-48e5-89ef-6042b51491d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480818087 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.480818087
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.532527407
Short name T435
Test name
Test status
Simulation time 31080324 ps
CPU time 1.22 seconds
Started Jul 21 06:42:37 PM PDT 24
Finished Jul 21 06:42:39 PM PDT 24
Peak memory 220356 kb
Host smart-30cdca2b-70d2-4602-aeb5-f94dad11617f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532527407 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.532527407
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.3058921022
Short name T803
Test name
Test status
Simulation time 264384891 ps
CPU time 1.72 seconds
Started Jul 21 06:42:34 PM PDT 24
Finished Jul 21 06:42:37 PM PDT 24
Peak memory 218992 kb
Host smart-d315a816-7bab-47cc-8115-336b3e8f62e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058921022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.3058921022
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.2520354031
Short name T289
Test name
Test status
Simulation time 30076135 ps
CPU time 1.3 seconds
Started Jul 21 06:42:36 PM PDT 24
Finished Jul 21 06:42:38 PM PDT 24
Peak memory 220300 kb
Host smart-de68681b-567e-47a0-9e9b-79fd9eb099cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520354031 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.2520354031
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.3968112577
Short name T658
Test name
Test status
Simulation time 96742707 ps
CPU time 1.63 seconds
Started Jul 21 06:42:42 PM PDT 24
Finished Jul 21 06:42:45 PM PDT 24
Peak memory 218940 kb
Host smart-af5a79b9-1ca4-44be-91a1-c7ae770f092c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968112577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.3968112577
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.2113639674
Short name T82
Test name
Test status
Simulation time 36201600 ps
CPU time 1.12 seconds
Started Jul 21 06:42:43 PM PDT 24
Finished Jul 21 06:42:45 PM PDT 24
Peak memory 219808 kb
Host smart-1c4b04c4-cb32-4276-8d00-53b9c2203ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113639674 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.2113639674
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.1165882572
Short name T332
Test name
Test status
Simulation time 60114172 ps
CPU time 0.95 seconds
Started Jul 21 06:42:46 PM PDT 24
Finished Jul 21 06:42:49 PM PDT 24
Peak memory 217564 kb
Host smart-8ce2a6b0-c5a5-4264-b3b6-443d9e2b7c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165882572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.1165882572
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.855719489
Short name T138
Test name
Test status
Simulation time 466228618 ps
CPU time 1.29 seconds
Started Jul 21 06:42:37 PM PDT 24
Finished Jul 21 06:42:39 PM PDT 24
Peak memory 216072 kb
Host smart-35d7c416-46e7-486b-afe1-dab13001c91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855719489 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.855719489
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.1854423263
Short name T733
Test name
Test status
Simulation time 65240264 ps
CPU time 1.31 seconds
Started Jul 21 06:42:34 PM PDT 24
Finished Jul 21 06:42:37 PM PDT 24
Peak memory 218640 kb
Host smart-2090d0b4-4dd7-4cb1-91d6-64ce8ae27bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854423263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1854423263
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.2164571316
Short name T907
Test name
Test status
Simulation time 24694440 ps
CPU time 1.2 seconds
Started Jul 21 06:42:43 PM PDT 24
Finished Jul 21 06:42:45 PM PDT 24
Peak memory 216004 kb
Host smart-1d231763-3bc6-4760-a99e-396e757d4ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164571316 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.2164571316
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.3084602616
Short name T691
Test name
Test status
Simulation time 62560916 ps
CPU time 2.18 seconds
Started Jul 21 06:43:00 PM PDT 24
Finished Jul 21 06:43:04 PM PDT 24
Peak memory 220452 kb
Host smart-28811f83-c15a-41a9-9870-e9df5af77672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084602616 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3084602616
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.4018932138
Short name T870
Test name
Test status
Simulation time 22114837 ps
CPU time 1.13 seconds
Started Jul 21 06:42:44 PM PDT 24
Finished Jul 21 06:42:46 PM PDT 24
Peak memory 219976 kb
Host smart-28e3a3cb-7eab-44b3-9ce5-0012be16748c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018932138 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.4018932138
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.2023489914
Short name T950
Test name
Test status
Simulation time 47136942 ps
CPU time 1.01 seconds
Started Jul 21 06:42:41 PM PDT 24
Finished Jul 21 06:42:43 PM PDT 24
Peak memory 217876 kb
Host smart-da9c66ae-9019-4972-b718-7c5f55db2cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023489914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.2023489914
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.1832247763
Short name T487
Test name
Test status
Simulation time 41162337 ps
CPU time 1.1 seconds
Started Jul 21 06:42:34 PM PDT 24
Finished Jul 21 06:42:37 PM PDT 24
Peak memory 219940 kb
Host smart-89e87f7d-7302-46c7-818a-d5a9cae9e6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832247763 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.1832247763
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.48769354
Short name T650
Test name
Test status
Simulation time 140372085 ps
CPU time 2.93 seconds
Started Jul 21 06:43:10 PM PDT 24
Finished Jul 21 06:43:13 PM PDT 24
Peak memory 220440 kb
Host smart-20aa3e8a-26a0-4516-9e9b-830b601a83c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48769354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.48769354
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.503171954
Short name T710
Test name
Test status
Simulation time 40537783 ps
CPU time 1.4 seconds
Started Jul 21 06:42:50 PM PDT 24
Finished Jul 21 06:42:53 PM PDT 24
Peak memory 218784 kb
Host smart-df74391b-8b6b-420a-a4dc-a1361a253bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503171954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.503171954
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.2791740364
Short name T171
Test name
Test status
Simulation time 29042563 ps
CPU time 1.25 seconds
Started Jul 21 06:42:41 PM PDT 24
Finished Jul 21 06:42:43 PM PDT 24
Peak memory 219772 kb
Host smart-f9a2e8d6-683f-40b4-9534-b71f64618ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791740364 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.2791740364
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.311043825
Short name T817
Test name
Test status
Simulation time 80686958 ps
CPU time 1.42 seconds
Started Jul 21 06:42:47 PM PDT 24
Finished Jul 21 06:42:50 PM PDT 24
Peak memory 219156 kb
Host smart-5f67249a-b143-4165-8965-2798527efd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311043825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.311043825
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.3173921224
Short name T28
Test name
Test status
Simulation time 91841858 ps
CPU time 1.33 seconds
Started Jul 21 06:41:00 PM PDT 24
Finished Jul 21 06:41:02 PM PDT 24
Peak memory 216020 kb
Host smart-7daa1699-ee81-42ae-bc4e-1636f2cd1361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173921224 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3173921224
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.3324303562
Short name T665
Test name
Test status
Simulation time 15842265 ps
CPU time 0.9 seconds
Started Jul 21 06:41:12 PM PDT 24
Finished Jul 21 06:41:13 PM PDT 24
Peak memory 207008 kb
Host smart-20beb76b-e3d0-4716-8487-ace7afc7f9b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324303562 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3324303562
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.3190839389
Short name T209
Test name
Test status
Simulation time 11905038 ps
CPU time 0.91 seconds
Started Jul 21 06:41:01 PM PDT 24
Finished Jul 21 06:41:03 PM PDT 24
Peak memory 216600 kb
Host smart-35417edb-a104-4809-905f-3c5146fbdf59
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190839389 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.3190839389
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2289996230
Short name T567
Test name
Test status
Simulation time 35635750 ps
CPU time 1.37 seconds
Started Jul 21 06:41:04 PM PDT 24
Finished Jul 21 06:41:06 PM PDT 24
Peak memory 216984 kb
Host smart-32f0db66-29ff-4b58-ad3d-abc0d476fc71
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289996230 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2289996230
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.1470784455
Short name T7
Test name
Test status
Simulation time 41028983 ps
CPU time 0.89 seconds
Started Jul 21 06:41:01 PM PDT 24
Finished Jul 21 06:41:02 PM PDT 24
Peak memory 218796 kb
Host smart-9cd5b971-6b39-4210-949a-8dfe7aa37731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470784455 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1470784455
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.2932053531
Short name T371
Test name
Test status
Simulation time 90547686 ps
CPU time 1.63 seconds
Started Jul 21 06:41:01 PM PDT 24
Finished Jul 21 06:41:03 PM PDT 24
Peak memory 219264 kb
Host smart-628ff0c5-2e95-4700-b51f-981999151eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932053531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2932053531
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.821541850
Short name T57
Test name
Test status
Simulation time 25292656 ps
CPU time 1.03 seconds
Started Jul 21 06:41:04 PM PDT 24
Finished Jul 21 06:41:06 PM PDT 24
Peak memory 215848 kb
Host smart-0701dcb6-a240-40fb-8b62-50b43119f770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821541850 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.821541850
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.3034520166
Short name T417
Test name
Test status
Simulation time 43722444 ps
CPU time 0.93 seconds
Started Jul 21 06:41:04 PM PDT 24
Finished Jul 21 06:41:06 PM PDT 24
Peak memory 215520 kb
Host smart-debaa49b-02f3-4e85-b303-7ff681b7655b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034520166 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.3034520166
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.2343923589
Short name T348
Test name
Test status
Simulation time 298179856 ps
CPU time 1.77 seconds
Started Jul 21 06:41:02 PM PDT 24
Finished Jul 21 06:41:04 PM PDT 24
Peak memory 217380 kb
Host smart-d6e70bf6-99a9-4dc4-9b24-d29f066cd14d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343923589 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2343923589
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.175965341
Short name T926
Test name
Test status
Simulation time 30675312868 ps
CPU time 790.27 seconds
Started Jul 21 06:41:03 PM PDT 24
Finished Jul 21 06:54:14 PM PDT 24
Peak memory 223932 kb
Host smart-23e37626-9598-4f1f-a1ec-9c00a0bf3003
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175965341 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.175965341
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.3919165145
Short name T838
Test name
Test status
Simulation time 36304326 ps
CPU time 1.05 seconds
Started Jul 21 06:42:45 PM PDT 24
Finished Jul 21 06:42:49 PM PDT 24
Peak memory 218952 kb
Host smart-a30aa04c-8de9-4aae-8b44-aa2db0675be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919165145 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.3919165145
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.1807801878
Short name T804
Test name
Test status
Simulation time 36453437 ps
CPU time 1.36 seconds
Started Jul 21 06:42:34 PM PDT 24
Finished Jul 21 06:42:36 PM PDT 24
Peak memory 218856 kb
Host smart-6df9332b-82ac-4ebf-8b60-a81124b3e869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807801878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1807801878
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.18278888
Short name T882
Test name
Test status
Simulation time 77222946 ps
CPU time 1.21 seconds
Started Jul 21 06:42:49 PM PDT 24
Finished Jul 21 06:42:52 PM PDT 24
Peak memory 220104 kb
Host smart-f92097e8-edf1-4eab-a76a-2f7531c9db3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18278888 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.18278888
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.1403052624
Short name T407
Test name
Test status
Simulation time 39600468 ps
CPU time 1.81 seconds
Started Jul 21 06:42:37 PM PDT 24
Finished Jul 21 06:42:40 PM PDT 24
Peak memory 219096 kb
Host smart-bff34ad9-3bfe-4b7c-abf1-d24b2453e3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403052624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1403052624
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.2016223492
Short name T426
Test name
Test status
Simulation time 28803763 ps
CPU time 1.26 seconds
Started Jul 21 06:42:36 PM PDT 24
Finished Jul 21 06:42:39 PM PDT 24
Peak memory 218804 kb
Host smart-d344de18-295c-462e-96d0-990b3a6f0eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016223492 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.2016223492
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.457210391
Short name T586
Test name
Test status
Simulation time 34459748 ps
CPU time 1.34 seconds
Started Jul 21 06:42:33 PM PDT 24
Finished Jul 21 06:42:36 PM PDT 24
Peak memory 217568 kb
Host smart-7cdd2869-98be-429e-af11-33c775b55cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457210391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.457210391
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.4196596395
Short name T690
Test name
Test status
Simulation time 47247583 ps
CPU time 1.19 seconds
Started Jul 21 06:42:41 PM PDT 24
Finished Jul 21 06:42:43 PM PDT 24
Peak memory 218716 kb
Host smart-890b6f4d-71c1-4465-86ec-4e0c6417e52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196596395 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.4196596395
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/164.edn_alert.3109875949
Short name T139
Test name
Test status
Simulation time 47633355 ps
CPU time 1.24 seconds
Started Jul 21 06:42:44 PM PDT 24
Finished Jul 21 06:42:46 PM PDT 24
Peak memory 219908 kb
Host smart-89b8a71c-0516-4cc7-9158-a3cc971cc8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109875949 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.3109875949
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.1741936925
Short name T84
Test name
Test status
Simulation time 57864219 ps
CPU time 1.75 seconds
Started Jul 21 06:42:39 PM PDT 24
Finished Jul 21 06:42:42 PM PDT 24
Peak memory 218776 kb
Host smart-c0407b24-8023-4cb4-a414-717dcd576f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741936925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.1741936925
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.3724194601
Short name T624
Test name
Test status
Simulation time 44389999 ps
CPU time 1.09 seconds
Started Jul 21 06:42:34 PM PDT 24
Finished Jul 21 06:42:36 PM PDT 24
Peak memory 218668 kb
Host smart-5dc4c7ac-7491-49f4-b76f-abe37c9b7479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724194601 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.3724194601
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.846470135
Short name T924
Test name
Test status
Simulation time 30673825 ps
CPU time 0.98 seconds
Started Jul 21 06:42:39 PM PDT 24
Finished Jul 21 06:42:41 PM PDT 24
Peak memory 217576 kb
Host smart-816f90bf-f450-4dcc-80c6-fd85ba1262e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846470135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.846470135
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.1840520454
Short name T683
Test name
Test status
Simulation time 74956732 ps
CPU time 1.14 seconds
Started Jul 21 06:42:45 PM PDT 24
Finished Jul 21 06:42:48 PM PDT 24
Peak memory 220580 kb
Host smart-d43d5fe0-dca3-4a21-b297-45509581c6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840520454 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.1840520454
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.431096081
Short name T320
Test name
Test status
Simulation time 212560550 ps
CPU time 1.29 seconds
Started Jul 21 06:42:46 PM PDT 24
Finished Jul 21 06:42:50 PM PDT 24
Peak memory 219308 kb
Host smart-45738e4b-0003-4f13-9508-b2d53f96e803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431096081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.431096081
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.1720710488
Short name T217
Test name
Test status
Simulation time 84192620 ps
CPU time 1.16 seconds
Started Jul 21 06:42:57 PM PDT 24
Finished Jul 21 06:42:59 PM PDT 24
Peak memory 222416 kb
Host smart-a5a6e987-55cf-41a3-ba10-63a0973cc5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720710488 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.1720710488
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.1396523835
Short name T991
Test name
Test status
Simulation time 164146264 ps
CPU time 1.05 seconds
Started Jul 21 06:42:39 PM PDT 24
Finished Jul 21 06:42:41 PM PDT 24
Peak memory 217556 kb
Host smart-40de3521-3be2-4f98-ad1b-d8c873b00750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396523835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1396523835
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.2105681511
Short name T450
Test name
Test status
Simulation time 24876374 ps
CPU time 1.14 seconds
Started Jul 21 06:42:34 PM PDT 24
Finished Jul 21 06:42:36 PM PDT 24
Peak memory 220220 kb
Host smart-bd213f66-8905-44e7-aecd-ccc2d4059b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105681511 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.2105681511
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.1709553440
Short name T633
Test name
Test status
Simulation time 90392945 ps
CPU time 1.25 seconds
Started Jul 21 06:42:40 PM PDT 24
Finished Jul 21 06:42:42 PM PDT 24
Peak memory 219092 kb
Host smart-412c9323-65ae-435a-85e5-0f0e7fab9219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709553440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1709553440
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.2560117581
Short name T630
Test name
Test status
Simulation time 33412240 ps
CPU time 1.26 seconds
Started Jul 21 06:42:35 PM PDT 24
Finished Jul 21 06:42:37 PM PDT 24
Peak memory 217464 kb
Host smart-d8e5d5fd-08fa-4af1-9833-2e738401ec21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560117581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.2560117581
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.425381833
Short name T648
Test name
Test status
Simulation time 103069852 ps
CPU time 1.28 seconds
Started Jul 21 06:41:13 PM PDT 24
Finished Jul 21 06:41:16 PM PDT 24
Peak memory 216044 kb
Host smart-25a8d75e-f497-4b99-b8be-d01b27b416af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425381833 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.425381833
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.2213823903
Short name T880
Test name
Test status
Simulation time 22340403 ps
CPU time 0.99 seconds
Started Jul 21 06:41:14 PM PDT 24
Finished Jul 21 06:41:17 PM PDT 24
Peak memory 207096 kb
Host smart-19cd7441-08c8-4538-bf50-11e8556b661a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213823903 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2213823903
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.3871721422
Short name T428
Test name
Test status
Simulation time 30843799 ps
CPU time 0.86 seconds
Started Jul 21 06:41:15 PM PDT 24
Finished Jul 21 06:41:18 PM PDT 24
Peak memory 216444 kb
Host smart-7fb5eb9a-d64e-4aff-ac46-45e007d8a7bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871721422 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3871721422
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.3358208401
Short name T780
Test name
Test status
Simulation time 58121168 ps
CPU time 1.05 seconds
Started Jul 21 06:41:14 PM PDT 24
Finished Jul 21 06:41:16 PM PDT 24
Peak memory 217096 kb
Host smart-897a5b3b-92d7-491f-8cf1-2120431526da
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358208401 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.3358208401
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_genbits.3064817541
Short name T662
Test name
Test status
Simulation time 52578813 ps
CPU time 1.18 seconds
Started Jul 21 06:41:15 PM PDT 24
Finished Jul 21 06:41:18 PM PDT 24
Peak memory 217544 kb
Host smart-59438bf4-146b-4850-aa1b-d81670629c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064817541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3064817541
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.2831757690
Short name T1
Test name
Test status
Simulation time 41398556 ps
CPU time 1.02 seconds
Started Jul 21 06:41:13 PM PDT 24
Finished Jul 21 06:41:16 PM PDT 24
Peak memory 224288 kb
Host smart-2925a9cf-2dba-4577-ac72-1c4d72641ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831757690 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.2831757690
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.3930063813
Short name T868
Test name
Test status
Simulation time 78326200 ps
CPU time 0.9 seconds
Started Jul 21 06:41:13 PM PDT 24
Finished Jul 21 06:41:15 PM PDT 24
Peak memory 215532 kb
Host smart-f1fd8932-15d9-4c9f-a9d8-558f93c080f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930063813 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.3930063813
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.61120640
Short name T550
Test name
Test status
Simulation time 189427308 ps
CPU time 4.08 seconds
Started Jul 21 06:41:14 PM PDT 24
Finished Jul 21 06:41:20 PM PDT 24
Peak memory 217204 kb
Host smart-c25b483e-4d37-4083-8217-5c09f1a3d23d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61120640 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.61120640
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.662885995
Short name T231
Test name
Test status
Simulation time 84657404219 ps
CPU time 356.21 seconds
Started Jul 21 06:41:13 PM PDT 24
Finished Jul 21 06:47:10 PM PDT 24
Peak memory 218480 kb
Host smart-fefd57f0-d9fa-462d-addc-2f5de22ca80c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662885995 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.662885995
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.1712157754
Short name T958
Test name
Test status
Simulation time 103966450 ps
CPU time 1.17 seconds
Started Jul 21 06:42:39 PM PDT 24
Finished Jul 21 06:42:41 PM PDT 24
Peak memory 219168 kb
Host smart-2ec2e7c0-c2e7-4033-bd8a-dae9724c9598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712157754 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.1712157754
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.2115729303
Short name T419
Test name
Test status
Simulation time 35592983 ps
CPU time 1.51 seconds
Started Jul 21 06:42:39 PM PDT 24
Finished Jul 21 06:42:41 PM PDT 24
Peak memory 218620 kb
Host smart-db2c3283-309c-446e-b9db-c131eb4b8f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115729303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.2115729303
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.2270838897
Short name T598
Test name
Test status
Simulation time 51766031 ps
CPU time 1.25 seconds
Started Jul 21 06:42:57 PM PDT 24
Finished Jul 21 06:42:59 PM PDT 24
Peak memory 220396 kb
Host smart-197ca85d-df3b-49f1-af2e-f40572da3b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270838897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.2270838897
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.1315687326
Short name T865
Test name
Test status
Simulation time 68939006 ps
CPU time 1.1 seconds
Started Jul 21 06:42:34 PM PDT 24
Finished Jul 21 06:42:36 PM PDT 24
Peak memory 220036 kb
Host smart-96d46c37-5f97-48a5-a04c-fb9df779f334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315687326 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.1315687326
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.452150210
Short name T501
Test name
Test status
Simulation time 89619820 ps
CPU time 1.49 seconds
Started Jul 21 06:42:42 PM PDT 24
Finished Jul 21 06:42:44 PM PDT 24
Peak memory 219220 kb
Host smart-4d071aa4-7135-4613-8c96-b96066a80b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452150210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.452150210
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.648369375
Short name T77
Test name
Test status
Simulation time 45627503 ps
CPU time 1.21 seconds
Started Jul 21 06:42:39 PM PDT 24
Finished Jul 21 06:42:41 PM PDT 24
Peak memory 220344 kb
Host smart-0e6bf39d-9c00-43ba-8b49-356b6c829a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648369375 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.648369375
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.1487292417
Short name T535
Test name
Test status
Simulation time 37454492 ps
CPU time 1.54 seconds
Started Jul 21 06:42:34 PM PDT 24
Finished Jul 21 06:42:37 PM PDT 24
Peak memory 218984 kb
Host smart-2460f358-9bd8-4e00-abfe-944fd487c70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487292417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.1487292417
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.617948725
Short name T677
Test name
Test status
Simulation time 70931764 ps
CPU time 1.06 seconds
Started Jul 21 06:42:44 PM PDT 24
Finished Jul 21 06:42:47 PM PDT 24
Peak memory 220216 kb
Host smart-1678c189-35f7-42a2-9189-031680e62d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617948725 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.617948725
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.3287666117
Short name T652
Test name
Test status
Simulation time 60894142 ps
CPU time 1.53 seconds
Started Jul 21 06:42:48 PM PDT 24
Finished Jul 21 06:42:52 PM PDT 24
Peak memory 218824 kb
Host smart-df393f8e-d7ad-47a8-996d-0b51f45d300a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287666117 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3287666117
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.1810999606
Short name T782
Test name
Test status
Simulation time 33383423 ps
CPU time 1.17 seconds
Started Jul 21 06:42:45 PM PDT 24
Finished Jul 21 06:42:49 PM PDT 24
Peak memory 220076 kb
Host smart-4f3572b8-9076-4510-a7b4-1db3191d3e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810999606 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.1810999606
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.343526056
Short name T27
Test name
Test status
Simulation time 65749954 ps
CPU time 1.63 seconds
Started Jul 21 06:42:52 PM PDT 24
Finished Jul 21 06:42:55 PM PDT 24
Peak memory 219024 kb
Host smart-0cb88e6a-6359-45dc-9b8f-11d41c0bf26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343526056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.343526056
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.942854687
Short name T408
Test name
Test status
Simulation time 23284563 ps
CPU time 1.15 seconds
Started Jul 21 06:42:41 PM PDT 24
Finished Jul 21 06:42:43 PM PDT 24
Peak memory 219964 kb
Host smart-f8201b1c-bd1d-40dc-9c0c-ee1c8fa3fec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942854687 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.942854687
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.2362674938
Short name T453
Test name
Test status
Simulation time 37186060 ps
CPU time 1.44 seconds
Started Jul 21 06:42:49 PM PDT 24
Finished Jul 21 06:42:52 PM PDT 24
Peak memory 217624 kb
Host smart-b029101c-c98b-4518-9bfe-6cfe8ae1bfca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362674938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2362674938
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.399763770
Short name T45
Test name
Test status
Simulation time 92634644 ps
CPU time 1.18 seconds
Started Jul 21 06:42:47 PM PDT 24
Finished Jul 21 06:42:50 PM PDT 24
Peak memory 219896 kb
Host smart-7a7e18d0-cb60-439a-b32e-17c30d8edc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399763770 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.399763770
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.1058512804
Short name T515
Test name
Test status
Simulation time 48250731 ps
CPU time 1.14 seconds
Started Jul 21 06:42:44 PM PDT 24
Finished Jul 21 06:42:47 PM PDT 24
Peak memory 217420 kb
Host smart-d22def9c-5107-4c47-83b4-ac1197a5ada9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058512804 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.1058512804
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.1316041299
Short name T711
Test name
Test status
Simulation time 56726949 ps
CPU time 1.37 seconds
Started Jul 21 06:42:49 PM PDT 24
Finished Jul 21 06:42:52 PM PDT 24
Peak memory 216064 kb
Host smart-e328ab8b-da9e-4841-9357-754dbf12978e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316041299 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.1316041299
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.751179875
Short name T313
Test name
Test status
Simulation time 62562401 ps
CPU time 1.61 seconds
Started Jul 21 06:42:48 PM PDT 24
Finished Jul 21 06:42:51 PM PDT 24
Peak memory 218684 kb
Host smart-07fa7c0b-3c2b-4585-8771-3cb4c36a2159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751179875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.751179875
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.3396146313
Short name T103
Test name
Test status
Simulation time 40784908 ps
CPU time 1.17 seconds
Started Jul 21 06:42:58 PM PDT 24
Finished Jul 21 06:43:01 PM PDT 24
Peak memory 219740 kb
Host smart-e0467dbe-adb3-4a74-8b5e-3b4589c8e4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396146313 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.3396146313
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.2246819340
Short name T465
Test name
Test status
Simulation time 95965832 ps
CPU time 1.16 seconds
Started Jul 21 06:42:52 PM PDT 24
Finished Jul 21 06:42:55 PM PDT 24
Peak memory 219656 kb
Host smart-3ebe7620-1d51-470f-9b28-da2b1dd9b439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246819340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.2246819340
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.3287040169
Short name T576
Test name
Test status
Simulation time 93266563 ps
CPU time 1.25 seconds
Started Jul 21 06:41:15 PM PDT 24
Finished Jul 21 06:41:18 PM PDT 24
Peak memory 221056 kb
Host smart-91418888-3112-49f0-b32c-b929f0d70649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287040169 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.3287040169
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_disable.754755069
Short name T158
Test name
Test status
Simulation time 13664827 ps
CPU time 1 seconds
Started Jul 21 06:41:14 PM PDT 24
Finished Jul 21 06:41:16 PM PDT 24
Peak memory 215800 kb
Host smart-98d238e3-ebce-40ed-b770-d270bebfa481
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754755069 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.754755069
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.3796152370
Short name T719
Test name
Test status
Simulation time 77774225 ps
CPU time 1.09 seconds
Started Jul 21 06:41:12 PM PDT 24
Finished Jul 21 06:41:13 PM PDT 24
Peak memory 217012 kb
Host smart-e46bb12d-1325-4a6f-a579-b5392f6af602
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796152370 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.3796152370
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.3893324274
Short name T172
Test name
Test status
Simulation time 18246019 ps
CPU time 1.08 seconds
Started Jul 21 06:41:13 PM PDT 24
Finished Jul 21 06:41:16 PM PDT 24
Peak memory 218764 kb
Host smart-c3c2fefd-72e5-4148-ad32-1583015f136a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893324274 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.3893324274
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.876211468
Short name T507
Test name
Test status
Simulation time 143231530 ps
CPU time 1.2 seconds
Started Jul 21 06:41:14 PM PDT 24
Finished Jul 21 06:41:16 PM PDT 24
Peak memory 220428 kb
Host smart-a0341638-ce25-4e12-bd52-b2240bfd294b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876211468 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.876211468
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.1830151276
Short name T830
Test name
Test status
Simulation time 99158257 ps
CPU time 0.82 seconds
Started Jul 21 06:41:14 PM PDT 24
Finished Jul 21 06:41:16 PM PDT 24
Peak memory 215572 kb
Host smart-6f928ab9-cf1a-4bd0-85e9-70f5b8caa0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830151276 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1830151276
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.1732447055
Short name T770
Test name
Test status
Simulation time 17920232 ps
CPU time 1.05 seconds
Started Jul 21 06:41:11 PM PDT 24
Finished Jul 21 06:41:13 PM PDT 24
Peak memory 215568 kb
Host smart-5d9694cb-8817-494a-a677-bd4fea224c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732447055 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.1732447055
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1968328497
Short name T884
Test name
Test status
Simulation time 375101556 ps
CPU time 3.73 seconds
Started Jul 21 06:41:14 PM PDT 24
Finished Jul 21 06:41:19 PM PDT 24
Peak memory 217400 kb
Host smart-81d20a97-78ae-4b2c-9418-6519ff32f3d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968328497 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1968328497
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1932537349
Short name T570
Test name
Test status
Simulation time 8972448600 ps
CPU time 206.86 seconds
Started Jul 21 06:41:15 PM PDT 24
Finished Jul 21 06:44:44 PM PDT 24
Peak memory 222116 kb
Host smart-c3cd8e63-0ce7-40c9-aa84-42d87bf49151
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932537349 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1932537349
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.56605132
Short name T124
Test name
Test status
Simulation time 441615044 ps
CPU time 1.76 seconds
Started Jul 21 06:43:01 PM PDT 24
Finished Jul 21 06:43:04 PM PDT 24
Peak memory 218780 kb
Host smart-90e15248-0210-49fc-b0e3-47d8475e43bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56605132 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.56605132
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.1820074880
Short name T573
Test name
Test status
Simulation time 80609240 ps
CPU time 1.43 seconds
Started Jul 21 06:42:38 PM PDT 24
Finished Jul 21 06:42:40 PM PDT 24
Peak memory 219100 kb
Host smart-0186a7e1-8154-4218-8c7c-3f5745111a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820074880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.1820074880
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.1380764485
Short name T927
Test name
Test status
Simulation time 22733153 ps
CPU time 1.19 seconds
Started Jul 21 06:42:44 PM PDT 24
Finished Jul 21 06:42:46 PM PDT 24
Peak memory 221040 kb
Host smart-90611596-90cb-49bb-a568-851fe673866c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380764485 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.1380764485
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.3772656353
Short name T443
Test name
Test status
Simulation time 153987901 ps
CPU time 2.44 seconds
Started Jul 21 06:42:57 PM PDT 24
Finished Jul 21 06:43:01 PM PDT 24
Peak memory 220668 kb
Host smart-bdba738c-1a1e-4456-94e3-35c52f1ba717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772656353 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3772656353
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.2897931822
Short name T753
Test name
Test status
Simulation time 52077581 ps
CPU time 1.17 seconds
Started Jul 21 06:42:41 PM PDT 24
Finished Jul 21 06:42:43 PM PDT 24
Peak memory 218960 kb
Host smart-71dde623-a8db-496b-9cb1-5767403241ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897931822 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.2897931822
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.68057420
Short name T326
Test name
Test status
Simulation time 222702769 ps
CPU time 3.04 seconds
Started Jul 21 06:42:43 PM PDT 24
Finished Jul 21 06:42:47 PM PDT 24
Peak memory 220324 kb
Host smart-dcad4590-8132-40fd-bf44-90f7cbd3529e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68057420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.68057420
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.3337318429
Short name T457
Test name
Test status
Simulation time 128520705 ps
CPU time 1.16 seconds
Started Jul 21 06:42:47 PM PDT 24
Finished Jul 21 06:42:50 PM PDT 24
Peak memory 219444 kb
Host smart-95cd964e-3992-4316-aefa-666137c3c577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337318429 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.3337318429
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.2071865731
Short name T454
Test name
Test status
Simulation time 71116360 ps
CPU time 2.45 seconds
Started Jul 21 06:43:01 PM PDT 24
Finished Jul 21 06:43:04 PM PDT 24
Peak memory 220360 kb
Host smart-d7092bf3-229e-406c-b9ea-4bf026072180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071865731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.2071865731
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.2625203922
Short name T542
Test name
Test status
Simulation time 41921160 ps
CPU time 1.14 seconds
Started Jul 21 06:42:46 PM PDT 24
Finished Jul 21 06:42:49 PM PDT 24
Peak memory 218892 kb
Host smart-274c0b43-e904-41a3-93cb-d6b558764b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625203922 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.2625203922
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.464914311
Short name T794
Test name
Test status
Simulation time 37893812 ps
CPU time 1.61 seconds
Started Jul 21 06:42:43 PM PDT 24
Finished Jul 21 06:42:46 PM PDT 24
Peak memory 218840 kb
Host smart-674d68ea-3c8b-48df-a4eb-079c8a38f044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464914311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.464914311
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.193777443
Short name T100
Test name
Test status
Simulation time 94413665 ps
CPU time 1.12 seconds
Started Jul 21 06:42:59 PM PDT 24
Finished Jul 21 06:43:01 PM PDT 24
Peak memory 218664 kb
Host smart-fa6ca981-6675-41e5-b919-9a83932746b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193777443 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.193777443
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.1113271757
Short name T747
Test name
Test status
Simulation time 167847469 ps
CPU time 1.19 seconds
Started Jul 21 06:42:56 PM PDT 24
Finished Jul 21 06:42:58 PM PDT 24
Peak memory 217644 kb
Host smart-a093315a-54f9-4857-83e3-d9bf56dc82b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113271757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.1113271757
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.2122892203
Short name T414
Test name
Test status
Simulation time 26224828 ps
CPU time 1.27 seconds
Started Jul 21 06:42:59 PM PDT 24
Finished Jul 21 06:43:02 PM PDT 24
Peak memory 218980 kb
Host smart-adbc7fbb-b684-420a-a6a0-ae69b90779a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122892203 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.2122892203
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.1363875760
Short name T935
Test name
Test status
Simulation time 201401379 ps
CPU time 2.49 seconds
Started Jul 21 06:43:02 PM PDT 24
Finished Jul 21 06:43:06 PM PDT 24
Peak memory 220332 kb
Host smart-ce260eb8-173a-46ee-a33d-91a568a45980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363875760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.1363875760
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.3334949201
Short name T828
Test name
Test status
Simulation time 24418719 ps
CPU time 1.21 seconds
Started Jul 21 06:42:49 PM PDT 24
Finished Jul 21 06:42:52 PM PDT 24
Peak memory 220832 kb
Host smart-702a1079-aa43-46e9-beca-6b5e33e8aec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334949201 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.3334949201
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/188.edn_alert.1350207175
Short name T661
Test name
Test status
Simulation time 26312301 ps
CPU time 1.14 seconds
Started Jul 21 06:42:45 PM PDT 24
Finished Jul 21 06:42:49 PM PDT 24
Peak memory 218780 kb
Host smart-f335e71d-7d0f-4db6-8ac6-cfb2acb3be69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350207175 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.1350207175
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.516661638
Short name T700
Test name
Test status
Simulation time 72696359 ps
CPU time 1.57 seconds
Started Jul 21 06:42:47 PM PDT 24
Finished Jul 21 06:42:50 PM PDT 24
Peak memory 218808 kb
Host smart-1eaadb18-0a79-4af6-aaeb-64ac631668ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516661638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.516661638
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.3625043138
Short name T91
Test name
Test status
Simulation time 102483487 ps
CPU time 1.27 seconds
Started Jul 21 06:42:59 PM PDT 24
Finished Jul 21 06:43:02 PM PDT 24
Peak memory 216036 kb
Host smart-29cc71a7-5a12-481b-a23a-83e268d2b51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625043138 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.3625043138
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.442783761
Short name T76
Test name
Test status
Simulation time 40793159 ps
CPU time 1.47 seconds
Started Jul 21 06:42:45 PM PDT 24
Finished Jul 21 06:42:49 PM PDT 24
Peak memory 218808 kb
Host smart-3c8eff49-9cdc-4462-874c-3a00f1d4e30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442783761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.442783761
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.294055269
Short name T182
Test name
Test status
Simulation time 68469131 ps
CPU time 1.35 seconds
Started Jul 21 06:41:14 PM PDT 24
Finished Jul 21 06:41:16 PM PDT 24
Peak memory 221616 kb
Host smart-1c545cbf-90cc-4e4c-8a87-239e22506534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294055269 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.294055269
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.4125321299
Short name T352
Test name
Test status
Simulation time 36509876 ps
CPU time 0.89 seconds
Started Jul 21 06:41:12 PM PDT 24
Finished Jul 21 06:41:14 PM PDT 24
Peak memory 206988 kb
Host smart-d51a95e7-9890-4eca-b28d-9880a08d0fb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125321299 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.4125321299
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.65291078
Short name T974
Test name
Test status
Simulation time 27298761 ps
CPU time 0.82 seconds
Started Jul 21 06:41:12 PM PDT 24
Finished Jul 21 06:41:13 PM PDT 24
Peak memory 216112 kb
Host smart-2168e239-47c0-48f7-89e4-198ff576d0de
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65291078 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.65291078
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.2763581153
Short name T538
Test name
Test status
Simulation time 40041311 ps
CPU time 1.13 seconds
Started Jul 21 06:41:14 PM PDT 24
Finished Jul 21 06:41:16 PM PDT 24
Peak memory 218656 kb
Host smart-cf9aefca-eced-41ec-8d50-a36a3687a5fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763581153 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.2763581153
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.2096202560
Short name T128
Test name
Test status
Simulation time 76477520 ps
CPU time 0.95 seconds
Started Jul 21 06:41:14 PM PDT 24
Finished Jul 21 06:41:16 PM PDT 24
Peak memory 220056 kb
Host smart-6053f767-7b58-426b-9230-0c0a7abd94a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096202560 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.2096202560
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.2920111810
Short name T692
Test name
Test status
Simulation time 74948162 ps
CPU time 1.85 seconds
Started Jul 21 06:41:13 PM PDT 24
Finished Jul 21 06:41:16 PM PDT 24
Peak memory 220420 kb
Host smart-61d64706-96ce-494c-989d-cdc547186b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920111810 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.2920111810
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3267160556
Short name T643
Test name
Test status
Simulation time 48775719 ps
CPU time 0.91 seconds
Started Jul 21 06:41:11 PM PDT 24
Finished Jul 21 06:41:12 PM PDT 24
Peak memory 215532 kb
Host smart-31416b1c-faa4-4585-b4cb-87fead04dfcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267160556 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3267160556
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.2253963022
Short name T696
Test name
Test status
Simulation time 20353433 ps
CPU time 0.92 seconds
Started Jul 21 06:41:13 PM PDT 24
Finished Jul 21 06:41:15 PM PDT 24
Peak memory 215564 kb
Host smart-c887e0ec-0991-43f5-affe-7d9171edb98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253963022 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.2253963022
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.4214724561
Short name T673
Test name
Test status
Simulation time 301743421 ps
CPU time 5.87 seconds
Started Jul 21 06:41:12 PM PDT 24
Finished Jul 21 06:41:19 PM PDT 24
Peak memory 217592 kb
Host smart-8ccfcb4a-e0e8-4a55-b764-946df15abbfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214724561 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.4214724561
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.1252880730
Short name T227
Test name
Test status
Simulation time 75815151813 ps
CPU time 883.76 seconds
Started Jul 21 06:41:11 PM PDT 24
Finished Jul 21 06:55:55 PM PDT 24
Peak memory 221552 kb
Host smart-d6d146e5-cf36-4d65-ab17-6f5f1b82ab59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252880730 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.1252880730
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.3146152792
Short name T815
Test name
Test status
Simulation time 114920549 ps
CPU time 1.14 seconds
Started Jul 21 06:43:01 PM PDT 24
Finished Jul 21 06:43:03 PM PDT 24
Peak memory 220060 kb
Host smart-fd7f8f0a-131d-4d34-8e40-0a43d1726ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146152792 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.3146152792
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.965375142
Short name T657
Test name
Test status
Simulation time 84981077 ps
CPU time 1.33 seconds
Started Jul 21 06:42:49 PM PDT 24
Finished Jul 21 06:42:52 PM PDT 24
Peak memory 219076 kb
Host smart-84d37876-5a1a-465a-9c7b-840b4bfc17fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965375142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.965375142
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.86602911
Short name T273
Test name
Test status
Simulation time 46386604 ps
CPU time 1.29 seconds
Started Jul 21 06:42:59 PM PDT 24
Finished Jul 21 06:43:02 PM PDT 24
Peak memory 219744 kb
Host smart-9f39b782-18e6-4868-96c1-c882cefc3038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86602911 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.86602911
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.3211495568
Short name T61
Test name
Test status
Simulation time 124910688 ps
CPU time 1.06 seconds
Started Jul 21 06:42:52 PM PDT 24
Finished Jul 21 06:42:54 PM PDT 24
Peak memory 217524 kb
Host smart-04f25806-bd0f-44dd-9218-c1472d5a110e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211495568 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.3211495568
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.545645577
Short name T517
Test name
Test status
Simulation time 64864980 ps
CPU time 1.19 seconds
Started Jul 21 06:43:06 PM PDT 24
Finished Jul 21 06:43:08 PM PDT 24
Peak memory 219976 kb
Host smart-5c599019-7bc1-428b-a60b-4d56d939ef54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545645577 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.545645577
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.114143170
Short name T40
Test name
Test status
Simulation time 166578532 ps
CPU time 1.2 seconds
Started Jul 21 06:42:50 PM PDT 24
Finished Jul 21 06:42:53 PM PDT 24
Peak memory 217756 kb
Host smart-b643d215-3747-475d-aadc-3b318df2e25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114143170 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.114143170
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.3040148286
Short name T181
Test name
Test status
Simulation time 127805685 ps
CPU time 1.26 seconds
Started Jul 21 06:43:06 PM PDT 24
Finished Jul 21 06:43:08 PM PDT 24
Peak memory 220120 kb
Host smart-43c4efff-1717-4316-a4a7-9a29819c6d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040148286 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.3040148286
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.1618019603
Short name T786
Test name
Test status
Simulation time 62444127 ps
CPU time 2.3 seconds
Started Jul 21 06:42:46 PM PDT 24
Finished Jul 21 06:42:51 PM PDT 24
Peak memory 215744 kb
Host smart-c9fb23e6-20d1-4aea-a0e8-08659a67908b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618019603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.1618019603
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.2622106135
Short name T191
Test name
Test status
Simulation time 40830539 ps
CPU time 1.15 seconds
Started Jul 21 06:42:49 PM PDT 24
Finished Jul 21 06:42:52 PM PDT 24
Peak memory 220536 kb
Host smart-e6972c0f-d974-4744-b1ef-64f349a01dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622106135 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.2622106135
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.2911270500
Short name T308
Test name
Test status
Simulation time 35097364 ps
CPU time 1.49 seconds
Started Jul 21 06:43:04 PM PDT 24
Finished Jul 21 06:43:06 PM PDT 24
Peak memory 218992 kb
Host smart-70dee868-406e-47e2-8627-6cfff7d89198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911270500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2911270500
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.4186779100
Short name T294
Test name
Test status
Simulation time 93450499 ps
CPU time 1.07 seconds
Started Jul 21 06:43:02 PM PDT 24
Finished Jul 21 06:43:04 PM PDT 24
Peak memory 216004 kb
Host smart-d98a917e-4c5c-4b52-bdd4-8e62aebf550c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186779100 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.4186779100
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.3303610213
Short name T336
Test name
Test status
Simulation time 271765779 ps
CPU time 3.22 seconds
Started Jul 21 06:42:45 PM PDT 24
Finished Jul 21 06:42:51 PM PDT 24
Peak memory 219920 kb
Host smart-e23a52e9-e3dd-4eda-a740-476c339b4bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303610213 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3303610213
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.2930201752
Short name T272
Test name
Test status
Simulation time 80304090 ps
CPU time 1.19 seconds
Started Jul 21 06:43:11 PM PDT 24
Finished Jul 21 06:43:12 PM PDT 24
Peak memory 218944 kb
Host smart-3f9ef000-c7ca-458f-ab1b-f9c4c8d4c0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930201752 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.2930201752
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.3650362557
Short name T316
Test name
Test status
Simulation time 32300361 ps
CPU time 1.36 seconds
Started Jul 21 06:42:46 PM PDT 24
Finished Jul 21 06:42:49 PM PDT 24
Peak memory 218816 kb
Host smart-5f211913-3693-457e-8889-4b7d9172c631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650362557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3650362557
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.1180442375
Short name T855
Test name
Test status
Simulation time 110814349 ps
CPU time 1.25 seconds
Started Jul 21 06:42:47 PM PDT 24
Finished Jul 21 06:42:50 PM PDT 24
Peak memory 215996 kb
Host smart-f4aea272-d802-4c5a-aa73-2b0d1807e699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180442375 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.1180442375
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.1780010407
Short name T344
Test name
Test status
Simulation time 61453731 ps
CPU time 1.27 seconds
Started Jul 21 06:42:51 PM PDT 24
Finished Jul 21 06:42:54 PM PDT 24
Peak memory 219096 kb
Host smart-5abb4eaf-a1f5-496d-b37f-8efd681d46fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780010407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.1780010407
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.127704867
Short name T178
Test name
Test status
Simulation time 90290061 ps
CPU time 1.17 seconds
Started Jul 21 06:42:49 PM PDT 24
Finished Jul 21 06:42:52 PM PDT 24
Peak memory 220100 kb
Host smart-0292f8af-f40c-4a51-90f5-b155a9800694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127704867 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.127704867
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.1820346786
Short name T605
Test name
Test status
Simulation time 53816936 ps
CPU time 1.49 seconds
Started Jul 21 06:42:46 PM PDT 24
Finished Jul 21 06:42:49 PM PDT 24
Peak memory 217476 kb
Host smart-94d9c9a6-d487-4e69-a034-091945286126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820346786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.1820346786
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.166776033
Short name T932
Test name
Test status
Simulation time 49117689 ps
CPU time 1.16 seconds
Started Jul 21 06:42:55 PM PDT 24
Finished Jul 21 06:42:57 PM PDT 24
Peak memory 219956 kb
Host smart-68072795-ac73-4f44-a63b-9504ab721e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166776033 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.166776033
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.261001600
Short name T694
Test name
Test status
Simulation time 43946917 ps
CPU time 1.54 seconds
Started Jul 21 06:42:57 PM PDT 24
Finished Jul 21 06:43:00 PM PDT 24
Peak memory 218964 kb
Host smart-93c10dd9-ea6b-4482-a81b-47f0f81ff04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261001600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.261001600
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.1395113497
Short name T462
Test name
Test status
Simulation time 168597436 ps
CPU time 1.19 seconds
Started Jul 21 06:40:43 PM PDT 24
Finished Jul 21 06:40:45 PM PDT 24
Peak memory 218772 kb
Host smart-f87d7b84-dd93-4d01-a1e8-ca3ba0684a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395113497 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.1395113497
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.596776227
Short name T392
Test name
Test status
Simulation time 39788266 ps
CPU time 0.88 seconds
Started Jul 21 06:40:45 PM PDT 24
Finished Jul 21 06:40:47 PM PDT 24
Peak memory 215512 kb
Host smart-bdfbe1a4-d334-463e-bfd5-19d66c69e5df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596776227 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.596776227
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.3726703869
Short name T479
Test name
Test status
Simulation time 72766333 ps
CPU time 0.86 seconds
Started Jul 21 06:40:40 PM PDT 24
Finished Jul 21 06:40:42 PM PDT 24
Peak memory 216188 kb
Host smart-1631aa32-5ef1-4d7a-ac4c-6ce199b1abf9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726703869 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.3726703869
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.2306335986
Short name T117
Test name
Test status
Simulation time 36758560 ps
CPU time 1.27 seconds
Started Jul 21 06:40:43 PM PDT 24
Finished Jul 21 06:40:45 PM PDT 24
Peak memory 217076 kb
Host smart-3094d9d9-d839-42ee-a083-cb376c9a6140
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306335986 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.2306335986
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.1029720926
Short name T921
Test name
Test status
Simulation time 57614068 ps
CPU time 1.07 seconds
Started Jul 21 06:40:38 PM PDT 24
Finished Jul 21 06:40:39 PM PDT 24
Peak memory 220292 kb
Host smart-054f78f7-0eb8-4d3f-ad53-57360d3bc50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029720926 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.1029720926
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.1212765697
Short name T536
Test name
Test status
Simulation time 25786477 ps
CPU time 1 seconds
Started Jul 21 06:40:42 PM PDT 24
Finished Jul 21 06:40:44 PM PDT 24
Peak memory 217532 kb
Host smart-1699ceaa-23bf-4f38-8af5-00709d21d9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212765697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1212765697
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.2677478221
Short name T777
Test name
Test status
Simulation time 21668705 ps
CPU time 1.06 seconds
Started Jul 21 06:40:38 PM PDT 24
Finished Jul 21 06:40:39 PM PDT 24
Peak memory 215836 kb
Host smart-02f1fbde-c4d1-42d8-bc07-028e97ae2a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677478221 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.2677478221
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.2983982108
Short name T656
Test name
Test status
Simulation time 22746413 ps
CPU time 0.88 seconds
Started Jul 21 06:40:39 PM PDT 24
Finished Jul 21 06:40:41 PM PDT 24
Peak memory 207352 kb
Host smart-9e18d2d0-ec40-4d6b-aaae-cae7415eb4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983982108 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2983982108
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.527103205
Short name T17
Test name
Test status
Simulation time 639614013 ps
CPU time 3.97 seconds
Started Jul 21 06:40:45 PM PDT 24
Finished Jul 21 06:40:50 PM PDT 24
Peak memory 242208 kb
Host smart-1d405a53-99d7-44f1-b8f4-e30408eebe54
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527103205 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.527103205
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.2804567916
Short name T608
Test name
Test status
Simulation time 29511393 ps
CPU time 0.96 seconds
Started Jul 21 06:40:40 PM PDT 24
Finished Jul 21 06:40:42 PM PDT 24
Peak memory 215536 kb
Host smart-6e56d1e9-b92b-4f98-9b93-8f8f2f36a38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804567916 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.2804567916
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.2341991043
Short name T783
Test name
Test status
Simulation time 452308343 ps
CPU time 3.85 seconds
Started Jul 21 06:40:41 PM PDT 24
Finished Jul 21 06:40:45 PM PDT 24
Peak memory 215584 kb
Host smart-6e3470ff-c60c-45a8-ad18-8db20f7b04b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341991043 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2341991043
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.3516732978
Short name T812
Test name
Test status
Simulation time 489886597032 ps
CPU time 2082.52 seconds
Started Jul 21 06:40:43 PM PDT 24
Finished Jul 21 07:15:27 PM PDT 24
Peak memory 229136 kb
Host smart-09adf6d8-f808-4f23-9517-130087711050
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516732978 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.3516732978
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.193784070
Short name T985
Test name
Test status
Simulation time 22549971 ps
CPU time 1.17 seconds
Started Jul 21 06:41:13 PM PDT 24
Finished Jul 21 06:41:15 PM PDT 24
Peak memory 219108 kb
Host smart-89df63d2-8413-4d67-a76b-0908a37fdcba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193784070 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.193784070
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.2479345761
Short name T721
Test name
Test status
Simulation time 23953464 ps
CPU time 0.88 seconds
Started Jul 21 06:41:15 PM PDT 24
Finished Jul 21 06:41:18 PM PDT 24
Peak memory 215160 kb
Host smart-83fcd72c-8b72-435a-8150-abd2e039e0e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479345761 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2479345761
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.1612491049
Short name T978
Test name
Test status
Simulation time 14372362 ps
CPU time 0.95 seconds
Started Jul 21 06:41:15 PM PDT 24
Finished Jul 21 06:41:18 PM PDT 24
Peak memory 215412 kb
Host smart-f6deffe6-c7d6-4661-a3fb-51032543fa89
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612491049 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1612491049
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_err.1599438230
Short name T150
Test name
Test status
Simulation time 33787039 ps
CPU time 1.11 seconds
Started Jul 21 06:41:11 PM PDT 24
Finished Jul 21 06:41:13 PM PDT 24
Peak memory 221056 kb
Host smart-8e339e22-1583-4b61-a865-445d2d04e1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599438230 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.1599438230
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.323085488
Short name T857
Test name
Test status
Simulation time 85730437 ps
CPU time 2.88 seconds
Started Jul 21 06:41:13 PM PDT 24
Finished Jul 21 06:41:16 PM PDT 24
Peak memory 218892 kb
Host smart-e29afb93-3f7e-4934-81a2-c7a649eb56b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323085488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.323085488
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.721973159
Short name T604
Test name
Test status
Simulation time 22326045 ps
CPU time 1.28 seconds
Started Jul 21 06:41:12 PM PDT 24
Finished Jul 21 06:41:15 PM PDT 24
Peak memory 215816 kb
Host smart-27527de2-5d18-4fd8-b270-bcf093d1db65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721973159 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.721973159
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.3641512096
Short name T948
Test name
Test status
Simulation time 39366640 ps
CPU time 0.94 seconds
Started Jul 21 06:41:17 PM PDT 24
Finished Jul 21 06:41:19 PM PDT 24
Peak memory 215616 kb
Host smart-c495997c-69d5-4eae-a1a0-0a9f7966b0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641512096 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.3641512096
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.918105083
Short name T769
Test name
Test status
Simulation time 189337053 ps
CPU time 2.52 seconds
Started Jul 21 06:41:13 PM PDT 24
Finished Jul 21 06:41:17 PM PDT 24
Peak memory 215480 kb
Host smart-ab40364a-b918-430e-a199-057a3ac7c5de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918105083 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.918105083
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.4034895584
Short name T224
Test name
Test status
Simulation time 111165143188 ps
CPU time 646.61 seconds
Started Jul 21 06:41:14 PM PDT 24
Finished Jul 21 06:52:02 PM PDT 24
Peak memory 221348 kb
Host smart-7e3497d0-98b7-49c0-982b-c1417cc2efde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034895584 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.4034895584
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.4028350892
Short name T810
Test name
Test status
Simulation time 52779971 ps
CPU time 1.13 seconds
Started Jul 21 06:43:05 PM PDT 24
Finished Jul 21 06:43:06 PM PDT 24
Peak memory 219148 kb
Host smart-49d4490f-e253-47c5-b197-25c892fe76c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028350892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.4028350892
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.1222006201
Short name T83
Test name
Test status
Simulation time 50700784 ps
CPU time 1.6 seconds
Started Jul 21 06:43:02 PM PDT 24
Finished Jul 21 06:43:05 PM PDT 24
Peak memory 218684 kb
Host smart-0a3aceff-136a-42fb-9dda-07c2a2ee7d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222006201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.1222006201
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.1405253764
Short name T566
Test name
Test status
Simulation time 116732613 ps
CPU time 3.2 seconds
Started Jul 21 06:43:01 PM PDT 24
Finished Jul 21 06:43:05 PM PDT 24
Peak memory 220308 kb
Host smart-05b8d261-d440-46da-93cd-f85e70e55e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405253764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.1405253764
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.1964508233
Short name T523
Test name
Test status
Simulation time 58818872 ps
CPU time 1.34 seconds
Started Jul 21 06:43:06 PM PDT 24
Finished Jul 21 06:43:08 PM PDT 24
Peak memory 220044 kb
Host smart-a9f5be46-26a2-4f8a-bf09-908db2c56275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964508233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.1964508233
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.3772021588
Short name T396
Test name
Test status
Simulation time 319485633 ps
CPU time 4.3 seconds
Started Jul 21 06:42:45 PM PDT 24
Finished Jul 21 06:42:52 PM PDT 24
Peak memory 217716 kb
Host smart-e1b7bf58-b117-44f0-8653-74a87bc3b9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772021588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3772021588
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3546066424
Short name T738
Test name
Test status
Simulation time 75282289 ps
CPU time 1.06 seconds
Started Jul 21 06:43:00 PM PDT 24
Finished Jul 21 06:43:02 PM PDT 24
Peak memory 219872 kb
Host smart-85e4e3ee-c748-40f5-aef0-91f25f9348c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546066424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3546066424
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2933995148
Short name T627
Test name
Test status
Simulation time 28232261 ps
CPU time 1.22 seconds
Started Jul 21 06:42:46 PM PDT 24
Finished Jul 21 06:42:49 PM PDT 24
Peak memory 220136 kb
Host smart-f2ab5c7f-7807-441c-adcb-a59025419d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933995148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2933995148
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.3999646188
Short name T502
Test name
Test status
Simulation time 48721040 ps
CPU time 1.44 seconds
Started Jul 21 06:42:45 PM PDT 24
Finished Jul 21 06:42:48 PM PDT 24
Peak memory 218888 kb
Host smart-f0e2756a-477c-4e24-add8-d84a617caab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999646188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3999646188
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.2550238151
Short name T899
Test name
Test status
Simulation time 589463372 ps
CPU time 4.55 seconds
Started Jul 21 06:42:44 PM PDT 24
Finished Jul 21 06:42:50 PM PDT 24
Peak memory 220112 kb
Host smart-774727c1-3fb0-4f22-9f7e-005fd91a0d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550238151 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.2550238151
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.1122712263
Short name T446
Test name
Test status
Simulation time 90402449 ps
CPU time 1.4 seconds
Started Jul 21 06:42:55 PM PDT 24
Finished Jul 21 06:42:57 PM PDT 24
Peak memory 215604 kb
Host smart-6489a84c-6da5-4f67-925d-d0d3fe9b1084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122712263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.1122712263
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.2920286761
Short name T859
Test name
Test status
Simulation time 36793062 ps
CPU time 1.09 seconds
Started Jul 21 06:41:14 PM PDT 24
Finished Jul 21 06:41:16 PM PDT 24
Peak memory 219176 kb
Host smart-ad22f92a-2bdd-43a5-9991-2065824bc054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920286761 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.2920286761
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.3846314923
Short name T67
Test name
Test status
Simulation time 20632151 ps
CPU time 0.86 seconds
Started Jul 21 06:41:16 PM PDT 24
Finished Jul 21 06:41:18 PM PDT 24
Peak memory 206800 kb
Host smart-f8ad8a4c-ef89-46fc-8451-a465d8f86365
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846314923 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.3846314923
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.262819196
Short name T174
Test name
Test status
Simulation time 16046120 ps
CPU time 0.81 seconds
Started Jul 21 06:41:16 PM PDT 24
Finished Jul 21 06:41:18 PM PDT 24
Peak memory 216492 kb
Host smart-ac7f32ec-cf45-4fcd-9b5b-7c8ac9cac890
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262819196 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.262819196
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.1369870639
Short name T59
Test name
Test status
Simulation time 80963894 ps
CPU time 1.23 seconds
Started Jul 21 06:41:16 PM PDT 24
Finished Jul 21 06:41:19 PM PDT 24
Peak memory 217196 kb
Host smart-e0872c20-50c1-44d5-b4b7-ff24e1207c19
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369870639 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.1369870639
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_genbits.3353373418
Short name T458
Test name
Test status
Simulation time 50083305 ps
CPU time 1.37 seconds
Started Jul 21 06:41:15 PM PDT 24
Finished Jul 21 06:41:18 PM PDT 24
Peak memory 220024 kb
Host smart-84ab13cb-2757-4638-abb5-a614999480d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353373418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.3353373418
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.2344175882
Short name T425
Test name
Test status
Simulation time 21307707 ps
CPU time 1.07 seconds
Started Jul 21 06:41:16 PM PDT 24
Finished Jul 21 06:41:18 PM PDT 24
Peak memory 215828 kb
Host smart-fed27912-a47a-4edc-b9f3-0576026739ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344175882 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.2344175882
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.2535338803
Short name T959
Test name
Test status
Simulation time 54615721 ps
CPU time 0.92 seconds
Started Jul 21 06:41:12 PM PDT 24
Finished Jul 21 06:41:13 PM PDT 24
Peak memory 215520 kb
Host smart-f35d2818-d459-4f09-b587-8b42ea1b9491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535338803 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.2535338803
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.747175145
Short name T527
Test name
Test status
Simulation time 1752549220 ps
CPU time 3.93 seconds
Started Jul 21 06:41:14 PM PDT 24
Finished Jul 21 06:41:20 PM PDT 24
Peak memory 217616 kb
Host smart-562eaad5-0a4b-4b10-895d-1b3f15ee8237
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747175145 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.747175145
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.3693611345
Short name T564
Test name
Test status
Simulation time 155858127713 ps
CPU time 1193.66 seconds
Started Jul 21 06:41:17 PM PDT 24
Finished Jul 21 07:01:12 PM PDT 24
Peak memory 230388 kb
Host smart-90f759cb-e19a-497b-95d3-233a206ad59f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693611345 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.3693611345
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.1436111572
Short name T554
Test name
Test status
Simulation time 40236201 ps
CPU time 1.15 seconds
Started Jul 21 06:43:07 PM PDT 24
Finished Jul 21 06:43:09 PM PDT 24
Peak memory 219768 kb
Host smart-e98efb47-cf2b-428c-99b8-adc8133e23bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436111572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.1436111572
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.2787020226
Short name T914
Test name
Test status
Simulation time 45572212 ps
CPU time 1.11 seconds
Started Jul 21 06:43:03 PM PDT 24
Finished Jul 21 06:43:05 PM PDT 24
Peak memory 218600 kb
Host smart-23e88d93-2f25-412e-96db-86e6f7625213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787020226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.2787020226
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.754091273
Short name T484
Test name
Test status
Simulation time 76538960 ps
CPU time 1.13 seconds
Started Jul 21 06:42:58 PM PDT 24
Finished Jul 21 06:43:00 PM PDT 24
Peak memory 217424 kb
Host smart-b9e46a30-d5e9-4e2a-90aa-bae735416fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754091273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.754091273
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3122333597
Short name T764
Test name
Test status
Simulation time 103416115 ps
CPU time 1.18 seconds
Started Jul 21 06:42:47 PM PDT 24
Finished Jul 21 06:42:50 PM PDT 24
Peak memory 217520 kb
Host smart-db3cdeb5-06cc-47ad-b7e4-fca21872233f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122333597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3122333597
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.582450293
Short name T601
Test name
Test status
Simulation time 159686623 ps
CPU time 2.45 seconds
Started Jul 21 06:42:45 PM PDT 24
Finished Jul 21 06:42:50 PM PDT 24
Peak memory 220380 kb
Host smart-b7bc681e-3180-424e-ae83-b57eeb12fe30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582450293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.582450293
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.2976762508
Short name T442
Test name
Test status
Simulation time 38453342 ps
CPU time 1.36 seconds
Started Jul 21 06:42:49 PM PDT 24
Finished Jul 21 06:42:52 PM PDT 24
Peak memory 215536 kb
Host smart-e4f04079-f97c-4fd5-a78e-ad136949d5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976762508 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.2976762508
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.2906290566
Short name T524
Test name
Test status
Simulation time 89443498 ps
CPU time 1.63 seconds
Started Jul 21 06:42:46 PM PDT 24
Finished Jul 21 06:42:50 PM PDT 24
Peak memory 219152 kb
Host smart-76e22011-93eb-4add-aa07-be565989c788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906290566 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2906290566
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.3913507882
Short name T411
Test name
Test status
Simulation time 64890745 ps
CPU time 2.51 seconds
Started Jul 21 06:43:00 PM PDT 24
Finished Jul 21 06:43:04 PM PDT 24
Peak memory 220428 kb
Host smart-db740330-2010-4a8b-844d-e793204d01c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913507882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.3913507882
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.3828178687
Short name T645
Test name
Test status
Simulation time 46241995 ps
CPU time 1.32 seconds
Started Jul 21 06:42:58 PM PDT 24
Finished Jul 21 06:43:00 PM PDT 24
Peak memory 218720 kb
Host smart-1c6f142b-8fbd-4ae2-8d7e-a59caef73a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828178687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.3828178687
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.2082080176
Short name T775
Test name
Test status
Simulation time 51074938 ps
CPU time 1.53 seconds
Started Jul 21 06:43:00 PM PDT 24
Finished Jul 21 06:43:03 PM PDT 24
Peak memory 218784 kb
Host smart-67db3347-8e35-4640-a527-64161734da29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082080176 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.2082080176
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.1479767496
Short name T553
Test name
Test status
Simulation time 122922534 ps
CPU time 1.12 seconds
Started Jul 21 06:41:24 PM PDT 24
Finished Jul 21 06:41:27 PM PDT 24
Peak memory 220072 kb
Host smart-590cc355-b02c-4e63-a623-1582e4180b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479767496 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.1479767496
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.600701078
Short name T359
Test name
Test status
Simulation time 17519874 ps
CPU time 1 seconds
Started Jul 21 06:41:19 PM PDT 24
Finished Jul 21 06:41:20 PM PDT 24
Peak memory 215424 kb
Host smart-77efb1c9-dfbc-47ff-ab4b-49755be601df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600701078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.600701078
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.1136907338
Short name T184
Test name
Test status
Simulation time 176073526 ps
CPU time 0.87 seconds
Started Jul 21 06:41:16 PM PDT 24
Finished Jul 21 06:41:18 PM PDT 24
Peak memory 216544 kb
Host smart-d888d5c0-5490-49de-ac7c-343bed1f6b5c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136907338 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.1136907338
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.1812327048
Short name T836
Test name
Test status
Simulation time 40752326 ps
CPU time 1.38 seconds
Started Jul 21 06:41:19 PM PDT 24
Finished Jul 21 06:41:21 PM PDT 24
Peak memory 217192 kb
Host smart-a649c1bf-e0a0-498f-b20e-5be2250dee29
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812327048 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.1812327048
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.3385873743
Short name T980
Test name
Test status
Simulation time 19707829 ps
CPU time 1.13 seconds
Started Jul 21 06:41:21 PM PDT 24
Finished Jul 21 06:41:23 PM PDT 24
Peak memory 218776 kb
Host smart-13ad7dd8-1961-4a58-b0c1-ce1796667fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385873743 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.3385873743
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.2855310085
Short name T860
Test name
Test status
Simulation time 53318408 ps
CPU time 1.49 seconds
Started Jul 21 06:41:18 PM PDT 24
Finished Jul 21 06:41:20 PM PDT 24
Peak memory 218996 kb
Host smart-7dd754ad-aa77-4992-855b-815e55582b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855310085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2855310085
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.803475833
Short name T477
Test name
Test status
Simulation time 20876517 ps
CPU time 1.23 seconds
Started Jul 21 06:41:15 PM PDT 24
Finished Jul 21 06:41:18 PM PDT 24
Peak memory 224228 kb
Host smart-0cdaad58-5ce3-44df-b48f-81dba5eb9c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803475833 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.803475833
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.3172628758
Short name T992
Test name
Test status
Simulation time 114008531 ps
CPU time 0.88 seconds
Started Jul 21 06:41:16 PM PDT 24
Finished Jul 21 06:41:18 PM PDT 24
Peak memory 215376 kb
Host smart-e7988991-7376-458b-af92-20b9fff06824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172628758 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.3172628758
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.1272616450
Short name T236
Test name
Test status
Simulation time 410811011 ps
CPU time 2.48 seconds
Started Jul 21 06:41:18 PM PDT 24
Finished Jul 21 06:41:21 PM PDT 24
Peak memory 217472 kb
Host smart-de7ac279-a5a7-49f5-b010-5cec199ba0e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272616450 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.1272616450
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.2965134387
Short name T306
Test name
Test status
Simulation time 45948712790 ps
CPU time 294.38 seconds
Started Jul 21 06:41:19 PM PDT 24
Finished Jul 21 06:46:14 PM PDT 24
Peak memory 218488 kb
Host smart-6c7c088a-bc5d-4822-a045-d457486a4969
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965134387 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.2965134387
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.1530624958
Short name T415
Test name
Test status
Simulation time 49775289 ps
CPU time 1.29 seconds
Started Jul 21 06:43:07 PM PDT 24
Finished Jul 21 06:43:09 PM PDT 24
Peak memory 218760 kb
Host smart-492403ae-1d6c-4c40-b517-49f97fecc184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530624958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.1530624958
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.321873729
Short name T916
Test name
Test status
Simulation time 49275804 ps
CPU time 1.26 seconds
Started Jul 21 06:42:49 PM PDT 24
Finished Jul 21 06:42:52 PM PDT 24
Peak memory 217664 kb
Host smart-67c72b86-a2ff-4d4d-afa3-0d73daf87a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321873729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.321873729
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.47784088
Short name T64
Test name
Test status
Simulation time 113590440 ps
CPU time 1.24 seconds
Started Jul 21 06:42:51 PM PDT 24
Finished Jul 21 06:42:54 PM PDT 24
Peak memory 217528 kb
Host smart-9f3c79c5-0231-4644-9a5b-12c8943db29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47784088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.47784088
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.1928010936
Short name T811
Test name
Test status
Simulation time 142602164 ps
CPU time 0.95 seconds
Started Jul 21 06:42:52 PM PDT 24
Finished Jul 21 06:42:54 PM PDT 24
Peak memory 217744 kb
Host smart-2832a35f-8a22-4a30-889d-eff1c70c0d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928010936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.1928010936
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.481539830
Short name T903
Test name
Test status
Simulation time 238006221 ps
CPU time 1.02 seconds
Started Jul 21 06:42:51 PM PDT 24
Finished Jul 21 06:42:53 PM PDT 24
Peak memory 217604 kb
Host smart-407bf6f2-3b0c-42da-9cf9-42d76181dc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481539830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.481539830
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.2315736779
Short name T330
Test name
Test status
Simulation time 75834989 ps
CPU time 1.27 seconds
Started Jul 21 06:43:04 PM PDT 24
Finished Jul 21 06:43:06 PM PDT 24
Peak memory 220604 kb
Host smart-79291ed6-2d5b-4397-a704-6e8bdf651dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315736779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.2315736779
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.2848943502
Short name T333
Test name
Test status
Simulation time 45362987 ps
CPU time 1.58 seconds
Started Jul 21 06:43:05 PM PDT 24
Finished Jul 21 06:43:07 PM PDT 24
Peak memory 217528 kb
Host smart-bf7dc5da-b3ba-4147-8abc-1a80e8e701e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848943502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2848943502
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.2119214367
Short name T699
Test name
Test status
Simulation time 53440884 ps
CPU time 1.47 seconds
Started Jul 21 06:43:20 PM PDT 24
Finished Jul 21 06:43:23 PM PDT 24
Peak memory 218908 kb
Host smart-214d90eb-2450-440a-a16f-c29fbdc5363a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119214367 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.2119214367
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.2752543639
Short name T97
Test name
Test status
Simulation time 53099115 ps
CPU time 1.42 seconds
Started Jul 21 06:42:56 PM PDT 24
Finished Jul 21 06:42:59 PM PDT 24
Peak memory 219008 kb
Host smart-8ac8b3d7-adfd-416f-b3c4-d46f1b6d7682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752543639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2752543639
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.907556744
Short name T394
Test name
Test status
Simulation time 123649159 ps
CPU time 1.03 seconds
Started Jul 21 06:42:50 PM PDT 24
Finished Jul 21 06:42:53 PM PDT 24
Peak memory 217716 kb
Host smart-4d3ed1a4-d8ae-4237-9006-0eceeacf2957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907556744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.907556744
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.2496736472
Short name T676
Test name
Test status
Simulation time 100166610 ps
CPU time 1.23 seconds
Started Jul 21 06:41:14 PM PDT 24
Finished Jul 21 06:41:17 PM PDT 24
Peak memory 215996 kb
Host smart-fe7a0493-19d4-470a-b271-4601b2c5a5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496736472 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.2496736472
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.4097591626
Short name T757
Test name
Test status
Simulation time 10604541 ps
CPU time 0.86 seconds
Started Jul 21 06:41:17 PM PDT 24
Finished Jul 21 06:41:19 PM PDT 24
Peak memory 207160 kb
Host smart-3405a8b8-3f95-4e8a-b24b-a539a603a1e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097591626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.4097591626
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.2845507379
Short name T437
Test name
Test status
Simulation time 12088591 ps
CPU time 0.93 seconds
Started Jul 21 06:41:16 PM PDT 24
Finished Jul 21 06:41:18 PM PDT 24
Peak memory 215832 kb
Host smart-01644e1b-8259-4906-aa88-485bd3bca95d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845507379 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2845507379
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3327494789
Short name T797
Test name
Test status
Simulation time 37422896 ps
CPU time 1.54 seconds
Started Jul 21 06:41:19 PM PDT 24
Finished Jul 21 06:41:21 PM PDT 24
Peak memory 217144 kb
Host smart-719b4414-6a82-4b01-b162-e06fd99b823d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327494789 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3327494789
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.4267168486
Short name T546
Test name
Test status
Simulation time 103524496 ps
CPU time 0.91 seconds
Started Jul 21 06:41:21 PM PDT 24
Finished Jul 21 06:41:23 PM PDT 24
Peak memory 220000 kb
Host smart-7e2f620d-9ab6-46bd-b7b8-af803dc200f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267168486 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.4267168486
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_intr.852514927
Short name T826
Test name
Test status
Simulation time 27028899 ps
CPU time 0.97 seconds
Started Jul 21 06:41:15 PM PDT 24
Finished Jul 21 06:41:18 PM PDT 24
Peak memory 215736 kb
Host smart-76e1ed4a-2cf0-4a41-a961-4b609283a8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852514927 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.852514927
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.2229200666
Short name T749
Test name
Test status
Simulation time 22249137 ps
CPU time 0.88 seconds
Started Jul 21 06:41:24 PM PDT 24
Finished Jul 21 06:41:27 PM PDT 24
Peak memory 215536 kb
Host smart-b43cce8c-29ac-4789-9030-50499b1997ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229200666 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.2229200666
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.3979812507
Short name T304
Test name
Test status
Simulation time 414084595 ps
CPU time 4.69 seconds
Started Jul 21 06:41:19 PM PDT 24
Finished Jul 21 06:41:24 PM PDT 24
Peak memory 215636 kb
Host smart-e26a7f1e-5d4d-41d3-9f04-947bb33f2f49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979812507 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3979812507
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.617363548
Short name T970
Test name
Test status
Simulation time 178322371547 ps
CPU time 2249.23 seconds
Started Jul 21 06:41:24 PM PDT 24
Finished Jul 21 07:18:55 PM PDT 24
Peak memory 231112 kb
Host smart-fb3c87ff-e9d0-4475-b4ff-76a28da66235
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617363548 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.617363548
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.1327789801
Short name T533
Test name
Test status
Simulation time 88951974 ps
CPU time 1.32 seconds
Started Jul 21 06:43:06 PM PDT 24
Finished Jul 21 06:43:08 PM PDT 24
Peak memory 217572 kb
Host smart-f644b73b-85fe-409a-b369-0ea0d3757830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327789801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.1327789801
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.541663417
Short name T508
Test name
Test status
Simulation time 39453108 ps
CPU time 1.34 seconds
Started Jul 21 06:43:09 PM PDT 24
Finished Jul 21 06:43:11 PM PDT 24
Peak memory 215672 kb
Host smart-8ef98e8d-ff6a-4e56-8169-e972ee5cc1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541663417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.541663417
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.1050884432
Short name T639
Test name
Test status
Simulation time 52084771 ps
CPU time 1.08 seconds
Started Jul 21 06:42:52 PM PDT 24
Finished Jul 21 06:42:54 PM PDT 24
Peak memory 217560 kb
Host smart-ae425166-10ea-4da6-a01e-8d651cacda87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050884432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.1050884432
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.3198913929
Short name T368
Test name
Test status
Simulation time 59831435 ps
CPU time 1.09 seconds
Started Jul 21 06:43:04 PM PDT 24
Finished Jul 21 06:43:06 PM PDT 24
Peak memory 215528 kb
Host smart-f9b62bb2-32c7-4144-ac67-cdf9a5bf5a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198913929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3198913929
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.878133963
Short name T367
Test name
Test status
Simulation time 68481337 ps
CPU time 1.31 seconds
Started Jul 21 06:42:52 PM PDT 24
Finished Jul 21 06:42:55 PM PDT 24
Peak memory 218532 kb
Host smart-a96f5b9b-e70f-441b-a048-239a8179c9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878133963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.878133963
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.769625192
Short name T445
Test name
Test status
Simulation time 44542500 ps
CPU time 1.88 seconds
Started Jul 21 06:43:07 PM PDT 24
Finished Jul 21 06:43:09 PM PDT 24
Peak memory 219008 kb
Host smart-280d9ecf-2004-4331-9b34-b77ee30554a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769625192 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.769625192
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.1322299773
Short name T434
Test name
Test status
Simulation time 88486695 ps
CPU time 1.41 seconds
Started Jul 21 06:43:01 PM PDT 24
Finished Jul 21 06:43:04 PM PDT 24
Peak memory 219276 kb
Host smart-040e3dfe-dc16-4d5a-b874-457a57153cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322299773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.1322299773
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.1697989332
Short name T667
Test name
Test status
Simulation time 20461473 ps
CPU time 1.16 seconds
Started Jul 21 06:42:57 PM PDT 24
Finished Jul 21 06:42:59 PM PDT 24
Peak memory 218912 kb
Host smart-4405a6f0-5a1b-4ba5-9cf5-079d1031e5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697989332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1697989332
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.2516156120
Short name T582
Test name
Test status
Simulation time 123550078 ps
CPU time 1.3 seconds
Started Jul 21 06:43:02 PM PDT 24
Finished Jul 21 06:43:04 PM PDT 24
Peak memory 220116 kb
Host smart-79853c6d-96b2-48cd-9c8f-55aabe7e0c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516156120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.2516156120
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.3244945636
Short name T569
Test name
Test status
Simulation time 25893126 ps
CPU time 1.35 seconds
Started Jul 21 06:43:08 PM PDT 24
Finished Jul 21 06:43:10 PM PDT 24
Peak memory 218928 kb
Host smart-bd0bb2cf-7a29-4637-a49f-6f3e18d8a464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244945636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.3244945636
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.2698442866
Short name T993
Test name
Test status
Simulation time 106401098 ps
CPU time 1.19 seconds
Started Jul 21 06:41:21 PM PDT 24
Finished Jul 21 06:41:23 PM PDT 24
Peak memory 219880 kb
Host smart-cd13b4ee-f01e-4743-ac7d-1e322f5b7a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698442866 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.2698442866
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.4092384260
Short name T472
Test name
Test status
Simulation time 77457958 ps
CPU time 0.94 seconds
Started Jul 21 06:41:24 PM PDT 24
Finished Jul 21 06:41:26 PM PDT 24
Peak memory 207000 kb
Host smart-4f7dc2c0-653d-4947-9614-61a606b993a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092384260 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.4092384260
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.3327740375
Short name T204
Test name
Test status
Simulation time 12304017 ps
CPU time 0.87 seconds
Started Jul 21 06:41:20 PM PDT 24
Finished Jul 21 06:41:21 PM PDT 24
Peak memory 216676 kb
Host smart-08330c61-571e-4a23-a480-3d39463cd4d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327740375 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.3327740375
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.434060244
Short name T345
Test name
Test status
Simulation time 79254221 ps
CPU time 1.08 seconds
Started Jul 21 06:41:28 PM PDT 24
Finished Jul 21 06:41:32 PM PDT 24
Peak memory 218584 kb
Host smart-7fe1e3f4-38a4-4f43-b99f-8f76984554f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434060244 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_di
sable_auto_req_mode.434060244
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.3889581720
Short name T427
Test name
Test status
Simulation time 34050888 ps
CPU time 0.89 seconds
Started Jul 21 06:41:21 PM PDT 24
Finished Jul 21 06:41:23 PM PDT 24
Peak memory 218464 kb
Host smart-def95873-7913-4821-9fb9-47fcac4fa375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889581720 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.3889581720
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.3445244856
Short name T734
Test name
Test status
Simulation time 59958703 ps
CPU time 1.64 seconds
Started Jul 21 06:41:27 PM PDT 24
Finished Jul 21 06:41:32 PM PDT 24
Peak memory 218908 kb
Host smart-a4eb7437-4dd1-4066-a474-9f991c1d55d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445244856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.3445244856
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.704947168
Short name T30
Test name
Test status
Simulation time 99320226 ps
CPU time 0.85 seconds
Started Jul 21 06:41:22 PM PDT 24
Finished Jul 21 06:41:24 PM PDT 24
Peak memory 215804 kb
Host smart-8b297738-a1c3-4a66-9c57-63780e11f029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704947168 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.704947168
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.4054781440
Short name T385
Test name
Test status
Simulation time 23893909 ps
CPU time 1.01 seconds
Started Jul 21 06:41:14 PM PDT 24
Finished Jul 21 06:41:17 PM PDT 24
Peak memory 215532 kb
Host smart-d9ab5c65-d97a-410c-999d-ff0aca22943a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054781440 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.4054781440
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.2483800172
Short name T521
Test name
Test status
Simulation time 1635292465 ps
CPU time 5 seconds
Started Jul 21 06:41:23 PM PDT 24
Finished Jul 21 06:41:29 PM PDT 24
Peak memory 217424 kb
Host smart-5a0056a2-878a-4ba1-ae1a-3b385616335e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483800172 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2483800172
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.3677776481
Short name T871
Test name
Test status
Simulation time 93479007458 ps
CPU time 2192.86 seconds
Started Jul 21 06:41:23 PM PDT 24
Finished Jul 21 07:17:57 PM PDT 24
Peak memory 228168 kb
Host smart-57d717f9-27bf-48b0-b9c8-f6691da473b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677776481 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.3677776481
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.4253816081
Short name T307
Test name
Test status
Simulation time 60871176 ps
CPU time 1.7 seconds
Started Jul 21 06:42:56 PM PDT 24
Finished Jul 21 06:42:58 PM PDT 24
Peak memory 218920 kb
Host smart-de335044-de5a-4167-abdf-faa1b62ed224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253816081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.4253816081
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.6601452
Short name T821
Test name
Test status
Simulation time 68187246 ps
CPU time 1.06 seconds
Started Jul 21 06:42:51 PM PDT 24
Finished Jul 21 06:42:54 PM PDT 24
Peak memory 217600 kb
Host smart-e960ebd2-c4dd-4877-b2e6-724b7a459eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6601452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.6601452
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.351605132
Short name T793
Test name
Test status
Simulation time 43491273 ps
CPU time 1.08 seconds
Started Jul 21 06:42:54 PM PDT 24
Finished Jul 21 06:42:55 PM PDT 24
Peak memory 217700 kb
Host smart-a9f5d084-7e38-4657-a36e-1c043e20c185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351605132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.351605132
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.473901153
Short name T900
Test name
Test status
Simulation time 56357107 ps
CPU time 1.49 seconds
Started Jul 21 06:42:55 PM PDT 24
Finished Jul 21 06:42:57 PM PDT 24
Peak memory 219172 kb
Host smart-160db918-adee-4c5e-930a-775c676cad26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473901153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.473901153
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.1230209825
Short name T823
Test name
Test status
Simulation time 88519672 ps
CPU time 1.4 seconds
Started Jul 21 06:42:58 PM PDT 24
Finished Jul 21 06:43:00 PM PDT 24
Peak memory 217680 kb
Host smart-7486bb00-5bf8-457a-9daa-8a98c4c7f4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230209825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1230209825
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.219957958
Short name T429
Test name
Test status
Simulation time 47526925 ps
CPU time 0.95 seconds
Started Jul 21 06:42:58 PM PDT 24
Finished Jul 21 06:43:00 PM PDT 24
Peak memory 217548 kb
Host smart-d22b4600-e0c7-459c-a73e-76cd15571a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219957958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.219957958
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.4239916888
Short name T583
Test name
Test status
Simulation time 49585338 ps
CPU time 1.22 seconds
Started Jul 21 06:42:57 PM PDT 24
Finished Jul 21 06:42:59 PM PDT 24
Peak memory 220044 kb
Host smart-c5bd724e-610f-467f-ba1b-22a51e42bf37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239916888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.4239916888
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.3053372836
Short name T12
Test name
Test status
Simulation time 118842013 ps
CPU time 1.32 seconds
Started Jul 21 06:43:05 PM PDT 24
Finished Jul 21 06:43:07 PM PDT 24
Peak memory 220296 kb
Host smart-b0ad87f1-a5ca-479b-b05f-7f1ff3ffde33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053372836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.3053372836
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.21943985
Short name T161
Test name
Test status
Simulation time 84582508 ps
CPU time 1.18 seconds
Started Jul 21 06:41:24 PM PDT 24
Finished Jul 21 06:41:27 PM PDT 24
Peak memory 221696 kb
Host smart-19c03825-9690-472e-a6b7-3417b117f5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21943985 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.21943985
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.3559737251
Short name T350
Test name
Test status
Simulation time 62621806 ps
CPU time 0.99 seconds
Started Jul 21 06:41:22 PM PDT 24
Finished Jul 21 06:41:24 PM PDT 24
Peak memory 215208 kb
Host smart-f6d98741-112a-4a5a-aa31-3a2e03ce5481
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559737251 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3559737251
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.3244776323
Short name T522
Test name
Test status
Simulation time 33105073 ps
CPU time 0.85 seconds
Started Jul 21 06:41:20 PM PDT 24
Finished Jul 21 06:41:22 PM PDT 24
Peak memory 216500 kb
Host smart-ae4117c1-e067-4141-93ed-90cc7a665138
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244776323 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.3244776323
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.1156017555
Short name T146
Test name
Test status
Simulation time 112925187 ps
CPU time 1.15 seconds
Started Jul 21 06:41:22 PM PDT 24
Finished Jul 21 06:41:24 PM PDT 24
Peak memory 217588 kb
Host smart-f71d71e9-3445-4e2f-aff9-b40a259665df
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156017555 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.1156017555
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.2838081783
Short name T46
Test name
Test status
Simulation time 20156385 ps
CPU time 1.01 seconds
Started Jul 21 06:41:22 PM PDT 24
Finished Jul 21 06:41:24 PM PDT 24
Peak memory 219788 kb
Host smart-6d0f785a-e8aa-4231-9782-6329e2c3af40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838081783 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.2838081783
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.2431087097
Short name T496
Test name
Test status
Simulation time 74273158 ps
CPU time 2.55 seconds
Started Jul 21 06:41:25 PM PDT 24
Finished Jul 21 06:41:29 PM PDT 24
Peak memory 220564 kb
Host smart-3905cad6-aefe-43da-b2a7-f824dab4a4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431087097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.2431087097
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.1165673579
Short name T675
Test name
Test status
Simulation time 33131048 ps
CPU time 0.85 seconds
Started Jul 21 06:41:27 PM PDT 24
Finished Jul 21 06:41:31 PM PDT 24
Peak memory 215944 kb
Host smart-3a3e8c21-9bb2-4af8-8119-043d44dbc06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165673579 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.1165673579
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.964698212
Short name T606
Test name
Test status
Simulation time 30337704 ps
CPU time 0.93 seconds
Started Jul 21 06:41:25 PM PDT 24
Finished Jul 21 06:41:28 PM PDT 24
Peak memory 215536 kb
Host smart-8b76d2da-a19f-4cc4-8d7a-70bb57d2b7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964698212 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.964698212
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2320368865
Short name T951
Test name
Test status
Simulation time 331732222 ps
CPU time 4.5 seconds
Started Jul 21 06:41:25 PM PDT 24
Finished Jul 21 06:41:33 PM PDT 24
Peak memory 215712 kb
Host smart-25e38058-fb56-4d08-811f-6de7a67fc77a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320368865 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2320368865
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.415401613
Short name T433
Test name
Test status
Simulation time 231777739863 ps
CPU time 559.75 seconds
Started Jul 21 06:41:23 PM PDT 24
Finished Jul 21 06:50:43 PM PDT 24
Peak memory 228164 kb
Host smart-5ad49309-5fbc-4e44-944e-88a0c033da61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415401613 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.415401613
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.59482366
Short name T940
Test name
Test status
Simulation time 40388417 ps
CPU time 1.43 seconds
Started Jul 21 06:43:15 PM PDT 24
Finished Jul 21 06:43:18 PM PDT 24
Peak memory 218660 kb
Host smart-81df5a8e-af7a-489b-b940-fe1b8d9ca78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59482366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.59482366
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.677169271
Short name T755
Test name
Test status
Simulation time 79826373 ps
CPU time 2.46 seconds
Started Jul 21 06:43:07 PM PDT 24
Finished Jul 21 06:43:10 PM PDT 24
Peak memory 219112 kb
Host smart-9f516434-8cbf-4f1a-99fe-0d6a266feb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677169271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.677169271
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.219391091
Short name T825
Test name
Test status
Simulation time 66489652 ps
CPU time 1.36 seconds
Started Jul 21 06:42:53 PM PDT 24
Finished Jul 21 06:42:55 PM PDT 24
Peak memory 217400 kb
Host smart-b5201d11-5f62-4943-8e36-33ce8cd4f692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219391091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.219391091
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.2145735679
Short name T560
Test name
Test status
Simulation time 52783934 ps
CPU time 1.52 seconds
Started Jul 21 06:42:56 PM PDT 24
Finished Jul 21 06:42:58 PM PDT 24
Peak memory 220232 kb
Host smart-fae71f72-9f8a-4c02-8fef-fe2b82c0844a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145735679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.2145735679
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.3231074948
Short name T831
Test name
Test status
Simulation time 42749919 ps
CPU time 1.48 seconds
Started Jul 21 06:42:52 PM PDT 24
Finished Jul 21 06:42:55 PM PDT 24
Peak memory 220120 kb
Host smart-435eff14-150a-4e24-87ac-534be42e248d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231074948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.3231074948
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.4025730036
Short name T632
Test name
Test status
Simulation time 62861426 ps
CPU time 2.34 seconds
Started Jul 21 06:42:49 PM PDT 24
Finished Jul 21 06:42:53 PM PDT 24
Peak memory 220428 kb
Host smart-a9710282-d531-4381-8b91-02a51ba939d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025730036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.4025730036
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.1285036046
Short name T917
Test name
Test status
Simulation time 32556678 ps
CPU time 1.33 seconds
Started Jul 21 06:42:51 PM PDT 24
Finished Jul 21 06:42:54 PM PDT 24
Peak memory 217472 kb
Host smart-83bb5381-4278-40f2-802f-c6aad07fde3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285036046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1285036046
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.923191321
Short name T389
Test name
Test status
Simulation time 49556628 ps
CPU time 1.15 seconds
Started Jul 21 06:42:51 PM PDT 24
Finished Jul 21 06:42:54 PM PDT 24
Peak memory 217544 kb
Host smart-b29bdbdd-fda7-407a-bb61-5bd82463d556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923191321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.923191321
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.217512568
Short name T373
Test name
Test status
Simulation time 222005636 ps
CPU time 3.12 seconds
Started Jul 21 06:43:09 PM PDT 24
Finished Jul 21 06:43:12 PM PDT 24
Peak memory 220516 kb
Host smart-e39fcd0f-e85a-4569-bfdd-751a1b6f822c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217512568 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.217512568
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.2527014092
Short name T323
Test name
Test status
Simulation time 73067070 ps
CPU time 1.48 seconds
Started Jul 21 06:43:17 PM PDT 24
Finished Jul 21 06:43:20 PM PDT 24
Peak memory 220160 kb
Host smart-7f075e57-2b14-4c71-b415-42bf686470f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527014092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.2527014092
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.3404561044
Short name T787
Test name
Test status
Simulation time 30166920 ps
CPU time 1.32 seconds
Started Jul 21 06:41:20 PM PDT 24
Finished Jul 21 06:41:22 PM PDT 24
Peak memory 216004 kb
Host smart-f6c14488-7a66-4d61-86b8-bdc719fc427d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404561044 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.3404561044
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.2485130341
Short name T349
Test name
Test status
Simulation time 60594288 ps
CPU time 0.94 seconds
Started Jul 21 06:41:20 PM PDT 24
Finished Jul 21 06:41:21 PM PDT 24
Peak memory 215240 kb
Host smart-f5981a99-02cd-4a17-9fa9-c4db43eb170e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485130341 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2485130341
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.1965446323
Short name T215
Test name
Test status
Simulation time 35579748 ps
CPU time 0.84 seconds
Started Jul 21 06:41:26 PM PDT 24
Finished Jul 21 06:41:35 PM PDT 24
Peak memory 216620 kb
Host smart-af62fd78-d5f6-42af-b521-76b01c75a838
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965446323 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1965446323
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.4253601724
Short name T754
Test name
Test status
Simulation time 106721226 ps
CPU time 1.22 seconds
Started Jul 21 06:41:22 PM PDT 24
Finished Jul 21 06:41:24 PM PDT 24
Peak memory 217124 kb
Host smart-f55b6539-4a47-4043-841b-1981debd82d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253601724 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.4253601724
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.4138219806
Short name T193
Test name
Test status
Simulation time 18971793 ps
CPU time 1.17 seconds
Started Jul 21 06:41:19 PM PDT 24
Finished Jul 21 06:41:21 PM PDT 24
Peak memory 229900 kb
Host smart-7958614d-62ed-4df2-b3f3-261830822035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138219806 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.4138219806
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.2664814831
Short name T983
Test name
Test status
Simulation time 71932061 ps
CPU time 1.17 seconds
Started Jul 21 06:41:22 PM PDT 24
Finished Jul 21 06:41:24 PM PDT 24
Peak memory 217368 kb
Host smart-6d150e59-4027-4cc9-8f9c-883ea1cf3d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664814831 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.2664814831
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.3880655765
Short name T607
Test name
Test status
Simulation time 22524051 ps
CPU time 0.98 seconds
Started Jul 21 06:41:21 PM PDT 24
Finished Jul 21 06:41:23 PM PDT 24
Peak memory 216056 kb
Host smart-3cbab7a4-99ad-4549-9e43-35765ffc6c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880655765 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.3880655765
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.179089047
Short name T723
Test name
Test status
Simulation time 29025514 ps
CPU time 0.94 seconds
Started Jul 21 06:41:21 PM PDT 24
Finished Jul 21 06:41:23 PM PDT 24
Peak memory 215540 kb
Host smart-249729c6-d80c-4e53-9eff-836a219beff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179089047 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.179089047
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.726765462
Short name T235
Test name
Test status
Simulation time 1062066553 ps
CPU time 5.56 seconds
Started Jul 21 06:41:21 PM PDT 24
Finished Jul 21 06:41:27 PM PDT 24
Peak memory 217472 kb
Host smart-683b3c58-47c8-47c5-8597-6ad30c382810
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726765462 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.726765462
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.274642179
Short name T222
Test name
Test status
Simulation time 56597521049 ps
CPU time 714.66 seconds
Started Jul 21 06:41:27 PM PDT 24
Finished Jul 21 06:53:25 PM PDT 24
Peak memory 223928 kb
Host smart-0f80ac01-ecc0-4b80-888f-255449959909
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274642179 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.274642179
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.2355963505
Short name T19
Test name
Test status
Simulation time 54535665 ps
CPU time 1.16 seconds
Started Jul 21 06:43:15 PM PDT 24
Finished Jul 21 06:43:18 PM PDT 24
Peak memory 217716 kb
Host smart-bad8bb88-b536-4e51-a574-98ea57e9241a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355963505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.2355963505
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.1989976210
Short name T703
Test name
Test status
Simulation time 221489438 ps
CPU time 3.46 seconds
Started Jul 21 06:42:56 PM PDT 24
Finished Jul 21 06:43:01 PM PDT 24
Peak memory 217892 kb
Host smart-027ad620-449d-438c-a51d-a3b44ab3de3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989976210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1989976210
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.4089265729
Short name T356
Test name
Test status
Simulation time 54302963 ps
CPU time 1.37 seconds
Started Jul 21 06:43:17 PM PDT 24
Finished Jul 21 06:43:19 PM PDT 24
Peak memory 218956 kb
Host smart-32efd67e-a978-4cc8-841b-a86fb0348858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089265729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.4089265729
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.1482665116
Short name T416
Test name
Test status
Simulation time 55140836 ps
CPU time 1.83 seconds
Started Jul 21 06:42:57 PM PDT 24
Finished Jul 21 06:43:00 PM PDT 24
Peak memory 218912 kb
Host smart-f9844026-b3c0-4695-a4d9-e3c82927342e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482665116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1482665116
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.1299855536
Short name T767
Test name
Test status
Simulation time 101773206 ps
CPU time 1.31 seconds
Started Jul 21 06:43:16 PM PDT 24
Finished Jul 21 06:43:18 PM PDT 24
Peak memory 219084 kb
Host smart-ca65afc3-ea64-4e44-82d8-eef08e9433c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299855536 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.1299855536
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.3891166656
Short name T975
Test name
Test status
Simulation time 60931208 ps
CPU time 1.15 seconds
Started Jul 21 06:43:15 PM PDT 24
Finished Jul 21 06:43:17 PM PDT 24
Peak memory 217524 kb
Host smart-ae5baa0a-8735-401b-925d-6eaa02a0cb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891166656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.3891166656
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.1364636107
Short name T312
Test name
Test status
Simulation time 33312016 ps
CPU time 1.55 seconds
Started Jul 21 06:42:55 PM PDT 24
Finished Jul 21 06:42:57 PM PDT 24
Peak memory 218816 kb
Host smart-960fedd2-703f-4ccd-bf71-8978eaa63bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364636107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.1364636107
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.1858081976
Short name T905
Test name
Test status
Simulation time 345318247 ps
CPU time 3.66 seconds
Started Jul 21 06:42:59 PM PDT 24
Finished Jul 21 06:43:04 PM PDT 24
Peak memory 220616 kb
Host smart-2eb41bcb-002c-4862-baea-9faf30d44640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858081976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.1858081976
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.496991312
Short name T881
Test name
Test status
Simulation time 126222144 ps
CPU time 1.14 seconds
Started Jul 21 06:43:13 PM PDT 24
Finished Jul 21 06:43:15 PM PDT 24
Peak memory 217592 kb
Host smart-560c7468-ae70-4a80-a656-cd6e818ccbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496991312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.496991312
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.345798353
Short name T534
Test name
Test status
Simulation time 36918388 ps
CPU time 1.49 seconds
Started Jul 21 06:43:04 PM PDT 24
Finished Jul 21 06:43:06 PM PDT 24
Peak memory 218716 kb
Host smart-ea35f630-fb5e-40b7-9289-aaa4aded79bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345798353 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.345798353
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.1026139350
Short name T154
Test name
Test status
Simulation time 99507090 ps
CPU time 1.25 seconds
Started Jul 21 06:41:20 PM PDT 24
Finished Jul 21 06:41:22 PM PDT 24
Peak memory 218884 kb
Host smart-f54401be-e546-4b5c-aefd-0f85922d2a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026139350 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.1026139350
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1756812570
Short name T981
Test name
Test status
Simulation time 12054008 ps
CPU time 0.86 seconds
Started Jul 21 06:41:21 PM PDT 24
Finished Jul 21 06:41:23 PM PDT 24
Peak memory 207104 kb
Host smart-7972dcf8-d48c-4d53-bec8-988c2b23a40b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756812570 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1756812570
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.3670979093
Short name T785
Test name
Test status
Simulation time 30079439 ps
CPU time 1.07 seconds
Started Jul 21 06:41:19 PM PDT 24
Finished Jul 21 06:41:20 PM PDT 24
Peak memory 216996 kb
Host smart-b1b81668-d9ee-43cf-8ae4-6f47a36d8c81
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670979093 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.3670979093
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.1064801706
Short name T197
Test name
Test status
Simulation time 20933106 ps
CPU time 1.08 seconds
Started Jul 21 06:41:22 PM PDT 24
Finished Jul 21 06:41:23 PM PDT 24
Peak memory 218816 kb
Host smart-61148dca-d7de-4d59-a9c0-99ef336564cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064801706 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.1064801706
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.3733742812
Short name T89
Test name
Test status
Simulation time 39376317 ps
CPU time 1.65 seconds
Started Jul 21 06:41:24 PM PDT 24
Finished Jul 21 06:41:27 PM PDT 24
Peak memory 218908 kb
Host smart-a64cd5c0-5248-42e5-b838-4d19e56e5b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733742812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.3733742812
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.2510687765
Short name T547
Test name
Test status
Simulation time 22878051 ps
CPU time 1.17 seconds
Started Jul 21 06:41:20 PM PDT 24
Finished Jul 21 06:41:22 PM PDT 24
Peak memory 224456 kb
Host smart-acdb7af3-a6c2-413c-b302-1045a749929a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510687765 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.2510687765
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.2288666223
Short name T768
Test name
Test status
Simulation time 24250251 ps
CPU time 0.95 seconds
Started Jul 21 06:41:25 PM PDT 24
Finished Jul 21 06:41:28 PM PDT 24
Peak memory 215540 kb
Host smart-449b0fc7-9155-440d-8c36-088e326deb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288666223 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.2288666223
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.2214948945
Short name T234
Test name
Test status
Simulation time 235809592 ps
CPU time 2.78 seconds
Started Jul 21 06:41:23 PM PDT 24
Finished Jul 21 06:41:27 PM PDT 24
Peak memory 217520 kb
Host smart-c7f1020e-c75d-4109-abfb-2183015eaa5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214948945 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2214948945
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/270.edn_genbits.1395080687
Short name T530
Test name
Test status
Simulation time 36203394 ps
CPU time 1.4 seconds
Started Jul 21 06:42:58 PM PDT 24
Finished Jul 21 06:43:01 PM PDT 24
Peak memory 218760 kb
Host smart-cdf8d61e-b9cf-46a5-8545-9930130c738e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395080687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.1395080687
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.834967098
Short name T898
Test name
Test status
Simulation time 30768149 ps
CPU time 1.24 seconds
Started Jul 21 06:42:57 PM PDT 24
Finished Jul 21 06:42:59 PM PDT 24
Peak memory 217420 kb
Host smart-9571de0b-9e74-4609-98e4-1caacfd12452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834967098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.834967098
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.2004811043
Short name T377
Test name
Test status
Simulation time 45115981 ps
CPU time 1.41 seconds
Started Jul 21 06:43:16 PM PDT 24
Finished Jul 21 06:43:18 PM PDT 24
Peak memory 217456 kb
Host smart-bfc14951-49fe-4ad8-a9db-de4d71c859bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004811043 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2004811043
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.2598375986
Short name T422
Test name
Test status
Simulation time 29272156 ps
CPU time 1.27 seconds
Started Jul 21 06:42:59 PM PDT 24
Finished Jul 21 06:43:01 PM PDT 24
Peak memory 220188 kb
Host smart-6a512332-08a1-4b68-a06a-b299d67affcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598375986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.2598375986
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.836963653
Short name T626
Test name
Test status
Simulation time 149926151 ps
CPU time 1.98 seconds
Started Jul 21 06:43:04 PM PDT 24
Finished Jul 21 06:43:06 PM PDT 24
Peak memory 219152 kb
Host smart-e36aaa83-7dfa-483a-8174-8d2d520ca91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836963653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.836963653
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.487482532
Short name T995
Test name
Test status
Simulation time 79976044 ps
CPU time 1.77 seconds
Started Jul 21 06:43:11 PM PDT 24
Finished Jul 21 06:43:13 PM PDT 24
Peak memory 219088 kb
Host smart-5ef7b3bf-fbab-4c01-b7c9-299c2b63ba8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487482532 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.487482532
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.3575205247
Short name T480
Test name
Test status
Simulation time 47031320 ps
CPU time 1.13 seconds
Started Jul 21 06:43:00 PM PDT 24
Finished Jul 21 06:43:03 PM PDT 24
Peak memory 217464 kb
Host smart-0a8bb5c0-153b-42ca-b4bb-0af56e8f4bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575205247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.3575205247
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.2141177831
Short name T792
Test name
Test status
Simulation time 31445692 ps
CPU time 1.25 seconds
Started Jul 21 06:42:57 PM PDT 24
Finished Jul 21 06:42:59 PM PDT 24
Peak memory 217496 kb
Host smart-09929313-a6bf-4258-8080-e9c6e463ef10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141177831 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.2141177831
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.1925618444
Short name T845
Test name
Test status
Simulation time 46992588 ps
CPU time 1.91 seconds
Started Jul 21 06:43:12 PM PDT 24
Finished Jul 21 06:43:15 PM PDT 24
Peak memory 218984 kb
Host smart-0ed05b1d-e65c-43b0-ad39-8c16a81dfe8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925618444 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.1925618444
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.1453717683
Short name T824
Test name
Test status
Simulation time 46764974 ps
CPU time 1.12 seconds
Started Jul 21 06:41:25 PM PDT 24
Finished Jul 21 06:41:29 PM PDT 24
Peak memory 220372 kb
Host smart-6fe40c3e-eb1b-49c0-83a7-f583343e178b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453717683 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.1453717683
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.981276955
Short name T730
Test name
Test status
Simulation time 53771737 ps
CPU time 0.95 seconds
Started Jul 21 06:41:27 PM PDT 24
Finished Jul 21 06:41:31 PM PDT 24
Peak memory 206984 kb
Host smart-4ccb4db1-a79c-4139-a334-f751706acbae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981276955 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.981276955
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.3509088769
Short name T451
Test name
Test status
Simulation time 27530837 ps
CPU time 0.91 seconds
Started Jul 21 06:41:27 PM PDT 24
Finished Jul 21 06:41:31 PM PDT 24
Peak memory 216500 kb
Host smart-88a5392e-233e-4945-94bf-5d00c6360c8c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509088769 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.3509088769
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.1092012173
Short name T360
Test name
Test status
Simulation time 173460672 ps
CPU time 1.09 seconds
Started Jul 21 06:41:27 PM PDT 24
Finished Jul 21 06:41:31 PM PDT 24
Peak memory 217272 kb
Host smart-eb90c5e6-e1ce-4ae6-baf6-31b1bd70a08f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092012173 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.1092012173
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.2617548783
Short name T143
Test name
Test status
Simulation time 57265226 ps
CPU time 1.04 seconds
Started Jul 21 06:41:26 PM PDT 24
Finished Jul 21 06:41:30 PM PDT 24
Peak memory 221112 kb
Host smart-be1251c7-6d3d-469d-93fb-c80f58d2b88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617548783 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2617548783
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.1127306785
Short name T357
Test name
Test status
Simulation time 61967985 ps
CPU time 1.04 seconds
Started Jul 21 06:41:21 PM PDT 24
Finished Jul 21 06:41:23 PM PDT 24
Peak memory 217524 kb
Host smart-e27eb952-f018-49e0-8f98-0cebb8268988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127306785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.1127306785
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.2160823800
Short name T610
Test name
Test status
Simulation time 19559116 ps
CPU time 1.07 seconds
Started Jul 21 06:41:24 PM PDT 24
Finished Jul 21 06:41:27 PM PDT 24
Peak memory 216164 kb
Host smart-2866cad7-b569-4649-9a3c-4af4ea6e4930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160823800 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.2160823800
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.3408182280
Short name T354
Test name
Test status
Simulation time 46104902 ps
CPU time 0.94 seconds
Started Jul 21 06:41:27 PM PDT 24
Finished Jul 21 06:41:34 PM PDT 24
Peak memory 215588 kb
Host smart-7265251f-6f84-4154-bc3a-e5813dc09cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408182280 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.3408182280
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.1452167484
Short name T808
Test name
Test status
Simulation time 684214065 ps
CPU time 6.25 seconds
Started Jul 21 06:41:23 PM PDT 24
Finished Jul 21 06:41:30 PM PDT 24
Peak memory 215640 kb
Host smart-822c4003-aa3d-4322-aaf2-99d0961e991b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452167484 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.1452167484
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.2150059307
Short name T494
Test name
Test status
Simulation time 142903805693 ps
CPU time 355.76 seconds
Started Jul 21 06:41:23 PM PDT 24
Finished Jul 21 06:47:20 PM PDT 24
Peak memory 218700 kb
Host smart-b533f6ba-2671-4bd6-bd4a-23897df719ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150059307 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.2150059307
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.576864636
Short name T220
Test name
Test status
Simulation time 51529569 ps
CPU time 1.34 seconds
Started Jul 21 06:42:58 PM PDT 24
Finished Jul 21 06:43:00 PM PDT 24
Peak memory 219988 kb
Host smart-9bfa11af-e788-4978-bb28-7f0cfabb7846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576864636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.576864636
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.3753529027
Short name T559
Test name
Test status
Simulation time 60934512 ps
CPU time 1.08 seconds
Started Jul 21 06:43:10 PM PDT 24
Finished Jul 21 06:43:11 PM PDT 24
Peak memory 220428 kb
Host smart-d85931fc-8949-4026-937a-46adec995911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753529027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.3753529027
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.3236255377
Short name T512
Test name
Test status
Simulation time 299384798 ps
CPU time 3.77 seconds
Started Jul 21 06:42:58 PM PDT 24
Finished Jul 21 06:43:03 PM PDT 24
Peak memory 220100 kb
Host smart-7ab4280e-20da-479d-8577-760d48a03b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236255377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.3236255377
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.1417177113
Short name T977
Test name
Test status
Simulation time 37776905 ps
CPU time 1.4 seconds
Started Jul 21 06:43:00 PM PDT 24
Finished Jul 21 06:43:03 PM PDT 24
Peak memory 218708 kb
Host smart-66dba531-820a-48fe-91f7-9423919e1c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417177113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.1417177113
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.2301471981
Short name T702
Test name
Test status
Simulation time 37840260 ps
CPU time 1.18 seconds
Started Jul 21 06:43:19 PM PDT 24
Finished Jul 21 06:43:21 PM PDT 24
Peak memory 217468 kb
Host smart-2fb25acc-e5a5-4e2e-9c0c-0cefdc6b1dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301471981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2301471981
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.3146635990
Short name T399
Test name
Test status
Simulation time 43334381 ps
CPU time 1.58 seconds
Started Jul 21 06:42:59 PM PDT 24
Finished Jul 21 06:43:03 PM PDT 24
Peak memory 220152 kb
Host smart-1539b5d1-8639-40e8-af43-21482491a6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146635990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3146635990
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.1422609519
Short name T10
Test name
Test status
Simulation time 118822353 ps
CPU time 1.3 seconds
Started Jul 21 06:43:02 PM PDT 24
Finished Jul 21 06:43:05 PM PDT 24
Peak memory 219940 kb
Host smart-82937acc-6066-41ed-8a9a-6df72b78bf20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422609519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.1422609519
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.3312716323
Short name T340
Test name
Test status
Simulation time 115245145 ps
CPU time 1.22 seconds
Started Jul 21 06:42:57 PM PDT 24
Finished Jul 21 06:42:59 PM PDT 24
Peak memory 220140 kb
Host smart-51dfa524-ce17-4889-ae97-589a02274a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312716323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.3312716323
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.4167843170
Short name T478
Test name
Test status
Simulation time 89026906 ps
CPU time 1.28 seconds
Started Jul 21 06:42:59 PM PDT 24
Finished Jul 21 06:43:02 PM PDT 24
Peak memory 218816 kb
Host smart-b3cc9cf3-80ad-4348-95a2-114c70b27576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167843170 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.4167843170
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.138740298
Short name T911
Test name
Test status
Simulation time 57793498 ps
CPU time 1.24 seconds
Started Jul 21 06:42:59 PM PDT 24
Finished Jul 21 06:43:02 PM PDT 24
Peak memory 217584 kb
Host smart-eed40126-40f0-4bf7-a4d7-68f81c444389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138740298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.138740298
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.108998657
Short name T618
Test name
Test status
Simulation time 26906844 ps
CPU time 1.19 seconds
Started Jul 21 06:41:24 PM PDT 24
Finished Jul 21 06:41:27 PM PDT 24
Peak memory 219724 kb
Host smart-5d656980-89f0-4123-8085-0dd02f6ebff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108998657 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.108998657
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.2007208525
Short name T679
Test name
Test status
Simulation time 48855187 ps
CPU time 0.88 seconds
Started Jul 21 06:41:25 PM PDT 24
Finished Jul 21 06:41:27 PM PDT 24
Peak memory 207048 kb
Host smart-6c675ffc-9a38-4829-aecb-5a46b98259a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007208525 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.2007208525
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.2281205407
Short name T852
Test name
Test status
Simulation time 21536976 ps
CPU time 0.89 seconds
Started Jul 21 06:41:25 PM PDT 24
Finished Jul 21 06:41:28 PM PDT 24
Peak memory 216452 kb
Host smart-9262e6b7-b025-45f1-9d11-639039ea5a35
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281205407 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2281205407
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.2632551711
Short name T495
Test name
Test status
Simulation time 86295807 ps
CPU time 1.1 seconds
Started Jul 21 06:41:27 PM PDT 24
Finished Jul 21 06:41:31 PM PDT 24
Peak memory 215908 kb
Host smart-47ff49c3-6049-4e47-9892-86de9ec369cf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632551711 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.2632551711
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.3138834135
Short name T52
Test name
Test status
Simulation time 31545644 ps
CPU time 1.14 seconds
Started Jul 21 06:41:25 PM PDT 24
Finished Jul 21 06:41:28 PM PDT 24
Peak memory 224296 kb
Host smart-f01ab8bc-1b94-49cb-b07c-2bb1e90547cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138834135 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.3138834135
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.4266631972
Short name T531
Test name
Test status
Simulation time 61146447 ps
CPU time 2.36 seconds
Started Jul 21 06:41:27 PM PDT 24
Finished Jul 21 06:41:33 PM PDT 24
Peak memory 218740 kb
Host smart-00b1fab4-3e57-409a-a1e9-9e60f418d43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266631972 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.4266631972
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.3720153945
Short name T640
Test name
Test status
Simulation time 22122797 ps
CPU time 0.99 seconds
Started Jul 21 06:41:25 PM PDT 24
Finished Jul 21 06:41:28 PM PDT 24
Peak memory 216224 kb
Host smart-80941681-09a6-4a3e-830b-bc9330c47cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720153945 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.3720153945
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.1435985606
Short name T994
Test name
Test status
Simulation time 15813645 ps
CPU time 0.99 seconds
Started Jul 21 06:41:24 PM PDT 24
Finished Jul 21 06:41:26 PM PDT 24
Peak memory 215620 kb
Host smart-6e8c39ad-0e79-4323-8f3e-e1f9a54646a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435985606 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.1435985606
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.2687548073
Short name T481
Test name
Test status
Simulation time 923419200 ps
CPU time 5.68 seconds
Started Jul 21 06:41:28 PM PDT 24
Finished Jul 21 06:41:36 PM PDT 24
Peak memory 217456 kb
Host smart-13ef3bb9-90c5-43ec-9356-01366f21a2a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687548073 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.2687548073
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.2586784423
Short name T963
Test name
Test status
Simulation time 13309680081 ps
CPU time 301.51 seconds
Started Jul 21 06:41:26 PM PDT 24
Finished Jul 21 06:46:31 PM PDT 24
Peak memory 223188 kb
Host smart-1d1b077b-af28-4f8d-9031-ed8912278c8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586784423 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.2586784423
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.206613117
Short name T965
Test name
Test status
Simulation time 71875901 ps
CPU time 1.11 seconds
Started Jul 21 06:42:59 PM PDT 24
Finished Jul 21 06:43:02 PM PDT 24
Peak memory 217652 kb
Host smart-aba7c500-f6b6-4ec8-a489-72e5b27d8b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206613117 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.206613117
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.2108460327
Short name T908
Test name
Test status
Simulation time 40936790 ps
CPU time 1.52 seconds
Started Jul 21 06:43:00 PM PDT 24
Finished Jul 21 06:43:03 PM PDT 24
Peak memory 220164 kb
Host smart-be9b7000-c417-435d-a557-412da9c439e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108460327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2108460327
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.1465188885
Short name T548
Test name
Test status
Simulation time 83166640 ps
CPU time 2.99 seconds
Started Jul 21 06:43:06 PM PDT 24
Finished Jul 21 06:43:10 PM PDT 24
Peak memory 220468 kb
Host smart-b1372aea-4c3a-48d9-86ec-bd7aa78c1e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465188885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.1465188885
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2932484356
Short name T1000
Test name
Test status
Simulation time 216496135 ps
CPU time 1.31 seconds
Started Jul 21 06:43:00 PM PDT 24
Finished Jul 21 06:43:03 PM PDT 24
Peak memory 220304 kb
Host smart-fd781f35-9fe0-455a-9343-8601b2a46c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932484356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2932484356
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3630004806
Short name T328
Test name
Test status
Simulation time 70768988 ps
CPU time 1.63 seconds
Started Jul 21 06:43:10 PM PDT 24
Finished Jul 21 06:43:12 PM PDT 24
Peak memory 218964 kb
Host smart-6f56688e-ae39-4adc-a4b9-9a58a8d4b523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630004806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3630004806
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.794405723
Short name T936
Test name
Test status
Simulation time 110358897 ps
CPU time 1.06 seconds
Started Jul 21 06:43:02 PM PDT 24
Finished Jul 21 06:43:04 PM PDT 24
Peak memory 217664 kb
Host smart-a507b032-722b-4af6-87a4-d8a35f432225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794405723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.794405723
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.547241126
Short name T748
Test name
Test status
Simulation time 24012078 ps
CPU time 1.13 seconds
Started Jul 21 06:43:02 PM PDT 24
Finished Jul 21 06:43:04 PM PDT 24
Peak memory 217796 kb
Host smart-ca984367-b5e0-4772-98a0-ad77c4e5224c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547241126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.547241126
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.1503292296
Short name T513
Test name
Test status
Simulation time 131751918 ps
CPU time 2.11 seconds
Started Jul 21 06:42:58 PM PDT 24
Finished Jul 21 06:43:02 PM PDT 24
Peak memory 220296 kb
Host smart-eb53e99b-3d33-4698-977d-fd6aeb922bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503292296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1503292296
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.344400529
Short name T303
Test name
Test status
Simulation time 65099724 ps
CPU time 1.08 seconds
Started Jul 21 06:42:58 PM PDT 24
Finished Jul 21 06:43:00 PM PDT 24
Peak memory 217728 kb
Host smart-08065462-1efd-4b97-b38e-5480accc3351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344400529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.344400529
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.2460663853
Short name T241
Test name
Test status
Simulation time 32692159 ps
CPU time 1.32 seconds
Started Jul 21 06:40:50 PM PDT 24
Finished Jul 21 06:40:54 PM PDT 24
Peak memory 219044 kb
Host smart-b50085ca-ac30-47b0-b210-7ff748a4079b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460663853 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.2460663853
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.4129143952
Short name T623
Test name
Test status
Simulation time 16483893 ps
CPU time 0.98 seconds
Started Jul 21 06:40:45 PM PDT 24
Finished Jul 21 06:40:47 PM PDT 24
Peak memory 207044 kb
Host smart-101a2c3f-4940-43b0-8ad7-f2e7ad9fcd79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129143952 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.4129143952
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.80126383
Short name T687
Test name
Test status
Simulation time 19064826 ps
CPU time 0.87 seconds
Started Jul 21 06:40:50 PM PDT 24
Finished Jul 21 06:40:52 PM PDT 24
Peak memory 216752 kb
Host smart-553d3b38-96d3-4442-8e5d-55bd82b79e11
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80126383 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.80126383
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.886065639
Short name T121
Test name
Test status
Simulation time 33228339 ps
CPU time 1.32 seconds
Started Jul 21 06:40:51 PM PDT 24
Finished Jul 21 06:40:55 PM PDT 24
Peak memory 217236 kb
Host smart-aebcb2ed-2d9f-4ccc-b8b4-414be29bc0f3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886065639 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_dis
able_auto_req_mode.886065639
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.3195681981
Short name T54
Test name
Test status
Simulation time 38633222 ps
CPU time 0.9 seconds
Started Jul 21 06:40:44 PM PDT 24
Finished Jul 21 06:40:45 PM PDT 24
Peak memory 224152 kb
Host smart-6c32fa6b-b88d-4d49-986c-f8bd581c652c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195681981 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.3195681981
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.3806895841
Short name T482
Test name
Test status
Simulation time 42121670 ps
CPU time 1.09 seconds
Started Jul 21 06:40:43 PM PDT 24
Finished Jul 21 06:40:45 PM PDT 24
Peak memory 217568 kb
Host smart-21371fb0-6c3c-4117-a1e2-a6cfbebfb165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806895841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.3806895841
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.494056403
Short name T634
Test name
Test status
Simulation time 28453880 ps
CPU time 0.97 seconds
Started Jul 21 06:40:55 PM PDT 24
Finished Jul 21 06:40:58 PM PDT 24
Peak memory 215676 kb
Host smart-dc874074-8686-4fd5-adfd-ff8799d7c36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494056403 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.494056403
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.1317065884
Short name T299
Test name
Test status
Simulation time 16644126 ps
CPU time 0.95 seconds
Started Jul 21 06:40:48 PM PDT 24
Finished Jul 21 06:40:50 PM PDT 24
Peak memory 207332 kb
Host smart-e14fe89d-714e-4fbf-8781-99086173c1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317065884 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1317065884
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.3376421139
Short name T56
Test name
Test status
Simulation time 295960629 ps
CPU time 4.79 seconds
Started Jul 21 06:40:48 PM PDT 24
Finished Jul 21 06:40:53 PM PDT 24
Peak memory 242316 kb
Host smart-8104079b-9d20-4d7b-b598-60abeabba470
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376421139 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.3376421139
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.2633048025
Short name T98
Test name
Test status
Simulation time 16464017 ps
CPU time 0.99 seconds
Started Jul 21 06:40:51 PM PDT 24
Finished Jul 21 06:40:54 PM PDT 24
Peak memory 215600 kb
Host smart-b7d6ffab-f904-47b5-8414-12d153a286cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633048025 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2633048025
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.4054483093
Short name T727
Test name
Test status
Simulation time 72187017 ps
CPU time 1.32 seconds
Started Jul 21 06:40:51 PM PDT 24
Finished Jul 21 06:40:55 PM PDT 24
Peak memory 218868 kb
Host smart-b34b0629-4c48-478c-a0dc-2f0444e577f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054483093 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.4054483093
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2083209948
Short name T382
Test name
Test status
Simulation time 166801118543 ps
CPU time 3310.53 seconds
Started Jul 21 06:40:47 PM PDT 24
Finished Jul 21 07:35:59 PM PDT 24
Peak memory 236696 kb
Host smart-24b5d823-85ea-4637-8dc6-63b9c2f4fe0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083209948 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.2083209948
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.1849967795
Short name T214
Test name
Test status
Simulation time 158217036 ps
CPU time 1.18 seconds
Started Jul 21 06:41:26 PM PDT 24
Finished Jul 21 06:41:30 PM PDT 24
Peak memory 219804 kb
Host smart-9a8f0d83-a844-46f0-8369-719f737a0200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849967795 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1849967795
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.3439746504
Short name T827
Test name
Test status
Simulation time 16004397 ps
CPU time 0.93 seconds
Started Jul 21 06:41:32 PM PDT 24
Finished Jul 21 06:41:34 PM PDT 24
Peak memory 215128 kb
Host smart-391fc0cd-ccd9-4fcc-b801-6b900b020095
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439746504 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3439746504
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.527005352
Short name T26
Test name
Test status
Simulation time 40950722 ps
CPU time 0.82 seconds
Started Jul 21 06:41:27 PM PDT 24
Finished Jul 21 06:41:30 PM PDT 24
Peak memory 215672 kb
Host smart-82a2e1b1-8855-48be-be96-ed3d80d53a7c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527005352 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.527005352
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.226708877
Short name T475
Test name
Test status
Simulation time 53189551 ps
CPU time 1.14 seconds
Started Jul 21 06:41:26 PM PDT 24
Finished Jul 21 06:41:31 PM PDT 24
Peak memory 218376 kb
Host smart-70461bb5-8710-41f8-91d3-8f05dcf842e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226708877 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_di
sable_auto_req_mode.226708877
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.41194009
Short name T166
Test name
Test status
Simulation time 19568283 ps
CPU time 1.09 seconds
Started Jul 21 06:41:25 PM PDT 24
Finished Jul 21 06:41:29 PM PDT 24
Peak memory 218884 kb
Host smart-318bcbb3-7752-4ba3-b131-8132fc89750a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41194009 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.41194009
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.1497311060
Short name T311
Test name
Test status
Simulation time 146591809 ps
CPU time 2.06 seconds
Started Jul 21 06:41:25 PM PDT 24
Finished Jul 21 06:41:30 PM PDT 24
Peak memory 219956 kb
Host smart-824412d1-1eee-488b-aabc-707c9a60b3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497311060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1497311060
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.2654853889
Short name T942
Test name
Test status
Simulation time 21542224 ps
CPU time 1.18 seconds
Started Jul 21 06:41:24 PM PDT 24
Finished Jul 21 06:41:27 PM PDT 24
Peak memory 224304 kb
Host smart-b84451e4-443b-4019-b4ec-0b66ec418133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654853889 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2654853889
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.394796670
Short name T492
Test name
Test status
Simulation time 38661354 ps
CPU time 0.9 seconds
Started Jul 21 06:41:28 PM PDT 24
Finished Jul 21 06:41:32 PM PDT 24
Peak memory 215492 kb
Host smart-84b04652-5b74-435c-8747-0e0edab29331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394796670 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.394796670
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.136792010
Short name T629
Test name
Test status
Simulation time 356989918 ps
CPU time 6.83 seconds
Started Jul 21 06:41:24 PM PDT 24
Finished Jul 21 06:41:32 PM PDT 24
Peak memory 215516 kb
Host smart-cdd54de7-7286-4c7f-88e5-568274b9c3ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136792010 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.136792010
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.1122420754
Short name T697
Test name
Test status
Simulation time 209424612733 ps
CPU time 3396.79 seconds
Started Jul 21 06:41:25 PM PDT 24
Finished Jul 21 07:38:05 PM PDT 24
Peak memory 233272 kb
Host smart-fa5b17e5-b59e-4e4c-bd07-02d16b3cb6a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122420754 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.1122420754
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.1035972081
Short name T473
Test name
Test status
Simulation time 40327914 ps
CPU time 1.11 seconds
Started Jul 21 06:41:29 PM PDT 24
Finished Jul 21 06:41:33 PM PDT 24
Peak memory 221072 kb
Host smart-e9e2c229-8496-47ee-beb1-73ec3da84919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035972081 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1035972081
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.2938314501
Short name T986
Test name
Test status
Simulation time 38578769 ps
CPU time 1.01 seconds
Started Jul 21 06:41:26 PM PDT 24
Finished Jul 21 06:41:30 PM PDT 24
Peak memory 207096 kb
Host smart-fe5064a6-930c-4211-ac56-3eaa23afd947
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938314501 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.2938314501
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.4045322340
Short name T198
Test name
Test status
Simulation time 47318977 ps
CPU time 0.82 seconds
Started Jul 21 06:41:26 PM PDT 24
Finished Jul 21 06:41:30 PM PDT 24
Peak memory 216460 kb
Host smart-366fe803-0c9e-41b8-9e90-69975b0eac5b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045322340 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.4045322340
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.753340356
Short name T116
Test name
Test status
Simulation time 454442819 ps
CPU time 1.03 seconds
Started Jul 21 06:41:26 PM PDT 24
Finished Jul 21 06:41:29 PM PDT 24
Peak memory 217156 kb
Host smart-3a7d34f4-ebd1-4bc0-8555-70e6ba5813b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753340356 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_di
sable_auto_req_mode.753340356
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.3347428801
Short name T976
Test name
Test status
Simulation time 54900138 ps
CPU time 1.09 seconds
Started Jul 21 06:41:27 PM PDT 24
Finished Jul 21 06:41:31 PM PDT 24
Peak memory 220228 kb
Host smart-222680d2-07f1-445a-b774-26ba9bde704c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347428801 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.3347428801
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.2701713150
Short name T844
Test name
Test status
Simulation time 49570850 ps
CPU time 1.68 seconds
Started Jul 21 06:41:27 PM PDT 24
Finished Jul 21 06:41:32 PM PDT 24
Peak memory 218856 kb
Host smart-4f795fb0-cf7a-4f76-afde-b7b01a5d797a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701713150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.2701713150
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.461134333
Short name T846
Test name
Test status
Simulation time 20272610 ps
CPU time 1.12 seconds
Started Jul 21 06:41:28 PM PDT 24
Finished Jul 21 06:41:32 PM PDT 24
Peak memory 215780 kb
Host smart-e2f96a07-6e65-4d71-a297-d3ff69bd514f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461134333 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.461134333
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.1294327070
Short name T813
Test name
Test status
Simulation time 18513600 ps
CPU time 1.03 seconds
Started Jul 21 06:41:27 PM PDT 24
Finished Jul 21 06:41:32 PM PDT 24
Peak memory 215508 kb
Host smart-3ffb36a6-6372-4f9e-9dd0-ba071b4514d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294327070 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.1294327070
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.3760638610
Short name T563
Test name
Test status
Simulation time 270597227 ps
CPU time 5.25 seconds
Started Jul 21 06:41:25 PM PDT 24
Finished Jul 21 06:41:33 PM PDT 24
Peak memory 217504 kb
Host smart-6711a1d7-9cba-4a92-84f4-a1b5f0eba6fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760638610 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.3760638610
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.1769291902
Short name T228
Test name
Test status
Simulation time 41379454422 ps
CPU time 889.51 seconds
Started Jul 21 06:41:27 PM PDT 24
Finished Jul 21 06:56:19 PM PDT 24
Peak memory 219072 kb
Host smart-407d75eb-8c41-462c-8fc0-9e11760c700d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769291902 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.1769291902
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.2838684690
Short name T849
Test name
Test status
Simulation time 40468586 ps
CPU time 1.09 seconds
Started Jul 21 06:41:27 PM PDT 24
Finished Jul 21 06:41:31 PM PDT 24
Peak memory 221076 kb
Host smart-6eebd714-ae3c-461e-a34d-1aecafd7a3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838684690 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.2838684690
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.2838149179
Short name T969
Test name
Test status
Simulation time 61771675 ps
CPU time 1.01 seconds
Started Jul 21 06:41:26 PM PDT 24
Finished Jul 21 06:41:29 PM PDT 24
Peak memory 207200 kb
Host smart-d58c24ea-318e-41b1-9a38-a29197e7885e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838149179 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.2838149179
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.393502146
Short name T625
Test name
Test status
Simulation time 27823382 ps
CPU time 0.82 seconds
Started Jul 21 06:41:26 PM PDT 24
Finished Jul 21 06:41:29 PM PDT 24
Peak memory 216252 kb
Host smart-337dcbab-05dc-4823-b198-d0fabcd4faff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393502146 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.393502146
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_err.1974760303
Short name T731
Test name
Test status
Simulation time 24955994 ps
CPU time 1.35 seconds
Started Jul 21 06:41:26 PM PDT 24
Finished Jul 21 06:41:30 PM PDT 24
Peak memory 229896 kb
Host smart-16b2de51-a76b-43cb-8b2d-4399ce0bc97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974760303 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.1974760303
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.3094643086
Short name T715
Test name
Test status
Simulation time 69061974 ps
CPU time 1.17 seconds
Started Jul 21 06:41:23 PM PDT 24
Finished Jul 21 06:41:26 PM PDT 24
Peak memory 217632 kb
Host smart-f0a04245-8205-47b4-b942-c8ad74cd6366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094643086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3094643086
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.1650616097
Short name T552
Test name
Test status
Simulation time 22312598 ps
CPU time 1.11 seconds
Started Jul 21 06:41:27 PM PDT 24
Finished Jul 21 06:41:31 PM PDT 24
Peak memory 215760 kb
Host smart-0ed121e1-d4c3-446c-995d-59948bc2be8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650616097 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.1650616097
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.1902430051
Short name T518
Test name
Test status
Simulation time 57026713 ps
CPU time 0.96 seconds
Started Jul 21 06:41:26 PM PDT 24
Finished Jul 21 06:41:30 PM PDT 24
Peak memory 215588 kb
Host smart-a2d30b56-ae03-465e-8a63-e23a397b59d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902430051 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.1902430051
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.2895804488
Short name T609
Test name
Test status
Simulation time 413035628 ps
CPU time 4.72 seconds
Started Jul 21 06:41:27 PM PDT 24
Finished Jul 21 06:41:34 PM PDT 24
Peak memory 217440 kb
Host smart-8daaa30b-cffb-43c1-a2b2-1c513360f382
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895804488 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.2895804488
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1253498927
Short name T229
Test name
Test status
Simulation time 143915819538 ps
CPU time 823.19 seconds
Started Jul 21 06:41:27 PM PDT 24
Finished Jul 21 06:55:13 PM PDT 24
Peak memory 221740 kb
Host smart-1990ca12-a3e1-4cbb-9df7-48f825d24404
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253498927 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1253498927
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.776782980
Short name T800
Test name
Test status
Simulation time 44048542 ps
CPU time 1.15 seconds
Started Jul 21 06:41:28 PM PDT 24
Finished Jul 21 06:41:32 PM PDT 24
Peak memory 220588 kb
Host smart-d556f170-45ee-41fc-aa50-15a4c3268024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776782980 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.776782980
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.2542672489
Short name T390
Test name
Test status
Simulation time 13418755 ps
CPU time 0.86 seconds
Started Jul 21 06:41:34 PM PDT 24
Finished Jul 21 06:41:37 PM PDT 24
Peak memory 207248 kb
Host smart-2b7af082-b873-42ca-bf16-20bd29e87380
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542672489 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2542672489
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.468757871
Short name T208
Test name
Test status
Simulation time 41721027 ps
CPU time 0.86 seconds
Started Jul 21 06:41:31 PM PDT 24
Finished Jul 21 06:41:34 PM PDT 24
Peak memory 216576 kb
Host smart-f9b136cf-b079-4d50-8403-5f8b24e12915
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468757871 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.468757871
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.3264088163
Short name T737
Test name
Test status
Simulation time 61450395 ps
CPU time 1.24 seconds
Started Jul 21 06:41:47 PM PDT 24
Finished Jul 21 06:41:48 PM PDT 24
Peak memory 217152 kb
Host smart-db633f26-0a25-46d3-987d-aa15d1dfd1a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264088163 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.3264088163
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.494004664
Short name T461
Test name
Test status
Simulation time 19497014 ps
CPU time 1.15 seconds
Started Jul 21 06:41:27 PM PDT 24
Finished Jul 21 06:41:31 PM PDT 24
Peak memory 224284 kb
Host smart-c75e54dc-8b18-46f4-ab44-d5bb7231f646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494004664 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.494004664
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.2664570352
Short name T410
Test name
Test status
Simulation time 23905915 ps
CPU time 1.18 seconds
Started Jul 21 06:41:24 PM PDT 24
Finished Jul 21 06:41:33 PM PDT 24
Peak memory 218828 kb
Host smart-1b760930-8957-4d82-82db-a36baee9de59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664570352 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2664570352
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.3635267494
Short name T37
Test name
Test status
Simulation time 32890552 ps
CPU time 0.85 seconds
Started Jul 21 06:41:28 PM PDT 24
Finished Jul 21 06:41:32 PM PDT 24
Peak memory 215944 kb
Host smart-d76aea8d-3439-4ab4-9562-b0585240a84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635267494 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.3635267494
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.1874433878
Short name T470
Test name
Test status
Simulation time 46973087 ps
CPU time 0.93 seconds
Started Jul 21 06:41:23 PM PDT 24
Finished Jul 21 06:41:26 PM PDT 24
Peak memory 215584 kb
Host smart-4f12c494-5d10-4ab4-af87-078e70323b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874433878 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.1874433878
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3788501142
Short name T614
Test name
Test status
Simulation time 67144647 ps
CPU time 1.26 seconds
Started Jul 21 06:41:28 PM PDT 24
Finished Jul 21 06:41:32 PM PDT 24
Peak memory 215528 kb
Host smart-54e5187b-273f-4ba9-8ee1-1bc40ab68670
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788501142 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3788501142
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.1505147434
Short name T705
Test name
Test status
Simulation time 1453425387350 ps
CPU time 1973.01 seconds
Started Jul 21 06:41:26 PM PDT 24
Finished Jul 21 07:14:22 PM PDT 24
Peak memory 228516 kb
Host smart-5103c439-fcca-4186-8c0f-6718f1483697
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505147434 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.1505147434
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.960579489
Short name T397
Test name
Test status
Simulation time 287054736 ps
CPU time 1.32 seconds
Started Jul 21 06:41:30 PM PDT 24
Finished Jul 21 06:41:34 PM PDT 24
Peak memory 219020 kb
Host smart-8520aec9-4a6d-4050-8f9c-51d9a5a2d1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960579489 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.960579489
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.1352286621
Short name T363
Test name
Test status
Simulation time 46553080 ps
CPU time 1.03 seconds
Started Jul 21 06:41:34 PM PDT 24
Finished Jul 21 06:41:37 PM PDT 24
Peak memory 207000 kb
Host smart-a956cc02-cdae-4de1-a40e-b6110895e03c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352286621 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1352286621
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.1451375974
Short name T577
Test name
Test status
Simulation time 47913202 ps
CPU time 0.87 seconds
Started Jul 21 06:41:32 PM PDT 24
Finished Jul 21 06:41:35 PM PDT 24
Peak memory 216464 kb
Host smart-94dda248-f7ac-477b-b13c-2789ef93012e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451375974 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1451375974
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_err.405768902
Short name T944
Test name
Test status
Simulation time 28710496 ps
CPU time 1.21 seconds
Started Jul 21 06:41:38 PM PDT 24
Finished Jul 21 06:41:40 PM PDT 24
Peak memory 219812 kb
Host smart-e7dfb6a2-4a1c-4b21-a54e-184ade4d38f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405768902 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.405768902
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.378327189
Short name T575
Test name
Test status
Simulation time 28230926 ps
CPU time 1.16 seconds
Started Jul 21 06:41:29 PM PDT 24
Finished Jul 21 06:41:33 PM PDT 24
Peak memory 217604 kb
Host smart-145c88c0-25c9-49d4-be25-c3b4e015e3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378327189 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.378327189
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.3427703657
Short name T999
Test name
Test status
Simulation time 20883316 ps
CPU time 1.09 seconds
Started Jul 21 06:41:33 PM PDT 24
Finished Jul 21 06:41:36 PM PDT 24
Peak memory 216144 kb
Host smart-b0c57e32-ecf8-4c70-b26c-f71d1aaadd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427703657 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.3427703657
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.2865345599
Short name T909
Test name
Test status
Simulation time 17178392 ps
CPU time 0.97 seconds
Started Jul 21 06:41:34 PM PDT 24
Finished Jul 21 06:41:36 PM PDT 24
Peak memory 215548 kb
Host smart-716eb4ec-c480-46d3-8a02-962d3fcb6f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865345599 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.2865345599
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.2260529292
Short name T941
Test name
Test status
Simulation time 112643414 ps
CPU time 1.13 seconds
Started Jul 21 06:41:31 PM PDT 24
Finished Jul 21 06:41:34 PM PDT 24
Peak memory 215500 kb
Host smart-b5e8585c-e84a-48d1-94dc-328e9a50bf89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260529292 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.2260529292
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.328554139
Short name T230
Test name
Test status
Simulation time 39489740915 ps
CPU time 533.71 seconds
Started Jul 21 06:41:31 PM PDT 24
Finished Jul 21 06:50:27 PM PDT 24
Peak memory 223960 kb
Host smart-9e9ca44d-e7f9-4fca-ba41-33926e062e48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328554139 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.328554139
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.3377634907
Short name T581
Test name
Test status
Simulation time 303600605 ps
CPU time 1.47 seconds
Started Jul 21 06:41:34 PM PDT 24
Finished Jul 21 06:41:37 PM PDT 24
Peak memory 219996 kb
Host smart-b58993eb-9561-41c6-a60d-a36e936e748c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377634907 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.3377634907
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.2155802608
Short name T347
Test name
Test status
Simulation time 249768992 ps
CPU time 0.99 seconds
Started Jul 21 06:41:30 PM PDT 24
Finished Jul 21 06:41:33 PM PDT 24
Peak memory 207148 kb
Host smart-6efe9e75-8cd6-48f4-a456-a0cc2398241b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155802608 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.2155802608
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.3453945538
Short name T157
Test name
Test status
Simulation time 12486258 ps
CPU time 0.9 seconds
Started Jul 21 06:41:47 PM PDT 24
Finished Jul 21 06:41:49 PM PDT 24
Peak memory 215900 kb
Host smart-fa69d7e9-7c49-49aa-8303-b4e11669a41f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453945538 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.3453945538
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.491432174
Short name T971
Test name
Test status
Simulation time 28231172 ps
CPU time 1.08 seconds
Started Jul 21 06:41:34 PM PDT 24
Finished Jul 21 06:41:37 PM PDT 24
Peak memory 217064 kb
Host smart-e4ea1118-eba5-41a8-86cc-4091ed4d9b27
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491432174 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_di
sable_auto_req_mode.491432174
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.180416532
Short name T893
Test name
Test status
Simulation time 30771262 ps
CPU time 1.3 seconds
Started Jul 21 06:41:34 PM PDT 24
Finished Jul 21 06:41:37 PM PDT 24
Peak memory 219928 kb
Host smart-1dcb3646-1792-4a97-816f-8ce4c2e0e855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180416532 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.180416532
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.445133993
Short name T716
Test name
Test status
Simulation time 124230510 ps
CPU time 1.05 seconds
Started Jul 21 06:41:30 PM PDT 24
Finished Jul 21 06:41:33 PM PDT 24
Peak memory 217528 kb
Host smart-2f802bde-dffb-4d87-b238-bf30d9796120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445133993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.445133993
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.2479354403
Short name T622
Test name
Test status
Simulation time 37652594 ps
CPU time 0.88 seconds
Started Jul 21 06:41:48 PM PDT 24
Finished Jul 21 06:41:50 PM PDT 24
Peak memory 215776 kb
Host smart-4b7f0729-0fcd-4843-8ef5-39ec4e6b3704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479354403 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.2479354403
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.741383148
Short name T704
Test name
Test status
Simulation time 33216070 ps
CPU time 0.89 seconds
Started Jul 21 06:41:32 PM PDT 24
Finished Jul 21 06:41:35 PM PDT 24
Peak memory 215556 kb
Host smart-acd8b430-f9da-47b7-aa17-a8b93bc2adfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741383148 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.741383148
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.2560406309
Short name T506
Test name
Test status
Simulation time 696016541 ps
CPU time 4.65 seconds
Started Jul 21 06:41:44 PM PDT 24
Finished Jul 21 06:41:50 PM PDT 24
Peak memory 217748 kb
Host smart-5aa6edc5-a70d-4f42-81d6-219189d9feae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560406309 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2560406309
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.4285781634
Short name T934
Test name
Test status
Simulation time 65117144058 ps
CPU time 756.31 seconds
Started Jul 21 06:41:30 PM PDT 24
Finished Jul 21 06:54:13 PM PDT 24
Peak memory 224036 kb
Host smart-d6734be9-3b41-4d60-8a61-77aafb675f00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285781634 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.4285781634
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert_test.3463870985
Short name T918
Test name
Test status
Simulation time 40602349 ps
CPU time 1.03 seconds
Started Jul 21 06:41:33 PM PDT 24
Finished Jul 21 06:41:35 PM PDT 24
Peak memory 206984 kb
Host smart-b5d55dab-2773-44a8-a356-89c0b457f843
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463870985 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3463870985
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.2809306689
Short name T869
Test name
Test status
Simulation time 13311028 ps
CPU time 0.95 seconds
Started Jul 21 06:41:33 PM PDT 24
Finished Jul 21 06:41:36 PM PDT 24
Peak memory 216832 kb
Host smart-d8c431d2-80b9-486e-a7cf-b88ea06c1cdb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809306689 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2809306689
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.2022499278
Short name T216
Test name
Test status
Simulation time 78130248 ps
CPU time 1.08 seconds
Started Jul 21 06:41:28 PM PDT 24
Finished Jul 21 06:41:32 PM PDT 24
Peak memory 219940 kb
Host smart-f7a974ac-7170-41ba-b84b-f6de77f13585
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022499278 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.2022499278
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.704119363
Short name T199
Test name
Test status
Simulation time 24918507 ps
CPU time 0.97 seconds
Started Jul 21 06:41:34 PM PDT 24
Finished Jul 21 06:41:37 PM PDT 24
Peak memory 219812 kb
Host smart-13d49785-b0d8-416d-93cb-dc770ca0ae6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704119363 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.704119363
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.4242494757
Short name T873
Test name
Test status
Simulation time 29849588 ps
CPU time 1.42 seconds
Started Jul 21 06:41:32 PM PDT 24
Finished Jul 21 06:41:36 PM PDT 24
Peak memory 217700 kb
Host smart-218de3c6-1019-4937-b798-8149db49e08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242494757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.4242494757
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.1894341502
Short name T603
Test name
Test status
Simulation time 27200155 ps
CPU time 0.97 seconds
Started Jul 21 06:41:30 PM PDT 24
Finished Jul 21 06:41:34 PM PDT 24
Peak memory 215896 kb
Host smart-63d4230b-9b86-42b2-b6e8-e42f4fe69c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894341502 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.1894341502
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.4279263334
Short name T401
Test name
Test status
Simulation time 51496311 ps
CPU time 0.94 seconds
Started Jul 21 06:41:32 PM PDT 24
Finished Jul 21 06:41:35 PM PDT 24
Peak memory 215548 kb
Host smart-b2c612c0-5876-40d2-83fd-24a346fc5247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279263334 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.4279263334
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.133005377
Short name T23
Test name
Test status
Simulation time 76657539 ps
CPU time 1.05 seconds
Started Jul 21 06:41:30 PM PDT 24
Finished Jul 21 06:41:33 PM PDT 24
Peak memory 215540 kb
Host smart-01451350-60ef-467a-b238-3aa8d50d61a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133005377 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.133005377
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.216910942
Short name T68
Test name
Test status
Simulation time 62537036660 ps
CPU time 343.2 seconds
Started Jul 21 06:41:38 PM PDT 24
Finished Jul 21 06:47:22 PM PDT 24
Peak memory 219440 kb
Host smart-f6573812-79ba-44b1-8045-d46d947d05b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216910942 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.216910942
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.3851612858
Short name T375
Test name
Test status
Simulation time 65129945 ps
CPU time 1.16 seconds
Started Jul 21 06:41:30 PM PDT 24
Finished Jul 21 06:41:34 PM PDT 24
Peak memory 219020 kb
Host smart-54d4b473-8181-496c-a41a-62925d7b401f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851612858 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3851612858
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.3420534562
Short name T922
Test name
Test status
Simulation time 19823564 ps
CPU time 1.05 seconds
Started Jul 21 06:41:34 PM PDT 24
Finished Jul 21 06:41:37 PM PDT 24
Peak memory 215432 kb
Host smart-61b6244e-5f94-4819-9cac-c56567886641
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420534562 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.3420534562
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.4293052941
Short name T175
Test name
Test status
Simulation time 10282098 ps
CPU time 0.85 seconds
Started Jul 21 06:41:32 PM PDT 24
Finished Jul 21 06:41:35 PM PDT 24
Peak memory 216568 kb
Host smart-ece345f4-03bc-4b36-b985-61e6997ea6a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293052941 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.4293052941
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.4222252338
Short name T717
Test name
Test status
Simulation time 40345717 ps
CPU time 1.14 seconds
Started Jul 21 06:41:32 PM PDT 24
Finished Jul 21 06:41:35 PM PDT 24
Peak memory 218564 kb
Host smart-6fd0f0e4-4132-4e5b-812c-90bc61809027
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222252338 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.4222252338
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.3788079393
Short name T14
Test name
Test status
Simulation time 32849332 ps
CPU time 0.98 seconds
Started Jul 21 06:41:31 PM PDT 24
Finished Jul 21 06:41:34 PM PDT 24
Peak memory 224136 kb
Host smart-70a2383f-f7a2-440f-a2ec-0b5d79a297d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788079393 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.3788079393
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.459499645
Short name T595
Test name
Test status
Simulation time 114620102 ps
CPU time 1.14 seconds
Started Jul 21 06:41:37 PM PDT 24
Finished Jul 21 06:41:39 PM PDT 24
Peak memory 217412 kb
Host smart-24d8f1c9-143c-4f6f-9729-c18027ba082b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459499645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.459499645
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.3235730079
Short name T71
Test name
Test status
Simulation time 37697485 ps
CPU time 0.89 seconds
Started Jul 21 06:41:32 PM PDT 24
Finished Jul 21 06:41:35 PM PDT 24
Peak memory 215856 kb
Host smart-33fb1d36-d5e7-4822-822f-30e8955c9b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235730079 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.3235730079
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.2002446696
Short name T889
Test name
Test status
Simulation time 49954689 ps
CPU time 0.92 seconds
Started Jul 21 06:41:32 PM PDT 24
Finished Jul 21 06:41:35 PM PDT 24
Peak memory 215532 kb
Host smart-4d2964a4-2258-46b3-9226-57a9b02390b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002446696 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.2002446696
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.266220039
Short name T829
Test name
Test status
Simulation time 575002875 ps
CPU time 5.04 seconds
Started Jul 21 06:41:34 PM PDT 24
Finished Jul 21 06:41:41 PM PDT 24
Peak memory 220152 kb
Host smart-ca4e3925-e818-4660-a2e9-aa83d4c42e1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266220039 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.266220039
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.2425702181
Short name T759
Test name
Test status
Simulation time 82333783205 ps
CPU time 2067.18 seconds
Started Jul 21 06:41:47 PM PDT 24
Finished Jul 21 07:16:15 PM PDT 24
Peak memory 230404 kb
Host smart-aae3d6ca-58a0-463c-b5af-10e1305eb00a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425702181 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.2425702181
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.3898747785
Short name T636
Test name
Test status
Simulation time 35457842 ps
CPU time 1.16 seconds
Started Jul 21 06:41:37 PM PDT 24
Finished Jul 21 06:41:39 PM PDT 24
Peak memory 219868 kb
Host smart-84595ddd-6d3e-4849-8348-da1f8bf84744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898747785 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3898747785
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.2561242793
Short name T541
Test name
Test status
Simulation time 12989416 ps
CPU time 0.89 seconds
Started Jul 21 06:41:36 PM PDT 24
Finished Jul 21 06:41:38 PM PDT 24
Peak memory 207016 kb
Host smart-f53ef11c-ba77-4e73-99ed-775946f9ded5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561242793 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.2561242793
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.1931235711
Short name T170
Test name
Test status
Simulation time 33580216 ps
CPU time 0.89 seconds
Started Jul 21 06:41:46 PM PDT 24
Finished Jul 21 06:41:47 PM PDT 24
Peak memory 216432 kb
Host smart-ddfaedfd-ef76-45cb-860d-705735e0b207
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931235711 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.1931235711
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_err.2565252576
Short name T201
Test name
Test status
Simulation time 38417207 ps
CPU time 1.14 seconds
Started Jul 21 06:41:50 PM PDT 24
Finished Jul 21 06:41:52 PM PDT 24
Peak memory 218072 kb
Host smart-c278479d-2c90-41e1-9713-7de4f4f48445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565252576 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.2565252576
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.3899374365
Short name T895
Test name
Test status
Simulation time 52503497 ps
CPU time 1.51 seconds
Started Jul 21 06:41:39 PM PDT 24
Finished Jul 21 06:41:41 PM PDT 24
Peak memory 219096 kb
Host smart-cccf4d5c-745d-491c-adb6-56e07aed6a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899374365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.3899374365
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.910901441
Short name T514
Test name
Test status
Simulation time 26015896 ps
CPU time 0.96 seconds
Started Jul 21 06:41:37 PM PDT 24
Finished Jul 21 06:41:39 PM PDT 24
Peak memory 215740 kb
Host smart-8bb0d94b-8f09-4f8a-a869-b4f1a96db798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910901441 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.910901441
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.3155734268
Short name T362
Test name
Test status
Simulation time 165725870 ps
CPU time 0.92 seconds
Started Jul 21 06:41:34 PM PDT 24
Finished Jul 21 06:41:37 PM PDT 24
Peak memory 215544 kb
Host smart-479830a6-9138-48c8-a143-514db86e1595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155734268 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.3155734268
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.2847538866
Short name T48
Test name
Test status
Simulation time 224260354 ps
CPU time 4.53 seconds
Started Jul 21 06:41:35 PM PDT 24
Finished Jul 21 06:41:41 PM PDT 24
Peak memory 218680 kb
Host smart-d5420212-e593-49fb-abd8-27f71b1cca4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847538866 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.2847538866
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.3338603247
Short name T913
Test name
Test status
Simulation time 200851487245 ps
CPU time 1174.71 seconds
Started Jul 21 06:41:37 PM PDT 24
Finished Jul 21 07:01:13 PM PDT 24
Peak memory 222160 kb
Host smart-891cbb2f-5ad8-4b2b-af74-9cb50285da44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338603247 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.3338603247
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2987020585
Short name T743
Test name
Test status
Simulation time 28124350 ps
CPU time 1.29 seconds
Started Jul 21 06:41:46 PM PDT 24
Finished Jul 21 06:41:48 PM PDT 24
Peak memory 220196 kb
Host smart-644f3d46-2144-44e4-b566-2f00ce04eed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987020585 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2987020585
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.731984064
Short name T47
Test name
Test status
Simulation time 38726966 ps
CPU time 0.95 seconds
Started Jul 21 06:41:37 PM PDT 24
Finished Jul 21 06:41:39 PM PDT 24
Peak memory 215276 kb
Host smart-8865fabf-3af1-4a82-8c1f-8cd9b6e58ba4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731984064 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.731984064
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.3580215561
Short name T555
Test name
Test status
Simulation time 39909581 ps
CPU time 0.85 seconds
Started Jul 21 06:41:45 PM PDT 24
Finished Jul 21 06:41:46 PM PDT 24
Peak memory 216104 kb
Host smart-e2fe8501-c466-4b4c-9eee-92ba376d7681
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580215561 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.3580215561
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_err.3568659243
Short name T133
Test name
Test status
Simulation time 26813077 ps
CPU time 0.96 seconds
Started Jul 21 06:41:43 PM PDT 24
Finished Jul 21 06:41:44 PM PDT 24
Peak memory 220156 kb
Host smart-6059fd58-d27b-44e0-83b8-40c1347fb95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568659243 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3568659243
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.1488836326
Short name T766
Test name
Test status
Simulation time 32304296 ps
CPU time 1.31 seconds
Started Jul 21 06:41:52 PM PDT 24
Finished Jul 21 06:41:55 PM PDT 24
Peak memory 218884 kb
Host smart-b85af6e8-2c5b-4aeb-b53c-5281de98d0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488836326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1488836326
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.3700901023
Short name T418
Test name
Test status
Simulation time 27116200 ps
CPU time 0.98 seconds
Started Jul 21 06:41:55 PM PDT 24
Finished Jul 21 06:41:58 PM PDT 24
Peak memory 215776 kb
Host smart-80eaf4aa-d49d-4e5f-b702-aaa39737a686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700901023 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.3700901023
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.3392846573
Short name T736
Test name
Test status
Simulation time 16012086 ps
CPU time 1.01 seconds
Started Jul 21 06:41:41 PM PDT 24
Finished Jul 21 06:41:42 PM PDT 24
Peak memory 215552 kb
Host smart-068bd03f-1127-4830-bdfd-518afe86bb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392846573 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.3392846573
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.3906718361
Short name T671
Test name
Test status
Simulation time 819232921 ps
CPU time 5.19 seconds
Started Jul 21 06:41:43 PM PDT 24
Finished Jul 21 06:41:48 PM PDT 24
Peak memory 217256 kb
Host smart-1416c75d-2242-4c15-84c3-346733e2ce52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906718361 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3906718361
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.1101606594
Short name T420
Test name
Test status
Simulation time 115479232413 ps
CPU time 1473.68 seconds
Started Jul 21 06:41:37 PM PDT 24
Finished Jul 21 07:06:12 PM PDT 24
Peak memory 233768 kb
Host smart-4f6e50c1-032b-4f23-8790-e248c6ca61b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101606594 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.1101606594
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.93874198
Short name T619
Test name
Test status
Simulation time 23725599 ps
CPU time 1.17 seconds
Started Jul 21 06:40:50 PM PDT 24
Finished Jul 21 06:40:53 PM PDT 24
Peak memory 218744 kb
Host smart-253b59e4-6c40-4ab9-99e1-6e1e3943adf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93874198 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.93874198
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.2660004778
Short name T532
Test name
Test status
Simulation time 39860140 ps
CPU time 0.98 seconds
Started Jul 21 06:40:49 PM PDT 24
Finished Jul 21 06:40:51 PM PDT 24
Peak memory 207072 kb
Host smart-a0bcfa1c-6052-4aea-9635-c69da4d48d32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660004778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2660004778
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.2303121400
Short name T202
Test name
Test status
Simulation time 12335839 ps
CPU time 0.89 seconds
Started Jul 21 06:40:44 PM PDT 24
Finished Jul 21 06:40:46 PM PDT 24
Peak memory 216480 kb
Host smart-5a0ea98f-8e88-4242-9fd0-bc852cff3b5e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303121400 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.2303121400
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.82167325
Short name T123
Test name
Test status
Simulation time 26338111 ps
CPU time 1.2 seconds
Started Jul 21 06:40:49 PM PDT 24
Finished Jul 21 06:40:52 PM PDT 24
Peak memory 217136 kb
Host smart-33c6d1f1-eed5-45b1-8b8e-531d3a60ce0a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82167325 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disa
ble_auto_req_mode.82167325
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.703760084
Short name T168
Test name
Test status
Simulation time 24175709 ps
CPU time 0.92 seconds
Started Jul 21 06:40:44 PM PDT 24
Finished Jul 21 06:40:45 PM PDT 24
Peak memory 218788 kb
Host smart-c628efc2-bdb4-4679-8474-5c7f68f7ef4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703760084 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.703760084
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.438214118
Short name T441
Test name
Test status
Simulation time 123496331 ps
CPU time 1.13 seconds
Started Jul 21 06:40:48 PM PDT 24
Finished Jul 21 06:40:50 PM PDT 24
Peak memory 217612 kb
Host smart-624b6d66-e296-4e07-bb7e-afc3b4964d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438214118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.438214118
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.363395830
Short name T663
Test name
Test status
Simulation time 63223680 ps
CPU time 0.88 seconds
Started Jul 21 06:40:45 PM PDT 24
Finished Jul 21 06:40:47 PM PDT 24
Peak memory 215776 kb
Host smart-33bcc20c-d8bf-468b-881f-4d6b93b81cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363395830 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.363395830
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.894391353
Short name T21
Test name
Test status
Simulation time 16734458 ps
CPU time 0.95 seconds
Started Jul 21 06:40:44 PM PDT 24
Finished Jul 21 06:40:45 PM PDT 24
Peak memory 207408 kb
Host smart-e4943a13-ad9c-474f-8473-62472ad7915d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894391353 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.894391353
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_smoke.2579794229
Short name T22
Test name
Test status
Simulation time 26675580 ps
CPU time 0.94 seconds
Started Jul 21 06:40:47 PM PDT 24
Finished Jul 21 06:40:49 PM PDT 24
Peak memory 215532 kb
Host smart-79b0f376-5c48-45dd-b815-dc90a570803f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579794229 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.2579794229
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1003820909
Short name T796
Test name
Test status
Simulation time 539938048 ps
CPU time 5.24 seconds
Started Jul 21 06:40:47 PM PDT 24
Finished Jul 21 06:40:54 PM PDT 24
Peak memory 217496 kb
Host smart-792417f7-6eda-48eb-be8b-bbcd68de3321
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003820909 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1003820909
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2794724817
Short name T788
Test name
Test status
Simulation time 446175206289 ps
CPU time 1116.44 seconds
Started Jul 21 06:40:49 PM PDT 24
Finished Jul 21 06:59:26 PM PDT 24
Peak memory 231752 kb
Host smart-4f665ac6-b42e-4277-b1b0-786c1461ba63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794724817 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.2794724817
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.866675191
Short name T920
Test name
Test status
Simulation time 36562075 ps
CPU time 1.16 seconds
Started Jul 21 06:41:37 PM PDT 24
Finished Jul 21 06:41:39 PM PDT 24
Peak memory 221500 kb
Host smart-2be0021b-a368-4767-8197-4de5f67ddb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866675191 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.866675191
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.1405872531
Short name T904
Test name
Test status
Simulation time 35289867 ps
CPU time 0.84 seconds
Started Jul 21 06:41:36 PM PDT 24
Finished Jul 21 06:41:38 PM PDT 24
Peak memory 207152 kb
Host smart-348f1744-ad8e-4479-9be7-516eead51fd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405872531 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1405872531
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.3805760326
Short name T544
Test name
Test status
Simulation time 101684312 ps
CPU time 1.14 seconds
Started Jul 21 06:41:43 PM PDT 24
Finished Jul 21 06:41:44 PM PDT 24
Peak memory 217064 kb
Host smart-4a6ed360-6265-45f1-8847-0b1ca6b6ae61
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805760326 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.3805760326
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.813680398
Short name T919
Test name
Test status
Simulation time 20887699 ps
CPU time 1.13 seconds
Started Jul 21 06:41:40 PM PDT 24
Finished Jul 21 06:41:42 PM PDT 24
Peak memory 220032 kb
Host smart-70592dcd-d7dc-4b0e-87a6-faa94043f3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813680398 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.813680398
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.2515479027
Short name T653
Test name
Test status
Simulation time 33383553 ps
CPU time 1.28 seconds
Started Jul 21 06:41:41 PM PDT 24
Finished Jul 21 06:41:42 PM PDT 24
Peak memory 218856 kb
Host smart-9b33aa00-049f-499d-a8a6-acfea3e47785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515479027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.2515479027
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.1955998763
Short name T923
Test name
Test status
Simulation time 24552667 ps
CPU time 0.97 seconds
Started Jul 21 06:41:54 PM PDT 24
Finished Jul 21 06:41:57 PM PDT 24
Peak memory 215908 kb
Host smart-097c5379-2f33-4324-8638-18be8d7b61fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955998763 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.1955998763
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.1894458461
Short name T784
Test name
Test status
Simulation time 17354438 ps
CPU time 1.02 seconds
Started Jul 21 06:41:37 PM PDT 24
Finished Jul 21 06:41:39 PM PDT 24
Peak memory 215528 kb
Host smart-503e5b22-9a91-499e-b9ab-a452c2ed0f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894458461 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1894458461
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.4045354937
Short name T902
Test name
Test status
Simulation time 336411199 ps
CPU time 6.32 seconds
Started Jul 21 06:41:48 PM PDT 24
Finished Jul 21 06:41:55 PM PDT 24
Peak memory 219096 kb
Host smart-539ed82f-d18a-48ec-88da-e76f15a87b75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045354937 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.4045354937
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.1476385245
Short name T38
Test name
Test status
Simulation time 92282189970 ps
CPU time 593 seconds
Started Jul 21 06:41:58 PM PDT 24
Finished Jul 21 06:51:52 PM PDT 24
Peak memory 220732 kb
Host smart-57db0898-2f95-4895-8bf2-27eccfa1c60a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476385245 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.1476385245
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.3415102222
Short name T423
Test name
Test status
Simulation time 26389528 ps
CPU time 1.24 seconds
Started Jul 21 06:41:36 PM PDT 24
Finished Jul 21 06:41:38 PM PDT 24
Peak memory 219004 kb
Host smart-4d5f182f-aa0c-4013-8a2e-211e5cd4ca92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415102222 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.3415102222
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.1624654528
Short name T714
Test name
Test status
Simulation time 46133425 ps
CPU time 0.94 seconds
Started Jul 21 06:41:45 PM PDT 24
Finished Jul 21 06:41:46 PM PDT 24
Peak memory 206968 kb
Host smart-6e7f19df-5a46-4149-96e7-6d6225a68846
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624654528 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1624654528
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.647868915
Short name T185
Test name
Test status
Simulation time 35624914 ps
CPU time 0.86 seconds
Started Jul 21 06:41:36 PM PDT 24
Finished Jul 21 06:41:38 PM PDT 24
Peak memory 216468 kb
Host smart-8fd9ac07-8a7c-4434-8726-24716378f658
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647868915 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.647868915
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.3019702392
Short name T65
Test name
Test status
Simulation time 90645066 ps
CPU time 1.2 seconds
Started Jul 21 06:41:37 PM PDT 24
Finished Jul 21 06:41:39 PM PDT 24
Peak memory 218504 kb
Host smart-5fd27c5e-1a76-44bc-8e57-22ffb51c8d38
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019702392 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.3019702392
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.1046201349
Short name T194
Test name
Test status
Simulation time 22471072 ps
CPU time 0.98 seconds
Started Jul 21 06:42:01 PM PDT 24
Finished Jul 21 06:42:04 PM PDT 24
Peak memory 219860 kb
Host smart-53a27b25-e0f6-4940-928b-c110d85e539a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046201349 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.1046201349
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_intr.2051175541
Short name T452
Test name
Test status
Simulation time 102574409 ps
CPU time 0.93 seconds
Started Jul 21 06:41:36 PM PDT 24
Finished Jul 21 06:41:38 PM PDT 24
Peak memory 224148 kb
Host smart-b5fb2023-e673-49d7-8a05-a801367c5b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051175541 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2051175541
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.3830930250
Short name T641
Test name
Test status
Simulation time 30378773 ps
CPU time 0.95 seconds
Started Jul 21 06:41:36 PM PDT 24
Finished Jul 21 06:41:38 PM PDT 24
Peak memory 215496 kb
Host smart-0454905a-5557-44c7-bcb2-d50e4ff1b78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830930250 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.3830930250
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.3105565769
Short name T395
Test name
Test status
Simulation time 165270281 ps
CPU time 3.74 seconds
Started Jul 21 06:41:48 PM PDT 24
Finished Jul 21 06:41:52 PM PDT 24
Peak memory 217532 kb
Host smart-c182beef-a80c-4c7a-9130-27f3917a3bf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105565769 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3105565769
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1412212668
Short name T850
Test name
Test status
Simulation time 51121592164 ps
CPU time 1076.08 seconds
Started Jul 21 06:41:48 PM PDT 24
Finished Jul 21 06:59:45 PM PDT 24
Peak memory 223952 kb
Host smart-02dd5f0e-7613-4957-b427-ea255d8a0748
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412212668 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.1412212668
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.3135935230
Short name T807
Test name
Test status
Simulation time 24802490 ps
CPU time 1.16 seconds
Started Jul 21 06:41:50 PM PDT 24
Finished Jul 21 06:41:51 PM PDT 24
Peak memory 221240 kb
Host smart-00ac7cc0-7f79-4019-a7c1-73011badf0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135935230 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.3135935230
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.1586558364
Short name T834
Test name
Test status
Simulation time 19855953 ps
CPU time 0.99 seconds
Started Jul 21 06:41:53 PM PDT 24
Finished Jul 21 06:41:55 PM PDT 24
Peak memory 215228 kb
Host smart-bee18496-9500-4d26-9c7c-16793221e676
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586558364 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.1586558364
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.3504539595
Short name T638
Test name
Test status
Simulation time 43223185 ps
CPU time 1.42 seconds
Started Jul 21 06:41:50 PM PDT 24
Finished Jul 21 06:41:52 PM PDT 24
Peak memory 217252 kb
Host smart-57a29e42-601d-4770-b8e1-3cedf59ab06b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504539595 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.3504539595
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.401100601
Short name T183
Test name
Test status
Simulation time 23695067 ps
CPU time 0.93 seconds
Started Jul 21 06:41:53 PM PDT 24
Finished Jul 21 06:41:54 PM PDT 24
Peak memory 218900 kb
Host smart-ef4e0a55-5eff-4f83-b42a-59373805da3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401100601 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.401100601
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.3138841428
Short name T41
Test name
Test status
Simulation time 50113118 ps
CPU time 1.34 seconds
Started Jul 21 06:41:43 PM PDT 24
Finished Jul 21 06:41:45 PM PDT 24
Peak memory 218884 kb
Host smart-ffd809d5-6ee0-40d7-908a-2f29c210fb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138841428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.3138841428
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_smoke.4126317458
Short name T713
Test name
Test status
Simulation time 38629335 ps
CPU time 0.9 seconds
Started Jul 21 06:41:46 PM PDT 24
Finished Jul 21 06:41:47 PM PDT 24
Peak memory 215540 kb
Host smart-28492903-219a-4ae6-824e-ba777b76ab62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126317458 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.4126317458
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.1091953733
Short name T744
Test name
Test status
Simulation time 51731775 ps
CPU time 1.67 seconds
Started Jul 21 06:41:40 PM PDT 24
Finished Jul 21 06:41:43 PM PDT 24
Peak memory 217596 kb
Host smart-1f107d98-4e80-46f8-b51d-965b5f64f690
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091953733 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1091953733
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.4033106125
Short name T483
Test name
Test status
Simulation time 57108086163 ps
CPU time 1361.46 seconds
Started Jul 21 06:41:46 PM PDT 24
Finished Jul 21 07:04:28 PM PDT 24
Peak memory 224516 kb
Host smart-59a902e6-387a-4dd0-8dc6-d8ff55060907
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033106125 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.4033106125
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.3093798308
Short name T456
Test name
Test status
Simulation time 68807931 ps
CPU time 1.15 seconds
Started Jul 21 06:41:49 PM PDT 24
Finished Jul 21 06:41:51 PM PDT 24
Peak memory 220144 kb
Host smart-29b5966b-7b0b-46aa-97b5-ce62edde199a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093798308 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.3093798308
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.1309525005
Short name T979
Test name
Test status
Simulation time 28972036 ps
CPU time 0.97 seconds
Started Jul 21 06:41:45 PM PDT 24
Finished Jul 21 06:41:47 PM PDT 24
Peak memory 215176 kb
Host smart-d098a8e9-ea54-4496-bf7b-bc6292651c09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309525005 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.1309525005
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.2674234634
Short name T210
Test name
Test status
Simulation time 13575749 ps
CPU time 0.88 seconds
Started Jul 21 06:41:47 PM PDT 24
Finished Jul 21 06:41:48 PM PDT 24
Peak memory 216440 kb
Host smart-14251040-4206-44af-865b-018ebfb78b82
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674234634 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2674234634
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1158010061
Short name T134
Test name
Test status
Simulation time 42077690 ps
CPU time 0.99 seconds
Started Jul 21 06:41:49 PM PDT 24
Finished Jul 21 06:41:50 PM PDT 24
Peak memory 218604 kb
Host smart-f5ce4f11-9eb9-4a9f-8a17-ccb798f58a77
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158010061 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1158010061
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.899597814
Short name T141
Test name
Test status
Simulation time 21199771 ps
CPU time 1.17 seconds
Started Jul 21 06:41:50 PM PDT 24
Finished Jul 21 06:41:52 PM PDT 24
Peak memory 219992 kb
Host smart-fa56754f-4cef-4989-bce7-83aa9fa2d9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899597814 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.899597814
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.2026183068
Short name T820
Test name
Test status
Simulation time 56423246 ps
CPU time 1.37 seconds
Started Jul 21 06:42:03 PM PDT 24
Finished Jul 21 06:42:05 PM PDT 24
Peak memory 218832 kb
Host smart-15e4d2c9-2fb3-4443-8b87-64b83480c2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026183068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.2026183068
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.3234455735
Short name T1001
Test name
Test status
Simulation time 38284971 ps
CPU time 0.87 seconds
Started Jul 21 06:41:57 PM PDT 24
Finished Jul 21 06:41:59 PM PDT 24
Peak memory 215480 kb
Host smart-815c77d4-412a-44c5-bba1-66989a1314db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234455735 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.3234455735
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.3167856730
Short name T678
Test name
Test status
Simulation time 57559568 ps
CPU time 0.94 seconds
Started Jul 21 06:41:49 PM PDT 24
Finished Jul 21 06:41:50 PM PDT 24
Peak memory 215608 kb
Host smart-bf826b76-3244-4c3c-8086-7198fe67aa03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167856730 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.3167856730
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1148267711
Short name T549
Test name
Test status
Simulation time 720786872 ps
CPU time 4.38 seconds
Started Jul 21 06:41:55 PM PDT 24
Finished Jul 21 06:42:01 PM PDT 24
Peak memory 220124 kb
Host smart-0c449e28-a022-447a-a8d6-96d217d26567
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148267711 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1148267711
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2559277368
Short name T835
Test name
Test status
Simulation time 130122778040 ps
CPU time 674.81 seconds
Started Jul 21 06:42:02 PM PDT 24
Finished Jul 21 06:53:18 PM PDT 24
Peak memory 220724 kb
Host smart-bf5e53a5-a53e-4186-a508-844e58967773
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559277368 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.2559277368
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.1415176212
Short name T107
Test name
Test status
Simulation time 88191772 ps
CPU time 1.2 seconds
Started Jul 21 06:41:52 PM PDT 24
Finished Jul 21 06:41:54 PM PDT 24
Peak memory 219884 kb
Host smart-248c85f7-b926-40bf-ba74-39e242faa84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415176212 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.1415176212
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.1331124100
Short name T617
Test name
Test status
Simulation time 53424493 ps
CPU time 0.84 seconds
Started Jul 21 06:41:56 PM PDT 24
Finished Jul 21 06:41:58 PM PDT 24
Peak memory 206812 kb
Host smart-9ddf01a4-a1e7-44d0-b9f2-4423d00fd8b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331124100 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.1331124100
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.1863081199
Short name T153
Test name
Test status
Simulation time 62616026 ps
CPU time 1.08 seconds
Started Jul 21 06:41:53 PM PDT 24
Finished Jul 21 06:41:55 PM PDT 24
Peak memory 217212 kb
Host smart-253650c8-23cc-4655-b598-f35b17693157
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863081199 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.1863081199
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.3127750498
Short name T156
Test name
Test status
Simulation time 30348272 ps
CPU time 1.29 seconds
Started Jul 21 06:41:44 PM PDT 24
Finished Jul 21 06:41:46 PM PDT 24
Peak memory 219824 kb
Host smart-0b243045-7950-4b1e-88b5-864d864bbf95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127750498 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.3127750498
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.2359089499
Short name T964
Test name
Test status
Simulation time 50798981 ps
CPU time 1.12 seconds
Started Jul 21 06:41:50 PM PDT 24
Finished Jul 21 06:41:52 PM PDT 24
Peak memory 218628 kb
Host smart-81dac222-3fcd-407b-adef-287c91502b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359089499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.2359089499
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.2469712337
Short name T32
Test name
Test status
Simulation time 19975298 ps
CPU time 1.05 seconds
Started Jul 21 06:41:49 PM PDT 24
Finished Jul 21 06:41:51 PM PDT 24
Peak memory 216212 kb
Host smart-7841a17d-98b8-4d07-8f27-95b9fa9867d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469712337 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.2469712337
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.1577916646
Short name T668
Test name
Test status
Simulation time 54159273 ps
CPU time 0.91 seconds
Started Jul 21 06:41:47 PM PDT 24
Finished Jul 21 06:41:49 PM PDT 24
Peak memory 215476 kb
Host smart-735d638d-371e-4353-b93d-ea7e07ea3177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577916646 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.1577916646
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.3197707058
Short name T592
Test name
Test status
Simulation time 253636721 ps
CPU time 3.05 seconds
Started Jul 21 06:41:54 PM PDT 24
Finished Jul 21 06:41:59 PM PDT 24
Peak memory 217484 kb
Host smart-66d8747f-eb99-4fc8-925f-18d7ca9965aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197707058 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3197707058
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.3303285172
Short name T444
Test name
Test status
Simulation time 74607878693 ps
CPU time 973.62 seconds
Started Jul 21 06:41:44 PM PDT 24
Finished Jul 21 06:57:58 PM PDT 24
Peak memory 220864 kb
Host smart-50a88723-b08f-4e34-bedd-576d6a75a4f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303285172 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.3303285172
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.42892621
Short name T816
Test name
Test status
Simulation time 56510383 ps
CPU time 1.29 seconds
Started Jul 21 06:41:54 PM PDT 24
Finished Jul 21 06:41:57 PM PDT 24
Peak memory 219980 kb
Host smart-f11d96b5-ca0b-4936-a18c-d9bd1d9ec437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42892621 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.42892621
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.3052251012
Short name T342
Test name
Test status
Simulation time 17690132 ps
CPU time 0.98 seconds
Started Jul 21 06:41:54 PM PDT 24
Finished Jul 21 06:41:56 PM PDT 24
Peak memory 206968 kb
Host smart-3b95bf2d-5760-4582-ab72-28fc76eeb101
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052251012 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3052251012
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.1243345771
Short name T88
Test name
Test status
Simulation time 15094293 ps
CPU time 0.89 seconds
Started Jul 21 06:41:52 PM PDT 24
Finished Jul 21 06:41:53 PM PDT 24
Peak memory 216660 kb
Host smart-d2f21b0b-6739-49af-b468-7ee85b1cea2d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243345771 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.1243345771
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.133906095
Short name T485
Test name
Test status
Simulation time 40913289 ps
CPU time 1.4 seconds
Started Jul 21 06:41:56 PM PDT 24
Finished Jul 21 06:41:58 PM PDT 24
Peak memory 217156 kb
Host smart-4c463135-6adc-4eb0-ae72-b215d9311e7d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133906095 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_di
sable_auto_req_mode.133906095
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_genbits.784150932
Short name T801
Test name
Test status
Simulation time 197707159 ps
CPU time 3.14 seconds
Started Jul 21 06:41:53 PM PDT 24
Finished Jul 21 06:41:57 PM PDT 24
Peak memory 220196 kb
Host smart-9bd28c08-efb5-4e7a-9d73-8862041f9df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784150932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.784150932
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.1333543611
Short name T90
Test name
Test status
Simulation time 34055608 ps
CPU time 0.9 seconds
Started Jul 21 06:41:55 PM PDT 24
Finished Jul 21 06:41:57 PM PDT 24
Peak memory 215916 kb
Host smart-330bf1ab-e48c-409d-8b2d-003c7ebd34fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333543611 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.1333543611
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.3499279478
Short name T388
Test name
Test status
Simulation time 104378598 ps
CPU time 0.92 seconds
Started Jul 21 06:41:58 PM PDT 24
Finished Jul 21 06:42:00 PM PDT 24
Peak memory 215576 kb
Host smart-0355fb13-a158-4b42-8d0b-275a9d10bd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499279478 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.3499279478
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.2725091449
Short name T698
Test name
Test status
Simulation time 350152718 ps
CPU time 3.82 seconds
Started Jul 21 06:42:02 PM PDT 24
Finished Jul 21 06:42:11 PM PDT 24
Peak memory 217592 kb
Host smart-9754faa0-e9e6-477f-993d-a5c52f981e1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725091449 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.2725091449
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3504825998
Short name T221
Test name
Test status
Simulation time 213424487728 ps
CPU time 929.06 seconds
Started Jul 21 06:41:53 PM PDT 24
Finished Jul 21 06:57:23 PM PDT 24
Peak memory 223864 kb
Host smart-ad9569db-1900-4679-888f-5f638edb6f1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504825998 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.3504825998
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.1061120942
Short name T130
Test name
Test status
Simulation time 124500460 ps
CPU time 1.28 seconds
Started Jul 21 06:41:51 PM PDT 24
Finished Jul 21 06:41:53 PM PDT 24
Peak memory 218728 kb
Host smart-032e0065-305d-43f8-a58a-19c53e1aa42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061120942 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.1061120942
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.2857113538
Short name T669
Test name
Test status
Simulation time 11583342 ps
CPU time 0.84 seconds
Started Jul 21 06:42:15 PM PDT 24
Finished Jul 21 06:42:17 PM PDT 24
Peak memory 206984 kb
Host smart-4c9b70c1-cd73-4248-b99c-05ecbc736c0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857113538 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2857113538
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.997307513
Short name T469
Test name
Test status
Simulation time 11016100 ps
CPU time 0.9 seconds
Started Jul 21 06:41:55 PM PDT 24
Finished Jul 21 06:41:57 PM PDT 24
Peak memory 216180 kb
Host smart-0ca23794-a494-4b22-85e2-291977235caf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997307513 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.997307513
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.3922495377
Short name T957
Test name
Test status
Simulation time 75791880 ps
CPU time 1.22 seconds
Started Jul 21 06:41:53 PM PDT 24
Finished Jul 21 06:41:56 PM PDT 24
Peak memory 218712 kb
Host smart-8996e1a4-6cd1-49ea-bde2-8c395a49ba3b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922495377 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.3922495377
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.4220353923
Short name T720
Test name
Test status
Simulation time 40872376 ps
CPU time 1.06 seconds
Started Jul 21 06:41:54 PM PDT 24
Finished Jul 21 06:41:57 PM PDT 24
Peak memory 219816 kb
Host smart-79461c12-f840-4143-bac9-6e300085ddd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220353923 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.4220353923
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.429484287
Short name T466
Test name
Test status
Simulation time 35343387 ps
CPU time 1.29 seconds
Started Jul 21 06:41:58 PM PDT 24
Finished Jul 21 06:42:00 PM PDT 24
Peak memory 219984 kb
Host smart-d678f51b-9564-4720-bb11-82ba37ba93f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429484287 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.429484287
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.1712582589
Short name T50
Test name
Test status
Simulation time 22137147 ps
CPU time 1.15 seconds
Started Jul 21 06:41:51 PM PDT 24
Finished Jul 21 06:41:53 PM PDT 24
Peak memory 224328 kb
Host smart-3a455c07-b74f-4920-80d0-2e8c9bef5e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712582589 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1712582589
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.3615771215
Short name T351
Test name
Test status
Simulation time 17145494 ps
CPU time 1.03 seconds
Started Jul 21 06:42:01 PM PDT 24
Finished Jul 21 06:42:03 PM PDT 24
Peak memory 215472 kb
Host smart-66f22713-fc0f-4ca6-afb8-4bac2da8558f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615771215 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.3615771215
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.4118894294
Short name T491
Test name
Test status
Simulation time 340043284 ps
CPU time 3.32 seconds
Started Jul 21 06:41:53 PM PDT 24
Finished Jul 21 06:41:57 PM PDT 24
Peak memory 217596 kb
Host smart-c5070cf2-6f66-4a5d-8bbb-3d9eb915813e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118894294 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.4118894294
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.828964184
Short name T393
Test name
Test status
Simulation time 17630655197 ps
CPU time 237.78 seconds
Started Jul 21 06:41:49 PM PDT 24
Finished Jul 21 06:45:47 PM PDT 24
Peak memory 223580 kb
Host smart-791e2e4b-f83d-4cf1-92f4-417310d2dce7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828964184 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.828964184
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.2634113832
Short name T681
Test name
Test status
Simulation time 66988308 ps
CPU time 1.07 seconds
Started Jul 21 06:42:15 PM PDT 24
Finished Jul 21 06:42:18 PM PDT 24
Peak memory 220996 kb
Host smart-49955075-87c9-498d-ac1d-b7408300789d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634113832 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2634113832
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.1505751015
Short name T364
Test name
Test status
Simulation time 31849331 ps
CPU time 1.23 seconds
Started Jul 21 06:42:00 PM PDT 24
Finished Jul 21 06:42:03 PM PDT 24
Peak memory 207068 kb
Host smart-3596c945-3863-449c-89c8-e47b6f1cbc25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505751015 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1505751015
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.1737581906
Short name T86
Test name
Test status
Simulation time 17166607 ps
CPU time 0.86 seconds
Started Jul 21 06:42:05 PM PDT 24
Finished Jul 21 06:42:07 PM PDT 24
Peak memory 216468 kb
Host smart-e771a04a-2b4a-4369-9a5f-ffba68502eb4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737581906 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1737581906
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.800789775
Short name T853
Test name
Test status
Simulation time 23099551 ps
CPU time 1.06 seconds
Started Jul 21 06:42:16 PM PDT 24
Finished Jul 21 06:42:19 PM PDT 24
Peak memory 218976 kb
Host smart-b7938c89-969d-476d-adc8-62ad160f1bf1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800789775 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_di
sable_auto_req_mode.800789775
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.869996448
Short name T867
Test name
Test status
Simulation time 39765002 ps
CPU time 1.13 seconds
Started Jul 21 06:41:54 PM PDT 24
Finished Jul 21 06:41:56 PM PDT 24
Peak memory 221060 kb
Host smart-4ba9504b-0a4e-4799-8c7b-78b89bd22639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869996448 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.869996448
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.752021167
Short name T431
Test name
Test status
Simulation time 287357887 ps
CPU time 3.17 seconds
Started Jul 21 06:42:01 PM PDT 24
Finished Jul 21 06:42:06 PM PDT 24
Peak memory 217708 kb
Host smart-e27c2ef4-27b7-4b16-8734-511a7c95a454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752021167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.752021167
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1159499512
Short name T404
Test name
Test status
Simulation time 27478060 ps
CPU time 0.96 seconds
Started Jul 21 06:42:10 PM PDT 24
Finished Jul 21 06:42:12 PM PDT 24
Peak memory 215784 kb
Host smart-369da6e8-9ab6-4299-93aa-dccb4ec12840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159499512 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1159499512
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.2066410999
Short name T341
Test name
Test status
Simulation time 25821524 ps
CPU time 0.95 seconds
Started Jul 21 06:41:55 PM PDT 24
Finished Jul 21 06:41:58 PM PDT 24
Peak memory 215484 kb
Host smart-c667d154-a1ce-4b25-a6cc-07174e66c253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066410999 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.2066410999
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.1845681787
Short name T594
Test name
Test status
Simulation time 136017782 ps
CPU time 1.85 seconds
Started Jul 21 06:41:54 PM PDT 24
Finished Jul 21 06:41:57 PM PDT 24
Peak memory 217512 kb
Host smart-8b64f88d-c446-4b2c-b827-80b69a9683a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845681787 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1845681787
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.1575507182
Short name T861
Test name
Test status
Simulation time 109589836086 ps
CPU time 683.1 seconds
Started Jul 21 06:42:17 PM PDT 24
Finished Jul 21 06:53:42 PM PDT 24
Peak memory 221564 kb
Host smart-832c87f9-a77f-46ec-9dc7-4a39747982c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575507182 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.1575507182
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.2153160223
Short name T672
Test name
Test status
Simulation time 62846952 ps
CPU time 1.2 seconds
Started Jul 21 06:42:07 PM PDT 24
Finished Jul 21 06:42:09 PM PDT 24
Peak memory 218748 kb
Host smart-d50d7335-8d15-436a-b3c4-62c742c72df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153160223 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.2153160223
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.635996679
Short name T666
Test name
Test status
Simulation time 26584089 ps
CPU time 0.85 seconds
Started Jul 21 06:42:10 PM PDT 24
Finished Jul 21 06:42:12 PM PDT 24
Peak memory 206964 kb
Host smart-0b46af5a-3a4b-4946-ae21-3dc7abd65abd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635996679 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.635996679
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.2541915724
Short name T439
Test name
Test status
Simulation time 34948424 ps
CPU time 0.87 seconds
Started Jul 21 06:41:55 PM PDT 24
Finished Jul 21 06:41:58 PM PDT 24
Peak memory 215608 kb
Host smart-5c04374a-9e42-43a8-8ba9-5d8ac615994c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541915724 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.2541915724
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.4109402509
Short name T151
Test name
Test status
Simulation time 34624019 ps
CPU time 1.33 seconds
Started Jul 21 06:42:02 PM PDT 24
Finished Jul 21 06:42:05 PM PDT 24
Peak memory 217248 kb
Host smart-97108a33-1173-4f55-8c0a-6c40973e03f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109402509 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.4109402509
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.1931332561
Short name T232
Test name
Test status
Simulation time 67119596 ps
CPU time 1.11 seconds
Started Jul 21 06:41:54 PM PDT 24
Finished Jul 21 06:41:57 PM PDT 24
Peak memory 220204 kb
Host smart-1e39fd7e-e2fc-4c24-8e44-649c717078e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931332561 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.1931332561
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.1270354534
Short name T637
Test name
Test status
Simulation time 108100306 ps
CPU time 2.54 seconds
Started Jul 21 06:42:04 PM PDT 24
Finished Jul 21 06:42:07 PM PDT 24
Peak memory 218924 kb
Host smart-b5081ba9-e9d6-4d8b-9d36-7cb6989d3963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270354534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1270354534
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.1410497503
Short name T36
Test name
Test status
Simulation time 21682572 ps
CPU time 1.11 seconds
Started Jul 21 06:42:06 PM PDT 24
Finished Jul 21 06:42:08 PM PDT 24
Peak memory 216172 kb
Host smart-026abbb6-e6c7-4c5b-992a-eb31fa0cc5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410497503 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.1410497503
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.877154300
Short name T599
Test name
Test status
Simulation time 22682500 ps
CPU time 0.93 seconds
Started Jul 21 06:41:57 PM PDT 24
Finished Jul 21 06:42:00 PM PDT 24
Peak memory 215560 kb
Host smart-4fff4550-8e9b-4832-93be-abf07bd50d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877154300 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.877154300
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.972932559
Short name T62
Test name
Test status
Simulation time 243541326 ps
CPU time 3.68 seconds
Started Jul 21 06:41:54 PM PDT 24
Finished Jul 21 06:41:59 PM PDT 24
Peak memory 217324 kb
Host smart-ea95e7f7-a45d-44d0-9891-f0be21f2b9bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972932559 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.972932559
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_alert.3850415878
Short name T891
Test name
Test status
Simulation time 29517152 ps
CPU time 1.25 seconds
Started Jul 21 06:42:00 PM PDT 24
Finished Jul 21 06:42:02 PM PDT 24
Peak memory 220920 kb
Host smart-e08507b0-ff1e-4add-b500-f0451ba88599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850415878 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.3850415878
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.4015693003
Short name T66
Test name
Test status
Simulation time 16884206 ps
CPU time 0.9 seconds
Started Jul 21 06:42:01 PM PDT 24
Finished Jul 21 06:42:03 PM PDT 24
Peak memory 207012 kb
Host smart-bb5f2870-af4c-41e9-aed0-7aaaf002c22a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015693003 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.4015693003
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.3403358908
Short name T81
Test name
Test status
Simulation time 22135910 ps
CPU time 0.89 seconds
Started Jul 21 06:42:06 PM PDT 24
Finished Jul 21 06:42:07 PM PDT 24
Peak memory 216476 kb
Host smart-70af7afa-21bb-46c5-971c-ccc68ac5e87b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403358908 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.3403358908
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_genbits.3814142966
Short name T43
Test name
Test status
Simulation time 93736837 ps
CPU time 1.07 seconds
Started Jul 21 06:41:59 PM PDT 24
Finished Jul 21 06:42:02 PM PDT 24
Peak memory 217572 kb
Host smart-5b4d6be5-105d-4771-8901-939d74aafbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814142966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3814142966
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.1805853908
Short name T474
Test name
Test status
Simulation time 26150795 ps
CPU time 1.04 seconds
Started Jul 21 06:42:00 PM PDT 24
Finished Jul 21 06:42:02 PM PDT 24
Peak memory 215992 kb
Host smart-7e4c8098-2f3f-40b3-90aa-23a01ea99693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805853908 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.1805853908
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.2936046529
Short name T943
Test name
Test status
Simulation time 16311057 ps
CPU time 1.01 seconds
Started Jul 21 06:42:13 PM PDT 24
Finished Jul 21 06:42:15 PM PDT 24
Peak memory 215584 kb
Host smart-9e47fbb7-338e-4f64-83c1-237aa1e5e619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936046529 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.2936046529
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.3052435511
Short name T600
Test name
Test status
Simulation time 256578614 ps
CPU time 4.93 seconds
Started Jul 21 06:41:54 PM PDT 24
Finished Jul 21 06:42:00 PM PDT 24
Peak memory 217444 kb
Host smart-472a66ef-ffc1-4e20-a868-1e470f6b74c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052435511 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.3052435511
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.3901854458
Short name T745
Test name
Test status
Simulation time 520562033817 ps
CPU time 1157.94 seconds
Started Jul 21 06:42:15 PM PDT 24
Finished Jul 21 07:01:35 PM PDT 24
Peak memory 223548 kb
Host smart-f2fc727e-0ae8-4c5b-bed0-1d58b958bbdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901854458 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.3901854458
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.3541947688
Short name T118
Test name
Test status
Simulation time 73943281 ps
CPU time 1.18 seconds
Started Jul 21 06:40:46 PM PDT 24
Finished Jul 21 06:40:48 PM PDT 24
Peak memory 219776 kb
Host smart-27c6ae04-88b6-4836-b5b0-eac22588e4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541947688 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3541947688
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.814336117
Short name T366
Test name
Test status
Simulation time 12244107 ps
CPU time 0.85 seconds
Started Jul 21 06:40:47 PM PDT 24
Finished Jul 21 06:40:49 PM PDT 24
Peak memory 207328 kb
Host smart-5b2bba2b-d243-4c52-94ca-098f9a6c4772
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814336117 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.814336117
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.1025723968
Short name T635
Test name
Test status
Simulation time 21148310 ps
CPU time 1 seconds
Started Jul 21 06:40:46 PM PDT 24
Finished Jul 21 06:40:48 PM PDT 24
Peak memory 216052 kb
Host smart-ffdaa7d4-0ebd-4475-a37e-bb74f6c5b2f4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025723968 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1025723968
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.3530771540
Short name T135
Test name
Test status
Simulation time 49151987 ps
CPU time 1.15 seconds
Started Jul 21 06:40:44 PM PDT 24
Finished Jul 21 06:40:46 PM PDT 24
Peak memory 219688 kb
Host smart-fd6a4c42-a644-4553-9104-e62669188e08
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530771540 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.3530771540
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.2783456440
Short name T49
Test name
Test status
Simulation time 24758297 ps
CPU time 1.34 seconds
Started Jul 21 06:40:47 PM PDT 24
Finished Jul 21 06:40:49 PM PDT 24
Peak memory 229864 kb
Host smart-fb953cb6-8092-4aa9-a624-51cde5e77264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783456440 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.2783456440
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.1100437120
Short name T778
Test name
Test status
Simulation time 37099463 ps
CPU time 1.07 seconds
Started Jul 21 06:40:47 PM PDT 24
Finished Jul 21 06:40:49 PM PDT 24
Peak memory 217560 kb
Host smart-704d4a9e-53f8-4b4e-8bbd-f5c93868f2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100437120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1100437120
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.223703760
Short name T374
Test name
Test status
Simulation time 22528897 ps
CPU time 1.1 seconds
Started Jul 21 06:40:45 PM PDT 24
Finished Jul 21 06:40:47 PM PDT 24
Peak memory 215724 kb
Host smart-1cc95045-fa6d-4994-9012-ad05052492a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223703760 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.223703760
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.16150648
Short name T25
Test name
Test status
Simulation time 40284102 ps
CPU time 0.97 seconds
Started Jul 21 06:40:45 PM PDT 24
Finished Jul 21 06:40:47 PM PDT 24
Peak memory 207372 kb
Host smart-ff8917fd-8787-4aec-b806-7332452394ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16150648 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.16150648
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.1370125882
Short name T762
Test name
Test status
Simulation time 43467793 ps
CPU time 0.91 seconds
Started Jul 21 06:40:45 PM PDT 24
Finished Jul 21 06:40:46 PM PDT 24
Peak memory 215564 kb
Host smart-d0cc372e-c440-48bd-8c37-cf1085d1c9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370125882 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.1370125882
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.2095837043
Short name T448
Test name
Test status
Simulation time 221368324 ps
CPU time 2.83 seconds
Started Jul 21 06:40:50 PM PDT 24
Finished Jul 21 06:40:54 PM PDT 24
Peak memory 217432 kb
Host smart-2cd74e65-1d19-4543-9962-2216dab7f684
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095837043 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2095837043
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.461803997
Short name T493
Test name
Test status
Simulation time 88209349499 ps
CPU time 1346 seconds
Started Jul 21 06:40:47 PM PDT 24
Finished Jul 21 07:03:14 PM PDT 24
Peak memory 224904 kb
Host smart-0280dd7f-cb17-41eb-aa09-7fb44ddd5b45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461803997 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.461803997
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.208177463
Short name T403
Test name
Test status
Simulation time 32602290 ps
CPU time 1.23 seconds
Started Jul 21 06:42:00 PM PDT 24
Finished Jul 21 06:42:02 PM PDT 24
Peak memory 218748 kb
Host smart-84d73ab7-a915-4002-8951-a28eeda721c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208177463 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.208177463
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.1782344214
Short name T165
Test name
Test status
Simulation time 30236379 ps
CPU time 1.28 seconds
Started Jul 21 06:42:06 PM PDT 24
Finished Jul 21 06:42:08 PM PDT 24
Peak memory 220016 kb
Host smart-47d78cbb-8f46-4f09-bd66-44cdb4e4f35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782344214 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.1782344214
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.1858388405
Short name T879
Test name
Test status
Simulation time 34885946 ps
CPU time 1.39 seconds
Started Jul 21 06:42:01 PM PDT 24
Finished Jul 21 06:42:04 PM PDT 24
Peak memory 218764 kb
Host smart-b8d0a18f-213a-4d16-b780-b9eeb5f20e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858388405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1858388405
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.531707602
Short name T380
Test name
Test status
Simulation time 85501441 ps
CPU time 1.12 seconds
Started Jul 21 06:41:58 PM PDT 24
Finished Jul 21 06:42:01 PM PDT 24
Peak memory 218924 kb
Host smart-3dc67a59-36f4-497f-8453-54d6f00e74dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531707602 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.531707602
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.1033163368
Short name T163
Test name
Test status
Simulation time 23790074 ps
CPU time 1.07 seconds
Started Jul 21 06:41:55 PM PDT 24
Finished Jul 21 06:41:58 PM PDT 24
Peak memory 224172 kb
Host smart-ab1deaca-51ec-4cde-9eb3-f5f61b8c48c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033163368 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.1033163368
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.4073068305
Short name T885
Test name
Test status
Simulation time 38697416 ps
CPU time 1.18 seconds
Started Jul 21 06:42:00 PM PDT 24
Finished Jul 21 06:42:02 PM PDT 24
Peak memory 217676 kb
Host smart-5d36d779-a1fb-4164-9d65-05930d65ed8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073068305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.4073068305
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.3726834405
Short name T179
Test name
Test status
Simulation time 28284794 ps
CPU time 1.18 seconds
Started Jul 21 06:41:58 PM PDT 24
Finished Jul 21 06:42:01 PM PDT 24
Peak memory 219896 kb
Host smart-d3e90cfb-43be-42bf-b4ae-41a71b399465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726834405 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.3726834405
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.2909055759
Short name T545
Test name
Test status
Simulation time 34095910 ps
CPU time 1.04 seconds
Started Jul 21 06:41:55 PM PDT 24
Finished Jul 21 06:41:57 PM PDT 24
Peak memory 229836 kb
Host smart-f436553e-4333-4276-ac26-7a54a1281265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909055759 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2909055759
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.2191180528
Short name T611
Test name
Test status
Simulation time 41322920 ps
CPU time 1.47 seconds
Started Jul 21 06:42:04 PM PDT 24
Finished Jul 21 06:42:06 PM PDT 24
Peak memory 218772 kb
Host smart-7a563092-ff44-482f-9d74-4149e7ef8468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191180528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.2191180528
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.21371989
Short name T763
Test name
Test status
Simulation time 23622659 ps
CPU time 1.22 seconds
Started Jul 21 06:41:57 PM PDT 24
Finished Jul 21 06:42:00 PM PDT 24
Peak memory 219628 kb
Host smart-4c8e021b-3aeb-4070-83ef-5cb7d02499fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21371989 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.21371989
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.3888909133
Short name T127
Test name
Test status
Simulation time 51599279 ps
CPU time 0.97 seconds
Started Jul 21 06:42:10 PM PDT 24
Finished Jul 21 06:42:12 PM PDT 24
Peak memory 219892 kb
Host smart-4a3c3be4-2ef2-48dd-91fd-f89182f51c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888909133 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.3888909133
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.1638798817
Short name T315
Test name
Test status
Simulation time 74117720 ps
CPU time 1.15 seconds
Started Jul 21 06:42:01 PM PDT 24
Finished Jul 21 06:42:04 PM PDT 24
Peak memory 219468 kb
Host smart-6e752bda-d245-4fb8-ab5c-4fcda73b8fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638798817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.1638798817
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.669681588
Short name T701
Test name
Test status
Simulation time 111161163 ps
CPU time 1.21 seconds
Started Jul 21 06:42:16 PM PDT 24
Finished Jul 21 06:42:18 PM PDT 24
Peak memory 218848 kb
Host smart-b70307d6-c03f-4719-ab13-95abd595f4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669681588 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.669681588
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.3307176
Short name T499
Test name
Test status
Simulation time 44800081 ps
CPU time 0.86 seconds
Started Jul 21 06:42:05 PM PDT 24
Finished Jul 21 06:42:07 PM PDT 24
Peak memory 218712 kb
Host smart-c0bb4c55-3b79-450b-89bd-58737bedf1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307176 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.3307176
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.1666046791
Short name T80
Test name
Test status
Simulation time 118453437 ps
CPU time 1.46 seconds
Started Jul 21 06:42:23 PM PDT 24
Finished Jul 21 06:42:26 PM PDT 24
Peak memory 219016 kb
Host smart-27c4e343-7582-4b1d-9ca7-b9975c4bc1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666046791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1666046791
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.306587414
Short name T440
Test name
Test status
Simulation time 19039064 ps
CPU time 1.04 seconds
Started Jul 21 06:41:59 PM PDT 24
Finished Jul 21 06:42:01 PM PDT 24
Peak memory 218816 kb
Host smart-7cea1f32-ad9a-4d08-9f47-54de9729f935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306587414 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.306587414
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.2209096924
Short name T353
Test name
Test status
Simulation time 40222380 ps
CPU time 1.41 seconds
Started Jul 21 06:42:00 PM PDT 24
Finished Jul 21 06:42:03 PM PDT 24
Peak memory 217384 kb
Host smart-9f7e6a35-dcff-4e31-a41f-f0af3a1e77a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209096924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.2209096924
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.4052820762
Short name T795
Test name
Test status
Simulation time 78191817 ps
CPU time 1.24 seconds
Started Jul 21 06:42:09 PM PDT 24
Finished Jul 21 06:42:11 PM PDT 24
Peak memory 220176 kb
Host smart-0d7eff65-c685-4a32-ad7f-2c0416e4cfbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052820762 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.4052820762
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.2206580503
Short name T693
Test name
Test status
Simulation time 39415425 ps
CPU time 1.12 seconds
Started Jul 21 06:41:57 PM PDT 24
Finished Jul 21 06:41:59 PM PDT 24
Peak memory 220752 kb
Host smart-ebfbd6c0-0731-412f-a46e-9528e19f1d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206580503 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.2206580503
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.3696784114
Short name T877
Test name
Test status
Simulation time 37240528 ps
CPU time 1.09 seconds
Started Jul 21 06:42:12 PM PDT 24
Finished Jul 21 06:42:14 PM PDT 24
Peak memory 219732 kb
Host smart-0bd8c884-a2b3-4184-8475-4367d3a18904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696784114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.3696784114
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.2971960149
Short name T805
Test name
Test status
Simulation time 49656733 ps
CPU time 1.04 seconds
Started Jul 21 06:42:10 PM PDT 24
Finished Jul 21 06:42:12 PM PDT 24
Peak memory 220832 kb
Host smart-a0c2bac1-4775-4f82-931f-f89dc3abce2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971960149 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.2971960149
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.3040198253
Short name T335
Test name
Test status
Simulation time 266892085 ps
CPU time 3.86 seconds
Started Jul 21 06:41:55 PM PDT 24
Finished Jul 21 06:42:00 PM PDT 24
Peak memory 215532 kb
Host smart-f120b1c1-fd38-40db-8c80-02bad0bdf060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040198253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3040198253
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.1364343614
Short name T274
Test name
Test status
Simulation time 67651059 ps
CPU time 1.16 seconds
Started Jul 21 06:42:00 PM PDT 24
Finished Jul 21 06:42:02 PM PDT 24
Peak memory 218848 kb
Host smart-56511a46-49c2-43b4-8e27-cf32c91eaa39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364343614 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.1364343614
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.1109847663
Short name T378
Test name
Test status
Simulation time 32399076 ps
CPU time 0.84 seconds
Started Jul 21 06:41:58 PM PDT 24
Finished Jul 21 06:42:00 PM PDT 24
Peak memory 218488 kb
Host smart-322f4191-973e-4f5a-8396-66509ceb1423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109847663 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.1109847663
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.2164358875
Short name T406
Test name
Test status
Simulation time 47099412 ps
CPU time 1.94 seconds
Started Jul 21 06:41:59 PM PDT 24
Finished Jul 21 06:42:02 PM PDT 24
Peak memory 220320 kb
Host smart-87a6bb35-70dd-47b4-ab99-e4739f087834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164358875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.2164358875
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.1334048103
Short name T528
Test name
Test status
Simulation time 43649166 ps
CPU time 1.15 seconds
Started Jul 21 06:41:56 PM PDT 24
Finished Jul 21 06:41:58 PM PDT 24
Peak memory 220636 kb
Host smart-370b4abf-99a6-4068-88c6-43ffdaa7115e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334048103 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.1334048103
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.342927542
Short name T132
Test name
Test status
Simulation time 24464537 ps
CPU time 1.18 seconds
Started Jul 21 06:41:54 PM PDT 24
Finished Jul 21 06:41:56 PM PDT 24
Peak memory 220080 kb
Host smart-bb693b3c-15d1-4ab7-a0c2-8640d9e6967b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342927542 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.342927542
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.2818093270
Short name T596
Test name
Test status
Simulation time 58056321 ps
CPU time 1.78 seconds
Started Jul 21 06:42:01 PM PDT 24
Finished Jul 21 06:42:04 PM PDT 24
Peak memory 219052 kb
Host smart-3a338122-5bf7-47a6-8337-4cb347e12efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818093270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.2818093270
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.2040298379
Short name T712
Test name
Test status
Simulation time 181089460 ps
CPU time 1.29 seconds
Started Jul 21 06:40:51 PM PDT 24
Finished Jul 21 06:40:54 PM PDT 24
Peak memory 219660 kb
Host smart-63d0a47c-00ca-4091-881e-997b9873db9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040298379 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.2040298379
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.743716678
Short name T937
Test name
Test status
Simulation time 60328306 ps
CPU time 0.98 seconds
Started Jul 21 06:40:51 PM PDT 24
Finished Jul 21 06:40:54 PM PDT 24
Peak memory 207016 kb
Host smart-967898ef-8a00-4d89-8322-f94766536b4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743716678 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.743716678
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.3236646500
Short name T205
Test name
Test status
Simulation time 23752531 ps
CPU time 0.86 seconds
Started Jul 21 06:40:45 PM PDT 24
Finished Jul 21 06:40:47 PM PDT 24
Peak memory 216444 kb
Host smart-c2ef9651-6f7f-4ee6-9952-c142ae94ce72
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236646500 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.3236646500
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.3032709618
Short name T525
Test name
Test status
Simulation time 57100093 ps
CPU time 1.13 seconds
Started Jul 21 06:40:51 PM PDT 24
Finished Jul 21 06:40:54 PM PDT 24
Peak memory 217192 kb
Host smart-d80a0e1e-762b-4cbb-a6df-36253650d527
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032709618 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.3032709618
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.39068088
Short name T73
Test name
Test status
Simulation time 37419002 ps
CPU time 0.93 seconds
Started Jul 21 06:40:49 PM PDT 24
Finished Jul 21 06:40:52 PM PDT 24
Peak memory 220100 kb
Host smart-c731dbc8-4ee1-49a1-9377-8236731f7ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39068088 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.39068088
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.1343129907
Short name T707
Test name
Test status
Simulation time 34502229 ps
CPU time 1.27 seconds
Started Jul 21 06:40:45 PM PDT 24
Finished Jul 21 06:40:47 PM PDT 24
Peak memory 217428 kb
Host smart-4f9c4582-ff8b-444d-94fb-5cfe428f83e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343129907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.1343129907
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.340210339
Short name T864
Test name
Test status
Simulation time 36363027 ps
CPU time 0.88 seconds
Started Jul 21 06:40:50 PM PDT 24
Finished Jul 21 06:40:53 PM PDT 24
Peak memory 215640 kb
Host smart-08bb5287-6634-49c6-9978-7994b7317bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340210339 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.340210339
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_smoke.563177132
Short name T739
Test name
Test status
Simulation time 22924224 ps
CPU time 1 seconds
Started Jul 21 06:40:45 PM PDT 24
Finished Jul 21 06:40:47 PM PDT 24
Peak memory 215496 kb
Host smart-d518a7ab-05b6-4c9f-8d78-d19dae6fc679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563177132 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.563177132
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.1698289280
Short name T689
Test name
Test status
Simulation time 173427010 ps
CPU time 2.16 seconds
Started Jul 21 06:40:47 PM PDT 24
Finished Jul 21 06:40:50 PM PDT 24
Peak memory 215628 kb
Host smart-1216f6b5-b3b9-462d-8dc2-c82c6af2b15c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698289280 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.1698289280
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.423747992
Short name T405
Test name
Test status
Simulation time 126063516037 ps
CPU time 279.81 seconds
Started Jul 21 06:40:48 PM PDT 24
Finished Jul 21 06:45:30 PM PDT 24
Peak memory 224028 kb
Host smart-b56c36de-fa22-4e9f-b18c-a1f31aac8801
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423747992 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.423747992
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.1392348163
Short name T654
Test name
Test status
Simulation time 83185034 ps
CPU time 1.2 seconds
Started Jul 21 06:42:21 PM PDT 24
Finished Jul 21 06:42:23 PM PDT 24
Peak memory 220076 kb
Host smart-bba46d60-3702-44cd-bf5b-ce04c2acaaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392348163 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.1392348163
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.2961285504
Short name T5
Test name
Test status
Simulation time 56910967 ps
CPU time 1.01 seconds
Started Jul 21 06:42:05 PM PDT 24
Finished Jul 21 06:42:07 PM PDT 24
Peak memory 220824 kb
Host smart-4d0e4204-8f42-4772-bccc-4ab6c9c2c8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961285504 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.2961285504
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.3040479557
Short name T516
Test name
Test status
Simulation time 99693239 ps
CPU time 1.31 seconds
Started Jul 21 06:42:05 PM PDT 24
Finished Jul 21 06:42:07 PM PDT 24
Peak memory 218952 kb
Host smart-8ba0638f-5fd8-428a-b7a9-fd06084cb5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040479557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3040479557
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.1750530782
Short name T412
Test name
Test status
Simulation time 37403415 ps
CPU time 1.25 seconds
Started Jul 21 06:42:18 PM PDT 24
Finished Jul 21 06:42:21 PM PDT 24
Peak memory 219000 kb
Host smart-99cc30bb-bed4-41c9-a44d-5d0f4e3990ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750530782 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.1750530782
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.2727066427
Short name T207
Test name
Test status
Simulation time 23804602 ps
CPU time 1.29 seconds
Started Jul 21 06:42:25 PM PDT 24
Finished Jul 21 06:42:27 PM PDT 24
Peak memory 229952 kb
Host smart-d0bf918c-5540-4d34-8b96-99343d8d603c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727066427 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.2727066427
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.2448782157
Short name T590
Test name
Test status
Simulation time 36503893 ps
CPU time 1.09 seconds
Started Jul 21 06:42:07 PM PDT 24
Finished Jul 21 06:42:09 PM PDT 24
Peak memory 217208 kb
Host smart-7ef0643c-6efc-4931-93d6-e484ae0768a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448782157 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.2448782157
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.25020683
Short name T188
Test name
Test status
Simulation time 24615099 ps
CPU time 1.18 seconds
Started Jul 21 06:42:07 PM PDT 24
Finished Jul 21 06:42:09 PM PDT 24
Peak memory 219152 kb
Host smart-468662c9-470f-4152-b4de-cd910cc3c821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25020683 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.25020683
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.629029992
Short name T486
Test name
Test status
Simulation time 36289142 ps
CPU time 0.83 seconds
Started Jul 21 06:42:17 PM PDT 24
Finished Jul 21 06:42:19 PM PDT 24
Peak memory 218540 kb
Host smart-50cf88d1-7348-476b-928f-2c0ef79a3c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629029992 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.629029992
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.889984617
Short name T511
Test name
Test status
Simulation time 47192096 ps
CPU time 1.47 seconds
Started Jul 21 06:42:16 PM PDT 24
Finished Jul 21 06:42:19 PM PDT 24
Peak memory 218908 kb
Host smart-c2fa0017-33d8-4649-a95f-f5f795a0803e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889984617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.889984617
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.2255776506
Short name T136
Test name
Test status
Simulation time 39283124 ps
CPU time 1.13 seconds
Started Jul 21 06:42:09 PM PDT 24
Finished Jul 21 06:42:11 PM PDT 24
Peak memory 219836 kb
Host smart-928f0aa1-3541-41c5-87a5-eb4c2a073e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255776506 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.2255776506
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.4067291335
Short name T848
Test name
Test status
Simulation time 24361307 ps
CPU time 0.86 seconds
Started Jul 21 06:42:10 PM PDT 24
Finished Jul 21 06:42:12 PM PDT 24
Peak memory 218616 kb
Host smart-f38f3fb0-5b42-4554-92af-d1ffbf5d0a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067291335 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.4067291335
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.150009021
Short name T968
Test name
Test status
Simulation time 89257635 ps
CPU time 2 seconds
Started Jul 21 06:42:21 PM PDT 24
Finished Jul 21 06:42:24 PM PDT 24
Peak memory 218824 kb
Host smart-bf93174f-2254-4840-a9d6-066130d34505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150009021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.150009021
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.1996883488
Short name T894
Test name
Test status
Simulation time 23740606 ps
CPU time 1.16 seconds
Started Jul 21 06:42:17 PM PDT 24
Finished Jul 21 06:42:20 PM PDT 24
Peak memory 220220 kb
Host smart-a79498fc-cfcf-4045-ad4d-fdc7bdf0aef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996883488 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.1996883488
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.4214640410
Short name T34
Test name
Test status
Simulation time 18961103 ps
CPU time 1.03 seconds
Started Jul 21 06:42:02 PM PDT 24
Finished Jul 21 06:42:04 PM PDT 24
Peak memory 218588 kb
Host smart-f8fdda93-f812-461e-817b-b55d14cfb096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214640410 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.4214640410
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.4271091186
Short name T402
Test name
Test status
Simulation time 68545285 ps
CPU time 1.6 seconds
Started Jul 21 06:42:19 PM PDT 24
Finished Jul 21 06:42:22 PM PDT 24
Peak memory 219096 kb
Host smart-6d3257b3-1e46-47e2-a2fa-b0d71ee39d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271091186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.4271091186
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.3303055158
Short name T740
Test name
Test status
Simulation time 25064195 ps
CPU time 1.16 seconds
Started Jul 21 06:42:19 PM PDT 24
Finished Jul 21 06:42:21 PM PDT 24
Peak memory 218812 kb
Host smart-16bf71ef-e80f-407c-95ea-c772faaaa43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303055158 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.3303055158
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.1686325448
Short name T680
Test name
Test status
Simulation time 49247064 ps
CPU time 1.12 seconds
Started Jul 21 06:42:05 PM PDT 24
Finished Jul 21 06:42:07 PM PDT 24
Peak memory 224292 kb
Host smart-571d3934-c310-4e0d-849d-d7f1248ecd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686325448 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.1686325448
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.636232299
Short name T460
Test name
Test status
Simulation time 50975100 ps
CPU time 1.86 seconds
Started Jul 21 06:42:06 PM PDT 24
Finished Jul 21 06:42:09 PM PDT 24
Peak memory 218660 kb
Host smart-725bedb6-30cd-42f1-a762-a4e720135244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636232299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.636232299
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.3720973215
Short name T131
Test name
Test status
Simulation time 71721912 ps
CPU time 1.09 seconds
Started Jul 21 06:42:12 PM PDT 24
Finished Jul 21 06:42:14 PM PDT 24
Peak memory 220188 kb
Host smart-283265ac-a82f-4532-9a99-d9e01bbbcc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720973215 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.3720973215
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.1188703724
Short name T164
Test name
Test status
Simulation time 19628818 ps
CPU time 0.97 seconds
Started Jul 21 06:42:05 PM PDT 24
Finished Jul 21 06:42:07 PM PDT 24
Peak memory 218844 kb
Host smart-bfe613c3-be8e-4470-bc2a-8b1d301671b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188703724 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1188703724
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.1745801258
Short name T688
Test name
Test status
Simulation time 25471044 ps
CPU time 1.15 seconds
Started Jul 21 06:42:18 PM PDT 24
Finished Jul 21 06:42:21 PM PDT 24
Peak memory 218752 kb
Host smart-3acd62de-d586-4498-9a15-71c91b6570b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745801258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.1745801258
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.911315937
Short name T931
Test name
Test status
Simulation time 29903444 ps
CPU time 1.2 seconds
Started Jul 21 06:41:58 PM PDT 24
Finished Jul 21 06:42:01 PM PDT 24
Peak memory 220112 kb
Host smart-26111bc2-153a-4dac-a53f-93fb483b3697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911315937 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.911315937
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.3486342257
Short name T949
Test name
Test status
Simulation time 30732327 ps
CPU time 1.08 seconds
Started Jul 21 06:41:59 PM PDT 24
Finished Jul 21 06:42:01 PM PDT 24
Peak memory 229816 kb
Host smart-488e7331-a9a8-4db6-b44d-b262cbba9d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486342257 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.3486342257
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.3696630175
Short name T897
Test name
Test status
Simulation time 47080688 ps
CPU time 1.66 seconds
Started Jul 21 06:42:16 PM PDT 24
Finished Jul 21 06:42:19 PM PDT 24
Peak memory 217676 kb
Host smart-489fe94e-0eec-41bf-9be3-cd14c03b20d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696630175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3696630175
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.2407812023
Short name T686
Test name
Test status
Simulation time 36519997 ps
CPU time 1.12 seconds
Started Jul 21 06:42:17 PM PDT 24
Finished Jul 21 06:42:20 PM PDT 24
Peak memory 220460 kb
Host smart-544337f3-df0e-4d88-9ac4-82dfcb747df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407812023 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.2407812023
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.4210112890
Short name T203
Test name
Test status
Simulation time 32341605 ps
CPU time 0.86 seconds
Started Jul 21 06:42:15 PM PDT 24
Finished Jul 21 06:42:17 PM PDT 24
Peak memory 218716 kb
Host smart-86c37205-6184-4fdf-9e17-f77b15073fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210112890 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.4210112890
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/69.edn_alert.772719362
Short name T851
Test name
Test status
Simulation time 90456064 ps
CPU time 1.16 seconds
Started Jul 21 06:42:17 PM PDT 24
Finished Jul 21 06:42:20 PM PDT 24
Peak memory 220168 kb
Host smart-ef1c56ea-ddd3-4015-ba54-562196c08692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772719362 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.772719362
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.1201894123
Short name T464
Test name
Test status
Simulation time 33418003 ps
CPU time 0.87 seconds
Started Jul 21 06:42:06 PM PDT 24
Finished Jul 21 06:42:08 PM PDT 24
Peak memory 218584 kb
Host smart-c85d9902-5096-4ff4-94d7-cc1a98338aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201894123 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.1201894123
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.2071798392
Short name T776
Test name
Test status
Simulation time 46787021 ps
CPU time 1.78 seconds
Started Jul 21 06:42:00 PM PDT 24
Finished Jul 21 06:42:03 PM PDT 24
Peak memory 218900 kb
Host smart-9225cf09-b849-4201-89ad-a61becc19b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071798392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.2071798392
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.112940610
Short name T140
Test name
Test status
Simulation time 47616416 ps
CPU time 1.11 seconds
Started Jul 21 06:40:47 PM PDT 24
Finished Jul 21 06:40:49 PM PDT 24
Peak memory 220944 kb
Host smart-b9c3095b-1df4-4c8d-92da-735df036e123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112940610 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.112940610
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.3565677073
Short name T615
Test name
Test status
Simulation time 53087028 ps
CPU time 0.88 seconds
Started Jul 21 06:40:55 PM PDT 24
Finished Jul 21 06:40:58 PM PDT 24
Peak memory 215140 kb
Host smart-7d700770-da3f-469d-8125-60e5fab31804
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565677073 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.3565677073
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.3387981917
Short name T74
Test name
Test status
Simulation time 13434913 ps
CPU time 0.87 seconds
Started Jul 21 06:40:46 PM PDT 24
Finished Jul 21 06:40:48 PM PDT 24
Peak memory 216288 kb
Host smart-7e98a274-4f46-4bf1-ac6a-fc2d54736c0b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387981917 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3387981917
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.3501894646
Short name T872
Test name
Test status
Simulation time 177164395 ps
CPU time 1.19 seconds
Started Jul 21 06:40:49 PM PDT 24
Finished Jul 21 06:40:52 PM PDT 24
Peak memory 218932 kb
Host smart-bb62a405-9554-481f-bb9f-17be219d339c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501894646 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.3501894646
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.659528722
Short name T119
Test name
Test status
Simulation time 26187657 ps
CPU time 0.98 seconds
Started Jul 21 06:40:46 PM PDT 24
Finished Jul 21 06:40:48 PM PDT 24
Peak memory 220024 kb
Host smart-8691d109-f4aa-4d3d-968d-661964ff1c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659528722 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.659528722
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.1258989688
Short name T561
Test name
Test status
Simulation time 51979626 ps
CPU time 1.79 seconds
Started Jul 21 06:40:51 PM PDT 24
Finished Jul 21 06:40:55 PM PDT 24
Peak memory 220392 kb
Host smart-d0137c3e-4bdc-43bf-a580-a474d32e596d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258989688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1258989688
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_regwen.741663202
Short name T297
Test name
Test status
Simulation time 28796945 ps
CPU time 0.99 seconds
Started Jul 21 06:40:45 PM PDT 24
Finished Jul 21 06:40:47 PM PDT 24
Peak memory 207360 kb
Host smart-2d886a00-c124-4bc4-b2d6-5e66197fb652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741663202 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.741663202
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.2169551442
Short name T901
Test name
Test status
Simulation time 25291980 ps
CPU time 0.95 seconds
Started Jul 21 06:40:46 PM PDT 24
Finished Jul 21 06:40:48 PM PDT 24
Peak memory 215580 kb
Host smart-3b6321d0-bbb6-4899-adaa-738de1380990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169551442 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.2169551442
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.1047311418
Short name T765
Test name
Test status
Simulation time 108145315 ps
CPU time 1.85 seconds
Started Jul 21 06:40:47 PM PDT 24
Finished Jul 21 06:40:50 PM PDT 24
Peak memory 217524 kb
Host smart-12386bcc-d508-44bd-8231-6d7e4d3c3ddb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047311418 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1047311418
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2208791236
Short name T223
Test name
Test status
Simulation time 47646156972 ps
CPU time 260.54 seconds
Started Jul 21 06:40:48 PM PDT 24
Finished Jul 21 06:45:09 PM PDT 24
Peak memory 224056 kb
Host smart-7603a195-e384-4a6f-bd5a-a59e367d2c1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208791236 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.2208791236
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.3399783941
Short name T718
Test name
Test status
Simulation time 78258534 ps
CPU time 1.16 seconds
Started Jul 21 06:42:05 PM PDT 24
Finished Jul 21 06:42:07 PM PDT 24
Peak memory 219848 kb
Host smart-ddae5c0f-71ce-450d-a754-2f4ffe3eb38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399783941 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.3399783941
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.1128910621
Short name T211
Test name
Test status
Simulation time 24826886 ps
CPU time 0.98 seconds
Started Jul 21 06:42:01 PM PDT 24
Finished Jul 21 06:42:03 PM PDT 24
Peak memory 220048 kb
Host smart-24fcb528-864a-430f-b741-5ce27bd9f05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128910621 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.1128910621
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.612129161
Short name T361
Test name
Test status
Simulation time 35827594 ps
CPU time 1.2 seconds
Started Jul 21 06:42:19 PM PDT 24
Finished Jul 21 06:42:21 PM PDT 24
Peak memory 217588 kb
Host smart-fd97374f-9abc-45fb-bb76-e58a4555fc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612129161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.612129161
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.3336339166
Short name T471
Test name
Test status
Simulation time 68008771 ps
CPU time 1.06 seconds
Started Jul 21 06:42:14 PM PDT 24
Finished Jul 21 06:42:16 PM PDT 24
Peak memory 219052 kb
Host smart-c892bb60-056b-45db-8635-705776b6ede4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336339166 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.3336339166
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.3151192412
Short name T113
Test name
Test status
Simulation time 24772551 ps
CPU time 1.34 seconds
Started Jul 21 06:42:13 PM PDT 24
Finished Jul 21 06:42:16 PM PDT 24
Peak memory 230004 kb
Host smart-056e7229-512b-4441-9cf0-2ae9997633b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151192412 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.3151192412
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.3950531537
Short name T726
Test name
Test status
Simulation time 77604384 ps
CPU time 1.29 seconds
Started Jul 21 06:42:09 PM PDT 24
Finished Jul 21 06:42:11 PM PDT 24
Peak memory 218932 kb
Host smart-3384d42f-6dd5-4d23-b35c-e80fa4d829c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950531537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.3950531537
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.923131894
Short name T219
Test name
Test status
Simulation time 62585068 ps
CPU time 1.14 seconds
Started Jul 21 06:41:59 PM PDT 24
Finished Jul 21 06:42:01 PM PDT 24
Peak memory 219624 kb
Host smart-630623e1-04ea-4a2e-a5f0-3d0d1bbfa5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923131894 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.923131894
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.1746636058
Short name T997
Test name
Test status
Simulation time 25435608 ps
CPU time 1.21 seconds
Started Jul 21 06:42:16 PM PDT 24
Finished Jul 21 06:42:19 PM PDT 24
Peak memory 218736 kb
Host smart-093ed78c-4f94-4bd3-a604-c1cfc38dce6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746636058 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.1746636058
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.3358951053
Short name T819
Test name
Test status
Simulation time 126904410 ps
CPU time 1.96 seconds
Started Jul 21 06:42:08 PM PDT 24
Finished Jul 21 06:42:10 PM PDT 24
Peak memory 220416 kb
Host smart-74984839-c376-4ec0-aac2-6765f5991b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358951053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.3358951053
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.634424020
Short name T854
Test name
Test status
Simulation time 112063533 ps
CPU time 1.25 seconds
Started Jul 21 06:42:07 PM PDT 24
Finished Jul 21 06:42:10 PM PDT 24
Peak memory 219348 kb
Host smart-ae884280-6c56-4d37-82dd-e1697114eecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634424020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.634424020
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.2927235760
Short name T155
Test name
Test status
Simulation time 32766795 ps
CPU time 0.88 seconds
Started Jul 21 06:42:08 PM PDT 24
Finished Jul 21 06:42:10 PM PDT 24
Peak memory 218604 kb
Host smart-bf48005c-26d3-4d75-829c-ec0c603c2312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927235760 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.2927235760
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.3984740983
Short name T301
Test name
Test status
Simulation time 52575191 ps
CPU time 1.27 seconds
Started Jul 21 06:42:20 PM PDT 24
Finished Jul 21 06:42:23 PM PDT 24
Peak memory 218652 kb
Host smart-a76db078-1aa3-4b26-8913-4a44c56c8727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984740983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.3984740983
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.2780911581
Short name T413
Test name
Test status
Simulation time 84105217 ps
CPU time 1.04 seconds
Started Jul 21 06:42:12 PM PDT 24
Finished Jul 21 06:42:14 PM PDT 24
Peak memory 218972 kb
Host smart-ce96b9a3-e19b-46d1-ae93-a43e44c55f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780911581 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.2780911581
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.858044233
Short name T206
Test name
Test status
Simulation time 21628508 ps
CPU time 1 seconds
Started Jul 21 06:42:14 PM PDT 24
Finished Jul 21 06:42:16 PM PDT 24
Peak memory 219724 kb
Host smart-4671e060-658a-434f-a27b-a5787e558892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858044233 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.858044233
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.2568118218
Short name T664
Test name
Test status
Simulation time 80579413 ps
CPU time 1.11 seconds
Started Jul 21 06:42:07 PM PDT 24
Finished Jul 21 06:42:09 PM PDT 24
Peak memory 217484 kb
Host smart-c40b8851-2b7c-48ec-afe5-397572da695f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568118218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2568118218
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.574180797
Short name T189
Test name
Test status
Simulation time 29682134 ps
CPU time 1.34 seconds
Started Jul 21 06:42:34 PM PDT 24
Finished Jul 21 06:42:36 PM PDT 24
Peak memory 221056 kb
Host smart-afea5775-c44f-4c53-8a06-ad22830ce4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574180797 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.574180797
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.844913412
Short name T212
Test name
Test status
Simulation time 55705038 ps
CPU time 1.14 seconds
Started Jul 21 06:42:08 PM PDT 24
Finished Jul 21 06:42:10 PM PDT 24
Peak memory 220060 kb
Host smart-6a5db0b7-1b53-438a-8b2a-a5eeed000d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844913412 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.844913412
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.3225237031
Short name T498
Test name
Test status
Simulation time 106041702 ps
CPU time 1.31 seconds
Started Jul 21 06:42:27 PM PDT 24
Finished Jul 21 06:42:29 PM PDT 24
Peak memory 219052 kb
Host smart-db1e0485-74e4-4cd7-a83b-611e4dc68861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225237031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.3225237031
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.1426583059
Short name T290
Test name
Test status
Simulation time 148860430 ps
CPU time 1.22 seconds
Started Jul 21 06:42:07 PM PDT 24
Finished Jul 21 06:42:09 PM PDT 24
Peak memory 220816 kb
Host smart-3b0c3627-7bc9-41e5-a549-d5b7367bde48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426583059 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.1426583059
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.236988921
Short name T756
Test name
Test status
Simulation time 33936601 ps
CPU time 1.16 seconds
Started Jul 21 06:42:34 PM PDT 24
Finished Jul 21 06:42:37 PM PDT 24
Peak memory 220980 kb
Host smart-dd22761c-1f60-4c3c-aafb-5b908d2e1e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236988921 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.236988921
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.2678877574
Short name T746
Test name
Test status
Simulation time 57725011 ps
CPU time 1.98 seconds
Started Jul 21 06:42:29 PM PDT 24
Finished Jul 21 06:42:32 PM PDT 24
Peak memory 220212 kb
Host smart-a6207ae8-1b9d-4479-828f-9488ea90621c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678877574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2678877574
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.781031168
Short name T866
Test name
Test status
Simulation time 90369110 ps
CPU time 1.15 seconds
Started Jul 21 06:42:08 PM PDT 24
Finished Jul 21 06:42:11 PM PDT 24
Peak memory 219916 kb
Host smart-db07a7d7-5d96-40c7-ad93-41068138caaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781031168 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.781031168
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.2114257583
Short name T58
Test name
Test status
Simulation time 73063390 ps
CPU time 1.08 seconds
Started Jul 21 06:42:07 PM PDT 24
Finished Jul 21 06:42:09 PM PDT 24
Peak memory 219868 kb
Host smart-c0abbfb0-1615-4f86-9a01-d88ebe8646f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114257583 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.2114257583
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.2169772404
Short name T878
Test name
Test status
Simulation time 108386440 ps
CPU time 1.45 seconds
Started Jul 21 06:42:07 PM PDT 24
Finished Jul 21 06:42:10 PM PDT 24
Peak memory 217708 kb
Host smart-46e0107f-8290-4514-9e4a-a26c99daca5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169772404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.2169772404
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.3298359390
Short name T110
Test name
Test status
Simulation time 236251744 ps
CPU time 1.18 seconds
Started Jul 21 06:42:11 PM PDT 24
Finished Jul 21 06:42:13 PM PDT 24
Peak memory 218748 kb
Host smart-d4477d7f-51fd-41fb-838d-3dabc718ba27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298359390 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.3298359390
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.655575812
Short name T540
Test name
Test status
Simulation time 32102979 ps
CPU time 0.9 seconds
Started Jul 21 06:42:22 PM PDT 24
Finished Jul 21 06:42:24 PM PDT 24
Peak memory 218524 kb
Host smart-3b016098-dbbf-4e06-a462-919174657f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655575812 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.655575812
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.39150179
Short name T862
Test name
Test status
Simulation time 53354456 ps
CPU time 1.85 seconds
Started Jul 21 06:42:23 PM PDT 24
Finished Jul 21 06:42:27 PM PDT 24
Peak memory 215552 kb
Host smart-5eff98f4-4e91-4409-9890-13f3ba10488a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39150179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.39150179
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.3274807255
Short name T833
Test name
Test status
Simulation time 82502851 ps
CPU time 1.09 seconds
Started Jul 21 06:42:05 PM PDT 24
Finished Jul 21 06:42:07 PM PDT 24
Peak memory 220132 kb
Host smart-219a5760-5101-4adc-859f-35d307eb66fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274807255 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.3274807255
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.2062188760
Short name T476
Test name
Test status
Simulation time 24366709 ps
CPU time 0.93 seconds
Started Jul 21 06:42:26 PM PDT 24
Finished Jul 21 06:42:28 PM PDT 24
Peak memory 218968 kb
Host smart-3c64c8c9-c1c3-4227-8947-de634db5ec5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062188760 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.2062188760
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.2238957891
Short name T339
Test name
Test status
Simulation time 72538536 ps
CPU time 1.43 seconds
Started Jul 21 06:42:27 PM PDT 24
Finished Jul 21 06:42:30 PM PDT 24
Peak memory 220328 kb
Host smart-f39370c4-a551-4f16-9eae-9106f0de4b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238957891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.2238957891
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.1571265025
Short name T984
Test name
Test status
Simulation time 123880792 ps
CPU time 1.15 seconds
Started Jul 21 06:40:48 PM PDT 24
Finished Jul 21 06:40:50 PM PDT 24
Peak memory 219944 kb
Host smart-1da77b0e-e0ea-400c-a5c9-b7d2d05ce5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571265025 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.1571265025
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.2776852078
Short name T593
Test name
Test status
Simulation time 13432609 ps
CPU time 0.86 seconds
Started Jul 21 06:40:51 PM PDT 24
Finished Jul 21 06:40:54 PM PDT 24
Peak memory 207280 kb
Host smart-59e6e7c2-d0a7-46f1-a7a0-6d20ba57653e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776852078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2776852078
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.3895457465
Short name T15
Test name
Test status
Simulation time 94665511 ps
CPU time 1.12 seconds
Started Jul 21 06:40:56 PM PDT 24
Finished Jul 21 06:40:59 PM PDT 24
Peak memory 217092 kb
Host smart-23361923-fbc8-478c-97ad-d9b6e8c9fdf5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895457465 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.3895457465
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.673683576
Short name T162
Test name
Test status
Simulation time 25001244 ps
CPU time 1.05 seconds
Started Jul 21 06:40:48 PM PDT 24
Finished Jul 21 06:40:50 PM PDT 24
Peak memory 224240 kb
Host smart-04b1ee2c-d8d1-4c00-b396-2c6b3a6fda38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673683576 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.673683576
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.851051976
Short name T832
Test name
Test status
Simulation time 48256939 ps
CPU time 1.55 seconds
Started Jul 21 06:40:50 PM PDT 24
Finished Jul 21 06:40:53 PM PDT 24
Peak memory 218780 kb
Host smart-adfd5ff7-da7e-428a-8df9-76c69c69570e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851051976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.851051976
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.1452081110
Short name T447
Test name
Test status
Simulation time 25183847 ps
CPU time 0.94 seconds
Started Jul 21 06:40:55 PM PDT 24
Finished Jul 21 06:40:58 PM PDT 24
Peak memory 215796 kb
Host smart-44de749c-fee0-4aa4-841a-afef092080ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452081110 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.1452081110
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.1200435687
Short name T291
Test name
Test status
Simulation time 33362661 ps
CPU time 0.83 seconds
Started Jul 21 06:40:55 PM PDT 24
Finished Jul 21 06:40:58 PM PDT 24
Peak memory 207304 kb
Host smart-ce4d28dd-6499-4ee3-a00c-08383e24fe1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200435687 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.1200435687
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.4074907436
Short name T372
Test name
Test status
Simulation time 29049409 ps
CPU time 0.92 seconds
Started Jul 21 06:40:55 PM PDT 24
Finished Jul 21 06:40:58 PM PDT 24
Peak memory 215500 kb
Host smart-91e55c46-6855-4bdd-a478-e6f629750dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074907436 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.4074907436
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.598557333
Short name T568
Test name
Test status
Simulation time 393461562 ps
CPU time 5.39 seconds
Started Jul 21 06:40:50 PM PDT 24
Finished Jul 21 06:40:57 PM PDT 24
Peak memory 215616 kb
Host smart-a17e462e-a8d2-433c-a57a-2ca61de091eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598557333 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.598557333
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.1400504631
Short name T842
Test name
Test status
Simulation time 42495299075 ps
CPU time 422.58 seconds
Started Jul 21 06:40:49 PM PDT 24
Finished Jul 21 06:47:53 PM PDT 24
Peak memory 223972 kb
Host smart-6f29af7f-d994-4741-bbc6-422d0a6f2fdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400504631 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.1400504631
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.3564255688
Short name T858
Test name
Test status
Simulation time 25246528 ps
CPU time 1.26 seconds
Started Jul 21 06:42:08 PM PDT 24
Finished Jul 21 06:42:10 PM PDT 24
Peak memory 218988 kb
Host smart-d5244db4-7b7e-4cad-bb9a-38177911ef1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564255688 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.3564255688
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.2322847764
Short name T173
Test name
Test status
Simulation time 42362971 ps
CPU time 0.88 seconds
Started Jul 21 06:42:08 PM PDT 24
Finished Jul 21 06:42:10 PM PDT 24
Peak memory 218464 kb
Host smart-44590959-ebc7-4075-b5fa-b2868af95228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322847764 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.2322847764
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.388074342
Short name T843
Test name
Test status
Simulation time 38062605 ps
CPU time 1.36 seconds
Started Jul 21 06:42:15 PM PDT 24
Finished Jul 21 06:42:17 PM PDT 24
Peak memory 218764 kb
Host smart-8ce63c73-821a-4411-9c3b-bb466fbe161f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388074342 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.388074342
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.2893983240
Short name T996
Test name
Test status
Simulation time 83930079 ps
CPU time 1.15 seconds
Started Jul 21 06:42:21 PM PDT 24
Finished Jul 21 06:42:24 PM PDT 24
Peak memory 215984 kb
Host smart-ba3d9a8a-1365-4122-b334-a6d1ed4d1f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893983240 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.2893983240
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.734499253
Short name T670
Test name
Test status
Simulation time 53075780 ps
CPU time 1.21 seconds
Started Jul 21 06:42:29 PM PDT 24
Finished Jul 21 06:42:30 PM PDT 24
Peak memory 219944 kb
Host smart-8d80518b-22b8-43f3-adae-dc560b0e1680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734499253 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.734499253
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.4164775610
Short name T551
Test name
Test status
Simulation time 414629040 ps
CPU time 1.36 seconds
Started Jul 21 06:42:12 PM PDT 24
Finished Jul 21 06:42:14 PM PDT 24
Peak memory 220404 kb
Host smart-6bb9e4d8-db69-411f-bc7f-5d2b1f9002ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164775610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.4164775610
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.2821302724
Short name T752
Test name
Test status
Simulation time 28363934 ps
CPU time 1.27 seconds
Started Jul 21 06:42:21 PM PDT 24
Finished Jul 21 06:42:24 PM PDT 24
Peak memory 220244 kb
Host smart-7df112d2-72a7-4e45-82e9-fe8428fbd6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821302724 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.2821302724
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.3472986067
Short name T892
Test name
Test status
Simulation time 19900310 ps
CPU time 1.24 seconds
Started Jul 21 06:42:25 PM PDT 24
Finished Jul 21 06:42:27 PM PDT 24
Peak memory 229844 kb
Host smart-e5b9d0af-905b-4042-a6a3-31ea91000e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472986067 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.3472986067
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.2310881818
Short name T537
Test name
Test status
Simulation time 94950220 ps
CPU time 1.48 seconds
Started Jul 21 06:42:17 PM PDT 24
Finished Jul 21 06:42:21 PM PDT 24
Peak memory 219292 kb
Host smart-1ae41340-691f-4306-b5e2-1cb3b31c0031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310881818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.2310881818
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.3446549591
Short name T659
Test name
Test status
Simulation time 192402054 ps
CPU time 1.35 seconds
Started Jul 21 06:42:06 PM PDT 24
Finished Jul 21 06:42:09 PM PDT 24
Peak memory 216084 kb
Host smart-aecae703-2461-4cbc-a041-3b74704b2578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446549591 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.3446549591
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.1241699268
Short name T558
Test name
Test status
Simulation time 31524654 ps
CPU time 1.04 seconds
Started Jul 21 06:42:20 PM PDT 24
Finished Jul 21 06:42:23 PM PDT 24
Peak memory 224328 kb
Host smart-7ee2b36b-92ca-463f-991a-db4a57c2e476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241699268 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.1241699268
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.100155713
Short name T646
Test name
Test status
Simulation time 85502426 ps
CPU time 1.21 seconds
Started Jul 21 06:42:16 PM PDT 24
Finished Jul 21 06:42:19 PM PDT 24
Peak memory 217548 kb
Host smart-939547ba-92f4-4842-b9cb-22500f834b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100155713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.100155713
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.2946157773
Short name T187
Test name
Test status
Simulation time 93943089 ps
CPU time 1.16 seconds
Started Jul 21 06:42:12 PM PDT 24
Finished Jul 21 06:42:13 PM PDT 24
Peak memory 220116 kb
Host smart-670680eb-e310-4a0d-80ca-07d44e7f81f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946157773 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.2946157773
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.1584497554
Short name T488
Test name
Test status
Simulation time 68211580 ps
CPU time 1.06 seconds
Started Jul 21 06:42:07 PM PDT 24
Finished Jul 21 06:42:09 PM PDT 24
Peak memory 220028 kb
Host smart-0c6207de-fdc3-4655-949c-163258bcb395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584497554 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.1584497554
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.2566220333
Short name T806
Test name
Test status
Simulation time 38279626 ps
CPU time 1.44 seconds
Started Jul 21 06:42:11 PM PDT 24
Finished Jul 21 06:42:13 PM PDT 24
Peak memory 218712 kb
Host smart-23b1a059-c7d7-466c-93aa-ef50eb8391db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566220333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.2566220333
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.3914277557
Short name T78
Test name
Test status
Simulation time 98220350 ps
CPU time 1.27 seconds
Started Jul 21 06:42:08 PM PDT 24
Finished Jul 21 06:42:11 PM PDT 24
Peak memory 216008 kb
Host smart-3ea389b7-742f-4479-b555-7e2b75ad07c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914277557 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.3914277557
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.3839508607
Short name T519
Test name
Test status
Simulation time 36339939 ps
CPU time 1.06 seconds
Started Jul 21 06:42:22 PM PDT 24
Finished Jul 21 06:42:25 PM PDT 24
Peak memory 221032 kb
Host smart-aedf9ae4-13ae-4c3b-9631-9e5f111189f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839508607 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.3839508607
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.3326546139
Short name T331
Test name
Test status
Simulation time 35693206 ps
CPU time 1.44 seconds
Started Jul 21 06:42:10 PM PDT 24
Finished Jul 21 06:42:12 PM PDT 24
Peak memory 220156 kb
Host smart-9c09f5e6-f0e1-452c-be5b-61f8928d81d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326546139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3326546139
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.193600969
Short name T148
Test name
Test status
Simulation time 75133098 ps
CPU time 1.16 seconds
Started Jul 21 06:42:11 PM PDT 24
Finished Jul 21 06:42:13 PM PDT 24
Peak memory 218960 kb
Host smart-7625410f-ae7b-4638-8a92-2960fe92db84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193600969 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.193600969
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.602829291
Short name T760
Test name
Test status
Simulation time 24358696 ps
CPU time 1.17 seconds
Started Jul 21 06:42:18 PM PDT 24
Finished Jul 21 06:42:21 PM PDT 24
Peak memory 218864 kb
Host smart-3069956f-3ced-4292-a996-1b3313411be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602829291 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.602829291
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.516211700
Short name T774
Test name
Test status
Simulation time 52131177 ps
CPU time 1.77 seconds
Started Jul 21 06:42:09 PM PDT 24
Finished Jul 21 06:42:12 PM PDT 24
Peak memory 218944 kb
Host smart-7745d520-6eba-465c-a9c5-d882caba1aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516211700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.516211700
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.2400618116
Short name T839
Test name
Test status
Simulation time 27599288 ps
CPU time 1.29 seconds
Started Jul 21 06:42:28 PM PDT 24
Finished Jul 21 06:42:30 PM PDT 24
Peak memory 220900 kb
Host smart-3e39ea1a-1ad3-49b9-ac47-fd2fbf404fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400618116 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.2400618116
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.2831223120
Short name T621
Test name
Test status
Simulation time 27335110 ps
CPU time 0.95 seconds
Started Jul 21 06:42:27 PM PDT 24
Finished Jul 21 06:42:29 PM PDT 24
Peak memory 224052 kb
Host smart-b877d3e9-f330-41f4-8342-b27e083021fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831223120 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.2831223120
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.2930470817
Short name T888
Test name
Test status
Simulation time 95995211 ps
CPU time 1.38 seconds
Started Jul 21 06:42:11 PM PDT 24
Finished Jul 21 06:42:13 PM PDT 24
Peak memory 219016 kb
Host smart-9ca18b1d-75b4-44c9-adc6-f4eb830f6d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930470817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2930470817
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.3846833486
Short name T571
Test name
Test status
Simulation time 25242466 ps
CPU time 1.22 seconds
Started Jul 21 06:42:06 PM PDT 24
Finished Jul 21 06:42:07 PM PDT 24
Peak memory 218872 kb
Host smart-e493df8f-31d8-4381-a3ff-a0c9668f1e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846833486 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.3846833486
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.2381737893
Short name T114
Test name
Test status
Simulation time 30997527 ps
CPU time 1.09 seconds
Started Jul 21 06:42:22 PM PDT 24
Finished Jul 21 06:42:25 PM PDT 24
Peak memory 220040 kb
Host smart-d15dd752-6d08-4cfd-9246-c56bc5eb411d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381737893 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.2381737893
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1918425022
Short name T620
Test name
Test status
Simulation time 33958532 ps
CPU time 1.48 seconds
Started Jul 21 06:42:09 PM PDT 24
Finished Jul 21 06:42:11 PM PDT 24
Peak memory 218752 kb
Host smart-4ab22e11-c41b-474c-9025-ba1afdbf9152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918425022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1918425022
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.1258896088
Short name T773
Test name
Test status
Simulation time 26646832 ps
CPU time 1.23 seconds
Started Jul 21 06:42:08 PM PDT 24
Finished Jul 21 06:42:11 PM PDT 24
Peak memory 221016 kb
Host smart-a14976d0-be5a-4f10-8c65-9128606abd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258896088 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.1258896088
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.462740691
Short name T945
Test name
Test status
Simulation time 132660685 ps
CPU time 0.99 seconds
Started Jul 21 06:42:08 PM PDT 24
Finished Jul 21 06:42:11 PM PDT 24
Peak memory 218916 kb
Host smart-4a93c834-ed3a-4aef-919e-e2e73cb7c9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462740691 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.462740691
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.1317674362
Short name T386
Test name
Test status
Simulation time 105842282 ps
CPU time 1.38 seconds
Started Jul 21 06:42:10 PM PDT 24
Finished Jul 21 06:42:12 PM PDT 24
Peak memory 220356 kb
Host smart-bece12c4-627b-4a69-9094-a09213453b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317674362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.1317674362
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.2161227936
Short name T279
Test name
Test status
Simulation time 23978019 ps
CPU time 1.2 seconds
Started Jul 21 06:40:56 PM PDT 24
Finished Jul 21 06:40:59 PM PDT 24
Peak memory 218868 kb
Host smart-4f750e52-4f4d-4670-8ced-e0fdeee226e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161227936 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.2161227936
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.1894318011
Short name T761
Test name
Test status
Simulation time 19099272 ps
CPU time 1.02 seconds
Started Jul 21 06:40:51 PM PDT 24
Finished Jul 21 06:40:54 PM PDT 24
Peak memory 215148 kb
Host smart-0f91a77d-e912-4f6b-a44c-0d89fb621132
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894318011 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1894318011
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.715463956
Short name T967
Test name
Test status
Simulation time 45008104 ps
CPU time 1.07 seconds
Started Jul 21 06:40:49 PM PDT 24
Finished Jul 21 06:40:51 PM PDT 24
Peak memory 219728 kb
Host smart-33f88636-94a6-4917-b63c-d316371a7019
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715463956 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_dis
able_auto_req_mode.715463956
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.504584795
Short name T142
Test name
Test status
Simulation time 52872790 ps
CPU time 1.12 seconds
Started Jul 21 06:40:51 PM PDT 24
Finished Jul 21 06:40:54 PM PDT 24
Peak memory 230044 kb
Host smart-0d35f613-a0af-432f-a06d-7473fd34c6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504584795 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.504584795
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.2444254843
Short name T589
Test name
Test status
Simulation time 51368653 ps
CPU time 1.06 seconds
Started Jul 21 06:40:49 PM PDT 24
Finished Jul 21 06:40:51 PM PDT 24
Peak memory 217672 kb
Host smart-14c619b4-f605-461d-8a15-c3be35890ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444254843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.2444254843
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.3152831098
Short name T93
Test name
Test status
Simulation time 19766595 ps
CPU time 1.06 seconds
Started Jul 21 06:40:51 PM PDT 24
Finished Jul 21 06:40:54 PM PDT 24
Peak memory 216068 kb
Host smart-3014ac79-cad4-46c8-b3a5-d522885946ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152831098 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.3152831098
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.2002097486
Short name T233
Test name
Test status
Simulation time 36732890 ps
CPU time 0.99 seconds
Started Jul 21 06:40:56 PM PDT 24
Finished Jul 21 06:40:59 PM PDT 24
Peak memory 207248 kb
Host smart-bb6b7b85-9c5f-45f3-b30e-2ae4992be141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002097486 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2002097486
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.1964356275
Short name T369
Test name
Test status
Simulation time 44423486 ps
CPU time 0.96 seconds
Started Jul 21 06:40:51 PM PDT 24
Finished Jul 21 06:40:54 PM PDT 24
Peak memory 207460 kb
Host smart-4be3a28a-6e07-4659-b4f8-82dead394b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964356275 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.1964356275
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.3853127160
Short name T572
Test name
Test status
Simulation time 64839154 ps
CPU time 1.43 seconds
Started Jul 21 06:40:53 PM PDT 24
Finished Jul 21 06:40:56 PM PDT 24
Peak memory 218736 kb
Host smart-c2ac9267-2ffa-4567-88ec-2b97c8a49031
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853127160 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.3853127160
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.54703199
Short name T94
Test name
Test status
Simulation time 342780713986 ps
CPU time 1927.64 seconds
Started Jul 21 06:40:50 PM PDT 24
Finished Jul 21 07:13:00 PM PDT 24
Peak memory 227228 kb
Host smart-9ff5f577-61d1-46a3-b790-1fe8a59c1588
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54703199 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.54703199
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.240114102
Short name T557
Test name
Test status
Simulation time 44948395 ps
CPU time 1.14 seconds
Started Jul 21 06:42:29 PM PDT 24
Finished Jul 21 06:42:31 PM PDT 24
Peak memory 219716 kb
Host smart-df304114-9cc9-4df3-8128-d8c243797b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240114102 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.240114102
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.3037828094
Short name T438
Test name
Test status
Simulation time 19792820 ps
CPU time 1.13 seconds
Started Jul 21 06:42:08 PM PDT 24
Finished Jul 21 06:42:11 PM PDT 24
Peak memory 218656 kb
Host smart-fd7a1968-792c-4622-a6e5-385877d74baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037828094 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.3037828094
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.2706825267
Short name T741
Test name
Test status
Simulation time 48516634 ps
CPU time 1.32 seconds
Started Jul 21 06:42:27 PM PDT 24
Finished Jul 21 06:42:30 PM PDT 24
Peak memory 217456 kb
Host smart-e6f01168-50a4-49ce-841d-7963ede9a20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706825267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.2706825267
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.539163538
Short name T436
Test name
Test status
Simulation time 297298920 ps
CPU time 1.16 seconds
Started Jul 21 06:42:24 PM PDT 24
Finished Jul 21 06:42:26 PM PDT 24
Peak memory 219152 kb
Host smart-70815da1-e042-46c9-907f-e62c038ffab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539163538 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.539163538
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.3251865442
Short name T644
Test name
Test status
Simulation time 28701005 ps
CPU time 1.27 seconds
Started Jul 21 06:42:21 PM PDT 24
Finished Jul 21 06:42:23 PM PDT 24
Peak memory 221204 kb
Host smart-6be86efb-b008-41ee-a674-75e109b615ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251865442 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3251865442
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.1179274758
Short name T790
Test name
Test status
Simulation time 37877473 ps
CPU time 1.16 seconds
Started Jul 21 06:42:13 PM PDT 24
Finished Jul 21 06:42:15 PM PDT 24
Peak memory 217772 kb
Host smart-fb28227d-7050-47b0-bc1f-6ec57956e687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179274758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.1179274758
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.613928917
Short name T539
Test name
Test status
Simulation time 69805771 ps
CPU time 1.16 seconds
Started Jul 21 06:42:08 PM PDT 24
Finished Jul 21 06:42:10 PM PDT 24
Peak memory 221072 kb
Host smart-996aa38c-e24f-49a3-a7fc-e9e3a6150846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613928917 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.613928917
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.36684752
Short name T722
Test name
Test status
Simulation time 27314213 ps
CPU time 1.23 seconds
Started Jul 21 06:42:28 PM PDT 24
Finished Jul 21 06:42:30 PM PDT 24
Peak memory 229984 kb
Host smart-7b42da2b-a99c-4484-9f49-1b9ccffeb34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36684752 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.36684752
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.837625120
Short name T309
Test name
Test status
Simulation time 72399631 ps
CPU time 1.35 seconds
Started Jul 21 06:42:17 PM PDT 24
Finished Jul 21 06:42:20 PM PDT 24
Peak memory 219200 kb
Host smart-09e46b3e-393b-4a6a-9364-3ca88ba2bf82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837625120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.837625120
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.3381996598
Short name T987
Test name
Test status
Simulation time 141237298 ps
CPU time 1.33 seconds
Started Jul 21 06:42:16 PM PDT 24
Finished Jul 21 06:42:18 PM PDT 24
Peak memory 218920 kb
Host smart-b75e665a-bf78-46cf-a7f8-55e0b84e8a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381996598 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.3381996598
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.4064146362
Short name T998
Test name
Test status
Simulation time 28433361 ps
CPU time 0.97 seconds
Started Jul 21 06:42:26 PM PDT 24
Finished Jul 21 06:42:28 PM PDT 24
Peak memory 229632 kb
Host smart-6f3ffe26-1fb1-437d-934a-354535983b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064146362 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.4064146362
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.2276221425
Short name T758
Test name
Test status
Simulation time 60755195 ps
CPU time 1.26 seconds
Started Jul 21 06:42:14 PM PDT 24
Finished Jul 21 06:42:16 PM PDT 24
Peak memory 217488 kb
Host smart-5daba8f6-c1f6-4477-b6c6-d207e7019a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276221425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2276221425
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.473798920
Short name T296
Test name
Test status
Simulation time 79088153 ps
CPU time 1.2 seconds
Started Jul 21 06:42:13 PM PDT 24
Finished Jul 21 06:42:15 PM PDT 24
Peak memory 219964 kb
Host smart-dbc2ed07-6b2c-47c7-a084-0be8dfc3f0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473798920 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.473798920
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.159916617
Short name T655
Test name
Test status
Simulation time 30668716 ps
CPU time 0.88 seconds
Started Jul 21 06:42:24 PM PDT 24
Finished Jul 21 06:42:26 PM PDT 24
Peak memory 218568 kb
Host smart-7462fd5d-2817-4098-b6e7-c0358a7ab4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159916617 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.159916617
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.1381921040
Short name T490
Test name
Test status
Simulation time 44218786 ps
CPU time 1.57 seconds
Started Jul 21 06:42:13 PM PDT 24
Finished Jul 21 06:42:16 PM PDT 24
Peak memory 218680 kb
Host smart-dfc01e3d-7b17-42be-8390-b3dbc02a4444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381921040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.1381921040
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.3123231421
Short name T840
Test name
Test status
Simulation time 28940528 ps
CPU time 1.35 seconds
Started Jul 21 06:42:21 PM PDT 24
Finished Jul 21 06:42:24 PM PDT 24
Peak memory 218972 kb
Host smart-1314d687-aa89-48a6-a52a-25902f98949e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123231421 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.3123231421
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.2555452914
Short name T196
Test name
Test status
Simulation time 19124482 ps
CPU time 1.1 seconds
Started Jul 21 06:42:13 PM PDT 24
Finished Jul 21 06:42:16 PM PDT 24
Peak memory 219896 kb
Host smart-16abfc91-6e29-4d00-93f7-c4087356bee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555452914 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2555452914
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.2657177654
Short name T990
Test name
Test status
Simulation time 38677417 ps
CPU time 1.33 seconds
Started Jul 21 06:42:32 PM PDT 24
Finished Jul 21 06:42:34 PM PDT 24
Peak memory 218636 kb
Host smart-3fad0f64-0ab5-44f1-82b7-20ec71eb556a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657177654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2657177654
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.726275651
Short name T953
Test name
Test status
Simulation time 44798338 ps
CPU time 1.17 seconds
Started Jul 21 06:42:17 PM PDT 24
Finished Jul 21 06:42:20 PM PDT 24
Peak memory 219896 kb
Host smart-a4e340ab-fd43-408a-bc95-867c509e4e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726275651 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.726275651
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.3461584768
Short name T112
Test name
Test status
Simulation time 75825638 ps
CPU time 1.03 seconds
Started Jul 21 06:42:37 PM PDT 24
Finished Jul 21 06:42:39 PM PDT 24
Peak memory 220856 kb
Host smart-10c91e41-0f53-4d08-8110-1f2d63dcadae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461584768 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3461584768
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.2775533949
Short name T421
Test name
Test status
Simulation time 149931845 ps
CPU time 1.47 seconds
Started Jul 21 06:42:38 PM PDT 24
Finished Jul 21 06:42:40 PM PDT 24
Peak memory 218792 kb
Host smart-211e3dc3-315b-4637-b5cb-9b14879310d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775533949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.2775533949
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.2761412965
Short name T137
Test name
Test status
Simulation time 29630135 ps
CPU time 1.24 seconds
Started Jul 21 06:42:20 PM PDT 24
Finished Jul 21 06:42:23 PM PDT 24
Peak memory 220996 kb
Host smart-e6922d97-a8de-4aa9-a798-641a7bb5e9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761412965 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.2761412965
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.1932555531
Short name T565
Test name
Test status
Simulation time 55956897 ps
CPU time 0.99 seconds
Started Jul 21 06:42:38 PM PDT 24
Finished Jul 21 06:42:40 PM PDT 24
Peak memory 221056 kb
Host smart-15b250ca-0a22-41f3-aefd-f27522cdb98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932555531 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.1932555531
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.3431918075
Short name T988
Test name
Test status
Simulation time 28226170 ps
CPU time 1.3 seconds
Started Jul 21 06:42:23 PM PDT 24
Finished Jul 21 06:42:25 PM PDT 24
Peak memory 217640 kb
Host smart-8ee828cc-ee4f-4ae3-a7ec-b82e78644f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431918075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.3431918075
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.3484160863
Short name T709
Test name
Test status
Simulation time 25707144 ps
CPU time 1.21 seconds
Started Jul 21 06:42:24 PM PDT 24
Finished Jul 21 06:42:27 PM PDT 24
Peak memory 216008 kb
Host smart-e833feee-b16d-4cca-8834-1d080f1e96d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484160863 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.3484160863
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.1146203882
Short name T13
Test name
Test status
Simulation time 34040002 ps
CPU time 1.07 seconds
Started Jul 21 06:42:14 PM PDT 24
Finished Jul 21 06:42:16 PM PDT 24
Peak memory 229904 kb
Host smart-2717a25f-7cf7-4d71-a5aa-9a5783fc67ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146203882 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1146203882
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.1791299220
Short name T725
Test name
Test status
Simulation time 103970993 ps
CPU time 1.04 seconds
Started Jul 21 06:42:27 PM PDT 24
Finished Jul 21 06:42:29 PM PDT 24
Peak memory 217396 kb
Host smart-b472109f-8f6d-457b-8a07-794974e7a3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791299220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.1791299220
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.2805247698
Short name T106
Test name
Test status
Simulation time 47277975 ps
CPU time 1.15 seconds
Started Jul 21 06:42:12 PM PDT 24
Finished Jul 21 06:42:14 PM PDT 24
Peak memory 219096 kb
Host smart-6e88e9ea-07ba-4c9b-8121-542793cc44f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805247698 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.2805247698
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.2749081286
Short name T129
Test name
Test status
Simulation time 39162781 ps
CPU time 1.2 seconds
Started Jul 21 06:42:14 PM PDT 24
Finished Jul 21 06:42:16 PM PDT 24
Peak memory 229932 kb
Host smart-2cdc2b14-c0ac-4bf5-a6a0-1112be4af218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749081286 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.2749081286
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.850689707
Short name T708
Test name
Test status
Simulation time 52874991 ps
CPU time 1.34 seconds
Started Jul 21 06:42:16 PM PDT 24
Finished Jul 21 06:42:19 PM PDT 24
Peak memory 217628 kb
Host smart-1c29de20-9e6e-4c55-837f-69b0b7f0cb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850689707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.850689707
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%