Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.83 98.25 93.85 91.61 91.86 96.37 99.77 92.08


Total test records in report: 1130
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T269 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3946346585 Jul 22 06:50:40 PM PDT 24 Jul 22 06:51:04 PM PDT 24 15203236 ps
T1022 /workspace/coverage/cover_reg_top/2.edn_intr_test.1205914566 Jul 22 06:50:15 PM PDT 24 Jul 22 06:50:20 PM PDT 24 24711410 ps
T1023 /workspace/coverage/cover_reg_top/1.edn_intr_test.3826543290 Jul 22 06:50:14 PM PDT 24 Jul 22 06:50:20 PM PDT 24 31213928 ps
T285 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3824219380 Jul 22 06:50:24 PM PDT 24 Jul 22 06:50:40 PM PDT 24 182858577 ps
T1024 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1797692693 Jul 22 06:51:20 PM PDT 24 Jul 22 06:52:12 PM PDT 24 137053441 ps
T1025 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3995120659 Jul 22 06:50:25 PM PDT 24 Jul 22 06:50:42 PM PDT 24 62555854 ps
T1026 /workspace/coverage/cover_reg_top/18.edn_tl_errors.63322529 Jul 22 06:50:51 PM PDT 24 Jul 22 06:51:31 PM PDT 24 104281053 ps
T1027 /workspace/coverage/cover_reg_top/3.edn_csr_rw.2635284271 Jul 22 06:50:28 PM PDT 24 Jul 22 06:50:43 PM PDT 24 118460389 ps
T1028 /workspace/coverage/cover_reg_top/15.edn_csr_rw.3354831559 Jul 22 06:50:42 PM PDT 24 Jul 22 06:51:09 PM PDT 24 20703466 ps
T270 /workspace/coverage/cover_reg_top/5.edn_csr_rw.3013614068 Jul 22 06:50:29 PM PDT 24 Jul 22 06:50:45 PM PDT 24 16526006 ps
T1029 /workspace/coverage/cover_reg_top/16.edn_intr_test.3825303401 Jul 22 06:50:40 PM PDT 24 Jul 22 06:51:04 PM PDT 24 52511391 ps
T1030 /workspace/coverage/cover_reg_top/7.edn_tl_errors.3039173613 Jul 22 06:50:25 PM PDT 24 Jul 22 06:50:40 PM PDT 24 57345729 ps
T1031 /workspace/coverage/cover_reg_top/0.edn_csr_rw.992014534 Jul 22 06:50:15 PM PDT 24 Jul 22 06:50:20 PM PDT 24 21736417 ps
T1032 /workspace/coverage/cover_reg_top/11.edn_csr_rw.706523159 Jul 22 06:51:22 PM PDT 24 Jul 22 06:52:13 PM PDT 24 30795436 ps
T1033 /workspace/coverage/cover_reg_top/13.edn_tl_errors.2210449760 Jul 22 06:50:29 PM PDT 24 Jul 22 06:50:46 PM PDT 24 314399064 ps
T1034 /workspace/coverage/cover_reg_top/39.edn_intr_test.3880303223 Jul 22 06:50:49 PM PDT 24 Jul 22 06:51:25 PM PDT 24 15088648 ps
T1035 /workspace/coverage/cover_reg_top/34.edn_intr_test.494614666 Jul 22 06:50:43 PM PDT 24 Jul 22 06:51:12 PM PDT 24 50046557 ps
T1036 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.529253220 Jul 22 06:50:25 PM PDT 24 Jul 22 06:50:40 PM PDT 24 30907461 ps
T250 /workspace/coverage/cover_reg_top/6.edn_csr_rw.359833224 Jul 22 06:50:23 PM PDT 24 Jul 22 06:50:35 PM PDT 24 32426991 ps
T1037 /workspace/coverage/cover_reg_top/1.edn_tl_errors.860345650 Jul 22 06:50:12 PM PDT 24 Jul 22 06:50:16 PM PDT 24 138297450 ps
T1038 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1092807513 Jul 22 06:50:40 PM PDT 24 Jul 22 06:51:04 PM PDT 24 18418948 ps
T1039 /workspace/coverage/cover_reg_top/28.edn_intr_test.349600798 Jul 22 06:50:38 PM PDT 24 Jul 22 06:51:00 PM PDT 24 18554513 ps
T1040 /workspace/coverage/cover_reg_top/19.edn_tl_errors.28809878 Jul 22 06:50:38 PM PDT 24 Jul 22 06:51:02 PM PDT 24 43887202 ps
T1041 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.834337042 Jul 22 06:50:42 PM PDT 24 Jul 22 06:51:09 PM PDT 24 155231687 ps
T1042 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3374042785 Jul 22 06:50:39 PM PDT 24 Jul 22 06:51:02 PM PDT 24 23513330 ps
T1043 /workspace/coverage/cover_reg_top/21.edn_intr_test.2600268082 Jul 22 06:50:42 PM PDT 24 Jul 22 06:51:09 PM PDT 24 40862430 ps
T1044 /workspace/coverage/cover_reg_top/15.edn_tl_errors.2963980741 Jul 22 06:50:39 PM PDT 24 Jul 22 06:51:02 PM PDT 24 81781819 ps
T1045 /workspace/coverage/cover_reg_top/4.edn_intr_test.1548381486 Jul 22 06:50:31 PM PDT 24 Jul 22 06:50:47 PM PDT 24 18193280 ps
T1046 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.40288828 Jul 22 06:50:43 PM PDT 24 Jul 22 06:51:12 PM PDT 24 19394623 ps
T1047 /workspace/coverage/cover_reg_top/0.edn_tl_errors.3559828308 Jul 22 06:50:14 PM PDT 24 Jul 22 06:50:20 PM PDT 24 105581299 ps
T1048 /workspace/coverage/cover_reg_top/9.edn_tl_errors.2928583662 Jul 22 06:50:27 PM PDT 24 Jul 22 06:50:44 PM PDT 24 156950003 ps
T1049 /workspace/coverage/cover_reg_top/15.edn_intr_test.3417413605 Jul 22 06:50:43 PM PDT 24 Jul 22 06:51:11 PM PDT 24 14303929 ps
T1050 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2882002280 Jul 22 06:50:25 PM PDT 24 Jul 22 06:50:40 PM PDT 24 54518190 ps
T251 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1229239591 Jul 22 06:50:25 PM PDT 24 Jul 22 06:50:40 PM PDT 24 19046935 ps
T1051 /workspace/coverage/cover_reg_top/41.edn_intr_test.1409030831 Jul 22 06:50:48 PM PDT 24 Jul 22 06:51:22 PM PDT 24 14872304 ps
T1052 /workspace/coverage/cover_reg_top/13.edn_intr_test.1839558342 Jul 22 06:50:30 PM PDT 24 Jul 22 06:50:46 PM PDT 24 14890856 ps
T1053 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3317671548 Jul 22 06:50:40 PM PDT 24 Jul 22 06:51:04 PM PDT 24 17417312 ps
T1054 /workspace/coverage/cover_reg_top/10.edn_intr_test.2808051440 Jul 22 06:50:26 PM PDT 24 Jul 22 06:50:41 PM PDT 24 11711319 ps
T1055 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.430568483 Jul 22 06:50:43 PM PDT 24 Jul 22 06:51:11 PM PDT 24 25729793 ps
T1056 /workspace/coverage/cover_reg_top/17.edn_tl_errors.130849073 Jul 22 06:50:37 PM PDT 24 Jul 22 06:51:00 PM PDT 24 846063549 ps
T252 /workspace/coverage/cover_reg_top/17.edn_csr_rw.3503746072 Jul 22 06:50:39 PM PDT 24 Jul 22 06:51:01 PM PDT 24 37883702 ps
T253 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1966577729 Jul 22 06:50:16 PM PDT 24 Jul 22 06:50:24 PM PDT 24 34891658 ps
T1057 /workspace/coverage/cover_reg_top/11.edn_intr_test.841646563 Jul 22 06:51:19 PM PDT 24 Jul 22 06:52:10 PM PDT 24 38968936 ps
T1058 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.4084984502 Jul 22 06:50:27 PM PDT 24 Jul 22 06:50:43 PM PDT 24 223859348 ps
T254 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.25218368 Jul 22 06:50:33 PM PDT 24 Jul 22 06:50:51 PM PDT 24 72464596 ps
T1059 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3448925023 Jul 22 06:50:15 PM PDT 24 Jul 22 06:50:21 PM PDT 24 48144161 ps
T282 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3314794076 Jul 22 06:50:38 PM PDT 24 Jul 22 06:51:01 PM PDT 24 89995086 ps
T1060 /workspace/coverage/cover_reg_top/10.edn_tl_errors.1437519024 Jul 22 06:50:25 PM PDT 24 Jul 22 06:50:42 PM PDT 24 176549020 ps
T1061 /workspace/coverage/cover_reg_top/16.edn_tl_errors.3375816940 Jul 22 06:51:22 PM PDT 24 Jul 22 06:52:14 PM PDT 24 102227408 ps
T1062 /workspace/coverage/cover_reg_top/26.edn_intr_test.2489736795 Jul 22 06:50:40 PM PDT 24 Jul 22 06:51:04 PM PDT 24 11081035 ps
T1063 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.414514948 Jul 22 06:50:40 PM PDT 24 Jul 22 06:51:05 PM PDT 24 49428230 ps
T1064 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.802032780 Jul 22 06:50:40 PM PDT 24 Jul 22 06:51:04 PM PDT 24 37995200 ps
T1065 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.411616165 Jul 22 06:50:25 PM PDT 24 Jul 22 06:50:40 PM PDT 24 34825880 ps
T1066 /workspace/coverage/cover_reg_top/4.edn_tl_errors.338700258 Jul 22 06:50:24 PM PDT 24 Jul 22 06:50:40 PM PDT 24 176566454 ps
T1067 /workspace/coverage/cover_reg_top/36.edn_intr_test.3957868613 Jul 22 06:50:48 PM PDT 24 Jul 22 06:51:23 PM PDT 24 27560717 ps
T1068 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3648823192 Jul 22 06:50:26 PM PDT 24 Jul 22 06:50:41 PM PDT 24 36337541 ps
T1069 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2407448972 Jul 22 06:50:16 PM PDT 24 Jul 22 06:50:24 PM PDT 24 64792264 ps
T1070 /workspace/coverage/cover_reg_top/27.edn_intr_test.1192001012 Jul 22 06:50:41 PM PDT 24 Jul 22 06:51:07 PM PDT 24 24077328 ps
T1071 /workspace/coverage/cover_reg_top/19.edn_intr_test.1504109622 Jul 22 06:50:41 PM PDT 24 Jul 22 06:51:08 PM PDT 24 13427766 ps
T283 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3681775156 Jul 22 06:50:29 PM PDT 24 Jul 22 06:50:46 PM PDT 24 101525337 ps
T1072 /workspace/coverage/cover_reg_top/32.edn_intr_test.3105267787 Jul 22 06:50:38 PM PDT 24 Jul 22 06:51:00 PM PDT 24 14871307 ps
T284 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.941047891 Jul 22 06:50:33 PM PDT 24 Jul 22 06:50:52 PM PDT 24 318529259 ps
T1073 /workspace/coverage/cover_reg_top/25.edn_intr_test.1434858591 Jul 22 06:50:40 PM PDT 24 Jul 22 06:51:04 PM PDT 24 16627990 ps
T1074 /workspace/coverage/cover_reg_top/11.edn_tl_errors.1299457979 Jul 22 06:50:26 PM PDT 24 Jul 22 06:50:43 PM PDT 24 175192097 ps
T1075 /workspace/coverage/cover_reg_top/40.edn_intr_test.3315296660 Jul 22 06:50:48 PM PDT 24 Jul 22 06:51:24 PM PDT 24 56585890 ps
T1076 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.4185910410 Jul 22 06:50:17 PM PDT 24 Jul 22 06:50:25 PM PDT 24 41738273 ps
T1077 /workspace/coverage/cover_reg_top/31.edn_intr_test.880271835 Jul 22 06:50:42 PM PDT 24 Jul 22 06:51:09 PM PDT 24 37506975 ps
T1078 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2931068925 Jul 22 06:50:31 PM PDT 24 Jul 22 06:50:49 PM PDT 24 110957472 ps
T1079 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2659974739 Jul 22 06:50:16 PM PDT 24 Jul 22 06:50:22 PM PDT 24 46793285 ps
T1080 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2105820092 Jul 22 06:50:13 PM PDT 24 Jul 22 06:50:18 PM PDT 24 27314970 ps
T1081 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3811625882 Jul 22 06:50:30 PM PDT 24 Jul 22 06:50:48 PM PDT 24 179446290 ps
T1082 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2218017022 Jul 22 06:50:31 PM PDT 24 Jul 22 06:50:48 PM PDT 24 96939072 ps
T1083 /workspace/coverage/cover_reg_top/1.edn_csr_rw.1218239082 Jul 22 06:50:16 PM PDT 24 Jul 22 06:50:23 PM PDT 24 22300653 ps
T1084 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.399678682 Jul 22 06:50:17 PM PDT 24 Jul 22 06:50:25 PM PDT 24 73389719 ps
T1085 /workspace/coverage/cover_reg_top/14.edn_tl_errors.3530399836 Jul 22 06:50:30 PM PDT 24 Jul 22 06:50:47 PM PDT 24 26959694 ps
T286 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.4234664110 Jul 22 06:50:16 PM PDT 24 Jul 22 06:50:22 PM PDT 24 160010470 ps
T1086 /workspace/coverage/cover_reg_top/18.edn_csr_rw.1497318307 Jul 22 06:50:40 PM PDT 24 Jul 22 06:51:04 PM PDT 24 93631188 ps
T255 /workspace/coverage/cover_reg_top/8.edn_csr_rw.2052782834 Jul 22 06:50:22 PM PDT 24 Jul 22 06:50:34 PM PDT 24 20358875 ps
T1087 /workspace/coverage/cover_reg_top/44.edn_intr_test.374299695 Jul 22 06:50:49 PM PDT 24 Jul 22 06:51:26 PM PDT 24 58501685 ps
T256 /workspace/coverage/cover_reg_top/10.edn_csr_rw.280258948 Jul 22 06:50:27 PM PDT 24 Jul 22 06:50:42 PM PDT 24 32021049 ps
T257 /workspace/coverage/cover_reg_top/9.edn_csr_rw.1932836098 Jul 22 06:50:25 PM PDT 24 Jul 22 06:50:39 PM PDT 24 19538938 ps
T1088 /workspace/coverage/cover_reg_top/12.edn_intr_test.2705277174 Jul 22 06:50:29 PM PDT 24 Jul 22 06:50:44 PM PDT 24 82824147 ps
T1089 /workspace/coverage/cover_reg_top/2.edn_csr_rw.1283785483 Jul 22 06:50:16 PM PDT 24 Jul 22 06:50:22 PM PDT 24 54833564 ps
T1090 /workspace/coverage/cover_reg_top/49.edn_intr_test.3684909449 Jul 22 06:50:56 PM PDT 24 Jul 22 06:51:36 PM PDT 24 144930264 ps
T1091 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2629693568 Jul 22 06:50:17 PM PDT 24 Jul 22 06:50:28 PM PDT 24 172477029 ps
T1092 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2477922664 Jul 22 06:50:14 PM PDT 24 Jul 22 06:50:20 PM PDT 24 32449753 ps
T1093 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2439161243 Jul 22 06:50:44 PM PDT 24 Jul 22 06:51:14 PM PDT 24 34087852 ps
T1094 /workspace/coverage/cover_reg_top/47.edn_intr_test.159785164 Jul 22 06:51:09 PM PDT 24 Jul 22 06:51:56 PM PDT 24 36597097 ps
T1095 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1937433427 Jul 22 06:50:28 PM PDT 24 Jul 22 06:50:44 PM PDT 24 27513238 ps
T1096 /workspace/coverage/cover_reg_top/46.edn_intr_test.3379311652 Jul 22 06:50:53 PM PDT 24 Jul 22 06:51:34 PM PDT 24 20069732 ps
T1097 /workspace/coverage/cover_reg_top/22.edn_intr_test.2473947905 Jul 22 06:50:42 PM PDT 24 Jul 22 06:51:10 PM PDT 24 32014389 ps
T1098 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3271034763 Jul 22 06:50:39 PM PDT 24 Jul 22 06:51:02 PM PDT 24 46118447 ps
T1099 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2543492075 Jul 22 06:50:15 PM PDT 24 Jul 22 06:50:21 PM PDT 24 122630678 ps
T1100 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1165385430 Jul 22 06:50:30 PM PDT 24 Jul 22 06:50:47 PM PDT 24 17958843 ps
T1101 /workspace/coverage/cover_reg_top/12.edn_csr_rw.1810023653 Jul 22 06:51:22 PM PDT 24 Jul 22 06:52:13 PM PDT 24 14561163 ps
T1102 /workspace/coverage/cover_reg_top/9.edn_intr_test.1483865472 Jul 22 06:50:27 PM PDT 24 Jul 22 06:50:42 PM PDT 24 26977699 ps
T1103 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1158980206 Jul 22 06:50:31 PM PDT 24 Jul 22 06:50:48 PM PDT 24 129250762 ps
T1104 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1909894745 Jul 22 06:50:24 PM PDT 24 Jul 22 06:50:37 PM PDT 24 36296855 ps
T1105 /workspace/coverage/cover_reg_top/35.edn_intr_test.1418893554 Jul 22 06:50:40 PM PDT 24 Jul 22 06:51:04 PM PDT 24 15344855 ps
T258 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.660780542 Jul 22 06:50:15 PM PDT 24 Jul 22 06:50:20 PM PDT 24 16888170 ps
T1106 /workspace/coverage/cover_reg_top/24.edn_intr_test.2405152230 Jul 22 06:50:42 PM PDT 24 Jul 22 06:51:09 PM PDT 24 14363770 ps
T259 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2327577664 Jul 22 06:50:15 PM PDT 24 Jul 22 06:50:21 PM PDT 24 89646576 ps
T1107 /workspace/coverage/cover_reg_top/0.edn_intr_test.2171156636 Jul 22 06:50:13 PM PDT 24 Jul 22 06:50:16 PM PDT 24 73188444 ps
T1108 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.587445886 Jul 22 06:50:16 PM PDT 24 Jul 22 06:50:26 PM PDT 24 203198352 ps
T1109 /workspace/coverage/cover_reg_top/20.edn_intr_test.29760273 Jul 22 06:50:42 PM PDT 24 Jul 22 06:51:09 PM PDT 24 23244578 ps
T287 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2633336639 Jul 22 06:50:40 PM PDT 24 Jul 22 06:51:04 PM PDT 24 125520395 ps
T1110 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.534990505 Jul 22 06:50:29 PM PDT 24 Jul 22 06:50:45 PM PDT 24 77808758 ps
T1111 /workspace/coverage/cover_reg_top/3.edn_tl_errors.3431793363 Jul 22 06:50:27 PM PDT 24 Jul 22 06:50:46 PM PDT 24 150863506 ps
T1112 /workspace/coverage/cover_reg_top/48.edn_intr_test.274242514 Jul 22 06:50:49 PM PDT 24 Jul 22 06:51:25 PM PDT 24 35749250 ps
T1113 /workspace/coverage/cover_reg_top/18.edn_intr_test.2374510502 Jul 22 06:50:40 PM PDT 24 Jul 22 06:51:04 PM PDT 24 89415194 ps
T261 /workspace/coverage/cover_reg_top/13.edn_csr_rw.389168846 Jul 22 06:50:30 PM PDT 24 Jul 22 06:50:46 PM PDT 24 51366863 ps
T1114 /workspace/coverage/cover_reg_top/30.edn_intr_test.89323449 Jul 22 06:50:38 PM PDT 24 Jul 22 06:51:00 PM PDT 24 49620815 ps
T1115 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3322359733 Jul 22 06:50:40 PM PDT 24 Jul 22 06:51:05 PM PDT 24 210029554 ps
T260 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2861036685 Jul 22 06:50:16 PM PDT 24 Jul 22 06:50:23 PM PDT 24 161016156 ps
T1116 /workspace/coverage/cover_reg_top/4.edn_csr_rw.1673134570 Jul 22 06:50:24 PM PDT 24 Jul 22 06:50:37 PM PDT 24 47047892 ps
T1117 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3007009328 Jul 22 06:50:23 PM PDT 24 Jul 22 06:50:36 PM PDT 24 88868708 ps
T1118 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.817062118 Jul 22 06:50:23 PM PDT 24 Jul 22 06:50:36 PM PDT 24 100507259 ps
T1119 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.448657347 Jul 22 06:50:25 PM PDT 24 Jul 22 06:50:40 PM PDT 24 114616525 ps
T1120 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2738164613 Jul 22 06:51:00 PM PDT 24 Jul 22 06:51:47 PM PDT 24 84180574 ps
T1121 /workspace/coverage/cover_reg_top/7.edn_csr_rw.2096977172 Jul 22 06:50:25 PM PDT 24 Jul 22 06:50:40 PM PDT 24 27982919 ps
T262 /workspace/coverage/cover_reg_top/14.edn_csr_rw.184956354 Jul 22 06:50:39 PM PDT 24 Jul 22 06:51:02 PM PDT 24 15741926 ps
T1122 /workspace/coverage/cover_reg_top/19.edn_csr_rw.3693032864 Jul 22 06:50:42 PM PDT 24 Jul 22 06:51:11 PM PDT 24 15511033 ps
T1123 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.394532294 Jul 22 06:50:22 PM PDT 24 Jul 22 06:50:34 PM PDT 24 62668302 ps
T1124 /workspace/coverage/cover_reg_top/6.edn_intr_test.2945891966 Jul 22 06:50:34 PM PDT 24 Jul 22 06:50:53 PM PDT 24 20308318 ps
T1125 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1176289785 Jul 22 06:50:24 PM PDT 24 Jul 22 06:50:37 PM PDT 24 28705610 ps
T1126 /workspace/coverage/cover_reg_top/3.edn_intr_test.456435399 Jul 22 06:50:54 PM PDT 24 Jul 22 06:51:35 PM PDT 24 32750508 ps
T1127 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1172123368 Jul 22 06:51:21 PM PDT 24 Jul 22 06:52:12 PM PDT 24 24882452 ps
T1128 /workspace/coverage/cover_reg_top/45.edn_intr_test.2398655607 Jul 22 06:50:50 PM PDT 24 Jul 22 06:51:27 PM PDT 24 81347125 ps
T1129 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.766980286 Jul 22 06:50:39 PM PDT 24 Jul 22 06:51:04 PM PDT 24 88065172 ps
T1130 /workspace/coverage/cover_reg_top/23.edn_intr_test.4162445959 Jul 22 06:50:41 PM PDT 24 Jul 22 06:51:08 PM PDT 24 48390864 ps

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.2310945104
Short name T5
Test name
Test status
Simulation time 51894694773 ps
CPU time 610.32 seconds
Started Jul 22 05:42:10 PM PDT 24
Finished Jul 22 05:52:22 PM PDT 24
Peak memory 219100 kb
Host smart-4275d248-edc8-4d14-9825-fc0a1ab7216a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310945104 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.2310945104
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/207.edn_genbits.353131019
Short name T40
Test name
Test status
Simulation time 62793631 ps
CPU time 2.37 seconds
Started Jul 22 05:44:42 PM PDT 24
Finished Jul 22 05:44:45 PM PDT 24
Peak memory 218684 kb
Host smart-a6dee885-2e84-41b1-840b-26c155c1c947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353131019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.353131019
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.2051532981
Short name T27
Test name
Test status
Simulation time 24539654 ps
CPU time 1.23 seconds
Started Jul 22 05:44:04 PM PDT 24
Finished Jul 22 05:44:06 PM PDT 24
Peak memory 218996 kb
Host smart-0dbc5374-5788-4b4e-82f7-fe7c1a8f303a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051532981 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.2051532981
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/3.edn_sec_cm.679336614
Short name T4
Test name
Test status
Simulation time 1000304938 ps
CPU time 4.75 seconds
Started Jul 22 05:41:54 PM PDT 24
Finished Jul 22 05:42:00 PM PDT 24
Peak memory 236532 kb
Host smart-97091572-4ce1-412c-b594-16e45ad5154b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679336614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.679336614
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.825618330
Short name T9
Test name
Test status
Simulation time 49461372 ps
CPU time 1.21 seconds
Started Jul 22 05:41:59 PM PDT 24
Finished Jul 22 05:42:01 PM PDT 24
Peak memory 217896 kb
Host smart-e263516c-5352-45e2-8cdd-a622006f997f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825618330 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_dis
able_auto_req_mode.825618330
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_disable.71166179
Short name T177
Test name
Test status
Simulation time 12699240 ps
CPU time 0.89 seconds
Started Jul 22 05:42:12 PM PDT 24
Finished Jul 22 05:42:14 PM PDT 24
Peak memory 216544 kb
Host smart-e33cbdd3-740c-44dc-81a4-8e2e8a681072
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71166179 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.71166179
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/85.edn_err.3547483865
Short name T52
Test name
Test status
Simulation time 31078800 ps
CPU time 1.33 seconds
Started Jul 22 05:43:44 PM PDT 24
Finished Jul 22 05:43:47 PM PDT 24
Peak memory 225888 kb
Host smart-4fbb9df6-a466-4eb2-b114-fe2602853652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547483865 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.3547483865
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/189.edn_alert.1230616365
Short name T43
Test name
Test status
Simulation time 46414892 ps
CPU time 1.19 seconds
Started Jul 22 05:44:42 PM PDT 24
Finished Jul 22 05:44:44 PM PDT 24
Peak memory 216012 kb
Host smart-507f5130-5fe4-4020-98df-dde382f82489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230616365 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.1230616365
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/264.edn_genbits.1439947435
Short name T12
Test name
Test status
Simulation time 81862309 ps
CPU time 1.26 seconds
Started Jul 22 05:44:56 PM PDT 24
Finished Jul 22 05:44:57 PM PDT 24
Peak memory 220404 kb
Host smart-b1727574-fd25-4f40-9742-4e1eafa0009e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439947435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.1439947435
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.2596422924
Short name T92
Test name
Test status
Simulation time 425313047369 ps
CPU time 2337.17 seconds
Started Jul 22 05:42:54 PM PDT 24
Finished Jul 22 06:21:53 PM PDT 24
Peak memory 228640 kb
Host smart-0d18e759-cb92-48d1-aab0-50da0d045fe4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596422924 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.2596422924
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/163.edn_alert.3640051055
Short name T22
Test name
Test status
Simulation time 33152430 ps
CPU time 1.05 seconds
Started Jul 22 05:44:24 PM PDT 24
Finished Jul 22 05:44:26 PM PDT 24
Peak memory 219968 kb
Host smart-e5affad3-0f7f-42e2-943e-303ca328bd92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640051055 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.3640051055
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/8.edn_regwen.4188935078
Short name T462
Test name
Test status
Simulation time 18247709 ps
CPU time 0.99 seconds
Started Jul 22 05:42:03 PM PDT 24
Finished Jul 22 05:42:05 PM PDT 24
Peak memory 207368 kb
Host smart-2b68f6eb-a39c-4045-8f04-5e5ac6ee0b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188935078 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.4188935078
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/193.edn_alert.691146506
Short name T193
Test name
Test status
Simulation time 25136905 ps
CPU time 1.17 seconds
Started Jul 22 05:44:42 PM PDT 24
Finished Jul 22 05:44:44 PM PDT 24
Peak memory 220404 kb
Host smart-031edcf4-c09f-4aaf-b33b-39c65df900ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691146506 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.691146506
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2072035210
Short name T278
Test name
Test status
Simulation time 239937236 ps
CPU time 2.1 seconds
Started Jul 22 06:50:28 PM PDT 24
Finished Jul 22 06:50:45 PM PDT 24
Peak memory 206636 kb
Host smart-ab5f3b99-9899-42f2-9604-a148c0dc2f3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072035210 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.2072035210
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.1564692994
Short name T141
Test name
Test status
Simulation time 30255506 ps
CPU time 1.15 seconds
Started Jul 22 05:41:54 PM PDT 24
Finished Jul 22 05:41:56 PM PDT 24
Peak memory 217124 kb
Host smart-454922f5-4625-4eaf-b043-d66ff101491d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564692994 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.1564692994
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/112.edn_alert.2368382986
Short name T137
Test name
Test status
Simulation time 124344810 ps
CPU time 1.11 seconds
Started Jul 22 05:43:57 PM PDT 24
Finished Jul 22 05:44:00 PM PDT 24
Peak memory 218828 kb
Host smart-9197ffc2-975c-4507-8d2f-d327cc459c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368382986 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.2368382986
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/44.edn_err.4076032665
Short name T91
Test name
Test status
Simulation time 24055660 ps
CPU time 0.92 seconds
Started Jul 22 05:43:15 PM PDT 24
Finished Jul 22 05:43:17 PM PDT 24
Peak memory 218928 kb
Host smart-2b1ce7f0-0bb2-4af4-a139-92c24054bd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076032665 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.4076032665
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/24.edn_alert.1311687124
Short name T220
Test name
Test status
Simulation time 31557364 ps
CPU time 1.43 seconds
Started Jul 22 05:42:36 PM PDT 24
Finished Jul 22 05:42:38 PM PDT 24
Peak memory 216116 kb
Host smart-d0739ba1-621d-420f-ad08-1c5c0451f2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311687124 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.1311687124
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/10.edn_disable.3789113325
Short name T200
Test name
Test status
Simulation time 112864584 ps
CPU time 0.88 seconds
Started Jul 22 05:42:00 PM PDT 24
Finished Jul 22 05:42:02 PM PDT 24
Peak memory 216564 kb
Host smart-bf5c3b6d-eb88-47b3-89b2-2a52027fbd6e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789113325 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.3789113325
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable.1417910890
Short name T168
Test name
Test status
Simulation time 99717146 ps
CPU time 0.89 seconds
Started Jul 22 05:42:35 PM PDT 24
Finished Jul 22 05:42:36 PM PDT 24
Peak memory 216564 kb
Host smart-a893e361-d39f-4276-bac9-124e2a7dec32
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417910890 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.1417910890
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.3503746072
Short name T252
Test name
Test status
Simulation time 37883702 ps
CPU time 0.89 seconds
Started Jul 22 06:50:39 PM PDT 24
Finished Jul 22 06:51:01 PM PDT 24
Peak memory 206484 kb
Host smart-b3e9e35a-03a1-4cf3-a88b-e3d0f6dff0b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503746072 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.3503746072
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/default/150.edn_alert.2844442865
Short name T214
Test name
Test status
Simulation time 28343505 ps
CPU time 1.28 seconds
Started Jul 22 05:44:13 PM PDT 24
Finished Jul 22 05:44:15 PM PDT 24
Peak memory 220244 kb
Host smart-232d5573-22b5-4154-9632-374dbb454e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844442865 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.2844442865
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/190.edn_alert.2643828365
Short name T113
Test name
Test status
Simulation time 79594326 ps
CPU time 1.21 seconds
Started Jul 22 05:44:43 PM PDT 24
Finished Jul 22 05:44:45 PM PDT 24
Peak memory 218916 kb
Host smart-c1385e7f-ffb1-4d72-8d33-1b5489a4601a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643828365 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.2643828365
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.2989632699
Short name T542
Test name
Test status
Simulation time 20450960 ps
CPU time 1.05 seconds
Started Jul 22 05:42:51 PM PDT 24
Finished Jul 22 05:42:54 PM PDT 24
Peak memory 217336 kb
Host smart-635930f4-4993-4db1-ab2a-3a728395b841
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989632699 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.2989632699
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_disable.2844616535
Short name T155
Test name
Test status
Simulation time 10918763 ps
CPU time 0.85 seconds
Started Jul 22 05:42:28 PM PDT 24
Finished Jul 22 05:42:30 PM PDT 24
Peak memory 215780 kb
Host smart-f2551c62-90c4-41bf-ac49-22e7d9a645ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844616535 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.2844616535
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/26.edn_genbits.1432910989
Short name T315
Test name
Test status
Simulation time 59013185 ps
CPU time 2.34 seconds
Started Jul 22 05:42:51 PM PDT 24
Finished Jul 22 05:42:55 PM PDT 24
Peak memory 218872 kb
Host smart-588dafe1-bb84-47e2-938e-da586c4ace2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432910989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.1432910989
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/60.edn_alert.195951129
Short name T68
Test name
Test status
Simulation time 55802587 ps
CPU time 1.3 seconds
Started Jul 22 05:43:31 PM PDT 24
Finished Jul 22 05:43:32 PM PDT 24
Peak memory 218804 kb
Host smart-6e4132d4-433a-460d-872c-893dcdb294f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195951129 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.195951129
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/142.edn_alert.2355518353
Short name T179
Test name
Test status
Simulation time 75076269 ps
CPU time 1.17 seconds
Started Jul 22 05:45:01 PM PDT 24
Finished Jul 22 05:45:03 PM PDT 24
Peak memory 218728 kb
Host smart-80a75385-a97c-4d1e-8359-c4b06d54de35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355518353 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.2355518353
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/160.edn_alert.1112731789
Short name T125
Test name
Test status
Simulation time 36634349 ps
CPU time 1.28 seconds
Started Jul 22 05:44:27 PM PDT 24
Finished Jul 22 05:44:29 PM PDT 24
Peak memory 219980 kb
Host smart-4e0a32b8-505a-4551-80ae-9e423973dc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112731789 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.1112731789
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert.3286174124
Short name T143
Test name
Test status
Simulation time 249647458 ps
CPU time 1.44 seconds
Started Jul 22 05:41:53 PM PDT 24
Finished Jul 22 05:41:55 PM PDT 24
Peak memory 219012 kb
Host smart-a7faffc4-0997-4f2c-96ac-3c738c08cf5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286174124 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.3286174124
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/42.edn_intr.1083725785
Short name T30
Test name
Test status
Simulation time 35370411 ps
CPU time 0.93 seconds
Started Jul 22 05:43:02 PM PDT 24
Finished Jul 22 05:43:05 PM PDT 24
Peak memory 215952 kb
Host smart-aa57cc4b-4af7-4da8-a699-b90ee8caa932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083725785 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.1083725785
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.2614277995
Short name T10
Test name
Test status
Simulation time 65214337 ps
CPU time 1.04 seconds
Started Jul 22 05:42:01 PM PDT 24
Finished Jul 22 05:42:03 PM PDT 24
Peak memory 220044 kb
Host smart-8181fe2d-4744-43a6-b4fa-946844c60730
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614277995 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.2614277995
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/282.edn_genbits.429435119
Short name T453
Test name
Test status
Simulation time 148508222 ps
CPU time 1.42 seconds
Started Jul 22 05:44:53 PM PDT 24
Finished Jul 22 05:44:56 PM PDT 24
Peak memory 219120 kb
Host smart-47a82817-568e-46e6-b3ee-3087b3206698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429435119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.429435119
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.4209171969
Short name T314
Test name
Test status
Simulation time 276051671 ps
CPU time 4.22 seconds
Started Jul 22 05:44:16 PM PDT 24
Finished Jul 22 05:44:21 PM PDT 24
Peak memory 220352 kb
Host smart-552b8e0f-2a9b-4096-b876-93c3c65d5da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209171969 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.4209171969
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.4190735767
Short name T183
Test name
Test status
Simulation time 345646071 ps
CPU time 1.37 seconds
Started Jul 22 05:41:52 PM PDT 24
Finished Jul 22 05:41:55 PM PDT 24
Peak memory 220220 kb
Host smart-a2fd87ee-8f7f-4a4e-acd1-7573f12a1070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190735767 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.4190735767
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/14.edn_intr.2471093528
Short name T33
Test name
Test status
Simulation time 21442783 ps
CPU time 1.09 seconds
Started Jul 22 05:42:12 PM PDT 24
Finished Jul 22 05:42:15 PM PDT 24
Peak memory 216296 kb
Host smart-b2beb700-b73c-47ee-b0f0-6549d85a8995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471093528 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.2471093528
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/102.edn_alert.2009785478
Short name T856
Test name
Test status
Simulation time 41069112 ps
CPU time 1.06 seconds
Started Jul 22 05:43:57 PM PDT 24
Finished Jul 22 05:44:00 PM PDT 24
Peak memory 220184 kb
Host smart-3a5350eb-bf23-4836-bfd3-d35d4fa1ea0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009785478 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.2009785478
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/103.edn_alert.1829158767
Short name T171
Test name
Test status
Simulation time 66927909 ps
CPU time 1.17 seconds
Started Jul 22 05:43:51 PM PDT 24
Finished Jul 22 05:43:53 PM PDT 24
Peak memory 219004 kb
Host smart-7f8f949f-59d0-4ef3-813f-30d2aebece2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829158767 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.1829158767
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/12.edn_disable.2309242160
Short name T202
Test name
Test status
Simulation time 12773708 ps
CPU time 0.93 seconds
Started Jul 22 05:42:13 PM PDT 24
Finished Jul 22 05:42:16 PM PDT 24
Peak memory 216884 kb
Host smart-47025947-d6cf-4f51-84f4-101fc90ba541
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309242160 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2309242160
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/14.edn_err.4129504174
Short name T213
Test name
Test status
Simulation time 38470475 ps
CPU time 0.93 seconds
Started Jul 22 05:42:11 PM PDT 24
Finished Jul 22 05:42:13 PM PDT 24
Peak memory 219584 kb
Host smart-118ff3f7-087b-4563-940a-72ab5bcb09d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129504174 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.4129504174
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/145.edn_alert.4280621149
Short name T218
Test name
Test status
Simulation time 26892652 ps
CPU time 1.21 seconds
Started Jul 22 05:44:15 PM PDT 24
Finished Jul 22 05:44:17 PM PDT 24
Peak memory 218996 kb
Host smart-1ce7152d-a18f-49a5-949a-93c3a5431746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280621149 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.4280621149
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.3612513670
Short name T110
Test name
Test status
Simulation time 76487073 ps
CPU time 1 seconds
Started Jul 22 05:42:28 PM PDT 24
Finished Jul 22 05:42:29 PM PDT 24
Peak memory 217124 kb
Host smart-89513c49-d4c1-4539-be7f-89e4a53b0a39
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612513670 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.3612513670
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.166824295
Short name T192
Test name
Test status
Simulation time 19340744 ps
CPU time 1.03 seconds
Started Jul 22 05:42:19 PM PDT 24
Finished Jul 22 05:42:20 PM PDT 24
Peak memory 218660 kb
Host smart-693ccba8-c192-42e6-9385-9848b10a5399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166824295 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.166824295
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.1529061692
Short name T148
Test name
Test status
Simulation time 126220943 ps
CPU time 1.08 seconds
Started Jul 22 05:42:33 PM PDT 24
Finished Jul 22 05:42:35 PM PDT 24
Peak memory 217256 kb
Host smart-7a7d1303-6ffe-4f2f-a916-2db8492e16da
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529061692 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.1529061692
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.912757341
Short name T130
Test name
Test status
Simulation time 35383982 ps
CPU time 1 seconds
Started Jul 22 05:43:48 PM PDT 24
Finished Jul 22 05:43:50 PM PDT 24
Peak memory 218800 kb
Host smart-a4c8570d-6df9-4ebc-b42d-5e70b049a3d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912757341 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_di
sable_auto_req_mode.912757341
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_disable.3394041847
Short name T161
Test name
Test status
Simulation time 31465984 ps
CPU time 0.85 seconds
Started Jul 22 05:42:49 PM PDT 24
Finished Jul 22 05:42:51 PM PDT 24
Peak memory 216580 kb
Host smart-36179477-c476-421f-b295-dacb2e6b8b26
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394041847 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.3394041847
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable.913013190
Short name T210
Test name
Test status
Simulation time 10907899 ps
CPU time 0.86 seconds
Started Jul 22 05:41:53 PM PDT 24
Finished Jul 22 05:41:54 PM PDT 24
Peak memory 216684 kb
Host smart-3ec5ce30-5602-4db9-9a58-6e3a73a1769c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913013190 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.913013190
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/10.edn_genbits.2865484170
Short name T308
Test name
Test status
Simulation time 83985253 ps
CPU time 2.68 seconds
Started Jul 22 05:42:13 PM PDT 24
Finished Jul 22 05:42:18 PM PDT 24
Peak memory 220472 kb
Host smart-25bbafa2-1e93-4e2d-9ed7-dc2e80318f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865484170 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.2865484170
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.2363819470
Short name T337
Test name
Test status
Simulation time 38550331 ps
CPU time 1.34 seconds
Started Jul 22 05:44:06 PM PDT 24
Finished Jul 22 05:44:08 PM PDT 24
Peak memory 218940 kb
Host smart-d577f388-6c99-4b4a-923b-e7371960a20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363819470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2363819470
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_alert_test.3638273456
Short name T95
Test name
Test status
Simulation time 40911745 ps
CPU time 0.88 seconds
Started Jul 22 05:41:41 PM PDT 24
Finished Jul 22 05:41:42 PM PDT 24
Peak memory 215436 kb
Host smart-9b2da31d-4ca7-4cae-a287-f37c6593a900
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638273456 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.3638273456
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.3488668656
Short name T492
Test name
Test status
Simulation time 145190087266 ps
CPU time 1675.02 seconds
Started Jul 22 05:42:06 PM PDT 24
Finished Jul 22 06:10:02 PM PDT 24
Peak memory 225712 kb
Host smart-e629ca8b-827c-4ee9-a5e0-80f2a79b7d69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488668656 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.3488668656
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.1874552641
Short name T340
Test name
Test status
Simulation time 54038415 ps
CPU time 1.05 seconds
Started Jul 22 05:44:42 PM PDT 24
Finished Jul 22 05:44:44 PM PDT 24
Peak memory 219200 kb
Host smart-a60a72cd-acc5-4d5d-bca1-35f1aab5f4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874552641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.1874552641
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_stress_all.612745396
Short name T61
Test name
Test status
Simulation time 214855805 ps
CPU time 4.48 seconds
Started Jul 22 05:43:31 PM PDT 24
Finished Jul 22 05:43:37 PM PDT 24
Peak memory 217472 kb
Host smart-b9f6a959-be3e-4dbd-bedb-984e4d819f31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612745396 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.612745396
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_intr.2695988294
Short name T31
Test name
Test status
Simulation time 53621614 ps
CPU time 0.82 seconds
Started Jul 22 05:43:25 PM PDT 24
Finished Jul 22 05:43:27 PM PDT 24
Peak memory 215872 kb
Host smart-beb8e4bf-715d-40c1-ab7c-88c460f8509b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695988294 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.2695988294
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.4090243862
Short name T247
Test name
Test status
Simulation time 91223332 ps
CPU time 0.94 seconds
Started Jul 22 06:50:28 PM PDT 24
Finished Jul 22 06:50:44 PM PDT 24
Peak memory 206788 kb
Host smart-ae4cfb64-dfe4-4d7e-822e-844afabebfbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090243862 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.4090243862
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.941047891
Short name T284
Test name
Test status
Simulation time 318529259 ps
CPU time 2.48 seconds
Started Jul 22 06:50:33 PM PDT 24
Finished Jul 22 06:50:52 PM PDT 24
Peak memory 206720 kb
Host smart-07350abb-e028-40d4-8dda-26144074cde1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941047891 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.941047891
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/default/1.edn_regwen.1851098829
Short name T25
Test name
Test status
Simulation time 43601652 ps
CPU time 0.88 seconds
Started Jul 22 05:41:42 PM PDT 24
Finished Jul 22 05:41:44 PM PDT 24
Peak memory 207400 kb
Host smart-c741f39d-c293-42ba-ba81-90373fb565e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851098829 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.1851098829
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_stress_all.375004105
Short name T571
Test name
Test status
Simulation time 1083989681 ps
CPU time 2.77 seconds
Started Jul 22 05:41:44 PM PDT 24
Finished Jul 22 05:41:47 PM PDT 24
Peak memory 217496 kb
Host smart-58d17bbd-e7d1-4669-b899-677382b2d09d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375004105 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.375004105
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/102.edn_genbits.1087954425
Short name T326
Test name
Test status
Simulation time 49360047 ps
CPU time 1.28 seconds
Started Jul 22 05:43:52 PM PDT 24
Finished Jul 22 05:43:54 PM PDT 24
Peak memory 219020 kb
Host smart-f5a82940-d39c-4c19-97d3-44f639fef8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087954425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.1087954425
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_genbits.1831545077
Short name T842
Test name
Test status
Simulation time 37451224 ps
CPU time 1.33 seconds
Started Jul 22 05:42:07 PM PDT 24
Finished Jul 22 05:42:09 PM PDT 24
Peak memory 217640 kb
Host smart-116ca209-8a95-47bb-81e8-41ae1f37134f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831545077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1831545077
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/170.edn_genbits.1234572898
Short name T37
Test name
Test status
Simulation time 45409120 ps
CPU time 1.65 seconds
Started Jul 22 05:44:23 PM PDT 24
Finished Jul 22 05:44:25 PM PDT 24
Peak memory 218816 kb
Host smart-5592518b-b0f2-470b-9707-a43d3ebfae2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234572898 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1234572898
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.2401143343
Short name T328
Test name
Test status
Simulation time 95084709 ps
CPU time 2.49 seconds
Started Jul 22 05:44:41 PM PDT 24
Finished Jul 22 05:44:45 PM PDT 24
Peak memory 220540 kb
Host smart-65487525-39ca-4d44-9732-2978ab18ef66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401143343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.2401143343
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.703586555
Short name T329
Test name
Test status
Simulation time 53576462 ps
CPU time 1.06 seconds
Started Jul 22 05:44:49 PM PDT 24
Finished Jul 22 05:44:50 PM PDT 24
Peak memory 219412 kb
Host smart-8828bbe5-5e98-43ca-80b0-2575e0940c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703586555 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.703586555
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.3286860513
Short name T320
Test name
Test status
Simulation time 80387791 ps
CPU time 1.56 seconds
Started Jul 22 05:44:38 PM PDT 24
Finished Jul 22 05:44:40 PM PDT 24
Peak memory 218872 kb
Host smart-4167fee2-35c4-478c-9806-e18948963ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286860513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3286860513
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.1991963683
Short name T333
Test name
Test status
Simulation time 54612768 ps
CPU time 1.66 seconds
Started Jul 22 05:44:48 PM PDT 24
Finished Jul 22 05:44:50 PM PDT 24
Peak memory 218896 kb
Host smart-d54043c6-bc45-4259-9968-ecd1aa5f74bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991963683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.1991963683
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.1282126861
Short name T87
Test name
Test status
Simulation time 25798670 ps
CPU time 1.03 seconds
Started Jul 22 05:42:52 PM PDT 24
Finished Jul 22 05:42:55 PM PDT 24
Peak memory 216244 kb
Host smart-4539d2bf-2773-4d93-bb15-b1437aad13e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282126861 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.1282126861
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/68.edn_err.3306837657
Short name T98
Test name
Test status
Simulation time 50042343 ps
CPU time 1 seconds
Started Jul 22 05:43:43 PM PDT 24
Finished Jul 22 05:43:45 PM PDT 24
Peak memory 219996 kb
Host smart-4bdf8c75-e1d5-4808-8aaf-37cf7f3b0201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306837657 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.3306837657
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/189.edn_genbits.65517668
Short name T21
Test name
Test status
Simulation time 62770064 ps
CPU time 1.48 seconds
Started Jul 22 05:44:46 PM PDT 24
Finished Jul 22 05:44:48 PM PDT 24
Peak memory 220280 kb
Host smart-ae95b07e-1bc1-4aac-b41e-387cf8ca015e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65517668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.65517668
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.770878559
Short name T330
Test name
Test status
Simulation time 41225156 ps
CPU time 1.57 seconds
Started Jul 22 05:44:04 PM PDT 24
Finished Jul 22 05:44:07 PM PDT 24
Peak memory 220680 kb
Host smart-549bef97-be06-4ca0-bbeb-22811ce0409c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770878559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.770878559
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2876761126
Short name T249
Test name
Test status
Simulation time 16828475 ps
CPU time 1.09 seconds
Started Jul 22 06:50:13 PM PDT 24
Finished Jul 22 06:50:17 PM PDT 24
Peak memory 206424 kb
Host smart-83100cef-e16b-4637-b8be-23de33851801
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876761126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.2876761126
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.587445886
Short name T1108
Test name
Test status
Simulation time 203198352 ps
CPU time 5.05 seconds
Started Jul 22 06:50:16 PM PDT 24
Finished Jul 22 06:50:26 PM PDT 24
Peak memory 206412 kb
Host smart-0f19f727-1a45-4498-b6fe-0de50d7b0085
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587445886 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.587445886
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.660780542
Short name T258
Test name
Test status
Simulation time 16888170 ps
CPU time 0.96 seconds
Started Jul 22 06:50:15 PM PDT 24
Finished Jul 22 06:50:20 PM PDT 24
Peak memory 206488 kb
Host smart-fff2d397-d8e9-4803-8a2c-de1f2715f66a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660780542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.660780542
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1495066254
Short name T1015
Test name
Test status
Simulation time 65927866 ps
CPU time 1.29 seconds
Started Jul 22 06:50:15 PM PDT 24
Finished Jul 22 06:50:21 PM PDT 24
Peak memory 214796 kb
Host smart-8e2bde54-30c5-418c-b091-5f64532dcd02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495066254 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.1495066254
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.992014534
Short name T1031
Test name
Test status
Simulation time 21736417 ps
CPU time 0.85 seconds
Started Jul 22 06:50:15 PM PDT 24
Finished Jul 22 06:50:20 PM PDT 24
Peak memory 206460 kb
Host smart-96c4f6f0-d977-4a6a-a797-61c19929dd9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992014534 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.992014534
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.2171156636
Short name T1107
Test name
Test status
Simulation time 73188444 ps
CPU time 0.86 seconds
Started Jul 22 06:50:13 PM PDT 24
Finished Jul 22 06:50:16 PM PDT 24
Peak memory 206496 kb
Host smart-4ebe0682-def6-4f6d-b1b3-0a665024c8c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171156636 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.2171156636
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2477922664
Short name T1092
Test name
Test status
Simulation time 32449753 ps
CPU time 1.18 seconds
Started Jul 22 06:50:14 PM PDT 24
Finished Jul 22 06:50:20 PM PDT 24
Peak memory 206628 kb
Host smart-3cc1002c-2e7b-4616-9676-98932e1b8269
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477922664 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.2477922664
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3559828308
Short name T1047
Test name
Test status
Simulation time 105581299 ps
CPU time 2.31 seconds
Started Jul 22 06:50:14 PM PDT 24
Finished Jul 22 06:50:20 PM PDT 24
Peak memory 214812 kb
Host smart-08bbe1ec-61ab-442c-9dda-1ac17c225bf8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559828308 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3559828308
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2861036685
Short name T260
Test name
Test status
Simulation time 161016156 ps
CPU time 1.44 seconds
Started Jul 22 06:50:16 PM PDT 24
Finished Jul 22 06:50:23 PM PDT 24
Peak memory 206424 kb
Host smart-ac9a0302-821c-464a-9ef3-abf8f81e9795
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861036685 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.2861036685
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2629693568
Short name T1091
Test name
Test status
Simulation time 172477029 ps
CPU time 5.34 seconds
Started Jul 22 06:50:17 PM PDT 24
Finished Jul 22 06:50:28 PM PDT 24
Peak memory 206408 kb
Host smart-a75cab50-27e6-4247-afae-4e161810cd0a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629693568 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2629693568
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3448925023
Short name T1059
Test name
Test status
Simulation time 48144161 ps
CPU time 0.95 seconds
Started Jul 22 06:50:15 PM PDT 24
Finished Jul 22 06:50:21 PM PDT 24
Peak memory 206492 kb
Host smart-a49e6fce-4d4c-41d7-aad9-c48b2c5856ce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448925023 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.3448925023
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.399678682
Short name T1084
Test name
Test status
Simulation time 73389719 ps
CPU time 1.46 seconds
Started Jul 22 06:50:17 PM PDT 24
Finished Jul 22 06:50:25 PM PDT 24
Peak memory 214828 kb
Host smart-fd28212e-4d3d-4c02-95ce-72eccd8875e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399678682 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.399678682
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.1218239082
Short name T1083
Test name
Test status
Simulation time 22300653 ps
CPU time 0.95 seconds
Started Jul 22 06:50:16 PM PDT 24
Finished Jul 22 06:50:23 PM PDT 24
Peak memory 206392 kb
Host smart-1e08312d-f538-42a8-a6ad-0d0a107d7407
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218239082 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.1218239082
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3826543290
Short name T1023
Test name
Test status
Simulation time 31213928 ps
CPU time 0.79 seconds
Started Jul 22 06:50:14 PM PDT 24
Finished Jul 22 06:50:20 PM PDT 24
Peak memory 206280 kb
Host smart-b8fd8bba-8ca9-44c2-aec5-6e51da50ce77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826543290 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3826543290
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2407448972
Short name T1069
Test name
Test status
Simulation time 64792264 ps
CPU time 1.03 seconds
Started Jul 22 06:50:16 PM PDT 24
Finished Jul 22 06:50:24 PM PDT 24
Peak memory 206472 kb
Host smart-e2b5c4a9-271d-4a21-b9ba-9a38f1733d47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407448972 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.2407448972
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.860345650
Short name T1037
Test name
Test status
Simulation time 138297450 ps
CPU time 2.52 seconds
Started Jul 22 06:50:12 PM PDT 24
Finished Jul 22 06:50:16 PM PDT 24
Peak memory 214796 kb
Host smart-0297ebc0-91a2-4462-b12c-3007b15902c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860345650 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.860345650
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2543492075
Short name T1099
Test name
Test status
Simulation time 122630678 ps
CPU time 1.79 seconds
Started Jul 22 06:50:15 PM PDT 24
Finished Jul 22 06:50:21 PM PDT 24
Peak memory 206524 kb
Host smart-c31bfefe-ef49-49f2-993a-5e24b1d1f7fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543492075 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.2543492075
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2931068925
Short name T1078
Test name
Test status
Simulation time 110957472 ps
CPU time 1.42 seconds
Started Jul 22 06:50:31 PM PDT 24
Finished Jul 22 06:50:49 PM PDT 24
Peak memory 218572 kb
Host smart-169e4b9e-0767-40ef-9e4d-e805dbdd89b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931068925 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.2931068925
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.280258948
Short name T256
Test name
Test status
Simulation time 32021049 ps
CPU time 0.84 seconds
Started Jul 22 06:50:27 PM PDT 24
Finished Jul 22 06:50:42 PM PDT 24
Peak memory 206420 kb
Host smart-6c844810-9e01-4f30-9cb0-1289106ccc5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280258948 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.280258948
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2808051440
Short name T1054
Test name
Test status
Simulation time 11711319 ps
CPU time 0.83 seconds
Started Jul 22 06:50:26 PM PDT 24
Finished Jul 22 06:50:41 PM PDT 24
Peak memory 206716 kb
Host smart-097df789-7ee2-46cc-b6e2-60f82cd5e97d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808051440 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2808051440
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.1437519024
Short name T1060
Test name
Test status
Simulation time 176549020 ps
CPU time 3.31 seconds
Started Jul 22 06:50:25 PM PDT 24
Finished Jul 22 06:50:42 PM PDT 24
Peak memory 214816 kb
Host smart-e3309ffe-727c-40cd-b39b-39eac6a381ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437519024 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1437519024
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2218017022
Short name T1082
Test name
Test status
Simulation time 96939072 ps
CPU time 1.73 seconds
Started Jul 22 06:50:31 PM PDT 24
Finished Jul 22 06:50:48 PM PDT 24
Peak memory 214768 kb
Host smart-b761d689-c0a1-4c1b-9168-77d8f37db3ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218017022 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.2218017022
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3740512034
Short name T1001
Test name
Test status
Simulation time 33860481 ps
CPU time 1.41 seconds
Started Jul 22 06:51:22 PM PDT 24
Finished Jul 22 06:52:13 PM PDT 24
Peak memory 217540 kb
Host smart-e171eee1-e2fd-438e-b5c6-28136e2db44d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740512034 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3740512034
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.706523159
Short name T1032
Test name
Test status
Simulation time 30795436 ps
CPU time 0.81 seconds
Started Jul 22 06:51:22 PM PDT 24
Finished Jul 22 06:52:13 PM PDT 24
Peak memory 206268 kb
Host smart-a8978774-3735-4f23-b4a0-aae0c9c21a30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706523159 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.706523159
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.841646563
Short name T1057
Test name
Test status
Simulation time 38968936 ps
CPU time 0.81 seconds
Started Jul 22 06:51:19 PM PDT 24
Finished Jul 22 06:52:10 PM PDT 24
Peak memory 206460 kb
Host smart-8b063c8a-5e6d-4b97-81d4-f4527b6b18e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841646563 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.841646563
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.512179261
Short name T263
Test name
Test status
Simulation time 194320485 ps
CPU time 1.42 seconds
Started Jul 22 06:50:28 PM PDT 24
Finished Jul 22 06:50:44 PM PDT 24
Peak memory 206524 kb
Host smart-45dd463f-ff2c-4cbe-9588-6aef884ff7a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512179261 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_ou
tstanding.512179261
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.1299457979
Short name T1074
Test name
Test status
Simulation time 175192097 ps
CPU time 3.21 seconds
Started Jul 22 06:50:26 PM PDT 24
Finished Jul 22 06:50:43 PM PDT 24
Peak memory 214796 kb
Host smart-13ddde1d-c0e2-442e-8432-fc9c21464658
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299457979 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.1299457979
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3811625882
Short name T1081
Test name
Test status
Simulation time 179446290 ps
CPU time 2.28 seconds
Started Jul 22 06:50:30 PM PDT 24
Finished Jul 22 06:50:48 PM PDT 24
Peak memory 214592 kb
Host smart-d21bb925-722e-453c-a050-e0eef9848c9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811625882 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.3811625882
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.411616165
Short name T1065
Test name
Test status
Simulation time 34825880 ps
CPU time 1.45 seconds
Started Jul 22 06:50:25 PM PDT 24
Finished Jul 22 06:50:40 PM PDT 24
Peak memory 214828 kb
Host smart-50777650-4c0a-4063-9685-6be6347e39f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411616165 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.411616165
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.1810023653
Short name T1101
Test name
Test status
Simulation time 14561163 ps
CPU time 0.91 seconds
Started Jul 22 06:51:22 PM PDT 24
Finished Jul 22 06:52:13 PM PDT 24
Peak memory 206252 kb
Host smart-5232c6b2-18f0-44d5-aa13-91c38e6db751
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810023653 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.1810023653
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.2705277174
Short name T1088
Test name
Test status
Simulation time 82824147 ps
CPU time 0.85 seconds
Started Jul 22 06:50:29 PM PDT 24
Finished Jul 22 06:50:44 PM PDT 24
Peak memory 206456 kb
Host smart-4362963b-5184-4c80-812e-372c0e93223a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705277174 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2705277174
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3910476187
Short name T248
Test name
Test status
Simulation time 42662069 ps
CPU time 1.14 seconds
Started Jul 22 06:50:29 PM PDT 24
Finished Jul 22 06:50:45 PM PDT 24
Peak memory 206612 kb
Host smart-0a994650-5922-4a80-9fd5-71d29654e63b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910476187 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.3910476187
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3738951421
Short name T1014
Test name
Test status
Simulation time 56903612 ps
CPU time 1.97 seconds
Started Jul 22 06:50:33 PM PDT 24
Finished Jul 22 06:50:51 PM PDT 24
Peak memory 214824 kb
Host smart-ccc29964-fc66-43fd-b0b2-bf0dc5d47cd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738951421 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3738951421
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.864138374
Short name T1021
Test name
Test status
Simulation time 38834020 ps
CPU time 1.55 seconds
Started Jul 22 06:50:23 PM PDT 24
Finished Jul 22 06:50:37 PM PDT 24
Peak memory 214904 kb
Host smart-d9d5a107-cc66-4f2f-86d0-1e9f68459255
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864138374 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.864138374
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.389168846
Short name T261
Test name
Test status
Simulation time 51366863 ps
CPU time 0.85 seconds
Started Jul 22 06:50:30 PM PDT 24
Finished Jul 22 06:50:46 PM PDT 24
Peak memory 206464 kb
Host smart-78cdd696-2422-46ee-9dcc-5f16ad159d09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389168846 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.389168846
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.1839558342
Short name T1052
Test name
Test status
Simulation time 14890856 ps
CPU time 0.85 seconds
Started Jul 22 06:50:30 PM PDT 24
Finished Jul 22 06:50:46 PM PDT 24
Peak memory 206476 kb
Host smart-368f284b-fadd-487e-9c17-53f1e9c0d62f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839558342 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.1839558342
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.534990505
Short name T1110
Test name
Test status
Simulation time 77808758 ps
CPU time 1.54 seconds
Started Jul 22 06:50:29 PM PDT 24
Finished Jul 22 06:50:45 PM PDT 24
Peak memory 206528 kb
Host smart-f98ddca6-2344-4b5b-b9d4-e72deadf4d93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534990505 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_ou
tstanding.534990505
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.2210449760
Short name T1033
Test name
Test status
Simulation time 314399064 ps
CPU time 2.77 seconds
Started Jul 22 06:50:29 PM PDT 24
Finished Jul 22 06:50:46 PM PDT 24
Peak memory 214860 kb
Host smart-5724a9d7-6209-4307-942b-d5f804373963
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210449760 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2210449760
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3681775156
Short name T283
Test name
Test status
Simulation time 101525337 ps
CPU time 2.62 seconds
Started Jul 22 06:50:29 PM PDT 24
Finished Jul 22 06:50:46 PM PDT 24
Peak memory 206472 kb
Host smart-b4f04be0-529c-45a4-a974-fcb4296bb298
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681775156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.3681775156
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1092807513
Short name T1038
Test name
Test status
Simulation time 18418948 ps
CPU time 1.04 seconds
Started Jul 22 06:50:40 PM PDT 24
Finished Jul 22 06:51:04 PM PDT 24
Peak memory 206580 kb
Host smart-5def4878-acaf-4ba0-ad87-f101fd050f24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092807513 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1092807513
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.184956354
Short name T262
Test name
Test status
Simulation time 15741926 ps
CPU time 0.9 seconds
Started Jul 22 06:50:39 PM PDT 24
Finished Jul 22 06:51:02 PM PDT 24
Peak memory 206412 kb
Host smart-fd009617-8126-40c0-a93b-6b0514a095d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184956354 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.184956354
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.149917652
Short name T1009
Test name
Test status
Simulation time 49245101 ps
CPU time 0.79 seconds
Started Jul 22 06:50:40 PM PDT 24
Finished Jul 22 06:51:04 PM PDT 24
Peak memory 206276 kb
Host smart-356d94e7-510f-47a7-8e9b-ffe9d0a1cdc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149917652 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.149917652
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2266307787
Short name T264
Test name
Test status
Simulation time 40139284 ps
CPU time 1.43 seconds
Started Jul 22 06:50:51 PM PDT 24
Finished Jul 22 06:51:31 PM PDT 24
Peak memory 206568 kb
Host smart-58026645-5496-4deb-8115-85505a7ac78f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266307787 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.2266307787
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.3530399836
Short name T1085
Test name
Test status
Simulation time 26959694 ps
CPU time 1.85 seconds
Started Jul 22 06:50:30 PM PDT 24
Finished Jul 22 06:50:47 PM PDT 24
Peak memory 214676 kb
Host smart-3e5d2d91-9076-4c0e-b37c-62110f43117a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530399836 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3530399836
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2633336639
Short name T287
Test name
Test status
Simulation time 125520395 ps
CPU time 1.38 seconds
Started Jul 22 06:50:40 PM PDT 24
Finished Jul 22 06:51:04 PM PDT 24
Peak memory 214856 kb
Host smart-ac53f791-2d66-4897-af7d-cdc2fb1c450d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633336639 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.2633336639
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.430568483
Short name T1055
Test name
Test status
Simulation time 25729793 ps
CPU time 1.27 seconds
Started Jul 22 06:50:43 PM PDT 24
Finished Jul 22 06:51:11 PM PDT 24
Peak memory 217008 kb
Host smart-d44d426d-325e-4a91-ba33-a71490396765
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430568483 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.430568483
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.3354831559
Short name T1028
Test name
Test status
Simulation time 20703466 ps
CPU time 0.84 seconds
Started Jul 22 06:50:42 PM PDT 24
Finished Jul 22 06:51:09 PM PDT 24
Peak memory 206468 kb
Host smart-771a2f67-fd9a-4efe-9511-9aade63042c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354831559 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.3354831559
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3417413605
Short name T1049
Test name
Test status
Simulation time 14303929 ps
CPU time 0.87 seconds
Started Jul 22 06:50:43 PM PDT 24
Finished Jul 22 06:51:11 PM PDT 24
Peak memory 206548 kb
Host smart-aea4acfe-ef82-4957-9989-d726fd4877ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417413605 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3417413605
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3374042785
Short name T1042
Test name
Test status
Simulation time 23513330 ps
CPU time 1.19 seconds
Started Jul 22 06:50:39 PM PDT 24
Finished Jul 22 06:51:02 PM PDT 24
Peak memory 206508 kb
Host smart-af0e0d71-e598-46ff-ae27-7792c0924c1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374042785 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.3374042785
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.2963980741
Short name T1044
Test name
Test status
Simulation time 81781819 ps
CPU time 1.87 seconds
Started Jul 22 06:50:39 PM PDT 24
Finished Jul 22 06:51:02 PM PDT 24
Peak memory 218360 kb
Host smart-9381cc21-f651-4add-aafc-2112bec6966c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963980741 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2963980741
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.766980286
Short name T1129
Test name
Test status
Simulation time 88065172 ps
CPU time 2.43 seconds
Started Jul 22 06:50:39 PM PDT 24
Finished Jul 22 06:51:04 PM PDT 24
Peak memory 206692 kb
Host smart-14220770-75a4-40af-ba3b-973a2c674cb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766980286 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.766980286
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.40288828
Short name T1046
Test name
Test status
Simulation time 19394623 ps
CPU time 1.09 seconds
Started Jul 22 06:50:43 PM PDT 24
Finished Jul 22 06:51:12 PM PDT 24
Peak memory 216424 kb
Host smart-704925c6-6426-46f7-b019-8be3aa7952a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40288828 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.40288828
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.4016550429
Short name T266
Test name
Test status
Simulation time 99733027 ps
CPU time 0.78 seconds
Started Jul 22 06:50:43 PM PDT 24
Finished Jul 22 06:51:13 PM PDT 24
Peak memory 206348 kb
Host smart-8b6e8a0e-d94b-4829-96a3-ab9810a50c8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016550429 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.4016550429
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3825303401
Short name T1029
Test name
Test status
Simulation time 52511391 ps
CPU time 0.81 seconds
Started Jul 22 06:50:40 PM PDT 24
Finished Jul 22 06:51:04 PM PDT 24
Peak memory 206460 kb
Host smart-49ab1ca1-65fc-44c1-93c1-9d5d00bef60a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825303401 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3825303401
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3946346585
Short name T269
Test name
Test status
Simulation time 15203236 ps
CPU time 0.99 seconds
Started Jul 22 06:50:40 PM PDT 24
Finished Jul 22 06:51:04 PM PDT 24
Peak memory 206504 kb
Host smart-98397ea4-5a74-4a0a-b2ec-5a76454c2ef8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946346585 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3946346585
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.3375816940
Short name T1061
Test name
Test status
Simulation time 102227408 ps
CPU time 2.08 seconds
Started Jul 22 06:51:22 PM PDT 24
Finished Jul 22 06:52:14 PM PDT 24
Peak memory 214524 kb
Host smart-1a41b565-14ce-45aa-a6cf-a782d401cc75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375816940 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3375816940
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3322359733
Short name T1115
Test name
Test status
Simulation time 210029554 ps
CPU time 2.12 seconds
Started Jul 22 06:50:40 PM PDT 24
Finished Jul 22 06:51:05 PM PDT 24
Peak memory 206764 kb
Host smart-d4d27afa-f7cb-4738-ada5-5f8245770ff6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322359733 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.3322359733
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2439161243
Short name T1093
Test name
Test status
Simulation time 34087852 ps
CPU time 1.39 seconds
Started Jul 22 06:50:44 PM PDT 24
Finished Jul 22 06:51:14 PM PDT 24
Peak memory 214776 kb
Host smart-4f423c48-1212-4310-8f5f-75203d68b259
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439161243 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2439161243
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.1066699352
Short name T1008
Test name
Test status
Simulation time 44340090 ps
CPU time 0.84 seconds
Started Jul 22 06:50:38 PM PDT 24
Finished Jul 22 06:51:00 PM PDT 24
Peak memory 206280 kb
Host smart-a305e58a-c998-4c47-a1e3-258c2836be7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066699352 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1066699352
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.931158837
Short name T267
Test name
Test status
Simulation time 18444889 ps
CPU time 1 seconds
Started Jul 22 06:50:47 PM PDT 24
Finished Jul 22 06:51:21 PM PDT 24
Peak memory 206556 kb
Host smart-e2894d24-e03f-4d91-898e-7b32f4c71a26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931158837 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_ou
tstanding.931158837
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.130849073
Short name T1056
Test name
Test status
Simulation time 846063549 ps
CPU time 2.69 seconds
Started Jul 22 06:50:37 PM PDT 24
Finished Jul 22 06:51:00 PM PDT 24
Peak memory 214792 kb
Host smart-7c5d062c-e4ad-41b5-8b06-521edebcd561
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130849073 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.130849073
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.834337042
Short name T1041
Test name
Test status
Simulation time 155231687 ps
CPU time 1.42 seconds
Started Jul 22 06:50:42 PM PDT 24
Finished Jul 22 06:51:09 PM PDT 24
Peak memory 206512 kb
Host smart-10ff703e-1ffb-4cba-83f3-cc4faeedebb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834337042 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.834337042
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3317671548
Short name T1053
Test name
Test status
Simulation time 17417312 ps
CPU time 0.97 seconds
Started Jul 22 06:50:40 PM PDT 24
Finished Jul 22 06:51:04 PM PDT 24
Peak memory 206588 kb
Host smart-6d20e41a-f6c2-487c-966b-92af9ce9ae81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317671548 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3317671548
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1497318307
Short name T1086
Test name
Test status
Simulation time 93631188 ps
CPU time 0.83 seconds
Started Jul 22 06:50:40 PM PDT 24
Finished Jul 22 06:51:04 PM PDT 24
Peak memory 206264 kb
Host smart-959b3ce7-fd9a-41a5-8fb2-6c70b82ac156
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497318307 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1497318307
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2374510502
Short name T1113
Test name
Test status
Simulation time 89415194 ps
CPU time 0.82 seconds
Started Jul 22 06:50:40 PM PDT 24
Finished Jul 22 06:51:04 PM PDT 24
Peak memory 206496 kb
Host smart-e74e5b12-3c47-4972-af13-ac03c190026a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374510502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2374510502
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.79211964
Short name T268
Test name
Test status
Simulation time 56354962 ps
CPU time 0.97 seconds
Started Jul 22 06:50:38 PM PDT 24
Finished Jul 22 06:51:00 PM PDT 24
Peak memory 206556 kb
Host smart-c38b6d96-960a-4003-b44c-b87c0d391ea7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79211964 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_out
standing.79211964
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.63322529
Short name T1026
Test name
Test status
Simulation time 104281053 ps
CPU time 2.15 seconds
Started Jul 22 06:50:51 PM PDT 24
Finished Jul 22 06:51:31 PM PDT 24
Peak memory 214772 kb
Host smart-e532d180-65cb-4945-802f-b7837fc09590
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63322529 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.63322529
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.414514948
Short name T1063
Test name
Test status
Simulation time 49428230 ps
CPU time 1.72 seconds
Started Jul 22 06:50:40 PM PDT 24
Finished Jul 22 06:51:05 PM PDT 24
Peak memory 206520 kb
Host smart-c8e72b09-21fd-4bbb-a109-643cf61c03b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414514948 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.414514948
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3271034763
Short name T1098
Test name
Test status
Simulation time 46118447 ps
CPU time 1.22 seconds
Started Jul 22 06:50:39 PM PDT 24
Finished Jul 22 06:51:02 PM PDT 24
Peak memory 223052 kb
Host smart-433a9e33-42a9-44c1-96f2-7cb80e159067
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271034763 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3271034763
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.3693032864
Short name T1122
Test name
Test status
Simulation time 15511033 ps
CPU time 0.94 seconds
Started Jul 22 06:50:42 PM PDT 24
Finished Jul 22 06:51:11 PM PDT 24
Peak memory 206468 kb
Host smart-927f7718-387c-46ad-865e-4515c8a61f23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693032864 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.3693032864
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.1504109622
Short name T1071
Test name
Test status
Simulation time 13427766 ps
CPU time 0.88 seconds
Started Jul 22 06:50:41 PM PDT 24
Finished Jul 22 06:51:08 PM PDT 24
Peak memory 206472 kb
Host smart-4d6c0f12-3384-49f9-aca6-1d407c7dea2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504109622 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.1504109622
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.802032780
Short name T1064
Test name
Test status
Simulation time 37995200 ps
CPU time 0.99 seconds
Started Jul 22 06:50:40 PM PDT 24
Finished Jul 22 06:51:04 PM PDT 24
Peak memory 206444 kb
Host smart-1f1a4fee-a4b4-41de-aa95-3e1a9e612141
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802032780 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_ou
tstanding.802032780
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.28809878
Short name T1040
Test name
Test status
Simulation time 43887202 ps
CPU time 2.85 seconds
Started Jul 22 06:50:38 PM PDT 24
Finished Jul 22 06:51:02 PM PDT 24
Peak memory 214756 kb
Host smart-734345e5-33e8-44ca-af5c-1733c8b6c2a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28809878 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.28809878
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3314794076
Short name T282
Test name
Test status
Simulation time 89995086 ps
CPU time 1.57 seconds
Started Jul 22 06:50:38 PM PDT 24
Finished Jul 22 06:51:01 PM PDT 24
Peak memory 214984 kb
Host smart-f191a7db-b2b8-48cf-a760-182f0ec053c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314794076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3314794076
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2327577664
Short name T259
Test name
Test status
Simulation time 89646576 ps
CPU time 1.23 seconds
Started Jul 22 06:50:15 PM PDT 24
Finished Jul 22 06:50:21 PM PDT 24
Peak memory 206556 kb
Host smart-0c461b2b-f24a-4834-84ab-042716df242d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327577664 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.2327577664
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1966577729
Short name T253
Test name
Test status
Simulation time 34891658 ps
CPU time 2.03 seconds
Started Jul 22 06:50:16 PM PDT 24
Finished Jul 22 06:50:24 PM PDT 24
Peak memory 206556 kb
Host smart-038c16cd-783c-47e3-85ca-0ff42dba8286
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966577729 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1966577729
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2659974739
Short name T1079
Test name
Test status
Simulation time 46793285 ps
CPU time 0.96 seconds
Started Jul 22 06:50:16 PM PDT 24
Finished Jul 22 06:50:22 PM PDT 24
Peak memory 206408 kb
Host smart-42a3a5ef-c4a7-46b1-ab31-836c20fb79ad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659974739 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.2659974739
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2094241640
Short name T1018
Test name
Test status
Simulation time 20236438 ps
CPU time 1.49 seconds
Started Jul 22 06:50:15 PM PDT 24
Finished Jul 22 06:50:21 PM PDT 24
Peak memory 214456 kb
Host smart-cefd67f2-b0c3-417e-a8fa-b36122e090c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094241640 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.2094241640
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.1283785483
Short name T1089
Test name
Test status
Simulation time 54833564 ps
CPU time 0.91 seconds
Started Jul 22 06:50:16 PM PDT 24
Finished Jul 22 06:50:22 PM PDT 24
Peak memory 206500 kb
Host smart-c65a2d7b-46ad-4072-a9ac-caa602b157ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283785483 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.1283785483
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1205914566
Short name T1022
Test name
Test status
Simulation time 24711410 ps
CPU time 0.9 seconds
Started Jul 22 06:50:15 PM PDT 24
Finished Jul 22 06:50:20 PM PDT 24
Peak memory 206032 kb
Host smart-dbde8b84-e49e-438e-a8d5-ac9eb5ec6cba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205914566 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1205914566
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2105820092
Short name T1080
Test name
Test status
Simulation time 27314970 ps
CPU time 1.03 seconds
Started Jul 22 06:50:13 PM PDT 24
Finished Jul 22 06:50:18 PM PDT 24
Peak memory 206544 kb
Host smart-5acd4692-20ee-41ff-a9ca-b968bee031cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105820092 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.2105820092
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.3718002717
Short name T1005
Test name
Test status
Simulation time 167434373 ps
CPU time 2.65 seconds
Started Jul 22 06:50:13 PM PDT 24
Finished Jul 22 06:50:19 PM PDT 24
Peak memory 214868 kb
Host smart-2da25632-3e90-4068-aa0c-a684f1904b7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718002717 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.3718002717
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.4185910410
Short name T1076
Test name
Test status
Simulation time 41738273 ps
CPU time 1.5 seconds
Started Jul 22 06:50:17 PM PDT 24
Finished Jul 22 06:50:25 PM PDT 24
Peak memory 206768 kb
Host smart-ae3577a6-0457-4b32-8bee-4722e02b656f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185910410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.4185910410
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.29760273
Short name T1109
Test name
Test status
Simulation time 23244578 ps
CPU time 0.83 seconds
Started Jul 22 06:50:42 PM PDT 24
Finished Jul 22 06:51:09 PM PDT 24
Peak memory 206476 kb
Host smart-af7e23d8-86cb-4342-a989-5fc1d35914ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29760273 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.29760273
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.2600268082
Short name T1043
Test name
Test status
Simulation time 40862430 ps
CPU time 0.82 seconds
Started Jul 22 06:50:42 PM PDT 24
Finished Jul 22 06:51:09 PM PDT 24
Peak memory 206536 kb
Host smart-b7bef60f-ed33-46f2-9644-a51550c633fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600268082 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.2600268082
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.2473947905
Short name T1097
Test name
Test status
Simulation time 32014389 ps
CPU time 0.77 seconds
Started Jul 22 06:50:42 PM PDT 24
Finished Jul 22 06:51:10 PM PDT 24
Peak memory 206296 kb
Host smart-3f057ea9-da25-47d3-b4ce-14199cbc9d8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473947905 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2473947905
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.4162445959
Short name T1130
Test name
Test status
Simulation time 48390864 ps
CPU time 0.86 seconds
Started Jul 22 06:50:41 PM PDT 24
Finished Jul 22 06:51:08 PM PDT 24
Peak memory 206468 kb
Host smart-a8da2ff1-d43c-46c4-ba8a-dc79bdea8a47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162445959 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.4162445959
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.2405152230
Short name T1106
Test name
Test status
Simulation time 14363770 ps
CPU time 0.86 seconds
Started Jul 22 06:50:42 PM PDT 24
Finished Jul 22 06:51:09 PM PDT 24
Peak memory 206612 kb
Host smart-25476299-0550-49e2-8e17-c4d5c71eddc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405152230 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.2405152230
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.1434858591
Short name T1073
Test name
Test status
Simulation time 16627990 ps
CPU time 0.93 seconds
Started Jul 22 06:50:40 PM PDT 24
Finished Jul 22 06:51:04 PM PDT 24
Peak memory 206460 kb
Host smart-77170bd1-7d00-478f-9c8a-58efa981549f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434858591 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.1434858591
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.2489736795
Short name T1062
Test name
Test status
Simulation time 11081035 ps
CPU time 0.81 seconds
Started Jul 22 06:50:40 PM PDT 24
Finished Jul 22 06:51:04 PM PDT 24
Peak memory 206468 kb
Host smart-28b755c9-640f-4303-a845-c18292f781d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489736795 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2489736795
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.1192001012
Short name T1070
Test name
Test status
Simulation time 24077328 ps
CPU time 0.85 seconds
Started Jul 22 06:50:41 PM PDT 24
Finished Jul 22 06:51:07 PM PDT 24
Peak memory 206520 kb
Host smart-12623410-c9b4-40fe-bae7-6b88108bd580
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192001012 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1192001012
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.349600798
Short name T1039
Test name
Test status
Simulation time 18554513 ps
CPU time 0.89 seconds
Started Jul 22 06:50:38 PM PDT 24
Finished Jul 22 06:51:00 PM PDT 24
Peak memory 206576 kb
Host smart-ec423fab-9191-4054-a836-6fe008167077
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349600798 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.349600798
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.3319941000
Short name T1017
Test name
Test status
Simulation time 19320834 ps
CPU time 0.81 seconds
Started Jul 22 06:50:34 PM PDT 24
Finished Jul 22 06:50:52 PM PDT 24
Peak memory 206320 kb
Host smart-04865e78-1195-4e3a-9116-3928d1b126b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319941000 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.3319941000
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1229239591
Short name T251
Test name
Test status
Simulation time 19046935 ps
CPU time 1.25 seconds
Started Jul 22 06:50:25 PM PDT 24
Finished Jul 22 06:50:40 PM PDT 24
Peak memory 206484 kb
Host smart-31907e23-47f8-4147-be4b-0be922923885
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229239591 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.1229239591
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3995120659
Short name T1025
Test name
Test status
Simulation time 62555854 ps
CPU time 3.39 seconds
Started Jul 22 06:50:25 PM PDT 24
Finished Jul 22 06:50:42 PM PDT 24
Peak memory 206500 kb
Host smart-24760e22-63fe-484f-a38e-8c6a62cdae75
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995120659 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3995120659
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.394532294
Short name T1123
Test name
Test status
Simulation time 62668302 ps
CPU time 0.81 seconds
Started Jul 22 06:50:22 PM PDT 24
Finished Jul 22 06:50:34 PM PDT 24
Peak memory 206236 kb
Host smart-0b9c10e4-ac08-4730-be2e-fc7e0aef6bee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394532294 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.394532294
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.529253220
Short name T1036
Test name
Test status
Simulation time 30907461 ps
CPU time 1.94 seconds
Started Jul 22 06:50:25 PM PDT 24
Finished Jul 22 06:50:40 PM PDT 24
Peak memory 214564 kb
Host smart-912173c9-c241-4597-9691-4b23986d2499
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529253220 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.529253220
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.2635284271
Short name T1027
Test name
Test status
Simulation time 118460389 ps
CPU time 0.92 seconds
Started Jul 22 06:50:28 PM PDT 24
Finished Jul 22 06:50:43 PM PDT 24
Peak memory 206292 kb
Host smart-6bc39cb7-b758-4ad1-b9bb-f5f1e8478ce1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635284271 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.2635284271
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.456435399
Short name T1126
Test name
Test status
Simulation time 32750508 ps
CPU time 0.85 seconds
Started Jul 22 06:50:54 PM PDT 24
Finished Jul 22 06:51:35 PM PDT 24
Peak memory 206444 kb
Host smart-7a392f30-2985-4e96-8d65-f322de19702a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456435399 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.456435399
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1172123368
Short name T1127
Test name
Test status
Simulation time 24882452 ps
CPU time 1.11 seconds
Started Jul 22 06:51:21 PM PDT 24
Finished Jul 22 06:52:12 PM PDT 24
Peak memory 206528 kb
Host smart-99efc331-5f24-4c38-9863-ce0d2e6cf1c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172123368 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.1172123368
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.3431793363
Short name T1111
Test name
Test status
Simulation time 150863506 ps
CPU time 1.69 seconds
Started Jul 22 06:50:27 PM PDT 24
Finished Jul 22 06:50:46 PM PDT 24
Peak memory 214788 kb
Host smart-87bcec6b-4447-4e51-a01a-f8533045329a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431793363 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3431793363
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.4234664110
Short name T286
Test name
Test status
Simulation time 160010470 ps
CPU time 1.54 seconds
Started Jul 22 06:50:16 PM PDT 24
Finished Jul 22 06:50:22 PM PDT 24
Peak memory 206644 kb
Host smart-ea103349-6d9a-49b6-aebc-a23f397277e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234664110 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.4234664110
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.89323449
Short name T1114
Test name
Test status
Simulation time 49620815 ps
CPU time 0.78 seconds
Started Jul 22 06:50:38 PM PDT 24
Finished Jul 22 06:51:00 PM PDT 24
Peak memory 206284 kb
Host smart-d9484eef-1802-4bc2-b8c0-063aef345f9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89323449 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.89323449
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.880271835
Short name T1077
Test name
Test status
Simulation time 37506975 ps
CPU time 0.79 seconds
Started Jul 22 06:50:42 PM PDT 24
Finished Jul 22 06:51:09 PM PDT 24
Peak memory 206276 kb
Host smart-05e0af76-becd-477b-9ba5-6b3c7d6569ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880271835 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.880271835
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.3105267787
Short name T1072
Test name
Test status
Simulation time 14871307 ps
CPU time 0.88 seconds
Started Jul 22 06:50:38 PM PDT 24
Finished Jul 22 06:51:00 PM PDT 24
Peak memory 206384 kb
Host smart-88a8fb69-ec0c-41ae-9276-762cf8cfffa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105267787 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3105267787
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.3006593168
Short name T1003
Test name
Test status
Simulation time 14810885 ps
CPU time 0.9 seconds
Started Jul 22 06:50:42 PM PDT 24
Finished Jul 22 06:51:09 PM PDT 24
Peak memory 206472 kb
Host smart-b12b85e0-0fe4-4355-9059-86a088a5a420
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006593168 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3006593168
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.494614666
Short name T1035
Test name
Test status
Simulation time 50046557 ps
CPU time 0.88 seconds
Started Jul 22 06:50:43 PM PDT 24
Finished Jul 22 06:51:12 PM PDT 24
Peak memory 206468 kb
Host smart-ec5e1c45-90be-40f6-a3f7-cee1d09b551d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494614666 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.494614666
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1418893554
Short name T1105
Test name
Test status
Simulation time 15344855 ps
CPU time 0.87 seconds
Started Jul 22 06:50:40 PM PDT 24
Finished Jul 22 06:51:04 PM PDT 24
Peak memory 206464 kb
Host smart-b65453ac-c5a7-48b8-ad5f-d96331a7f1a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418893554 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1418893554
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3957868613
Short name T1067
Test name
Test status
Simulation time 27560717 ps
CPU time 0.87 seconds
Started Jul 22 06:50:48 PM PDT 24
Finished Jul 22 06:51:23 PM PDT 24
Peak memory 206536 kb
Host smart-12be9ef4-90bd-4ada-b939-5eb2d2bbf8bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957868613 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3957868613
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.3910325717
Short name T1020
Test name
Test status
Simulation time 26456839 ps
CPU time 0.82 seconds
Started Jul 22 06:50:48 PM PDT 24
Finished Jul 22 06:51:22 PM PDT 24
Peak memory 206372 kb
Host smart-cdc429ec-b6ea-4dbc-9dd4-85abd4b31157
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910325717 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.3910325717
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.1832116077
Short name T1012
Test name
Test status
Simulation time 19568075 ps
CPU time 0.79 seconds
Started Jul 22 06:50:54 PM PDT 24
Finished Jul 22 06:51:35 PM PDT 24
Peak memory 206348 kb
Host smart-3d5dd45a-1764-4c64-8cab-bf7fab25fa10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832116077 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1832116077
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.3880303223
Short name T1034
Test name
Test status
Simulation time 15088648 ps
CPU time 0.8 seconds
Started Jul 22 06:50:49 PM PDT 24
Finished Jul 22 06:51:25 PM PDT 24
Peak memory 206528 kb
Host smart-7b57dea5-73af-421e-be0e-6b4133d3e633
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880303223 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3880303223
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.25218368
Short name T254
Test name
Test status
Simulation time 72464596 ps
CPU time 1.49 seconds
Started Jul 22 06:50:33 PM PDT 24
Finished Jul 22 06:50:51 PM PDT 24
Peak memory 206460 kb
Host smart-7ac07a8e-8861-419e-a7ff-32b283b1b501
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25218368 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.25218368
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1224864285
Short name T999
Test name
Test status
Simulation time 172109748 ps
CPU time 4.92 seconds
Started Jul 22 06:50:23 PM PDT 24
Finished Jul 22 06:50:41 PM PDT 24
Peak memory 206452 kb
Host smart-78a5e89d-aab9-41e4-8312-e1154525285d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224864285 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.1224864285
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3007009328
Short name T1117
Test name
Test status
Simulation time 88868708 ps
CPU time 0.91 seconds
Started Jul 22 06:50:23 PM PDT 24
Finished Jul 22 06:50:36 PM PDT 24
Peak memory 206384 kb
Host smart-c93960aa-8e5f-4222-acb3-0baa8a5b4b37
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007009328 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3007009328
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.448657347
Short name T1119
Test name
Test status
Simulation time 114616525 ps
CPU time 1.72 seconds
Started Jul 22 06:50:25 PM PDT 24
Finished Jul 22 06:50:40 PM PDT 24
Peak memory 214820 kb
Host smart-02c12653-6cc7-4ad8-a4ca-ba5bef83bdd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448657347 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.448657347
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.1673134570
Short name T1116
Test name
Test status
Simulation time 47047892 ps
CPU time 0.93 seconds
Started Jul 22 06:50:24 PM PDT 24
Finished Jul 22 06:50:37 PM PDT 24
Peak memory 206480 kb
Host smart-eaacbb9c-7963-4a80-befa-04c009ee7179
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673134570 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.1673134570
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.1548381486
Short name T1045
Test name
Test status
Simulation time 18193280 ps
CPU time 0.85 seconds
Started Jul 22 06:50:31 PM PDT 24
Finished Jul 22 06:50:47 PM PDT 24
Peak memory 206448 kb
Host smart-0b99dfbc-d732-4c3f-bffa-c6c509de9b6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548381486 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1548381486
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1909894745
Short name T1104
Test name
Test status
Simulation time 36296855 ps
CPU time 1.44 seconds
Started Jul 22 06:50:24 PM PDT 24
Finished Jul 22 06:50:37 PM PDT 24
Peak memory 206516 kb
Host smart-6eb2c81c-6fdf-4667-b3c2-4ac8fcb25c09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909894745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.1909894745
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.338700258
Short name T1066
Test name
Test status
Simulation time 176566454 ps
CPU time 3.11 seconds
Started Jul 22 06:50:24 PM PDT 24
Finished Jul 22 06:50:40 PM PDT 24
Peak memory 214880 kb
Host smart-61130c24-1908-46fe-a239-7bad5831af86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338700258 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.338700258
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3824219380
Short name T285
Test name
Test status
Simulation time 182858577 ps
CPU time 2.41 seconds
Started Jul 22 06:50:24 PM PDT 24
Finished Jul 22 06:50:40 PM PDT 24
Peak memory 214696 kb
Host smart-c1e85492-c05e-4885-9908-dbb4b6b99da8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824219380 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.3824219380
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.3315296660
Short name T1075
Test name
Test status
Simulation time 56585890 ps
CPU time 0.87 seconds
Started Jul 22 06:50:48 PM PDT 24
Finished Jul 22 06:51:24 PM PDT 24
Peak memory 206476 kb
Host smart-16074127-e2cc-46d7-8242-fb6671d73276
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315296660 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.3315296660
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.1409030831
Short name T1051
Test name
Test status
Simulation time 14872304 ps
CPU time 0.85 seconds
Started Jul 22 06:50:48 PM PDT 24
Finished Jul 22 06:51:22 PM PDT 24
Peak memory 206716 kb
Host smart-64543521-0790-407b-8be1-1fad7d316633
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409030831 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1409030831
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.163435360
Short name T1007
Test name
Test status
Simulation time 12072566 ps
CPU time 0.84 seconds
Started Jul 22 06:50:49 PM PDT 24
Finished Jul 22 06:51:26 PM PDT 24
Peak memory 206440 kb
Host smart-3f46a158-be71-4810-8b7d-c6e9cd10ae9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163435360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.163435360
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.481349384
Short name T1004
Test name
Test status
Simulation time 52174864 ps
CPU time 0.84 seconds
Started Jul 22 06:50:49 PM PDT 24
Finished Jul 22 06:51:25 PM PDT 24
Peak memory 206528 kb
Host smart-29608e52-340f-4aef-9097-f36e157f3149
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481349384 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.481349384
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.374299695
Short name T1087
Test name
Test status
Simulation time 58501685 ps
CPU time 0.88 seconds
Started Jul 22 06:50:49 PM PDT 24
Finished Jul 22 06:51:26 PM PDT 24
Peak memory 206428 kb
Host smart-21300a65-a974-4b12-9ccb-f64c86a29802
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374299695 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.374299695
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.2398655607
Short name T1128
Test name
Test status
Simulation time 81347125 ps
CPU time 0.8 seconds
Started Jul 22 06:50:50 PM PDT 24
Finished Jul 22 06:51:27 PM PDT 24
Peak memory 206268 kb
Host smart-e4b0bcf3-f22c-45e5-97ea-7cef5a1183fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398655607 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.2398655607
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.3379311652
Short name T1096
Test name
Test status
Simulation time 20069732 ps
CPU time 0.86 seconds
Started Jul 22 06:50:53 PM PDT 24
Finished Jul 22 06:51:34 PM PDT 24
Peak memory 206272 kb
Host smart-607dd7c7-5e13-47e0-8073-cfb0a600b89c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379311652 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.3379311652
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.159785164
Short name T1094
Test name
Test status
Simulation time 36597097 ps
CPU time 0.83 seconds
Started Jul 22 06:51:09 PM PDT 24
Finished Jul 22 06:51:56 PM PDT 24
Peak memory 206424 kb
Host smart-84f2134c-f47a-410a-938b-28c376765a49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159785164 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.159785164
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.274242514
Short name T1112
Test name
Test status
Simulation time 35749250 ps
CPU time 0.88 seconds
Started Jul 22 06:50:49 PM PDT 24
Finished Jul 22 06:51:25 PM PDT 24
Peak memory 206464 kb
Host smart-d39abdee-b101-4663-b4b4-7e71397b9603
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274242514 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.274242514
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.3684909449
Short name T1090
Test name
Test status
Simulation time 144930264 ps
CPU time 0.84 seconds
Started Jul 22 06:50:56 PM PDT 24
Finished Jul 22 06:51:36 PM PDT 24
Peak memory 206376 kb
Host smart-074900c8-fd3c-47d1-a897-2f324211f1e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684909449 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.3684909449
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1797692693
Short name T1024
Test name
Test status
Simulation time 137053441 ps
CPU time 2.02 seconds
Started Jul 22 06:51:20 PM PDT 24
Finished Jul 22 06:52:12 PM PDT 24
Peak memory 214896 kb
Host smart-a32c1127-a9ea-4415-838b-2cb811d6ebc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797692693 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1797692693
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.3013614068
Short name T270
Test name
Test status
Simulation time 16526006 ps
CPU time 0.92 seconds
Started Jul 22 06:50:29 PM PDT 24
Finished Jul 22 06:50:45 PM PDT 24
Peak memory 206444 kb
Host smart-c56ce5a6-14a6-40ca-920d-c1e1253657dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013614068 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.3013614068
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.2935725261
Short name T1013
Test name
Test status
Simulation time 16092411 ps
CPU time 0.91 seconds
Started Jul 22 06:50:30 PM PDT 24
Finished Jul 22 06:50:47 PM PDT 24
Peak memory 206452 kb
Host smart-cbe211a0-47b5-4f7a-a75c-9b586d927e3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935725261 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.2935725261
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1165385430
Short name T1100
Test name
Test status
Simulation time 17958843 ps
CPU time 1.05 seconds
Started Jul 22 06:50:30 PM PDT 24
Finished Jul 22 06:50:47 PM PDT 24
Peak memory 206504 kb
Host smart-880d742f-fee6-43a3-af23-b5a77bd3c93f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165385430 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1165385430
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.1319949348
Short name T1002
Test name
Test status
Simulation time 26187629 ps
CPU time 1.9 seconds
Started Jul 22 06:51:24 PM PDT 24
Finished Jul 22 06:52:18 PM PDT 24
Peak memory 223028 kb
Host smart-6e083c9e-2fb6-4f3a-8360-3a65366dc4f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319949348 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.1319949348
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1158980206
Short name T1103
Test name
Test status
Simulation time 129250762 ps
CPU time 1.9 seconds
Started Jul 22 06:50:31 PM PDT 24
Finished Jul 22 06:50:48 PM PDT 24
Peak memory 214704 kb
Host smart-25824c5a-b7d9-4847-a9be-aa73a8a4ac61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158980206 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1158980206
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1937433427
Short name T1095
Test name
Test status
Simulation time 27513238 ps
CPU time 0.99 seconds
Started Jul 22 06:50:28 PM PDT 24
Finished Jul 22 06:50:44 PM PDT 24
Peak memory 206860 kb
Host smart-69bfacaa-2cad-4383-bb89-eaa480a2900b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937433427 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1937433427
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.359833224
Short name T250
Test name
Test status
Simulation time 32426991 ps
CPU time 0.81 seconds
Started Jul 22 06:50:23 PM PDT 24
Finished Jul 22 06:50:35 PM PDT 24
Peak memory 206280 kb
Host smart-c2aaf51a-ad69-4aea-8932-c1bae68c94dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359833224 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.359833224
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.2945891966
Short name T1124
Test name
Test status
Simulation time 20308318 ps
CPU time 0.83 seconds
Started Jul 22 06:50:34 PM PDT 24
Finished Jul 22 06:50:53 PM PDT 24
Peak memory 206560 kb
Host smart-36db724b-910a-4921-ad31-15c87b27fb7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945891966 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.2945891966
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1176289785
Short name T1125
Test name
Test status
Simulation time 28705610 ps
CPU time 1.03 seconds
Started Jul 22 06:50:24 PM PDT 24
Finished Jul 22 06:50:37 PM PDT 24
Peak memory 206528 kb
Host smart-23600668-5b1c-452d-8fb8-0bdc64343f1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176289785 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.1176289785
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3047253479
Short name T1006
Test name
Test status
Simulation time 421151763 ps
CPU time 3.96 seconds
Started Jul 22 06:50:25 PM PDT 24
Finished Jul 22 06:50:41 PM PDT 24
Peak memory 214900 kb
Host smart-ec2e368c-2efa-4741-8aa0-db0562d98509
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047253479 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3047253479
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1213049817
Short name T279
Test name
Test status
Simulation time 92282260 ps
CPU time 2.17 seconds
Started Jul 22 06:50:28 PM PDT 24
Finished Jul 22 06:50:45 PM PDT 24
Peak memory 206596 kb
Host smart-d4405b56-bf5c-4ede-b48e-3a6ab091021a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213049817 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.1213049817
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.671067495
Short name T1011
Test name
Test status
Simulation time 68389687 ps
CPU time 1.39 seconds
Started Jul 22 06:50:26 PM PDT 24
Finished Jul 22 06:50:42 PM PDT 24
Peak memory 217932 kb
Host smart-2ed904e3-31e3-4588-b189-c0baa234f763
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671067495 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.671067495
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.2096977172
Short name T1121
Test name
Test status
Simulation time 27982919 ps
CPU time 0.91 seconds
Started Jul 22 06:50:25 PM PDT 24
Finished Jul 22 06:50:40 PM PDT 24
Peak memory 206492 kb
Host smart-6103be6e-755e-4a01-930c-d3cce36e89b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096977172 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.2096977172
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.1030473273
Short name T1000
Test name
Test status
Simulation time 19384903 ps
CPU time 0.9 seconds
Started Jul 22 06:51:14 PM PDT 24
Finished Jul 22 06:52:04 PM PDT 24
Peak memory 206360 kb
Host smart-4586665c-f957-4eb9-a133-3f6c5b4fa097
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030473273 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.1030473273
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.789484120
Short name T265
Test name
Test status
Simulation time 75002797 ps
CPU time 1.18 seconds
Started Jul 22 06:50:22 PM PDT 24
Finished Jul 22 06:50:34 PM PDT 24
Peak memory 206572 kb
Host smart-5dfeb8ac-ef4c-41c7-b280-31a46919d3df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789484120 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_out
standing.789484120
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.3039173613
Short name T1030
Test name
Test status
Simulation time 57345729 ps
CPU time 1.9 seconds
Started Jul 22 06:50:25 PM PDT 24
Finished Jul 22 06:50:40 PM PDT 24
Peak memory 214664 kb
Host smart-0130ea2e-f943-4312-9e74-5c6319725f0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039173613 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.3039173613
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.4084984502
Short name T1058
Test name
Test status
Simulation time 223859348 ps
CPU time 1.59 seconds
Started Jul 22 06:50:27 PM PDT 24
Finished Jul 22 06:50:43 PM PDT 24
Peak memory 206780 kb
Host smart-7ea5c0f9-1ae2-4762-9c45-3e6c5ecc8037
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084984502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.4084984502
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2882002280
Short name T1050
Test name
Test status
Simulation time 54518190 ps
CPU time 1.35 seconds
Started Jul 22 06:50:25 PM PDT 24
Finished Jul 22 06:50:40 PM PDT 24
Peak memory 217936 kb
Host smart-6a362534-5cbe-4632-991e-624235932b0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882002280 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.2882002280
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.2052782834
Short name T255
Test name
Test status
Simulation time 20358875 ps
CPU time 0.87 seconds
Started Jul 22 06:50:22 PM PDT 24
Finished Jul 22 06:50:34 PM PDT 24
Peak memory 206444 kb
Host smart-d35daa7d-d85a-4c12-814a-16d48e5e9f3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052782834 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.2052782834
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.3860961298
Short name T1019
Test name
Test status
Simulation time 36667258 ps
CPU time 0.79 seconds
Started Jul 22 06:50:23 PM PDT 24
Finished Jul 22 06:50:35 PM PDT 24
Peak memory 206268 kb
Host smart-81bf5089-576b-49d9-8288-c0ce64196339
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860961298 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.3860961298
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3648823192
Short name T1068
Test name
Test status
Simulation time 36337541 ps
CPU time 1.11 seconds
Started Jul 22 06:50:26 PM PDT 24
Finished Jul 22 06:50:41 PM PDT 24
Peak memory 206524 kb
Host smart-7fdbdde6-7f1d-4ae4-80a5-737a5eddc10e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648823192 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.3648823192
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.1030217798
Short name T1016
Test name
Test status
Simulation time 222142640 ps
CPU time 1.97 seconds
Started Jul 22 06:50:27 PM PDT 24
Finished Jul 22 06:50:43 PM PDT 24
Peak memory 214824 kb
Host smart-b6c72e54-2974-45db-b743-86ae419e9ebb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030217798 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.1030217798
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2738164613
Short name T1120
Test name
Test status
Simulation time 84180574 ps
CPU time 2.03 seconds
Started Jul 22 06:51:00 PM PDT 24
Finished Jul 22 06:51:47 PM PDT 24
Peak memory 206508 kb
Host smart-3c64289a-61c0-4e7b-ad27-fe0908036d4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738164613 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2738164613
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1297147762
Short name T1010
Test name
Test status
Simulation time 34417534 ps
CPU time 1.36 seconds
Started Jul 22 06:50:26 PM PDT 24
Finished Jul 22 06:50:42 PM PDT 24
Peak memory 214880 kb
Host smart-f55290ae-e9df-4507-873c-feeedc3c8599
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297147762 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.1297147762
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.1932836098
Short name T257
Test name
Test status
Simulation time 19538938 ps
CPU time 0.96 seconds
Started Jul 22 06:50:25 PM PDT 24
Finished Jul 22 06:50:39 PM PDT 24
Peak memory 206484 kb
Host smart-02feaa09-e13b-44d8-8dd2-c64d45e132a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932836098 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.1932836098
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.1483865472
Short name T1102
Test name
Test status
Simulation time 26977699 ps
CPU time 0.89 seconds
Started Jul 22 06:50:27 PM PDT 24
Finished Jul 22 06:50:42 PM PDT 24
Peak memory 206452 kb
Host smart-bcf080be-74f6-4c31-8192-9f9ec0b8f366
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483865472 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.1483865472
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.817062118
Short name T1118
Test name
Test status
Simulation time 100507259 ps
CPU time 1.1 seconds
Started Jul 22 06:50:23 PM PDT 24
Finished Jul 22 06:50:36 PM PDT 24
Peak memory 206608 kb
Host smart-d1e6b31a-6ff8-42e9-ae8e-64853e110499
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817062118 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_out
standing.817062118
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.2928583662
Short name T1048
Test name
Test status
Simulation time 156950003 ps
CPU time 2.46 seconds
Started Jul 22 06:50:27 PM PDT 24
Finished Jul 22 06:50:44 PM PDT 24
Peak memory 215080 kb
Host smart-f012c14b-e302-46b5-a8d9-188a5d3d85cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928583662 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.2928583662
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2299253668
Short name T277
Test name
Test status
Simulation time 309645542 ps
CPU time 2.42 seconds
Started Jul 22 06:50:33 PM PDT 24
Finished Jul 22 06:50:51 PM PDT 24
Peak memory 214792 kb
Host smart-b550fc69-01f8-43bd-a667-c0e86cfc5e4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299253668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.2299253668
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.498359212
Short name T381
Test name
Test status
Simulation time 28319227 ps
CPU time 1.23 seconds
Started Jul 22 05:41:41 PM PDT 24
Finished Jul 22 05:41:43 PM PDT 24
Peak memory 221224 kb
Host smart-69bd2178-f4f8-43f5-970b-c80a54f02a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498359212 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.498359212
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_disable.210154791
Short name T888
Test name
Test status
Simulation time 73694152 ps
CPU time 0.87 seconds
Started Jul 22 05:41:42 PM PDT 24
Finished Jul 22 05:41:44 PM PDT 24
Peak memory 216588 kb
Host smart-9c6aa838-0385-45e5-ac8e-9fb72708d6de
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210154791 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.210154791
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.4125067147
Short name T203
Test name
Test status
Simulation time 39754963 ps
CPU time 1.38 seconds
Started Jul 22 05:41:44 PM PDT 24
Finished Jul 22 05:41:46 PM PDT 24
Peak memory 217288 kb
Host smart-44caeb02-65bd-4f3e-aa20-dc9dfbc6f272
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125067147 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.4125067147
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.1258546503
Short name T185
Test name
Test status
Simulation time 21738267 ps
CPU time 1.08 seconds
Started Jul 22 05:41:46 PM PDT 24
Finished Jul 22 05:41:48 PM PDT 24
Peak memory 218840 kb
Host smart-3ebdbc8d-0dd5-47d9-bc70-7fecf42e7590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258546503 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1258546503
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.2910059436
Short name T485
Test name
Test status
Simulation time 35931199 ps
CPU time 1.32 seconds
Started Jul 22 05:41:44 PM PDT 24
Finished Jul 22 05:41:46 PM PDT 24
Peak memory 217692 kb
Host smart-eba046ff-b8a5-472e-aa24-afdba2947dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910059436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2910059436
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.2177421782
Short name T372
Test name
Test status
Simulation time 29020909 ps
CPU time 1.03 seconds
Started Jul 22 05:41:45 PM PDT 24
Finished Jul 22 05:41:46 PM PDT 24
Peak memory 215808 kb
Host smart-51e9deee-2182-4ab0-b01f-fc70313419f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177421782 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.2177421782
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.993939933
Short name T882
Test name
Test status
Simulation time 26047365 ps
CPU time 0.98 seconds
Started Jul 22 05:41:47 PM PDT 24
Finished Jul 22 05:41:48 PM PDT 24
Peak memory 207428 kb
Host smart-144e81a2-7635-4f7b-81b9-6eb2a4a80138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993939933 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.993939933
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.1548318384
Short name T17
Test name
Test status
Simulation time 439811434 ps
CPU time 6.9 seconds
Started Jul 22 05:41:42 PM PDT 24
Finished Jul 22 05:41:50 PM PDT 24
Peak memory 236404 kb
Host smart-c7e18e16-aef8-43d4-9dcc-737ad8471f45
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548318384 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1548318384
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.4294681635
Short name T864
Test name
Test status
Simulation time 49395777 ps
CPU time 0.85 seconds
Started Jul 22 05:41:44 PM PDT 24
Finished Jul 22 05:41:45 PM PDT 24
Peak memory 215436 kb
Host smart-f8b62b5e-03cd-41dc-a3cb-699d6ddf48ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294681635 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.4294681635
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.3352316493
Short name T429
Test name
Test status
Simulation time 625447063 ps
CPU time 3.69 seconds
Started Jul 22 05:41:45 PM PDT 24
Finished Jul 22 05:41:49 PM PDT 24
Peak memory 217420 kb
Host smart-b5bec007-23ad-4849-af4c-15828633f462
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352316493 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.3352316493
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.3807514262
Short name T776
Test name
Test status
Simulation time 22955332249 ps
CPU time 494.37 seconds
Started Jul 22 05:44:47 PM PDT 24
Finished Jul 22 05:53:02 PM PDT 24
Peak memory 224108 kb
Host smart-923298e2-ff7e-4512-8a4c-a13e7bccf4f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807514262 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.3807514262
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.356321013
Short name T81
Test name
Test status
Simulation time 34089862 ps
CPU time 1.41 seconds
Started Jul 22 05:41:47 PM PDT 24
Finished Jul 22 05:41:49 PM PDT 24
Peak memory 216044 kb
Host smart-35d65a22-c871-4d3c-9217-36e20f78b45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356321013 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.356321013
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.595687332
Short name T407
Test name
Test status
Simulation time 12863691 ps
CPU time 0.88 seconds
Started Jul 22 05:41:45 PM PDT 24
Finished Jul 22 05:41:47 PM PDT 24
Peak memory 207296 kb
Host smart-660ade44-1625-41ad-91c4-e916475de951
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595687332 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.595687332
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.1141438534
Short name T872
Test name
Test status
Simulation time 178869836 ps
CPU time 0.95 seconds
Started Jul 22 05:41:43 PM PDT 24
Finished Jul 22 05:41:45 PM PDT 24
Peak memory 216564 kb
Host smart-a45e001e-2a1e-4c49-975e-57e029accce9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141438534 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.1141438534
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2431681983
Short name T822
Test name
Test status
Simulation time 144358732 ps
CPU time 1.26 seconds
Started Jul 22 05:41:42 PM PDT 24
Finished Jul 22 05:41:44 PM PDT 24
Peak memory 217056 kb
Host smart-c30f6768-19b1-457d-ad1d-3ff6618790f3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431681983 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2431681983
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.2552227998
Short name T65
Test name
Test status
Simulation time 20112670 ps
CPU time 1.08 seconds
Started Jul 22 05:41:44 PM PDT 24
Finished Jul 22 05:41:46 PM PDT 24
Peak memory 219956 kb
Host smart-b965cce9-a7c4-4b75-ba11-a1113c8bff79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552227998 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.2552227998
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.3931805213
Short name T990
Test name
Test status
Simulation time 83101687 ps
CPU time 1.38 seconds
Started Jul 22 05:41:42 PM PDT 24
Finished Jul 22 05:41:44 PM PDT 24
Peak memory 219112 kb
Host smart-db58d867-34e5-4897-8e34-3576fdfdc959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931805213 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.3931805213
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.838875843
Short name T860
Test name
Test status
Simulation time 19899420 ps
CPU time 1.1 seconds
Started Jul 22 05:41:42 PM PDT 24
Finished Jul 22 05:41:44 PM PDT 24
Peak memory 216140 kb
Host smart-0f444be3-f601-4c03-8918-2f32153ae8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838875843 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.838875843
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_sec_cm.14886323
Short name T18
Test name
Test status
Simulation time 858523179 ps
CPU time 7.35 seconds
Started Jul 22 05:41:43 PM PDT 24
Finished Jul 22 05:41:51 PM PDT 24
Peak memory 236340 kb
Host smart-3f87cbcb-fb31-4ab4-8366-1ca51c1e5481
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14886323 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.14886323
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.3108301009
Short name T362
Test name
Test status
Simulation time 18580194 ps
CPU time 1.01 seconds
Started Jul 22 05:41:47 PM PDT 24
Finished Jul 22 05:41:49 PM PDT 24
Peak memory 215612 kb
Host smart-87322f13-85e4-4b0f-9b1a-9a0e59cf4785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108301009 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.3108301009
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.1949063217
Short name T833
Test name
Test status
Simulation time 17691481574 ps
CPU time 398.06 seconds
Started Jul 22 05:41:43 PM PDT 24
Finished Jul 22 05:48:22 PM PDT 24
Peak memory 218392 kb
Host smart-37c3f2e5-458b-494b-9d7d-d33e5fb65f2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949063217 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.1949063217
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.3443623158
Short name T151
Test name
Test status
Simulation time 176696709 ps
CPU time 1.36 seconds
Started Jul 22 05:42:04 PM PDT 24
Finished Jul 22 05:42:06 PM PDT 24
Peak memory 218904 kb
Host smart-5b94f0d1-1bf0-4b06-b528-34de40737ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443623158 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.3443623158
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.213073727
Short name T637
Test name
Test status
Simulation time 16450124 ps
CPU time 0.95 seconds
Started Jul 22 05:42:04 PM PDT 24
Finished Jul 22 05:42:05 PM PDT 24
Peak memory 206632 kb
Host smart-2661107d-46ba-4e43-b8d7-3d1e7fffa692
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213073727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.213073727
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.1960211942
Short name T296
Test name
Test status
Simulation time 60138933 ps
CPU time 1.12 seconds
Started Jul 22 05:42:03 PM PDT 24
Finished Jul 22 05:42:05 PM PDT 24
Peak memory 218720 kb
Host smart-64455d8e-db35-4f90-b696-4028a29b511e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960211942 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.1960211942
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.3525511748
Short name T64
Test name
Test status
Simulation time 22360164 ps
CPU time 0.94 seconds
Started Jul 22 05:42:04 PM PDT 24
Finished Jul 22 05:42:06 PM PDT 24
Peak memory 219928 kb
Host smart-c424ad07-9574-4bf6-b9a6-ebb6b7053eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525511748 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.3525511748
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_intr.1877324736
Short name T371
Test name
Test status
Simulation time 22452611 ps
CPU time 1.17 seconds
Started Jul 22 05:42:02 PM PDT 24
Finished Jul 22 05:42:04 PM PDT 24
Peak memory 215744 kb
Host smart-441625b6-6028-40a8-a174-36bad5d65072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877324736 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1877324736
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.3502786476
Short name T511
Test name
Test status
Simulation time 17720508 ps
CPU time 0.97 seconds
Started Jul 22 05:42:03 PM PDT 24
Finished Jul 22 05:42:05 PM PDT 24
Peak memory 215632 kb
Host smart-1b981755-377d-49a2-a17e-8ff93b26db33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502786476 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.3502786476
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.4064106405
Short name T352
Test name
Test status
Simulation time 224697498 ps
CPU time 4.61 seconds
Started Jul 22 05:42:03 PM PDT 24
Finished Jul 22 05:42:08 PM PDT 24
Peak memory 217484 kb
Host smart-adb809bb-44cb-44f4-91ea-26328a766b21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064106405 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.4064106405
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/100.edn_alert.2157252066
Short name T779
Test name
Test status
Simulation time 371601790 ps
CPU time 1.46 seconds
Started Jul 22 05:43:56 PM PDT 24
Finished Jul 22 05:43:58 PM PDT 24
Peak memory 221044 kb
Host smart-9ab2f53e-b4ef-495f-a060-742352c9480a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157252066 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.2157252066
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.4285767556
Short name T505
Test name
Test status
Simulation time 54213523 ps
CPU time 1.44 seconds
Started Jul 22 05:43:56 PM PDT 24
Finished Jul 22 05:43:58 PM PDT 24
Peak memory 219256 kb
Host smart-23cdab8c-8b6b-4510-98cb-e960e7a16d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285767556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.4285767556
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.479169949
Short name T804
Test name
Test status
Simulation time 44742256 ps
CPU time 1.19 seconds
Started Jul 22 05:43:54 PM PDT 24
Finished Jul 22 05:43:56 PM PDT 24
Peak memory 219492 kb
Host smart-624762d6-67f0-49d3-bfaf-ecd0cf5766be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479169949 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.479169949
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.2237035078
Short name T549
Test name
Test status
Simulation time 33609599 ps
CPU time 1.52 seconds
Started Jul 22 05:43:57 PM PDT 24
Finished Jul 22 05:43:59 PM PDT 24
Peak memory 217568 kb
Host smart-48c21c27-c43f-4571-9148-2ac2ce7d4913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237035078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.2237035078
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.2068969398
Short name T435
Test name
Test status
Simulation time 68653983 ps
CPU time 1.18 seconds
Started Jul 22 05:43:59 PM PDT 24
Finished Jul 22 05:44:01 PM PDT 24
Peak memory 217632 kb
Host smart-e9e1e079-3962-4b5e-9b7e-1c9d357a609e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068969398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.2068969398
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.2068903218
Short name T597
Test name
Test status
Simulation time 35993400 ps
CPU time 1.25 seconds
Started Jul 22 05:43:59 PM PDT 24
Finished Jul 22 05:44:01 PM PDT 24
Peak memory 218872 kb
Host smart-2c9c27c4-22f0-4e11-8167-770da7b977d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068903218 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.2068903218
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.1928188645
Short name T731
Test name
Test status
Simulation time 34702470 ps
CPU time 1.44 seconds
Started Jul 22 05:43:57 PM PDT 24
Finished Jul 22 05:44:00 PM PDT 24
Peak memory 217764 kb
Host smart-596a9c1e-2176-437e-b048-448cb88af24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928188645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.1928188645
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.841738546
Short name T934
Test name
Test status
Simulation time 60196634 ps
CPU time 1.13 seconds
Started Jul 22 05:43:57 PM PDT 24
Finished Jul 22 05:44:00 PM PDT 24
Peak memory 219872 kb
Host smart-76590050-66d8-4cf5-9b2b-e1be1f3f12ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841738546 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.841738546
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.1734703218
Short name T739
Test name
Test status
Simulation time 109332720 ps
CPU time 1.62 seconds
Started Jul 22 05:43:53 PM PDT 24
Finished Jul 22 05:43:56 PM PDT 24
Peak memory 219096 kb
Host smart-1bb356ec-68cb-48ef-a76e-72aafea8869b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734703218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1734703218
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.2141662942
Short name T162
Test name
Test status
Simulation time 92581131 ps
CPU time 1.24 seconds
Started Jul 22 05:43:51 PM PDT 24
Finished Jul 22 05:43:53 PM PDT 24
Peak memory 216080 kb
Host smart-f6a77b5c-d2ba-4879-b551-3951e8006b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141662942 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.2141662942
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.3738759964
Short name T376
Test name
Test status
Simulation time 28661750 ps
CPU time 1.38 seconds
Started Jul 22 05:45:02 PM PDT 24
Finished Jul 22 05:45:05 PM PDT 24
Peak memory 218884 kb
Host smart-bdd035fd-8a7b-4bfe-8607-529eece47f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738759964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.3738759964
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.934263564
Short name T803
Test name
Test status
Simulation time 220625547 ps
CPU time 1.48 seconds
Started Jul 22 05:43:59 PM PDT 24
Finished Jul 22 05:44:01 PM PDT 24
Peak memory 220168 kb
Host smart-05bec7e7-e022-4c4c-83e2-fc748a21fa1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934263564 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.934263564
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.1725788880
Short name T48
Test name
Test status
Simulation time 86830071 ps
CPU time 3.02 seconds
Started Jul 22 05:43:55 PM PDT 24
Finished Jul 22 05:43:59 PM PDT 24
Peak memory 218940 kb
Host smart-967fe16c-505b-4863-abdb-37e24bdfe50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725788880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.1725788880
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.1655557497
Short name T753
Test name
Test status
Simulation time 27166083 ps
CPU time 1.25 seconds
Started Jul 22 05:43:57 PM PDT 24
Finished Jul 22 05:44:00 PM PDT 24
Peak memory 220928 kb
Host smart-876b8973-1057-42d9-be17-db2ce84c9721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655557497 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.1655557497
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.3334320506
Short name T850
Test name
Test status
Simulation time 45994322 ps
CPU time 1.57 seconds
Started Jul 22 05:43:58 PM PDT 24
Finished Jul 22 05:44:01 PM PDT 24
Peak memory 218704 kb
Host smart-8de41577-3f8d-4a4d-be5a-b7cb146b0a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334320506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.3334320506
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.3240603109
Short name T1
Test name
Test status
Simulation time 68340113 ps
CPU time 1.09 seconds
Started Jul 22 05:43:58 PM PDT 24
Finished Jul 22 05:44:00 PM PDT 24
Peak memory 216008 kb
Host smart-830b7668-7dd0-4d2d-9746-721f360c52fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240603109 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.3240603109
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.3746898846
Short name T988
Test name
Test status
Simulation time 38270296 ps
CPU time 1.43 seconds
Started Jul 22 05:43:57 PM PDT 24
Finished Jul 22 05:44:00 PM PDT 24
Peak memory 218740 kb
Host smart-92108303-4d81-4f08-9b3e-d2258fc3da3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746898846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3746898846
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.613343179
Short name T94
Test name
Test status
Simulation time 58972735 ps
CPU time 1.19 seconds
Started Jul 22 05:42:12 PM PDT 24
Finished Jul 22 05:42:14 PM PDT 24
Peak memory 219032 kb
Host smart-e4a722b9-1e3e-4360-9e39-1cde3eeb7f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613343179 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.613343179
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.2573431396
Short name T235
Test name
Test status
Simulation time 36330213 ps
CPU time 1.05 seconds
Started Jul 22 05:42:04 PM PDT 24
Finished Jul 22 05:42:05 PM PDT 24
Peak memory 206700 kb
Host smart-f37300fd-23e8-4ad9-90b8-710b03385230
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573431396 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.2573431396
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.1002817471
Short name T442
Test name
Test status
Simulation time 31543745 ps
CPU time 1.2 seconds
Started Jul 22 05:42:12 PM PDT 24
Finished Jul 22 05:42:14 PM PDT 24
Peak memory 218744 kb
Host smart-62435505-cb24-4733-af55-e300424ac9c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002817471 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.1002817471
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.163733940
Short name T16
Test name
Test status
Simulation time 23869823 ps
CPU time 0.94 seconds
Started Jul 22 05:42:03 PM PDT 24
Finished Jul 22 05:42:04 PM PDT 24
Peak memory 224104 kb
Host smart-f5b2802f-b121-43c2-bd37-ebfd9999271b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163733940 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.163733940
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_intr.3773610722
Short name T394
Test name
Test status
Simulation time 35713647 ps
CPU time 1 seconds
Started Jul 22 05:42:12 PM PDT 24
Finished Jul 22 05:42:14 PM PDT 24
Peak memory 224124 kb
Host smart-a118e2c3-6a06-4f21-8cae-5fcb0aa249f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773610722 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.3773610722
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.3464617932
Short name T380
Test name
Test status
Simulation time 120725442 ps
CPU time 0.91 seconds
Started Jul 22 05:42:02 PM PDT 24
Finished Jul 22 05:42:04 PM PDT 24
Peak memory 215668 kb
Host smart-68a27e80-6e03-41b7-8428-9a232552937b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464617932 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.3464617932
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.3999666955
Short name T201
Test name
Test status
Simulation time 932246458 ps
CPU time 3.91 seconds
Started Jul 22 05:42:03 PM PDT 24
Finished Jul 22 05:42:08 PM PDT 24
Peak memory 220232 kb
Host smart-bd703a1b-2291-43d1-b1a9-3c108ecf4c8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999666955 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.3999666955
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.4183471957
Short name T650
Test name
Test status
Simulation time 49918745948 ps
CPU time 284.38 seconds
Started Jul 22 05:42:01 PM PDT 24
Finished Jul 22 05:46:46 PM PDT 24
Peak memory 219420 kb
Host smart-af6e9b95-870e-4a30-8fd0-b5d14df7e3e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183471957 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.4183471957
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.2967420950
Short name T790
Test name
Test status
Simulation time 28557543 ps
CPU time 1.18 seconds
Started Jul 22 05:44:00 PM PDT 24
Finished Jul 22 05:44:02 PM PDT 24
Peak memory 219908 kb
Host smart-083d067f-5949-4d8d-b98e-c26eafe2bb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967420950 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.2967420950
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.2216125626
Short name T62
Test name
Test status
Simulation time 45098757 ps
CPU time 1.39 seconds
Started Jul 22 05:43:59 PM PDT 24
Finished Jul 22 05:44:01 PM PDT 24
Peak memory 218988 kb
Host smart-cea53b91-68a0-4cb1-8129-6f30f57250d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216125626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2216125626
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.3953387191
Short name T593
Test name
Test status
Simulation time 61501642 ps
CPU time 1.11 seconds
Started Jul 22 05:43:57 PM PDT 24
Finished Jul 22 05:44:00 PM PDT 24
Peak memory 220152 kb
Host smart-e9eb0ecc-fb37-4091-a6b7-6032d40540f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953387191 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.3953387191
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.813748304
Short name T987
Test name
Test status
Simulation time 133525181 ps
CPU time 1.21 seconds
Started Jul 22 05:43:57 PM PDT 24
Finished Jul 22 05:43:59 PM PDT 24
Peak memory 220400 kb
Host smart-254e4a2a-6fc5-47c4-ae3b-c6973a948ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813748304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.813748304
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.772831710
Short name T397
Test name
Test status
Simulation time 54079760 ps
CPU time 1.23 seconds
Started Jul 22 05:44:00 PM PDT 24
Finished Jul 22 05:44:02 PM PDT 24
Peak memory 218900 kb
Host smart-c14a0b75-6d1e-4326-857c-dc8123f49c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772831710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.772831710
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.2213607604
Short name T423
Test name
Test status
Simulation time 49578367 ps
CPU time 1.21 seconds
Started Jul 22 05:44:04 PM PDT 24
Finished Jul 22 05:44:07 PM PDT 24
Peak memory 219588 kb
Host smart-d5aa5ed5-bbc8-44b6-9f65-b45c3a2a6e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213607604 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.2213607604
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.1937741047
Short name T979
Test name
Test status
Simulation time 89073256 ps
CPU time 1.21 seconds
Started Jul 22 05:43:51 PM PDT 24
Finished Jul 22 05:43:54 PM PDT 24
Peak memory 217848 kb
Host smart-fe77df32-9e4c-4e39-993a-06bc8358920e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937741047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.1937741047
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.1425206055
Short name T386
Test name
Test status
Simulation time 28198752 ps
CPU time 1.23 seconds
Started Jul 22 05:44:06 PM PDT 24
Finished Jul 22 05:44:08 PM PDT 24
Peak memory 215984 kb
Host smart-88d43950-47fc-4ea8-81cd-9729b15fd342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425206055 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.1425206055
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.227973930
Short name T902
Test name
Test status
Simulation time 39490035 ps
CPU time 1.41 seconds
Started Jul 22 05:44:05 PM PDT 24
Finished Jul 22 05:44:07 PM PDT 24
Peak memory 219980 kb
Host smart-e949afb6-4b9b-4625-9a57-7130bb09ed22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227973930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.227973930
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.410732242
Short name T825
Test name
Test status
Simulation time 24092430 ps
CPU time 1.22 seconds
Started Jul 22 05:44:04 PM PDT 24
Finished Jul 22 05:44:06 PM PDT 24
Peak memory 221092 kb
Host smart-c9e54c86-f2dc-45b3-bc4d-71cae2bd1d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410732242 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.410732242
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.3754401274
Short name T85
Test name
Test status
Simulation time 80417167 ps
CPU time 2.63 seconds
Started Jul 22 05:44:07 PM PDT 24
Finished Jul 22 05:44:10 PM PDT 24
Peak memory 220720 kb
Host smart-23e5de34-1ca6-4a6a-be6e-7b7d8f74d57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754401274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.3754401274
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.507333419
Short name T300
Test name
Test status
Simulation time 50023272 ps
CPU time 1.25 seconds
Started Jul 22 05:44:06 PM PDT 24
Finished Jul 22 05:44:08 PM PDT 24
Peak memory 221188 kb
Host smart-6e473d3a-f4b9-4621-9d79-691ac3e3351b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507333419 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.507333419
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.122424506
Short name T349
Test name
Test status
Simulation time 78574497 ps
CPU time 0.99 seconds
Started Jul 22 05:44:03 PM PDT 24
Finished Jul 22 05:44:05 PM PDT 24
Peak memory 217652 kb
Host smart-ea1d3b9a-fe83-492c-b726-3410800426ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122424506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.122424506
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.1497858425
Short name T273
Test name
Test status
Simulation time 60700599 ps
CPU time 1.3 seconds
Started Jul 22 05:45:35 PM PDT 24
Finished Jul 22 05:45:38 PM PDT 24
Peak memory 219804 kb
Host smart-f047a6ad-0cc4-4dff-8612-3972e8a6f01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497858425 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.1497858425
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.63673867
Short name T967
Test name
Test status
Simulation time 127170924 ps
CPU time 2.11 seconds
Started Jul 22 05:44:04 PM PDT 24
Finished Jul 22 05:44:08 PM PDT 24
Peak memory 220328 kb
Host smart-4804db96-716d-4472-b39f-19e186b7509b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63673867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.63673867
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.2712585803
Short name T49
Test name
Test status
Simulation time 77727905 ps
CPU time 1.09 seconds
Started Jul 22 05:44:16 PM PDT 24
Finished Jul 22 05:44:18 PM PDT 24
Peak memory 218992 kb
Host smart-778e2c43-53df-4704-9f89-03bd6463ab41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712585803 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.2712585803
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.3747977900
Short name T839
Test name
Test status
Simulation time 40046269 ps
CPU time 1.39 seconds
Started Jul 22 05:44:03 PM PDT 24
Finished Jul 22 05:44:05 PM PDT 24
Peak memory 217624 kb
Host smart-f1637a20-27eb-4651-b1be-e738c2df6dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747977900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3747977900
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.3652923905
Short name T695
Test name
Test status
Simulation time 32987873 ps
CPU time 1.22 seconds
Started Jul 22 05:44:04 PM PDT 24
Finished Jul 22 05:44:07 PM PDT 24
Peak memory 218848 kb
Host smart-d30547ae-1b75-4de1-891d-300801065166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652923905 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.3652923905
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.3341430126
Short name T472
Test name
Test status
Simulation time 91648051 ps
CPU time 1.13 seconds
Started Jul 22 05:44:00 PM PDT 24
Finished Jul 22 05:44:02 PM PDT 24
Peak memory 217528 kb
Host smart-5178ec21-130b-4fdd-a451-114fb72647de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341430126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3341430126
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.3984476742
Short name T927
Test name
Test status
Simulation time 40742769 ps
CPU time 1.21 seconds
Started Jul 22 05:42:11 PM PDT 24
Finished Jul 22 05:42:14 PM PDT 24
Peak memory 219112 kb
Host smart-9a02d96d-beae-466c-93e9-2d815cf46eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984476742 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.3984476742
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.4085276575
Short name T521
Test name
Test status
Simulation time 115997456 ps
CPU time 0.89 seconds
Started Jul 22 05:42:10 PM PDT 24
Finished Jul 22 05:42:12 PM PDT 24
Peak memory 206904 kb
Host smart-ad073e5e-9ce9-4a86-818e-37944954ed15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085276575 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.4085276575
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3165000735
Short name T519
Test name
Test status
Simulation time 38373899 ps
CPU time 1.02 seconds
Started Jul 22 05:42:12 PM PDT 24
Finished Jul 22 05:42:15 PM PDT 24
Peak memory 218672 kb
Host smart-d2441421-5cd5-4d81-98f4-eaeb163c772d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165000735 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3165000735
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.1327778694
Short name T893
Test name
Test status
Simulation time 22475080 ps
CPU time 0.91 seconds
Started Jul 22 05:42:11 PM PDT 24
Finished Jul 22 05:42:14 PM PDT 24
Peak memory 219052 kb
Host smart-eb483417-b237-48d3-a2ad-f9fbb81539bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327778694 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.1327778694
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.3362400570
Short name T661
Test name
Test status
Simulation time 90392786 ps
CPU time 1.33 seconds
Started Jul 22 05:42:02 PM PDT 24
Finished Jul 22 05:42:04 PM PDT 24
Peak memory 219188 kb
Host smart-53ae6489-20e9-4bca-b7a8-04d2a4140709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362400570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.3362400570
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.2050408312
Short name T763
Test name
Test status
Simulation time 29458218 ps
CPU time 1.07 seconds
Started Jul 22 05:45:09 PM PDT 24
Finished Jul 22 05:45:11 PM PDT 24
Peak memory 215716 kb
Host smart-2a3dfc19-75ae-44cd-b19b-8d90834a335e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050408312 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.2050408312
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.418590213
Short name T611
Test name
Test status
Simulation time 24240993 ps
CPU time 0.96 seconds
Started Jul 22 05:42:07 PM PDT 24
Finished Jul 22 05:42:09 PM PDT 24
Peak memory 215628 kb
Host smart-a52bd464-5d2e-4f3d-8e69-9da456c473c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418590213 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.418590213
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.628976681
Short name T658
Test name
Test status
Simulation time 193571467 ps
CPU time 1.05 seconds
Started Jul 22 05:42:02 PM PDT 24
Finished Jul 22 05:42:03 PM PDT 24
Peak memory 207244 kb
Host smart-68ee5d9d-4915-4852-9965-28974ea9fcbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628976681 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.628976681
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.2684010145
Short name T229
Test name
Test status
Simulation time 154874589679 ps
CPU time 421.24 seconds
Started Jul 22 05:42:10 PM PDT 24
Finished Jul 22 05:49:13 PM PDT 24
Peak memory 224192 kb
Host smart-8ea0e6bc-c1ae-48f1-aae7-722078ff5365
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684010145 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.2684010145
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.3004413162
Short name T819
Test name
Test status
Simulation time 92782039 ps
CPU time 1.35 seconds
Started Jul 22 05:44:04 PM PDT 24
Finished Jul 22 05:44:07 PM PDT 24
Peak memory 219456 kb
Host smart-572997d7-4bf1-4c4b-95aa-1a4e81176c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004413162 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.3004413162
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.3482363131
Short name T639
Test name
Test status
Simulation time 37397379 ps
CPU time 1.45 seconds
Started Jul 22 05:47:17 PM PDT 24
Finished Jul 22 05:47:19 PM PDT 24
Peak memory 218732 kb
Host smart-6a56a3a9-89da-40d5-8407-7ab6ae89c246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482363131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3482363131
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.1987392129
Short name T364
Test name
Test status
Simulation time 90895639 ps
CPU time 1.22 seconds
Started Jul 22 05:45:35 PM PDT 24
Finished Jul 22 05:45:38 PM PDT 24
Peak memory 220548 kb
Host smart-e2ce7570-712d-4be3-b1df-f25463dd6a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987392129 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.1987392129
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.2566619966
Short name T547
Test name
Test status
Simulation time 71852702 ps
CPU time 2.43 seconds
Started Jul 22 05:44:06 PM PDT 24
Finished Jul 22 05:44:09 PM PDT 24
Peak memory 219968 kb
Host smart-33b1b91a-1b1b-414f-8e39-4d837eb423c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566619966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.2566619966
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.3650140110
Short name T795
Test name
Test status
Simulation time 96055354 ps
CPU time 1.27 seconds
Started Jul 22 05:44:03 PM PDT 24
Finished Jul 22 05:44:05 PM PDT 24
Peak memory 220120 kb
Host smart-f7e468cb-3bf6-4dac-9f51-a707fd8fb38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650140110 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.3650140110
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.3144630999
Short name T963
Test name
Test status
Simulation time 34812202 ps
CPU time 1.41 seconds
Started Jul 22 05:44:06 PM PDT 24
Finished Jul 22 05:44:08 PM PDT 24
Peak memory 219864 kb
Host smart-760fde38-ef9c-4d54-8c25-1746cb3bda2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144630999 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.3144630999
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.4026915
Short name T894
Test name
Test status
Simulation time 28010915 ps
CPU time 1.34 seconds
Started Jul 22 05:44:04 PM PDT 24
Finished Jul 22 05:44:06 PM PDT 24
Peak memory 219716 kb
Host smart-4bbf255c-05ea-476a-9b98-8654a38824f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026915 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.4026915
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.187313220
Short name T488
Test name
Test status
Simulation time 48491216 ps
CPU time 1.55 seconds
Started Jul 22 05:47:17 PM PDT 24
Finished Jul 22 05:47:19 PM PDT 24
Peak memory 217732 kb
Host smart-bc9f0727-07d5-4bc9-a67f-d13b9a173aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187313220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.187313220
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.3663802892
Short name T946
Test name
Test status
Simulation time 27811500 ps
CPU time 1.21 seconds
Started Jul 22 05:44:03 PM PDT 24
Finished Jul 22 05:44:05 PM PDT 24
Peak memory 220292 kb
Host smart-c0b42752-a6dc-49f9-b6bf-564ad3a8d866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663802892 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.3663802892
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.1029819514
Short name T541
Test name
Test status
Simulation time 42968359 ps
CPU time 1.58 seconds
Started Jul 22 05:45:35 PM PDT 24
Finished Jul 22 05:45:38 PM PDT 24
Peak memory 217768 kb
Host smart-0db4ba8c-b7e3-4ff0-b428-91512b18778b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029819514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1029819514
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.2127085952
Short name T245
Test name
Test status
Simulation time 109848163 ps
CPU time 1.33 seconds
Started Jul 22 05:44:03 PM PDT 24
Finished Jul 22 05:44:05 PM PDT 24
Peak memory 216052 kb
Host smart-752bad18-ef4f-4250-a424-0c8201f2b2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127085952 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.2127085952
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/126.edn_alert.3861789657
Short name T884
Test name
Test status
Simulation time 43753368 ps
CPU time 1.23 seconds
Started Jul 22 05:44:02 PM PDT 24
Finished Jul 22 05:44:04 PM PDT 24
Peak memory 218824 kb
Host smart-692ed53d-093c-463a-ac3c-89c66ff26dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861789657 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.3861789657
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.3193876533
Short name T676
Test name
Test status
Simulation time 67823612 ps
CPU time 1.23 seconds
Started Jul 22 05:44:04 PM PDT 24
Finished Jul 22 05:44:06 PM PDT 24
Peak memory 217860 kb
Host smart-c948095d-a328-4005-b704-0ff8bd4d6b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193876533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.3193876533
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.1750418582
Short name T274
Test name
Test status
Simulation time 106628391 ps
CPU time 1.33 seconds
Started Jul 22 05:44:04 PM PDT 24
Finished Jul 22 05:44:07 PM PDT 24
Peak memory 216088 kb
Host smart-75189cf4-c671-4480-9e64-ad256c757b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750418582 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.1750418582
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.468986678
Short name T771
Test name
Test status
Simulation time 68907892 ps
CPU time 1.26 seconds
Started Jul 22 05:44:02 PM PDT 24
Finished Jul 22 05:44:04 PM PDT 24
Peak memory 218924 kb
Host smart-9ad564a3-95eb-41c5-84ba-329b35947981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468986678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.468986678
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.2415997619
Short name T39
Test name
Test status
Simulation time 44180731 ps
CPU time 1.21 seconds
Started Jul 22 05:44:07 PM PDT 24
Finished Jul 22 05:44:08 PM PDT 24
Peak memory 216164 kb
Host smart-c5b7c9f8-121d-400a-aacb-332ff6e539db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415997619 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.2415997619
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.255490640
Short name T983
Test name
Test status
Simulation time 90472406 ps
CPU time 1.24 seconds
Started Jul 22 05:44:06 PM PDT 24
Finished Jul 22 05:44:07 PM PDT 24
Peak memory 220088 kb
Host smart-22f41ea3-f25b-4a3c-b532-20071b365018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255490640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.255490640
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.4118191306
Short name T871
Test name
Test status
Simulation time 118970329 ps
CPU time 1.18 seconds
Started Jul 22 05:42:09 PM PDT 24
Finished Jul 22 05:42:11 PM PDT 24
Peak memory 218876 kb
Host smart-b8dd34db-d5c2-40cd-907f-38087cf05665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118191306 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.4118191306
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.3236815521
Short name T662
Test name
Test status
Simulation time 24395426 ps
CPU time 1.03 seconds
Started Jul 22 05:42:12 PM PDT 24
Finished Jul 22 05:42:14 PM PDT 24
Peak memory 207028 kb
Host smart-9a2a1fb5-8526-4d65-9bec-38a73536f481
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236815521 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3236815521
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.1981814907
Short name T854
Test name
Test status
Simulation time 40378870 ps
CPU time 0.83 seconds
Started Jul 22 05:42:12 PM PDT 24
Finished Jul 22 05:42:15 PM PDT 24
Peak memory 216712 kb
Host smart-c6f20106-abe2-4881-90d5-c9fba34d2f95
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981814907 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1981814907
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.1232163603
Short name T207
Test name
Test status
Simulation time 52756383 ps
CPU time 1.12 seconds
Started Jul 22 05:42:10 PM PDT 24
Finished Jul 22 05:42:12 PM PDT 24
Peak memory 217340 kb
Host smart-8a7644ad-1d3d-423f-8acf-94d8254d28a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232163603 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.1232163603
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.1346631424
Short name T114
Test name
Test status
Simulation time 21452082 ps
CPU time 1.29 seconds
Started Jul 22 05:42:13 PM PDT 24
Finished Jul 22 05:42:16 PM PDT 24
Peak memory 229928 kb
Host smart-9d6cfa16-85b8-46e6-9ecb-8e9c5042b990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346631424 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.1346631424
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.292277441
Short name T525
Test name
Test status
Simulation time 35334796 ps
CPU time 1.37 seconds
Started Jul 22 05:42:12 PM PDT 24
Finished Jul 22 05:42:15 PM PDT 24
Peak memory 217640 kb
Host smart-24a642c1-c133-4226-916a-e8162f615b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292277441 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.292277441
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.902012383
Short name T103
Test name
Test status
Simulation time 24738421 ps
CPU time 1.08 seconds
Started Jul 22 05:42:12 PM PDT 24
Finished Jul 22 05:42:14 PM PDT 24
Peak memory 216264 kb
Host smart-ba0266c0-4429-4f85-9aab-952083d6464c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902012383 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.902012383
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.397767795
Short name T681
Test name
Test status
Simulation time 47531329 ps
CPU time 0.98 seconds
Started Jul 22 05:42:12 PM PDT 24
Finished Jul 22 05:42:14 PM PDT 24
Peak memory 215600 kb
Host smart-c7a34a0c-a458-4121-b2a7-3b66d2080e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397767795 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.397767795
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.699521441
Short name T633
Test name
Test status
Simulation time 531164653 ps
CPU time 3.29 seconds
Started Jul 22 05:42:11 PM PDT 24
Finished Jul 22 05:42:15 PM PDT 24
Peak memory 217560 kb
Host smart-2d267c9f-9707-4c14-a61b-c393327fd26a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699521441 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.699521441
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.3704838988
Short name T457
Test name
Test status
Simulation time 213340708710 ps
CPU time 1132.91 seconds
Started Jul 22 05:42:11 PM PDT 24
Finished Jul 22 06:01:04 PM PDT 24
Peak memory 223216 kb
Host smart-eda0d1e6-ac0d-4484-a203-2e710717e1f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704838988 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.3704838988
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.2232958847
Short name T696
Test name
Test status
Simulation time 28272273 ps
CPU time 1.17 seconds
Started Jul 22 05:44:07 PM PDT 24
Finished Jul 22 05:44:09 PM PDT 24
Peak memory 219972 kb
Host smart-73d59b65-37bc-4b95-8466-9e83a36bb5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232958847 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.2232958847
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.2455944488
Short name T730
Test name
Test status
Simulation time 352138953 ps
CPU time 1.16 seconds
Started Jul 22 05:44:08 PM PDT 24
Finished Jul 22 05:44:09 PM PDT 24
Peak memory 217672 kb
Host smart-494f05bd-979a-492c-b5f1-6375f674bf35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455944488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2455944488
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.3989841848
Short name T276
Test name
Test status
Simulation time 60159473 ps
CPU time 1.03 seconds
Started Jul 22 05:44:04 PM PDT 24
Finished Jul 22 05:44:06 PM PDT 24
Peak memory 221112 kb
Host smart-826d8abc-0c7b-4e25-946f-cbb012a526d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989841848 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.3989841848
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.2251768457
Short name T97
Test name
Test status
Simulation time 35315182 ps
CPU time 1.23 seconds
Started Jul 22 05:44:02 PM PDT 24
Finished Jul 22 05:44:04 PM PDT 24
Peak memory 218072 kb
Host smart-197120b2-3d5c-4e9f-86b1-59392c256176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251768457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2251768457
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.2044546859
Short name T617
Test name
Test status
Simulation time 197287773 ps
CPU time 1.28 seconds
Started Jul 22 05:47:17 PM PDT 24
Finished Jul 22 05:47:19 PM PDT 24
Peak memory 218772 kb
Host smart-e120cb93-9500-4d3b-a194-d6de2894101d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044546859 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.2044546859
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.511977237
Short name T659
Test name
Test status
Simulation time 43705520 ps
CPU time 1.12 seconds
Started Jul 22 05:45:35 PM PDT 24
Finished Jul 22 05:45:37 PM PDT 24
Peak memory 217472 kb
Host smart-f13cb70c-b85d-484e-a552-6fe300b8170e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511977237 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.511977237
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.1731140419
Short name T722
Test name
Test status
Simulation time 27888000 ps
CPU time 1.2 seconds
Started Jul 22 05:44:13 PM PDT 24
Finished Jul 22 05:44:14 PM PDT 24
Peak memory 220104 kb
Host smart-4cb4c0e3-7a25-438f-8a7a-840acaffda46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731140419 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.1731140419
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.2212392569
Short name T482
Test name
Test status
Simulation time 62120558 ps
CPU time 1.32 seconds
Started Jul 22 05:44:13 PM PDT 24
Finished Jul 22 05:44:15 PM PDT 24
Peak memory 220300 kb
Host smart-aa584601-6f05-46c0-a316-2760c7dea30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212392569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.2212392569
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.1159882519
Short name T271
Test name
Test status
Simulation time 63758556 ps
CPU time 1.01 seconds
Started Jul 22 05:44:18 PM PDT 24
Finished Jul 22 05:44:20 PM PDT 24
Peak memory 221016 kb
Host smart-08d7872b-a817-41fa-ad09-6a6fb812c807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159882519 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.1159882519
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/135.edn_alert.241654887
Short name T994
Test name
Test status
Simulation time 31819296 ps
CPU time 1.33 seconds
Started Jul 22 05:44:14 PM PDT 24
Finished Jul 22 05:44:16 PM PDT 24
Peak memory 216024 kb
Host smart-90c2e7be-4b7f-4a27-83f0-8b12d58b5e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241654887 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.241654887
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.625305298
Short name T598
Test name
Test status
Simulation time 36606774 ps
CPU time 1.12 seconds
Started Jul 22 05:44:14 PM PDT 24
Finished Jul 22 05:44:16 PM PDT 24
Peak memory 220204 kb
Host smart-c29b69c5-8c2b-43ea-bbf2-8bcdfc3162c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625305298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.625305298
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.3456928405
Short name T477
Test name
Test status
Simulation time 64495859 ps
CPU time 1.29 seconds
Started Jul 22 05:44:15 PM PDT 24
Finished Jul 22 05:44:16 PM PDT 24
Peak memory 218748 kb
Host smart-d017cd2b-7934-4db2-85c5-71a065fbbb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456928405 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.3456928405
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.1319061896
Short name T948
Test name
Test status
Simulation time 34032209 ps
CPU time 1.29 seconds
Started Jul 22 05:44:17 PM PDT 24
Finished Jul 22 05:44:19 PM PDT 24
Peak memory 218728 kb
Host smart-8b6a31de-89a5-4434-aa0d-bef5a73d0337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319061896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.1319061896
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.384905998
Short name T969
Test name
Test status
Simulation time 94670914 ps
CPU time 1.35 seconds
Started Jul 22 05:45:35 PM PDT 24
Finished Jul 22 05:45:38 PM PDT 24
Peak memory 218904 kb
Host smart-98ad10e9-0b82-4260-96a9-6fb88a7a34d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384905998 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.384905998
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.2307554499
Short name T425
Test name
Test status
Simulation time 97849241 ps
CPU time 1.59 seconds
Started Jul 22 05:45:01 PM PDT 24
Finished Jul 22 05:45:03 PM PDT 24
Peak memory 217700 kb
Host smart-b89a5c99-884f-4f81-8c46-bb485a3bd23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307554499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.2307554499
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.1620317333
Short name T493
Test name
Test status
Simulation time 44334369 ps
CPU time 1.24 seconds
Started Jul 22 05:44:15 PM PDT 24
Finished Jul 22 05:44:18 PM PDT 24
Peak memory 221064 kb
Host smart-ce504147-411f-4b08-9937-08fe6014e3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620317333 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.1620317333
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.2071286394
Short name T897
Test name
Test status
Simulation time 46530315 ps
CPU time 1.53 seconds
Started Jul 22 05:45:01 PM PDT 24
Finished Jul 22 05:45:03 PM PDT 24
Peak memory 219068 kb
Host smart-d6235472-d4fd-4d50-808b-d99a6090b1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071286394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.2071286394
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.1541820337
Short name T67
Test name
Test status
Simulation time 76282756 ps
CPU time 1.15 seconds
Started Jul 22 05:44:15 PM PDT 24
Finished Jul 22 05:44:17 PM PDT 24
Peak memory 219736 kb
Host smart-a24b9ca3-473d-48cc-b436-0ce5e5877b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541820337 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.1541820337
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.2203501824
Short name T401
Test name
Test status
Simulation time 100521269 ps
CPU time 1.11 seconds
Started Jul 22 05:44:12 PM PDT 24
Finished Jul 22 05:44:14 PM PDT 24
Peak memory 219712 kb
Host smart-f59b2ef7-8ce5-4cc1-8098-7e2a39f4f91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203501824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.2203501824
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.2142290150
Short name T538
Test name
Test status
Simulation time 51637318 ps
CPU time 1.19 seconds
Started Jul 22 05:42:12 PM PDT 24
Finished Jul 22 05:42:14 PM PDT 24
Peak memory 220052 kb
Host smart-ffc2e598-2e66-4ae5-a283-c1f8faa246a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142290150 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.2142290150
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.1653416559
Short name T408
Test name
Test status
Simulation time 15043247 ps
CPU time 0.92 seconds
Started Jul 22 05:42:11 PM PDT 24
Finished Jul 22 05:42:13 PM PDT 24
Peak memory 207032 kb
Host smart-40447537-211a-407c-9123-2301b51585e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653416559 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1653416559
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.310185873
Short name T176
Test name
Test status
Simulation time 14002538 ps
CPU time 0.93 seconds
Started Jul 22 05:42:12 PM PDT 24
Finished Jul 22 05:42:14 PM PDT 24
Peak memory 216896 kb
Host smart-1528f90c-b031-425a-88ae-d1c098aba3cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310185873 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.310185873
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.805520589
Short name T834
Test name
Test status
Simulation time 92915392 ps
CPU time 1.17 seconds
Started Jul 22 05:42:12 PM PDT 24
Finished Jul 22 05:42:15 PM PDT 24
Peak memory 217328 kb
Host smart-214e501e-bcbd-432a-9a82-0e51153682f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805520589 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_di
sable_auto_req_mode.805520589
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_genbits.1445589674
Short name T338
Test name
Test status
Simulation time 80270587 ps
CPU time 1.09 seconds
Started Jul 22 05:42:12 PM PDT 24
Finished Jul 22 05:42:14 PM PDT 24
Peak memory 217600 kb
Host smart-fa64f948-62b8-4572-92c6-fc950f1aa539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445589674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.1445589674
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_smoke.940182488
Short name T682
Test name
Test status
Simulation time 34941246 ps
CPU time 0.9 seconds
Started Jul 22 05:42:13 PM PDT 24
Finished Jul 22 05:42:16 PM PDT 24
Peak memory 215536 kb
Host smart-9af24f42-580f-4e20-be85-944c0031e1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940182488 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.940182488
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.799533001
Short name T497
Test name
Test status
Simulation time 150771302 ps
CPU time 1.97 seconds
Started Jul 22 05:42:13 PM PDT 24
Finished Jul 22 05:42:17 PM PDT 24
Peak memory 207448 kb
Host smart-271f8ce0-0fbc-4511-b9f9-a65a2f05ccaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799533001 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.799533001
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/140.edn_alert.4126456969
Short name T675
Test name
Test status
Simulation time 41283368 ps
CPU time 1.23 seconds
Started Jul 22 05:44:16 PM PDT 24
Finished Jul 22 05:44:19 PM PDT 24
Peak memory 219156 kb
Host smart-353d1aaf-0fd2-437a-b74a-9774cee4bcc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126456969 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.4126456969
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.1194787079
Short name T570
Test name
Test status
Simulation time 81617433 ps
CPU time 1.9 seconds
Started Jul 22 05:44:15 PM PDT 24
Finished Jul 22 05:44:18 PM PDT 24
Peak memory 220224 kb
Host smart-1574571c-c936-439a-951c-faf286ff8f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194787079 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.1194787079
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.3409414512
Short name T840
Test name
Test status
Simulation time 47336719 ps
CPU time 1.1 seconds
Started Jul 22 05:44:16 PM PDT 24
Finished Jul 22 05:44:18 PM PDT 24
Peak memory 219992 kb
Host smart-df0a3ed6-2c08-492f-b825-374bd230ed09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409414512 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.3409414512
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.3793702408
Short name T954
Test name
Test status
Simulation time 32701289 ps
CPU time 1.31 seconds
Started Jul 22 05:44:15 PM PDT 24
Finished Jul 22 05:44:18 PM PDT 24
Peak memory 220236 kb
Host smart-969ef8b3-5343-4665-bd68-8e9188887753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793702408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3793702408
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.619552893
Short name T447
Test name
Test status
Simulation time 32576882 ps
CPU time 1.26 seconds
Started Jul 22 05:44:15 PM PDT 24
Finished Jul 22 05:44:17 PM PDT 24
Peak memory 217680 kb
Host smart-fdbb7d4a-cc54-46db-90fa-5b5f4b661520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619552893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.619552893
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.3633191807
Short name T952
Test name
Test status
Simulation time 47211684 ps
CPU time 1.17 seconds
Started Jul 22 05:44:16 PM PDT 24
Finished Jul 22 05:44:18 PM PDT 24
Peak memory 216040 kb
Host smart-e85a2424-95eb-431c-b76f-373c26953917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633191807 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.3633191807
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.1253637309
Short name T573
Test name
Test status
Simulation time 43854523 ps
CPU time 1.59 seconds
Started Jul 22 05:44:16 PM PDT 24
Finished Jul 22 05:44:19 PM PDT 24
Peak memory 220420 kb
Host smart-9d879947-86e0-4bc3-9f07-183af51e368c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253637309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.1253637309
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.3649596858
Short name T307
Test name
Test status
Simulation time 27057367 ps
CPU time 1.21 seconds
Started Jul 22 05:44:18 PM PDT 24
Finished Jul 22 05:44:20 PM PDT 24
Peak memory 215992 kb
Host smart-e2ea85f9-5220-4684-a7ef-cf804ff53cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649596858 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.3649596858
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.1414694653
Short name T612
Test name
Test status
Simulation time 76631659 ps
CPU time 1.44 seconds
Started Jul 22 05:44:16 PM PDT 24
Finished Jul 22 05:44:18 PM PDT 24
Peak memory 218728 kb
Host smart-274319b8-3517-460d-941c-ef39a0a38ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414694653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.1414694653
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.953695744
Short name T409
Test name
Test status
Simulation time 110366990 ps
CPU time 1.52 seconds
Started Jul 22 05:44:16 PM PDT 24
Finished Jul 22 05:44:19 PM PDT 24
Peak memory 218844 kb
Host smart-74ea7fde-bf45-49be-8f0c-9caa4068a9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953695744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.953695744
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.3992053663
Short name T654
Test name
Test status
Simulation time 67872307 ps
CPU time 1.09 seconds
Started Jul 22 05:44:16 PM PDT 24
Finished Jul 22 05:44:18 PM PDT 24
Peak memory 219464 kb
Host smart-32253f31-8101-428a-ac56-ded1a801625c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992053663 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.3992053663
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.1140917870
Short name T548
Test name
Test status
Simulation time 238347916 ps
CPU time 1.55 seconds
Started Jul 22 05:44:16 PM PDT 24
Finished Jul 22 05:44:18 PM PDT 24
Peak memory 219192 kb
Host smart-5afa54ef-bb14-4d76-bc79-9c99797ee41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140917870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1140917870
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.1854487026
Short name T835
Test name
Test status
Simulation time 327456448 ps
CPU time 1.39 seconds
Started Jul 22 05:44:19 PM PDT 24
Finished Jul 22 05:44:21 PM PDT 24
Peak memory 215996 kb
Host smart-035e7bfb-5298-4573-ba76-b590abadf0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854487026 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.1854487026
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.1029726987
Short name T418
Test name
Test status
Simulation time 41746836 ps
CPU time 1.47 seconds
Started Jul 22 05:44:17 PM PDT 24
Finished Jul 22 05:44:20 PM PDT 24
Peak memory 218988 kb
Host smart-09e8881b-6915-40db-8edf-d72c7e21a19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029726987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.1029726987
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.2766282503
Short name T975
Test name
Test status
Simulation time 85586065 ps
CPU time 1.14 seconds
Started Jul 22 05:44:14 PM PDT 24
Finished Jul 22 05:44:16 PM PDT 24
Peak memory 218696 kb
Host smart-c686547a-46a1-44ea-aa34-de3cc16cdd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766282503 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.2766282503
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.3913128280
Short name T480
Test name
Test status
Simulation time 108563485 ps
CPU time 1.14 seconds
Started Jul 22 05:44:17 PM PDT 24
Finished Jul 22 05:44:19 PM PDT 24
Peak memory 217424 kb
Host smart-a2b87a01-2fbe-473b-8ef6-5d7be57d01e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913128280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.3913128280
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.3389985612
Short name T384
Test name
Test status
Simulation time 375764737 ps
CPU time 1.13 seconds
Started Jul 22 05:44:18 PM PDT 24
Finished Jul 22 05:44:20 PM PDT 24
Peak memory 218896 kb
Host smart-ce7817ee-593c-463d-a8aa-9ee56aa2153c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389985612 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.3389985612
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.3297051406
Short name T970
Test name
Test status
Simulation time 27340261 ps
CPU time 1.16 seconds
Started Jul 22 05:44:18 PM PDT 24
Finished Jul 22 05:44:20 PM PDT 24
Peak memory 217620 kb
Host smart-110d25d9-dc15-46c9-995a-ac5cd41fbf9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297051406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.3297051406
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.1401903610
Short name T172
Test name
Test status
Simulation time 105516351 ps
CPU time 1.07 seconds
Started Jul 22 05:42:11 PM PDT 24
Finished Jul 22 05:42:14 PM PDT 24
Peak memory 220612 kb
Host smart-b080d51b-9e26-45c6-a9b8-9809ecc33e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401903610 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.1401903610
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.2020218176
Short name T50
Test name
Test status
Simulation time 89958260 ps
CPU time 0.85 seconds
Started Jul 22 05:42:12 PM PDT 24
Finished Jul 22 05:42:15 PM PDT 24
Peak memory 215172 kb
Host smart-b5f33aec-ccef-4bb7-b6d7-3cf4a06a6d50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020218176 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2020218176
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.1695683404
Short name T490
Test name
Test status
Simulation time 19308976 ps
CPU time 0.87 seconds
Started Jul 22 05:42:12 PM PDT 24
Finished Jul 22 05:42:15 PM PDT 24
Peak memory 215764 kb
Host smart-ea05dcbd-dcf4-40b7-a466-7743cbfd0953
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695683404 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1695683404
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.3127154363
Short name T78
Test name
Test status
Simulation time 40991404 ps
CPU time 1.29 seconds
Started Jul 22 05:42:09 PM PDT 24
Finished Jul 22 05:42:11 PM PDT 24
Peak memory 217220 kb
Host smart-f0b1bad8-1a42-47fb-8b86-70058dbd77f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127154363 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.3127154363
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.2361992932
Short name T209
Test name
Test status
Simulation time 27810768 ps
CPU time 0.9 seconds
Started Jul 22 05:42:11 PM PDT 24
Finished Jul 22 05:42:12 PM PDT 24
Peak memory 218612 kb
Host smart-ecbbd96a-05ea-4296-984f-54037f5fbdf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361992932 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2361992932
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.1240609289
Short name T930
Test name
Test status
Simulation time 102420476 ps
CPU time 1.3 seconds
Started Jul 22 05:42:13 PM PDT 24
Finished Jul 22 05:42:16 PM PDT 24
Peak memory 220352 kb
Host smart-ac6dfb55-d8d7-40c1-b749-32a2a64c6fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240609289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1240609289
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.1805599178
Short name T487
Test name
Test status
Simulation time 21604980 ps
CPU time 1.18 seconds
Started Jul 22 05:42:14 PM PDT 24
Finished Jul 22 05:42:16 PM PDT 24
Peak memory 224312 kb
Host smart-fe5c38cc-b84a-40f2-b14e-b0183004bbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805599178 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.1805599178
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.3140680134
Short name T82
Test name
Test status
Simulation time 35012330 ps
CPU time 0.86 seconds
Started Jul 22 05:42:12 PM PDT 24
Finished Jul 22 05:42:14 PM PDT 24
Peak memory 215608 kb
Host smart-9a8bf56a-efdb-49b5-b2db-814386397117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140680134 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.3140680134
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.2073498916
Short name T667
Test name
Test status
Simulation time 714230921 ps
CPU time 5.15 seconds
Started Jul 22 05:42:11 PM PDT 24
Finished Jul 22 05:42:17 PM PDT 24
Peak memory 217440 kb
Host smart-a68bbbc1-6615-434c-bbbf-18bc06a08e69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073498916 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.2073498916
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.718941073
Short name T851
Test name
Test status
Simulation time 40944206395 ps
CPU time 460.8 seconds
Started Jul 22 05:42:12 PM PDT 24
Finished Jul 22 05:49:54 PM PDT 24
Peak memory 218572 kb
Host smart-58a6dcff-d764-4bd1-8b9a-579810c45696
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718941073 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.718941073
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.1906700462
Short name T419
Test name
Test status
Simulation time 56187252 ps
CPU time 1.27 seconds
Started Jul 22 05:44:16 PM PDT 24
Finished Jul 22 05:44:18 PM PDT 24
Peak memory 217532 kb
Host smart-f07c04b1-8438-41bd-a726-e160fca28702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906700462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.1906700462
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.1262194347
Short name T575
Test name
Test status
Simulation time 82201051 ps
CPU time 1.18 seconds
Started Jul 22 05:44:13 PM PDT 24
Finished Jul 22 05:44:15 PM PDT 24
Peak memory 220192 kb
Host smart-cd62b922-f685-450d-acb1-05d369c53501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262194347 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.1262194347
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.2153107028
Short name T782
Test name
Test status
Simulation time 40004566 ps
CPU time 1.44 seconds
Started Jul 22 05:44:16 PM PDT 24
Finished Jul 22 05:44:19 PM PDT 24
Peak memory 218956 kb
Host smart-73c345b5-3048-4afe-897a-21c4b671b0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153107028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.2153107028
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.1597547726
Short name T974
Test name
Test status
Simulation time 22392600 ps
CPU time 1.28 seconds
Started Jul 22 05:44:14 PM PDT 24
Finished Jul 22 05:44:16 PM PDT 24
Peak memory 220224 kb
Host smart-bb03bb89-d063-428a-817a-4d2409c3c8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597547726 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.1597547726
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.3898613800
Short name T73
Test name
Test status
Simulation time 119835069 ps
CPU time 1.51 seconds
Started Jul 22 05:44:53 PM PDT 24
Finished Jul 22 05:44:56 PM PDT 24
Peak memory 219040 kb
Host smart-ffd76b8d-f9af-4812-b931-8f15a9629cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898613800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.3898613800
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.3469572673
Short name T516
Test name
Test status
Simulation time 44624555 ps
CPU time 1.2 seconds
Started Jul 22 05:44:14 PM PDT 24
Finished Jul 22 05:44:15 PM PDT 24
Peak memory 220196 kb
Host smart-4bd7656c-03b4-4593-8252-be0201803881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469572673 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.3469572673
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.3939198145
Short name T798
Test name
Test status
Simulation time 63719347 ps
CPU time 1.26 seconds
Started Jul 22 05:44:18 PM PDT 24
Finished Jul 22 05:44:20 PM PDT 24
Peak memory 218688 kb
Host smart-1729ae94-272d-47f2-bba6-c4942ec6aca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939198145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.3939198145
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.1574810018
Short name T701
Test name
Test status
Simulation time 205611821 ps
CPU time 1.29 seconds
Started Jul 22 05:44:16 PM PDT 24
Finished Jul 22 05:44:19 PM PDT 24
Peak memory 219868 kb
Host smart-f87823b4-a611-4e58-97f7-381321ffcd13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574810018 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.1574810018
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.962455412
Short name T70
Test name
Test status
Simulation time 30333452 ps
CPU time 0.99 seconds
Started Jul 22 05:44:17 PM PDT 24
Finished Jul 22 05:44:19 PM PDT 24
Peak memory 217500 kb
Host smart-618c9d2b-f041-47b3-8074-d0e2b26b0cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962455412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.962455412
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.3163411521
Short name T553
Test name
Test status
Simulation time 90611456 ps
CPU time 1.22 seconds
Started Jul 22 05:44:30 PM PDT 24
Finished Jul 22 05:44:31 PM PDT 24
Peak memory 218900 kb
Host smart-d699df6a-009d-4699-959e-2fb536011678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163411521 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.3163411521
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.3152180991
Short name T42
Test name
Test status
Simulation time 30759664 ps
CPU time 1.27 seconds
Started Jul 22 05:44:15 PM PDT 24
Finished Jul 22 05:44:18 PM PDT 24
Peak memory 217500 kb
Host smart-732e06c2-9f98-484f-8f2a-e9230b52b820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152180991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3152180991
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.864216340
Short name T799
Test name
Test status
Simulation time 74179535 ps
CPU time 1.13 seconds
Started Jul 22 05:44:14 PM PDT 24
Finished Jul 22 05:44:16 PM PDT 24
Peak memory 219752 kb
Host smart-771a0a9d-b87a-416a-944a-6a2ed14c3064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864216340 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.864216340
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.502843179
Short name T683
Test name
Test status
Simulation time 209126872 ps
CPU time 2.12 seconds
Started Jul 22 05:44:18 PM PDT 24
Finished Jul 22 05:44:21 PM PDT 24
Peak memory 220512 kb
Host smart-68f8e9d6-1e78-4cc3-90b8-d975f80983f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502843179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.502843179
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.1529511003
Short name T742
Test name
Test status
Simulation time 39817687 ps
CPU time 1.14 seconds
Started Jul 22 05:44:15 PM PDT 24
Finished Jul 22 05:44:16 PM PDT 24
Peak memory 218684 kb
Host smart-b4e96335-e46d-40a4-adf9-46443de97247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529511003 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.1529511003
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.1445025551
Short name T38
Test name
Test status
Simulation time 50285719 ps
CPU time 1.16 seconds
Started Jul 22 05:44:14 PM PDT 24
Finished Jul 22 05:44:16 PM PDT 24
Peak memory 217652 kb
Host smart-35b9ba75-916e-48b1-8825-408b8c062083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445025551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.1445025551
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.1791526309
Short name T664
Test name
Test status
Simulation time 22901089 ps
CPU time 1.19 seconds
Started Jul 22 05:44:19 PM PDT 24
Finished Jul 22 05:44:21 PM PDT 24
Peak memory 220208 kb
Host smart-ab1fd245-a7e8-4f4a-b2ad-526a6b0532b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791526309 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.1791526309
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.403100283
Short name T331
Test name
Test status
Simulation time 108951299 ps
CPU time 1.19 seconds
Started Jul 22 05:44:14 PM PDT 24
Finished Jul 22 05:44:15 PM PDT 24
Peak memory 218784 kb
Host smart-c0f7e7db-0abb-4401-ad4d-e4b3c41a9daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403100283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.403100283
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.2219786382
Short name T912
Test name
Test status
Simulation time 69437239 ps
CPU time 1.19 seconds
Started Jul 22 05:44:24 PM PDT 24
Finished Jul 22 05:44:25 PM PDT 24
Peak memory 220148 kb
Host smart-26ff9038-8e8d-4903-90ae-68119f66f596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219786382 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.2219786382
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.1951558060
Short name T627
Test name
Test status
Simulation time 40616914 ps
CPU time 1.61 seconds
Started Jul 22 05:44:22 PM PDT 24
Finished Jul 22 05:44:24 PM PDT 24
Peak memory 218836 kb
Host smart-564f5735-b3c3-4e53-82fb-7d86c973bcbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951558060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1951558060
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.2940461395
Short name T629
Test name
Test status
Simulation time 114648797 ps
CPU time 1.11 seconds
Started Jul 22 05:42:12 PM PDT 24
Finished Jul 22 05:42:14 PM PDT 24
Peak memory 218940 kb
Host smart-b654f445-8433-4e48-a66c-7e75cf6d4bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940461395 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.2940461395
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.1425519537
Short name T939
Test name
Test status
Simulation time 17524717 ps
CPU time 0.84 seconds
Started Jul 22 05:42:18 PM PDT 24
Finished Jul 22 05:42:20 PM PDT 24
Peak memory 207104 kb
Host smart-fc60cab2-01c3-48b3-84db-84010fcac011
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425519537 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1425519537
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.2042779542
Short name T460
Test name
Test status
Simulation time 41986709 ps
CPU time 0.88 seconds
Started Jul 22 05:42:28 PM PDT 24
Finished Jul 22 05:42:29 PM PDT 24
Peak memory 216640 kb
Host smart-4e36a9b7-42fe-4268-80d6-b58467eaed4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042779542 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2042779542
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.329263735
Short name T750
Test name
Test status
Simulation time 60428642 ps
CPU time 1.51 seconds
Started Jul 22 05:42:21 PM PDT 24
Finished Jul 22 05:42:23 PM PDT 24
Peak memory 217452 kb
Host smart-b6e83760-bdc0-4f41-86d7-c5a9640ec632
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329263735 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_di
sable_auto_req_mode.329263735
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.3362134690
Short name T501
Test name
Test status
Simulation time 33499221 ps
CPU time 1.08 seconds
Started Jul 22 05:42:29 PM PDT 24
Finished Jul 22 05:42:31 PM PDT 24
Peak memory 220168 kb
Host smart-44e13ebf-834e-4fa6-9a70-0e119459fe24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362134690 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.3362134690
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.4013811531
Short name T448
Test name
Test status
Simulation time 28750981 ps
CPU time 1.2 seconds
Started Jul 22 05:42:13 PM PDT 24
Finished Jul 22 05:42:16 PM PDT 24
Peak memory 218672 kb
Host smart-eb741ce5-08e1-45d8-89a3-9c60b0209db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013811531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.4013811531
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.3464936804
Short name T865
Test name
Test status
Simulation time 21062630 ps
CPU time 1.07 seconds
Started Jul 22 05:42:11 PM PDT 24
Finished Jul 22 05:42:13 PM PDT 24
Peak memory 216208 kb
Host smart-2032dc05-d120-4e58-81d3-57f563d84913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464936804 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.3464936804
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.362383251
Short name T395
Test name
Test status
Simulation time 17169369 ps
CPU time 0.97 seconds
Started Jul 22 05:42:12 PM PDT 24
Finished Jul 22 05:42:15 PM PDT 24
Peak memory 215608 kb
Host smart-09b4677f-af6e-4f23-a101-88c1caf48926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362383251 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.362383251
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.244736550
Short name T23
Test name
Test status
Simulation time 330308576 ps
CPU time 6.33 seconds
Started Jul 22 05:42:12 PM PDT 24
Finished Jul 22 05:42:20 PM PDT 24
Peak memory 218784 kb
Host smart-1145bae4-7422-4e5c-8c5f-6ce06764d78d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244736550 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.244736550
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2346418976
Short name T717
Test name
Test status
Simulation time 73988914745 ps
CPU time 835.92 seconds
Started Jul 22 05:42:13 PM PDT 24
Finished Jul 22 05:56:11 PM PDT 24
Peak memory 221476 kb
Host smart-76ce86a3-2812-4186-a09b-4dadcb98c98c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346418976 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2346418976
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.1347081534
Short name T563
Test name
Test status
Simulation time 53591073 ps
CPU time 1.13 seconds
Started Jul 22 05:44:27 PM PDT 24
Finished Jul 22 05:44:29 PM PDT 24
Peak memory 219344 kb
Host smart-a67646c3-55dd-4b38-b140-a42d1f309811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347081534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1347081534
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.685922736
Short name T306
Test name
Test status
Simulation time 39810280 ps
CPU time 1.23 seconds
Started Jul 22 05:44:26 PM PDT 24
Finished Jul 22 05:44:28 PM PDT 24
Peak memory 219948 kb
Host smart-a8df194c-1903-4cd8-b06d-3b19254ffc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685922736 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.685922736
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.2671067231
Short name T359
Test name
Test status
Simulation time 104645809 ps
CPU time 1.22 seconds
Started Jul 22 05:44:32 PM PDT 24
Finished Jul 22 05:44:34 PM PDT 24
Peak memory 217648 kb
Host smart-e4b6ab4f-eb31-4145-a501-9650abfa21df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671067231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.2671067231
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.4042202376
Short name T594
Test name
Test status
Simulation time 52013757 ps
CPU time 1.25 seconds
Started Jul 22 05:44:32 PM PDT 24
Finished Jul 22 05:44:34 PM PDT 24
Peak memory 219096 kb
Host smart-fd733647-7ee0-479f-be7d-9f8d23110c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042202376 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.4042202376
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.1523759713
Short name T558
Test name
Test status
Simulation time 28399050 ps
CPU time 1.24 seconds
Started Jul 22 05:44:24 PM PDT 24
Finished Jul 22 05:44:26 PM PDT 24
Peak memory 218768 kb
Host smart-a2acf99b-9646-4ab4-bf2c-192c48117835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523759713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.1523759713
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.3704635318
Short name T684
Test name
Test status
Simulation time 39834286 ps
CPU time 1.63 seconds
Started Jul 22 05:44:22 PM PDT 24
Finished Jul 22 05:44:25 PM PDT 24
Peak memory 218680 kb
Host smart-0fa91f2d-95e7-47a2-8a69-07120eefe777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704635318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.3704635318
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.2790761171
Short name T304
Test name
Test status
Simulation time 85332396 ps
CPU time 1.13 seconds
Started Jul 22 05:44:24 PM PDT 24
Finished Jul 22 05:44:26 PM PDT 24
Peak memory 218792 kb
Host smart-dac79ff1-0535-408e-b9f6-d502f2b7fea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790761171 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.2790761171
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.3124655888
Short name T595
Test name
Test status
Simulation time 95304200 ps
CPU time 1.37 seconds
Started Jul 22 05:44:25 PM PDT 24
Finished Jul 22 05:44:27 PM PDT 24
Peak memory 218940 kb
Host smart-f234722b-e1ee-48fc-8bfa-4dd8d874ef3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124655888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.3124655888
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.2332406749
Short name T157
Test name
Test status
Simulation time 26759915 ps
CPU time 1.21 seconds
Started Jul 22 05:44:23 PM PDT 24
Finished Jul 22 05:44:24 PM PDT 24
Peak memory 220384 kb
Host smart-9829919d-a0b5-452e-a286-05afc74649a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332406749 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.2332406749
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.2928832474
Short name T370
Test name
Test status
Simulation time 35577995 ps
CPU time 1.39 seconds
Started Jul 22 05:44:24 PM PDT 24
Finished Jul 22 05:44:26 PM PDT 24
Peak memory 218892 kb
Host smart-badd6bed-f3ce-4778-ba87-3a7584fb2be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928832474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.2928832474
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.2552100637
Short name T246
Test name
Test status
Simulation time 37649334 ps
CPU time 1.27 seconds
Started Jul 22 05:44:26 PM PDT 24
Finished Jul 22 05:44:28 PM PDT 24
Peak memory 216028 kb
Host smart-0ca9dbc9-bf70-4aa6-ac90-155f076bf7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552100637 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.2552100637
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.1034079504
Short name T928
Test name
Test status
Simulation time 55512546 ps
CPU time 0.96 seconds
Started Jul 22 05:44:23 PM PDT 24
Finished Jul 22 05:44:24 PM PDT 24
Peak memory 217792 kb
Host smart-1a3f0e0a-55a7-47bb-837b-2f86e26a31d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034079504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.1034079504
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.1844376946
Short name T950
Test name
Test status
Simulation time 52750146 ps
CPU time 1.05 seconds
Started Jul 22 05:44:34 PM PDT 24
Finished Jul 22 05:44:35 PM PDT 24
Peak memory 218912 kb
Host smart-595fde9b-8e80-4f0f-9436-08317fdc905b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844376946 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.1844376946
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.685820848
Short name T815
Test name
Test status
Simulation time 86510855 ps
CPU time 1.21 seconds
Started Jul 22 05:44:32 PM PDT 24
Finished Jul 22 05:44:34 PM PDT 24
Peak memory 220436 kb
Host smart-d3e988e2-13db-41eb-947d-25187262f81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685820848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.685820848
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.141879426
Short name T545
Test name
Test status
Simulation time 27811745 ps
CPU time 1.2 seconds
Started Jul 22 05:44:25 PM PDT 24
Finished Jul 22 05:44:27 PM PDT 24
Peak memory 218740 kb
Host smart-76737366-46e8-4039-b420-41fe4fb75954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141879426 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.141879426
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.3819412297
Short name T814
Test name
Test status
Simulation time 50416008 ps
CPU time 1.75 seconds
Started Jul 22 05:44:24 PM PDT 24
Finished Jul 22 05:44:27 PM PDT 24
Peak memory 219000 kb
Host smart-365015f1-2f84-4bf2-b49b-d7f2786a8d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819412297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.3819412297
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.2029085343
Short name T465
Test name
Test status
Simulation time 75693710 ps
CPU time 1.17 seconds
Started Jul 22 05:44:24 PM PDT 24
Finished Jul 22 05:44:25 PM PDT 24
Peak memory 219612 kb
Host smart-11a1110f-b7db-491e-97ad-cfa4813732fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029085343 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.2029085343
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.364162838
Short name T986
Test name
Test status
Simulation time 39632139 ps
CPU time 1.65 seconds
Started Jul 22 05:44:24 PM PDT 24
Finished Jul 22 05:44:27 PM PDT 24
Peak memory 217916 kb
Host smart-cb536f4a-bcca-4b18-bc35-ee6895027597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364162838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.364162838
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.1141679426
Short name T180
Test name
Test status
Simulation time 86321516 ps
CPU time 1.18 seconds
Started Jul 22 05:42:19 PM PDT 24
Finished Jul 22 05:42:21 PM PDT 24
Peak memory 216012 kb
Host smart-63a6e0a5-a754-478f-8323-a9c066844f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141679426 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1141679426
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.3019030061
Short name T535
Test name
Test status
Simulation time 87992716 ps
CPU time 1.05 seconds
Started Jul 22 05:42:29 PM PDT 24
Finished Jul 22 05:42:31 PM PDT 24
Peak memory 207044 kb
Host smart-239dbd24-a332-4046-83a4-dd6e410aa972
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019030061 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3019030061
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_err.3255192380
Short name T600
Test name
Test status
Simulation time 42261015 ps
CPU time 0.92 seconds
Started Jul 22 05:42:18 PM PDT 24
Finished Jul 22 05:42:20 PM PDT 24
Peak memory 224088 kb
Host smart-2398826a-3f1e-454e-88af-1783e74e155f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255192380 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.3255192380
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.1959617624
Short name T41
Test name
Test status
Simulation time 179016431 ps
CPU time 1.85 seconds
Started Jul 22 05:42:31 PM PDT 24
Finished Jul 22 05:42:34 PM PDT 24
Peak memory 219112 kb
Host smart-393a30d3-d27f-41c9-bcbd-ba1d9252b06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959617624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1959617624
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.1971959510
Short name T101
Test name
Test status
Simulation time 21150374 ps
CPU time 1.06 seconds
Started Jul 22 05:42:26 PM PDT 24
Finished Jul 22 05:42:27 PM PDT 24
Peak memory 216008 kb
Host smart-0af0c545-fd37-49a8-9af5-e2c0fe670dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971959510 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1971959510
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.2289748000
Short name T769
Test name
Test status
Simulation time 20017057 ps
CPU time 0.88 seconds
Started Jul 22 05:42:19 PM PDT 24
Finished Jul 22 05:42:21 PM PDT 24
Peak memory 215636 kb
Host smart-1844c213-3353-41c0-85bb-4d24224f4742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289748000 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.2289748000
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.94068282
Short name T807
Test name
Test status
Simulation time 33336653 ps
CPU time 1.26 seconds
Started Jul 22 05:42:30 PM PDT 24
Finished Jul 22 05:42:32 PM PDT 24
Peak memory 215660 kb
Host smart-73564400-6fc9-4b67-b9b7-b74f6512585e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94068282 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.94068282
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.3656084950
Short name T793
Test name
Test status
Simulation time 270712959850 ps
CPU time 1807.42 seconds
Started Jul 22 05:42:29 PM PDT 24
Finished Jul 22 06:12:38 PM PDT 24
Peak memory 226444 kb
Host smart-4522465e-bfdc-4b66-b38f-40af528616b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656084950 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.3656084950
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.1744122127
Short name T216
Test name
Test status
Simulation time 23438455 ps
CPU time 1.22 seconds
Started Jul 22 05:44:22 PM PDT 24
Finished Jul 22 05:44:24 PM PDT 24
Peak memory 218968 kb
Host smart-02b14655-c18f-4bf3-9a0f-ae2d6b32b3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744122127 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.1744122127
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/171.edn_alert.3274261499
Short name T801
Test name
Test status
Simulation time 45611896 ps
CPU time 1.12 seconds
Started Jul 22 05:44:22 PM PDT 24
Finished Jul 22 05:44:24 PM PDT 24
Peak memory 221180 kb
Host smart-ad95d782-8566-4e4a-9e7a-814f39fbed9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274261499 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.3274261499
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.513060601
Short name T396
Test name
Test status
Simulation time 60270740 ps
CPU time 1.13 seconds
Started Jul 22 05:44:21 PM PDT 24
Finished Jul 22 05:44:22 PM PDT 24
Peak memory 218900 kb
Host smart-a52068c9-4014-49ae-a1ba-fa0b4667eabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513060601 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.513060601
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.327335844
Short name T402
Test name
Test status
Simulation time 30432992 ps
CPU time 1.23 seconds
Started Jul 22 05:44:26 PM PDT 24
Finished Jul 22 05:44:28 PM PDT 24
Peak memory 220080 kb
Host smart-e680d119-5600-41e9-a589-fdd65d39164d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327335844 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.327335844
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.422334197
Short name T866
Test name
Test status
Simulation time 71353210 ps
CPU time 1.21 seconds
Started Jul 22 05:44:23 PM PDT 24
Finished Jul 22 05:44:25 PM PDT 24
Peak memory 219092 kb
Host smart-86634a0a-5ebc-4d9e-86d4-64cfb0deb9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422334197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.422334197
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.1542904643
Short name T150
Test name
Test status
Simulation time 53723977 ps
CPU time 1.23 seconds
Started Jul 22 05:44:23 PM PDT 24
Finished Jul 22 05:44:24 PM PDT 24
Peak memory 218904 kb
Host smart-b0fd404d-777e-49cc-a3d2-afb97a598df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542904643 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.1542904643
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.2437313333
Short name T599
Test name
Test status
Simulation time 77376386 ps
CPU time 1.21 seconds
Started Jul 22 05:44:32 PM PDT 24
Finished Jul 22 05:44:34 PM PDT 24
Peak memory 219564 kb
Host smart-79276236-062f-4664-b716-188d497372ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437313333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.2437313333
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.771829645
Short name T303
Test name
Test status
Simulation time 53698855 ps
CPU time 1.17 seconds
Started Jul 22 05:44:25 PM PDT 24
Finished Jul 22 05:44:27 PM PDT 24
Peak memory 220060 kb
Host smart-11ceea39-c9e5-423d-b116-6069bb306b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771829645 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.771829645
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.1064739554
Short name T454
Test name
Test status
Simulation time 77131035 ps
CPU time 2.78 seconds
Started Jul 22 05:44:22 PM PDT 24
Finished Jul 22 05:44:26 PM PDT 24
Peak memory 217752 kb
Host smart-2626ac24-3bcb-40e9-a942-007da6e66c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064739554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.1064739554
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.3206631111
Short name T977
Test name
Test status
Simulation time 29029898 ps
CPU time 1.38 seconds
Started Jul 22 05:44:24 PM PDT 24
Finished Jul 22 05:44:26 PM PDT 24
Peak memory 220040 kb
Host smart-1778590b-9eb0-4521-9a8d-055c6c66a0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206631111 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.3206631111
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.966592161
Short name T632
Test name
Test status
Simulation time 77096319 ps
CPU time 1.6 seconds
Started Jul 22 05:44:22 PM PDT 24
Finished Jul 22 05:44:24 PM PDT 24
Peak memory 219328 kb
Host smart-c92a23a4-8178-4ad6-94d1-625d3e7aa14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966592161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.966592161
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.1409910473
Short name T182
Test name
Test status
Simulation time 24003650 ps
CPU time 1.19 seconds
Started Jul 22 05:44:36 PM PDT 24
Finished Jul 22 05:44:38 PM PDT 24
Peak memory 221204 kb
Host smart-4efb8093-5161-4a11-a0e5-8ab921bd22e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409910473 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.1409910473
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.1619983492
Short name T646
Test name
Test status
Simulation time 33921959 ps
CPU time 1.27 seconds
Started Jul 22 05:44:23 PM PDT 24
Finished Jul 22 05:44:24 PM PDT 24
Peak memory 220180 kb
Host smart-e200c018-7fc5-406a-95b6-5bc613d111c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619983492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.1619983492
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.1075850416
Short name T243
Test name
Test status
Simulation time 80882603 ps
CPU time 1.24 seconds
Started Jul 22 05:44:24 PM PDT 24
Finished Jul 22 05:44:26 PM PDT 24
Peak memory 216052 kb
Host smart-2f8aa33e-7f20-41fe-9abc-531a5f67bfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075850416 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.1075850416
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.1252007615
Short name T733
Test name
Test status
Simulation time 51452049 ps
CPU time 1.13 seconds
Started Jul 22 05:44:26 PM PDT 24
Finished Jul 22 05:44:28 PM PDT 24
Peak memory 217504 kb
Host smart-11e0e1a6-f38d-4987-a587-04cb6fdedfb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252007615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.1252007615
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.2316312009
Short name T144
Test name
Test status
Simulation time 26836583 ps
CPU time 1.29 seconds
Started Jul 22 05:44:27 PM PDT 24
Finished Jul 22 05:44:29 PM PDT 24
Peak memory 220896 kb
Host smart-f42f9713-bd9b-40f3-9ef3-a41c4a12eb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316312009 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.2316312009
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.3424741477
Short name T736
Test name
Test status
Simulation time 51730154 ps
CPU time 1.17 seconds
Started Jul 22 05:44:32 PM PDT 24
Finished Jul 22 05:44:34 PM PDT 24
Peak memory 218820 kb
Host smart-5a2f4f6b-b136-46e4-b2fd-73ddd4c124d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424741477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3424741477
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.19141630
Short name T112
Test name
Test status
Simulation time 30488885 ps
CPU time 1.35 seconds
Started Jul 22 05:44:24 PM PDT 24
Finished Jul 22 05:44:26 PM PDT 24
Peak memory 220264 kb
Host smart-f9d55b76-03fc-49b8-8424-78ad9715aa6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19141630 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.19141630
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.3302022648
Short name T768
Test name
Test status
Simulation time 103163894 ps
CPU time 1.29 seconds
Started Jul 22 05:44:25 PM PDT 24
Finished Jul 22 05:44:27 PM PDT 24
Peak memory 217624 kb
Host smart-2be33867-358a-4358-83ab-fbbca47f4f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302022648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3302022648
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.370887409
Short name T156
Test name
Test status
Simulation time 51709197 ps
CPU time 1.28 seconds
Started Jul 22 05:42:20 PM PDT 24
Finished Jul 22 05:42:22 PM PDT 24
Peak memory 216060 kb
Host smart-9559e647-289b-41a3-b402-d92a178097ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370887409 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.370887409
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.2953687025
Short name T534
Test name
Test status
Simulation time 88761552 ps
CPU time 0.94 seconds
Started Jul 22 05:42:26 PM PDT 24
Finished Jul 22 05:42:28 PM PDT 24
Peak memory 207036 kb
Host smart-16b4387f-a79a-4e38-a9e6-249f8eea2654
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953687025 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2953687025
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.719947560
Short name T154
Test name
Test status
Simulation time 11283385 ps
CPU time 0.93 seconds
Started Jul 22 05:42:30 PM PDT 24
Finished Jul 22 05:42:32 PM PDT 24
Peak memory 215716 kb
Host smart-634a61d4-5a7c-4666-81e6-249d92c0b476
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719947560 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.719947560
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.108629133
Short name T539
Test name
Test status
Simulation time 27012244 ps
CPU time 1.02 seconds
Started Jul 22 05:42:29 PM PDT 24
Finished Jul 22 05:42:31 PM PDT 24
Peak memory 218572 kb
Host smart-0c8b92ae-f0a8-4ad2-af76-be0762cbc37a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108629133 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_di
sable_auto_req_mode.108629133
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_genbits.488117799
Short name T14
Test name
Test status
Simulation time 78848065 ps
CPU time 1.52 seconds
Started Jul 22 05:42:28 PM PDT 24
Finished Jul 22 05:42:31 PM PDT 24
Peak memory 220240 kb
Host smart-ba75cabc-13cb-4e13-882e-27505e9a03ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488117799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.488117799
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.3851214669
Short name T708
Test name
Test status
Simulation time 21170406 ps
CPU time 1.1 seconds
Started Jul 22 05:42:19 PM PDT 24
Finished Jul 22 05:42:20 PM PDT 24
Peak memory 216200 kb
Host smart-18900d99-b589-4690-bccb-992cfb960d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851214669 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.3851214669
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.1836732566
Short name T379
Test name
Test status
Simulation time 53727550 ps
CPU time 0.96 seconds
Started Jul 22 05:42:20 PM PDT 24
Finished Jul 22 05:42:22 PM PDT 24
Peak memory 215500 kb
Host smart-bfed43ed-9fa4-48c6-84a1-5231d27f82f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836732566 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.1836732566
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.4127223077
Short name T900
Test name
Test status
Simulation time 196687239 ps
CPU time 4.04 seconds
Started Jul 22 05:42:21 PM PDT 24
Finished Jul 22 05:42:26 PM PDT 24
Peak memory 220276 kb
Host smart-ec61a502-f664-4384-a8e0-9c01c1f1cb42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127223077 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.4127223077
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.3298849689
Short name T227
Test name
Test status
Simulation time 215464391185 ps
CPU time 1753.99 seconds
Started Jul 22 05:42:26 PM PDT 24
Finished Jul 22 06:11:41 PM PDT 24
Peak memory 225176 kb
Host smart-fe956f66-0878-4173-b699-9e6340d5b044
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298849689 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.3298849689
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.200952055
Short name T75
Test name
Test status
Simulation time 24455429 ps
CPU time 1.21 seconds
Started Jul 22 05:44:25 PM PDT 24
Finished Jul 22 05:44:27 PM PDT 24
Peak memory 220052 kb
Host smart-ee84ea02-e6ed-4499-8211-b93fea0a5c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200952055 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.200952055
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.785597273
Short name T652
Test name
Test status
Simulation time 46119324 ps
CPU time 1.53 seconds
Started Jul 22 05:44:27 PM PDT 24
Finished Jul 22 05:44:29 PM PDT 24
Peak memory 217640 kb
Host smart-0366f61c-ba61-4922-83d2-8364691eace7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785597273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.785597273
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.2687817005
Short name T711
Test name
Test status
Simulation time 97061202 ps
CPU time 1.33 seconds
Started Jul 22 05:44:40 PM PDT 24
Finished Jul 22 05:44:42 PM PDT 24
Peak memory 216040 kb
Host smart-4ad30249-4bca-47a1-ac80-f97ae81176bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687817005 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.2687817005
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.371468875
Short name T47
Test name
Test status
Simulation time 50311863 ps
CPU time 2.06 seconds
Started Jul 22 05:44:25 PM PDT 24
Finished Jul 22 05:44:28 PM PDT 24
Peak memory 218944 kb
Host smart-38acf35f-88aa-49a1-a93d-f236d0de0285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371468875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.371468875
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.3068700321
Short name T615
Test name
Test status
Simulation time 82856707 ps
CPU time 1.12 seconds
Started Jul 22 05:44:40 PM PDT 24
Finished Jul 22 05:44:42 PM PDT 24
Peak memory 218724 kb
Host smart-bc551314-2c86-4cb0-b7c1-e1b601cddc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068700321 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.3068700321
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.1276769337
Short name T859
Test name
Test status
Simulation time 85859923 ps
CPU time 1.16 seconds
Started Jul 22 05:44:40 PM PDT 24
Finished Jul 22 05:44:42 PM PDT 24
Peak memory 217672 kb
Host smart-675f4795-575c-4857-86fe-f909ed0e3d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276769337 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.1276769337
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.3848112367
Short name T483
Test name
Test status
Simulation time 49079369 ps
CPU time 1.3 seconds
Started Jul 22 05:44:38 PM PDT 24
Finished Jul 22 05:44:40 PM PDT 24
Peak memory 220272 kb
Host smart-8b0553c4-1492-4370-982b-ca0e29c47c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848112367 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.3848112367
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.700504707
Short name T609
Test name
Test status
Simulation time 41685447 ps
CPU time 1.61 seconds
Started Jul 22 05:44:41 PM PDT 24
Finished Jul 22 05:44:44 PM PDT 24
Peak memory 217708 kb
Host smart-4323889a-4284-433f-866c-d2a2099f610c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700504707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.700504707
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.1168803181
Short name T824
Test name
Test status
Simulation time 31963610 ps
CPU time 1.27 seconds
Started Jul 22 05:44:45 PM PDT 24
Finished Jul 22 05:44:47 PM PDT 24
Peak memory 221432 kb
Host smart-0665728b-48a7-40e3-9244-ec383e76a038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168803181 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.1168803181
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.1269878253
Short name T385
Test name
Test status
Simulation time 79523693 ps
CPU time 1.37 seconds
Started Jul 22 05:44:40 PM PDT 24
Finished Jul 22 05:44:42 PM PDT 24
Peak memory 219160 kb
Host smart-d0a1ac31-3edc-432b-b4ad-31f4aee89bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269878253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.1269878253
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.3475851338
Short name T638
Test name
Test status
Simulation time 292473252 ps
CPU time 1.39 seconds
Started Jul 22 05:44:43 PM PDT 24
Finished Jul 22 05:44:46 PM PDT 24
Peak memory 216064 kb
Host smart-b8be1ed6-7388-4ee6-b829-3f4aebbacdb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475851338 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.3475851338
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.2794499819
Short name T572
Test name
Test status
Simulation time 50457105 ps
CPU time 0.97 seconds
Started Jul 22 05:44:40 PM PDT 24
Finished Jul 22 05:44:42 PM PDT 24
Peak memory 217492 kb
Host smart-fbf3f562-48db-41fe-9db2-804890bb6204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794499819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2794499819
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.445650092
Short name T606
Test name
Test status
Simulation time 25429472 ps
CPU time 1.21 seconds
Started Jul 22 05:44:44 PM PDT 24
Finished Jul 22 05:44:47 PM PDT 24
Peak memory 220172 kb
Host smart-41e53566-848b-4ca4-b29e-1ec355632568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445650092 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.445650092
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/187.edn_alert.2143340543
Short name T288
Test name
Test status
Simulation time 29001406 ps
CPU time 1.36 seconds
Started Jul 22 05:44:39 PM PDT 24
Finished Jul 22 05:44:41 PM PDT 24
Peak memory 220544 kb
Host smart-1e3df37d-1204-41b1-b5d1-551160b7bf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143340543 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.2143340543
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.2689493271
Short name T441
Test name
Test status
Simulation time 177649652 ps
CPU time 2.9 seconds
Started Jul 22 05:44:41 PM PDT 24
Finished Jul 22 05:44:45 PM PDT 24
Peak memory 220108 kb
Host smart-768ae30d-4fa3-4e62-9e9a-8710d4c5bddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689493271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2689493271
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.782969156
Short name T877
Test name
Test status
Simulation time 38878691 ps
CPU time 1.08 seconds
Started Jul 22 05:44:44 PM PDT 24
Finished Jul 22 05:44:46 PM PDT 24
Peak memory 218772 kb
Host smart-da52ee59-ecd6-4e73-a974-ab9c526ae0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782969156 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.782969156
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.394090678
Short name T478
Test name
Test status
Simulation time 295887160 ps
CPU time 2.79 seconds
Started Jul 22 05:44:41 PM PDT 24
Finished Jul 22 05:44:45 PM PDT 24
Peak memory 219696 kb
Host smart-6509fc20-4f7a-46d8-83d9-0a9d08707622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394090678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.394090678
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.417604615
Short name T299
Test name
Test status
Simulation time 27955565 ps
CPU time 1.27 seconds
Started Jul 22 05:42:22 PM PDT 24
Finished Jul 22 05:42:24 PM PDT 24
Peak memory 221192 kb
Host smart-169e6315-5ede-4bd0-a545-e3040c39a157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417604615 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.417604615
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.3329561006
Short name T557
Test name
Test status
Simulation time 77771173 ps
CPU time 0.89 seconds
Started Jul 22 05:42:19 PM PDT 24
Finished Jul 22 05:42:21 PM PDT 24
Peak memory 207052 kb
Host smart-c3ceba98-36d0-40dd-8744-09be0164759b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329561006 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3329561006
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.9113652
Short name T215
Test name
Test status
Simulation time 15416477 ps
CPU time 0.92 seconds
Started Jul 22 05:42:20 PM PDT 24
Finished Jul 22 05:42:22 PM PDT 24
Peak memory 215924 kb
Host smart-a2cbd4f7-ba13-43fd-b2bd-4a3de0672eef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9113652 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.9113652
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.4011353271
Short name T959
Test name
Test status
Simulation time 50476241 ps
CPU time 1.18 seconds
Started Jul 22 05:42:18 PM PDT 24
Finished Jul 22 05:42:19 PM PDT 24
Peak memory 218960 kb
Host smart-1c88cc9f-d1ef-4e11-b4e5-74035cb88635
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011353271 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.4011353271
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.2689306140
Short name T522
Test name
Test status
Simulation time 51711739 ps
CPU time 0.86 seconds
Started Jul 22 05:42:20 PM PDT 24
Finished Jul 22 05:42:22 PM PDT 24
Peak memory 218640 kb
Host smart-062f7077-aeb4-459a-989b-53eb002013f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689306140 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.2689306140
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.446824328
Short name T672
Test name
Test status
Simulation time 47491394 ps
CPU time 1.66 seconds
Started Jul 22 05:42:30 PM PDT 24
Finished Jul 22 05:42:33 PM PDT 24
Peak memory 220728 kb
Host smart-c4fdd542-4cbe-4673-9ffd-4a86c7887a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446824328 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.446824328
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3882273078
Short name T51
Test name
Test status
Simulation time 41873516 ps
CPU time 1 seconds
Started Jul 22 05:42:25 PM PDT 24
Finished Jul 22 05:42:26 PM PDT 24
Peak memory 224356 kb
Host smart-3700e166-a030-41fc-845c-fda66718469e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882273078 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3882273078
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.2134100822
Short name T342
Test name
Test status
Simulation time 16810125 ps
CPU time 0.97 seconds
Started Jul 22 05:42:20 PM PDT 24
Finished Jul 22 05:42:22 PM PDT 24
Peak memory 215592 kb
Host smart-38f3aecc-60a5-465f-b256-e589dd4e86cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134100822 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.2134100822
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.120145017
Short name T236
Test name
Test status
Simulation time 1052140922 ps
CPU time 5.48 seconds
Started Jul 22 05:42:23 PM PDT 24
Finished Jul 22 05:42:29 PM PDT 24
Peak memory 217508 kb
Host smart-1a6732aa-221f-45a4-bc89-5db2ea1d8935
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120145017 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.120145017
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.2235591168
Short name T961
Test name
Test status
Simulation time 276352897953 ps
CPU time 1880.6 seconds
Started Jul 22 05:42:25 PM PDT 24
Finished Jul 22 06:13:46 PM PDT 24
Peak memory 228016 kb
Host smart-ce3d53e9-b96f-4ae8-ba08-e5afc40a6c6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235591168 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.2235591168
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.588918344
Short name T770
Test name
Test status
Simulation time 37659225 ps
CPU time 1.67 seconds
Started Jul 22 05:44:39 PM PDT 24
Finished Jul 22 05:44:41 PM PDT 24
Peak memory 218804 kb
Host smart-b1193cb7-a76b-43ac-b48e-dcba8b00d43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588918344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.588918344
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.103087313
Short name T136
Test name
Test status
Simulation time 24748852 ps
CPU time 1.15 seconds
Started Jul 22 05:44:49 PM PDT 24
Finished Jul 22 05:44:50 PM PDT 24
Peak memory 218952 kb
Host smart-b44eddb7-864d-4feb-961d-c96d8ae675bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103087313 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.103087313
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.457782636
Short name T867
Test name
Test status
Simulation time 52156381 ps
CPU time 1.47 seconds
Started Jul 22 05:44:42 PM PDT 24
Finished Jul 22 05:44:44 PM PDT 24
Peak memory 220620 kb
Host smart-a115edd6-5c94-459e-8966-9d0574be277f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457782636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.457782636
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.865201439
Short name T195
Test name
Test status
Simulation time 153421490 ps
CPU time 1.21 seconds
Started Jul 22 05:44:39 PM PDT 24
Finished Jul 22 05:44:40 PM PDT 24
Peak memory 221720 kb
Host smart-77592e7b-b44c-4d3e-a122-77a37a4ab5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865201439 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.865201439
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.2680236793
Short name T732
Test name
Test status
Simulation time 35636018 ps
CPU time 1.29 seconds
Started Jul 22 05:44:39 PM PDT 24
Finished Jul 22 05:44:41 PM PDT 24
Peak memory 217620 kb
Host smart-ebbd0f16-b01b-404e-9f12-e9c2bed2c033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680236793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2680236793
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.2247973687
Short name T904
Test name
Test status
Simulation time 51937475 ps
CPU time 1.15 seconds
Started Jul 22 05:44:38 PM PDT 24
Finished Jul 22 05:44:40 PM PDT 24
Peak memory 217444 kb
Host smart-01df2f3c-19c2-44c0-a3fa-b511b5885e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247973687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.2247973687
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.2391401070
Short name T726
Test name
Test status
Simulation time 95250104 ps
CPU time 1.26 seconds
Started Jul 22 05:44:39 PM PDT 24
Finished Jul 22 05:44:42 PM PDT 24
Peak memory 220868 kb
Host smart-c878d53c-5a26-43b1-870e-afbe06544e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391401070 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.2391401070
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.2528318789
Short name T373
Test name
Test status
Simulation time 61146504 ps
CPU time 1.02 seconds
Started Jul 22 05:44:39 PM PDT 24
Finished Jul 22 05:44:41 PM PDT 24
Peak memory 219040 kb
Host smart-e3345c6f-3e03-4fea-b030-6e002cb386d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528318789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2528318789
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.3504782852
Short name T221
Test name
Test status
Simulation time 42216626 ps
CPU time 1.18 seconds
Started Jul 22 05:44:39 PM PDT 24
Finished Jul 22 05:44:42 PM PDT 24
Peak memory 220528 kb
Host smart-e0dca418-dbfc-45c2-9736-e635d931259a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504782852 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.3504782852
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.883149201
Short name T388
Test name
Test status
Simulation time 70645083 ps
CPU time 1.31 seconds
Started Jul 22 05:44:46 PM PDT 24
Finished Jul 22 05:44:48 PM PDT 24
Peak memory 218676 kb
Host smart-00a83e38-0799-403a-bf83-e517e06dbb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883149201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.883149201
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.43255488
Short name T191
Test name
Test status
Simulation time 100818613 ps
CPU time 1.28 seconds
Started Jul 22 05:44:43 PM PDT 24
Finished Jul 22 05:44:45 PM PDT 24
Peak memory 216060 kb
Host smart-f977e9f1-1076-4710-b589-02478656650c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43255488 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.43255488
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.3950114172
Short name T806
Test name
Test status
Simulation time 72477954 ps
CPU time 2.72 seconds
Started Jul 22 05:44:43 PM PDT 24
Finished Jul 22 05:44:47 PM PDT 24
Peak memory 220696 kb
Host smart-4ae12d86-c543-43e8-9694-bb6894a1a6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950114172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3950114172
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.822038621
Short name T619
Test name
Test status
Simulation time 102430901 ps
CPU time 1.23 seconds
Started Jul 22 05:44:39 PM PDT 24
Finished Jul 22 05:44:41 PM PDT 24
Peak memory 221136 kb
Host smart-0ba6e7fa-a8ce-4ea1-a607-56601e7aaa26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822038621 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.822038621
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/198.edn_alert.2100990535
Short name T529
Test name
Test status
Simulation time 137096676 ps
CPU time 1.09 seconds
Started Jul 22 05:44:38 PM PDT 24
Finished Jul 22 05:44:40 PM PDT 24
Peak memory 220312 kb
Host smart-e84898cf-a88f-4085-829b-8fa2b3023d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100990535 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.2100990535
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.3976385680
Short name T422
Test name
Test status
Simulation time 133157332 ps
CPU time 0.99 seconds
Started Jul 22 05:44:43 PM PDT 24
Finished Jul 22 05:44:45 PM PDT 24
Peak memory 217536 kb
Host smart-8717f43a-5f4f-495d-a3d6-ce0f0cae1d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976385680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.3976385680
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.774247843
Short name T297
Test name
Test status
Simulation time 109384137 ps
CPU time 1.09 seconds
Started Jul 22 05:44:44 PM PDT 24
Finished Jul 22 05:44:46 PM PDT 24
Peak memory 219156 kb
Host smart-8ea661c2-8267-47c0-bf79-56a7c6ad0526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774247843 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.774247843
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.873134164
Short name T687
Test name
Test status
Simulation time 38369739 ps
CPU time 1.5 seconds
Started Jul 22 05:44:37 PM PDT 24
Finished Jul 22 05:44:39 PM PDT 24
Peak memory 220256 kb
Host smart-a10b826d-5a71-4fa2-8e40-85aa3fd3fd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873134164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.873134164
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert_test.555567701
Short name T692
Test name
Test status
Simulation time 31131409 ps
CPU time 0.9 seconds
Started Jul 22 05:41:55 PM PDT 24
Finished Jul 22 05:41:57 PM PDT 24
Peak memory 206992 kb
Host smart-05cb8195-625f-4bc5-9cb5-18b6c9925d34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555567701 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.555567701
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.4127673979
Short name T746
Test name
Test status
Simulation time 34357500 ps
CPU time 0.87 seconds
Started Jul 22 05:41:51 PM PDT 24
Finished Jul 22 05:41:52 PM PDT 24
Peak memory 215728 kb
Host smart-746f19b3-7863-4267-8f44-62bf2a1a4f66
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127673979 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.4127673979
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_err.4019654981
Short name T208
Test name
Test status
Simulation time 35088991 ps
CPU time 0.9 seconds
Started Jul 22 05:41:56 PM PDT 24
Finished Jul 22 05:41:58 PM PDT 24
Peak memory 219792 kb
Host smart-be71c987-f932-4763-883e-5cba31482741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019654981 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.4019654981
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.3577790458
Short name T514
Test name
Test status
Simulation time 66404406 ps
CPU time 1.09 seconds
Started Jul 22 05:41:44 PM PDT 24
Finished Jul 22 05:41:45 PM PDT 24
Peak memory 220256 kb
Host smart-b6452ca0-188a-46f3-bfd1-9563e8fe5ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577790458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3577790458
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.961195569
Short name T102
Test name
Test status
Simulation time 21257466 ps
CPU time 1.06 seconds
Started Jul 22 05:44:42 PM PDT 24
Finished Jul 22 05:44:44 PM PDT 24
Peak memory 216156 kb
Host smart-c1a74bb0-3ad8-41be-9a2b-8418ff92280d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961195569 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.961195569
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.3931492242
Short name T845
Test name
Test status
Simulation time 25283284 ps
CPU time 0.93 seconds
Started Jul 22 05:41:44 PM PDT 24
Finished Jul 22 05:41:46 PM PDT 24
Peak memory 207424 kb
Host smart-cd4892bf-0627-4e62-93ea-6b7182e9ec63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931492242 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3931492242
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.729700210
Short name T56
Test name
Test status
Simulation time 469535745 ps
CPU time 7.91 seconds
Started Jul 22 05:41:54 PM PDT 24
Finished Jul 22 05:42:03 PM PDT 24
Peak memory 237728 kb
Host smart-87167ff2-952f-42ca-afc3-669d7e83e9bb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729700210 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.729700210
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.959005435
Short name T540
Test name
Test status
Simulation time 39685087 ps
CPU time 0.92 seconds
Started Jul 22 05:41:45 PM PDT 24
Finished Jul 22 05:41:47 PM PDT 24
Peak memory 215536 kb
Host smart-8935b046-a0c4-4b51-810b-aab12b81f009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959005435 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.959005435
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.258354852
Short name T438
Test name
Test status
Simulation time 119463221 ps
CPU time 1.7 seconds
Started Jul 22 05:41:50 PM PDT 24
Finished Jul 22 05:41:52 PM PDT 24
Peak memory 217720 kb
Host smart-17dec48c-1786-489d-bfff-1dbbfb85aea9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258354852 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.258354852
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1573122467
Short name T223
Test name
Test status
Simulation time 20942365071 ps
CPU time 480.09 seconds
Started Jul 22 05:41:45 PM PDT 24
Finished Jul 22 05:49:46 PM PDT 24
Peak memory 218884 kb
Host smart-c53f5000-868f-45cb-b02f-9abbc95039f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573122467 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1573122467
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.4275497229
Short name T431
Test name
Test status
Simulation time 25983243 ps
CPU time 1.22 seconds
Started Jul 22 05:42:29 PM PDT 24
Finished Jul 22 05:42:31 PM PDT 24
Peak memory 216028 kb
Host smart-cfc84c2e-f109-42a6-9997-f1d085f390f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275497229 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.4275497229
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.2509001456
Short name T526
Test name
Test status
Simulation time 12239970 ps
CPU time 0.86 seconds
Started Jul 22 05:42:37 PM PDT 24
Finished Jul 22 05:42:39 PM PDT 24
Peak memory 207096 kb
Host smart-a3dfa288-dc7a-4018-915f-bbbae8210062
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509001456 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2509001456
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.2697133261
Short name T445
Test name
Test status
Simulation time 12276516 ps
CPU time 0.93 seconds
Started Jul 22 05:42:31 PM PDT 24
Finished Jul 22 05:42:33 PM PDT 24
Peak memory 216864 kb
Host smart-6bab8316-f029-45d1-8755-6c804fad9bf8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697133261 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.2697133261
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_err.2719404523
Short name T122
Test name
Test status
Simulation time 24971572 ps
CPU time 1.01 seconds
Started Jul 22 05:42:25 PM PDT 24
Finished Jul 22 05:42:26 PM PDT 24
Peak memory 219884 kb
Host smart-1ebc311a-0f6e-4268-bf5c-db354b4f70f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719404523 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2719404523
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.1598552448
Short name T430
Test name
Test status
Simulation time 76607710 ps
CPU time 1.77 seconds
Started Jul 22 05:42:18 PM PDT 24
Finished Jul 22 05:42:20 PM PDT 24
Peak memory 220724 kb
Host smart-d0e1bb75-6ce1-4191-9fb9-5cd462c0ece9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598552448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1598552448
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.1915402576
Short name T607
Test name
Test status
Simulation time 32678399 ps
CPU time 0.89 seconds
Started Jul 22 05:42:29 PM PDT 24
Finished Jul 22 05:42:31 PM PDT 24
Peak memory 215956 kb
Host smart-73c95929-9c35-40f0-bb33-117775787c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915402576 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1915402576
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.409323023
Short name T374
Test name
Test status
Simulation time 45862352 ps
CPU time 0.95 seconds
Started Jul 22 05:42:26 PM PDT 24
Finished Jul 22 05:42:27 PM PDT 24
Peak memory 215576 kb
Host smart-8a6ef337-e2e5-4dec-9ace-7a2ed20a9c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409323023 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.409323023
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.111115498
Short name T559
Test name
Test status
Simulation time 291203727 ps
CPU time 5.54 seconds
Started Jul 22 05:42:29 PM PDT 24
Finished Jul 22 05:42:36 PM PDT 24
Peak memory 217568 kb
Host smart-03cec74d-1639-4fe9-8f66-1e97a823f0fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111115498 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.111115498
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.1415014469
Short name T471
Test name
Test status
Simulation time 27417713925 ps
CPU time 166.51 seconds
Started Jul 22 05:42:19 PM PDT 24
Finished Jul 22 05:45:06 PM PDT 24
Peak memory 217016 kb
Host smart-388a1036-6c8b-4758-8670-1e440a8c8e1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415014469 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.1415014469
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/201.edn_genbits.377737644
Short name T580
Test name
Test status
Simulation time 94318770 ps
CPU time 1.17 seconds
Started Jul 22 05:44:44 PM PDT 24
Finished Jul 22 05:44:47 PM PDT 24
Peak memory 218860 kb
Host smart-ac5b32ea-21fc-46b3-b6e3-ee2b399736b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377737644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.377737644
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.3030066816
Short name T498
Test name
Test status
Simulation time 139505195 ps
CPU time 1.38 seconds
Started Jul 22 05:44:41 PM PDT 24
Finished Jul 22 05:44:43 PM PDT 24
Peak memory 219232 kb
Host smart-ca78aa62-3bd2-4e03-97ea-1a9f14b7fe30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030066816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3030066816
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.1109059275
Short name T509
Test name
Test status
Simulation time 67774552 ps
CPU time 2.5 seconds
Started Jul 22 05:44:38 PM PDT 24
Finished Jul 22 05:44:41 PM PDT 24
Peak memory 219264 kb
Host smart-216bb31f-563e-45da-9c2d-f81cac6875c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109059275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.1109059275
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.717119564
Short name T491
Test name
Test status
Simulation time 74362447 ps
CPU time 1.41 seconds
Started Jul 22 05:44:39 PM PDT 24
Finished Jul 22 05:44:41 PM PDT 24
Peak memory 218812 kb
Host smart-6497036b-26c4-464c-9149-fde2a00a0152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717119564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.717119564
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.3630575087
Short name T991
Test name
Test status
Simulation time 43761752 ps
CPU time 1.56 seconds
Started Jul 22 05:44:38 PM PDT 24
Finished Jul 22 05:44:40 PM PDT 24
Peak memory 218868 kb
Host smart-eddd5099-2c2e-44b1-986a-03ea4da3fb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630575087 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.3630575087
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.1733914415
Short name T677
Test name
Test status
Simulation time 48238152 ps
CPU time 1.5 seconds
Started Jul 22 05:44:44 PM PDT 24
Finished Jul 22 05:44:47 PM PDT 24
Peak memory 215780 kb
Host smart-5296cc8f-3061-49c5-8167-dab943fd929c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733914415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.1733914415
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.2883047736
Short name T322
Test name
Test status
Simulation time 33977739 ps
CPU time 1.62 seconds
Started Jul 22 05:44:42 PM PDT 24
Finished Jul 22 05:44:44 PM PDT 24
Peak memory 220316 kb
Host smart-115bc346-d95a-4c8f-9e43-3b83815a3ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883047736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.2883047736
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3387904109
Short name T917
Test name
Test status
Simulation time 51531060 ps
CPU time 1.24 seconds
Started Jul 22 05:42:35 PM PDT 24
Finished Jul 22 05:42:37 PM PDT 24
Peak memory 219464 kb
Host smart-717172c1-1f99-48f1-942d-fc616e2af684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387904109 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3387904109
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.4175216772
Short name T666
Test name
Test status
Simulation time 15469550 ps
CPU time 0.94 seconds
Started Jul 22 05:42:28 PM PDT 24
Finished Jul 22 05:42:30 PM PDT 24
Peak memory 207032 kb
Host smart-b727fbae-aeda-404d-b97c-c94bd67c93fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175216772 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.4175216772
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.1766357115
Short name T841
Test name
Test status
Simulation time 32113001 ps
CPU time 0.85 seconds
Started Jul 22 05:42:30 PM PDT 24
Finished Jul 22 05:42:31 PM PDT 24
Peak memory 216800 kb
Host smart-6283da02-3c76-453f-8cf5-6c09c9ab96fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766357115 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1766357115
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_err.488417070
Short name T721
Test name
Test status
Simulation time 51208379 ps
CPU time 1.05 seconds
Started Jul 22 05:42:31 PM PDT 24
Finished Jul 22 05:42:33 PM PDT 24
Peak memory 219172 kb
Host smart-59fb8c95-b2f9-4b9d-af9c-f46e0a520a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488417070 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.488417070
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.721782724
Short name T567
Test name
Test status
Simulation time 33398655 ps
CPU time 1.46 seconds
Started Jul 22 05:42:30 PM PDT 24
Finished Jul 22 05:42:32 PM PDT 24
Peak memory 218788 kb
Host smart-09409465-7abf-4812-abd6-16f3b18f910d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721782724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.721782724
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.1556164310
Short name T581
Test name
Test status
Simulation time 35271930 ps
CPU time 0.99 seconds
Started Jul 22 05:42:31 PM PDT 24
Finished Jul 22 05:42:33 PM PDT 24
Peak memory 224360 kb
Host smart-ba4e1494-dd4b-45a4-8cb9-f90e82333424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556164310 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.1556164310
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.1662220563
Short name T881
Test name
Test status
Simulation time 16984735 ps
CPU time 0.95 seconds
Started Jul 22 05:42:31 PM PDT 24
Finished Jul 22 05:42:33 PM PDT 24
Peak memory 215628 kb
Host smart-8e242c0b-3c29-40a6-be6f-abf0b1e4b5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662220563 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.1662220563
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.3475420899
Short name T754
Test name
Test status
Simulation time 315901560 ps
CPU time 6.55 seconds
Started Jul 22 05:42:36 PM PDT 24
Finished Jul 22 05:42:43 PM PDT 24
Peak memory 215664 kb
Host smart-cae7bc02-2b41-4ccc-b392-d8af81cbdf03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475420899 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.3475420899
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.1212765589
Short name T828
Test name
Test status
Simulation time 12309136123 ps
CPU time 272.86 seconds
Started Jul 22 05:42:29 PM PDT 24
Finished Jul 22 05:47:03 PM PDT 24
Peak memory 218512 kb
Host smart-56f1d08f-00e2-468f-b4be-797c7f2b1afe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212765589 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.1212765589
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.1479262475
Short name T992
Test name
Test status
Simulation time 123021233 ps
CPU time 1.12 seconds
Started Jul 22 05:44:45 PM PDT 24
Finished Jul 22 05:44:47 PM PDT 24
Peak memory 217592 kb
Host smart-655346e3-adbd-4be4-936b-8eaf3943956f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479262475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.1479262475
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.2865220244
Short name T691
Test name
Test status
Simulation time 36751702 ps
CPU time 1.28 seconds
Started Jul 22 05:44:38 PM PDT 24
Finished Jul 22 05:44:40 PM PDT 24
Peak memory 217444 kb
Host smart-2544f5bf-a043-4d68-b598-d5aac2b5f0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865220244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.2865220244
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.3467652396
Short name T199
Test name
Test status
Simulation time 96988380 ps
CPU time 1.4 seconds
Started Jul 22 05:44:42 PM PDT 24
Finished Jul 22 05:44:44 PM PDT 24
Peak memory 218984 kb
Host smart-8ca1b3f5-0c34-4d8f-a2a7-2d944ed902eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467652396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.3467652396
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.1650423007
Short name T848
Test name
Test status
Simulation time 48032450 ps
CPU time 1.15 seconds
Started Jul 22 05:44:39 PM PDT 24
Finished Jul 22 05:44:41 PM PDT 24
Peak memory 217688 kb
Host smart-4c90d943-c24c-4bd7-8cc2-b812cb91b29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650423007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.1650423007
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.4188503065
Short name T693
Test name
Test status
Simulation time 97976860 ps
CPU time 1.13 seconds
Started Jul 22 05:44:39 PM PDT 24
Finished Jul 22 05:44:41 PM PDT 24
Peak memory 217532 kb
Host smart-23a11be9-d059-4bf7-b33d-9dad6c20e649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188503065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.4188503065
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.797663702
Short name T863
Test name
Test status
Simulation time 43163991 ps
CPU time 1.52 seconds
Started Jul 22 05:44:40 PM PDT 24
Finished Jul 22 05:44:43 PM PDT 24
Peak memory 218776 kb
Host smart-e8d85597-e957-4cb2-b58e-dd23e424580d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797663702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.797663702
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.1729682058
Short name T319
Test name
Test status
Simulation time 62739936 ps
CPU time 1.22 seconds
Started Jul 22 05:44:43 PM PDT 24
Finished Jul 22 05:44:45 PM PDT 24
Peak memory 217772 kb
Host smart-93a5b402-802a-473c-8655-6816b6ba3fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729682058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1729682058
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.4203176729
Short name T641
Test name
Test status
Simulation time 206788781 ps
CPU time 0.98 seconds
Started Jul 22 05:44:43 PM PDT 24
Finished Jul 22 05:44:45 PM PDT 24
Peak memory 217616 kb
Host smart-9a98513d-0607-4f43-a174-2e2553fc6464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203176729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.4203176729
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.2591450000
Short name T714
Test name
Test status
Simulation time 30124952 ps
CPU time 1.22 seconds
Started Jul 22 05:44:40 PM PDT 24
Finished Jul 22 05:44:42 PM PDT 24
Peak memory 217544 kb
Host smart-40cefc3d-823d-4f8c-9ec3-9c1512be98c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591450000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2591450000
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.687792117
Short name T481
Test name
Test status
Simulation time 41661804 ps
CPU time 1.59 seconds
Started Jul 22 05:44:42 PM PDT 24
Finished Jul 22 05:44:45 PM PDT 24
Peak memory 218860 kb
Host smart-70bae369-a861-4ed0-b7d9-0cf893451a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687792117 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.687792117
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.2484931399
Short name T496
Test name
Test status
Simulation time 97391986 ps
CPU time 1.27 seconds
Started Jul 22 05:42:35 PM PDT 24
Finished Jul 22 05:42:37 PM PDT 24
Peak memory 218948 kb
Host smart-6012f970-e3b7-404e-9e75-b7fb7f75c5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484931399 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.2484931399
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.1516416683
Short name T413
Test name
Test status
Simulation time 118979255 ps
CPU time 0.95 seconds
Started Jul 22 05:42:34 PM PDT 24
Finished Jul 22 05:42:35 PM PDT 24
Peak memory 215396 kb
Host smart-8f88239c-f990-4b07-b382-74da7c300677
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516416683 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1516416683
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.1453473576
Short name T554
Test name
Test status
Simulation time 40136642 ps
CPU time 0.83 seconds
Started Jul 22 05:42:28 PM PDT 24
Finished Jul 22 05:42:30 PM PDT 24
Peak memory 216720 kb
Host smart-81e3375b-bc79-4631-aa3c-6e282ef68b0d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453473576 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.1453473576
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.883263546
Short name T377
Test name
Test status
Simulation time 56401883 ps
CPU time 1.27 seconds
Started Jul 22 05:42:37 PM PDT 24
Finished Jul 22 05:42:38 PM PDT 24
Peak memory 217280 kb
Host smart-c82c8bb5-cbfd-4a0b-98c8-42b89d2d88eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883263546 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_di
sable_auto_req_mode.883263546
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.3598621217
Short name T953
Test name
Test status
Simulation time 19646450 ps
CPU time 1.09 seconds
Started Jul 22 05:42:35 PM PDT 24
Finished Jul 22 05:42:37 PM PDT 24
Peak memory 218880 kb
Host smart-0631cf72-7e72-4402-ad0f-d9eef09adcdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598621217 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.3598621217
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.2607288885
Short name T432
Test name
Test status
Simulation time 39003081 ps
CPU time 1.47 seconds
Started Jul 22 05:42:33 PM PDT 24
Finished Jul 22 05:42:36 PM PDT 24
Peak memory 220480 kb
Host smart-55cd5afb-830f-4ce4-9839-6099ffb6d9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607288885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2607288885
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.725260295
Short name T32
Test name
Test status
Simulation time 31541429 ps
CPU time 0.97 seconds
Started Jul 22 05:42:36 PM PDT 24
Finished Jul 22 05:42:38 PM PDT 24
Peak memory 216128 kb
Host smart-ad0292af-0d44-4e0e-af59-9605e7e19a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725260295 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.725260295
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.1662926473
Short name T634
Test name
Test status
Simulation time 34792291 ps
CPU time 0.87 seconds
Started Jul 22 05:42:34 PM PDT 24
Finished Jul 22 05:42:36 PM PDT 24
Peak memory 215608 kb
Host smart-b58d03c0-7aaf-4cda-878a-29c6d0098b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662926473 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.1662926473
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2265373056
Short name T890
Test name
Test status
Simulation time 105572042 ps
CPU time 1.64 seconds
Started Jul 22 05:42:28 PM PDT 24
Finished Jul 22 05:42:31 PM PDT 24
Peak memory 215688 kb
Host smart-ae315e6e-8c7c-4784-b98d-b413b830c6c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265373056 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2265373056
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3451386766
Short name T399
Test name
Test status
Simulation time 37902457035 ps
CPU time 840.79 seconds
Started Jul 22 05:42:30 PM PDT 24
Finished Jul 22 05:56:32 PM PDT 24
Peak memory 224004 kb
Host smart-26fc97aa-6a36-496a-986c-42f326b62693
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451386766 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3451386766
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.3017941518
Short name T339
Test name
Test status
Simulation time 30639078 ps
CPU time 1.24 seconds
Started Jul 22 05:44:43 PM PDT 24
Finished Jul 22 05:44:45 PM PDT 24
Peak memory 217708 kb
Host smart-959bf9e3-5ea3-456c-825d-d4aea1e73b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017941518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.3017941518
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.2693937585
Short name T809
Test name
Test status
Simulation time 49275863 ps
CPU time 1.18 seconds
Started Jul 22 05:44:48 PM PDT 24
Finished Jul 22 05:44:50 PM PDT 24
Peak memory 217596 kb
Host smart-feba93d5-2764-4936-92cc-e398c613dd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693937585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.2693937585
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.679319688
Short name T69
Test name
Test status
Simulation time 61336149 ps
CPU time 1.01 seconds
Started Jul 22 05:44:44 PM PDT 24
Finished Jul 22 05:44:46 PM PDT 24
Peak memory 217672 kb
Host smart-c7d5c900-5563-44e4-ae2d-1884707b6d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679319688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.679319688
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.1290778070
Short name T416
Test name
Test status
Simulation time 82671699 ps
CPU time 0.99 seconds
Started Jul 22 05:44:43 PM PDT 24
Finished Jul 22 05:44:45 PM PDT 24
Peak memory 217504 kb
Host smart-467b301d-cb50-410b-80ab-eae5215702ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290778070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.1290778070
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.2846748553
Short name T759
Test name
Test status
Simulation time 250683441 ps
CPU time 1.26 seconds
Started Jul 22 05:44:43 PM PDT 24
Finished Jul 22 05:44:46 PM PDT 24
Peak memory 219800 kb
Host smart-1f4881cf-3213-4bac-b1e1-dd0bcb88e4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846748553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.2846748553
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.1943882544
Short name T797
Test name
Test status
Simulation time 47905481 ps
CPU time 1.18 seconds
Started Jul 22 05:44:43 PM PDT 24
Finished Jul 22 05:44:46 PM PDT 24
Peak memory 218952 kb
Host smart-1b26a364-4283-48bd-8105-65524234abac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943882544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.1943882544
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.3678749708
Short name T474
Test name
Test status
Simulation time 43366460 ps
CPU time 1.57 seconds
Started Jul 22 05:44:45 PM PDT 24
Finished Jul 22 05:44:47 PM PDT 24
Peak memory 218768 kb
Host smart-8b86d5d3-0c68-43e7-99e5-cc738bad08d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678749708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3678749708
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.1186634236
Short name T323
Test name
Test status
Simulation time 38912950 ps
CPU time 1.39 seconds
Started Jul 22 05:44:40 PM PDT 24
Finished Jul 22 05:44:42 PM PDT 24
Peak memory 218800 kb
Host smart-9777bc96-f2c1-48cf-886f-4572c53667ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186634236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.1186634236
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.1308742194
Short name T965
Test name
Test status
Simulation time 53672985 ps
CPU time 2 seconds
Started Jul 22 05:44:45 PM PDT 24
Finished Jul 22 05:44:48 PM PDT 24
Peak memory 218844 kb
Host smart-036e8b6d-3c57-44c3-bdae-f4ea0f43f20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308742194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1308742194
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.2637126597
Short name T889
Test name
Test status
Simulation time 31355010 ps
CPU time 1.37 seconds
Started Jul 22 05:42:31 PM PDT 24
Finished Jul 22 05:42:34 PM PDT 24
Peak memory 216084 kb
Host smart-1fb67ba3-7a21-4811-9a4e-85eaeb93db39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637126597 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.2637126597
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.411190298
Short name T424
Test name
Test status
Simulation time 35730318 ps
CPU time 0.95 seconds
Started Jul 22 05:42:31 PM PDT 24
Finished Jul 22 05:42:33 PM PDT 24
Peak memory 207012 kb
Host smart-485a8c7c-955e-4cf1-bbac-3fb2a1943d0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411190298 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.411190298
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.2868264636
Short name T347
Test name
Test status
Simulation time 10892795 ps
CPU time 0.9 seconds
Started Jul 22 05:42:37 PM PDT 24
Finished Jul 22 05:42:38 PM PDT 24
Peak memory 216216 kb
Host smart-9afbef2c-f161-4b8f-8d38-55154e8f9c63
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868264636 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2868264636
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.1184077922
Short name T469
Test name
Test status
Simulation time 32979970 ps
CPU time 1.21 seconds
Started Jul 22 05:42:33 PM PDT 24
Finished Jul 22 05:42:36 PM PDT 24
Peak memory 218844 kb
Host smart-ea96ba97-d823-47f0-9361-a47c903ba9b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184077922 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.1184077922
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.614114646
Short name T138
Test name
Test status
Simulation time 24550289 ps
CPU time 1.21 seconds
Started Jul 22 05:42:32 PM PDT 24
Finished Jul 22 05:42:34 PM PDT 24
Peak memory 219916 kb
Host smart-03ff683b-624f-45b9-a754-cad2fb3d1bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614114646 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.614114646
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.3892820154
Short name T729
Test name
Test status
Simulation time 781680027 ps
CPU time 4.51 seconds
Started Jul 22 05:42:34 PM PDT 24
Finished Jul 22 05:42:39 PM PDT 24
Peak memory 218932 kb
Host smart-99fa44ad-79c1-44c3-8bdd-f8002a4442b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892820154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3892820154
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.2882989021
Short name T749
Test name
Test status
Simulation time 39585308 ps
CPU time 0.94 seconds
Started Jul 22 05:42:36 PM PDT 24
Finished Jul 22 05:42:38 PM PDT 24
Peak memory 215696 kb
Host smart-7ae831b1-8429-4142-9c08-20906f052a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882989021 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.2882989021
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.2782048290
Short name T916
Test name
Test status
Simulation time 52209097 ps
CPU time 0.93 seconds
Started Jul 22 05:42:37 PM PDT 24
Finished Jul 22 05:42:39 PM PDT 24
Peak memory 215612 kb
Host smart-bce92e31-ec36-46d7-86ab-eb957619308c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782048290 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.2782048290
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.440083822
Short name T502
Test name
Test status
Simulation time 380168834 ps
CPU time 4.22 seconds
Started Jul 22 05:42:31 PM PDT 24
Finished Jul 22 05:42:36 PM PDT 24
Peak memory 217676 kb
Host smart-ebcb8ee2-1a31-4b51-8ebf-44ee1e650044
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440083822 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.440083822
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.3938562611
Short name T585
Test name
Test status
Simulation time 184655838633 ps
CPU time 1448.28 seconds
Started Jul 22 05:42:36 PM PDT 24
Finished Jul 22 06:06:45 PM PDT 24
Peak memory 226744 kb
Host smart-75217739-8ffc-4d8f-8323-f05d4c18d712
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938562611 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.3938562611
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.2035163295
Short name T334
Test name
Test status
Simulation time 39258128 ps
CPU time 1.62 seconds
Started Jul 22 05:44:46 PM PDT 24
Finished Jul 22 05:44:48 PM PDT 24
Peak memory 218848 kb
Host smart-847e3411-980d-4fc9-8070-225297b8ba46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035163295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2035163295
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.3896876204
Short name T77
Test name
Test status
Simulation time 25623935 ps
CPU time 1.13 seconds
Started Jul 22 05:44:46 PM PDT 24
Finished Jul 22 05:44:47 PM PDT 24
Peak memory 217488 kb
Host smart-574677e1-143b-4a23-85d9-dfe472dbf155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896876204 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3896876204
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.1797787049
Short name T874
Test name
Test status
Simulation time 189522062 ps
CPU time 3.46 seconds
Started Jul 22 05:44:46 PM PDT 24
Finished Jul 22 05:44:50 PM PDT 24
Peak memory 220472 kb
Host smart-ee6dd8f9-9380-435f-98d7-ccea3ec83442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797787049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.1797787049
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.3319739307
Short name T823
Test name
Test status
Simulation time 265539222 ps
CPU time 1.32 seconds
Started Jul 22 05:44:44 PM PDT 24
Finished Jul 22 05:44:47 PM PDT 24
Peak memory 217536 kb
Host smart-c51fbffc-d3d4-4262-a2a6-75675ebb8cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319739307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3319739307
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.1204533083
Short name T642
Test name
Test status
Simulation time 35512574 ps
CPU time 1.1 seconds
Started Jul 22 05:44:57 PM PDT 24
Finished Jul 22 05:44:59 PM PDT 24
Peak memory 217592 kb
Host smart-5faa7d7a-7a53-4113-a649-c03769877ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204533083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.1204533083
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.552678751
Short name T915
Test name
Test status
Simulation time 88045013 ps
CPU time 2.92 seconds
Started Jul 22 05:44:51 PM PDT 24
Finished Jul 22 05:44:54 PM PDT 24
Peak memory 220788 kb
Host smart-ac510df6-da2a-458d-ad79-9d45beed3c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552678751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.552678751
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.517004613
Short name T427
Test name
Test status
Simulation time 25413761 ps
CPU time 1.21 seconds
Started Jul 22 05:44:52 PM PDT 24
Finished Jul 22 05:44:53 PM PDT 24
Peak memory 220172 kb
Host smart-ab14e480-dfd9-4fca-bb1f-b143d72591ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517004613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.517004613
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.3859309212
Short name T813
Test name
Test status
Simulation time 110449146 ps
CPU time 1.51 seconds
Started Jul 22 05:45:16 PM PDT 24
Finished Jul 22 05:45:18 PM PDT 24
Peak memory 219188 kb
Host smart-c0e945f4-cf83-424d-8a31-f906cb860104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859309212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.3859309212
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.4204991056
Short name T311
Test name
Test status
Simulation time 54691642 ps
CPU time 1.7 seconds
Started Jul 22 05:44:52 PM PDT 24
Finished Jul 22 05:44:55 PM PDT 24
Peak memory 219552 kb
Host smart-d2d80432-d36c-4685-9dc9-e355b4fe5635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204991056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.4204991056
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.3543218936
Short name T932
Test name
Test status
Simulation time 69236053 ps
CPU time 1.64 seconds
Started Jul 22 05:44:55 PM PDT 24
Finished Jul 22 05:44:57 PM PDT 24
Peak memory 220508 kb
Host smart-c2d97e21-2aa8-4a0e-84eb-2df6b444a43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543218936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.3543218936
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert_test.796422802
Short name T962
Test name
Test status
Simulation time 36458588 ps
CPU time 0.82 seconds
Started Jul 22 05:42:33 PM PDT 24
Finished Jul 22 05:42:35 PM PDT 24
Peak memory 207004 kb
Host smart-02f0ef8f-10e0-4c7e-803e-13fcf7ed3b70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796422802 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.796422802
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.2378179855
Short name T818
Test name
Test status
Simulation time 82611868 ps
CPU time 0.88 seconds
Started Jul 22 05:42:36 PM PDT 24
Finished Jul 22 05:42:37 PM PDT 24
Peak memory 216584 kb
Host smart-90925256-f5b4-48f0-a65f-d29c958b98e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378179855 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.2378179855
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.2761032191
Short name T128
Test name
Test status
Simulation time 35999647 ps
CPU time 1.03 seconds
Started Jul 22 05:42:29 PM PDT 24
Finished Jul 22 05:42:31 PM PDT 24
Peak memory 219032 kb
Host smart-a9a83a1d-2728-4578-ac37-6bff3fbeb798
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761032191 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.2761032191
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.294235975
Short name T761
Test name
Test status
Simulation time 24917626 ps
CPU time 0.99 seconds
Started Jul 22 05:42:34 PM PDT 24
Finished Jul 22 05:42:36 PM PDT 24
Peak memory 219708 kb
Host smart-3a8da764-6e45-4b4f-82bb-08c39b1aed99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294235975 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.294235975
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.2440629079
Short name T727
Test name
Test status
Simulation time 46933845 ps
CPU time 1.29 seconds
Started Jul 22 05:42:32 PM PDT 24
Finished Jul 22 05:42:34 PM PDT 24
Peak memory 217524 kb
Host smart-63a9b825-9ee2-4ca4-be7f-0da225f99519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440629079 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.2440629079
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.314189414
Short name T707
Test name
Test status
Simulation time 36301821 ps
CPU time 1.03 seconds
Started Jul 22 05:42:32 PM PDT 24
Finished Jul 22 05:42:34 PM PDT 24
Peak memory 224356 kb
Host smart-587fede0-542c-486a-a774-6833c5b3cbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314189414 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.314189414
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.1915591828
Short name T507
Test name
Test status
Simulation time 24092077 ps
CPU time 0.92 seconds
Started Jul 22 05:42:31 PM PDT 24
Finished Jul 22 05:42:34 PM PDT 24
Peak memory 207456 kb
Host smart-2c4d9ee9-f15d-435b-a0f7-6d7557449918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915591828 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.1915591828
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.127401613
Short name T237
Test name
Test status
Simulation time 580064889 ps
CPU time 3.03 seconds
Started Jul 22 05:42:31 PM PDT 24
Finished Jul 22 05:42:35 PM PDT 24
Peak memory 217600 kb
Host smart-abf2b104-3755-4d66-8742-3371bbd0d199
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127401613 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.127401613
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.3070473758
Short name T34
Test name
Test status
Simulation time 31411842063 ps
CPU time 701.84 seconds
Started Jul 22 05:42:37 PM PDT 24
Finished Jul 22 05:54:19 PM PDT 24
Peak memory 217840 kb
Host smart-674cecd0-5cd6-443e-8180-1ab6789dad07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070473758 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.3070473758
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.1151659077
Short name T398
Test name
Test status
Simulation time 80827641 ps
CPU time 1.08 seconds
Started Jul 22 05:44:58 PM PDT 24
Finished Jul 22 05:44:59 PM PDT 24
Peak memory 217516 kb
Host smart-80047995-07fd-4baf-aaae-92746de50abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151659077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.1151659077
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.603262838
Short name T561
Test name
Test status
Simulation time 81394228 ps
CPU time 1.4 seconds
Started Jul 22 05:44:56 PM PDT 24
Finished Jul 22 05:44:58 PM PDT 24
Peak memory 219132 kb
Host smart-a0b7be2f-ac18-43cf-b9a1-28715f602ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603262838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.603262838
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1348128325
Short name T690
Test name
Test status
Simulation time 52387268 ps
CPU time 1.14 seconds
Started Jul 22 05:44:52 PM PDT 24
Finished Jul 22 05:44:54 PM PDT 24
Peak memory 217688 kb
Host smart-cc5b9153-3ac0-4d93-9276-08335f0d3353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348128325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1348128325
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.12149112
Short name T46
Test name
Test status
Simulation time 74133384 ps
CPU time 1.45 seconds
Started Jul 22 05:44:55 PM PDT 24
Finished Jul 22 05:44:57 PM PDT 24
Peak memory 217748 kb
Host smart-535d1ff4-e608-4947-8e6a-65742ca522a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12149112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.12149112
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.2859298343
Short name T625
Test name
Test status
Simulation time 65534971 ps
CPU time 1.12 seconds
Started Jul 22 05:44:58 PM PDT 24
Finished Jul 22 05:45:00 PM PDT 24
Peak memory 215564 kb
Host smart-858ab075-efc4-4d88-9dc5-f66fd9a32123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859298343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.2859298343
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.4081088210
Short name T405
Test name
Test status
Simulation time 111367521 ps
CPU time 1.54 seconds
Started Jul 22 05:44:51 PM PDT 24
Finished Jul 22 05:44:53 PM PDT 24
Peak memory 219148 kb
Host smart-9240d2b2-6322-4373-8e93-27e396ee8b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081088210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.4081088210
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.917627130
Short name T510
Test name
Test status
Simulation time 254194340 ps
CPU time 3.5 seconds
Started Jul 22 05:44:53 PM PDT 24
Finished Jul 22 05:44:58 PM PDT 24
Peak memory 220564 kb
Host smart-0292c65e-7ca8-476f-a341-2608ac77d1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917627130 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.917627130
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.1497307324
Short name T604
Test name
Test status
Simulation time 68825018 ps
CPU time 1.34 seconds
Started Jul 22 05:44:57 PM PDT 24
Finished Jul 22 05:44:59 PM PDT 24
Peak memory 219044 kb
Host smart-eafafa1e-f6bb-4515-b320-31b77ce40608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497307324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1497307324
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.3666094210
Short name T752
Test name
Test status
Simulation time 37925336 ps
CPU time 1.59 seconds
Started Jul 22 05:44:55 PM PDT 24
Finished Jul 22 05:44:58 PM PDT 24
Peak memory 219096 kb
Host smart-e625bda7-10f9-4b0b-ac58-c8f0700fed68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666094210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.3666094210
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.288787948
Short name T495
Test name
Test status
Simulation time 110182577 ps
CPU time 1.69 seconds
Started Jul 22 05:44:51 PM PDT 24
Finished Jul 22 05:44:53 PM PDT 24
Peak memory 219020 kb
Host smart-b807cf8f-1e1e-4fb7-8e7e-3cbfeea009b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288787948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.288787948
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.58529229
Short name T475
Test name
Test status
Simulation time 32310854 ps
CPU time 1.35 seconds
Started Jul 22 05:42:31 PM PDT 24
Finished Jul 22 05:42:34 PM PDT 24
Peak memory 220084 kb
Host smart-4779a932-aa55-46b9-9d29-03cfa3b9626c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58529229 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.58529229
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.672961572
Short name T855
Test name
Test status
Simulation time 12150828 ps
CPU time 0.88 seconds
Started Jul 22 05:42:49 PM PDT 24
Finished Jul 22 05:42:51 PM PDT 24
Peak memory 207024 kb
Host smart-60989044-2559-4bb7-a164-d3c90bcdbfa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672961572 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.672961572
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.1508021220
Short name T350
Test name
Test status
Simulation time 27391089 ps
CPU time 1.04 seconds
Started Jul 22 05:42:54 PM PDT 24
Finished Jul 22 05:42:56 PM PDT 24
Peak memory 218632 kb
Host smart-cb96d5c3-b1eb-4a45-b66f-ccf6ec23a09c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508021220 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.1508021220
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.245092043
Short name T789
Test name
Test status
Simulation time 18325883 ps
CPU time 1.05 seconds
Started Jul 22 05:42:31 PM PDT 24
Finished Jul 22 05:42:33 PM PDT 24
Peak memory 218636 kb
Host smart-88f27d7e-2b00-4c82-a787-f2cb570bd08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245092043 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.245092043
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.3851768253
Short name T312
Test name
Test status
Simulation time 49313686 ps
CPU time 1.47 seconds
Started Jul 22 05:42:34 PM PDT 24
Finished Jul 22 05:42:36 PM PDT 24
Peak memory 218252 kb
Host smart-03eb287e-9f6d-4e26-a996-2cda3a827518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851768253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3851768253
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.940269796
Short name T608
Test name
Test status
Simulation time 33627608 ps
CPU time 0.95 seconds
Started Jul 22 05:42:30 PM PDT 24
Finished Jul 22 05:42:31 PM PDT 24
Peak memory 215584 kb
Host smart-727759d6-d2b5-46f2-84ab-c867c2e06673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940269796 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.940269796
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.4174095211
Short name T582
Test name
Test status
Simulation time 48518254 ps
CPU time 0.91 seconds
Started Jul 22 05:42:31 PM PDT 24
Finished Jul 22 05:42:33 PM PDT 24
Peak memory 215608 kb
Host smart-d2870423-ee42-4554-8b5f-927708c331e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174095211 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.4174095211
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.1908975085
Short name T466
Test name
Test status
Simulation time 113752393 ps
CPU time 1.26 seconds
Started Jul 22 05:42:31 PM PDT 24
Finished Jul 22 05:42:33 PM PDT 24
Peak memory 215532 kb
Host smart-c7677fe7-4a4f-4652-bb85-ecdccabddc04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908975085 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1908975085
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.3540065260
Short name T231
Test name
Test status
Simulation time 119642121311 ps
CPU time 2527.16 seconds
Started Jul 22 05:42:35 PM PDT 24
Finished Jul 22 06:24:43 PM PDT 24
Peak memory 229400 kb
Host smart-4f99ab6d-9562-4641-9944-7c14cc8749b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540065260 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.3540065260
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.1639744380
Short name T810
Test name
Test status
Simulation time 42915630 ps
CPU time 1.59 seconds
Started Jul 22 05:44:53 PM PDT 24
Finished Jul 22 05:44:55 PM PDT 24
Peak memory 218852 kb
Host smart-3058566c-d578-4a16-917d-ce2f308d4f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639744380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.1639744380
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.3130728870
Short name T45
Test name
Test status
Simulation time 53645521 ps
CPU time 1.1 seconds
Started Jul 22 05:44:56 PM PDT 24
Finished Jul 22 05:44:58 PM PDT 24
Peak memory 217476 kb
Host smart-d59ac0b0-c6c2-41dd-9db7-12361aa4b226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130728870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.3130728870
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2728349737
Short name T879
Test name
Test status
Simulation time 53618708 ps
CPU time 1.66 seconds
Started Jul 22 05:44:56 PM PDT 24
Finished Jul 22 05:44:59 PM PDT 24
Peak memory 217620 kb
Host smart-661a6d6e-4780-40fe-995b-9a8ab8dda229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728349737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2728349737
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.2373948415
Short name T281
Test name
Test status
Simulation time 81956877 ps
CPU time 1.22 seconds
Started Jul 22 05:44:53 PM PDT 24
Finished Jul 22 05:44:54 PM PDT 24
Peak memory 217776 kb
Host smart-9b8efc04-d9f4-4cb8-904a-68fb4d9d2321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373948415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.2373948415
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.1005093241
Short name T705
Test name
Test status
Simulation time 96126786 ps
CPU time 1.54 seconds
Started Jul 22 05:44:58 PM PDT 24
Finished Jul 22 05:45:00 PM PDT 24
Peak memory 219292 kb
Host smart-1639327c-e02f-4e2e-8bb8-836817fadf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005093241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.1005093241
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.599284815
Short name T922
Test name
Test status
Simulation time 50819565 ps
CPU time 1.51 seconds
Started Jul 22 05:44:54 PM PDT 24
Finished Jul 22 05:44:56 PM PDT 24
Peak memory 218740 kb
Host smart-68069722-5df1-43ca-9991-0312c68c493d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599284815 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.599284815
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.3506692905
Short name T919
Test name
Test status
Simulation time 37930152 ps
CPU time 1.32 seconds
Started Jul 22 05:46:46 PM PDT 24
Finished Jul 22 05:46:48 PM PDT 24
Peak memory 217508 kb
Host smart-6d56476d-05fe-4f56-8fbd-cc606e29c996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506692905 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.3506692905
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.1818699349
Short name T357
Test name
Test status
Simulation time 33852060 ps
CPU time 1.32 seconds
Started Jul 22 05:44:57 PM PDT 24
Finished Jul 22 05:44:59 PM PDT 24
Peak memory 217540 kb
Host smart-3ec42e95-1115-4ae6-bce0-fb78fa104b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818699349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1818699349
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.3585589647
Short name T436
Test name
Test status
Simulation time 43148129 ps
CPU time 1.25 seconds
Started Jul 22 05:44:54 PM PDT 24
Finished Jul 22 05:44:56 PM PDT 24
Peak memory 220248 kb
Host smart-2e29dea6-b9e3-42e6-8a6b-d542b96b5e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585589647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.3585589647
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.1554673486
Short name T332
Test name
Test status
Simulation time 52243170 ps
CPU time 1.58 seconds
Started Jul 22 05:44:54 PM PDT 24
Finished Jul 22 05:44:57 PM PDT 24
Peak memory 218616 kb
Host smart-e02f9b3e-0355-432a-b891-7bc60f9af4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554673486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.1554673486
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.2989858572
Short name T817
Test name
Test status
Simulation time 23494589 ps
CPU time 1.21 seconds
Started Jul 22 05:42:51 PM PDT 24
Finished Jul 22 05:42:54 PM PDT 24
Peak memory 220044 kb
Host smart-92b69e83-dcf0-4e50-bed4-6d22a2b6adae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989858572 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.2989858572
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.114258353
Short name T503
Test name
Test status
Simulation time 14460841 ps
CPU time 0.9 seconds
Started Jul 22 05:42:45 PM PDT 24
Finished Jul 22 05:42:46 PM PDT 24
Peak memory 215132 kb
Host smart-879328df-0e94-4934-9130-929b15666f25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114258353 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.114258353
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.4226856895
Short name T188
Test name
Test status
Simulation time 47025833 ps
CPU time 0.89 seconds
Started Jul 22 05:42:49 PM PDT 24
Finished Jul 22 05:42:51 PM PDT 24
Peak memory 216592 kb
Host smart-a259ab2d-0d7f-49cc-8533-5f6c9ac35e27
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226856895 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.4226856895
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.1038666909
Short name T821
Test name
Test status
Simulation time 80045325 ps
CPU time 1.11 seconds
Started Jul 22 05:42:49 PM PDT 24
Finished Jul 22 05:42:50 PM PDT 24
Peak memory 217376 kb
Host smart-bc77a95e-c172-435b-a3f5-6252579d19e6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038666909 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.1038666909
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.174977457
Short name T345
Test name
Test status
Simulation time 18989488 ps
CPU time 1.05 seconds
Started Jul 22 05:42:46 PM PDT 24
Finished Jul 22 05:42:48 PM PDT 24
Peak memory 218856 kb
Host smart-4adc560f-5148-4ab7-af93-c4d7f9e9dcbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174977457 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.174977457
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_intr.975879429
Short name T458
Test name
Test status
Simulation time 22360834 ps
CPU time 1.11 seconds
Started Jul 22 05:42:50 PM PDT 24
Finished Jul 22 05:42:52 PM PDT 24
Peak memory 215740 kb
Host smart-ce9ca846-78ae-4ad4-8e0d-686a4a2b4a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975879429 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.975879429
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.4184301946
Short name T745
Test name
Test status
Simulation time 32190726 ps
CPU time 0.93 seconds
Started Jul 22 05:42:49 PM PDT 24
Finished Jul 22 05:42:52 PM PDT 24
Peak memory 215604 kb
Host smart-31155a57-7eaf-4cd8-9418-9a39781e159d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184301946 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.4184301946
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.1523803843
Short name T412
Test name
Test status
Simulation time 658749131 ps
CPU time 3.25 seconds
Started Jul 22 05:42:48 PM PDT 24
Finished Jul 22 05:42:52 PM PDT 24
Peak memory 217604 kb
Host smart-8dd573bf-946e-40fc-81a4-ade56344924f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523803843 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.1523803843
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.3131972346
Short name T723
Test name
Test status
Simulation time 61348869498 ps
CPU time 414.39 seconds
Started Jul 22 05:42:46 PM PDT 24
Finished Jul 22 05:49:40 PM PDT 24
Peak memory 217944 kb
Host smart-35cb4436-48a1-491e-9ce7-c27126345fbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131972346 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.3131972346
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.98625311
Short name T434
Test name
Test status
Simulation time 43718007 ps
CPU time 1.12 seconds
Started Jul 22 05:44:56 PM PDT 24
Finished Jul 22 05:44:58 PM PDT 24
Peak memory 219728 kb
Host smart-f152813d-094f-483c-b81f-d4fef06481bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98625311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.98625311
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.2566918733
Short name T669
Test name
Test status
Simulation time 211993799 ps
CPU time 2.39 seconds
Started Jul 22 05:44:55 PM PDT 24
Finished Jul 22 05:44:58 PM PDT 24
Peak memory 220460 kb
Host smart-c6aa47dc-30f0-4693-8b9d-ddf70fd15ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566918733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.2566918733
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.3611769118
Short name T791
Test name
Test status
Simulation time 45514765 ps
CPU time 1.42 seconds
Started Jul 22 05:44:53 PM PDT 24
Finished Jul 22 05:44:56 PM PDT 24
Peak memory 218852 kb
Host smart-8c62524e-15db-47fd-a790-dc748a1dacbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611769118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3611769118
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.3469009669
Short name T699
Test name
Test status
Simulation time 52239072 ps
CPU time 1.15 seconds
Started Jul 22 05:45:00 PM PDT 24
Finished Jul 22 05:45:02 PM PDT 24
Peak memory 218940 kb
Host smart-e873112c-caa3-42d9-aa81-72dab267af2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469009669 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.3469009669
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2362620159
Short name T420
Test name
Test status
Simulation time 81239524 ps
CPU time 1.46 seconds
Started Jul 22 05:44:53 PM PDT 24
Finished Jul 22 05:44:55 PM PDT 24
Peak memory 218860 kb
Host smart-1721dede-9902-4ce3-a5de-7b512493d07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362620159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2362620159
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.2043344643
Short name T382
Test name
Test status
Simulation time 125103808 ps
CPU time 1.7 seconds
Started Jul 22 05:44:51 PM PDT 24
Finished Jul 22 05:44:53 PM PDT 24
Peak memory 220712 kb
Host smart-5e3aee4b-63b6-4273-9fd3-4257e40f2d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043344643 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2043344643
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.1270278509
Short name T588
Test name
Test status
Simulation time 77013036 ps
CPU time 1.13 seconds
Started Jul 22 05:44:54 PM PDT 24
Finished Jul 22 05:44:55 PM PDT 24
Peak memory 217552 kb
Host smart-a2b7e4ae-6402-4c7d-a7b1-6d8b36974701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270278509 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.1270278509
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.4130020765
Short name T903
Test name
Test status
Simulation time 41719281 ps
CPU time 1.37 seconds
Started Jul 22 05:44:55 PM PDT 24
Finished Jul 22 05:44:57 PM PDT 24
Peak memory 219956 kb
Host smart-ab2f43dc-e040-4636-86f5-46566fe02b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130020765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.4130020765
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.3728720322
Short name T513
Test name
Test status
Simulation time 36101488 ps
CPU time 1.39 seconds
Started Jul 22 05:44:55 PM PDT 24
Finished Jul 22 05:44:57 PM PDT 24
Peak memory 217504 kb
Host smart-542b424e-e09c-4469-9048-c7b4194878dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728720322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3728720322
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.2080227250
Short name T653
Test name
Test status
Simulation time 70563775 ps
CPU time 1.17 seconds
Started Jul 22 05:42:50 PM PDT 24
Finished Jul 22 05:42:52 PM PDT 24
Peak memory 220212 kb
Host smart-123715fb-578b-4ac1-bfce-57aac94b6291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080227250 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.2080227250
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.785467623
Short name T765
Test name
Test status
Simulation time 22870978 ps
CPU time 0.84 seconds
Started Jul 22 05:42:47 PM PDT 24
Finished Jul 22 05:42:48 PM PDT 24
Peak memory 207104 kb
Host smart-b99400f3-9363-4d27-9088-42422fe446dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785467623 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.785467623
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.336082328
Short name T703
Test name
Test status
Simulation time 30761729 ps
CPU time 0.81 seconds
Started Jul 22 05:42:51 PM PDT 24
Finished Jul 22 05:42:54 PM PDT 24
Peak memory 216344 kb
Host smart-d4eda190-97b6-460a-85de-371f4e054f70
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336082328 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.336082328
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.1930587798
Short name T115
Test name
Test status
Simulation time 66133641 ps
CPU time 0.92 seconds
Started Jul 22 05:42:50 PM PDT 24
Finished Jul 22 05:42:52 PM PDT 24
Peak memory 217328 kb
Host smart-7992dae9-b9a3-4ca3-a4a2-a58cebc51cc1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930587798 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.1930587798
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.940134972
Short name T630
Test name
Test status
Simulation time 19693539 ps
CPU time 1.03 seconds
Started Jul 22 05:42:50 PM PDT 24
Finished Jul 22 05:42:53 PM PDT 24
Peak memory 218708 kb
Host smart-87da4036-dec1-4c6b-9a21-e19c47dfbc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940134972 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.940134972
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.2634055660
Short name T367
Test name
Test status
Simulation time 24833673 ps
CPU time 1.22 seconds
Started Jul 22 05:42:52 PM PDT 24
Finished Jul 22 05:42:55 PM PDT 24
Peak memory 218764 kb
Host smart-a7fbde94-e5ed-445b-b4fa-9cb4ecfa4244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634055660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.2634055660
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.758866502
Short name T689
Test name
Test status
Simulation time 32651202 ps
CPU time 0.97 seconds
Started Jul 22 05:42:51 PM PDT 24
Finished Jul 22 05:42:54 PM PDT 24
Peak memory 215884 kb
Host smart-77bf5c6c-ea90-4969-989c-80b469d98d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758866502 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.758866502
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.2608825225
Short name T831
Test name
Test status
Simulation time 24214357 ps
CPU time 0.99 seconds
Started Jul 22 05:42:47 PM PDT 24
Finished Jul 22 05:42:49 PM PDT 24
Peak memory 215568 kb
Host smart-6ea92b4f-2d5a-4ddf-9cd8-0afda090452f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608825225 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.2608825225
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.3740744995
Short name T566
Test name
Test status
Simulation time 251780084 ps
CPU time 4.76 seconds
Started Jul 22 05:42:49 PM PDT 24
Finished Jul 22 05:42:56 PM PDT 24
Peak memory 215572 kb
Host smart-24b65696-3f85-4f96-b33d-6534730d792e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740744995 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3740744995
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.2546238921
Short name T830
Test name
Test status
Simulation time 14625626504 ps
CPU time 369.98 seconds
Started Jul 22 05:42:48 PM PDT 24
Finished Jul 22 05:48:59 PM PDT 24
Peak memory 216912 kb
Host smart-c5c3ad42-abb0-415d-a253-f427dacb8f54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546238921 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.2546238921
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.3559574033
Short name T926
Test name
Test status
Simulation time 35007449 ps
CPU time 1.46 seconds
Started Jul 22 05:44:52 PM PDT 24
Finished Jul 22 05:44:54 PM PDT 24
Peak memory 217672 kb
Host smart-206de9eb-9aae-4f26-96dc-a1e50e845383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559574033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.3559574033
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.1945493492
Short name T602
Test name
Test status
Simulation time 37035578 ps
CPU time 1.41 seconds
Started Jul 22 05:44:55 PM PDT 24
Finished Jul 22 05:44:57 PM PDT 24
Peak memory 220280 kb
Host smart-f63ea5f8-a72a-478e-9c21-8ef2d487afc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945493492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.1945493492
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.590795784
Short name T976
Test name
Test status
Simulation time 56406524 ps
CPU time 0.99 seconds
Started Jul 22 05:44:57 PM PDT 24
Finished Jul 22 05:44:59 PM PDT 24
Peak memory 217624 kb
Host smart-f4171d0c-9157-4b68-8bae-88c348ad9864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590795784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.590795784
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.2923518423
Short name T324
Test name
Test status
Simulation time 64875526 ps
CPU time 1.19 seconds
Started Jul 22 05:44:49 PM PDT 24
Finished Jul 22 05:44:50 PM PDT 24
Peak memory 217664 kb
Host smart-164d4dbd-ed73-473e-b9cd-87089444724f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923518423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2923518423
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.1858424200
Short name T439
Test name
Test status
Simulation time 85513877 ps
CPU time 0.96 seconds
Started Jul 22 05:44:55 PM PDT 24
Finished Jul 22 05:44:56 PM PDT 24
Peak memory 217780 kb
Host smart-3ab059f2-6d99-4966-9107-d655a32709ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858424200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.1858424200
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2800629223
Short name T19
Test name
Test status
Simulation time 76617976 ps
CPU time 1.05 seconds
Started Jul 22 05:44:57 PM PDT 24
Finished Jul 22 05:44:59 PM PDT 24
Peak memory 220152 kb
Host smart-8867a27d-9dcf-40f4-bb38-3b7dc1db343d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800629223 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2800629223
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.1439032634
Short name T811
Test name
Test status
Simulation time 76133553 ps
CPU time 1.14 seconds
Started Jul 22 05:44:57 PM PDT 24
Finished Jul 22 05:44:59 PM PDT 24
Peak memory 217656 kb
Host smart-d7c82815-5702-4d39-8c72-67e561a485fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439032634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.1439032634
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.2864964004
Short name T369
Test name
Test status
Simulation time 24270572 ps
CPU time 1.19 seconds
Started Jul 22 05:44:54 PM PDT 24
Finished Jul 22 05:44:56 PM PDT 24
Peak memory 217592 kb
Host smart-1bd6919d-a7c7-4ccf-83ff-e292f98a486e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864964004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2864964004
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.3255305266
Short name T365
Test name
Test status
Simulation time 62000732 ps
CPU time 1.17 seconds
Started Jul 22 05:44:50 PM PDT 24
Finished Jul 22 05:44:52 PM PDT 24
Peak memory 220280 kb
Host smart-6c2c7c09-d732-497e-83a8-253ea1a923fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255305266 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3255305266
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.3575668391
Short name T596
Test name
Test status
Simulation time 74492927 ps
CPU time 1.59 seconds
Started Jul 22 05:44:52 PM PDT 24
Finished Jul 22 05:44:55 PM PDT 24
Peak memory 218916 kb
Host smart-63a14a16-5336-41de-88cd-1e2bdcc29b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575668391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.3575668391
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.1744493073
Short name T665
Test name
Test status
Simulation time 85301061 ps
CPU time 1.22 seconds
Started Jul 22 05:42:48 PM PDT 24
Finished Jul 22 05:42:49 PM PDT 24
Peak memory 220232 kb
Host smart-792c5377-ab8d-42e4-9680-a37daabfd354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744493073 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.1744493073
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.470455535
Short name T234
Test name
Test status
Simulation time 14844473 ps
CPU time 0.86 seconds
Started Jul 22 05:43:18 PM PDT 24
Finished Jul 22 05:43:19 PM PDT 24
Peak memory 206920 kb
Host smart-1b4d9419-935e-45e7-953a-d49b219abb50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470455535 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.470455535
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.829986271
Short name T517
Test name
Test status
Simulation time 13856110 ps
CPU time 0.9 seconds
Started Jul 22 05:42:54 PM PDT 24
Finished Jul 22 05:42:56 PM PDT 24
Peak memory 216764 kb
Host smart-71fc43cc-9b09-443b-ad45-a28283578a67
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829986271 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.829986271
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.707353562
Short name T620
Test name
Test status
Simulation time 24666455 ps
CPU time 1.19 seconds
Started Jul 22 05:42:53 PM PDT 24
Finished Jul 22 05:42:56 PM PDT 24
Peak memory 217348 kb
Host smart-f30a3c9a-69b1-40aa-b900-cc0c3481de2a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707353562 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_di
sable_auto_req_mode.707353562
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.1783300191
Short name T886
Test name
Test status
Simulation time 31082982 ps
CPU time 0.85 seconds
Started Jul 22 05:42:49 PM PDT 24
Finished Jul 22 05:42:51 PM PDT 24
Peak memory 218328 kb
Host smart-e95c9196-190b-4db2-ad87-2902bb23470d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783300191 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.1783300191
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.3168141275
Short name T71
Test name
Test status
Simulation time 50517940 ps
CPU time 1.61 seconds
Started Jul 22 05:42:50 PM PDT 24
Finished Jul 22 05:42:52 PM PDT 24
Peak memory 218960 kb
Host smart-e9735285-9834-4f10-b2b8-288431c13eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168141275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3168141275
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.2396564971
Short name T537
Test name
Test status
Simulation time 23255164 ps
CPU time 1.23 seconds
Started Jul 22 05:42:51 PM PDT 24
Finished Jul 22 05:42:54 PM PDT 24
Peak memory 224260 kb
Host smart-3b888c89-6947-4d90-b4e9-b6d3dc6442dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396564971 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.2396564971
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.2515027170
Short name T680
Test name
Test status
Simulation time 48678353 ps
CPU time 0.89 seconds
Started Jul 22 05:42:50 PM PDT 24
Finished Jul 22 05:42:52 PM PDT 24
Peak memory 215636 kb
Host smart-8d8cd62b-5fee-4590-ad10-d1b56e8ffa50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515027170 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.2515027170
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.2790700432
Short name T767
Test name
Test status
Simulation time 482435642 ps
CPU time 5.35 seconds
Started Jul 22 05:42:48 PM PDT 24
Finished Jul 22 05:42:54 PM PDT 24
Peak memory 217448 kb
Host smart-d103036b-47f8-41c9-94ca-c268bf0df839
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790700432 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2790700432
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.1792534121
Short name T905
Test name
Test status
Simulation time 184972802497 ps
CPU time 1027.79 seconds
Started Jul 22 05:42:49 PM PDT 24
Finished Jul 22 05:59:57 PM PDT 24
Peak memory 222612 kb
Host smart-8ac09eea-fee8-4ea0-8507-e4f02b482ea2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792534121 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.1792534121
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.1336042906
Short name T79
Test name
Test status
Simulation time 83771135 ps
CPU time 1.18 seconds
Started Jul 22 05:44:56 PM PDT 24
Finished Jul 22 05:44:58 PM PDT 24
Peak memory 219152 kb
Host smart-fb8978c3-b156-409a-9d4c-b6a1b7d5b805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336042906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.1336042906
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.3748932279
Short name T512
Test name
Test status
Simulation time 50934555 ps
CPU time 1.41 seconds
Started Jul 22 05:44:52 PM PDT 24
Finished Jul 22 05:44:54 PM PDT 24
Peak memory 219976 kb
Host smart-40aaa37a-cc9b-4250-8064-194bb7df6ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748932279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.3748932279
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.153988514
Short name T500
Test name
Test status
Simulation time 71592294 ps
CPU time 1.17 seconds
Started Jul 22 05:46:46 PM PDT 24
Finished Jul 22 05:46:47 PM PDT 24
Peak memory 217780 kb
Host smart-650980b7-8302-4e5e-90d0-71167a27ffab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153988514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.153988514
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.2058980855
Short name T832
Test name
Test status
Simulation time 31080697 ps
CPU time 1.28 seconds
Started Jul 22 05:44:55 PM PDT 24
Finished Jul 22 05:44:57 PM PDT 24
Peak memory 220284 kb
Host smart-639e612f-24a5-4181-a817-9c636e056a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058980855 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2058980855
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.347008535
Short name T391
Test name
Test status
Simulation time 99961599 ps
CPU time 1.21 seconds
Started Jul 22 05:44:53 PM PDT 24
Finished Jul 22 05:44:55 PM PDT 24
Peak memory 220260 kb
Host smart-f378a8af-8093-4e60-9ae8-f5ec24f95f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347008535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.347008535
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.3417619180
Short name T361
Test name
Test status
Simulation time 144803241 ps
CPU time 2.27 seconds
Started Jul 22 05:44:51 PM PDT 24
Finished Jul 22 05:44:54 PM PDT 24
Peak memory 220680 kb
Host smart-41c0d791-7181-49ec-8830-2cffabdb2ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417619180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.3417619180
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.2720164537
Short name T655
Test name
Test status
Simulation time 43427700 ps
CPU time 1.64 seconds
Started Jul 22 05:44:59 PM PDT 24
Finished Jul 22 05:45:01 PM PDT 24
Peak memory 218900 kb
Host smart-c0a5c425-dd1e-445a-9da4-4149fa9f1538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720164537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.2720164537
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.2412109711
Short name T3
Test name
Test status
Simulation time 48370501 ps
CPU time 1.54 seconds
Started Jul 22 05:44:57 PM PDT 24
Finished Jul 22 05:44:59 PM PDT 24
Peak memory 218696 kb
Host smart-d3648e31-187d-4620-9241-b3c281c5b238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412109711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.2412109711
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.813373894
Short name T318
Test name
Test status
Simulation time 90715687 ps
CPU time 1.26 seconds
Started Jul 22 05:44:52 PM PDT 24
Finished Jul 22 05:44:54 PM PDT 24
Peak memory 219164 kb
Host smart-74389c16-8fdc-4cad-8476-47fc9dcfc242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813373894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.813373894
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.2389755289
Short name T892
Test name
Test status
Simulation time 29094203 ps
CPU time 1.26 seconds
Started Jul 22 05:42:51 PM PDT 24
Finished Jul 22 05:42:54 PM PDT 24
Peak memory 220116 kb
Host smart-9cdc20de-fabc-46cc-a210-80fd0c5c7ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389755289 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.2389755289
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.2584840032
Short name T715
Test name
Test status
Simulation time 69080284 ps
CPU time 0.84 seconds
Started Jul 22 05:42:49 PM PDT 24
Finished Jul 22 05:42:50 PM PDT 24
Peak memory 206856 kb
Host smart-fc523b1b-46bb-4afb-9d6f-519948a143f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584840032 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.2584840032
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.1163687268
Short name T697
Test name
Test status
Simulation time 91731166 ps
CPU time 1.09 seconds
Started Jul 22 05:42:51 PM PDT 24
Finished Jul 22 05:42:54 PM PDT 24
Peak memory 217352 kb
Host smart-02f88f7d-dd2a-4671-9608-7a10825cd250
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163687268 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.1163687268
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.657240833
Short name T346
Test name
Test status
Simulation time 19388392 ps
CPU time 1.08 seconds
Started Jul 22 05:42:50 PM PDT 24
Finished Jul 22 05:42:52 PM PDT 24
Peak memory 218708 kb
Host smart-a61522a7-4b96-4754-865a-9a32f7c27932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657240833 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.657240833
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.1394365842
Short name T348
Test name
Test status
Simulation time 55648589 ps
CPU time 1.2 seconds
Started Jul 22 05:42:49 PM PDT 24
Finished Jul 22 05:42:51 PM PDT 24
Peak memory 218792 kb
Host smart-480fe9ef-5ded-40b3-acb3-729d50a95712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394365842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.1394365842
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.3583737076
Short name T938
Test name
Test status
Simulation time 22480504 ps
CPU time 1.12 seconds
Started Jul 22 05:42:54 PM PDT 24
Finished Jul 22 05:42:56 PM PDT 24
Peak memory 224060 kb
Host smart-96376da4-d5da-4fa7-83ec-02030395a056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583737076 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.3583737076
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.466616576
Short name T800
Test name
Test status
Simulation time 18116013 ps
CPU time 1.03 seconds
Started Jul 22 05:42:54 PM PDT 24
Finished Jul 22 05:42:56 PM PDT 24
Peak memory 215268 kb
Host smart-d3d5e57a-4f74-481d-bce9-5649e7ce532f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466616576 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.466616576
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.1240969216
Short name T587
Test name
Test status
Simulation time 142500307 ps
CPU time 1.18 seconds
Started Jul 22 05:42:54 PM PDT 24
Finished Jul 22 05:42:57 PM PDT 24
Peak memory 219528 kb
Host smart-ff85a415-73ac-4f2a-9402-bb2c740c7a01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240969216 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1240969216
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.3386877134
Short name T224
Test name
Test status
Simulation time 62331986208 ps
CPU time 677.57 seconds
Started Jul 22 05:42:54 PM PDT 24
Finished Jul 22 05:54:13 PM PDT 24
Peak memory 218660 kb
Host smart-7e7a82c2-8c3d-412f-bc1a-eeafc9271cdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386877134 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.3386877134
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.3273390162
Short name T565
Test name
Test status
Simulation time 44922356 ps
CPU time 1.44 seconds
Started Jul 22 05:44:59 PM PDT 24
Finished Jul 22 05:45:01 PM PDT 24
Peak memory 218668 kb
Host smart-4c26edf1-65eb-4747-adf6-c2ad58e10467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273390162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.3273390162
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.1739376926
Short name T20
Test name
Test status
Simulation time 38153703 ps
CPU time 1.36 seconds
Started Jul 22 05:44:53 PM PDT 24
Finished Jul 22 05:44:55 PM PDT 24
Peak memory 220336 kb
Host smart-359a5cf6-5593-4ab2-aaa5-ff737bde8aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739376926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.1739376926
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.1938352548
Short name T562
Test name
Test status
Simulation time 65334473 ps
CPU time 1.29 seconds
Started Jul 22 05:45:00 PM PDT 24
Finished Jul 22 05:45:01 PM PDT 24
Peak memory 220208 kb
Host smart-17dc6f8c-09a5-4888-a7e1-9847554c8582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938352548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.1938352548
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.711511686
Short name T455
Test name
Test status
Simulation time 41818535 ps
CPU time 1.08 seconds
Started Jul 22 05:45:03 PM PDT 24
Finished Jul 22 05:45:06 PM PDT 24
Peak memory 217548 kb
Host smart-3256b505-3e9c-4997-93df-1a3ffd08e25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711511686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.711511686
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.2583499794
Short name T13
Test name
Test status
Simulation time 41005835 ps
CPU time 1.46 seconds
Started Jul 22 05:45:01 PM PDT 24
Finished Jul 22 05:45:04 PM PDT 24
Peak memory 220272 kb
Host smart-4a6ee9af-ed50-4468-a87c-a97278c84ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583499794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.2583499794
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.3141527263
Short name T335
Test name
Test status
Simulation time 177683468 ps
CPU time 2.02 seconds
Started Jul 22 05:45:02 PM PDT 24
Finished Jul 22 05:45:05 PM PDT 24
Peak memory 215672 kb
Host smart-1d929616-7489-480d-b3ce-720483c4cee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141527263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.3141527263
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.2488452908
Short name T679
Test name
Test status
Simulation time 79720067 ps
CPU time 1.15 seconds
Started Jul 22 05:45:03 PM PDT 24
Finished Jul 22 05:45:05 PM PDT 24
Peak memory 217652 kb
Host smart-8f596211-87a6-4d4f-9c30-9d7133c7781a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488452908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.2488452908
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.1459663731
Short name T603
Test name
Test status
Simulation time 50739444 ps
CPU time 1.53 seconds
Started Jul 22 05:45:03 PM PDT 24
Finished Jul 22 05:45:06 PM PDT 24
Peak memory 218648 kb
Host smart-f6b8a73d-e0ce-465c-80c3-746e99a9fbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459663731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1459663731
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.175355097
Short name T433
Test name
Test status
Simulation time 46422131 ps
CPU time 1.11 seconds
Started Jul 22 05:45:04 PM PDT 24
Finished Jul 22 05:45:06 PM PDT 24
Peak memory 215604 kb
Host smart-6ee3a945-4cbc-4c9a-8a57-9a7662ff7f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175355097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.175355097
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.3843419826
Short name T390
Test name
Test status
Simulation time 165388322 ps
CPU time 1.05 seconds
Started Jul 22 05:45:05 PM PDT 24
Finished Jul 22 05:45:07 PM PDT 24
Peak memory 217656 kb
Host smart-0926e8c0-8a89-4602-b689-45f1f73fbe3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843419826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3843419826
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert_test.1707661675
Short name T400
Test name
Test status
Simulation time 53878693 ps
CPU time 0.93 seconds
Started Jul 22 05:41:56 PM PDT 24
Finished Jul 22 05:41:58 PM PDT 24
Peak memory 206968 kb
Host smart-b5cb7b24-806c-4c7f-a0dc-e0fc7a98459f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707661675 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.1707661675
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.3427841861
Short name T366
Test name
Test status
Simulation time 125492131 ps
CPU time 0.85 seconds
Started Jul 22 05:41:56 PM PDT 24
Finished Jul 22 05:41:57 PM PDT 24
Peak memory 216264 kb
Host smart-59c9923f-c237-4726-a492-ad921d3a27c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427841861 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.3427841861
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.576424806
Short name T456
Test name
Test status
Simulation time 146426773 ps
CPU time 1.09 seconds
Started Jul 22 05:41:52 PM PDT 24
Finished Jul 22 05:41:54 PM PDT 24
Peak memory 217356 kb
Host smart-76b953c4-03f2-4dcc-94be-d1a18e4b1815
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576424806 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_dis
able_auto_req_mode.576424806
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.1093482118
Short name T997
Test name
Test status
Simulation time 30553151 ps
CPU time 1.26 seconds
Started Jul 22 05:41:52 PM PDT 24
Finished Jul 22 05:41:53 PM PDT 24
Peak memory 220012 kb
Host smart-016dd227-12fe-4998-b2ee-0530e6032c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093482118 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.1093482118
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.3444871796
Short name T568
Test name
Test status
Simulation time 57405843 ps
CPU time 0.93 seconds
Started Jul 22 05:41:59 PM PDT 24
Finished Jul 22 05:42:00 PM PDT 24
Peak memory 217564 kb
Host smart-d1e624a5-18b6-4620-93b9-ed177f6009ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444871796 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.3444871796
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.3976392863
Short name T410
Test name
Test status
Simulation time 41008281 ps
CPU time 0.94 seconds
Started Jul 22 05:41:53 PM PDT 24
Finished Jul 22 05:41:55 PM PDT 24
Peak memory 215688 kb
Host smart-4b0f021a-69b9-43aa-8a01-d570bda0ba0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976392863 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.3976392863
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.2831797236
Short name T24
Test name
Test status
Simulation time 18828840 ps
CPU time 1.02 seconds
Started Jul 22 05:42:37 PM PDT 24
Finished Jul 22 05:42:39 PM PDT 24
Peak memory 207492 kb
Host smart-560d7c17-2269-4027-b13b-eab8ba978d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831797236 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.2831797236
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.3783760788
Short name T344
Test name
Test status
Simulation time 61130333 ps
CPU time 0.92 seconds
Started Jul 22 05:41:53 PM PDT 24
Finished Jul 22 05:41:56 PM PDT 24
Peak memory 215624 kb
Host smart-1f25db07-3216-4bc8-9239-9f44f933d2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783760788 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3783760788
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.2222778705
Short name T239
Test name
Test status
Simulation time 159415591 ps
CPU time 3.46 seconds
Started Jul 22 05:41:53 PM PDT 24
Finished Jul 22 05:41:57 PM PDT 24
Peak memory 215700 kb
Host smart-5e815946-9bbd-4aa8-ae8c-89c247dc1a16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222778705 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2222778705
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3348637093
Short name T35
Test name
Test status
Simulation time 34714547595 ps
CPU time 387.72 seconds
Started Jul 22 05:41:54 PM PDT 24
Finished Jul 22 05:48:23 PM PDT 24
Peak memory 219568 kb
Host smart-3c15a893-0bca-4471-b4e5-2687ccd640c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348637093 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3348637093
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.987385159
Short name T643
Test name
Test status
Simulation time 44412742 ps
CPU time 1 seconds
Started Jul 22 05:42:53 PM PDT 24
Finished Jul 22 05:42:55 PM PDT 24
Peak memory 220040 kb
Host smart-1ada79d0-6969-4120-8974-32f062a1067c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987385159 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.987385159
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.2057251120
Short name T360
Test name
Test status
Simulation time 66243516 ps
CPU time 0.89 seconds
Started Jul 22 05:42:49 PM PDT 24
Finished Jul 22 05:42:51 PM PDT 24
Peak memory 206960 kb
Host smart-acf46e04-5e43-4b77-8ded-67de24b6b07d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057251120 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.2057251120
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.1170741658
Short name T937
Test name
Test status
Simulation time 35144047 ps
CPU time 0.85 seconds
Started Jul 22 05:42:54 PM PDT 24
Finished Jul 22 05:42:57 PM PDT 24
Peak memory 216404 kb
Host smart-5ae14c3a-c7cb-4048-b6a7-68974d62f63f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170741658 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1170741658
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_err.4182487428
Short name T126
Test name
Test status
Simulation time 29572542 ps
CPU time 1.08 seconds
Started Jul 22 05:42:48 PM PDT 24
Finished Jul 22 05:42:50 PM PDT 24
Peak memory 229876 kb
Host smart-7e4c5a5e-df96-464d-90f0-583856537d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182487428 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.4182487428
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.3117498628
Short name T574
Test name
Test status
Simulation time 60498262 ps
CPU time 1.07 seconds
Started Jul 22 05:42:53 PM PDT 24
Finished Jul 22 05:42:56 PM PDT 24
Peak memory 217704 kb
Host smart-6f0a1ccf-4d9e-4cf9-9d24-2ab6b5c3dc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117498628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3117498628
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.2921797213
Short name T363
Test name
Test status
Simulation time 22683753 ps
CPU time 1.11 seconds
Started Jul 22 05:42:52 PM PDT 24
Finished Jul 22 05:42:55 PM PDT 24
Peak memory 215996 kb
Host smart-493f40ee-e63c-4fc8-a663-c006b7a9976a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921797213 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2921797213
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.4036241015
Short name T506
Test name
Test status
Simulation time 20591871 ps
CPU time 1.03 seconds
Started Jul 22 05:42:50 PM PDT 24
Finished Jul 22 05:42:52 PM PDT 24
Peak memory 215624 kb
Host smart-fb6f066c-9f3b-4376-9eaa-2bc512003d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036241015 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.4036241015
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.3018074296
Short name T578
Test name
Test status
Simulation time 245697302 ps
CPU time 5.25 seconds
Started Jul 22 05:42:48 PM PDT 24
Finished Jul 22 05:42:54 PM PDT 24
Peak memory 217452 kb
Host smart-1585d3bb-aa72-49d5-b3b2-d2aaf0e8370c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018074296 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.3018074296
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.738062658
Short name T560
Test name
Test status
Simulation time 30955914170 ps
CPU time 399.56 seconds
Started Jul 22 05:42:50 PM PDT 24
Finished Jul 22 05:49:31 PM PDT 24
Peak memory 218272 kb
Host smart-07939977-a118-4eca-a1c8-6a8ad83cac91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738062658 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.738062658
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.3390984618
Short name T605
Test name
Test status
Simulation time 49921916 ps
CPU time 1.18 seconds
Started Jul 22 05:42:49 PM PDT 24
Finished Jul 22 05:42:51 PM PDT 24
Peak memory 220088 kb
Host smart-11a49f22-4123-4396-aa98-62a69a28bcc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390984618 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.3390984618
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.3298898384
Short name T536
Test name
Test status
Simulation time 24558533 ps
CPU time 0.89 seconds
Started Jul 22 05:42:55 PM PDT 24
Finished Jul 22 05:42:57 PM PDT 24
Peak memory 215200 kb
Host smart-0570cf06-1625-4ce7-a7da-642da1c84944
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298898384 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3298898384
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.3660733250
Short name T167
Test name
Test status
Simulation time 22959307 ps
CPU time 0.87 seconds
Started Jul 22 05:42:52 PM PDT 24
Finished Jul 22 05:42:55 PM PDT 24
Peak memory 216556 kb
Host smart-a8c520f7-dcfb-4c77-ab9a-399f347e2ed7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660733250 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3660733250
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2492644611
Short name T117
Test name
Test status
Simulation time 145193915 ps
CPU time 1.12 seconds
Started Jul 22 05:43:02 PM PDT 24
Finished Jul 22 05:43:04 PM PDT 24
Peak memory 217284 kb
Host smart-014b266d-9963-418f-adc8-038b7b23a4a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492644611 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2492644611
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.1953844179
Short name T626
Test name
Test status
Simulation time 18269828 ps
CPU time 0.99 seconds
Started Jul 22 05:42:50 PM PDT 24
Finished Jul 22 05:42:53 PM PDT 24
Peak memory 218872 kb
Host smart-c2928228-6103-4bf3-9573-6af8adf7d131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953844179 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.1953844179
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.2678398271
Short name T972
Test name
Test status
Simulation time 57031415 ps
CPU time 1.18 seconds
Started Jul 22 05:42:50 PM PDT 24
Finished Jul 22 05:42:52 PM PDT 24
Peak memory 217628 kb
Host smart-bfc7f421-675e-45fc-82a1-8663331e51a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678398271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.2678398271
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.2106810263
Short name T747
Test name
Test status
Simulation time 56165778 ps
CPU time 0.86 seconds
Started Jul 22 05:42:52 PM PDT 24
Finished Jul 22 05:42:54 PM PDT 24
Peak memory 215968 kb
Host smart-5b093b25-c1c7-40f1-be4e-396a4db1ea99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106810263 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.2106810263
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.2189109466
Short name T880
Test name
Test status
Simulation time 119914556 ps
CPU time 0.93 seconds
Started Jul 22 05:42:53 PM PDT 24
Finished Jul 22 05:42:55 PM PDT 24
Peak memory 215616 kb
Host smart-860c236c-ce1e-4181-b690-9591275989c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189109466 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.2189109466
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.547137683
Short name T671
Test name
Test status
Simulation time 505811105 ps
CPU time 5.24 seconds
Started Jul 22 05:42:51 PM PDT 24
Finished Jul 22 05:42:58 PM PDT 24
Peak memory 217636 kb
Host smart-2ce7ee7b-6ad0-4b62-8a73-f033d8c6dc18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547137683 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.547137683
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.3079263350
Short name T785
Test name
Test status
Simulation time 225239031675 ps
CPU time 2587.01 seconds
Started Jul 22 05:42:50 PM PDT 24
Finished Jul 22 06:25:59 PM PDT 24
Peak memory 228556 kb
Host smart-877bc241-a557-4bba-b24f-f4f30295a63a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079263350 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.3079263350
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.2260035974
Short name T958
Test name
Test status
Simulation time 34017717 ps
CPU time 1.35 seconds
Started Jul 22 05:43:04 PM PDT 24
Finished Jul 22 05:43:07 PM PDT 24
Peak memory 221416 kb
Host smart-b034bd58-79c6-4df6-9595-8f22a8261293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260035974 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.2260035974
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.614272156
Short name T356
Test name
Test status
Simulation time 238331895 ps
CPU time 0.89 seconds
Started Jul 22 05:42:52 PM PDT 24
Finished Jul 22 05:42:54 PM PDT 24
Peak memory 215148 kb
Host smart-457e8c00-824b-4e67-b959-9e2cb52d2e5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614272156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.614272156
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.3260243354
Short name T212
Test name
Test status
Simulation time 20205111 ps
CPU time 0.92 seconds
Started Jul 22 05:43:00 PM PDT 24
Finished Jul 22 05:43:02 PM PDT 24
Peak memory 216440 kb
Host smart-901904e3-307d-4883-b030-1946ffe514c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260243354 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3260243354
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.2467207675
Short name T755
Test name
Test status
Simulation time 62668122 ps
CPU time 0.92 seconds
Started Jul 22 05:42:51 PM PDT 24
Finished Jul 22 05:42:54 PM PDT 24
Peak memory 218580 kb
Host smart-e2434a56-b31e-428b-a120-cfa81c44e993
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467207675 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.2467207675
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.1224503264
Short name T883
Test name
Test status
Simulation time 46328060 ps
CPU time 1.14 seconds
Started Jul 22 05:42:55 PM PDT 24
Finished Jul 22 05:42:58 PM PDT 24
Peak memory 220152 kb
Host smart-7b0b504a-f5a0-41f6-bc43-f024a12e6f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224503264 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.1224503264
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.191961041
Short name T520
Test name
Test status
Simulation time 125381263 ps
CPU time 1.35 seconds
Started Jul 22 05:42:50 PM PDT 24
Finished Jul 22 05:42:53 PM PDT 24
Peak memory 218648 kb
Host smart-77511a54-a5eb-477d-977d-407b862458cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191961041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.191961041
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.2088721003
Short name T28
Test name
Test status
Simulation time 23795976 ps
CPU time 1.05 seconds
Started Jul 22 05:42:55 PM PDT 24
Finished Jul 22 05:42:58 PM PDT 24
Peak memory 216168 kb
Host smart-35689deb-99b7-4930-bb08-91764cf1cbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088721003 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.2088721003
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.3171108122
Short name T523
Test name
Test status
Simulation time 35920979 ps
CPU time 0.86 seconds
Started Jul 22 05:42:54 PM PDT 24
Finished Jul 22 05:42:56 PM PDT 24
Peak memory 215464 kb
Host smart-d7324c6f-2342-4c4c-ae20-4e01b74ede98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171108122 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.3171108122
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.130591410
Short name T651
Test name
Test status
Simulation time 382917972 ps
CPU time 7.21 seconds
Started Jul 22 05:42:54 PM PDT 24
Finished Jul 22 05:43:03 PM PDT 24
Peak memory 217348 kb
Host smart-0a624b1b-7dc6-4b67-b384-3663202e5250
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130591410 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.130591410
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.3326797260
Short name T230
Test name
Test status
Simulation time 213984398830 ps
CPU time 1174.12 seconds
Started Jul 22 05:42:52 PM PDT 24
Finished Jul 22 06:02:27 PM PDT 24
Peak memory 221780 kb
Host smart-efaacd67-e4bd-4853-b987-b8243ebec6f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326797260 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.3326797260
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.421264359
Short name T280
Test name
Test status
Simulation time 36143756 ps
CPU time 1.11 seconds
Started Jul 22 05:42:57 PM PDT 24
Finished Jul 22 05:42:59 PM PDT 24
Peak memory 220228 kb
Host smart-1a8fdfdf-4041-4d22-9f02-3acc9553ee09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421264359 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.421264359
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.1481888508
Short name T709
Test name
Test status
Simulation time 15208385 ps
CPU time 0.97 seconds
Started Jul 22 05:42:57 PM PDT 24
Finished Jul 22 05:42:59 PM PDT 24
Peak memory 215192 kb
Host smart-1948f557-f521-484a-8802-7e5c7293fba3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481888508 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.1481888508
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.2583816623
Short name T920
Test name
Test status
Simulation time 16863553 ps
CPU time 0.84 seconds
Started Jul 22 05:42:54 PM PDT 24
Finished Jul 22 05:42:56 PM PDT 24
Peak memory 216564 kb
Host smart-85b2278e-2bb4-4713-8603-39becc6c169e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583816623 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.2583816623
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.1654610833
Short name T576
Test name
Test status
Simulation time 40921746 ps
CPU time 1.27 seconds
Started Jul 22 05:42:51 PM PDT 24
Finished Jul 22 05:42:54 PM PDT 24
Peak memory 217176 kb
Host smart-911e318c-40bb-43b6-865e-28131e79b80c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654610833 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.1654610833
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.3736430111
Short name T175
Test name
Test status
Simulation time 26712731 ps
CPU time 0.89 seconds
Started Jul 22 05:43:02 PM PDT 24
Finished Jul 22 05:43:04 PM PDT 24
Peak memory 218512 kb
Host smart-11049838-f1da-4d1d-bac7-5ffbc457201e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736430111 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.3736430111
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.675866154
Short name T295
Test name
Test status
Simulation time 109228561 ps
CPU time 1.25 seconds
Started Jul 22 05:43:04 PM PDT 24
Finished Jul 22 05:43:07 PM PDT 24
Peak memory 219908 kb
Host smart-2be2ee56-dff9-477a-ba5d-a71398b430b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675866154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.675866154
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_smoke.2758587103
Short name T931
Test name
Test status
Simulation time 18358659 ps
CPU time 1.02 seconds
Started Jul 22 05:43:05 PM PDT 24
Finished Jul 22 05:43:07 PM PDT 24
Peak memory 207396 kb
Host smart-0c29154e-2fb7-47d1-bba9-e06368971d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758587103 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.2758587103
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3138094952
Short name T656
Test name
Test status
Simulation time 426728994 ps
CPU time 4.62 seconds
Started Jul 22 05:42:55 PM PDT 24
Finished Jul 22 05:43:01 PM PDT 24
Peak memory 215660 kb
Host smart-9572c079-d78f-429b-a6a7-6ba2763e1ab6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138094952 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3138094952
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.1686115222
Short name T313
Test name
Test status
Simulation time 228764983712 ps
CPU time 2473.98 seconds
Started Jul 22 05:42:52 PM PDT 24
Finished Jul 22 06:24:08 PM PDT 24
Peak memory 229736 kb
Host smart-2ab17114-e0de-4afc-bea8-ec86d3af0c4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686115222 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.1686115222
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.3372221942
Short name T244
Test name
Test status
Simulation time 33098655 ps
CPU time 1.35 seconds
Started Jul 22 05:43:03 PM PDT 24
Finished Jul 22 05:43:06 PM PDT 24
Peak memory 215976 kb
Host smart-b3ee1e03-cc7d-4de8-9517-2eba318f2dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372221942 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.3372221942
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.1648998682
Short name T805
Test name
Test status
Simulation time 16607479 ps
CPU time 0.95 seconds
Started Jul 22 05:42:52 PM PDT 24
Finished Jul 22 05:42:54 PM PDT 24
Peak memory 215180 kb
Host smart-1a65c945-7a65-452b-8769-7791b45478d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648998682 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1648998682
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.2893178257
Short name T936
Test name
Test status
Simulation time 35077185 ps
CPU time 0.84 seconds
Started Jul 22 05:42:57 PM PDT 24
Finished Jul 22 05:42:59 PM PDT 24
Peak memory 215772 kb
Host smart-e75d7de3-6366-440f-bcf4-25e73d3624a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893178257 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.2893178257
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2253906309
Short name T812
Test name
Test status
Simulation time 35761302 ps
CPU time 1.29 seconds
Started Jul 22 05:42:55 PM PDT 24
Finished Jul 22 05:42:58 PM PDT 24
Peak memory 217320 kb
Host smart-0dec4572-13e5-4a66-968b-6ec4554ec734
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253906309 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2253906309
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.1603435823
Short name T135
Test name
Test status
Simulation time 108304750 ps
CPU time 1.13 seconds
Started Jul 22 05:43:04 PM PDT 24
Finished Jul 22 05:43:07 PM PDT 24
Peak memory 224260 kb
Host smart-ee645d7a-c69d-47fc-b995-0985576379fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603435823 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.1603435823
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.296170800
Short name T764
Test name
Test status
Simulation time 59417126 ps
CPU time 1.06 seconds
Started Jul 22 05:42:56 PM PDT 24
Finished Jul 22 05:42:58 PM PDT 24
Peak memory 217612 kb
Host smart-c70718db-13fe-4c18-a369-66093a3d96eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296170800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.296170800
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.2845066129
Short name T941
Test name
Test status
Simulation time 21095742 ps
CPU time 1.08 seconds
Started Jul 22 05:42:58 PM PDT 24
Finished Jul 22 05:43:00 PM PDT 24
Peak memory 224340 kb
Host smart-ffc0d87c-b18a-44ea-948a-2f67cfa0528f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845066129 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.2845066129
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.2504964293
Short name T528
Test name
Test status
Simulation time 21067647 ps
CPU time 0.94 seconds
Started Jul 22 05:42:55 PM PDT 24
Finished Jul 22 05:42:57 PM PDT 24
Peak memory 215592 kb
Host smart-668013ef-2533-4ada-8029-31e3ecf740a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504964293 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.2504964293
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.2705875161
Short name T428
Test name
Test status
Simulation time 74702042 ps
CPU time 1.12 seconds
Started Jul 22 05:42:56 PM PDT 24
Finished Jul 22 05:42:58 PM PDT 24
Peak memory 217692 kb
Host smart-b0e0e692-fd1a-44a3-b890-d7135b766618
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705875161 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.2705875161
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_alert.3774024372
Short name T421
Test name
Test status
Simulation time 69605165 ps
CPU time 1.14 seconds
Started Jul 22 05:42:59 PM PDT 24
Finished Jul 22 05:43:00 PM PDT 24
Peak memory 216008 kb
Host smart-ce82491d-ba95-44c8-86ef-30a5b15534bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774024372 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.3774024372
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.1435652497
Short name T913
Test name
Test status
Simulation time 19791950 ps
CPU time 1.08 seconds
Started Jul 22 05:43:01 PM PDT 24
Finished Jul 22 05:43:02 PM PDT 24
Peak memory 215428 kb
Host smart-8956b50c-9837-45a8-83bf-8450ad8654e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435652497 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1435652497
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.1072909314
Short name T468
Test name
Test status
Simulation time 20408621 ps
CPU time 0.89 seconds
Started Jul 22 05:43:02 PM PDT 24
Finished Jul 22 05:43:05 PM PDT 24
Peak memory 216324 kb
Host smart-c59814f6-b87d-41d4-a804-c80b6b7ad64e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072909314 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1072909314
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.1533895672
Short name T978
Test name
Test status
Simulation time 58944168 ps
CPU time 1.1 seconds
Started Jul 22 05:42:59 PM PDT 24
Finished Jul 22 05:43:00 PM PDT 24
Peak memory 217420 kb
Host smart-f792a010-4ada-420f-9316-cf7e68209633
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533895672 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.1533895672
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.923124303
Short name T444
Test name
Test status
Simulation time 79491066 ps
CPU time 0.98 seconds
Started Jul 22 05:42:54 PM PDT 24
Finished Jul 22 05:42:56 PM PDT 24
Peak memory 219992 kb
Host smart-81b88c70-35c1-45ba-98f3-af88954ac8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923124303 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.923124303
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.799752408
Short name T310
Test name
Test status
Simulation time 239854055 ps
CPU time 1.45 seconds
Started Jul 22 05:42:54 PM PDT 24
Finished Jul 22 05:42:57 PM PDT 24
Peak memory 220104 kb
Host smart-cce18f22-545b-45d5-9db7-ab81eb64447a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799752408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.799752408
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.2622136748
Short name T393
Test name
Test status
Simulation time 25082082 ps
CPU time 0.98 seconds
Started Jul 22 05:42:52 PM PDT 24
Finished Jul 22 05:42:54 PM PDT 24
Peak memory 215880 kb
Host smart-f110b3c6-7a25-4693-8452-14a344483a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622136748 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.2622136748
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.2835267379
Short name T546
Test name
Test status
Simulation time 24072920 ps
CPU time 0.84 seconds
Started Jul 22 05:42:58 PM PDT 24
Finished Jul 22 05:43:00 PM PDT 24
Peak memory 215480 kb
Host smart-84490c42-6b9d-4892-bf17-05d59d33f50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835267379 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.2835267379
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.993984511
Short name T949
Test name
Test status
Simulation time 774935622 ps
CPU time 4.54 seconds
Started Jul 22 05:42:52 PM PDT 24
Finished Jul 22 05:42:58 PM PDT 24
Peak memory 217652 kb
Host smart-ddb45adc-47a9-4150-845e-00f4699b95ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993984511 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.993984511
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1707694113
Short name T700
Test name
Test status
Simulation time 163031106192 ps
CPU time 1341.5 seconds
Started Jul 22 05:43:02 PM PDT 24
Finished Jul 22 06:05:24 PM PDT 24
Peak memory 224216 kb
Host smart-341fcbaf-29d2-4a74-9171-0a73429e2bad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707694113 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1707694113
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.877012129
Short name T298
Test name
Test status
Simulation time 67953673 ps
CPU time 1.1 seconds
Started Jul 22 05:42:56 PM PDT 24
Finished Jul 22 05:42:58 PM PDT 24
Peak memory 220752 kb
Host smart-547cd7ea-afe5-4a6c-9206-46046470b2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877012129 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.877012129
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.2639111745
Short name T718
Test name
Test status
Simulation time 24398016 ps
CPU time 1.14 seconds
Started Jul 22 05:43:02 PM PDT 24
Finished Jul 22 05:43:04 PM PDT 24
Peak memory 207076 kb
Host smart-46eef0cc-84ec-4307-b394-ea3303a0d740
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639111745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.2639111745
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.981879648
Short name T187
Test name
Test status
Simulation time 20655486 ps
CPU time 0.85 seconds
Started Jul 22 05:42:57 PM PDT 24
Finished Jul 22 05:42:58 PM PDT 24
Peak memory 216576 kb
Host smart-f76f5873-2f80-4b01-9977-ea3ed6419077
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981879648 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.981879648
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.827759684
Short name T648
Test name
Test status
Simulation time 69209647 ps
CPU time 1.27 seconds
Started Jul 22 05:42:58 PM PDT 24
Finished Jul 22 05:43:00 PM PDT 24
Peak memory 218424 kb
Host smart-2ab7ff7e-9a34-4ae0-af0e-81e5a8df0756
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827759684 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_di
sable_auto_req_mode.827759684
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.285319892
Short name T943
Test name
Test status
Simulation time 20305007 ps
CPU time 1.18 seconds
Started Jul 22 05:43:04 PM PDT 24
Finished Jul 22 05:43:07 PM PDT 24
Peak memory 220040 kb
Host smart-a45bd2f6-b803-4925-8f43-8b471e06f02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285319892 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.285319892
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.3501972353
Short name T774
Test name
Test status
Simulation time 158247440 ps
CPU time 2.35 seconds
Started Jul 22 05:43:02 PM PDT 24
Finished Jul 22 05:43:06 PM PDT 24
Peak memory 220624 kb
Host smart-b1c59445-ccac-4701-93cc-b25922f66d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501972353 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.3501972353
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.1058540090
Short name T861
Test name
Test status
Simulation time 22846280 ps
CPU time 1.09 seconds
Started Jul 22 05:42:56 PM PDT 24
Finished Jul 22 05:42:58 PM PDT 24
Peak memory 224328 kb
Host smart-dd24ba2c-8e11-4cab-995d-a35b29d93584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058540090 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.1058540090
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.3526862341
Short name T966
Test name
Test status
Simulation time 53862554 ps
CPU time 0.91 seconds
Started Jul 22 05:42:57 PM PDT 24
Finished Jul 22 05:42:59 PM PDT 24
Peak memory 215616 kb
Host smart-a8affd0f-12cc-425c-9e90-38fb5dc5a227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526862341 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.3526862341
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.1496679790
Short name T720
Test name
Test status
Simulation time 253137788 ps
CPU time 5.03 seconds
Started Jul 22 05:43:03 PM PDT 24
Finished Jul 22 05:43:10 PM PDT 24
Peak memory 220372 kb
Host smart-affc8879-b10a-49f8-8221-f2f9d65f0fc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496679790 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.1496679790
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.2263496214
Short name T508
Test name
Test status
Simulation time 37437342895 ps
CPU time 793.23 seconds
Started Jul 22 05:42:54 PM PDT 24
Finished Jul 22 05:56:08 PM PDT 24
Peak memory 217316 kb
Host smart-750356d3-bd53-48a5-8243-b75e22d0a913
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263496214 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.2263496214
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.520767408
Short name T63
Test name
Test status
Simulation time 32347108 ps
CPU time 1.32 seconds
Started Jul 22 05:43:02 PM PDT 24
Finished Jul 22 05:43:05 PM PDT 24
Peak memory 220584 kb
Host smart-fd00a719-4a44-46b2-a844-804f246bf554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520767408 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.520767408
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.3449829224
Short name T404
Test name
Test status
Simulation time 24228405 ps
CPU time 0.92 seconds
Started Jul 22 05:43:04 PM PDT 24
Finished Jul 22 05:43:07 PM PDT 24
Peak memory 215188 kb
Host smart-2a54bf5d-24a1-44b4-9c51-b85de9ff592d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449829224 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.3449829224
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.2214745403
Short name T645
Test name
Test status
Simulation time 55871217 ps
CPU time 0.84 seconds
Started Jul 22 05:43:03 PM PDT 24
Finished Jul 22 05:43:05 PM PDT 24
Peak memory 215724 kb
Host smart-ba7273ea-d018-4390-88e6-1d0db7973249
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214745403 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.2214745403
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.3573957199
Short name T552
Test name
Test status
Simulation time 64159137 ps
CPU time 1.07 seconds
Started Jul 22 05:43:02 PM PDT 24
Finished Jul 22 05:43:05 PM PDT 24
Peak memory 218592 kb
Host smart-634dc282-0214-46ee-8068-8bf237de6562
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573957199 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.3573957199
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.3970283011
Short name T998
Test name
Test status
Simulation time 44160953 ps
CPU time 1.27 seconds
Started Jul 22 05:43:03 PM PDT 24
Finished Jul 22 05:43:06 PM PDT 24
Peak memory 225968 kb
Host smart-b3c6d083-51d3-4f2a-821f-8c9049018383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970283011 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.3970283011
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.2500064451
Short name T944
Test name
Test status
Simulation time 39924083 ps
CPU time 1.56 seconds
Started Jul 22 05:43:00 PM PDT 24
Finished Jul 22 05:43:03 PM PDT 24
Peak memory 217124 kb
Host smart-15985898-a1ae-4f45-9d83-25f9a6128550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500064451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.2500064451
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.797750710
Short name T72
Test name
Test status
Simulation time 31886900 ps
CPU time 0.89 seconds
Started Jul 22 05:42:57 PM PDT 24
Finished Jul 22 05:42:59 PM PDT 24
Peak memory 215532 kb
Host smart-32d01636-cc78-45ac-a722-01ba531345cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797750710 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.797750710
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.3277781238
Short name T989
Test name
Test status
Simulation time 15314094 ps
CPU time 1 seconds
Started Jul 22 05:43:02 PM PDT 24
Finished Jul 22 05:43:05 PM PDT 24
Peak memory 215608 kb
Host smart-5e7b5ebd-e72a-4dce-be42-f6dbc4323b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277781238 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3277781238
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.205750744
Short name T674
Test name
Test status
Simulation time 729576822 ps
CPU time 4.82 seconds
Started Jul 22 05:42:54 PM PDT 24
Finished Jul 22 05:43:00 PM PDT 24
Peak memory 217680 kb
Host smart-aadf7cc2-1ee3-4de9-8d2f-f035f9d313f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205750744 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.205750744
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.1272624234
Short name T226
Test name
Test status
Simulation time 210495752748 ps
CPU time 898.41 seconds
Started Jul 22 05:42:57 PM PDT 24
Finished Jul 22 05:57:57 PM PDT 24
Peak memory 221960 kb
Host smart-9e68d5a7-5428-44d6-9c39-22b6f0b309b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272624234 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.1272624234
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.1454981628
Short name T99
Test name
Test status
Simulation time 29103399 ps
CPU time 1.32 seconds
Started Jul 22 05:43:02 PM PDT 24
Finished Jul 22 05:43:05 PM PDT 24
Peak memory 218908 kb
Host smart-703514cd-f008-43f6-b605-ec37c89bd705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454981628 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.1454981628
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.2366266508
Short name T647
Test name
Test status
Simulation time 49824818 ps
CPU time 0.84 seconds
Started Jul 22 05:42:53 PM PDT 24
Finished Jul 22 05:42:55 PM PDT 24
Peak memory 206988 kb
Host smart-3d99dfee-9d82-4fec-b2f8-4086f5713b23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366266508 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.2366266508
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.394709610
Short name T219
Test name
Test status
Simulation time 95228703 ps
CPU time 0.92 seconds
Started Jul 22 05:43:03 PM PDT 24
Finished Jul 22 05:43:05 PM PDT 24
Peak memory 216512 kb
Host smart-cb03e221-2689-40b1-b88d-dd5fbe8b2b7c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394709610 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.394709610
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.2432901513
Short name T464
Test name
Test status
Simulation time 44337327 ps
CPU time 1.09 seconds
Started Jul 22 05:43:01 PM PDT 24
Finished Jul 22 05:43:04 PM PDT 24
Peak memory 217276 kb
Host smart-7a242c54-7ae6-4ded-bfa8-d1dc9cafe474
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432901513 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.2432901513
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.2497697579
Short name T7
Test name
Test status
Simulation time 224563161 ps
CPU time 1.3 seconds
Started Jul 22 05:43:00 PM PDT 24
Finished Jul 22 05:43:02 PM PDT 24
Peak memory 219592 kb
Host smart-b24f58d9-1159-47a0-8647-d4f28e95a00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497697579 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.2497697579
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.852069472
Short name T673
Test name
Test status
Simulation time 75716921 ps
CPU time 1.2 seconds
Started Jul 22 05:42:53 PM PDT 24
Finished Jul 22 05:42:56 PM PDT 24
Peak memory 217576 kb
Host smart-4b7a0838-8264-40a0-929c-14711a514ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852069472 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.852069472
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.3502542456
Short name T579
Test name
Test status
Simulation time 32846646 ps
CPU time 1.06 seconds
Started Jul 22 05:43:01 PM PDT 24
Finished Jul 22 05:43:02 PM PDT 24
Peak memory 224344 kb
Host smart-bbd5f521-ff81-481e-9efa-5b4667de4fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502542456 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.3502542456
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.728523411
Short name T762
Test name
Test status
Simulation time 211396669 ps
CPU time 0.94 seconds
Started Jul 22 05:42:54 PM PDT 24
Finished Jul 22 05:42:56 PM PDT 24
Peak memory 215552 kb
Host smart-c8a95662-0cc0-4307-adb0-2b007a61a15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728523411 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.728523411
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.2089207
Short name T668
Test name
Test status
Simulation time 555926454 ps
CPU time 2.92 seconds
Started Jul 22 05:42:52 PM PDT 24
Finished Jul 22 05:42:56 PM PDT 24
Peak memory 217352 kb
Host smart-dadde8ee-f7c5-45e8-84ae-db71b5b05dc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089207 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.2089207
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.234853995
Short name T616
Test name
Test status
Simulation time 73069859682 ps
CPU time 1625.2 seconds
Started Jul 22 05:43:03 PM PDT 24
Finished Jul 22 06:10:10 PM PDT 24
Peak memory 224348 kb
Host smart-e700a5cf-15d6-46b3-9a51-feac8dc8649c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234853995 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.234853995
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2567110955
Short name T11
Test name
Test status
Simulation time 99068496 ps
CPU time 1.08 seconds
Started Jul 22 05:43:01 PM PDT 24
Finished Jul 22 05:43:03 PM PDT 24
Peak memory 219140 kb
Host smart-e29963fc-0cca-455e-b1c8-fb19ae281d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567110955 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2567110955
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.1281574016
Short name T96
Test name
Test status
Simulation time 35257746 ps
CPU time 0.83 seconds
Started Jul 22 05:43:11 PM PDT 24
Finished Jul 22 05:43:12 PM PDT 24
Peak memory 214956 kb
Host smart-fd904cb8-13e3-4b03-a468-815113166bde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281574016 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.1281574016
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.2537860401
Short name T644
Test name
Test status
Simulation time 31355605 ps
CPU time 0.86 seconds
Started Jul 22 05:43:04 PM PDT 24
Finished Jul 22 05:43:07 PM PDT 24
Peak memory 216516 kb
Host smart-dcd5b736-02e9-4d6b-84bc-a90df599bf39
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537860401 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2537860401
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.3076213948
Short name T778
Test name
Test status
Simulation time 30128081 ps
CPU time 1.14 seconds
Started Jul 22 05:43:10 PM PDT 24
Finished Jul 22 05:43:11 PM PDT 24
Peak memory 217232 kb
Host smart-5638c8c3-2c2a-44a2-95e2-4e3751fb6f09
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076213948 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.3076213948
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.2242311713
Short name T8
Test name
Test status
Simulation time 20204159 ps
CPU time 1.16 seconds
Started Jul 22 05:43:22 PM PDT 24
Finished Jul 22 05:43:24 PM PDT 24
Peak memory 220256 kb
Host smart-a812bd22-983e-4d9b-989c-b6f040b2d03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242311713 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.2242311713
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.3822613411
Short name T891
Test name
Test status
Simulation time 44664529 ps
CPU time 1.18 seconds
Started Jul 22 05:43:02 PM PDT 24
Finished Jul 22 05:43:05 PM PDT 24
Peak memory 220060 kb
Host smart-d9dbaec0-d767-4310-ad07-818489781ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822613411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.3822613411
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.873373661
Short name T29
Test name
Test status
Simulation time 19947721 ps
CPU time 1.14 seconds
Started Jul 22 05:43:00 PM PDT 24
Finished Jul 22 05:43:02 PM PDT 24
Peak memory 216404 kb
Host smart-0897336f-7b38-4f0e-8a6f-5e6189639f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873373661 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.873373661
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.197515670
Short name T426
Test name
Test status
Simulation time 19085459 ps
CPU time 1.04 seconds
Started Jul 22 05:43:03 PM PDT 24
Finished Jul 22 05:43:05 PM PDT 24
Peak memory 215640 kb
Host smart-fa688750-22c8-4bd4-bb43-0831d8abf37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197515670 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.197515670
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.452651341
Short name T868
Test name
Test status
Simulation time 156735005 ps
CPU time 3.3 seconds
Started Jul 22 05:43:02 PM PDT 24
Finished Jul 22 05:43:07 PM PDT 24
Peak memory 217608 kb
Host smart-062a1a8f-2858-4466-94b6-0c73414bf6fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452651341 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.452651341
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.4058453403
Short name T225
Test name
Test status
Simulation time 77300477381 ps
CPU time 1732.05 seconds
Started Jul 22 05:43:09 PM PDT 24
Finished Jul 22 06:12:02 PM PDT 24
Peak memory 225500 kb
Host smart-b7c444aa-fbef-4cc0-bf27-e3eb548056a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058453403 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.4058453403
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.4216137444
Short name T686
Test name
Test status
Simulation time 31561616 ps
CPU time 1.19 seconds
Started Jul 22 05:41:59 PM PDT 24
Finished Jul 22 05:42:00 PM PDT 24
Peak memory 216104 kb
Host smart-897f6e58-adcf-47c6-95a6-2fa83de96b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216137444 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.4216137444
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.3605653982
Short name T870
Test name
Test status
Simulation time 60952112 ps
CPU time 0.96 seconds
Started Jul 22 05:41:52 PM PDT 24
Finished Jul 22 05:41:53 PM PDT 24
Peak memory 215428 kb
Host smart-bde8b4bb-efc1-43cf-9356-285399074bc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605653982 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.3605653982
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.3748238170
Short name T116
Test name
Test status
Simulation time 74401370 ps
CPU time 1.07 seconds
Started Jul 22 05:41:53 PM PDT 24
Finished Jul 22 05:41:55 PM PDT 24
Peak memory 217316 kb
Host smart-95eaa398-410d-448d-87dc-63533907b297
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748238170 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.3748238170
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.174380553
Short name T844
Test name
Test status
Simulation time 38617734 ps
CPU time 0.88 seconds
Started Jul 22 05:41:52 PM PDT 24
Finished Jul 22 05:41:54 PM PDT 24
Peak memory 218532 kb
Host smart-8dde01e4-8fc5-4147-b24e-6fc5b0c2d513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174380553 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.174380553
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.1421728518
Short name T827
Test name
Test status
Simulation time 34866548 ps
CPU time 1.34 seconds
Started Jul 22 05:41:53 PM PDT 24
Finished Jul 22 05:41:56 PM PDT 24
Peak memory 219716 kb
Host smart-a271873d-ef19-485d-b474-f96011aceb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421728518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1421728518
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.3723208142
Short name T463
Test name
Test status
Simulation time 35777921 ps
CPU time 0.88 seconds
Started Jul 22 05:41:55 PM PDT 24
Finished Jul 22 05:41:57 PM PDT 24
Peak memory 215728 kb
Host smart-19bcbea8-e306-48c9-b2b2-086651c629f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723208142 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3723208142
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.3546366984
Short name T291
Test name
Test status
Simulation time 24178599 ps
CPU time 0.91 seconds
Started Jul 22 05:41:53 PM PDT 24
Finished Jul 22 05:41:54 PM PDT 24
Peak memory 207436 kb
Host smart-383f3a71-d990-471b-bd95-dc3f9324b467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546366984 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.3546366984
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.3884419792
Short name T57
Test name
Test status
Simulation time 1019906520 ps
CPU time 8.46 seconds
Started Jul 22 05:41:56 PM PDT 24
Finished Jul 22 05:42:05 PM PDT 24
Peak memory 237552 kb
Host smart-dde7476d-2966-4a0c-aa54-f2daf372b1e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884419792 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.3884419792
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.2241024984
Short name T499
Test name
Test status
Simulation time 28965059 ps
CPU time 0.95 seconds
Started Jul 22 05:41:54 PM PDT 24
Finished Jul 22 05:41:56 PM PDT 24
Peak memory 215564 kb
Host smart-5994cfb2-dd34-4079-8c4d-f2aef014d54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241024984 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.2241024984
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.3670491532
Short name T476
Test name
Test status
Simulation time 595667588 ps
CPU time 3.9 seconds
Started Jul 22 05:41:52 PM PDT 24
Finished Jul 22 05:41:57 PM PDT 24
Peak memory 215596 kb
Host smart-9d1b1981-fd27-416f-a266-e39801b64b67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670491532 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.3670491532
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.46470762
Short name T228
Test name
Test status
Simulation time 425384473143 ps
CPU time 1761.59 seconds
Started Jul 22 05:41:55 PM PDT 24
Finished Jul 22 06:11:18 PM PDT 24
Peak memory 225360 kb
Host smart-481790da-88a4-4516-ad68-c7ed36748ca1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46470762 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.46470762
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.3717914051
Short name T957
Test name
Test status
Simulation time 23275545 ps
CPU time 1.18 seconds
Started Jul 22 05:43:09 PM PDT 24
Finished Jul 22 05:43:10 PM PDT 24
Peak memory 221304 kb
Host smart-8471aaf8-914f-4716-a37e-8a77b97bfe45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717914051 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.3717914051
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.1968383822
Short name T710
Test name
Test status
Simulation time 144354867 ps
CPU time 0.85 seconds
Started Jul 22 05:43:02 PM PDT 24
Finished Jul 22 05:43:03 PM PDT 24
Peak memory 214984 kb
Host smart-6b485f79-2a4a-4fc2-8e08-9c4be08c2d27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968383822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1968383822
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.4053981296
Short name T160
Test name
Test status
Simulation time 78778372 ps
CPU time 0.89 seconds
Started Jul 22 05:43:09 PM PDT 24
Finished Jul 22 05:43:10 PM PDT 24
Peak memory 216772 kb
Host smart-f241fd84-4a5c-4e57-8a8f-82f199883ab5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053981296 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.4053981296
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.2785125740
Short name T796
Test name
Test status
Simulation time 51998077 ps
CPU time 1.05 seconds
Started Jul 22 05:43:03 PM PDT 24
Finished Jul 22 05:43:06 PM PDT 24
Peak memory 218816 kb
Host smart-b4b4f933-9d1b-4fe0-b809-243debc51695
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785125740 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.2785125740
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.4046552368
Short name T2
Test name
Test status
Simulation time 17979435 ps
CPU time 1.03 seconds
Started Jul 22 05:43:11 PM PDT 24
Finished Jul 22 05:43:13 PM PDT 24
Peak memory 218616 kb
Host smart-9deca79a-bdcd-4149-a560-62837a97ccf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046552368 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.4046552368
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.1918937837
Short name T341
Test name
Test status
Simulation time 85420982 ps
CPU time 1.33 seconds
Started Jul 22 05:43:01 PM PDT 24
Finished Jul 22 05:43:03 PM PDT 24
Peak memory 220000 kb
Host smart-984ea64d-75ae-46cd-8d1a-0968d5be62ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918937837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1918937837
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.1533770266
Short name T489
Test name
Test status
Simulation time 22114939 ps
CPU time 1.11 seconds
Started Jul 22 05:43:12 PM PDT 24
Finished Jul 22 05:43:13 PM PDT 24
Peak memory 215756 kb
Host smart-8062aea7-2e87-4a7a-872c-f343803b3c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533770266 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.1533770266
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.4078796857
Short name T518
Test name
Test status
Simulation time 15846031 ps
CPU time 1 seconds
Started Jul 22 05:43:12 PM PDT 24
Finished Jul 22 05:43:13 PM PDT 24
Peak memory 215628 kb
Host smart-752fdd4e-73f5-4d02-a7b6-538d33bea1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078796857 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.4078796857
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.478345536
Short name T58
Test name
Test status
Simulation time 467380143 ps
CPU time 4.48 seconds
Started Jul 22 05:43:01 PM PDT 24
Finished Jul 22 05:43:07 PM PDT 24
Peak memory 217448 kb
Host smart-8eea6550-c2fb-42bd-80bf-7d06cf798c72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478345536 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.478345536
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2602333430
Short name T486
Test name
Test status
Simulation time 14099504144 ps
CPU time 244.16 seconds
Started Jul 22 05:43:08 PM PDT 24
Finished Jul 22 05:47:13 PM PDT 24
Peak memory 218868 kb
Host smart-a2128b13-752c-4084-b07d-17ca43ac7537
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602333430 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.2602333430
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.2053708374
Short name T725
Test name
Test status
Simulation time 130641053 ps
CPU time 1.2 seconds
Started Jul 22 05:43:02 PM PDT 24
Finished Jul 22 05:43:04 PM PDT 24
Peak memory 220464 kb
Host smart-16b77684-fb8b-4bb9-9a13-65dcb034a7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053708374 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.2053708374
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.3119414046
Short name T716
Test name
Test status
Simulation time 24087746 ps
CPU time 0.84 seconds
Started Jul 22 05:43:01 PM PDT 24
Finished Jul 22 05:43:03 PM PDT 24
Peak memory 215164 kb
Host smart-b2dc0b87-606e-403e-9284-527d50db183a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119414046 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.3119414046
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.873522184
Short name T186
Test name
Test status
Simulation time 11132220 ps
CPU time 0.87 seconds
Started Jul 22 05:43:04 PM PDT 24
Finished Jul 22 05:43:07 PM PDT 24
Peak memory 216556 kb
Host smart-17f8580c-0ff9-487e-84e0-53826c9ccfe6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873522184 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.873522184
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.72033760
Short name T993
Test name
Test status
Simulation time 45565476 ps
CPU time 1.52 seconds
Started Jul 22 05:43:06 PM PDT 24
Finished Jul 22 05:43:08 PM PDT 24
Peak memory 217224 kb
Host smart-f18489ce-a6f5-4598-b9ac-eede51f5a4b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72033760 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_dis
able_auto_req_mode.72033760
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.1543972325
Short name T964
Test name
Test status
Simulation time 19399656 ps
CPU time 1.17 seconds
Started Jul 22 05:43:01 PM PDT 24
Finished Jul 22 05:43:03 PM PDT 24
Peak memory 224268 kb
Host smart-4f8d164c-7fd7-43d7-9e3d-c9300e741362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543972325 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.1543972325
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.3879513883
Short name T515
Test name
Test status
Simulation time 93066071 ps
CPU time 1.05 seconds
Started Jul 22 05:43:03 PM PDT 24
Finished Jul 22 05:43:06 PM PDT 24
Peak memory 217480 kb
Host smart-da9441c8-9210-420b-b2aa-b966c794a304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879513883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.3879513883
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.2675809803
Short name T590
Test name
Test status
Simulation time 36171489 ps
CPU time 1.01 seconds
Started Jul 22 05:43:11 PM PDT 24
Finished Jul 22 05:43:13 PM PDT 24
Peak memory 224084 kb
Host smart-e07c1e3b-e9f9-415c-853d-c191632a3be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675809803 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2675809803
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.1451578269
Short name T76
Test name
Test status
Simulation time 37466177 ps
CPU time 0.86 seconds
Started Jul 22 05:43:10 PM PDT 24
Finished Jul 22 05:43:11 PM PDT 24
Peak memory 215556 kb
Host smart-34e089c8-4271-4c53-902f-a77ca8e557ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451578269 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.1451578269
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.3001935768
Short name T241
Test name
Test status
Simulation time 814738345 ps
CPU time 4.87 seconds
Started Jul 22 05:43:04 PM PDT 24
Finished Jul 22 05:43:10 PM PDT 24
Peak memory 220548 kb
Host smart-67934089-012c-415b-93bd-36dda374ef03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001935768 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3001935768
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.2137448244
Short name T90
Test name
Test status
Simulation time 50560619956 ps
CPU time 1247.25 seconds
Started Jul 22 05:43:11 PM PDT 24
Finished Jul 22 06:04:00 PM PDT 24
Peak memory 223680 kb
Host smart-79107c6f-25a1-417b-b487-d5e5367c98fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137448244 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.2137448244
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.2003658921
Short name T838
Test name
Test status
Simulation time 46244188 ps
CPU time 1.18 seconds
Started Jul 22 05:43:04 PM PDT 24
Finished Jul 22 05:43:07 PM PDT 24
Peak memory 216060 kb
Host smart-0a3194c5-c087-4dc8-8fdd-5f38207b01e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003658921 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.2003658921
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.464738603
Short name T660
Test name
Test status
Simulation time 25090424 ps
CPU time 0.85 seconds
Started Jul 22 05:43:17 PM PDT 24
Finished Jul 22 05:43:19 PM PDT 24
Peak memory 207032 kb
Host smart-5b73ba38-29e4-4428-8c4a-89c658a0719b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464738603 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.464738603
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.1726040019
Short name T875
Test name
Test status
Simulation time 41573809 ps
CPU time 0.87 seconds
Started Jul 22 05:43:11 PM PDT 24
Finished Jul 22 05:43:12 PM PDT 24
Peak memory 216156 kb
Host smart-83cfd42d-7ed2-4b5f-b61b-2ad1e753d5bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726040019 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1726040019
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.3634595342
Short name T614
Test name
Test status
Simulation time 29517574 ps
CPU time 1.06 seconds
Started Jul 22 05:43:02 PM PDT 24
Finished Jul 22 05:43:05 PM PDT 24
Peak memory 218960 kb
Host smart-025fc37e-dce7-4f24-aac5-d9465be7f92e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634595342 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.3634595342
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.2040284002
Short name T649
Test name
Test status
Simulation time 29697785 ps
CPU time 0.98 seconds
Started Jul 22 05:43:10 PM PDT 24
Finished Jul 22 05:43:11 PM PDT 24
Peak memory 224160 kb
Host smart-2b836801-270e-4d59-ac67-26d2d5a67cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040284002 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.2040284002
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.1797090998
Short name T383
Test name
Test status
Simulation time 74822551 ps
CPU time 1.08 seconds
Started Jul 22 05:43:04 PM PDT 24
Finished Jul 22 05:43:06 PM PDT 24
Peak memory 217480 kb
Host smart-6e6b3a32-21df-4dbb-99b5-7ac1f360301e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797090998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.1797090998
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_smoke.3423619845
Short name T564
Test name
Test status
Simulation time 23530395 ps
CPU time 0.89 seconds
Started Jul 22 05:43:10 PM PDT 24
Finished Jul 22 05:43:11 PM PDT 24
Peak memory 215536 kb
Host smart-a71021ce-bb96-4037-85c7-777a2b3b88d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423619845 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3423619845
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.1708873387
Short name T414
Test name
Test status
Simulation time 58192842 ps
CPU time 1.78 seconds
Started Jul 22 05:43:03 PM PDT 24
Finished Jul 22 05:43:07 PM PDT 24
Peak memory 217528 kb
Host smart-7dff230c-ad41-45a2-b9e3-6771a27db64c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708873387 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1708873387
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.210343186
Short name T980
Test name
Test status
Simulation time 20356224213 ps
CPU time 449.44 seconds
Started Jul 22 05:43:10 PM PDT 24
Finished Jul 22 05:50:40 PM PDT 24
Peak memory 224096 kb
Host smart-53f22e5f-e3d2-4048-b4df-69c95ae76b03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210343186 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.210343186
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.774083800
Short name T111
Test name
Test status
Simulation time 46848935 ps
CPU time 1.27 seconds
Started Jul 22 05:43:13 PM PDT 24
Finished Jul 22 05:43:16 PM PDT 24
Peak memory 219820 kb
Host smart-f880f5df-d07d-485a-9e71-a590948a696f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774083800 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.774083800
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.1932955748
Short name T996
Test name
Test status
Simulation time 18563547 ps
CPU time 1.05 seconds
Started Jul 22 05:43:14 PM PDT 24
Finished Jul 22 05:43:16 PM PDT 24
Peak memory 207044 kb
Host smart-4a366c7c-4485-4609-8bf4-5ffcbe6d7b43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932955748 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.1932955748
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.790773511
Short name T910
Test name
Test status
Simulation time 10591037 ps
CPU time 0.86 seconds
Started Jul 22 05:43:14 PM PDT 24
Finished Jul 22 05:43:16 PM PDT 24
Peak memory 216796 kb
Host smart-5600f529-001b-40f3-86ae-2967526db525
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790773511 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.790773511
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.3455229849
Short name T846
Test name
Test status
Simulation time 137246844 ps
CPU time 1.26 seconds
Started Jul 22 05:43:12 PM PDT 24
Finished Jul 22 05:43:14 PM PDT 24
Peak memory 217336 kb
Host smart-9786f097-98bd-4d36-a342-9e9ee22fac1d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455229849 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.3455229849
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.3548832989
Short name T589
Test name
Test status
Simulation time 18156811 ps
CPU time 1.1 seconds
Started Jul 22 05:43:13 PM PDT 24
Finished Jul 22 05:43:15 PM PDT 24
Peak memory 224292 kb
Host smart-58209d78-1958-4d45-8108-0795f0023c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548832989 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.3548832989
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.2359866657
Short name T899
Test name
Test status
Simulation time 64746381 ps
CPU time 1.5 seconds
Started Jul 22 05:43:14 PM PDT 24
Finished Jul 22 05:43:17 PM PDT 24
Peak memory 218968 kb
Host smart-095862ee-f812-4c1f-b213-9841d6a8f852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359866657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.2359866657
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.2538335054
Short name T960
Test name
Test status
Simulation time 24734327 ps
CPU time 1 seconds
Started Jul 22 05:45:37 PM PDT 24
Finished Jul 22 05:45:39 PM PDT 24
Peak memory 215928 kb
Host smart-ba0bc865-98fd-4303-a9ed-7d12e53b04fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538335054 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.2538335054
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.2160674822
Short name T935
Test name
Test status
Simulation time 26305579 ps
CPU time 1 seconds
Started Jul 22 05:43:14 PM PDT 24
Finished Jul 22 05:43:16 PM PDT 24
Peak memory 215572 kb
Host smart-b03ba690-9418-421b-9f08-7b3bab75e292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160674822 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2160674822
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.485776229
Short name T853
Test name
Test status
Simulation time 585064227 ps
CPU time 3.63 seconds
Started Jul 22 05:43:15 PM PDT 24
Finished Jul 22 05:43:20 PM PDT 24
Peak memory 217652 kb
Host smart-8c5cd3a8-0c24-4f51-86c2-18d59290c307
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485776229 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.485776229
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2749809247
Short name T820
Test name
Test status
Simulation time 50457227646 ps
CPU time 1117.01 seconds
Started Jul 22 05:43:13 PM PDT 24
Finished Jul 22 06:01:51 PM PDT 24
Peak memory 224008 kb
Host smart-395c4738-5d15-405b-b401-30d837f28712
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749809247 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.2749809247
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.802563477
Short name T758
Test name
Test status
Simulation time 118563790 ps
CPU time 1.2 seconds
Started Jul 22 05:43:14 PM PDT 24
Finished Jul 22 05:43:17 PM PDT 24
Peak memory 221024 kb
Host smart-9afdc1e1-bd56-4fd8-973c-25eb8dda1169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802563477 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.802563477
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.3148858904
Short name T353
Test name
Test status
Simulation time 67818314 ps
CPU time 0.86 seconds
Started Jul 22 05:43:15 PM PDT 24
Finished Jul 22 05:43:17 PM PDT 24
Peak memory 214960 kb
Host smart-e5bcd1b0-b266-45fc-95aa-a7cf6d6f5be6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148858904 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3148858904
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.58026284
Short name T788
Test name
Test status
Simulation time 12003944 ps
CPU time 0.92 seconds
Started Jul 22 05:43:13 PM PDT 24
Finished Jul 22 05:43:15 PM PDT 24
Peak memory 216740 kb
Host smart-dbff43bc-fdf7-48fc-b20e-f9b359ad8609
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58026284 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.58026284
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.2308871974
Short name T862
Test name
Test status
Simulation time 34464815 ps
CPU time 1.17 seconds
Started Jul 22 05:43:13 PM PDT 24
Finished Jul 22 05:43:15 PM PDT 24
Peak memory 217140 kb
Host smart-bc0523ce-efa8-486f-b4c4-376b5737872a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308871974 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.2308871974
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_genbits.4040967871
Short name T887
Test name
Test status
Simulation time 91468758 ps
CPU time 1.35 seconds
Started Jul 22 05:43:15 PM PDT 24
Finished Jul 22 05:43:17 PM PDT 24
Peak memory 218656 kb
Host smart-f850c53b-7fad-4a6e-ae62-880582cd7272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040967871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.4040967871
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.1105558186
Short name T556
Test name
Test status
Simulation time 27847536 ps
CPU time 1.04 seconds
Started Jul 22 05:43:16 PM PDT 24
Finished Jul 22 05:43:18 PM PDT 24
Peak memory 224272 kb
Host smart-6c8b4f24-cdcd-4cb2-8224-3ea9d2e24f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105558186 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1105558186
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.2113423443
Short name T741
Test name
Test status
Simulation time 40467560 ps
CPU time 0.89 seconds
Started Jul 22 05:43:10 PM PDT 24
Finished Jul 22 05:43:12 PM PDT 24
Peak memory 215632 kb
Host smart-81be62ed-58d1-4230-a29b-b9b02db955bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113423443 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.2113423443
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.8878566
Short name T775
Test name
Test status
Simulation time 251483999 ps
CPU time 4.77 seconds
Started Jul 22 05:43:14 PM PDT 24
Finished Jul 22 05:43:20 PM PDT 24
Peak memory 215692 kb
Host smart-ebac48a8-2da5-4d8a-9ca6-ecbc3a3f99b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8878566 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.8878566
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.1098772204
Short name T981
Test name
Test status
Simulation time 6424661254 ps
CPU time 135.18 seconds
Started Jul 22 05:43:15 PM PDT 24
Finished Jul 22 05:45:31 PM PDT 24
Peak memory 217984 kb
Host smart-9535e497-4830-4b78-b592-c3f871f04c57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098772204 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.1098772204
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.3994548410
Short name T780
Test name
Test status
Simulation time 43259829 ps
CPU time 1.22 seconds
Started Jul 22 05:43:14 PM PDT 24
Finished Jul 22 05:43:16 PM PDT 24
Peak memory 219968 kb
Host smart-05b5db3b-26bc-4749-93dc-5508a64fa9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994548410 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.3994548410
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.3215166357
Short name T527
Test name
Test status
Simulation time 22726815 ps
CPU time 0.84 seconds
Started Jul 22 05:43:18 PM PDT 24
Finished Jul 22 05:43:20 PM PDT 24
Peak memory 207004 kb
Host smart-8c2cbe63-ba24-4371-90ec-6991ecb07818
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215166357 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3215166357
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.3827884519
Short name T178
Test name
Test status
Simulation time 29966772 ps
CPU time 0.84 seconds
Started Jul 22 05:43:15 PM PDT 24
Finished Jul 22 05:43:17 PM PDT 24
Peak memory 216504 kb
Host smart-da55ce99-23a3-47b1-a44c-7e6d506b07b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827884519 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3827884519
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.2378762863
Short name T129
Test name
Test status
Simulation time 41654862 ps
CPU time 1.24 seconds
Started Jul 22 05:43:13 PM PDT 24
Finished Jul 22 05:43:15 PM PDT 24
Peak memory 218700 kb
Host smart-674d0741-056e-4602-aff7-94227f95d98b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378762863 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.2378762863
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.1787180184
Short name T106
Test name
Test status
Simulation time 34231281 ps
CPU time 1.04 seconds
Started Jul 22 05:43:13 PM PDT 24
Finished Jul 22 05:43:16 PM PDT 24
Peak memory 219988 kb
Host smart-30cd87a0-372c-427f-a918-e770637e24e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787180184 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1787180184
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.2271463571
Short name T452
Test name
Test status
Simulation time 41981822 ps
CPU time 1.28 seconds
Started Jul 22 05:43:18 PM PDT 24
Finished Jul 22 05:43:20 PM PDT 24
Peak memory 215620 kb
Host smart-08a04b42-b188-4c04-a277-83b0cc8d09ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271463571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.2271463571
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.2889655056
Short name T15
Test name
Test status
Simulation time 20815273 ps
CPU time 1.23 seconds
Started Jul 22 05:43:13 PM PDT 24
Finished Jul 22 05:43:16 PM PDT 24
Peak memory 224368 kb
Host smart-2dd97446-b084-412b-9495-d5d3961cbdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889655056 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.2889655056
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.2880687666
Short name T494
Test name
Test status
Simulation time 19760289 ps
CPU time 1.02 seconds
Started Jul 22 05:43:12 PM PDT 24
Finished Jul 22 05:43:14 PM PDT 24
Peak memory 215568 kb
Host smart-1e6915b2-ba00-4ae7-994c-fc4d9b9f20d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880687666 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.2880687666
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.2622918343
Short name T530
Test name
Test status
Simulation time 669707110 ps
CPU time 4.16 seconds
Started Jul 22 05:43:14 PM PDT 24
Finished Jul 22 05:43:19 PM PDT 24
Peak memory 215580 kb
Host smart-f81739c8-1a6b-4744-b54c-be384bf766f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622918343 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.2622918343
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3604547079
Short name T592
Test name
Test status
Simulation time 63879154290 ps
CPU time 362.01 seconds
Started Jul 22 05:43:14 PM PDT 24
Finished Jul 22 05:49:17 PM PDT 24
Peak memory 223904 kb
Host smart-93a1fbec-2d61-47d4-8f38-5da5e529e171
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604547079 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.3604547079
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.3397259422
Short name T955
Test name
Test status
Simulation time 45718188 ps
CPU time 1.11 seconds
Started Jul 22 05:43:11 PM PDT 24
Finished Jul 22 05:43:13 PM PDT 24
Peak memory 216088 kb
Host smart-0ecc8cbd-6d69-4dde-9361-259371d6e009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397259422 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.3397259422
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.2196968226
Short name T702
Test name
Test status
Simulation time 70966022 ps
CPU time 0.86 seconds
Started Jul 22 05:43:13 PM PDT 24
Finished Jul 22 05:43:14 PM PDT 24
Peak memory 206840 kb
Host smart-bb497161-c3ac-4f77-9dce-fb6a4f52932f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196968226 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2196968226
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.3375962203
Short name T792
Test name
Test status
Simulation time 22493641 ps
CPU time 0.88 seconds
Started Jul 22 05:43:13 PM PDT 24
Finished Jul 22 05:43:15 PM PDT 24
Peak memory 216612 kb
Host smart-67548c3a-10c9-473f-ae0f-076dbcfd6c58
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375962203 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.3375962203
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.342982350
Short name T146
Test name
Test status
Simulation time 32819148 ps
CPU time 1.12 seconds
Started Jul 22 05:43:11 PM PDT 24
Finished Jul 22 05:43:13 PM PDT 24
Peak memory 217244 kb
Host smart-7670144e-61d1-4fba-884d-f9ab29a08eeb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342982350 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_di
sable_auto_req_mode.342982350
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.3054731784
Short name T973
Test name
Test status
Simulation time 21569889 ps
CPU time 0.91 seconds
Started Jul 22 05:43:29 PM PDT 24
Finished Jul 22 05:43:30 PM PDT 24
Peak memory 218512 kb
Host smart-31af034f-f6f8-4500-98bc-94ef1d59e6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054731784 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.3054731784
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.4043051668
Short name T470
Test name
Test status
Simulation time 29421054 ps
CPU time 1.18 seconds
Started Jul 22 05:43:17 PM PDT 24
Finished Jul 22 05:43:19 PM PDT 24
Peak memory 218824 kb
Host smart-5feba085-0082-4b1e-a37c-d4b5b706796f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043051668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.4043051668
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.2907373276
Short name T53
Test name
Test status
Simulation time 29560226 ps
CPU time 1.08 seconds
Started Jul 22 05:43:18 PM PDT 24
Finished Jul 22 05:43:20 PM PDT 24
Peak memory 224368 kb
Host smart-7e29d6ff-a71d-492c-be81-c11f09296b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907373276 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.2907373276
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.2837410001
Short name T586
Test name
Test status
Simulation time 27886378 ps
CPU time 1.03 seconds
Started Jul 22 05:43:14 PM PDT 24
Finished Jul 22 05:43:17 PM PDT 24
Peak memory 215852 kb
Host smart-dd93a557-b295-4700-8f73-29ede209e46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837410001 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.2837410001
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.3309434744
Short name T777
Test name
Test status
Simulation time 132017721 ps
CPU time 1.47 seconds
Started Jul 22 05:43:14 PM PDT 24
Finished Jul 22 05:43:17 PM PDT 24
Peak memory 215544 kb
Host smart-f92685c1-c5f2-4762-9311-3211f2b7ac8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309434744 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.3309434744
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.1722011951
Short name T233
Test name
Test status
Simulation time 68174125623 ps
CPU time 745.64 seconds
Started Jul 22 05:43:14 PM PDT 24
Finished Jul 22 05:55:40 PM PDT 24
Peak memory 224072 kb
Host smart-f6c5a205-c0f1-4b4c-9a22-391137218d8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722011951 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.1722011951
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.1587146199
Short name T631
Test name
Test status
Simulation time 53245841 ps
CPU time 1.26 seconds
Started Jul 22 05:43:31 PM PDT 24
Finished Jul 22 05:43:32 PM PDT 24
Peak memory 220216 kb
Host smart-d0f7b854-ab50-4a9c-b8be-707df54c9616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587146199 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.1587146199
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.1956009940
Short name T621
Test name
Test status
Simulation time 14654895 ps
CPU time 0.94 seconds
Started Jul 22 05:43:26 PM PDT 24
Finished Jul 22 05:43:28 PM PDT 24
Peak memory 207036 kb
Host smart-a9400456-731a-4601-b3ae-23980fa067ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956009940 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1956009940
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.3945888562
Short name T985
Test name
Test status
Simulation time 12326720 ps
CPU time 0.86 seconds
Started Jul 22 05:43:31 PM PDT 24
Finished Jul 22 05:43:33 PM PDT 24
Peak memory 216740 kb
Host smart-3585c907-098a-48b7-bc32-13ab0a6ed8f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945888562 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3945888562
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.3657626950
Short name T147
Test name
Test status
Simulation time 20430039 ps
CPU time 1.01 seconds
Started Jul 22 05:43:22 PM PDT 24
Finished Jul 22 05:43:24 PM PDT 24
Peak memory 217328 kb
Host smart-4bc417f3-dc3d-4093-a45c-556bd66a0b83
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657626950 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.3657626950
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.3412238027
Short name T109
Test name
Test status
Simulation time 24897893 ps
CPU time 1.19 seconds
Started Jul 22 05:43:25 PM PDT 24
Finished Jul 22 05:43:26 PM PDT 24
Peak memory 221000 kb
Host smart-f8af7c6b-bd46-45fa-a7a4-20df81d925f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412238027 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3412238027
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.2848225411
Short name T74
Test name
Test status
Simulation time 84109566 ps
CPU time 1.98 seconds
Started Jul 22 05:43:11 PM PDT 24
Finished Jul 22 05:43:14 PM PDT 24
Peak memory 218880 kb
Host smart-44df6bd4-e8e0-4c15-9d75-aae730e7f07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848225411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.2848225411
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.4170529425
Short name T449
Test name
Test status
Simulation time 33259189 ps
CPU time 0.88 seconds
Started Jul 22 05:43:22 PM PDT 24
Finished Jul 22 05:43:24 PM PDT 24
Peak memory 215740 kb
Host smart-98e420b0-0edf-4eed-b574-7d65f4c312c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170529425 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.4170529425
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.2483685545
Short name T849
Test name
Test status
Simulation time 16103819 ps
CPU time 1.06 seconds
Started Jul 22 05:43:13 PM PDT 24
Finished Jul 22 05:43:16 PM PDT 24
Peak memory 215636 kb
Host smart-d9caae57-f33a-4c15-88ab-70fbb09ccf66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483685545 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.2483685545
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.334962675
Short name T415
Test name
Test status
Simulation time 417471024 ps
CPU time 7.86 seconds
Started Jul 22 05:43:14 PM PDT 24
Finished Jul 22 05:43:23 PM PDT 24
Peak memory 215696 kb
Host smart-8a2ada6a-2463-44c0-bfb1-14ffb0800c09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334962675 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.334962675
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3847205244
Short name T743
Test name
Test status
Simulation time 38663581397 ps
CPU time 910.31 seconds
Started Jul 22 05:43:38 PM PDT 24
Finished Jul 22 05:58:49 PM PDT 24
Peak memory 220624 kb
Host smart-1b5dbf24-7e07-48eb-ba54-1779f836fa52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847205244 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3847205244
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.534495001
Short name T706
Test name
Test status
Simulation time 42005884 ps
CPU time 1.11 seconds
Started Jul 22 05:43:24 PM PDT 24
Finished Jul 22 05:43:25 PM PDT 24
Peak memory 219784 kb
Host smart-a5760892-480d-491c-ac78-de866aaad1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534495001 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.534495001
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.3667458646
Short name T933
Test name
Test status
Simulation time 26834084 ps
CPU time 0.86 seconds
Started Jul 22 05:43:21 PM PDT 24
Finished Jul 22 05:43:23 PM PDT 24
Peak memory 215148 kb
Host smart-98f8d8b7-1f07-49dc-b4e9-3aa28f328e74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667458646 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.3667458646
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.4222782491
Short name T971
Test name
Test status
Simulation time 11440859 ps
CPU time 0.84 seconds
Started Jul 22 05:43:26 PM PDT 24
Finished Jul 22 05:43:27 PM PDT 24
Peak memory 216720 kb
Host smart-9ddbf8c3-54fd-4e5a-ae8b-b3b5d50f5588
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222782491 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.4222782491
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.1116644717
Short name T204
Test name
Test status
Simulation time 66269312 ps
CPU time 1.07 seconds
Started Jul 22 05:43:25 PM PDT 24
Finished Jul 22 05:43:27 PM PDT 24
Peak memory 216956 kb
Host smart-a23a66de-96f3-4b55-9c71-a61287de5edc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116644717 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.1116644717
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.3523448915
Short name T55
Test name
Test status
Simulation time 70751625 ps
CPU time 1.15 seconds
Started Jul 22 05:43:24 PM PDT 24
Finished Jul 22 05:43:26 PM PDT 24
Peak memory 226016 kb
Host smart-3aea129e-3397-42aa-98c3-c7cec45e9f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523448915 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3523448915
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.815656205
Short name T543
Test name
Test status
Simulation time 39476043 ps
CPU time 1.49 seconds
Started Jul 22 05:43:22 PM PDT 24
Finished Jul 22 05:43:25 PM PDT 24
Peak memory 217564 kb
Host smart-7019ebe0-ac8f-4814-a2b7-50badc498e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815656205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.815656205
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_smoke.3597468312
Short name T354
Test name
Test status
Simulation time 59100830 ps
CPU time 0.95 seconds
Started Jul 22 05:43:26 PM PDT 24
Finished Jul 22 05:43:27 PM PDT 24
Peak memory 215636 kb
Host smart-f14bc12b-5272-4653-84fb-08e8486e81ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597468312 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.3597468312
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.1459450099
Short name T787
Test name
Test status
Simulation time 335664069 ps
CPU time 6.41 seconds
Started Jul 22 05:43:25 PM PDT 24
Finished Jul 22 05:43:32 PM PDT 24
Peak memory 217464 kb
Host smart-f2f32232-7d56-4580-aafe-617e2fe35eb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459450099 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1459450099
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.4216064861
Short name T446
Test name
Test status
Simulation time 22474287309 ps
CPU time 565.24 seconds
Started Jul 22 05:43:25 PM PDT 24
Finished Jul 22 05:52:50 PM PDT 24
Peak memory 217708 kb
Host smart-f271a0c3-edb2-4dcb-bc17-c0ed32c539b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216064861 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.4216064861
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.1426823860
Short name T808
Test name
Test status
Simulation time 36936461 ps
CPU time 1.16 seconds
Started Jul 22 05:43:27 PM PDT 24
Finished Jul 22 05:43:29 PM PDT 24
Peak memory 219620 kb
Host smart-d549732a-47d9-4a0b-aa91-03a59f92bbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426823860 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.1426823860
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.2484269565
Short name T583
Test name
Test status
Simulation time 39101386 ps
CPU time 0.86 seconds
Started Jul 22 05:43:27 PM PDT 24
Finished Jul 22 05:43:29 PM PDT 24
Peak memory 206828 kb
Host smart-c5ac12c7-644e-4f44-989f-a2f8ac1245f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484269565 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.2484269565
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.255557931
Short name T169
Test name
Test status
Simulation time 25450571 ps
CPU time 0.85 seconds
Started Jul 22 05:43:24 PM PDT 24
Finished Jul 22 05:43:25 PM PDT 24
Peak memory 216712 kb
Host smart-677802f9-8e5c-42ef-bcd3-5f1bf0abc4a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255557931 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.255557931
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.643151102
Short name T36
Test name
Test status
Simulation time 91650738 ps
CPU time 1.12 seconds
Started Jul 22 05:43:27 PM PDT 24
Finished Jul 22 05:43:29 PM PDT 24
Peak memory 217224 kb
Host smart-5c9f2996-639f-4866-b95e-a2319b588790
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643151102 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_di
sable_auto_req_mode.643151102
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.4019379780
Short name T66
Test name
Test status
Simulation time 30994940 ps
CPU time 1.22 seconds
Started Jul 22 05:43:20 PM PDT 24
Finished Jul 22 05:43:22 PM PDT 24
Peak memory 220108 kb
Host smart-79bf6be7-8bec-4913-9b46-ee4dda4b00d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019379780 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.4019379780
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.537072748
Short name T945
Test name
Test status
Simulation time 43696594 ps
CPU time 1.36 seconds
Started Jul 22 05:45:37 PM PDT 24
Finished Jul 22 05:45:39 PM PDT 24
Peak memory 215724 kb
Host smart-558f785b-0c69-4ebc-82a4-cf223a822df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537072748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.537072748
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.3157372172
Short name T88
Test name
Test status
Simulation time 36708405 ps
CPU time 0.84 seconds
Started Jul 22 05:43:27 PM PDT 24
Finished Jul 22 05:43:28 PM PDT 24
Peak memory 216096 kb
Host smart-b9ec5dc4-0b24-44cb-8dae-24a5f4eedcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157372172 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.3157372172
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.1769180212
Short name T551
Test name
Test status
Simulation time 17480410 ps
CPU time 1.01 seconds
Started Jul 22 05:43:26 PM PDT 24
Finished Jul 22 05:43:28 PM PDT 24
Peak memory 215788 kb
Host smart-52d3f789-2c1b-4197-b1ad-7127e759bf85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769180212 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.1769180212
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1455415360
Short name T914
Test name
Test status
Simulation time 133749619921 ps
CPU time 1358.74 seconds
Started Jul 22 05:43:23 PM PDT 24
Finished Jul 22 06:06:02 PM PDT 24
Peak memory 224436 kb
Host smart-2a38a52e-9108-4e01-953a-9c06fbcddf0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455415360 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1455415360
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.4084852408
Short name T289
Test name
Test status
Simulation time 35682568 ps
CPU time 1.18 seconds
Started Jul 22 05:42:00 PM PDT 24
Finished Jul 22 05:42:02 PM PDT 24
Peak memory 220440 kb
Host smart-bcebfa77-1e10-4abb-b11f-404c443327e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084852408 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.4084852408
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.3231851838
Short name T601
Test name
Test status
Simulation time 25671719 ps
CPU time 0.9 seconds
Started Jul 22 05:41:51 PM PDT 24
Finished Jul 22 05:41:52 PM PDT 24
Peak memory 206940 kb
Host smart-ec32b6cb-b535-480a-8cb4-f94b690738c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231851838 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.3231851838
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.966111710
Short name T918
Test name
Test status
Simulation time 32222273 ps
CPU time 0.82 seconds
Started Jul 22 05:41:54 PM PDT 24
Finished Jul 22 05:41:56 PM PDT 24
Peak memory 216696 kb
Host smart-4caac625-816b-47a4-ab69-49c37012629a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966111710 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.966111710
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.3617603154
Short name T142
Test name
Test status
Simulation time 147692548 ps
CPU time 1.12 seconds
Started Jul 22 05:41:52 PM PDT 24
Finished Jul 22 05:41:54 PM PDT 24
Peak memory 217128 kb
Host smart-658907df-596b-4d19-8f74-fc89a8c786b6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617603154 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.3617603154
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.4040500559
Short name T698
Test name
Test status
Simulation time 43766781 ps
CPU time 0.81 seconds
Started Jul 22 05:41:52 PM PDT 24
Finished Jul 22 05:41:54 PM PDT 24
Peak memory 218416 kb
Host smart-0b631bb2-b2a8-41ee-b52f-f7312ca814b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040500559 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.4040500559
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.1554327932
Short name T406
Test name
Test status
Simulation time 79069464 ps
CPU time 1.6 seconds
Started Jul 22 05:41:53 PM PDT 24
Finished Jul 22 05:41:56 PM PDT 24
Peak memory 219312 kb
Host smart-5423d5d1-157f-417d-bac3-343ed40a4914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554327932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1554327932
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.3360839986
Short name T623
Test name
Test status
Simulation time 24700122 ps
CPU time 0.95 seconds
Started Jul 22 05:41:58 PM PDT 24
Finished Jul 22 05:42:00 PM PDT 24
Peak memory 216220 kb
Host smart-25730b03-65ef-468c-b5d7-cd6262e6e0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360839986 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.3360839986
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.2897026858
Short name T26
Test name
Test status
Simulation time 85730228 ps
CPU time 0.95 seconds
Started Jul 22 05:41:49 PM PDT 24
Finished Jul 22 05:41:50 PM PDT 24
Peak memory 207400 kb
Host smart-040c3785-c997-433f-9d5f-eee264e8d664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897026858 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2897026858
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.806659095
Short name T951
Test name
Test status
Simulation time 20513352 ps
CPU time 0.96 seconds
Started Jul 22 05:41:59 PM PDT 24
Finished Jul 22 05:42:00 PM PDT 24
Peak memory 215532 kb
Host smart-5f9d77e6-d05a-48b8-a526-f0f6befad3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806659095 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.806659095
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.631315395
Short name T368
Test name
Test status
Simulation time 146271590 ps
CPU time 1.35 seconds
Started Jul 22 05:41:53 PM PDT 24
Finished Jul 22 05:41:55 PM PDT 24
Peak memory 215604 kb
Host smart-253848da-c8cc-4814-9732-208cdcda9dea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631315395 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.631315395
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.715809774
Short name T577
Test name
Test status
Simulation time 183308084805 ps
CPU time 2356.29 seconds
Started Jul 22 05:41:54 PM PDT 24
Finished Jul 22 06:21:11 PM PDT 24
Peak memory 231864 kb
Host smart-46ca4d7a-e8d1-47a5-8205-c65b0693b5cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715809774 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.715809774
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.1930138490
Short name T275
Test name
Test status
Simulation time 36936263 ps
CPU time 1.07 seconds
Started Jul 22 05:43:24 PM PDT 24
Finished Jul 22 05:43:26 PM PDT 24
Peak memory 221188 kb
Host smart-968e63bc-678e-4dac-b3b7-cb58c8ae4633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930138490 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.1930138490
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.1687198831
Short name T640
Test name
Test status
Simulation time 43048708 ps
CPU time 0.98 seconds
Started Jul 22 05:43:32 PM PDT 24
Finished Jul 22 05:43:34 PM PDT 24
Peak memory 224308 kb
Host smart-6a675364-22ff-4934-88d5-9997acd9a5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687198831 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.1687198831
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.1453365
Short name T635
Test name
Test status
Simulation time 71474288 ps
CPU time 1.31 seconds
Started Jul 22 05:43:27 PM PDT 24
Finished Jul 22 05:43:29 PM PDT 24
Peak memory 219036 kb
Host smart-c519a4d4-d4a1-4338-8e2b-c5d177cf009d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1453365
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.2875976661
Short name T290
Test name
Test status
Simulation time 30876952 ps
CPU time 1.26 seconds
Started Jul 22 05:43:21 PM PDT 24
Finished Jul 22 05:43:23 PM PDT 24
Peak memory 216116 kb
Host smart-b3558c3d-6be7-4b5b-870a-02eb1805cd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875976661 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.2875976661
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.1231498210
Short name T164
Test name
Test status
Simulation time 75734930 ps
CPU time 1.19 seconds
Started Jul 22 05:43:25 PM PDT 24
Finished Jul 22 05:43:27 PM PDT 24
Peak memory 226248 kb
Host smart-d831da4d-9494-4917-abe9-2b261cb20337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231498210 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.1231498210
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.3052507685
Short name T44
Test name
Test status
Simulation time 119304314 ps
CPU time 1.12 seconds
Started Jul 22 05:43:25 PM PDT 24
Finished Jul 22 05:43:26 PM PDT 24
Peak memory 217428 kb
Host smart-efa56fc5-5613-4f8b-be94-bc23ff984e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052507685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.3052507685
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.739628890
Short name T531
Test name
Test status
Simulation time 47168510 ps
CPU time 1.1 seconds
Started Jul 22 05:43:31 PM PDT 24
Finished Jul 22 05:43:33 PM PDT 24
Peak memory 219968 kb
Host smart-facf2fff-cf94-44e7-89a3-fc1a27a69039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739628890 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.739628890
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.1759622981
Short name T133
Test name
Test status
Simulation time 22284761 ps
CPU time 1.17 seconds
Started Jul 22 05:43:26 PM PDT 24
Finished Jul 22 05:43:27 PM PDT 24
Peak memory 224484 kb
Host smart-6f9d6d8d-e3f1-49a2-9987-74d558426991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759622981 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.1759622981
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.2708973821
Short name T719
Test name
Test status
Simulation time 24633276 ps
CPU time 1.12 seconds
Started Jul 22 05:43:31 PM PDT 24
Finished Jul 22 05:43:33 PM PDT 24
Peak memory 217696 kb
Host smart-58429631-dc8e-430d-b804-957df987c400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708973821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.2708973821
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.1219291554
Short name T131
Test name
Test status
Simulation time 51219435 ps
CPU time 1.25 seconds
Started Jul 22 05:43:31 PM PDT 24
Finished Jul 22 05:43:33 PM PDT 24
Peak memory 220952 kb
Host smart-f600cb13-2ee8-4d8c-82ea-a3c50fc7b44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219291554 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.1219291554
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.3226866697
Short name T760
Test name
Test status
Simulation time 20137658 ps
CPU time 1.17 seconds
Started Jul 22 05:43:34 PM PDT 24
Finished Jul 22 05:43:37 PM PDT 24
Peak memory 229856 kb
Host smart-3619ae2a-44fa-4409-bb40-0714d265f9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226866697 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.3226866697
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.2150250194
Short name T309
Test name
Test status
Simulation time 77439109 ps
CPU time 0.95 seconds
Started Jul 22 05:43:26 PM PDT 24
Finished Jul 22 05:43:28 PM PDT 24
Peak memory 217488 kb
Host smart-be63685f-e914-4956-a189-58b2e75c9bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150250194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.2150250194
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.3190852241
Short name T93
Test name
Test status
Simulation time 35137449 ps
CPU time 1.17 seconds
Started Jul 22 05:43:32 PM PDT 24
Finished Jul 22 05:43:35 PM PDT 24
Peak memory 219404 kb
Host smart-cdeb2fce-b917-407b-8b8c-fa90f1b542bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190852241 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.3190852241
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.2999257780
Short name T120
Test name
Test status
Simulation time 25563672 ps
CPU time 1.08 seconds
Started Jul 22 05:43:31 PM PDT 24
Finished Jul 22 05:43:32 PM PDT 24
Peak memory 229924 kb
Host smart-52959472-1a9c-40d6-b0c1-9bbc92a66fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999257780 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.2999257780
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.3479542899
Short name T321
Test name
Test status
Simulation time 56085637 ps
CPU time 1.49 seconds
Started Jul 22 05:43:33 PM PDT 24
Finished Jul 22 05:43:36 PM PDT 24
Peak memory 219124 kb
Host smart-c1043292-63d3-48dd-8c81-cfc6f826664c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479542899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.3479542899
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.83481697
Short name T724
Test name
Test status
Simulation time 27152299 ps
CPU time 1.2 seconds
Started Jul 22 05:43:33 PM PDT 24
Finished Jul 22 05:43:36 PM PDT 24
Peak memory 220508 kb
Host smart-488aeba2-debd-4dde-96cf-d6b9f5e3da00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83481697 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.83481697
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.926003833
Short name T152
Test name
Test status
Simulation time 303895572 ps
CPU time 1.17 seconds
Started Jul 22 05:43:34 PM PDT 24
Finished Jul 22 05:43:36 PM PDT 24
Peak memory 225896 kb
Host smart-cf57ac36-f4f8-4056-b10c-df34fd113f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926003833 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.926003833
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.3887685507
Short name T802
Test name
Test status
Simulation time 254680635 ps
CPU time 3.17 seconds
Started Jul 22 05:43:32 PM PDT 24
Finished Jul 22 05:43:36 PM PDT 24
Peak memory 220756 kb
Host smart-143fb8fe-bb6b-4fd8-a1f0-01f3e2fdd6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887685507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3887685507
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.3526601651
Short name T301
Test name
Test status
Simulation time 58076537 ps
CPU time 1.1 seconds
Started Jul 22 05:43:34 PM PDT 24
Finished Jul 22 05:43:36 PM PDT 24
Peak memory 220216 kb
Host smart-cc4256ae-1803-4f27-9406-76e9d7d0a020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526601651 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.3526601651
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.956563437
Short name T459
Test name
Test status
Simulation time 91907781 ps
CPU time 1.18 seconds
Started Jul 22 05:43:32 PM PDT 24
Finished Jul 22 05:43:34 PM PDT 24
Peak memory 219912 kb
Host smart-501c5764-3a85-4f3e-af40-8ea235b9971f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956563437 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.956563437
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.3068885258
Short name T704
Test name
Test status
Simulation time 42041725 ps
CPU time 1.55 seconds
Started Jul 22 05:43:32 PM PDT 24
Finished Jul 22 05:43:35 PM PDT 24
Peak memory 220112 kb
Host smart-29d071a8-ff54-4752-83e2-727f0b58a061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068885258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.3068885258
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.3168210896
Short name T794
Test name
Test status
Simulation time 101163892 ps
CPU time 1.31 seconds
Started Jul 22 05:43:33 PM PDT 24
Finished Jul 22 05:43:36 PM PDT 24
Peak memory 215984 kb
Host smart-2f3b3a78-3302-43a7-a52a-8137e2c104f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168210896 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.3168210896
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.4024261495
Short name T858
Test name
Test status
Simulation time 20941063 ps
CPU time 0.96 seconds
Started Jul 22 05:43:31 PM PDT 24
Finished Jul 22 05:43:33 PM PDT 24
Peak memory 218800 kb
Host smart-02fd78c1-4d1a-4ba3-810e-d20410746ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024261495 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.4024261495
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.749147440
Short name T378
Test name
Test status
Simulation time 119510455 ps
CPU time 0.96 seconds
Started Jul 22 05:43:32 PM PDT 24
Finished Jul 22 05:43:33 PM PDT 24
Peak memory 217636 kb
Host smart-18af8804-f0c1-4919-8043-dbad15c46ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749147440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.749147440
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.1963633024
Short name T504
Test name
Test status
Simulation time 27635553 ps
CPU time 1.15 seconds
Started Jul 22 05:43:38 PM PDT 24
Finished Jul 22 05:43:40 PM PDT 24
Peak memory 220216 kb
Host smart-585f1a34-7f83-46a5-84a8-c0d2103d77aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963633024 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.1963633024
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.2962164369
Short name T173
Test name
Test status
Simulation time 18437286 ps
CPU time 1.06 seconds
Started Jul 22 05:43:34 PM PDT 24
Finished Jul 22 05:43:36 PM PDT 24
Peak memory 218760 kb
Host smart-c71a7bd2-cf1e-4221-b393-7d02f366a7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962164369 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2962164369
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.3051572098
Short name T479
Test name
Test status
Simulation time 106447372 ps
CPU time 1.39 seconds
Started Jul 22 05:43:33 PM PDT 24
Finished Jul 22 05:43:35 PM PDT 24
Peak memory 220384 kb
Host smart-2bb8b8cb-ae31-4e71-a5a8-320d29e38c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051572098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.3051572098
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.3979884428
Short name T194
Test name
Test status
Simulation time 29822711 ps
CPU time 1.24 seconds
Started Jul 22 05:43:32 PM PDT 24
Finished Jul 22 05:43:34 PM PDT 24
Peak memory 221284 kb
Host smart-15f42550-387b-425e-8096-a756e5403dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979884428 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.3979884428
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.4204994769
Short name T108
Test name
Test status
Simulation time 24895971 ps
CPU time 0.96 seconds
Started Jul 22 05:43:33 PM PDT 24
Finished Jul 22 05:43:35 PM PDT 24
Peak memory 219756 kb
Host smart-accead86-0152-4a1b-a0ca-dcb276a704ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204994769 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.4204994769
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3760637859
Short name T713
Test name
Test status
Simulation time 70712850 ps
CPU time 1.55 seconds
Started Jul 22 05:43:34 PM PDT 24
Finished Jul 22 05:43:36 PM PDT 24
Peak memory 218836 kb
Host smart-610d84d7-da28-42b4-aced-078ac5c1cb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760637859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3760637859
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.1985273632
Short name T636
Test name
Test status
Simulation time 42237881 ps
CPU time 1.17 seconds
Started Jul 22 05:41:52 PM PDT 24
Finished Jul 22 05:41:54 PM PDT 24
Peak memory 220628 kb
Host smart-b9a75948-307e-43f4-b555-76b04335e789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985273632 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.1985273632
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.483299617
Short name T740
Test name
Test status
Simulation time 44063588 ps
CPU time 1.03 seconds
Started Jul 22 05:41:53 PM PDT 24
Finished Jul 22 05:41:56 PM PDT 24
Peak memory 207016 kb
Host smart-a397de77-34da-4ae7-ac4f-3f60061efd5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483299617 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.483299617
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.2396094961
Short name T550
Test name
Test status
Simulation time 12379686 ps
CPU time 0.84 seconds
Started Jul 22 05:41:58 PM PDT 24
Finished Jul 22 05:42:00 PM PDT 24
Peak memory 216224 kb
Host smart-b784f482-829f-4cb3-9db2-824af2a71df1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396094961 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.2396094961
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_err.361540184
Short name T766
Test name
Test status
Simulation time 28709891 ps
CPU time 0.86 seconds
Started Jul 22 05:41:55 PM PDT 24
Finished Jul 22 05:41:57 PM PDT 24
Peak memory 218632 kb
Host smart-82f0060f-8ff3-4327-9067-f5dba125a891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361540184 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.361540184
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.956742675
Short name T292
Test name
Test status
Simulation time 103338048 ps
CPU time 1.08 seconds
Started Jul 22 05:41:53 PM PDT 24
Finished Jul 22 05:41:56 PM PDT 24
Peak memory 220096 kb
Host smart-f59a939a-9771-4b9d-9cb2-1f29b6f38f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956742675 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.956742675
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.248079186
Short name T885
Test name
Test status
Simulation time 34815585 ps
CPU time 0.86 seconds
Started Jul 22 05:41:54 PM PDT 24
Finished Jul 22 05:41:56 PM PDT 24
Peak memory 216044 kb
Host smart-b84955c0-548c-45fa-8061-ebadd6141dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248079186 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.248079186
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.401289043
Short name T895
Test name
Test status
Simulation time 34305546 ps
CPU time 0.93 seconds
Started Jul 22 05:41:54 PM PDT 24
Finished Jul 22 05:41:56 PM PDT 24
Peak memory 207384 kb
Host smart-9819142b-7680-48e0-aa63-890d76150193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401289043 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.401289043
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.326946400
Short name T610
Test name
Test status
Simulation time 15536019 ps
CPU time 0.98 seconds
Started Jul 22 05:41:53 PM PDT 24
Finished Jul 22 05:41:55 PM PDT 24
Peak memory 215576 kb
Host smart-2db34216-5256-45a5-8e0e-dc5827ed6cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326946400 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.326946400
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.826922920
Short name T351
Test name
Test status
Simulation time 477858920 ps
CPU time 3.32 seconds
Started Jul 22 05:41:55 PM PDT 24
Finished Jul 22 05:41:59 PM PDT 24
Peak memory 215688 kb
Host smart-260db913-91b2-48b8-ad76-26144dc22bf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826922920 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.826922920
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.869237404
Short name T678
Test name
Test status
Simulation time 685778501257 ps
CPU time 1095.78 seconds
Started Jul 22 05:41:58 PM PDT 24
Finished Jul 22 06:00:15 PM PDT 24
Peak memory 223476 kb
Host smart-130d8102-7f6e-4288-9295-b4f5d69feb63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869237404 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.869237404
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.2889233850
Short name T196
Test name
Test status
Simulation time 34632313 ps
CPU time 0.88 seconds
Started Jul 22 05:43:30 PM PDT 24
Finished Jul 22 05:43:31 PM PDT 24
Peak memory 219428 kb
Host smart-156646e3-db76-4fff-85a7-7924cf89ad6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889233850 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.2889233850
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.1137748895
Short name T624
Test name
Test status
Simulation time 61401570 ps
CPU time 1.31 seconds
Started Jul 22 05:43:32 PM PDT 24
Finished Jul 22 05:43:34 PM PDT 24
Peak memory 218868 kb
Host smart-aa69049e-7912-4e56-96d0-a29781c2d4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137748895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.1137748895
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.3368295426
Short name T272
Test name
Test status
Simulation time 185849971 ps
CPU time 1.35 seconds
Started Jul 22 05:43:33 PM PDT 24
Finished Jul 22 05:43:36 PM PDT 24
Peak memory 220024 kb
Host smart-e7f6c137-3ee2-4bcf-b663-d0b765537ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368295426 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.3368295426
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.1018359552
Short name T158
Test name
Test status
Simulation time 23106156 ps
CPU time 1.02 seconds
Started Jul 22 05:43:33 PM PDT 24
Finished Jul 22 05:43:35 PM PDT 24
Peak memory 224260 kb
Host smart-a13cf9f5-dce7-4ab4-a997-784c3c71d986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018359552 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1018359552
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.3588897728
Short name T83
Test name
Test status
Simulation time 90882241 ps
CPU time 1.42 seconds
Started Jul 22 05:43:33 PM PDT 24
Finished Jul 22 05:43:36 PM PDT 24
Peak memory 217608 kb
Host smart-80bcae35-2140-47a3-bd7c-67788a66e62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588897728 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.3588897728
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.1003138121
Short name T181
Test name
Test status
Simulation time 28551424 ps
CPU time 1.2 seconds
Started Jul 22 05:43:34 PM PDT 24
Finished Jul 22 05:43:36 PM PDT 24
Peak memory 218964 kb
Host smart-0bfd67d4-9f27-429f-bcc1-f4a6b99c4ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003138121 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.1003138121
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.3555236643
Short name T533
Test name
Test status
Simulation time 40656037 ps
CPU time 1.11 seconds
Started Jul 22 05:43:32 PM PDT 24
Finished Jul 22 05:43:35 PM PDT 24
Peak memory 219936 kb
Host smart-41c83604-8e90-4647-8be9-1181bce69d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555236643 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.3555236643
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.2010929170
Short name T59
Test name
Test status
Simulation time 80150980 ps
CPU time 1 seconds
Started Jul 22 05:43:30 PM PDT 24
Finished Jul 22 05:43:32 PM PDT 24
Peak memory 217752 kb
Host smart-fa6eb114-00cb-40de-ae17-55366154d7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010929170 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.2010929170
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.2533468842
Short name T375
Test name
Test status
Simulation time 86886242 ps
CPU time 1.22 seconds
Started Jul 22 05:43:34 PM PDT 24
Finished Jul 22 05:43:37 PM PDT 24
Peak memory 220388 kb
Host smart-4a3a59b3-b9ce-4d14-9738-198a0d0e5aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533468842 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.2533468842
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.4177676359
Short name T121
Test name
Test status
Simulation time 27669175 ps
CPU time 1.09 seconds
Started Jul 22 05:43:34 PM PDT 24
Finished Jul 22 05:43:37 PM PDT 24
Peak memory 229892 kb
Host smart-d7da0085-743c-41b0-af6d-f03264aa5d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177676359 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.4177676359
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.1757529300
Short name T440
Test name
Test status
Simulation time 157880008 ps
CPU time 3.4 seconds
Started Jul 22 05:43:32 PM PDT 24
Finished Jul 22 05:43:37 PM PDT 24
Peak memory 220444 kb
Host smart-3d0a0c82-69f8-4b7b-b8c8-bd9508b13669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757529300 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.1757529300
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.1016621889
Short name T118
Test name
Test status
Simulation time 96877685 ps
CPU time 1.27 seconds
Started Jul 22 05:43:32 PM PDT 24
Finished Jul 22 05:43:34 PM PDT 24
Peak memory 218872 kb
Host smart-7d0ecdee-c06d-4149-a265-601a743f0148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016621889 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.1016621889
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.585581571
Short name T748
Test name
Test status
Simulation time 61107132 ps
CPU time 1.21 seconds
Started Jul 22 05:43:35 PM PDT 24
Finished Jul 22 05:43:37 PM PDT 24
Peak memory 219940 kb
Host smart-8c5d4afb-e1a3-4867-a7b3-c4f3a7126a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585581571 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.585581571
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.3066466569
Short name T728
Test name
Test status
Simulation time 25444198 ps
CPU time 1.24 seconds
Started Jul 22 05:43:32 PM PDT 24
Finished Jul 22 05:43:35 PM PDT 24
Peak memory 218972 kb
Host smart-9fccd3fb-e723-4933-a3f5-867b2b96f48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066466569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.3066466569
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.1435548133
Short name T411
Test name
Test status
Simulation time 80356238 ps
CPU time 1.13 seconds
Started Jul 22 05:43:34 PM PDT 24
Finished Jul 22 05:43:36 PM PDT 24
Peak memory 218904 kb
Host smart-5c15d7de-ec8b-4caa-915b-74dbed0bd8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435548133 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.1435548133
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.3298787965
Short name T6
Test name
Test status
Simulation time 22004153 ps
CPU time 1.07 seconds
Started Jul 22 05:43:32 PM PDT 24
Finished Jul 22 05:43:34 PM PDT 24
Peak memory 218940 kb
Host smart-7183d565-b0a5-4da2-95f8-535651a46ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298787965 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.3298787965
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.3852576462
Short name T995
Test name
Test status
Simulation time 110435437 ps
CPU time 2.82 seconds
Started Jul 22 05:43:34 PM PDT 24
Finished Jul 22 05:43:38 PM PDT 24
Peak memory 219464 kb
Host smart-7c5f4cb4-e914-45aa-8a24-f223568abcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852576462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.3852576462
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.3913494521
Short name T473
Test name
Test status
Simulation time 28439467 ps
CPU time 1.21 seconds
Started Jul 22 05:43:34 PM PDT 24
Finished Jul 22 05:43:36 PM PDT 24
Peak memory 220076 kb
Host smart-31d3a565-07c2-4ee3-84aa-80248e275d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913494521 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.3913494521
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.3758052451
Short name T139
Test name
Test status
Simulation time 37275023 ps
CPU time 1.08 seconds
Started Jul 22 05:43:42 PM PDT 24
Finished Jul 22 05:43:45 PM PDT 24
Peak memory 230124 kb
Host smart-24168b58-0a86-4605-8962-a6ab3ccaeefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758052451 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.3758052451
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.654129491
Short name T878
Test name
Test status
Simulation time 42791019 ps
CPU time 1.28 seconds
Started Jul 22 05:43:33 PM PDT 24
Finished Jul 22 05:43:36 PM PDT 24
Peak memory 218804 kb
Host smart-80f165d7-3387-48dd-865a-55408eb9e8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654129491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.654129491
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.258104756
Short name T293
Test name
Test status
Simulation time 38449474 ps
CPU time 1.06 seconds
Started Jul 22 05:43:41 PM PDT 24
Finished Jul 22 05:43:42 PM PDT 24
Peak memory 219980 kb
Host smart-f7a49ab4-cbe7-4ff2-83a8-e9b38d9f4958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258104756 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.258104756
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.1640460023
Short name T159
Test name
Test status
Simulation time 31417192 ps
CPU time 1.01 seconds
Started Jul 22 05:43:45 PM PDT 24
Finished Jul 22 05:43:48 PM PDT 24
Peak memory 223672 kb
Host smart-ed341015-68b8-40ab-8dd7-f28638c6f3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640460023 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1640460023
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.4275549704
Short name T929
Test name
Test status
Simulation time 153405313 ps
CPU time 2.32 seconds
Started Jul 22 05:43:44 PM PDT 24
Finished Jul 22 05:43:48 PM PDT 24
Peak memory 217924 kb
Host smart-689e4f75-aeee-41ca-8c20-9d1eaf130ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275549704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.4275549704
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.1449057860
Short name T170
Test name
Test status
Simulation time 40484078 ps
CPU time 1.08 seconds
Started Jul 22 05:43:42 PM PDT 24
Finished Jul 22 05:43:44 PM PDT 24
Peak memory 220148 kb
Host smart-4397ea48-a70b-474c-96cf-36c578e81a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449057860 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.1449057860
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_genbits.2761286767
Short name T843
Test name
Test status
Simulation time 94450184 ps
CPU time 1.35 seconds
Started Jul 22 05:43:41 PM PDT 24
Finished Jul 22 05:43:43 PM PDT 24
Peak memory 218812 kb
Host smart-b165580f-2c96-496b-a90b-7ae8daf832a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761286767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.2761286767
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.2926711555
Short name T132
Test name
Test status
Simulation time 219801108 ps
CPU time 1.32 seconds
Started Jul 22 05:43:48 PM PDT 24
Finished Jul 22 05:43:50 PM PDT 24
Peak memory 219956 kb
Host smart-20be5bfb-3681-49aa-a13d-555f969f6fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926711555 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.2926711555
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.1546144176
Short name T184
Test name
Test status
Simulation time 20028946 ps
CPU time 1.09 seconds
Started Jul 22 05:43:43 PM PDT 24
Finished Jul 22 05:43:46 PM PDT 24
Peak memory 218676 kb
Host smart-45e5eecd-c449-487b-ba8d-0893a3f80626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546144176 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.1546144176
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.3997205899
Short name T942
Test name
Test status
Simulation time 43275453 ps
CPU time 1.7 seconds
Started Jul 22 05:43:43 PM PDT 24
Finished Jul 22 05:43:45 PM PDT 24
Peak memory 217860 kb
Host smart-ba4df685-bc49-49e9-9275-c07b47d8a195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997205899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.3997205899
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.2814071516
Short name T773
Test name
Test status
Simulation time 155779679 ps
CPU time 1.15 seconds
Started Jul 22 05:42:04 PM PDT 24
Finished Jul 22 05:42:06 PM PDT 24
Peak memory 219744 kb
Host smart-ef0b8350-4917-4caa-ae76-4a6090569cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814071516 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.2814071516
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.727026414
Short name T450
Test name
Test status
Simulation time 22031964 ps
CPU time 0.98 seconds
Started Jul 22 05:41:59 PM PDT 24
Finished Jul 22 05:42:01 PM PDT 24
Peak memory 215188 kb
Host smart-a3ebcc76-7635-4cc6-bcdc-912fabd3b21a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727026414 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.727026414
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.1656885590
Short name T211
Test name
Test status
Simulation time 34100992 ps
CPU time 0.88 seconds
Started Jul 22 05:42:01 PM PDT 24
Finished Jul 22 05:42:02 PM PDT 24
Peak memory 216536 kb
Host smart-78e33b62-8409-4a1d-9d2d-3054a119b099
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656885590 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.1656885590
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_err.2795647103
Short name T923
Test name
Test status
Simulation time 25756749 ps
CPU time 1.21 seconds
Started Jul 22 05:42:02 PM PDT 24
Finished Jul 22 05:42:04 PM PDT 24
Peak memory 220072 kb
Host smart-a70875a0-cce9-45a1-8a58-391320feb9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795647103 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.2795647103
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.1730600883
Short name T968
Test name
Test status
Simulation time 39260149 ps
CPU time 1.4 seconds
Started Jul 22 05:41:54 PM PDT 24
Finished Jul 22 05:41:57 PM PDT 24
Peak memory 217816 kb
Host smart-b6502947-de80-41f6-b79d-c1aad8eacd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730600883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1730600883
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.246770892
Short name T86
Test name
Test status
Simulation time 21807340 ps
CPU time 1.08 seconds
Started Jul 22 05:42:07 PM PDT 24
Finished Jul 22 05:42:08 PM PDT 24
Peak memory 216300 kb
Host smart-477cd0db-891a-401a-89e2-d06dfa08d164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246770892 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.246770892
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.3647464758
Short name T694
Test name
Test status
Simulation time 54281413 ps
CPU time 0.85 seconds
Started Jul 22 05:41:55 PM PDT 24
Finished Jul 22 05:41:57 PM PDT 24
Peak memory 207192 kb
Host smart-a4922c58-00ab-41fc-a6a8-669870c9eaca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647464758 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.3647464758
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.4216357031
Short name T751
Test name
Test status
Simulation time 39967507 ps
CPU time 0.89 seconds
Started Jul 22 05:44:47 PM PDT 24
Finished Jul 22 05:44:48 PM PDT 24
Peak memory 215640 kb
Host smart-000131f5-e4ed-4c97-b5e7-f93283a3f3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216357031 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.4216357031
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.291575927
Short name T80
Test name
Test status
Simulation time 503488200 ps
CPU time 5.8 seconds
Started Jul 22 05:42:00 PM PDT 24
Finished Jul 22 05:42:07 PM PDT 24
Peak memory 218816 kb
Host smart-9f632321-9a6d-412e-8d5b-a3541cdd6d06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291575927 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.291575927
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2340491781
Short name T232
Test name
Test status
Simulation time 293352848923 ps
CPU time 1852.42 seconds
Started Jul 22 05:42:01 PM PDT 24
Finished Jul 22 06:12:54 PM PDT 24
Peak memory 225568 kb
Host smart-f3044f86-23cb-44c4-a244-6fe6248986c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340491781 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.2340491781
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.977011382
Short name T532
Test name
Test status
Simulation time 48623189 ps
CPU time 1.12 seconds
Started Jul 22 05:43:45 PM PDT 24
Finished Jul 22 05:43:48 PM PDT 24
Peak memory 219664 kb
Host smart-ed44e0e2-f249-402c-95de-3c82d5107841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977011382 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.977011382
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.3497902508
Short name T127
Test name
Test status
Simulation time 27807744 ps
CPU time 1.2 seconds
Started Jul 22 05:43:45 PM PDT 24
Finished Jul 22 05:43:48 PM PDT 24
Peak memory 220964 kb
Host smart-939da656-ef12-492b-b769-c8c6fc357fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497902508 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.3497902508
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.2350432779
Short name T737
Test name
Test status
Simulation time 77259810 ps
CPU time 1.58 seconds
Started Jul 22 05:43:45 PM PDT 24
Finished Jul 22 05:43:49 PM PDT 24
Peak memory 219872 kb
Host smart-b8b07865-c785-4fab-a4df-380d82533a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350432779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.2350432779
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.2660902407
Short name T217
Test name
Test status
Simulation time 82716904 ps
CPU time 1.18 seconds
Started Jul 22 05:43:47 PM PDT 24
Finished Jul 22 05:43:49 PM PDT 24
Peak memory 220424 kb
Host smart-3b7217ea-9d24-47fd-9ef1-a0908fa4ec43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660902407 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.2660902407
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.3141651028
Short name T165
Test name
Test status
Simulation time 22726805 ps
CPU time 0.95 seconds
Started Jul 22 05:43:41 PM PDT 24
Finished Jul 22 05:43:42 PM PDT 24
Peak memory 218888 kb
Host smart-5443eb26-53fa-4db8-ae1d-336fbd036ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141651028 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.3141651028
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.1982343030
Short name T924
Test name
Test status
Simulation time 41522376 ps
CPU time 1.41 seconds
Started Jul 22 05:43:50 PM PDT 24
Finished Jul 22 05:43:52 PM PDT 24
Peak memory 218660 kb
Host smart-46209c93-07fb-4deb-9d03-ea74a284d990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982343030 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.1982343030
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.4203295426
Short name T901
Test name
Test status
Simulation time 28105979 ps
CPU time 1.24 seconds
Started Jul 22 05:43:48 PM PDT 24
Finished Jul 22 05:43:50 PM PDT 24
Peak memory 219832 kb
Host smart-65b766f8-8694-48c9-86b7-23c3776691dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203295426 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.4203295426
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.3219796252
Short name T569
Test name
Test status
Simulation time 36213757 ps
CPU time 0.84 seconds
Started Jul 22 05:43:47 PM PDT 24
Finished Jul 22 05:43:49 PM PDT 24
Peak memory 219724 kb
Host smart-c99ed1bf-57ce-4d05-8997-7aec8865833c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219796252 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3219796252
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.655464395
Short name T685
Test name
Test status
Simulation time 122270770 ps
CPU time 2.85 seconds
Started Jul 22 05:43:44 PM PDT 24
Finished Jul 22 05:43:48 PM PDT 24
Peak memory 219088 kb
Host smart-54e1b1bb-c918-4bbc-aa80-5606b12cbaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655464395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.655464395
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.382280087
Short name T124
Test name
Test status
Simulation time 28739921 ps
CPU time 1.14 seconds
Started Jul 22 05:43:43 PM PDT 24
Finished Jul 22 05:43:46 PM PDT 24
Peak memory 219024 kb
Host smart-cb0fe5c5-ebb8-4f3b-b4fe-40cbf93df532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382280087 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.382280087
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.683386308
Short name T947
Test name
Test status
Simulation time 22309864 ps
CPU time 0.9 seconds
Started Jul 22 05:43:44 PM PDT 24
Finished Jul 22 05:43:47 PM PDT 24
Peak memory 218364 kb
Host smart-6983e899-6e06-4d39-9f2c-322da9e15dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683386308 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.683386308
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.2552825754
Short name T417
Test name
Test status
Simulation time 60845106 ps
CPU time 1.48 seconds
Started Jul 22 05:43:45 PM PDT 24
Finished Jul 22 05:43:48 PM PDT 24
Peak memory 218872 kb
Host smart-b4205d9d-aafc-4cbb-a7b3-ff2b1afce289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552825754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.2552825754
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.3214044455
Short name T389
Test name
Test status
Simulation time 84928999 ps
CPU time 1.1 seconds
Started Jul 22 05:43:43 PM PDT 24
Finished Jul 22 05:43:46 PM PDT 24
Peak memory 215876 kb
Host smart-ab556a8e-cddd-4832-bbfa-d76d2ca03c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214044455 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.3214044455
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.2837262360
Short name T163
Test name
Test status
Simulation time 30694531 ps
CPU time 1.26 seconds
Started Jul 22 05:43:47 PM PDT 24
Finished Jul 22 05:43:49 PM PDT 24
Peak memory 215660 kb
Host smart-a2a3377c-914c-4a76-b47a-32d15292074c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837262360 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.2837262360
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.577716619
Short name T925
Test name
Test status
Simulation time 42081415 ps
CPU time 1.3 seconds
Started Jul 22 05:43:45 PM PDT 24
Finished Jul 22 05:43:48 PM PDT 24
Peak memory 217688 kb
Host smart-48a5aa3a-8668-4827-95ec-d403d94078f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577716619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.577716619
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.1938341061
Short name T467
Test name
Test status
Simulation time 24441347 ps
CPU time 1.16 seconds
Started Jul 22 05:43:41 PM PDT 24
Finished Jul 22 05:43:43 PM PDT 24
Peak memory 219044 kb
Host smart-3d1e2e53-ea12-4c06-b2a7-3920a2d30f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938341061 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.1938341061
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.3100558475
Short name T826
Test name
Test status
Simulation time 40091186 ps
CPU time 0.84 seconds
Started Jul 22 05:43:44 PM PDT 24
Finished Jul 22 05:43:47 PM PDT 24
Peak memory 218596 kb
Host smart-7c529e7e-69af-477d-a076-8bc31ea17657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100558475 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3100558475
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.863177076
Short name T317
Test name
Test status
Simulation time 84640492 ps
CPU time 1.29 seconds
Started Jul 22 05:43:41 PM PDT 24
Finished Jul 22 05:43:43 PM PDT 24
Peak memory 219556 kb
Host smart-4e4ad9c2-4209-425f-aaff-ec75a622c1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863177076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.863177076
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.4053368743
Short name T123
Test name
Test status
Simulation time 75100911 ps
CPU time 1.17 seconds
Started Jul 22 05:43:42 PM PDT 24
Finished Jul 22 05:43:44 PM PDT 24
Peak memory 218756 kb
Host smart-86a5c3dd-1419-44b7-9c7c-6ff3f0dd0567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053368743 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.4053368743
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.2338008950
Short name T781
Test name
Test status
Simulation time 25667823 ps
CPU time 0.98 seconds
Started Jul 22 05:43:43 PM PDT 24
Finished Jul 22 05:43:45 PM PDT 24
Peak memory 218896 kb
Host smart-70b83d5c-4732-467d-b2ea-4b0392833ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338008950 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.2338008950
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.2463366138
Short name T325
Test name
Test status
Simulation time 81204735 ps
CPU time 1.35 seconds
Started Jul 22 05:43:43 PM PDT 24
Finished Jul 22 05:43:46 PM PDT 24
Peak memory 219188 kb
Host smart-2f4f4fad-3ba6-4d7f-afdd-a4e2fa8027e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463366138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2463366138
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.444965701
Short name T302
Test name
Test status
Simulation time 50455001 ps
CPU time 1.16 seconds
Started Jul 22 05:43:43 PM PDT 24
Finished Jul 22 05:43:46 PM PDT 24
Peak memory 216024 kb
Host smart-d8266b52-c50f-423f-a1f6-11e7ce9ce38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444965701 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.444965701
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.3920588795
Short name T107
Test name
Test status
Simulation time 21806428 ps
CPU time 1.21 seconds
Started Jul 22 05:43:46 PM PDT 24
Finished Jul 22 05:43:48 PM PDT 24
Peak memory 229924 kb
Host smart-707e6378-a2af-4976-b3b0-ca6647500731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920588795 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.3920588795
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.4095497481
Short name T618
Test name
Test status
Simulation time 37622193 ps
CPU time 1.63 seconds
Started Jul 22 05:43:44 PM PDT 24
Finished Jul 22 05:43:48 PM PDT 24
Peak memory 218864 kb
Host smart-609777e8-9edf-467f-9b64-f34c6bce0b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095497481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.4095497481
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.40736806
Short name T555
Test name
Test status
Simulation time 46447156 ps
CPU time 1.11 seconds
Started Jul 22 05:43:42 PM PDT 24
Finished Jul 22 05:43:43 PM PDT 24
Peak memory 220020 kb
Host smart-afb3c975-495a-45f0-a860-410de4941bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40736806 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.40736806
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.3499673081
Short name T105
Test name
Test status
Simulation time 48305342 ps
CPU time 0.96 seconds
Started Jul 22 05:43:43 PM PDT 24
Finished Jul 22 05:43:45 PM PDT 24
Peak memory 220040 kb
Host smart-97b8bb7d-74f2-40a3-989a-01245e01dbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499673081 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.3499673081
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.7142158
Short name T336
Test name
Test status
Simulation time 105921215 ps
CPU time 1.31 seconds
Started Jul 22 05:43:47 PM PDT 24
Finished Jul 22 05:43:49 PM PDT 24
Peak memory 219900 kb
Host smart-6f4a0012-21d0-476c-9a50-1c53982d0957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7142158 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.7142158
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.244363137
Short name T190
Test name
Test status
Simulation time 129954392 ps
CPU time 1.17 seconds
Started Jul 22 05:43:43 PM PDT 24
Finished Jul 22 05:43:46 PM PDT 24
Peak memory 218924 kb
Host smart-8daee509-8ec9-4afd-8257-d2588e685ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244363137 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.244363137
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.3412264128
Short name T437
Test name
Test status
Simulation time 38845409 ps
CPU time 1.16 seconds
Started Jul 22 05:43:49 PM PDT 24
Finished Jul 22 05:43:51 PM PDT 24
Peak memory 221084 kb
Host smart-2d7f581e-81b1-492f-acc3-1e185fad1124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412264128 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.3412264128
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.4109768212
Short name T873
Test name
Test status
Simulation time 163331668 ps
CPU time 1.43 seconds
Started Jul 22 05:43:45 PM PDT 24
Finished Jul 22 05:43:48 PM PDT 24
Peak memory 219852 kb
Host smart-730aca0c-7724-47a6-bd02-9a6ffadf934d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109768212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.4109768212
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.1498866745
Short name T829
Test name
Test status
Simulation time 26204273 ps
CPU time 1.19 seconds
Started Jul 22 05:42:07 PM PDT 24
Finished Jul 22 05:42:09 PM PDT 24
Peak memory 219232 kb
Host smart-b24a32d6-eb5c-4687-819f-84eb42e88b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498866745 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.1498866745
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.725720038
Short name T896
Test name
Test status
Simulation time 24668770 ps
CPU time 0.99 seconds
Started Jul 22 05:42:12 PM PDT 24
Finished Jul 22 05:42:14 PM PDT 24
Peak memory 206948 kb
Host smart-35796ea8-8d3e-4650-98d6-83f63b481eac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725720038 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.725720038
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.438021073
Short name T857
Test name
Test status
Simulation time 41014259 ps
CPU time 0.96 seconds
Started Jul 22 05:42:06 PM PDT 24
Finished Jul 22 05:42:08 PM PDT 24
Peak memory 216708 kb
Host smart-84186a38-18ab-44cc-a003-e81ee0aeb116
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438021073 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.438021073
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.192723762
Short name T205
Test name
Test status
Simulation time 43650011 ps
CPU time 1.1 seconds
Started Jul 22 05:42:05 PM PDT 24
Finished Jul 22 05:42:06 PM PDT 24
Peak memory 217184 kb
Host smart-0b9d666b-416a-4521-a2b1-4ba86a2fb0c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192723762 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_dis
able_auto_req_mode.192723762
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.473818764
Short name T197
Test name
Test status
Simulation time 30665801 ps
CPU time 0.89 seconds
Started Jul 22 05:42:06 PM PDT 24
Finished Jul 22 05:42:07 PM PDT 24
Peak memory 219616 kb
Host smart-9c5a96f5-c4c7-45d5-861d-eccc8b809a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473818764 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.473818764
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.3078067543
Short name T836
Test name
Test status
Simulation time 78535837 ps
CPU time 1.3 seconds
Started Jul 22 05:42:03 PM PDT 24
Finished Jul 22 05:42:04 PM PDT 24
Peak memory 217724 kb
Host smart-b14eae78-a658-40d6-aa6e-e985df51861a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078067543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3078067543
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.2335841051
Short name T544
Test name
Test status
Simulation time 23873730 ps
CPU time 1.03 seconds
Started Jul 22 05:42:00 PM PDT 24
Finished Jul 22 05:42:01 PM PDT 24
Peak memory 215928 kb
Host smart-93733fc2-9c97-4449-8dec-8daecf0e0fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335841051 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2335841051
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_smoke.3517574659
Short name T387
Test name
Test status
Simulation time 40680698 ps
CPU time 0.89 seconds
Started Jul 22 05:42:00 PM PDT 24
Finished Jul 22 05:42:01 PM PDT 24
Peak memory 215624 kb
Host smart-39fd73fd-c848-4ae4-916a-7840cfa400c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517574659 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.3517574659
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.1749789845
Short name T238
Test name
Test status
Simulation time 205908690 ps
CPU time 3.51 seconds
Started Jul 22 05:42:06 PM PDT 24
Finished Jul 22 05:42:10 PM PDT 24
Peak memory 217592 kb
Host smart-76a7a3e7-6544-457b-95cd-edc88a1d999d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749789845 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.1749789845
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.2183261002
Short name T956
Test name
Test status
Simulation time 211375349798 ps
CPU time 1243.92 seconds
Started Jul 22 05:42:02 PM PDT 24
Finished Jul 22 06:02:47 PM PDT 24
Peak memory 223480 kb
Host smart-1d586b58-f6ff-4bf2-bb14-25f61dbadabd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183261002 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.2183261002
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.2714329799
Short name T688
Test name
Test status
Simulation time 25910582 ps
CPU time 1.23 seconds
Started Jul 22 05:43:41 PM PDT 24
Finished Jul 22 05:43:43 PM PDT 24
Peak memory 220784 kb
Host smart-6d07cb88-6e64-47f9-8d7d-b0af5d157495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714329799 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.2714329799
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.358062751
Short name T134
Test name
Test status
Simulation time 30671655 ps
CPU time 1.03 seconds
Started Jul 22 05:43:46 PM PDT 24
Finished Jul 22 05:43:48 PM PDT 24
Peak memory 224256 kb
Host smart-3e2991b4-ea3a-44f9-b1cf-24c4f8dc88a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358062751 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.358062751
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.466246454
Short name T663
Test name
Test status
Simulation time 34849698 ps
CPU time 1.26 seconds
Started Jul 22 05:43:43 PM PDT 24
Finished Jul 22 05:43:45 PM PDT 24
Peak memory 217616 kb
Host smart-2529d6b3-51cf-4b2a-bbc1-c5a420338874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466246454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.466246454
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.3020690194
Short name T982
Test name
Test status
Simulation time 26723179 ps
CPU time 1.3 seconds
Started Jul 22 05:43:45 PM PDT 24
Finished Jul 22 05:43:48 PM PDT 24
Peak memory 219088 kb
Host smart-45de5bfe-a940-4ccb-ad0b-4c5fb0102fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020690194 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.3020690194
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.4268700997
Short name T657
Test name
Test status
Simulation time 54223366 ps
CPU time 0.87 seconds
Started Jul 22 05:43:44 PM PDT 24
Finished Jul 22 05:43:47 PM PDT 24
Peak memory 220048 kb
Host smart-97ec3854-32b6-46d7-aa1c-bde7238e0d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268700997 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.4268700997
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.2431893105
Short name T852
Test name
Test status
Simulation time 21030826 ps
CPU time 1.2 seconds
Started Jul 22 05:43:44 PM PDT 24
Finished Jul 22 05:43:47 PM PDT 24
Peak memory 219240 kb
Host smart-f6ffe6cb-a919-4e06-99ed-6bd11a9a69a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431893105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.2431893105
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.2894697726
Short name T613
Test name
Test status
Simulation time 46413336 ps
CPU time 1.14 seconds
Started Jul 22 05:43:43 PM PDT 24
Finished Jul 22 05:43:45 PM PDT 24
Peak memory 220088 kb
Host smart-a4a853e0-bba2-46c7-bd5d-2dd5a57d3f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894697726 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.2894697726
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.600292232
Short name T984
Test name
Test status
Simulation time 28658143 ps
CPU time 1.29 seconds
Started Jul 22 05:43:41 PM PDT 24
Finished Jul 22 05:43:43 PM PDT 24
Peak memory 226012 kb
Host smart-2f1cc1f1-bb55-4371-8169-aead2b159153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600292232 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.600292232
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.875057693
Short name T484
Test name
Test status
Simulation time 328709530 ps
CPU time 1.29 seconds
Started Jul 22 05:43:49 PM PDT 24
Finished Jul 22 05:43:51 PM PDT 24
Peak memory 220204 kb
Host smart-9ce96663-99fa-4c38-bcaf-43a06cd7aca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875057693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.875057693
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.4200169671
Short name T907
Test name
Test status
Simulation time 88368873 ps
CPU time 1.22 seconds
Started Jul 22 05:43:47 PM PDT 24
Finished Jul 22 05:43:49 PM PDT 24
Peak memory 219044 kb
Host smart-a810c651-01f9-481c-97b4-a8fed133f620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200169671 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.4200169671
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.1137713046
Short name T174
Test name
Test status
Simulation time 18225547 ps
CPU time 1.1 seconds
Started Jul 22 05:43:44 PM PDT 24
Finished Jul 22 05:43:47 PM PDT 24
Peak memory 224256 kb
Host smart-04e682cf-19d2-4df5-bca6-d29b1dd076b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137713046 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.1137713046
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.1321506918
Short name T222
Test name
Test status
Simulation time 36576109 ps
CPU time 1.35 seconds
Started Jul 22 05:43:47 PM PDT 24
Finished Jul 22 05:43:49 PM PDT 24
Peak memory 220236 kb
Host smart-b120367a-c405-49f7-971e-914a8d33bed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321506918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.1321506918
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.1459883332
Short name T869
Test name
Test status
Simulation time 48684393 ps
CPU time 1.13 seconds
Started Jul 22 05:43:50 PM PDT 24
Finished Jul 22 05:43:52 PM PDT 24
Peak memory 220188 kb
Host smart-8b05ecd4-e239-469a-ade3-10506f8e1032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459883332 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.1459883332
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.3375565514
Short name T392
Test name
Test status
Simulation time 19461623 ps
CPU time 1.13 seconds
Started Jul 22 05:43:44 PM PDT 24
Finished Jul 22 05:43:46 PM PDT 24
Peak memory 218916 kb
Host smart-c5af77cd-2e4a-48bb-98a0-7383a6edaa81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375565514 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.3375565514
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.2477905611
Short name T584
Test name
Test status
Simulation time 51574237 ps
CPU time 1.29 seconds
Started Jul 22 05:43:43 PM PDT 24
Finished Jul 22 05:43:46 PM PDT 24
Peak memory 218792 kb
Host smart-5174ae84-e527-428a-950d-ccca3ca5fccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477905611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.2477905611
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.60045818
Short name T305
Test name
Test status
Simulation time 36650808 ps
CPU time 1.06 seconds
Started Jul 22 05:43:43 PM PDT 24
Finished Jul 22 05:43:46 PM PDT 24
Peak memory 218984 kb
Host smart-fe334e22-7011-4fc4-a3c2-1a0f31608f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60045818 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.60045818
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_genbits.2597630015
Short name T451
Test name
Test status
Simulation time 119987398 ps
CPU time 3.05 seconds
Started Jul 22 05:43:47 PM PDT 24
Finished Jul 22 05:43:51 PM PDT 24
Peak memory 219628 kb
Host smart-13dc1a05-b05b-41e2-9eef-cf79f9d1e162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597630015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.2597630015
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.1695569433
Short name T906
Test name
Test status
Simulation time 21959032 ps
CPU time 1.18 seconds
Started Jul 22 05:43:46 PM PDT 24
Finished Jul 22 05:43:48 PM PDT 24
Peak memory 219108 kb
Host smart-e176bcbe-6dcc-4fc0-8982-f44c5fa12c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695569433 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.1695569433
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.3868640960
Short name T206
Test name
Test status
Simulation time 20644598 ps
CPU time 1.1 seconds
Started Jul 22 05:43:50 PM PDT 24
Finished Jul 22 05:43:51 PM PDT 24
Peak memory 220004 kb
Host smart-0bfe3a9e-5aeb-4067-8df2-b962c4f5b37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868640960 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.3868640960
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.3778059395
Short name T712
Test name
Test status
Simulation time 56146532 ps
CPU time 1.29 seconds
Started Jul 22 05:43:45 PM PDT 24
Finished Jul 22 05:43:48 PM PDT 24
Peak memory 217652 kb
Host smart-838687ff-737b-401a-b81c-cd73be2a4454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778059395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3778059395
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.2210692646
Short name T744
Test name
Test status
Simulation time 23098805 ps
CPU time 1.21 seconds
Started Jul 22 05:43:46 PM PDT 24
Finished Jul 22 05:43:49 PM PDT 24
Peak memory 221264 kb
Host smart-ca3678ab-a690-47a3-bf0f-8c68a97223cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210692646 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.2210692646
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.2930050067
Short name T756
Test name
Test status
Simulation time 33775913 ps
CPU time 0.84 seconds
Started Jul 22 05:43:42 PM PDT 24
Finished Jul 22 05:43:44 PM PDT 24
Peak memory 218696 kb
Host smart-c333d308-1f41-416a-83a7-6fc25fb6b326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930050067 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.2930050067
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.4291034302
Short name T343
Test name
Test status
Simulation time 34395664 ps
CPU time 1.02 seconds
Started Jul 22 05:43:49 PM PDT 24
Finished Jul 22 05:43:51 PM PDT 24
Peak memory 217664 kb
Host smart-28c4ec6b-619d-4ae0-9ba8-2e2e5a1aff87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291034302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.4291034302
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.2147755970
Short name T443
Test name
Test status
Simulation time 124781471 ps
CPU time 1.12 seconds
Started Jul 22 05:43:42 PM PDT 24
Finished Jul 22 05:43:44 PM PDT 24
Peak memory 222044 kb
Host smart-51b49894-8bea-4330-8f57-e400291ccf10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147755970 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.2147755970
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.3753049458
Short name T240
Test name
Test status
Simulation time 26756464 ps
CPU time 0.87 seconds
Started Jul 22 05:43:44 PM PDT 24
Finished Jul 22 05:43:47 PM PDT 24
Peak memory 218508 kb
Host smart-c1021e69-c9a8-449d-8f7c-6907140a6cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753049458 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.3753049458
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.2576583041
Short name T921
Test name
Test status
Simulation time 76484929 ps
CPU time 1.36 seconds
Started Jul 22 05:43:44 PM PDT 24
Finished Jul 22 05:43:47 PM PDT 24
Peak memory 218696 kb
Host smart-4e7770ac-102f-478b-8821-40f5f323089d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576583041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.2576583041
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.2348243793
Short name T84
Test name
Test status
Simulation time 102584951 ps
CPU time 1.14 seconds
Started Jul 22 05:43:51 PM PDT 24
Finished Jul 22 05:43:53 PM PDT 24
Peak memory 215980 kb
Host smart-eb7a6050-63f4-44da-aabd-334786df89a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348243793 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.2348243793
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.2100668331
Short name T100
Test name
Test status
Simulation time 23505857 ps
CPU time 1.13 seconds
Started Jul 22 05:43:51 PM PDT 24
Finished Jul 22 05:43:52 PM PDT 24
Peak memory 229884 kb
Host smart-b6fdd9e4-be15-4a3a-afef-f0cc40c72c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100668331 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.2100668331
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.2359788611
Short name T908
Test name
Test status
Simulation time 57298965 ps
CPU time 2.06 seconds
Started Jul 22 05:43:50 PM PDT 24
Finished Jul 22 05:43:53 PM PDT 24
Peak memory 219100 kb
Host smart-de3fbc4b-d853-4163-96c8-4dc61233ae01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359788611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.2359788611
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.428208078
Short name T734
Test name
Test status
Simulation time 27066956 ps
CPU time 1.27 seconds
Started Jul 22 05:42:01 PM PDT 24
Finished Jul 22 05:42:03 PM PDT 24
Peak memory 219992 kb
Host smart-76165e61-73be-44f9-8bfe-34f7808b8897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428208078 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.428208078
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.1345289839
Short name T355
Test name
Test status
Simulation time 16165277 ps
CPU time 0.95 seconds
Started Jul 22 05:42:04 PM PDT 24
Finished Jul 22 05:42:06 PM PDT 24
Peak memory 215472 kb
Host smart-29e1f220-bc6e-4253-b3f4-de86ae71c674
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345289839 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1345289839
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.374876242
Short name T837
Test name
Test status
Simulation time 14068889 ps
CPU time 0.89 seconds
Started Jul 22 05:42:00 PM PDT 24
Finished Jul 22 05:42:02 PM PDT 24
Peak memory 215880 kb
Host smart-acb891a3-69b4-4ffa-bf1e-e342b950018b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374876242 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.374876242
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.146328776
Short name T898
Test name
Test status
Simulation time 73876847 ps
CPU time 1.25 seconds
Started Jul 22 05:42:02 PM PDT 24
Finished Jul 22 05:42:03 PM PDT 24
Peak memory 217284 kb
Host smart-0fc2b22a-5edb-4bb5-a687-24130a3c6db7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146328776 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_dis
able_auto_req_mode.146328776
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.2933453438
Short name T166
Test name
Test status
Simulation time 54076176 ps
CPU time 1.01 seconds
Started Jul 22 05:42:04 PM PDT 24
Finished Jul 22 05:42:05 PM PDT 24
Peak memory 224120 kb
Host smart-642b158a-46d6-4c5c-b954-d05061dbfa07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933453438 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.2933453438
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.2104317937
Short name T327
Test name
Test status
Simulation time 24833833 ps
CPU time 1.28 seconds
Started Jul 22 05:42:03 PM PDT 24
Finished Jul 22 05:42:05 PM PDT 24
Peak memory 217992 kb
Host smart-4496b2de-8cf2-4d26-9105-b70300176245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104317937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.2104317937
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.3668578737
Short name T524
Test name
Test status
Simulation time 40815828 ps
CPU time 1 seconds
Started Jul 22 05:42:07 PM PDT 24
Finished Jul 22 05:42:08 PM PDT 24
Peak memory 224160 kb
Host smart-000b7d54-ba6d-40da-9e02-0a1d5a8c7beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668578737 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.3668578737
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.4241238571
Short name T847
Test name
Test status
Simulation time 27503080 ps
CPU time 0.89 seconds
Started Jul 22 05:42:01 PM PDT 24
Finished Jul 22 05:42:03 PM PDT 24
Peak memory 207388 kb
Host smart-ef7505de-af64-4e47-bf8b-83d3d41f9e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241238571 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.4241238571
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.3227675097
Short name T60
Test name
Test status
Simulation time 16005626 ps
CPU time 0.98 seconds
Started Jul 22 05:42:02 PM PDT 24
Finished Jul 22 05:42:04 PM PDT 24
Peak memory 215620 kb
Host smart-b9c6f168-5125-4ecc-805f-a1b4b4162e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227675097 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.3227675097
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.3426913989
Short name T940
Test name
Test status
Simulation time 2042835228 ps
CPU time 4.86 seconds
Started Jul 22 05:42:00 PM PDT 24
Finished Jul 22 05:42:06 PM PDT 24
Peak memory 215684 kb
Host smart-86c7bba5-2c6e-477c-9b24-78b9e32c868b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426913989 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.3426913989
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.1471879557
Short name T89
Test name
Test status
Simulation time 154377418165 ps
CPU time 2024.97 seconds
Started Jul 22 05:42:00 PM PDT 24
Finished Jul 22 06:15:46 PM PDT 24
Peak memory 229676 kb
Host smart-8053cc77-e8f8-4abb-be87-e3d6b1333a51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471879557 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.1471879557
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.1588244942
Short name T876
Test name
Test status
Simulation time 87617906 ps
CPU time 1.15 seconds
Started Jul 22 05:43:52 PM PDT 24
Finished Jul 22 05:43:54 PM PDT 24
Peak memory 216072 kb
Host smart-48281abd-048b-45e8-af22-0ce1aa852df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588244942 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.1588244942
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.1305715775
Short name T104
Test name
Test status
Simulation time 25191625 ps
CPU time 1.26 seconds
Started Jul 22 05:43:54 PM PDT 24
Finished Jul 22 05:43:56 PM PDT 24
Peak memory 230020 kb
Host smart-e4d3fa13-61bc-449c-a881-af75a9dceab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305715775 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.1305715775
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.280037936
Short name T316
Test name
Test status
Simulation time 109445369 ps
CPU time 1.74 seconds
Started Jul 22 05:43:53 PM PDT 24
Finished Jul 22 05:43:56 PM PDT 24
Peak memory 219176 kb
Host smart-dd06c796-e4d6-4922-bfc6-905aca4152b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280037936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.280037936
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.3896564987
Short name T786
Test name
Test status
Simulation time 67436653 ps
CPU time 1.19 seconds
Started Jul 22 05:43:51 PM PDT 24
Finished Jul 22 05:43:54 PM PDT 24
Peak memory 221800 kb
Host smart-237032e3-15bd-41c9-9dfa-adce2008d476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896564987 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.3896564987
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.3878235726
Short name T54
Test name
Test status
Simulation time 32601621 ps
CPU time 1.29 seconds
Started Jul 22 05:43:57 PM PDT 24
Finished Jul 22 05:43:59 PM PDT 24
Peak memory 225880 kb
Host smart-903f9b59-b7a9-40e4-9dea-cffa698a34e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878235726 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3878235726
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.2731846506
Short name T911
Test name
Test status
Simulation time 51702508 ps
CPU time 1.15 seconds
Started Jul 22 05:43:58 PM PDT 24
Finished Jul 22 05:44:00 PM PDT 24
Peak memory 218696 kb
Host smart-8b81af6e-2056-40a8-ad8c-a24b074a1156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731846506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.2731846506
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.117717712
Short name T909
Test name
Test status
Simulation time 26958623 ps
CPU time 1.17 seconds
Started Jul 22 05:43:53 PM PDT 24
Finished Jul 22 05:43:55 PM PDT 24
Peak memory 219024 kb
Host smart-1475fbed-26b0-4f76-852b-ea7c60068fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117717712 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.117717712
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.2987077923
Short name T145
Test name
Test status
Simulation time 23681654 ps
CPU time 1.15 seconds
Started Jul 22 05:43:58 PM PDT 24
Finished Jul 22 05:44:01 PM PDT 24
Peak memory 220004 kb
Host smart-08fd2ec8-5a48-4142-9f85-59aabee4d4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987077923 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.2987077923
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.264618400
Short name T461
Test name
Test status
Simulation time 165065513 ps
CPU time 0.97 seconds
Started Jul 22 05:43:52 PM PDT 24
Finished Jul 22 05:43:54 PM PDT 24
Peak memory 217580 kb
Host smart-29b7486f-bd39-4b31-bf7b-2ab7f7de737a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264618400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.264618400
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.810156566
Short name T403
Test name
Test status
Simulation time 404844198 ps
CPU time 1.55 seconds
Started Jul 22 05:43:51 PM PDT 24
Finished Jul 22 05:43:54 PM PDT 24
Peak memory 219932 kb
Host smart-f64b7d29-8b05-4fdd-ad03-4b7ba890ba88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810156566 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.810156566
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.2129046359
Short name T140
Test name
Test status
Simulation time 34548626 ps
CPU time 1.12 seconds
Started Jul 22 05:43:57 PM PDT 24
Finished Jul 22 05:43:59 PM PDT 24
Peak memory 220976 kb
Host smart-62700202-13d1-4b94-9187-d0d484b01045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129046359 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.2129046359
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.1435915328
Short name T757
Test name
Test status
Simulation time 73979793 ps
CPU time 1.72 seconds
Started Jul 22 05:43:51 PM PDT 24
Finished Jul 22 05:43:54 PM PDT 24
Peak memory 219032 kb
Host smart-917ccd2c-a7c8-4a68-b95b-b48353ac167b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435915328 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.1435915328
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.3630030929
Short name T294
Test name
Test status
Simulation time 43718907 ps
CPU time 1.16 seconds
Started Jul 22 05:43:56 PM PDT 24
Finished Jul 22 05:43:58 PM PDT 24
Peak memory 219108 kb
Host smart-760d63dc-a44a-4cbe-ac9e-90041d83c130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630030929 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.3630030929
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.982585587
Short name T670
Test name
Test status
Simulation time 75440221 ps
CPU time 1.08 seconds
Started Jul 22 05:44:00 PM PDT 24
Finished Jul 22 05:44:02 PM PDT 24
Peak memory 219756 kb
Host smart-506dc87f-d73e-4531-a7d0-1cd56638cb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982585587 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.982585587
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.3576569841
Short name T783
Test name
Test status
Simulation time 100400938 ps
CPU time 1.15 seconds
Started Jul 22 05:44:00 PM PDT 24
Finished Jul 22 05:44:02 PM PDT 24
Peak memory 217512 kb
Host smart-74f5cada-1004-4fea-83a6-b17a6e536dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576569841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.3576569841
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.3178433580
Short name T149
Test name
Test status
Simulation time 51475605 ps
CPU time 1.28 seconds
Started Jul 22 05:43:53 PM PDT 24
Finished Jul 22 05:43:55 PM PDT 24
Peak memory 220156 kb
Host smart-c8f6ebe2-9692-4fbf-8a78-3b62ea662591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178433580 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.3178433580
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.1242980170
Short name T198
Test name
Test status
Simulation time 20916894 ps
CPU time 1.08 seconds
Started Jul 22 05:45:34 PM PDT 24
Finished Jul 22 05:45:37 PM PDT 24
Peak memory 219708 kb
Host smart-30dd0d3c-d214-4702-a264-19401c0d6a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242980170 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.1242980170
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.3479440082
Short name T735
Test name
Test status
Simulation time 50425077 ps
CPU time 1.4 seconds
Started Jul 22 05:47:17 PM PDT 24
Finished Jul 22 05:47:19 PM PDT 24
Peak memory 218984 kb
Host smart-452ac36f-1160-4f96-8220-a60041acb0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479440082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.3479440082
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.1271804839
Short name T628
Test name
Test status
Simulation time 27985593 ps
CPU time 1.23 seconds
Started Jul 22 05:43:57 PM PDT 24
Finished Jul 22 05:44:00 PM PDT 24
Peak memory 219784 kb
Host smart-5919b5d5-b423-4e3b-82f5-0498e6a0954e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271804839 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.1271804839
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.4091154654
Short name T772
Test name
Test status
Simulation time 26405603 ps
CPU time 0.9 seconds
Started Jul 22 05:43:59 PM PDT 24
Finished Jul 22 05:44:00 PM PDT 24
Peak memory 218316 kb
Host smart-f2b880de-e44b-4f71-96b1-c646d8cf1fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091154654 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.4091154654
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.3570489001
Short name T784
Test name
Test status
Simulation time 176032958 ps
CPU time 1.1 seconds
Started Jul 22 05:43:55 PM PDT 24
Finished Jul 22 05:43:56 PM PDT 24
Peak memory 217552 kb
Host smart-3594095c-775e-4079-8223-a83dbdf4890f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570489001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.3570489001
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.3497386564
Short name T242
Test name
Test status
Simulation time 157370507 ps
CPU time 1.13 seconds
Started Jul 22 05:43:52 PM PDT 24
Finished Jul 22 05:43:54 PM PDT 24
Peak memory 218892 kb
Host smart-05dd4c0b-95ac-419d-bf96-c698419138f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497386564 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.3497386564
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.2831439758
Short name T153
Test name
Test status
Simulation time 19535479 ps
CPU time 1.07 seconds
Started Jul 22 05:43:57 PM PDT 24
Finished Jul 22 05:43:58 PM PDT 24
Peak memory 218996 kb
Host smart-01b81049-71b4-471b-90e8-1e3b5d9e9b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831439758 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.2831439758
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.885227036
Short name T816
Test name
Test status
Simulation time 35982927 ps
CPU time 1.31 seconds
Started Jul 22 05:44:00 PM PDT 24
Finished Jul 22 05:44:02 PM PDT 24
Peak memory 217468 kb
Host smart-a1a42d82-a1da-4a73-bdfa-0e4835059c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885227036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.885227036
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.2425606093
Short name T189
Test name
Test status
Simulation time 49995429 ps
CPU time 1.1 seconds
Started Jul 22 05:43:57 PM PDT 24
Finished Jul 22 05:44:00 PM PDT 24
Peak memory 220852 kb
Host smart-caa82ec6-e810-4005-8a42-6b64b1a49bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425606093 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.2425606093
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.2663138982
Short name T738
Test name
Test status
Simulation time 20300888 ps
CPU time 1.12 seconds
Started Jul 22 05:43:52 PM PDT 24
Finished Jul 22 05:43:54 PM PDT 24
Peak memory 218816 kb
Host smart-2a23df39-d1f2-4130-b82a-80a77c3e1be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663138982 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.2663138982
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.3787669974
Short name T591
Test name
Test status
Simulation time 131281125 ps
CPU time 1.37 seconds
Started Jul 22 05:43:57 PM PDT 24
Finished Jul 22 05:44:00 PM PDT 24
Peak memory 219312 kb
Host smart-71ac141f-85dd-4c52-a16c-e351c3fab47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787669974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.3787669974
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.1510274439
Short name T119
Test name
Test status
Simulation time 30755748 ps
CPU time 1.3 seconds
Started Jul 22 05:44:00 PM PDT 24
Finished Jul 22 05:44:02 PM PDT 24
Peak memory 219452 kb
Host smart-54c7d171-8a4f-4707-8120-f7c2ba065dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510274439 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.1510274439
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.2404553843
Short name T622
Test name
Test status
Simulation time 37457606 ps
CPU time 1.15 seconds
Started Jul 22 05:43:53 PM PDT 24
Finished Jul 22 05:43:55 PM PDT 24
Peak memory 217816 kb
Host smart-87471444-c641-4ad3-b490-81db3c1f1bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404553843 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.2404553843
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.2012644861
Short name T358
Test name
Test status
Simulation time 30366833 ps
CPU time 1.1 seconds
Started Jul 22 05:43:58 PM PDT 24
Finished Jul 22 05:44:00 PM PDT 24
Peak memory 220236 kb
Host smart-da3e0738-7043-4cd3-a8f0-88411639818a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012644861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.2012644861
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%