Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.67 98.25 93.97 97.02 92.44 96.37 99.77 91.89


Total test records in report: 1129
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T262 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.4273566497 Jul 23 07:04:37 PM PDT 24 Jul 23 07:04:41 PM PDT 24 132394099 ps
T263 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1071335169 Jul 23 07:04:45 PM PDT 24 Jul 23 07:04:47 PM PDT 24 15303805 ps
T264 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.48451745 Jul 23 07:03:57 PM PDT 24 Jul 23 07:03:59 PM PDT 24 92054084 ps
T1020 /workspace/coverage/cover_reg_top/37.edn_intr_test.1647832093 Jul 23 07:04:48 PM PDT 24 Jul 23 07:04:51 PM PDT 24 32852080 ps
T1021 /workspace/coverage/cover_reg_top/5.edn_tl_errors.54297305 Jul 23 07:04:15 PM PDT 24 Jul 23 07:04:20 PM PDT 24 106622968 ps
T1022 /workspace/coverage/cover_reg_top/16.edn_csr_rw.3333337822 Jul 23 07:04:39 PM PDT 24 Jul 23 07:04:42 PM PDT 24 17420754 ps
T1023 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1994665042 Jul 23 07:03:46 PM PDT 24 Jul 23 07:03:50 PM PDT 24 240948464 ps
T1024 /workspace/coverage/cover_reg_top/11.edn_csr_rw.1993009131 Jul 23 07:04:34 PM PDT 24 Jul 23 07:04:37 PM PDT 24 47983563 ps
T1025 /workspace/coverage/cover_reg_top/38.edn_intr_test.3311482690 Jul 23 07:04:47 PM PDT 24 Jul 23 07:04:49 PM PDT 24 11756398 ps
T1026 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.148078657 Jul 23 07:03:54 PM PDT 24 Jul 23 07:03:57 PM PDT 24 169667737 ps
T1027 /workspace/coverage/cover_reg_top/11.edn_tl_errors.1381096458 Jul 23 07:04:33 PM PDT 24 Jul 23 07:04:37 PM PDT 24 85379194 ps
T1028 /workspace/coverage/cover_reg_top/30.edn_intr_test.558484224 Jul 23 07:04:47 PM PDT 24 Jul 23 07:04:49 PM PDT 24 142826965 ps
T1029 /workspace/coverage/cover_reg_top/25.edn_intr_test.1034397749 Jul 23 07:04:45 PM PDT 24 Jul 23 07:04:47 PM PDT 24 37975304 ps
T1030 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.525970026 Jul 23 07:03:49 PM PDT 24 Jul 23 07:03:51 PM PDT 24 22410780 ps
T265 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3003593549 Jul 23 07:04:14 PM PDT 24 Jul 23 07:04:16 PM PDT 24 72574089 ps
T1031 /workspace/coverage/cover_reg_top/20.edn_intr_test.2708061087 Jul 23 07:04:47 PM PDT 24 Jul 23 07:04:49 PM PDT 24 19048643 ps
T1032 /workspace/coverage/cover_reg_top/15.edn_csr_rw.3077411630 Jul 23 07:04:33 PM PDT 24 Jul 23 07:04:36 PM PDT 24 27469192 ps
T255 /workspace/coverage/cover_reg_top/10.edn_csr_rw.947493703 Jul 23 07:04:35 PM PDT 24 Jul 23 07:04:38 PM PDT 24 115531304 ps
T1033 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2057914596 Jul 23 07:04:06 PM PDT 24 Jul 23 07:04:08 PM PDT 24 19197824 ps
T1034 /workspace/coverage/cover_reg_top/0.edn_intr_test.3986183213 Jul 23 07:03:44 PM PDT 24 Jul 23 07:03:46 PM PDT 24 32088762 ps
T1035 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1958968972 Jul 23 07:04:26 PM PDT 24 Jul 23 07:04:29 PM PDT 24 29572217 ps
T280 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1981120417 Jul 23 07:04:34 PM PDT 24 Jul 23 07:04:38 PM PDT 24 462096685 ps
T1036 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3701403578 Jul 23 07:04:26 PM PDT 24 Jul 23 07:04:29 PM PDT 24 45620829 ps
T1037 /workspace/coverage/cover_reg_top/2.edn_csr_rw.3081692296 Jul 23 07:03:51 PM PDT 24 Jul 23 07:03:53 PM PDT 24 51184627 ps
T1038 /workspace/coverage/cover_reg_top/1.edn_csr_rw.3003471511 Jul 23 07:03:51 PM PDT 24 Jul 23 07:03:53 PM PDT 24 42108057 ps
T1039 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3974047188 Jul 23 07:04:07 PM PDT 24 Jul 23 07:04:09 PM PDT 24 98563594 ps
T1040 /workspace/coverage/cover_reg_top/13.edn_tl_errors.1375219452 Jul 23 07:04:32 PM PDT 24 Jul 23 07:04:38 PM PDT 24 192133522 ps
T1041 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1352555422 Jul 23 07:03:49 PM PDT 24 Jul 23 07:03:52 PM PDT 24 85652855 ps
T1042 /workspace/coverage/cover_reg_top/6.edn_tl_errors.297339833 Jul 23 07:04:16 PM PDT 24 Jul 23 07:04:22 PM PDT 24 358376437 ps
T1043 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.114237903 Jul 23 07:04:40 PM PDT 24 Jul 23 07:04:43 PM PDT 24 226336000 ps
T1044 /workspace/coverage/cover_reg_top/22.edn_intr_test.2318989000 Jul 23 07:04:43 PM PDT 24 Jul 23 07:04:44 PM PDT 24 28291559 ps
T1045 /workspace/coverage/cover_reg_top/8.edn_intr_test.3109216815 Jul 23 07:04:27 PM PDT 24 Jul 23 07:04:29 PM PDT 24 97829771 ps
T1046 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1057214384 Jul 23 07:04:35 PM PDT 24 Jul 23 07:04:39 PM PDT 24 257764356 ps
T1047 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2116631374 Jul 23 07:04:37 PM PDT 24 Jul 23 07:04:42 PM PDT 24 77436456 ps
T1048 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2109318476 Jul 23 07:04:39 PM PDT 24 Jul 23 07:04:42 PM PDT 24 17432951 ps
T1049 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2497894325 Jul 23 07:04:17 PM PDT 24 Jul 23 07:04:22 PM PDT 24 198721495 ps
T1050 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1536935607 Jul 23 07:04:07 PM PDT 24 Jul 23 07:04:09 PM PDT 24 37316114 ps
T1051 /workspace/coverage/cover_reg_top/10.edn_intr_test.2699187352 Jul 23 07:04:35 PM PDT 24 Jul 23 07:04:39 PM PDT 24 19922849 ps
T1052 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1571596782 Jul 23 07:04:25 PM PDT 24 Jul 23 07:04:27 PM PDT 24 23302857 ps
T1053 /workspace/coverage/cover_reg_top/5.edn_intr_test.4055172394 Jul 23 07:04:15 PM PDT 24 Jul 23 07:04:17 PM PDT 24 169077031 ps
T1054 /workspace/coverage/cover_reg_top/4.edn_csr_rw.4252497780 Jul 23 07:04:05 PM PDT 24 Jul 23 07:04:07 PM PDT 24 11693132 ps
T1055 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2800771928 Jul 23 07:04:32 PM PDT 24 Jul 23 07:04:35 PM PDT 24 44075414 ps
T1056 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.468567465 Jul 23 07:04:37 PM PDT 24 Jul 23 07:04:40 PM PDT 24 275060951 ps
T249 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.319881420 Jul 23 07:04:07 PM PDT 24 Jul 23 07:04:09 PM PDT 24 54347258 ps
T1057 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.931521807 Jul 23 07:04:35 PM PDT 24 Jul 23 07:04:39 PM PDT 24 60778156 ps
T1058 /workspace/coverage/cover_reg_top/9.edn_csr_rw.3150511239 Jul 23 07:04:25 PM PDT 24 Jul 23 07:04:28 PM PDT 24 25606438 ps
T1059 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3157515136 Jul 23 07:04:26 PM PDT 24 Jul 23 07:04:28 PM PDT 24 95550193 ps
T1060 /workspace/coverage/cover_reg_top/9.edn_tl_errors.2860493890 Jul 23 07:04:28 PM PDT 24 Jul 23 07:04:31 PM PDT 24 75292630 ps
T250 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2635280801 Jul 23 07:03:54 PM PDT 24 Jul 23 07:03:57 PM PDT 24 14319388 ps
T1061 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2370948139 Jul 23 07:04:25 PM PDT 24 Jul 23 07:04:27 PM PDT 24 24556277 ps
T1062 /workspace/coverage/cover_reg_top/17.edn_tl_errors.4113212658 Jul 23 07:04:37 PM PDT 24 Jul 23 07:04:42 PM PDT 24 48221300 ps
T1063 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2925394028 Jul 23 07:04:32 PM PDT 24 Jul 23 07:04:35 PM PDT 24 19467750 ps
T1064 /workspace/coverage/cover_reg_top/9.edn_intr_test.310459772 Jul 23 07:04:26 PM PDT 24 Jul 23 07:04:29 PM PDT 24 15330019 ps
T256 /workspace/coverage/cover_reg_top/7.edn_csr_rw.4162990788 Jul 23 07:04:27 PM PDT 24 Jul 23 07:04:29 PM PDT 24 19736893 ps
T1065 /workspace/coverage/cover_reg_top/23.edn_intr_test.2071300486 Jul 23 07:04:45 PM PDT 24 Jul 23 07:04:47 PM PDT 24 23807968 ps
T1066 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.978736246 Jul 23 07:04:24 PM PDT 24 Jul 23 07:04:26 PM PDT 24 36566009 ps
T1067 /workspace/coverage/cover_reg_top/32.edn_intr_test.1184036872 Jul 23 07:04:47 PM PDT 24 Jul 23 07:04:49 PM PDT 24 22304824 ps
T251 /workspace/coverage/cover_reg_top/12.edn_csr_rw.425914174 Jul 23 07:04:32 PM PDT 24 Jul 23 07:04:33 PM PDT 24 22883906 ps
T1068 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3114121636 Jul 23 07:04:15 PM PDT 24 Jul 23 07:04:18 PM PDT 24 34619856 ps
T1069 /workspace/coverage/cover_reg_top/15.edn_tl_errors.4231164239 Jul 23 07:04:33 PM PDT 24 Jul 23 07:04:37 PM PDT 24 83119973 ps
T1070 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1480850284 Jul 23 07:03:44 PM PDT 24 Jul 23 07:03:45 PM PDT 24 17598998 ps
T1071 /workspace/coverage/cover_reg_top/8.edn_csr_rw.41645424 Jul 23 07:04:25 PM PDT 24 Jul 23 07:04:27 PM PDT 24 12767183 ps
T252 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2849893937 Jul 23 07:04:07 PM PDT 24 Jul 23 07:04:09 PM PDT 24 143174567 ps
T1072 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1628154519 Jul 23 07:04:34 PM PDT 24 Jul 23 07:04:37 PM PDT 24 98482899 ps
T1073 /workspace/coverage/cover_reg_top/14.edn_tl_errors.3074978292 Jul 23 07:04:35 PM PDT 24 Jul 23 07:04:41 PM PDT 24 333367325 ps
T1074 /workspace/coverage/cover_reg_top/33.edn_intr_test.3830548496 Jul 23 07:04:48 PM PDT 24 Jul 23 07:04:49 PM PDT 24 30644284 ps
T1075 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.424541220 Jul 23 07:03:56 PM PDT 24 Jul 23 07:03:59 PM PDT 24 51772240 ps
T1076 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3745019007 Jul 23 07:04:16 PM PDT 24 Jul 23 07:04:18 PM PDT 24 56835311 ps
T1077 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3322499285 Jul 23 07:03:49 PM PDT 24 Jul 23 07:03:52 PM PDT 24 26921276 ps
T1078 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.4130965825 Jul 23 07:04:38 PM PDT 24 Jul 23 07:04:41 PM PDT 24 32616657 ps
T1079 /workspace/coverage/cover_reg_top/4.edn_intr_test.3124290138 Jul 23 07:04:06 PM PDT 24 Jul 23 07:04:08 PM PDT 24 16098164 ps
T1080 /workspace/coverage/cover_reg_top/7.edn_intr_test.1112596502 Jul 23 07:04:25 PM PDT 24 Jul 23 07:04:27 PM PDT 24 45145819 ps
T281 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.444872653 Jul 23 07:04:32 PM PDT 24 Jul 23 07:04:35 PM PDT 24 192096485 ps
T1081 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3989834833 Jul 23 07:04:32 PM PDT 24 Jul 23 07:04:34 PM PDT 24 31824027 ps
T1082 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1797643296 Jul 23 07:03:50 PM PDT 24 Jul 23 07:03:54 PM PDT 24 35354691 ps
T253 /workspace/coverage/cover_reg_top/13.edn_csr_rw.2199776515 Jul 23 07:04:33 PM PDT 24 Jul 23 07:04:36 PM PDT 24 16848131 ps
T1083 /workspace/coverage/cover_reg_top/31.edn_intr_test.4269618690 Jul 23 07:04:50 PM PDT 24 Jul 23 07:04:52 PM PDT 24 16848465 ps
T1084 /workspace/coverage/cover_reg_top/49.edn_intr_test.2423768331 Jul 23 07:04:53 PM PDT 24 Jul 23 07:04:55 PM PDT 24 13992313 ps
T1085 /workspace/coverage/cover_reg_top/45.edn_intr_test.2937878531 Jul 23 07:04:52 PM PDT 24 Jul 23 07:04:54 PM PDT 24 14752370 ps
T282 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3685454977 Jul 23 07:03:58 PM PDT 24 Jul 23 07:04:01 PM PDT 24 77928238 ps
T1086 /workspace/coverage/cover_reg_top/3.edn_csr_rw.554955875 Jul 23 07:03:57 PM PDT 24 Jul 23 07:03:59 PM PDT 24 53865385 ps
T1087 /workspace/coverage/cover_reg_top/35.edn_intr_test.2340177945 Jul 23 07:04:48 PM PDT 24 Jul 23 07:04:50 PM PDT 24 11643299 ps
T1088 /workspace/coverage/cover_reg_top/43.edn_intr_test.2028003220 Jul 23 07:04:52 PM PDT 24 Jul 23 07:04:55 PM PDT 24 51316304 ps
T1089 /workspace/coverage/cover_reg_top/13.edn_intr_test.3252993697 Jul 23 07:04:30 PM PDT 24 Jul 23 07:04:32 PM PDT 24 57740677 ps
T1090 /workspace/coverage/cover_reg_top/18.edn_csr_rw.1365209550 Jul 23 07:04:37 PM PDT 24 Jul 23 07:04:40 PM PDT 24 26336167 ps
T257 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2892536355 Jul 23 07:04:06 PM PDT 24 Jul 23 07:04:09 PM PDT 24 255748281 ps
T1091 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3386146352 Jul 23 07:04:36 PM PDT 24 Jul 23 07:04:40 PM PDT 24 47942903 ps
T1092 /workspace/coverage/cover_reg_top/47.edn_intr_test.692679004 Jul 23 07:04:53 PM PDT 24 Jul 23 07:04:55 PM PDT 24 13504195 ps
T1093 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1790963506 Jul 23 07:04:39 PM PDT 24 Jul 23 07:04:42 PM PDT 24 691967264 ps
T1094 /workspace/coverage/cover_reg_top/8.edn_tl_errors.1289805266 Jul 23 07:04:25 PM PDT 24 Jul 23 07:04:27 PM PDT 24 93154902 ps
T1095 /workspace/coverage/cover_reg_top/16.edn_tl_errors.1623219496 Jul 23 07:04:33 PM PDT 24 Jul 23 07:04:37 PM PDT 24 65862193 ps
T1096 /workspace/coverage/cover_reg_top/12.edn_tl_errors.2066743170 Jul 23 07:04:31 PM PDT 24 Jul 23 07:04:34 PM PDT 24 59167918 ps
T1097 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3693006627 Jul 23 07:04:35 PM PDT 24 Jul 23 07:04:38 PM PDT 24 19674620 ps
T1098 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3868808682 Jul 23 07:03:53 PM PDT 24 Jul 23 07:03:57 PM PDT 24 99007997 ps
T258 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1484674499 Jul 23 07:03:58 PM PDT 24 Jul 23 07:04:05 PM PDT 24 257608318 ps
T1099 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.202036596 Jul 23 07:04:34 PM PDT 24 Jul 23 07:04:38 PM PDT 24 103311217 ps
T1100 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.4151197987 Jul 23 07:03:55 PM PDT 24 Jul 23 07:03:57 PM PDT 24 317843963 ps
T1101 /workspace/coverage/cover_reg_top/26.edn_intr_test.2041405972 Jul 23 07:04:42 PM PDT 24 Jul 23 07:04:43 PM PDT 24 26536029 ps
T1102 /workspace/coverage/cover_reg_top/3.edn_tl_errors.2285832855 Jul 23 07:03:56 PM PDT 24 Jul 23 07:04:01 PM PDT 24 77061237 ps
T1103 /workspace/coverage/cover_reg_top/10.edn_tl_errors.364725197 Jul 23 07:04:25 PM PDT 24 Jul 23 07:04:30 PM PDT 24 433680746 ps
T1104 /workspace/coverage/cover_reg_top/16.edn_intr_test.2710539333 Jul 23 07:04:39 PM PDT 24 Jul 23 07:04:42 PM PDT 24 35341098 ps
T1105 /workspace/coverage/cover_reg_top/28.edn_intr_test.424657033 Jul 23 07:04:47 PM PDT 24 Jul 23 07:04:49 PM PDT 24 41038078 ps
T1106 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.876082966 Jul 23 07:04:08 PM PDT 24 Jul 23 07:04:11 PM PDT 24 120287594 ps
T1107 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.491850715 Jul 23 07:04:32 PM PDT 24 Jul 23 07:04:35 PM PDT 24 87039515 ps
T1108 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.430178915 Jul 23 07:04:07 PM PDT 24 Jul 23 07:04:09 PM PDT 24 108580766 ps
T1109 /workspace/coverage/cover_reg_top/48.edn_intr_test.3934785079 Jul 23 07:04:53 PM PDT 24 Jul 23 07:04:55 PM PDT 24 46833028 ps
T1110 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3100161263 Jul 23 07:04:25 PM PDT 24 Jul 23 07:04:28 PM PDT 24 128867388 ps
T254 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2792931344 Jul 23 07:03:54 PM PDT 24 Jul 23 07:03:57 PM PDT 24 236619483 ps
T1111 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2458956635 Jul 23 07:04:45 PM PDT 24 Jul 23 07:04:48 PM PDT 24 203449492 ps
T1112 /workspace/coverage/cover_reg_top/44.edn_intr_test.366528816 Jul 23 07:04:52 PM PDT 24 Jul 23 07:04:54 PM PDT 24 39714161 ps
T1113 /workspace/coverage/cover_reg_top/4.edn_tl_errors.3794966416 Jul 23 07:04:07 PM PDT 24 Jul 23 07:04:11 PM PDT 24 271739604 ps
T1114 /workspace/coverage/cover_reg_top/12.edn_intr_test.447480996 Jul 23 07:04:33 PM PDT 24 Jul 23 07:04:36 PM PDT 24 22202640 ps
T283 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3561098708 Jul 23 07:04:26 PM PDT 24 Jul 23 07:04:29 PM PDT 24 370067729 ps
T1115 /workspace/coverage/cover_reg_top/21.edn_intr_test.2289568744 Jul 23 07:04:45 PM PDT 24 Jul 23 07:04:47 PM PDT 24 12557238 ps
T1116 /workspace/coverage/cover_reg_top/18.edn_tl_errors.856222469 Jul 23 07:04:37 PM PDT 24 Jul 23 07:04:42 PM PDT 24 79406338 ps
T1117 /workspace/coverage/cover_reg_top/0.edn_csr_rw.3789446443 Jul 23 07:03:44 PM PDT 24 Jul 23 07:03:46 PM PDT 24 37301070 ps
T1118 /workspace/coverage/cover_reg_top/14.edn_intr_test.1020825390 Jul 23 07:04:34 PM PDT 24 Jul 23 07:04:37 PM PDT 24 13273877 ps
T1119 /workspace/coverage/cover_reg_top/36.edn_intr_test.1269248605 Jul 23 07:04:48 PM PDT 24 Jul 23 07:04:50 PM PDT 24 56928960 ps
T1120 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3643210538 Jul 23 07:04:42 PM PDT 24 Jul 23 07:04:45 PM PDT 24 140412579 ps
T1121 /workspace/coverage/cover_reg_top/42.edn_intr_test.356292548 Jul 23 07:04:52 PM PDT 24 Jul 23 07:04:53 PM PDT 24 17259666 ps
T1122 /workspace/coverage/cover_reg_top/19.edn_tl_errors.3966161950 Jul 23 07:04:45 PM PDT 24 Jul 23 07:04:48 PM PDT 24 95439132 ps
T1123 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3035205585 Jul 23 07:04:32 PM PDT 24 Jul 23 07:04:34 PM PDT 24 150705099 ps
T1124 /workspace/coverage/cover_reg_top/2.edn_tl_errors.3414899586 Jul 23 07:03:52 PM PDT 24 Jul 23 07:03:57 PM PDT 24 473789172 ps
T1125 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1369532887 Jul 23 07:03:49 PM PDT 24 Jul 23 07:03:51 PM PDT 24 16648186 ps
T259 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2215457211 Jul 23 07:03:53 PM PDT 24 Jul 23 07:03:54 PM PDT 24 32908451 ps
T1126 /workspace/coverage/cover_reg_top/11.edn_intr_test.1623327838 Jul 23 07:04:34 PM PDT 24 Jul 23 07:04:37 PM PDT 24 39728620 ps
T1127 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.407215121 Jul 23 07:04:15 PM PDT 24 Jul 23 07:04:20 PM PDT 24 160991749 ps
T1128 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2293403261 Jul 23 07:04:34 PM PDT 24 Jul 23 07:04:38 PM PDT 24 32625519 ps
T1129 /workspace/coverage/cover_reg_top/0.edn_tl_errors.2303958437 Jul 23 07:03:45 PM PDT 24 Jul 23 07:03:48 PM PDT 24 110092502 ps

Test location /workspace/coverage/default/124.edn_genbits.924969234
Short name T1
Test name
Test status
Simulation time 117160510 ps
CPU time 1.64 seconds
Started Jul 23 07:10:44 PM PDT 24
Finished Jul 23 07:10:56 PM PDT 24
Peak memory 220644 kb
Host smart-4239073a-8211-4e62-ae30-f87ee48b2df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924969234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.924969234
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.1027782354
Short name T2
Test name
Test status
Simulation time 115486051185 ps
CPU time 374.77 seconds
Started Jul 23 07:09:46 PM PDT 24
Finished Jul 23 07:16:13 PM PDT 24
Peak memory 218876 kb
Host smart-a1ab7fc7-2f24-46bf-a4f1-ad7fefeea277
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027782354 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.1027782354
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/126.edn_alert.3784560988
Short name T14
Test name
Test status
Simulation time 63713502 ps
CPU time 1.17 seconds
Started Jul 23 07:10:39 PM PDT 24
Finished Jul 23 07:10:51 PM PDT 24
Peak memory 218832 kb
Host smart-c89d6f5b-69cb-4f4a-9565-cfed6ba1fa96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784560988 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.3784560988
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/2.edn_sec_cm.3547568626
Short name T16
Test name
Test status
Simulation time 1675564571 ps
CPU time 4.23 seconds
Started Jul 23 07:08:42 PM PDT 24
Finished Jul 23 07:08:48 PM PDT 24
Peak memory 235476 kb
Host smart-468c173d-905b-4e3f-90d6-1acffae4110a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547568626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.3547568626
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/57.edn_err.734336117
Short name T6
Test name
Test status
Simulation time 45350454 ps
CPU time 0.9 seconds
Started Jul 23 07:10:21 PM PDT 24
Finished Jul 23 07:10:29 PM PDT 24
Peak memory 220308 kb
Host smart-54a5d3ac-6852-479f-82d9-0dcd82eac96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734336117 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.734336117
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3468009901
Short name T40
Test name
Test status
Simulation time 52457116 ps
CPU time 1 seconds
Started Jul 23 07:09:35 PM PDT 24
Finished Jul 23 07:09:40 PM PDT 24
Peak memory 218540 kb
Host smart-f15d2252-11c1-4909-ac70-d7f45035e680
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468009901 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3468009901
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.909131281
Short name T5
Test name
Test status
Simulation time 97570903301 ps
CPU time 2474.65 seconds
Started Jul 23 07:10:04 PM PDT 24
Finished Jul 23 07:51:31 PM PDT 24
Peak memory 232624 kb
Host smart-5b2b6914-faad-4db6-aad6-9ed1fb2796df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909131281 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.909131281
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.3659616012
Short name T88
Test name
Test status
Simulation time 103677571 ps
CPU time 1.22 seconds
Started Jul 23 07:10:43 PM PDT 24
Finished Jul 23 07:10:55 PM PDT 24
Peak memory 220988 kb
Host smart-2646c1bb-97ed-4bfb-b430-0d68442d3e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659616012 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.3659616012
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/127.edn_alert.1215490047
Short name T26
Test name
Test status
Simulation time 86068858 ps
CPU time 1.11 seconds
Started Jul 23 07:10:43 PM PDT 24
Finished Jul 23 07:10:54 PM PDT 24
Peak memory 218820 kb
Host smart-0d13a0e1-2f61-4aa1-9ec9-74826b5a5ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215490047 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.1215490047
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/172.edn_alert.2819896026
Short name T266
Test name
Test status
Simulation time 32833014 ps
CPU time 1.29 seconds
Started Jul 23 07:11:00 PM PDT 24
Finished Jul 23 07:11:11 PM PDT 24
Peak memory 216072 kb
Host smart-4ad245ea-bc8b-4657-9cae-176b36de4806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819896026 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.2819896026
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/29.edn_disable.1396213213
Short name T46
Test name
Test status
Simulation time 16459254 ps
CPU time 0.85 seconds
Started Jul 23 07:09:40 PM PDT 24
Finished Jul 23 07:09:50 PM PDT 24
Peak memory 216556 kb
Host smart-064e403a-3da4-4d8a-930c-956866e770ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396213213 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1396213213
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2500892570
Short name T22
Test name
Test status
Simulation time 117701041 ps
CPU time 1.1 seconds
Started Jul 23 07:09:37 PM PDT 24
Finished Jul 23 07:09:43 PM PDT 24
Peak memory 217440 kb
Host smart-d139081d-9ac1-40ca-ba1a-15418f61876b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500892570 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2500892570
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_regwen.1963713934
Short name T558
Test name
Test status
Simulation time 48785830 ps
CPU time 0.88 seconds
Started Jul 23 07:08:40 PM PDT 24
Finished Jul 23 07:08:43 PM PDT 24
Peak memory 207424 kb
Host smart-dbf46280-9a9f-43e7-84cf-5b3ca472e795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963713934 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.1963713934
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.2586773867
Short name T122
Test name
Test status
Simulation time 34050384 ps
CPU time 1.25 seconds
Started Jul 23 07:09:13 PM PDT 24
Finished Jul 23 07:09:21 PM PDT 24
Peak memory 217372 kb
Host smart-1c158162-f205-4a51-a77e-ee5c39559a08
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586773867 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.2586773867
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1981120417
Short name T280
Test name
Test status
Simulation time 462096685 ps
CPU time 2.14 seconds
Started Jul 23 07:04:34 PM PDT 24
Finished Jul 23 07:04:38 PM PDT 24
Peak memory 206624 kb
Host smart-0e46e9ca-d6b3-4016-8bff-066b721dafc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981120417 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1981120417
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/default/194.edn_alert.3820336391
Short name T90
Test name
Test status
Simulation time 25072095 ps
CPU time 1.16 seconds
Started Jul 23 07:11:05 PM PDT 24
Finished Jul 23 07:11:15 PM PDT 24
Peak memory 220212 kb
Host smart-8ea5fd81-a6c4-4a63-8e8d-771dbae9f12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820336391 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.3820336391
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.1225500653
Short name T15
Test name
Test status
Simulation time 55130168 ps
CPU time 0.94 seconds
Started Jul 23 07:10:20 PM PDT 24
Finished Jul 23 07:10:28 PM PDT 24
Peak memory 229584 kb
Host smart-c460f06e-42da-49b5-8e71-7aefbba6d123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225500653 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.1225500653
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/103.edn_alert.2583235136
Short name T158
Test name
Test status
Simulation time 32940718 ps
CPU time 1.31 seconds
Started Jul 23 07:10:43 PM PDT 24
Finished Jul 23 07:10:55 PM PDT 24
Peak memory 219828 kb
Host smart-a1e41c46-47ec-4287-b660-918c326c41b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583235136 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.2583235136
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/13.edn_disable.1482405687
Short name T896
Test name
Test status
Simulation time 13480697 ps
CPU time 0.93 seconds
Started Jul 23 07:09:13 PM PDT 24
Finished Jul 23 07:09:20 PM PDT 24
Peak memory 216736 kb
Host smart-a2aee404-4ef7-42c5-a6f9-11a3c349874b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482405687 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1482405687
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable.883394669
Short name T169
Test name
Test status
Simulation time 23694967 ps
CPU time 0.9 seconds
Started Jul 23 07:09:35 PM PDT 24
Finished Jul 23 07:09:37 PM PDT 24
Peak memory 216708 kb
Host smart-280a6b18-5b5a-4a1d-9b47-488e0081c6b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883394669 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.883394669
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable.3204975148
Short name T206
Test name
Test status
Simulation time 45781200 ps
CPU time 0.84 seconds
Started Jul 23 07:09:42 PM PDT 24
Finished Jul 23 07:09:54 PM PDT 24
Peak memory 216720 kb
Host smart-e09cb013-75a6-40d3-87ef-420cd4be2500
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204975148 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3204975148
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2849893937
Short name T252
Test name
Test status
Simulation time 143174567 ps
CPU time 1.53 seconds
Started Jul 23 07:04:07 PM PDT 24
Finished Jul 23 07:04:09 PM PDT 24
Peak memory 206500 kb
Host smart-f3b23665-6e80-4d62-b5c9-cb27c1055293
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849893937 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.2849893937
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/default/10.edn_genbits.3832391670
Short name T11
Test name
Test status
Simulation time 194460132 ps
CPU time 1.37 seconds
Started Jul 23 07:09:01 PM PDT 24
Finished Jul 23 07:09:04 PM PDT 24
Peak memory 220724 kb
Host smart-cc80f072-5a75-406a-80ae-f0a8f1949d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832391670 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3832391670
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.2155945403
Short name T9
Test name
Test status
Simulation time 39175186 ps
CPU time 1.13 seconds
Started Jul 23 07:09:36 PM PDT 24
Finished Jul 23 07:09:41 PM PDT 24
Peak memory 219084 kb
Host smart-56196a0f-28f9-4a6e-ad83-94b5937c21f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155945403 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.2155945403
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.3331570918
Short name T286
Test name
Test status
Simulation time 86775064 ps
CPU time 3.13 seconds
Started Jul 23 07:10:55 PM PDT 24
Finished Jul 23 07:11:08 PM PDT 24
Peak memory 220232 kb
Host smart-9f9b53d1-00fb-4780-bad9-b1c3a9b01701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331570918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.3331570918
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.925662543
Short name T183
Test name
Test status
Simulation time 50948031 ps
CPU time 1.35 seconds
Started Jul 23 07:10:45 PM PDT 24
Finished Jul 23 07:10:57 PM PDT 24
Peak memory 221452 kb
Host smart-09f4ce53-88b3-458a-a3fe-55585ab2dfc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925662543 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.925662543
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert.311317113
Short name T179
Test name
Test status
Simulation time 194830460 ps
CPU time 1.18 seconds
Started Jul 23 07:08:43 PM PDT 24
Finished Jul 23 07:08:46 PM PDT 24
Peak memory 221148 kb
Host smart-04d23277-8b0c-4591-a54d-ac020da10495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311317113 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.311317113
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/109.edn_alert.1063420207
Short name T186
Test name
Test status
Simulation time 71991549 ps
CPU time 1.15 seconds
Started Jul 23 07:10:43 PM PDT 24
Finished Jul 23 07:10:55 PM PDT 24
Peak memory 219728 kb
Host smart-1bb5a570-abbf-4e05-8f4c-f2896375a624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063420207 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.1063420207
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/116.edn_alert.2895645314
Short name T81
Test name
Test status
Simulation time 75882807 ps
CPU time 1.28 seconds
Started Jul 23 07:10:42 PM PDT 24
Finished Jul 23 07:10:53 PM PDT 24
Peak memory 220156 kb
Host smart-b035c4fc-625e-48c1-97d6-a35180a041da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895645314 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.2895645314
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert.3366902163
Short name T426
Test name
Test status
Simulation time 40083042 ps
CPU time 1.16 seconds
Started Jul 23 07:09:15 PM PDT 24
Finished Jul 23 07:09:23 PM PDT 24
Peak memory 219700 kb
Host smart-878d41ea-dd8e-46cd-aa44-f7bd75092b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366902163 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.3366902163
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/170.edn_alert.3770882674
Short name T725
Test name
Test status
Simulation time 156690287 ps
CPU time 1.17 seconds
Started Jul 23 07:11:08 PM PDT 24
Finished Jul 23 07:11:18 PM PDT 24
Peak memory 218688 kb
Host smart-28ac1557-76cf-4258-994b-7cae26683feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770882674 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.3770882674
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert.1968648977
Short name T124
Test name
Test status
Simulation time 79187459 ps
CPU time 1.15 seconds
Started Jul 23 07:09:49 PM PDT 24
Finished Jul 23 07:10:02 PM PDT 24
Peak memory 219128 kb
Host smart-927b4bd6-5b22-4bc8-8535-28faa35aeb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968648977 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.1968648977
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/0.edn_intr.3212768237
Short name T36
Test name
Test status
Simulation time 23724664 ps
CPU time 1.06 seconds
Started Jul 23 07:08:37 PM PDT 24
Finished Jul 23 07:08:40 PM PDT 24
Peak memory 216200 kb
Host smart-727a131a-d29d-4880-b432-0aaa1cef3f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212768237 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.3212768237
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/58.edn_genbits.1551253162
Short name T21
Test name
Test status
Simulation time 188181629 ps
CPU time 1.13 seconds
Started Jul 23 07:10:21 PM PDT 24
Finished Jul 23 07:10:30 PM PDT 24
Peak memory 219812 kb
Host smart-517ae201-4212-4975-90c9-1c664f4e7077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551253162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1551253162
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.4234314202
Short name T374
Test name
Test status
Simulation time 32443498 ps
CPU time 1.35 seconds
Started Jul 23 07:10:59 PM PDT 24
Finished Jul 23 07:11:10 PM PDT 24
Peak memory 218928 kb
Host smart-6cb768bb-0cb4-4c44-9449-260fe09057b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234314202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.4234314202
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_disable.3911146475
Short name T557
Test name
Test status
Simulation time 22603349 ps
CPU time 0.87 seconds
Started Jul 23 07:09:39 PM PDT 24
Finished Jul 23 07:09:48 PM PDT 24
Peak memory 215764 kb
Host smart-14da26c8-8db0-401a-ab74-d46322d6775a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911146475 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.3911146475
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/25.edn_intr.1008489669
Short name T32
Test name
Test status
Simulation time 29726672 ps
CPU time 0.87 seconds
Started Jul 23 07:09:43 PM PDT 24
Finished Jul 23 07:09:56 PM PDT 24
Peak memory 216220 kb
Host smart-394918d3-30ab-43ba-8201-819365973637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008489669 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.1008489669
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.1805400987
Short name T537
Test name
Test status
Simulation time 47891040 ps
CPU time 1.13 seconds
Started Jul 23 07:08:49 PM PDT 24
Finished Jul 23 07:08:53 PM PDT 24
Peak memory 219160 kb
Host smart-fc2a4c50-568b-4b6f-b145-8002a4e47109
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805400987 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.1805400987
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_disable.2358840650
Short name T203
Test name
Test status
Simulation time 12415848 ps
CPU time 0.88 seconds
Started Jul 23 07:09:02 PM PDT 24
Finished Jul 23 07:09:05 PM PDT 24
Peak memory 216792 kb
Host smart-604d950d-a236-414c-b341-58443eab40a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358840650 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.2358840650
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3979631801
Short name T924
Test name
Test status
Simulation time 202973238 ps
CPU time 1.14 seconds
Started Jul 23 07:09:13 PM PDT 24
Finished Jul 23 07:09:20 PM PDT 24
Peak memory 217360 kb
Host smart-b1ecfcfe-5d9a-4e48-8831-5e3b98cd571e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979631801 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3979631801
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/122.edn_alert.1010978781
Short name T89
Test name
Test status
Simulation time 27569017 ps
CPU time 1.22 seconds
Started Jul 23 07:10:39 PM PDT 24
Finished Jul 23 07:10:51 PM PDT 24
Peak memory 219972 kb
Host smart-b3a46676-dfe5-4547-8bbc-1ce8d4e7ee8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010978781 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.1010978781
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/145.edn_alert.3750642862
Short name T173
Test name
Test status
Simulation time 23133336 ps
CPU time 1.09 seconds
Started Jul 23 07:10:47 PM PDT 24
Finished Jul 23 07:10:58 PM PDT 24
Peak memory 216040 kb
Host smart-a966b0d3-515e-4a65-94cb-42bd16a337de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750642862 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.3750642862
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/19.edn_disable.4012029854
Short name T882
Test name
Test status
Simulation time 39566954 ps
CPU time 0.81 seconds
Started Jul 23 07:09:38 PM PDT 24
Finished Jul 23 07:09:46 PM PDT 24
Peak memory 216732 kb
Host smart-92735be5-c4c9-4b76-86db-24f36009719f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012029854 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.4012029854
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.1487369814
Short name T205
Test name
Test status
Simulation time 39037932 ps
CPU time 1.37 seconds
Started Jul 23 07:09:38 PM PDT 24
Finished Jul 23 07:09:47 PM PDT 24
Peak memory 217216 kb
Host smart-baa990da-4e5a-4e9e-9cd5-6bb29f9061a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487369814 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.1487369814
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.3976549908
Short name T66
Test name
Test status
Simulation time 35085695 ps
CPU time 1.2 seconds
Started Jul 23 07:09:41 PM PDT 24
Finished Jul 23 07:09:54 PM PDT 24
Peak memory 217068 kb
Host smart-feedd330-93e1-41dc-9300-164e5c648c43
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976549908 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.3976549908
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.4030685037
Short name T189
Test name
Test status
Simulation time 22488586 ps
CPU time 0.91 seconds
Started Jul 23 07:09:39 PM PDT 24
Finished Jul 23 07:09:50 PM PDT 24
Peak memory 219024 kb
Host smart-0878284f-06e7-4440-8ce2-c7db6d5405b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030685037 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.4030685037
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.4250820921
Short name T131
Test name
Test status
Simulation time 218799659 ps
CPU time 1.11 seconds
Started Jul 23 07:09:43 PM PDT 24
Finished Jul 23 07:09:57 PM PDT 24
Peak memory 217240 kb
Host smart-8c261bbc-6ffc-4c9a-ba5d-46705f706c78
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250820921 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.4250820921
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_disable.1969803714
Short name T209
Test name
Test status
Simulation time 27071705 ps
CPU time 0.8 seconds
Started Jul 23 07:09:46 PM PDT 24
Finished Jul 23 07:09:59 PM PDT 24
Peak memory 216696 kb
Host smart-286a48f5-324c-4a67-a011-40ede8eef202
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969803714 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1969803714
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable.2417017537
Short name T83
Test name
Test status
Simulation time 26274311 ps
CPU time 0.84 seconds
Started Jul 23 07:09:42 PM PDT 24
Finished Jul 23 07:09:55 PM PDT 24
Peak memory 216680 kb
Host smart-70947760-a11d-4da4-a983-37980b51deaa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417017537 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2417017537
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/50.edn_err.1395287146
Short name T182
Test name
Test status
Simulation time 18726176 ps
CPU time 1.06 seconds
Started Jul 23 07:10:14 PM PDT 24
Finished Jul 23 07:10:22 PM PDT 24
Peak memory 218724 kb
Host smart-2b1d0249-f8e0-4712-843b-04151d370048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395287146 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.1395287146
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/11.edn_alert_test.546005409
Short name T349
Test name
Test status
Simulation time 28333807 ps
CPU time 0.94 seconds
Started Jul 23 07:09:11 PM PDT 24
Finished Jul 23 07:09:16 PM PDT 24
Peak memory 206984 kb
Host smart-44186e5a-600a-4850-8227-c9531fe33930
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546005409 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.546005409
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/207.edn_genbits.3008148266
Short name T44
Test name
Test status
Simulation time 35097003 ps
CPU time 1.38 seconds
Started Jul 23 07:11:07 PM PDT 24
Finished Jul 23 07:11:17 PM PDT 24
Peak memory 217852 kb
Host smart-0bab8740-8f62-4b2d-9011-30eb5b69b1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008148266 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3008148266
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.905960588
Short name T811
Test name
Test status
Simulation time 42369860 ps
CPU time 1.5 seconds
Started Jul 23 07:10:55 PM PDT 24
Finished Jul 23 07:11:08 PM PDT 24
Peak memory 215648 kb
Host smart-571569ad-c8f3-4722-b602-22f799bddc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905960588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.905960588
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.2434419300
Short name T94
Test name
Test status
Simulation time 20682051 ps
CPU time 1.07 seconds
Started Jul 23 07:09:37 PM PDT 24
Finished Jul 23 07:09:44 PM PDT 24
Peak memory 216192 kb
Host smart-8d3bd4f7-b7e1-4673-9f41-ca1b2f006c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434419300 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.2434419300
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3324883479
Short name T242
Test name
Test status
Simulation time 85937601 ps
CPU time 1.11 seconds
Started Jul 23 07:03:51 PM PDT 24
Finished Jul 23 07:03:53 PM PDT 24
Peak memory 206536 kb
Host smart-27ae40de-35cc-4150-863a-a5ef03ab8a26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324883479 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.3324883479
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3685454977
Short name T282
Test name
Test status
Simulation time 77928238 ps
CPU time 2.27 seconds
Started Jul 23 07:03:58 PM PDT 24
Finished Jul 23 07:04:01 PM PDT 24
Peak memory 214744 kb
Host smart-9e67c340-2be8-45aa-846a-45eb240e8cf0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685454977 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3685454977
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/default/102.edn_alert.1650638591
Short name T181
Test name
Test status
Simulation time 52276253 ps
CPU time 1.05 seconds
Started Jul 23 07:10:39 PM PDT 24
Finished Jul 23 07:10:51 PM PDT 24
Peak memory 218820 kb
Host smart-9d4bd432-cf9b-4da5-838d-edbb5f8ea981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650638591 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.1650638591
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/11.edn_stress_all.4180043724
Short name T670
Test name
Test status
Simulation time 434120582 ps
CPU time 2.92 seconds
Started Jul 23 07:09:01 PM PDT 24
Finished Jul 23 07:09:06 PM PDT 24
Peak memory 220384 kb
Host smart-709e03e5-6b11-48d4-9256-9e6bb5c2718a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180043724 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.4180043724
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all.4207420522
Short name T971
Test name
Test status
Simulation time 222006620 ps
CPU time 2.57 seconds
Started Jul 23 07:09:11 PM PDT 24
Finished Jul 23 07:09:16 PM PDT 24
Peak memory 218776 kb
Host smart-d81157a0-e91d-433d-80c6-4be8ccba7051
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207420522 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.4207420522
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/123.edn_genbits.3009916710
Short name T805
Test name
Test status
Simulation time 48603294 ps
CPU time 1.5 seconds
Started Jul 23 07:10:40 PM PDT 24
Finished Jul 23 07:10:52 PM PDT 24
Peak memory 219088 kb
Host smart-7afe6286-d6f2-400f-80a7-46eb99008c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009916710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.3009916710
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.2953986661
Short name T309
Test name
Test status
Simulation time 102557216 ps
CPU time 1.35 seconds
Started Jul 23 07:10:44 PM PDT 24
Finished Jul 23 07:10:56 PM PDT 24
Peak memory 217524 kb
Host smart-069e44c0-6a99-420b-a1df-a672a3432898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953986661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.2953986661
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.3685947710
Short name T769
Test name
Test status
Simulation time 30053768 ps
CPU time 1.42 seconds
Started Jul 23 07:10:58 PM PDT 24
Finished Jul 23 07:11:10 PM PDT 24
Peak memory 219092 kb
Host smart-77f8db6f-a6fb-42cc-a0ef-267cacf58d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685947710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.3685947710
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.2059503383
Short name T963
Test name
Test status
Simulation time 29929047 ps
CPU time 1.42 seconds
Started Jul 23 07:11:05 PM PDT 24
Finished Jul 23 07:11:16 PM PDT 24
Peak memory 220492 kb
Host smart-15e1ed13-c9d2-4886-b58d-a57c4a6b4546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059503383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2059503383
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/230.edn_genbits.3969880523
Short name T983
Test name
Test status
Simulation time 37659443 ps
CPU time 1.17 seconds
Started Jul 23 07:11:24 PM PDT 24
Finished Jul 23 07:11:36 PM PDT 24
Peak memory 218816 kb
Host smart-52ee64ea-6d9b-4951-952b-56ed4c2e0a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969880523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.3969880523
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.898385860
Short name T295
Test name
Test status
Simulation time 92112035 ps
CPU time 3.25 seconds
Started Jul 23 07:11:14 PM PDT 24
Finished Jul 23 07:11:27 PM PDT 24
Peak memory 219952 kb
Host smart-c2dce635-6280-4f88-9b38-949f6219f92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898385860 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.898385860
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.502247669
Short name T106
Test name
Test status
Simulation time 52538870 ps
CPU time 1.2 seconds
Started Jul 23 07:11:22 PM PDT 24
Finished Jul 23 07:11:34 PM PDT 24
Peak memory 219040 kb
Host smart-a3e526d2-f7da-4660-8a33-c24bb3fc934d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502247669 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.502247669
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.513996117
Short name T99
Test name
Test status
Simulation time 34431386 ps
CPU time 0.89 seconds
Started Jul 23 07:09:12 PM PDT 24
Finished Jul 23 07:09:17 PM PDT 24
Peak memory 215988 kb
Host smart-69b6e318-2112-4b24-a703-a8393e25a834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513996117 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.513996117
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/108.edn_genbits.34127551
Short name T472
Test name
Test status
Simulation time 77727754 ps
CPU time 1.77 seconds
Started Jul 23 07:10:37 PM PDT 24
Finished Jul 23 07:10:49 PM PDT 24
Peak memory 220652 kb
Host smart-b7220a9d-0206-492a-a194-20c832486d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34127551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.34127551
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.2630793165
Short name T114
Test name
Test status
Simulation time 99782153 ps
CPU time 1.19 seconds
Started Jul 23 07:10:49 PM PDT 24
Finished Jul 23 07:11:01 PM PDT 24
Peak memory 218988 kb
Host smart-b0db8a48-4309-40c8-a825-5f6a6629b8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630793165 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.2630793165
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/150.edn_alert.4224221601
Short name T217
Test name
Test status
Simulation time 50574074 ps
CPU time 1.08 seconds
Started Jul 23 07:10:53 PM PDT 24
Finished Jul 23 07:11:04 PM PDT 24
Peak memory 219144 kb
Host smart-4fe3ed32-a796-4feb-b34f-00dfc022e064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224221601 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.4224221601
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/151.edn_alert.1894387453
Short name T111
Test name
Test status
Simulation time 29157204 ps
CPU time 1.29 seconds
Started Jul 23 07:10:52 PM PDT 24
Finished Jul 23 07:11:03 PM PDT 24
Peak memory 219080 kb
Host smart-eb673016-cbcb-42d3-ab92-519f1bb48c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894387453 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.1894387453
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2792931344
Short name T254
Test name
Test status
Simulation time 236619483 ps
CPU time 1.47 seconds
Started Jul 23 07:03:54 PM PDT 24
Finished Jul 23 07:03:57 PM PDT 24
Peak memory 206484 kb
Host smart-e162bd97-a34b-4218-8860-aa98bbb85c87
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792931344 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.2792931344
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1994665042
Short name T1023
Test name
Test status
Simulation time 240948464 ps
CPU time 2.89 seconds
Started Jul 23 07:03:46 PM PDT 24
Finished Jul 23 07:03:50 PM PDT 24
Peak memory 206540 kb
Host smart-c07a40be-c1fe-4321-ad63-30621e5a4626
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994665042 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.1994665042
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1480850284
Short name T1070
Test name
Test status
Simulation time 17598998 ps
CPU time 0.91 seconds
Started Jul 23 07:03:44 PM PDT 24
Finished Jul 23 07:03:45 PM PDT 24
Peak memory 206496 kb
Host smart-b20bc4cc-4ca3-4145-9ae8-9385ea681163
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480850284 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.1480850284
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1797643296
Short name T1082
Test name
Test status
Simulation time 35354691 ps
CPU time 1.74 seconds
Started Jul 23 07:03:50 PM PDT 24
Finished Jul 23 07:03:54 PM PDT 24
Peak memory 214788 kb
Host smart-429022fb-4f48-4bd5-840c-96e1ce4232c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797643296 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.1797643296
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.3789446443
Short name T1117
Test name
Test status
Simulation time 37301070 ps
CPU time 0.85 seconds
Started Jul 23 07:03:44 PM PDT 24
Finished Jul 23 07:03:46 PM PDT 24
Peak memory 206544 kb
Host smart-d0392da9-2d6f-4ea0-8f20-5b70da88493b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789446443 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.3789446443
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.3986183213
Short name T1034
Test name
Test status
Simulation time 32088762 ps
CPU time 0.76 seconds
Started Jul 23 07:03:44 PM PDT 24
Finished Jul 23 07:03:46 PM PDT 24
Peak memory 206296 kb
Host smart-0d60bf8f-5432-480e-a44e-1711a1bdb6c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986183213 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.3986183213
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1369532887
Short name T1125
Test name
Test status
Simulation time 16648186 ps
CPU time 1.06 seconds
Started Jul 23 07:03:49 PM PDT 24
Finished Jul 23 07:03:51 PM PDT 24
Peak memory 206564 kb
Host smart-2b1b84d5-4c5c-4798-9eb6-e402307acdcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369532887 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.1369532887
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.2303958437
Short name T1129
Test name
Test status
Simulation time 110092502 ps
CPU time 1.63 seconds
Started Jul 23 07:03:45 PM PDT 24
Finished Jul 23 07:03:48 PM PDT 24
Peak memory 214900 kb
Host smart-a161e159-f567-4e40-b0cb-822819d67bd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303958437 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.2303958437
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2122576358
Short name T279
Test name
Test status
Simulation time 1505980964 ps
CPU time 2.51 seconds
Started Jul 23 07:03:45 PM PDT 24
Finished Jul 23 07:03:49 PM PDT 24
Peak memory 214828 kb
Host smart-396758a2-7fc2-49f3-8fa5-d61842b0dc23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122576358 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.2122576358
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.525970026
Short name T1030
Test name
Test status
Simulation time 22410780 ps
CPU time 1.09 seconds
Started Jul 23 07:03:49 PM PDT 24
Finished Jul 23 07:03:51 PM PDT 24
Peak memory 206508 kb
Host smart-08bba18b-85c5-4c78-a5f3-1c06c0e43a07
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525970026 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.525970026
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3868808682
Short name T1098
Test name
Test status
Simulation time 99007997 ps
CPU time 2.83 seconds
Started Jul 23 07:03:53 PM PDT 24
Finished Jul 23 07:03:57 PM PDT 24
Peak memory 206524 kb
Host smart-d977f244-a8f3-40f4-be3c-5f551cbc9cdf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868808682 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.3868808682
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1494439538
Short name T248
Test name
Test status
Simulation time 14801541 ps
CPU time 0.87 seconds
Started Jul 23 07:03:49 PM PDT 24
Finished Jul 23 07:03:51 PM PDT 24
Peak memory 206476 kb
Host smart-dca07d9b-0f9d-4666-98b5-e0bd16829376
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494439538 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1494439538
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3322499285
Short name T1077
Test name
Test status
Simulation time 26921276 ps
CPU time 1.18 seconds
Started Jul 23 07:03:49 PM PDT 24
Finished Jul 23 07:03:52 PM PDT 24
Peak memory 214808 kb
Host smart-cbbb9c9a-3ae1-4b38-8ac2-6427236248c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322499285 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3322499285
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.3003471511
Short name T1038
Test name
Test status
Simulation time 42108057 ps
CPU time 0.83 seconds
Started Jul 23 07:03:51 PM PDT 24
Finished Jul 23 07:03:53 PM PDT 24
Peak memory 206440 kb
Host smart-e44d425a-972d-4839-bb97-af0f943001d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003471511 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3003471511
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3272922492
Short name T1002
Test name
Test status
Simulation time 40945972 ps
CPU time 0.85 seconds
Started Jul 23 07:03:52 PM PDT 24
Finished Jul 23 07:03:54 PM PDT 24
Peak memory 206300 kb
Host smart-46718710-cf7b-4f37-9149-52a3113c62de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272922492 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3272922492
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.3776208958
Short name T997
Test name
Test status
Simulation time 69901618 ps
CPU time 1.57 seconds
Started Jul 23 07:03:50 PM PDT 24
Finished Jul 23 07:03:53 PM PDT 24
Peak memory 222952 kb
Host smart-ab80ebbf-5f72-418f-9665-aa61de4f86ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776208958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3776208958
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.148078657
Short name T1026
Test name
Test status
Simulation time 169667737 ps
CPU time 1.53 seconds
Started Jul 23 07:03:54 PM PDT 24
Finished Jul 23 07:03:57 PM PDT 24
Peak memory 206804 kb
Host smart-3aeb2165-398c-4bfd-958e-f651393010e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148078657 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.148078657
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1057214384
Short name T1046
Test name
Test status
Simulation time 257764356 ps
CPU time 0.99 seconds
Started Jul 23 07:04:35 PM PDT 24
Finished Jul 23 07:04:39 PM PDT 24
Peak memory 214676 kb
Host smart-aacbb3f1-8182-4c69-8f32-1356688868f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057214384 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.1057214384
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.947493703
Short name T255
Test name
Test status
Simulation time 115531304 ps
CPU time 0.81 seconds
Started Jul 23 07:04:35 PM PDT 24
Finished Jul 23 07:04:38 PM PDT 24
Peak memory 206296 kb
Host smart-bab81e76-1532-4015-955f-ccfc81fdcc47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947493703 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.947493703
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2699187352
Short name T1051
Test name
Test status
Simulation time 19922849 ps
CPU time 0.94 seconds
Started Jul 23 07:04:35 PM PDT 24
Finished Jul 23 07:04:39 PM PDT 24
Peak memory 206356 kb
Host smart-dadb071e-62a6-4b72-88e6-b51707d6383d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699187352 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2699187352
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3035205585
Short name T1123
Test name
Test status
Simulation time 150705099 ps
CPU time 1.11 seconds
Started Jul 23 07:04:32 PM PDT 24
Finished Jul 23 07:04:34 PM PDT 24
Peak memory 206484 kb
Host smart-7e43dad2-58e7-4d2a-b97d-08925f627880
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035205585 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.3035205585
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.364725197
Short name T1103
Test name
Test status
Simulation time 433680746 ps
CPU time 3.22 seconds
Started Jul 23 07:04:25 PM PDT 24
Finished Jul 23 07:04:30 PM PDT 24
Peak memory 214864 kb
Host smart-1f815f1d-06a6-4d1b-bfe3-ce13a1631879
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364725197 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.364725197
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1628154519
Short name T1072
Test name
Test status
Simulation time 98482899 ps
CPU time 1.63 seconds
Started Jul 23 07:04:34 PM PDT 24
Finished Jul 23 07:04:37 PM PDT 24
Peak memory 206504 kb
Host smart-8d08ce35-da3f-4595-a3d6-d492e0603ae0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628154519 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1628154519
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3693006627
Short name T1097
Test name
Test status
Simulation time 19674620 ps
CPU time 1.05 seconds
Started Jul 23 07:04:35 PM PDT 24
Finished Jul 23 07:04:38 PM PDT 24
Peak memory 206604 kb
Host smart-ec207f3b-1652-4304-8c28-a592dcbc2f82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693006627 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3693006627
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.1993009131
Short name T1024
Test name
Test status
Simulation time 47983563 ps
CPU time 0.89 seconds
Started Jul 23 07:04:34 PM PDT 24
Finished Jul 23 07:04:37 PM PDT 24
Peak memory 206684 kb
Host smart-b403f3d7-00e9-45b6-9eac-8a3de1b3e875
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993009131 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1993009131
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.1623327838
Short name T1126
Test name
Test status
Simulation time 39728620 ps
CPU time 0.79 seconds
Started Jul 23 07:04:34 PM PDT 24
Finished Jul 23 07:04:37 PM PDT 24
Peak memory 206272 kb
Host smart-26be6a99-9eb3-4ef1-985f-5955901577fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623327838 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1623327838
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.202036596
Short name T1099
Test name
Test status
Simulation time 103311217 ps
CPU time 1.23 seconds
Started Jul 23 07:04:34 PM PDT 24
Finished Jul 23 07:04:38 PM PDT 24
Peak memory 206544 kb
Host smart-8421f472-252f-4954-a6fb-5f680b10b00f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202036596 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_ou
tstanding.202036596
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.1381096458
Short name T1027
Test name
Test status
Simulation time 85379194 ps
CPU time 2.81 seconds
Started Jul 23 07:04:33 PM PDT 24
Finished Jul 23 07:04:37 PM PDT 24
Peak memory 214888 kb
Host smart-eebce271-68e8-42bd-a93b-db80b746d48a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381096458 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.1381096458
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.444872653
Short name T281
Test name
Test status
Simulation time 192096485 ps
CPU time 2.44 seconds
Started Jul 23 07:04:32 PM PDT 24
Finished Jul 23 07:04:35 PM PDT 24
Peak memory 214736 kb
Host smart-7c82f05b-c631-40c1-8a33-b5359824d6fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444872653 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.444872653
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.491850715
Short name T1107
Test name
Test status
Simulation time 87039515 ps
CPU time 1.54 seconds
Started Jul 23 07:04:32 PM PDT 24
Finished Jul 23 07:04:35 PM PDT 24
Peak memory 214796 kb
Host smart-1ea2ffef-15b2-483e-8659-62a4f9cb6070
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491850715 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.491850715
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.425914174
Short name T251
Test name
Test status
Simulation time 22883906 ps
CPU time 0.79 seconds
Started Jul 23 07:04:32 PM PDT 24
Finished Jul 23 07:04:33 PM PDT 24
Peak memory 206280 kb
Host smart-ed90c813-7bf0-4906-9cc3-81645c488a79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425914174 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.425914174
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.447480996
Short name T1114
Test name
Test status
Simulation time 22202640 ps
CPU time 0.78 seconds
Started Jul 23 07:04:33 PM PDT 24
Finished Jul 23 07:04:36 PM PDT 24
Peak memory 206276 kb
Host smart-bec22261-7326-44a5-a646-c0bf735b3a36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447480996 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.447480996
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1461381271
Short name T260
Test name
Test status
Simulation time 33959386 ps
CPU time 1.19 seconds
Started Jul 23 07:04:35 PM PDT 24
Finished Jul 23 07:04:38 PM PDT 24
Peak memory 206468 kb
Host smart-d247557e-b902-45d4-899f-5ec2ee0bacd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461381271 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.1461381271
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.2066743170
Short name T1096
Test name
Test status
Simulation time 59167918 ps
CPU time 2.11 seconds
Started Jul 23 07:04:31 PM PDT 24
Finished Jul 23 07:04:34 PM PDT 24
Peak memory 214820 kb
Host smart-1e5a9bf9-a61e-4e2d-989e-b56378b76990
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066743170 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.2066743170
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1559252409
Short name T1019
Test name
Test status
Simulation time 319273131 ps
CPU time 2.38 seconds
Started Jul 23 07:04:35 PM PDT 24
Finished Jul 23 07:04:39 PM PDT 24
Peak memory 206536 kb
Host smart-06afd253-a956-4e22-b57f-7fc7e4e59512
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559252409 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.1559252409
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3989834833
Short name T1081
Test name
Test status
Simulation time 31824027 ps
CPU time 1.1 seconds
Started Jul 23 07:04:32 PM PDT 24
Finished Jul 23 07:04:34 PM PDT 24
Peak memory 214828 kb
Host smart-69053e15-1848-482b-a5d1-a8814fd720a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989834833 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.3989834833
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.2199776515
Short name T253
Test name
Test status
Simulation time 16848131 ps
CPU time 0.99 seconds
Started Jul 23 07:04:33 PM PDT 24
Finished Jul 23 07:04:36 PM PDT 24
Peak memory 206456 kb
Host smart-152ff5c6-df8e-498d-bfc3-305ca229a58a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199776515 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.2199776515
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.3252993697
Short name T1089
Test name
Test status
Simulation time 57740677 ps
CPU time 0.87 seconds
Started Jul 23 07:04:30 PM PDT 24
Finished Jul 23 07:04:32 PM PDT 24
Peak memory 206508 kb
Host smart-934f2d8f-c958-4597-8ffc-e893b54483af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252993697 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.3252993697
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2925394028
Short name T1063
Test name
Test status
Simulation time 19467750 ps
CPU time 0.99 seconds
Started Jul 23 07:04:32 PM PDT 24
Finished Jul 23 07:04:35 PM PDT 24
Peak memory 206504 kb
Host smart-50806d29-bf62-46b4-83ed-2372bdebc2b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925394028 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2925394028
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.1375219452
Short name T1040
Test name
Test status
Simulation time 192133522 ps
CPU time 3.74 seconds
Started Jul 23 07:04:32 PM PDT 24
Finished Jul 23 07:04:38 PM PDT 24
Peak memory 214792 kb
Host smart-199ebfe2-2133-4b23-8c66-c0bafce6c8b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375219452 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1375219452
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2293403261
Short name T1128
Test name
Test status
Simulation time 32625519 ps
CPU time 1.42 seconds
Started Jul 23 07:04:34 PM PDT 24
Finished Jul 23 07:04:38 PM PDT 24
Peak memory 218092 kb
Host smart-77e90754-84db-4ba8-9575-56374d055cff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293403261 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2293403261
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.1265883433
Short name T1018
Test name
Test status
Simulation time 12904881 ps
CPU time 0.84 seconds
Started Jul 23 07:04:34 PM PDT 24
Finished Jul 23 07:04:37 PM PDT 24
Peak memory 206468 kb
Host smart-5c6b1a14-0824-4ac9-be92-e83dcb5f1c2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265883433 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1265883433
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.1020825390
Short name T1118
Test name
Test status
Simulation time 13273877 ps
CPU time 0.84 seconds
Started Jul 23 07:04:34 PM PDT 24
Finished Jul 23 07:04:37 PM PDT 24
Peak memory 206488 kb
Host smart-9fafb187-dce2-47d2-b07d-9fe62de13444
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020825390 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.1020825390
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1312198958
Short name T246
Test name
Test status
Simulation time 66071831 ps
CPU time 1.12 seconds
Started Jul 23 07:04:33 PM PDT 24
Finished Jul 23 07:04:36 PM PDT 24
Peak memory 206592 kb
Host smart-e9b123bf-5d6f-4804-ad81-157c5e2d3dc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312198958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.1312198958
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.3074978292
Short name T1073
Test name
Test status
Simulation time 333367325 ps
CPU time 3.1 seconds
Started Jul 23 07:04:35 PM PDT 24
Finished Jul 23 07:04:41 PM PDT 24
Peak memory 214852 kb
Host smart-549aa8da-c6b5-4e19-8579-ffffc31855dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074978292 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3074978292
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.674037521
Short name T274
Test name
Test status
Simulation time 55987437 ps
CPU time 1.67 seconds
Started Jul 23 07:04:32 PM PDT 24
Finished Jul 23 07:04:35 PM PDT 24
Peak memory 214760 kb
Host smart-ec08be9a-21f3-49d4-8f25-da90134c0283
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674037521 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.674037521
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2934579231
Short name T1016
Test name
Test status
Simulation time 53694969 ps
CPU time 1.25 seconds
Started Jul 23 07:04:35 PM PDT 24
Finished Jul 23 07:04:39 PM PDT 24
Peak memory 214828 kb
Host smart-6d1e92d3-1b1b-4478-ba27-b2492045c966
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934579231 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2934579231
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.3077411630
Short name T1032
Test name
Test status
Simulation time 27469192 ps
CPU time 0.9 seconds
Started Jul 23 07:04:33 PM PDT 24
Finished Jul 23 07:04:36 PM PDT 24
Peak memory 206380 kb
Host smart-3768b642-2424-46e8-99b0-cffc6c234f39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077411630 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.3077411630
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3101865420
Short name T1005
Test name
Test status
Simulation time 18316466 ps
CPU time 0.93 seconds
Started Jul 23 07:04:33 PM PDT 24
Finished Jul 23 07:04:36 PM PDT 24
Peak memory 206388 kb
Host smart-2911f335-d3b7-4b87-bbfd-445bae888b9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101865420 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3101865420
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2800771928
Short name T1055
Test name
Test status
Simulation time 44075414 ps
CPU time 1.06 seconds
Started Jul 23 07:04:32 PM PDT 24
Finished Jul 23 07:04:35 PM PDT 24
Peak memory 206532 kb
Host smart-91e2bf58-9c78-42ae-be5b-25e9c9c35215
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800771928 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.2800771928
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.4231164239
Short name T1069
Test name
Test status
Simulation time 83119973 ps
CPU time 2.24 seconds
Started Jul 23 07:04:33 PM PDT 24
Finished Jul 23 07:04:37 PM PDT 24
Peak memory 214796 kb
Host smart-00b96d42-30d0-44fe-a315-8af1ea404c54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231164239 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.4231164239
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.509650598
Short name T275
Test name
Test status
Simulation time 361867439 ps
CPU time 2.33 seconds
Started Jul 23 07:04:32 PM PDT 24
Finished Jul 23 07:04:37 PM PDT 24
Peak memory 206612 kb
Host smart-3f521def-2260-467e-b602-e904cd19b747
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509650598 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.509650598
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3386146352
Short name T1091
Test name
Test status
Simulation time 47942903 ps
CPU time 0.97 seconds
Started Jul 23 07:04:36 PM PDT 24
Finished Jul 23 07:04:40 PM PDT 24
Peak memory 206608 kb
Host smart-b971fc32-85eb-4f2e-b2e4-78abdc1330a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386146352 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.3386146352
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.3333337822
Short name T1022
Test name
Test status
Simulation time 17420754 ps
CPU time 0.95 seconds
Started Jul 23 07:04:39 PM PDT 24
Finished Jul 23 07:04:42 PM PDT 24
Peak memory 206440 kb
Host smart-ccb0930b-e323-4dd9-894b-e954ff1d8060
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333337822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.3333337822
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.2710539333
Short name T1104
Test name
Test status
Simulation time 35341098 ps
CPU time 0.82 seconds
Started Jul 23 07:04:39 PM PDT 24
Finished Jul 23 07:04:42 PM PDT 24
Peak memory 206460 kb
Host smart-c4c17f4d-06e6-493a-a681-ea710eec0d3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710539333 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.2710539333
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.4130965825
Short name T1078
Test name
Test status
Simulation time 32616657 ps
CPU time 1.03 seconds
Started Jul 23 07:04:38 PM PDT 24
Finished Jul 23 07:04:41 PM PDT 24
Peak memory 206436 kb
Host smart-aaacfec3-6189-40a7-aa60-ee600cc049a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130965825 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.4130965825
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.1623219496
Short name T1095
Test name
Test status
Simulation time 65862193 ps
CPU time 1.8 seconds
Started Jul 23 07:04:33 PM PDT 24
Finished Jul 23 07:04:37 PM PDT 24
Peak memory 218512 kb
Host smart-a3386763-d21a-43c4-8da5-1d6d25147463
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623219496 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.1623219496
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.931521807
Short name T1057
Test name
Test status
Simulation time 60778156 ps
CPU time 1.56 seconds
Started Jul 23 07:04:35 PM PDT 24
Finished Jul 23 07:04:39 PM PDT 24
Peak memory 206508 kb
Host smart-325e1b64-1ab9-45a6-8b77-9c833202310f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931521807 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.931521807
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.468567465
Short name T1056
Test name
Test status
Simulation time 275060951 ps
CPU time 0.99 seconds
Started Jul 23 07:04:37 PM PDT 24
Finished Jul 23 07:04:40 PM PDT 24
Peak memory 214892 kb
Host smart-d316691f-da43-4ee3-b9c1-ae9beea7700c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468567465 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.468567465
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.2166794730
Short name T247
Test name
Test status
Simulation time 19007379 ps
CPU time 0.94 seconds
Started Jul 23 07:04:38 PM PDT 24
Finished Jul 23 07:04:41 PM PDT 24
Peak memory 206484 kb
Host smart-022b0815-fafd-4967-af60-62379e8dedde
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166794730 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2166794730
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.3794486211
Short name T999
Test name
Test status
Simulation time 46974885 ps
CPU time 0.8 seconds
Started Jul 23 07:04:39 PM PDT 24
Finished Jul 23 07:04:42 PM PDT 24
Peak memory 206304 kb
Host smart-b08e0ce6-7b94-485f-b634-1ade1c7759c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794486211 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.3794486211
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2109318476
Short name T1048
Test name
Test status
Simulation time 17432951 ps
CPU time 1.02 seconds
Started Jul 23 07:04:39 PM PDT 24
Finished Jul 23 07:04:42 PM PDT 24
Peak memory 206624 kb
Host smart-91ef2c4d-e58a-45fe-a5c4-abbb964ad90f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109318476 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.2109318476
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.4113212658
Short name T1062
Test name
Test status
Simulation time 48221300 ps
CPU time 2.08 seconds
Started Jul 23 07:04:37 PM PDT 24
Finished Jul 23 07:04:42 PM PDT 24
Peak memory 214800 kb
Host smart-45b5d27e-34ad-4d50-a42a-8d8fafef05a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113212658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.4113212658
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2116631374
Short name T1047
Test name
Test status
Simulation time 77436456 ps
CPU time 1.87 seconds
Started Jul 23 07:04:37 PM PDT 24
Finished Jul 23 07:04:42 PM PDT 24
Peak memory 214800 kb
Host smart-ff8f64df-d172-444d-b7e0-4ce60aa617bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116631374 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.2116631374
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.114237903
Short name T1043
Test name
Test status
Simulation time 226336000 ps
CPU time 1.57 seconds
Started Jul 23 07:04:40 PM PDT 24
Finished Jul 23 07:04:43 PM PDT 24
Peak memory 214788 kb
Host smart-1dac1808-7b41-4e9e-9a59-f0117769536f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114237903 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.114237903
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1365209550
Short name T1090
Test name
Test status
Simulation time 26336167 ps
CPU time 0.95 seconds
Started Jul 23 07:04:37 PM PDT 24
Finished Jul 23 07:04:40 PM PDT 24
Peak memory 206472 kb
Host smart-1f09c261-f38d-4adc-aeaf-875a84d6df46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365209550 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1365209550
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.3787848002
Short name T1014
Test name
Test status
Simulation time 21995526 ps
CPU time 0.83 seconds
Started Jul 23 07:04:38 PM PDT 24
Finished Jul 23 07:04:41 PM PDT 24
Peak memory 206448 kb
Host smart-81f39ed0-e7cb-48d4-86ff-03ecf14b411f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787848002 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.3787848002
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.4273566497
Short name T262
Test name
Test status
Simulation time 132394099 ps
CPU time 1.37 seconds
Started Jul 23 07:04:37 PM PDT 24
Finished Jul 23 07:04:41 PM PDT 24
Peak memory 206548 kb
Host smart-e49cad72-7832-47ca-9a5c-22c2ddd752b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273566497 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.4273566497
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.856222469
Short name T1116
Test name
Test status
Simulation time 79406338 ps
CPU time 2.71 seconds
Started Jul 23 07:04:37 PM PDT 24
Finished Jul 23 07:04:42 PM PDT 24
Peak memory 214960 kb
Host smart-7f7af4c9-c409-49be-a283-0111414eedf7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856222469 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.856222469
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1790963506
Short name T1093
Test name
Test status
Simulation time 691967264 ps
CPU time 1.7 seconds
Started Jul 23 07:04:39 PM PDT 24
Finished Jul 23 07:04:42 PM PDT 24
Peak memory 206816 kb
Host smart-8fb7b846-ecf8-41e8-a3dc-245b29904d1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790963506 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1790963506
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2458956635
Short name T1111
Test name
Test status
Simulation time 203449492 ps
CPU time 1.22 seconds
Started Jul 23 07:04:45 PM PDT 24
Finished Jul 23 07:04:48 PM PDT 24
Peak memory 214780 kb
Host smart-e23157c7-240a-4d32-9506-2a1032e78705
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458956635 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.2458956635
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2091369953
Short name T244
Test name
Test status
Simulation time 32326831 ps
CPU time 0.81 seconds
Started Jul 23 07:04:45 PM PDT 24
Finished Jul 23 07:04:47 PM PDT 24
Peak memory 206240 kb
Host smart-2c4484a5-014f-4c66-989f-3403a57a155d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091369953 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2091369953
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.143125778
Short name T998
Test name
Test status
Simulation time 17901559 ps
CPU time 0.9 seconds
Started Jul 23 07:04:44 PM PDT 24
Finished Jul 23 07:04:45 PM PDT 24
Peak memory 206556 kb
Host smart-0979e515-6eed-47a2-bfad-f882d64bb456
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143125778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.143125778
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1071335169
Short name T263
Test name
Test status
Simulation time 15303805 ps
CPU time 0.94 seconds
Started Jul 23 07:04:45 PM PDT 24
Finished Jul 23 07:04:47 PM PDT 24
Peak memory 206468 kb
Host smart-0b5787e2-f13e-4b06-9cdb-9feb88c08aca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071335169 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.1071335169
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.3966161950
Short name T1122
Test name
Test status
Simulation time 95439132 ps
CPU time 1.9 seconds
Started Jul 23 07:04:45 PM PDT 24
Finished Jul 23 07:04:48 PM PDT 24
Peak memory 223032 kb
Host smart-6af7c6db-95b1-44d2-83dd-07f775294a6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966161950 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.3966161950
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3643210538
Short name T1120
Test name
Test status
Simulation time 140412579 ps
CPU time 2.44 seconds
Started Jul 23 07:04:42 PM PDT 24
Finished Jul 23 07:04:45 PM PDT 24
Peak memory 206572 kb
Host smart-fe6e9253-e45d-48e1-8d38-39e246ff4cdd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643210538 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3643210538
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2635280801
Short name T250
Test name
Test status
Simulation time 14319388 ps
CPU time 0.98 seconds
Started Jul 23 07:03:54 PM PDT 24
Finished Jul 23 07:03:57 PM PDT 24
Peak memory 206468 kb
Host smart-c6c459c3-f75a-4fc4-b386-3a99da531de0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635280801 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.2635280801
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3174561283
Short name T1006
Test name
Test status
Simulation time 539432829 ps
CPU time 3.64 seconds
Started Jul 23 07:03:50 PM PDT 24
Finished Jul 23 07:03:55 PM PDT 24
Peak memory 206540 kb
Host smart-42eeec57-c975-462f-ad6c-9e4977d23260
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174561283 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.3174561283
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2215457211
Short name T259
Test name
Test status
Simulation time 32908451 ps
CPU time 0.92 seconds
Started Jul 23 07:03:53 PM PDT 24
Finished Jul 23 07:03:54 PM PDT 24
Peak memory 206488 kb
Host smart-c2c746ae-4163-4434-905a-71e1818c9271
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215457211 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.2215457211
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.4151197987
Short name T1100
Test name
Test status
Simulation time 317843963 ps
CPU time 1.08 seconds
Started Jul 23 07:03:55 PM PDT 24
Finished Jul 23 07:03:57 PM PDT 24
Peak memory 214792 kb
Host smart-33f1327d-79de-4d54-8e3a-8b16d5f935b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151197987 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.4151197987
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.3081692296
Short name T1037
Test name
Test status
Simulation time 51184627 ps
CPU time 0.88 seconds
Started Jul 23 07:03:51 PM PDT 24
Finished Jul 23 07:03:53 PM PDT 24
Peak memory 206436 kb
Host smart-0e68d9ea-b6c8-4a53-93f4-3ed6079c9f81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081692296 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3081692296
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1848557378
Short name T1008
Test name
Test status
Simulation time 18702442 ps
CPU time 0.97 seconds
Started Jul 23 07:03:49 PM PDT 24
Finished Jul 23 07:03:52 PM PDT 24
Peak memory 206680 kb
Host smart-1cdb30da-984a-45d5-851e-9cdaa4548fa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848557378 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1848557378
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.48451745
Short name T264
Test name
Test status
Simulation time 92054084 ps
CPU time 1.12 seconds
Started Jul 23 07:03:57 PM PDT 24
Finished Jul 23 07:03:59 PM PDT 24
Peak memory 206552 kb
Host smart-b3504d0f-e10a-44b6-b597-6b37c9d3aaaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48451745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_outs
tanding.48451745
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.3414899586
Short name T1124
Test name
Test status
Simulation time 473789172 ps
CPU time 4.16 seconds
Started Jul 23 07:03:52 PM PDT 24
Finished Jul 23 07:03:57 PM PDT 24
Peak memory 214884 kb
Host smart-877f6c10-a73b-47b9-8287-a532986e8ce1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414899586 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.3414899586
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1352555422
Short name T1041
Test name
Test status
Simulation time 85652855 ps
CPU time 1.51 seconds
Started Jul 23 07:03:49 PM PDT 24
Finished Jul 23 07:03:52 PM PDT 24
Peak memory 206504 kb
Host smart-ae514a72-5efd-474c-ab97-ff349547e2d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352555422 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1352555422
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.2708061087
Short name T1031
Test name
Test status
Simulation time 19048643 ps
CPU time 0.83 seconds
Started Jul 23 07:04:47 PM PDT 24
Finished Jul 23 07:04:49 PM PDT 24
Peak memory 206464 kb
Host smart-63c9d77f-c7ad-4bd4-a688-bd47e8ec9def
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708061087 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.2708061087
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.2289568744
Short name T1115
Test name
Test status
Simulation time 12557238 ps
CPU time 0.83 seconds
Started Jul 23 07:04:45 PM PDT 24
Finished Jul 23 07:04:47 PM PDT 24
Peak memory 206424 kb
Host smart-a8d8aa0e-4c20-484c-8272-dbe9558161f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289568744 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.2289568744
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.2318989000
Short name T1044
Test name
Test status
Simulation time 28291559 ps
CPU time 0.79 seconds
Started Jul 23 07:04:43 PM PDT 24
Finished Jul 23 07:04:44 PM PDT 24
Peak memory 206288 kb
Host smart-d8d5252f-5e31-4842-a656-7cfa78e8562c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318989000 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2318989000
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.2071300486
Short name T1065
Test name
Test status
Simulation time 23807968 ps
CPU time 0.83 seconds
Started Jul 23 07:04:45 PM PDT 24
Finished Jul 23 07:04:47 PM PDT 24
Peak memory 206468 kb
Host smart-d90b1c85-58ed-4427-905d-80125db3affd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071300486 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2071300486
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.2317181779
Short name T1009
Test name
Test status
Simulation time 41927105 ps
CPU time 0.91 seconds
Started Jul 23 07:04:47 PM PDT 24
Finished Jul 23 07:04:49 PM PDT 24
Peak memory 206460 kb
Host smart-5aa37c3c-06a5-44b6-9a1c-03a6cae87ceb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317181779 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.2317181779
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.1034397749
Short name T1029
Test name
Test status
Simulation time 37975304 ps
CPU time 0.76 seconds
Started Jul 23 07:04:45 PM PDT 24
Finished Jul 23 07:04:47 PM PDT 24
Peak memory 206236 kb
Host smart-59d8cda7-c800-4f15-adc3-79b2a7b1e355
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034397749 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.1034397749
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.2041405972
Short name T1101
Test name
Test status
Simulation time 26536029 ps
CPU time 0.85 seconds
Started Jul 23 07:04:42 PM PDT 24
Finished Jul 23 07:04:43 PM PDT 24
Peak memory 206512 kb
Host smart-dd1144e5-ab86-4c9f-96b1-f64d7729a5ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041405972 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2041405972
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.2698711307
Short name T1012
Test name
Test status
Simulation time 47325556 ps
CPU time 0.82 seconds
Started Jul 23 07:04:47 PM PDT 24
Finished Jul 23 07:04:49 PM PDT 24
Peak memory 206468 kb
Host smart-cf83e952-7b96-4da4-8958-4b66c8bc8734
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698711307 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.2698711307
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.424657033
Short name T1105
Test name
Test status
Simulation time 41038078 ps
CPU time 0.83 seconds
Started Jul 23 07:04:47 PM PDT 24
Finished Jul 23 07:04:49 PM PDT 24
Peak memory 206464 kb
Host smart-c9b2e93f-07dc-4ce2-b42f-0c96540351df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424657033 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.424657033
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.2897289793
Short name T1000
Test name
Test status
Simulation time 14845750 ps
CPU time 0.85 seconds
Started Jul 23 07:04:45 PM PDT 24
Finished Jul 23 07:04:46 PM PDT 24
Peak memory 206412 kb
Host smart-7ae451a7-54e9-4436-a69b-5e781a5218e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897289793 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2897289793
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1484674499
Short name T258
Test name
Test status
Simulation time 257608318 ps
CPU time 6.32 seconds
Started Jul 23 07:03:58 PM PDT 24
Finished Jul 23 07:04:05 PM PDT 24
Peak memory 206584 kb
Host smart-8f38bfa6-5f31-4510-b916-0a752439ade1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484674499 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1484674499
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.424541220
Short name T1075
Test name
Test status
Simulation time 51772240 ps
CPU time 0.92 seconds
Started Jul 23 07:03:56 PM PDT 24
Finished Jul 23 07:03:59 PM PDT 24
Peak memory 206460 kb
Host smart-8fbd73cc-fe6d-4d47-899e-1b7355a5583c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424541220 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.424541220
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2057914596
Short name T1033
Test name
Test status
Simulation time 19197824 ps
CPU time 1.21 seconds
Started Jul 23 07:04:06 PM PDT 24
Finished Jul 23 07:04:08 PM PDT 24
Peak memory 214968 kb
Host smart-fa301f9c-a7f2-43cc-9d02-c870b6c9b818
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057914596 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2057914596
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.554955875
Short name T1086
Test name
Test status
Simulation time 53865385 ps
CPU time 0.83 seconds
Started Jul 23 07:03:57 PM PDT 24
Finished Jul 23 07:03:59 PM PDT 24
Peak memory 206480 kb
Host smart-95b5ec88-c60e-4dfe-b1c0-39c6a0f59aab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554955875 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.554955875
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.630687207
Short name T1004
Test name
Test status
Simulation time 13763323 ps
CPU time 0.85 seconds
Started Jul 23 07:03:58 PM PDT 24
Finished Jul 23 07:04:00 PM PDT 24
Peak memory 206576 kb
Host smart-3cea035b-33a4-4ad1-bf96-b4d5f771c23b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630687207 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.630687207
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3974047188
Short name T1039
Test name
Test status
Simulation time 98563594 ps
CPU time 1.05 seconds
Started Jul 23 07:04:07 PM PDT 24
Finished Jul 23 07:04:09 PM PDT 24
Peak memory 206556 kb
Host smart-978df359-7422-4e73-9b04-55d907a360f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974047188 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.3974047188
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.2285832855
Short name T1102
Test name
Test status
Simulation time 77061237 ps
CPU time 2.96 seconds
Started Jul 23 07:03:56 PM PDT 24
Finished Jul 23 07:04:01 PM PDT 24
Peak memory 214704 kb
Host smart-7c90af21-8694-48c9-92d4-95cf36520cfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285832855 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.2285832855
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.558484224
Short name T1028
Test name
Test status
Simulation time 142826965 ps
CPU time 0.84 seconds
Started Jul 23 07:04:47 PM PDT 24
Finished Jul 23 07:04:49 PM PDT 24
Peak memory 206304 kb
Host smart-b96f1da8-efe0-4593-ab1e-fe31e2cc3ffd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558484224 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.558484224
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.4269618690
Short name T1083
Test name
Test status
Simulation time 16848465 ps
CPU time 0.84 seconds
Started Jul 23 07:04:50 PM PDT 24
Finished Jul 23 07:04:52 PM PDT 24
Peak memory 206488 kb
Host smart-045df205-4e69-438a-8c2b-e087442cb38a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269618690 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.4269618690
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.1184036872
Short name T1067
Test name
Test status
Simulation time 22304824 ps
CPU time 0.8 seconds
Started Jul 23 07:04:47 PM PDT 24
Finished Jul 23 07:04:49 PM PDT 24
Peak memory 206428 kb
Host smart-6e920c03-39be-4b0d-a690-1ea62ce1ac7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184036872 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.1184036872
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.3830548496
Short name T1074
Test name
Test status
Simulation time 30644284 ps
CPU time 0.83 seconds
Started Jul 23 07:04:48 PM PDT 24
Finished Jul 23 07:04:49 PM PDT 24
Peak memory 206300 kb
Host smart-646d0c8c-9f64-4ced-97f0-817b1a2fc6f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830548496 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3830548496
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.3775640630
Short name T1001
Test name
Test status
Simulation time 41066523 ps
CPU time 0.81 seconds
Started Jul 23 07:04:49 PM PDT 24
Finished Jul 23 07:04:51 PM PDT 24
Peak memory 206460 kb
Host smart-f5723f07-1399-41aa-b8a4-2c79a9a162b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775640630 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3775640630
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.2340177945
Short name T1087
Test name
Test status
Simulation time 11643299 ps
CPU time 0.83 seconds
Started Jul 23 07:04:48 PM PDT 24
Finished Jul 23 07:04:50 PM PDT 24
Peak memory 206644 kb
Host smart-ea9d4e38-1639-4f09-831f-80c47b51e916
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340177945 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.2340177945
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.1269248605
Short name T1119
Test name
Test status
Simulation time 56928960 ps
CPU time 0.81 seconds
Started Jul 23 07:04:48 PM PDT 24
Finished Jul 23 07:04:50 PM PDT 24
Peak memory 206488 kb
Host smart-c3ed0ca3-f5b5-43ad-8a6a-a8a278d2f902
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269248605 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.1269248605
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.1647832093
Short name T1020
Test name
Test status
Simulation time 32852080 ps
CPU time 0.88 seconds
Started Jul 23 07:04:48 PM PDT 24
Finished Jul 23 07:04:51 PM PDT 24
Peak memory 206484 kb
Host smart-92d6875d-fdf8-42f2-81f3-2fcbf53c7da9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647832093 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1647832093
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.3311482690
Short name T1025
Test name
Test status
Simulation time 11756398 ps
CPU time 0.83 seconds
Started Jul 23 07:04:47 PM PDT 24
Finished Jul 23 07:04:49 PM PDT 24
Peak memory 206500 kb
Host smart-003b6623-ec69-45d2-a014-93d29ecab643
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311482690 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3311482690
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.1953126867
Short name T1003
Test name
Test status
Simulation time 26389713 ps
CPU time 0.88 seconds
Started Jul 23 07:04:48 PM PDT 24
Finished Jul 23 07:04:50 PM PDT 24
Peak memory 206428 kb
Host smart-6997704c-f592-420e-9793-9fc36e64e8a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953126867 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.1953126867
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.446353032
Short name T245
Test name
Test status
Simulation time 44794547 ps
CPU time 1.11 seconds
Started Jul 23 07:04:06 PM PDT 24
Finished Jul 23 07:04:08 PM PDT 24
Peak memory 206512 kb
Host smart-ebb90749-466e-4ec0-b025-450d7976530e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446353032 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.446353032
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2892536355
Short name T257
Test name
Test status
Simulation time 255748281 ps
CPU time 2 seconds
Started Jul 23 07:04:06 PM PDT 24
Finished Jul 23 07:04:09 PM PDT 24
Peak memory 206564 kb
Host smart-92b59d98-e6cb-482b-b177-72c2a8df543f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892536355 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2892536355
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.319881420
Short name T249
Test name
Test status
Simulation time 54347258 ps
CPU time 0.9 seconds
Started Jul 23 07:04:07 PM PDT 24
Finished Jul 23 07:04:09 PM PDT 24
Peak memory 206416 kb
Host smart-a2775a9c-bf83-43c0-9e84-7d5b050bbbab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319881420 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.319881420
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1536935607
Short name T1050
Test name
Test status
Simulation time 37316114 ps
CPU time 0.97 seconds
Started Jul 23 07:04:07 PM PDT 24
Finished Jul 23 07:04:09 PM PDT 24
Peak memory 206664 kb
Host smart-21a34383-3bc0-4f20-af2e-70750292aafa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536935607 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.1536935607
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.4252497780
Short name T1054
Test name
Test status
Simulation time 11693132 ps
CPU time 0.89 seconds
Started Jul 23 07:04:05 PM PDT 24
Finished Jul 23 07:04:07 PM PDT 24
Peak memory 206480 kb
Host smart-5516a34c-8409-4c8c-b163-0d9d641c2be6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252497780 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.4252497780
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.3124290138
Short name T1079
Test name
Test status
Simulation time 16098164 ps
CPU time 0.83 seconds
Started Jul 23 07:04:06 PM PDT 24
Finished Jul 23 07:04:08 PM PDT 24
Peak memory 206476 kb
Host smart-694766fc-c864-4a05-8c16-e5bc23be014c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124290138 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.3124290138
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.430178915
Short name T1108
Test name
Test status
Simulation time 108580766 ps
CPU time 1.33 seconds
Started Jul 23 07:04:07 PM PDT 24
Finished Jul 23 07:04:09 PM PDT 24
Peak memory 206508 kb
Host smart-6b687dde-4247-4b5c-b877-db4f73296318
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430178915 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_out
standing.430178915
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.3794966416
Short name T1113
Test name
Test status
Simulation time 271739604 ps
CPU time 2.65 seconds
Started Jul 23 07:04:07 PM PDT 24
Finished Jul 23 07:04:11 PM PDT 24
Peak memory 214892 kb
Host smart-cff41661-9545-4ec6-9cac-99c8065d2d29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794966416 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.3794966416
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.876082966
Short name T1106
Test name
Test status
Simulation time 120287594 ps
CPU time 1.92 seconds
Started Jul 23 07:04:08 PM PDT 24
Finished Jul 23 07:04:11 PM PDT 24
Peak memory 214748 kb
Host smart-9810d003-983a-4fd7-8421-88bc01dd8fb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876082966 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.876082966
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.306875530
Short name T1015
Test name
Test status
Simulation time 25996013 ps
CPU time 0.85 seconds
Started Jul 23 07:04:46 PM PDT 24
Finished Jul 23 07:04:48 PM PDT 24
Peak memory 206484 kb
Host smart-65ebd1ad-bd1d-412c-9aed-280cc6abffe6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306875530 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.306875530
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.3103867106
Short name T1007
Test name
Test status
Simulation time 14529702 ps
CPU time 0.87 seconds
Started Jul 23 07:04:48 PM PDT 24
Finished Jul 23 07:04:49 PM PDT 24
Peak memory 206480 kb
Host smart-92f10915-e267-4aa7-a702-b9ca55ffa4b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103867106 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.3103867106
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.356292548
Short name T1121
Test name
Test status
Simulation time 17259666 ps
CPU time 0.92 seconds
Started Jul 23 07:04:52 PM PDT 24
Finished Jul 23 07:04:53 PM PDT 24
Peak memory 206464 kb
Host smart-2d170fe0-5d43-4134-bc2d-c1d32c032275
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356292548 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.356292548
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.2028003220
Short name T1088
Test name
Test status
Simulation time 51316304 ps
CPU time 0.82 seconds
Started Jul 23 07:04:52 PM PDT 24
Finished Jul 23 07:04:55 PM PDT 24
Peak memory 206652 kb
Host smart-3be14088-6ec3-4996-a4bd-6ba26dce92e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028003220 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2028003220
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.366528816
Short name T1112
Test name
Test status
Simulation time 39714161 ps
CPU time 0.8 seconds
Started Jul 23 07:04:52 PM PDT 24
Finished Jul 23 07:04:54 PM PDT 24
Peak memory 206316 kb
Host smart-158f8432-175a-4234-9179-cec848f5d9b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366528816 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.366528816
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.2937878531
Short name T1085
Test name
Test status
Simulation time 14752370 ps
CPU time 0.85 seconds
Started Jul 23 07:04:52 PM PDT 24
Finished Jul 23 07:04:54 PM PDT 24
Peak memory 206504 kb
Host smart-260dd768-c1ae-422a-af68-8a1db7415eb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937878531 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.2937878531
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1502835978
Short name T1017
Test name
Test status
Simulation time 50750597 ps
CPU time 0.88 seconds
Started Jul 23 07:04:52 PM PDT 24
Finished Jul 23 07:04:54 PM PDT 24
Peak memory 206488 kb
Host smart-c4b43385-da87-4b84-b4cf-a21e3903967d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502835978 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1502835978
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.692679004
Short name T1092
Test name
Test status
Simulation time 13504195 ps
CPU time 0.92 seconds
Started Jul 23 07:04:53 PM PDT 24
Finished Jul 23 07:04:55 PM PDT 24
Peak memory 206560 kb
Host smart-9ab6de21-9857-4a30-953c-f936175ce25a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692679004 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.692679004
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.3934785079
Short name T1109
Test name
Test status
Simulation time 46833028 ps
CPU time 0.81 seconds
Started Jul 23 07:04:53 PM PDT 24
Finished Jul 23 07:04:55 PM PDT 24
Peak memory 206272 kb
Host smart-6a3f6aa0-74fa-4b1a-8f37-988add152303
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934785079 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3934785079
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.2423768331
Short name T1084
Test name
Test status
Simulation time 13992313 ps
CPU time 0.86 seconds
Started Jul 23 07:04:53 PM PDT 24
Finished Jul 23 07:04:55 PM PDT 24
Peak memory 206492 kb
Host smart-1c191236-5a1c-463a-8058-d860004bf793
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423768331 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.2423768331
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3745019007
Short name T1076
Test name
Test status
Simulation time 56835311 ps
CPU time 1.75 seconds
Started Jul 23 07:04:16 PM PDT 24
Finished Jul 23 07:04:18 PM PDT 24
Peak memory 214884 kb
Host smart-56468756-3a0e-4a82-9df8-68cff00a252d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745019007 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.3745019007
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.2466423158
Short name T243
Test name
Test status
Simulation time 20994848 ps
CPU time 0.84 seconds
Started Jul 23 07:04:14 PM PDT 24
Finished Jul 23 07:04:16 PM PDT 24
Peak memory 206492 kb
Host smart-96be165f-c07e-43b0-a3f2-b09e63bb29d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466423158 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2466423158
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.4055172394
Short name T1053
Test name
Test status
Simulation time 169077031 ps
CPU time 0.89 seconds
Started Jul 23 07:04:15 PM PDT 24
Finished Jul 23 07:04:17 PM PDT 24
Peak memory 206484 kb
Host smart-2b0478ea-d19a-4466-b0fe-822997f7c45f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055172394 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.4055172394
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3003593549
Short name T265
Test name
Test status
Simulation time 72574089 ps
CPU time 1.05 seconds
Started Jul 23 07:04:14 PM PDT 24
Finished Jul 23 07:04:16 PM PDT 24
Peak memory 206572 kb
Host smart-b6f3c9e5-0baa-44ff-956b-cf587b6d8731
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003593549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.3003593549
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.54297305
Short name T1021
Test name
Test status
Simulation time 106622968 ps
CPU time 3.6 seconds
Started Jul 23 07:04:15 PM PDT 24
Finished Jul 23 07:04:20 PM PDT 24
Peak memory 214888 kb
Host smart-104a43c4-9c7d-423a-b743-9c5f8586a723
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54297305 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.54297305
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.407215121
Short name T1127
Test name
Test status
Simulation time 160991749 ps
CPU time 3.22 seconds
Started Jul 23 07:04:15 PM PDT 24
Finished Jul 23 07:04:20 PM PDT 24
Peak memory 206648 kb
Host smart-3657eb97-6bdb-49d8-bbd5-1581a65260c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407215121 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.407215121
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2370948139
Short name T1061
Test name
Test status
Simulation time 24556277 ps
CPU time 0.99 seconds
Started Jul 23 07:04:25 PM PDT 24
Finished Jul 23 07:04:27 PM PDT 24
Peak memory 214836 kb
Host smart-33826618-d743-4e8c-bd59-a68d07aea6bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370948139 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.2370948139
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.1423328000
Short name T1010
Test name
Test status
Simulation time 12898494 ps
CPU time 0.85 seconds
Started Jul 23 07:04:15 PM PDT 24
Finished Jul 23 07:04:17 PM PDT 24
Peak memory 206548 kb
Host smart-ed33073e-f84e-4965-98ce-0fee0b5f6cac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423328000 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1423328000
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3494754580
Short name T1013
Test name
Test status
Simulation time 11611118 ps
CPU time 0.86 seconds
Started Jul 23 07:04:15 PM PDT 24
Finished Jul 23 07:04:17 PM PDT 24
Peak memory 206388 kb
Host smart-e9e4707e-9fee-4e29-971d-ba19125834b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494754580 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3494754580
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3114121636
Short name T1068
Test name
Test status
Simulation time 34619856 ps
CPU time 1.13 seconds
Started Jul 23 07:04:15 PM PDT 24
Finished Jul 23 07:04:18 PM PDT 24
Peak memory 206592 kb
Host smart-7ca833dc-04e9-4aa2-85b0-d3c29c632483
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114121636 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.3114121636
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.297339833
Short name T1042
Test name
Test status
Simulation time 358376437 ps
CPU time 5.13 seconds
Started Jul 23 07:04:16 PM PDT 24
Finished Jul 23 07:04:22 PM PDT 24
Peak memory 215080 kb
Host smart-d3e82a7a-5612-4a94-9d16-79c0fc49c775
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297339833 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.297339833
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2497894325
Short name T1049
Test name
Test status
Simulation time 198721495 ps
CPU time 3.94 seconds
Started Jul 23 07:04:17 PM PDT 24
Finished Jul 23 07:04:22 PM PDT 24
Peak memory 214768 kb
Host smart-0013ddd8-5fef-43b9-ab1a-6ce854861d65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497894325 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.2497894325
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1571596782
Short name T1052
Test name
Test status
Simulation time 23302857 ps
CPU time 1.56 seconds
Started Jul 23 07:04:25 PM PDT 24
Finished Jul 23 07:04:27 PM PDT 24
Peak memory 214832 kb
Host smart-22bae89f-cb13-48f4-9606-742a2917a2d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571596782 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1571596782
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.4162990788
Short name T256
Test name
Test status
Simulation time 19736893 ps
CPU time 0.88 seconds
Started Jul 23 07:04:27 PM PDT 24
Finished Jul 23 07:04:29 PM PDT 24
Peak memory 206436 kb
Host smart-6183ef8b-f4ef-4af4-84ec-52eb5593f23a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162990788 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.4162990788
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.1112596502
Short name T1080
Test name
Test status
Simulation time 45145819 ps
CPU time 0.83 seconds
Started Jul 23 07:04:25 PM PDT 24
Finished Jul 23 07:04:27 PM PDT 24
Peak memory 206484 kb
Host smart-4a66455c-ca98-477d-8f62-38150747528c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112596502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.1112596502
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1958968972
Short name T1035
Test name
Test status
Simulation time 29572217 ps
CPU time 1.1 seconds
Started Jul 23 07:04:26 PM PDT 24
Finished Jul 23 07:04:29 PM PDT 24
Peak memory 206536 kb
Host smart-0199bbc0-1e28-4be4-abe8-207e5b602c06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958968972 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.1958968972
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2170387845
Short name T1011
Test name
Test status
Simulation time 36496943 ps
CPU time 2.32 seconds
Started Jul 23 07:04:26 PM PDT 24
Finished Jul 23 07:04:30 PM PDT 24
Peak memory 214772 kb
Host smart-6a0a2441-9fc2-4391-a9fb-7a8f2485adab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170387845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2170387845
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3157515136
Short name T1059
Test name
Test status
Simulation time 95550193 ps
CPU time 1.61 seconds
Started Jul 23 07:04:26 PM PDT 24
Finished Jul 23 07:04:28 PM PDT 24
Peak memory 206576 kb
Host smart-e4d42e83-6a00-4a7e-b1cc-456ec7eff086
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157515136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.3157515136
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3100161263
Short name T1110
Test name
Test status
Simulation time 128867388 ps
CPU time 1.69 seconds
Started Jul 23 07:04:25 PM PDT 24
Finished Jul 23 07:04:28 PM PDT 24
Peak memory 214876 kb
Host smart-ea0505ff-5e05-4ce7-a355-cc50a21cc709
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100161263 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3100161263
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.41645424
Short name T1071
Test name
Test status
Simulation time 12767183 ps
CPU time 0.84 seconds
Started Jul 23 07:04:25 PM PDT 24
Finished Jul 23 07:04:27 PM PDT 24
Peak memory 206476 kb
Host smart-99337bf3-3a0e-45e5-a7ce-1c15d4297a1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41645424 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.41645424
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.3109216815
Short name T1045
Test name
Test status
Simulation time 97829771 ps
CPU time 0.75 seconds
Started Jul 23 07:04:27 PM PDT 24
Finished Jul 23 07:04:29 PM PDT 24
Peak memory 206292 kb
Host smart-430b2fa1-80ec-4870-846f-e9a4d4f51404
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109216815 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.3109216815
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3701403578
Short name T1036
Test name
Test status
Simulation time 45620829 ps
CPU time 1.02 seconds
Started Jul 23 07:04:26 PM PDT 24
Finished Jul 23 07:04:29 PM PDT 24
Peak memory 206528 kb
Host smart-c5b3fa42-8e27-4d9d-8ee4-d5d28c4b98f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701403578 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.3701403578
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.1289805266
Short name T1094
Test name
Test status
Simulation time 93154902 ps
CPU time 2.01 seconds
Started Jul 23 07:04:25 PM PDT 24
Finished Jul 23 07:04:27 PM PDT 24
Peak memory 214804 kb
Host smart-decb2e85-6752-4d74-be6c-6cd738c289b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289805266 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.1289805266
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1377433763
Short name T273
Test name
Test status
Simulation time 140652233 ps
CPU time 1.63 seconds
Started Jul 23 07:04:25 PM PDT 24
Finished Jul 23 07:04:27 PM PDT 24
Peak memory 206540 kb
Host smart-5d1bbee0-5c5a-4c56-a798-935cbe5b5e3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377433763 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1377433763
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.978736246
Short name T1066
Test name
Test status
Simulation time 36566009 ps
CPU time 1.03 seconds
Started Jul 23 07:04:24 PM PDT 24
Finished Jul 23 07:04:26 PM PDT 24
Peak memory 214896 kb
Host smart-75b4d8d8-a448-4863-8228-d5ce79c94926
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978736246 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.978736246
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.3150511239
Short name T1058
Test name
Test status
Simulation time 25606438 ps
CPU time 0.9 seconds
Started Jul 23 07:04:25 PM PDT 24
Finished Jul 23 07:04:28 PM PDT 24
Peak memory 206432 kb
Host smart-423dd98b-1c8d-4872-b7bb-40f039613db7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150511239 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3150511239
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.310459772
Short name T1064
Test name
Test status
Simulation time 15330019 ps
CPU time 0.86 seconds
Started Jul 23 07:04:26 PM PDT 24
Finished Jul 23 07:04:29 PM PDT 24
Peak memory 206448 kb
Host smart-b146ee6d-a311-4edf-b7b1-b42250bf0f20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310459772 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.310459772
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2188315020
Short name T261
Test name
Test status
Simulation time 67371625 ps
CPU time 1.5 seconds
Started Jul 23 07:04:26 PM PDT 24
Finished Jul 23 07:04:29 PM PDT 24
Peak memory 206744 kb
Host smart-c3fa9b3a-aee2-4b3a-a0ac-bf4d536807d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188315020 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.2188315020
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.2860493890
Short name T1060
Test name
Test status
Simulation time 75292630 ps
CPU time 2.77 seconds
Started Jul 23 07:04:28 PM PDT 24
Finished Jul 23 07:04:31 PM PDT 24
Peak memory 214772 kb
Host smart-0af5a67a-e4f1-4763-ab24-d447bae8aa6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860493890 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.2860493890
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3561098708
Short name T283
Test name
Test status
Simulation time 370067729 ps
CPU time 1.7 seconds
Started Jul 23 07:04:26 PM PDT 24
Finished Jul 23 07:04:29 PM PDT 24
Peak memory 214756 kb
Host smart-cbe9096d-3902-4521-9632-a9cc61e52d2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561098708 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3561098708
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.2444603001
Short name T880
Test name
Test status
Simulation time 173676604 ps
CPU time 1.08 seconds
Started Jul 23 07:08:36 PM PDT 24
Finished Jul 23 07:08:39 PM PDT 24
Peak memory 218704 kb
Host smart-96ac2002-b67e-493e-87d3-02100683e3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444603001 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.2444603001
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.3754901634
Short name T568
Test name
Test status
Simulation time 41238084 ps
CPU time 0.83 seconds
Started Jul 23 07:08:42 PM PDT 24
Finished Jul 23 07:08:45 PM PDT 24
Peak memory 215052 kb
Host smart-e3ea6ed4-f7dc-4aab-a62f-924ac343f0f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754901634 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.3754901634
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.2570791083
Short name T171
Test name
Test status
Simulation time 13273963 ps
CPU time 0.93 seconds
Started Jul 23 07:08:39 PM PDT 24
Finished Jul 23 07:08:41 PM PDT 24
Peak memory 216812 kb
Host smart-29805453-80d6-49cf-80c8-5f795d1cb6e5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570791083 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.2570791083
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.4040893117
Short name T207
Test name
Test status
Simulation time 75338822 ps
CPU time 1.23 seconds
Started Jul 23 07:08:41 PM PDT 24
Finished Jul 23 07:08:45 PM PDT 24
Peak memory 217424 kb
Host smart-277ff5a8-b35c-44e4-b09d-3920863d8c48
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040893117 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.4040893117
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.1006268506
Short name T833
Test name
Test status
Simulation time 98931077 ps
CPU time 1.16 seconds
Started Jul 23 07:08:39 PM PDT 24
Finished Jul 23 07:08:41 PM PDT 24
Peak memory 219956 kb
Host smart-00f88d84-a83b-406f-b1c0-33a3d0033f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006268506 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1006268506
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.2535077478
Short name T858
Test name
Test status
Simulation time 146467240 ps
CPU time 2.83 seconds
Started Jul 23 07:08:36 PM PDT 24
Finished Jul 23 07:08:40 PM PDT 24
Peak memory 219672 kb
Host smart-9afa2093-a5c8-44d2-8435-f5e1324e66c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535077478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2535077478
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_sec_cm.2862040183
Short name T19
Test name
Test status
Simulation time 3027611500 ps
CPU time 7.99 seconds
Started Jul 23 07:08:42 PM PDT 24
Finished Jul 23 07:08:52 PM PDT 24
Peak memory 236868 kb
Host smart-e3f3652b-64e8-4e2a-b1db-1efb0e3334fa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862040183 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.2862040183
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.2403018092
Short name T63
Test name
Test status
Simulation time 39536621 ps
CPU time 0.9 seconds
Started Jul 23 07:08:39 PM PDT 24
Finished Jul 23 07:08:42 PM PDT 24
Peak memory 215624 kb
Host smart-de630939-d700-454a-80bf-02253339f803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403018092 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2403018092
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.1004828572
Short name T457
Test name
Test status
Simulation time 237357711 ps
CPU time 3.85 seconds
Started Jul 23 07:08:38 PM PDT 24
Finished Jul 23 07:08:43 PM PDT 24
Peak memory 217716 kb
Host smart-15beabfc-43e7-4b05-a7d0-d5cf92cc39b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004828572 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.1004828572
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.968456933
Short name T706
Test name
Test status
Simulation time 76111166042 ps
CPU time 592.4 seconds
Started Jul 23 07:08:36 PM PDT 24
Finished Jul 23 07:18:30 PM PDT 24
Peak memory 219168 kb
Host smart-80d7926c-7f2f-467a-aa7e-738e9747b872
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968456933 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.968456933
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert_test.261832939
Short name T711
Test name
Test status
Simulation time 30264242 ps
CPU time 1 seconds
Started Jul 23 07:08:45 PM PDT 24
Finished Jul 23 07:08:47 PM PDT 24
Peak memory 215168 kb
Host smart-a6ece4b4-580e-4603-bca9-c6a575d5f6fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261832939 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.261832939
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.3864432759
Short name T642
Test name
Test status
Simulation time 33726051 ps
CPU time 0.83 seconds
Started Jul 23 07:08:40 PM PDT 24
Finished Jul 23 07:08:42 PM PDT 24
Peak memory 216584 kb
Host smart-787710a9-30dd-4f20-a0e7-97d6321fbe56
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864432759 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3864432759
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_err.3974018616
Short name T176
Test name
Test status
Simulation time 21302576 ps
CPU time 1.04 seconds
Started Jul 23 07:08:45 PM PDT 24
Finished Jul 23 07:08:47 PM PDT 24
Peak memory 224284 kb
Host smart-ad8c96f6-a44f-40ef-8b1c-e917e3c0bb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974018616 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.3974018616
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.1538293945
Short name T726
Test name
Test status
Simulation time 368485760 ps
CPU time 1.34 seconds
Started Jul 23 07:08:49 PM PDT 24
Finished Jul 23 07:08:53 PM PDT 24
Peak memory 219220 kb
Host smart-f34b3f13-5349-4cff-bca6-9c945335a092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538293945 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.1538293945
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.833933559
Short name T362
Test name
Test status
Simulation time 24602817 ps
CPU time 1 seconds
Started Jul 23 07:08:40 PM PDT 24
Finished Jul 23 07:08:43 PM PDT 24
Peak memory 215852 kb
Host smart-378ea285-7bcc-49d3-9ce6-85189b656a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833933559 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.833933559
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.1464519730
Short name T695
Test name
Test status
Simulation time 42960134 ps
CPU time 0.9 seconds
Started Jul 23 07:08:47 PM PDT 24
Finished Jul 23 07:08:50 PM PDT 24
Peak memory 207424 kb
Host smart-76d2e017-84b7-4d95-bdf7-4c5c6e06dc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464519730 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.1464519730
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.4152795005
Short name T62
Test name
Test status
Simulation time 644766235 ps
CPU time 9.86 seconds
Started Jul 23 07:08:43 PM PDT 24
Finished Jul 23 07:08:54 PM PDT 24
Peak memory 236448 kb
Host smart-00d1ed49-1a18-4f77-aa5e-3a7aad9d87f4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152795005 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.4152795005
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.2649084975
Short name T607
Test name
Test status
Simulation time 34468572 ps
CPU time 0.93 seconds
Started Jul 23 07:08:46 PM PDT 24
Finished Jul 23 07:08:48 PM PDT 24
Peak memory 215480 kb
Host smart-1e0aa67c-13f3-48df-adbe-0d352558c094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649084975 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.2649084975
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.512982408
Short name T237
Test name
Test status
Simulation time 397274007 ps
CPU time 1.84 seconds
Started Jul 23 07:08:40 PM PDT 24
Finished Jul 23 07:08:44 PM PDT 24
Peak memory 215624 kb
Host smart-428ea587-1a1a-451f-a395-642ab663f986
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512982408 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.512982408
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.1318066718
Short name T228
Test name
Test status
Simulation time 79585721466 ps
CPU time 457.11 seconds
Started Jul 23 07:08:42 PM PDT 24
Finished Jul 23 07:16:21 PM PDT 24
Peak memory 218644 kb
Host smart-8ce4c143-dc31-497c-86cf-7497d26bd6b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318066718 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.1318066718
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.2750630852
Short name T185
Test name
Test status
Simulation time 89556874 ps
CPU time 1.12 seconds
Started Jul 23 07:09:00 PM PDT 24
Finished Jul 23 07:09:02 PM PDT 24
Peak memory 216060 kb
Host smart-63a39826-10e4-4c16-befc-af68ac91634c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750630852 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.2750630852
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.3291331617
Short name T934
Test name
Test status
Simulation time 61162591 ps
CPU time 0.98 seconds
Started Jul 23 07:09:02 PM PDT 24
Finished Jul 23 07:09:05 PM PDT 24
Peak memory 215496 kb
Host smart-75fe1b0a-9f89-4608-ab38-eaff5c22b7fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291331617 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.3291331617
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.3288031702
Short name T370
Test name
Test status
Simulation time 39083124 ps
CPU time 1.18 seconds
Started Jul 23 07:09:00 PM PDT 24
Finished Jul 23 07:09:03 PM PDT 24
Peak memory 218824 kb
Host smart-b0b97bb7-888a-459b-ae6e-3b6ee2efe689
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288031702 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.3288031702
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.3753004734
Short name T148
Test name
Test status
Simulation time 39027846 ps
CPU time 1.04 seconds
Started Jul 23 07:09:05 PM PDT 24
Finished Jul 23 07:09:07 PM PDT 24
Peak memory 219864 kb
Host smart-5aaa6379-5067-4d5f-b29d-5f016b661df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753004734 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.3753004734
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_intr.4184193548
Short name T797
Test name
Test status
Simulation time 28285361 ps
CPU time 0.94 seconds
Started Jul 23 07:09:02 PM PDT 24
Finished Jul 23 07:09:05 PM PDT 24
Peak memory 216252 kb
Host smart-9fb0372d-f0a9-4f20-956d-e0a7fb9f7ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184193548 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.4184193548
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.3186241923
Short name T380
Test name
Test status
Simulation time 33477227 ps
CPU time 0.9 seconds
Started Jul 23 07:09:01 PM PDT 24
Finished Jul 23 07:09:04 PM PDT 24
Peak memory 215640 kb
Host smart-3c468104-5ed1-4e99-9bc6-1d408e10229e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186241923 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.3186241923
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.427191640
Short name T944
Test name
Test status
Simulation time 168636728 ps
CPU time 3.14 seconds
Started Jul 23 07:09:02 PM PDT 24
Finished Jul 23 07:09:07 PM PDT 24
Peak memory 217468 kb
Host smart-fca9ef2b-b596-431a-b89f-8329e165e220
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427191640 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.427191640
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.3444941380
Short name T555
Test name
Test status
Simulation time 105340496153 ps
CPU time 500.29 seconds
Started Jul 23 07:09:01 PM PDT 24
Finished Jul 23 07:17:23 PM PDT 24
Peak memory 220420 kb
Host smart-3c403b2d-1f43-4c26-afc8-bab8c3bd3246
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444941380 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.3444941380
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.897038230
Short name T180
Test name
Test status
Simulation time 65443532 ps
CPU time 1.04 seconds
Started Jul 23 07:10:38 PM PDT 24
Finished Jul 23 07:10:49 PM PDT 24
Peak memory 218680 kb
Host smart-7e3df166-bf15-4115-8b71-944aa8b1587e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897038230 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.897038230
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.1693479089
Short name T744
Test name
Test status
Simulation time 35931540 ps
CPU time 1.41 seconds
Started Jul 23 07:10:39 PM PDT 24
Finished Jul 23 07:10:51 PM PDT 24
Peak memory 217860 kb
Host smart-0b2645f6-5c17-4bb9-bfed-2a5b86df4123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693479089 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.1693479089
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.1476486986
Short name T594
Test name
Test status
Simulation time 35910390 ps
CPU time 1.17 seconds
Started Jul 23 07:10:40 PM PDT 24
Finished Jul 23 07:10:52 PM PDT 24
Peak memory 219968 kb
Host smart-469e9c70-6c22-4172-9465-1c40ab4f3923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476486986 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.1476486986
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.3069745120
Short name T622
Test name
Test status
Simulation time 33000461 ps
CPU time 1.32 seconds
Started Jul 23 07:10:40 PM PDT 24
Finished Jul 23 07:10:52 PM PDT 24
Peak memory 219680 kb
Host smart-7dd2fcd1-b9b4-49e1-9639-658ed6b7b9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069745120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.3069745120
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.3389319970
Short name T324
Test name
Test status
Simulation time 262546490 ps
CPU time 1.18 seconds
Started Jul 23 07:10:37 PM PDT 24
Finished Jul 23 07:10:48 PM PDT 24
Peak memory 217712 kb
Host smart-bce27562-4f31-4f22-bdc0-413c3b3ee19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389319970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.3389319970
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.2743092036
Short name T402
Test name
Test status
Simulation time 147082729 ps
CPU time 2.15 seconds
Started Jul 23 07:10:34 PM PDT 24
Finished Jul 23 07:10:46 PM PDT 24
Peak memory 220596 kb
Host smart-3aee67b6-9829-4965-b1d8-f358446f3f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743092036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.2743092036
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.1693335924
Short name T770
Test name
Test status
Simulation time 177204719 ps
CPU time 1.19 seconds
Started Jul 23 07:10:40 PM PDT 24
Finished Jul 23 07:10:51 PM PDT 24
Peak memory 219280 kb
Host smart-55886844-c0cf-4d49-92cd-129baf1ff475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693335924 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.1693335924
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.698824052
Short name T3
Test name
Test status
Simulation time 53612722 ps
CPU time 1.71 seconds
Started Jul 23 07:10:31 PM PDT 24
Finished Jul 23 07:10:42 PM PDT 24
Peak memory 218808 kb
Host smart-373ab3ea-a57c-421f-9699-acf000458bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698824052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.698824052
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.1029382466
Short name T285
Test name
Test status
Simulation time 135053260 ps
CPU time 1.17 seconds
Started Jul 23 07:10:35 PM PDT 24
Finished Jul 23 07:10:45 PM PDT 24
Peak memory 219052 kb
Host smart-154c3016-37e3-4bd5-9442-a0d5b4339371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029382466 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.1029382466
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.3551310105
Short name T608
Test name
Test status
Simulation time 32605021 ps
CPU time 1.23 seconds
Started Jul 23 07:10:37 PM PDT 24
Finished Jul 23 07:10:48 PM PDT 24
Peak memory 217592 kb
Host smart-08c2208b-6acc-4c0b-98c4-d4daeeb07672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551310105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.3551310105
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.816129459
Short name T316
Test name
Test status
Simulation time 113096524 ps
CPU time 1.3 seconds
Started Jul 23 07:10:39 PM PDT 24
Finished Jul 23 07:10:51 PM PDT 24
Peak memory 219760 kb
Host smart-e215f2f2-d083-4c82-a817-27fb3ccde9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816129459 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.816129459
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.2092357132
Short name T352
Test name
Test status
Simulation time 85560123 ps
CPU time 1.04 seconds
Started Jul 23 07:10:33 PM PDT 24
Finished Jul 23 07:10:43 PM PDT 24
Peak memory 217620 kb
Host smart-391bf5e0-358a-45a9-a78f-947a18d02a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092357132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.2092357132
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.2117569666
Short name T823
Test name
Test status
Simulation time 21765494 ps
CPU time 1.11 seconds
Started Jul 23 07:10:38 PM PDT 24
Finished Jul 23 07:10:49 PM PDT 24
Peak memory 219252 kb
Host smart-faf58579-f1b4-4bc4-b959-d34376885870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117569666 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.2117569666
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.1447918635
Short name T566
Test name
Test status
Simulation time 383086383 ps
CPU time 1.18 seconds
Started Jul 23 07:10:33 PM PDT 24
Finished Jul 23 07:10:43 PM PDT 24
Peak memory 217608 kb
Host smart-fc6a453d-a560-44bf-a13d-0f4dc5370f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447918635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.1447918635
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.173030957
Short name T213
Test name
Test status
Simulation time 25064479 ps
CPU time 1.21 seconds
Started Jul 23 07:10:43 PM PDT 24
Finished Jul 23 07:10:55 PM PDT 24
Peak memory 220052 kb
Host smart-2124a8ed-6a73-4e98-8029-8e528bd2edaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173030957 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.173030957
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.2608347171
Short name T788
Test name
Test status
Simulation time 54383596 ps
CPU time 1.37 seconds
Started Jul 23 07:10:46 PM PDT 24
Finished Jul 23 07:10:58 PM PDT 24
Peak memory 219244 kb
Host smart-e3d61413-0097-4d32-aaed-bbdff690e80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608347171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.2608347171
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.95785283
Short name T860
Test name
Test status
Simulation time 76421413 ps
CPU time 1.11 seconds
Started Jul 23 07:08:59 PM PDT 24
Finished Jul 23 07:09:02 PM PDT 24
Peak memory 220164 kb
Host smart-82ce9280-a582-4a93-a181-0a2474817d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95785283 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.95785283
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_disable.1107446298
Short name T674
Test name
Test status
Simulation time 20233135 ps
CPU time 0.86 seconds
Started Jul 23 07:08:58 PM PDT 24
Finished Jul 23 07:09:00 PM PDT 24
Peak memory 216716 kb
Host smart-92aa287c-c55f-4d06-9f14-35cee43e233c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107446298 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.1107446298
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.3619455206
Short name T651
Test name
Test status
Simulation time 174715463 ps
CPU time 1.22 seconds
Started Jul 23 07:09:10 PM PDT 24
Finished Jul 23 07:09:13 PM PDT 24
Peak memory 217236 kb
Host smart-2ac147e2-5ca4-40db-b271-9e980fbb394b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619455206 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.3619455206
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.1473921679
Short name T49
Test name
Test status
Simulation time 23545007 ps
CPU time 1 seconds
Started Jul 23 07:09:00 PM PDT 24
Finished Jul 23 07:09:03 PM PDT 24
Peak memory 224212 kb
Host smart-38d08ec3-d878-4b92-921c-624c2e4b28a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473921679 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.1473921679
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.2793213499
Short name T801
Test name
Test status
Simulation time 55509469 ps
CPU time 1.33 seconds
Started Jul 23 07:09:00 PM PDT 24
Finished Jul 23 07:09:03 PM PDT 24
Peak memory 219784 kb
Host smart-03034111-b28f-4b51-bd5c-29f597b91b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793213499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2793213499
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.4064812623
Short name T504
Test name
Test status
Simulation time 27500063 ps
CPU time 1.08 seconds
Started Jul 23 07:09:01 PM PDT 24
Finished Jul 23 07:09:04 PM PDT 24
Peak memory 224356 kb
Host smart-1a56e532-98cd-4901-afde-92367b424362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064812623 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.4064812623
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.155788550
Short name T544
Test name
Test status
Simulation time 26651203 ps
CPU time 0.93 seconds
Started Jul 23 07:08:59 PM PDT 24
Finished Jul 23 07:09:02 PM PDT 24
Peak memory 215640 kb
Host smart-6b977b64-eeb4-4ff2-a0a9-20c207683f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155788550 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.155788550
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.4061054850
Short name T232
Test name
Test status
Simulation time 47726068636 ps
CPU time 1132.15 seconds
Started Jul 23 07:09:02 PM PDT 24
Finished Jul 23 07:27:56 PM PDT 24
Peak memory 220804 kb
Host smart-dbe452d1-fbc4-40ff-83a0-0675a6944c81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061054850 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.4061054850
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.3492258130
Short name T271
Test name
Test status
Simulation time 51356606 ps
CPU time 1.24 seconds
Started Jul 23 07:10:41 PM PDT 24
Finished Jul 23 07:10:52 PM PDT 24
Peak memory 220796 kb
Host smart-14049095-4e8f-46c3-88c0-9953f7c0a89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492258130 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.3492258130
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.2981502399
Short name T605
Test name
Test status
Simulation time 35851154 ps
CPU time 1.3 seconds
Started Jul 23 07:10:39 PM PDT 24
Finished Jul 23 07:10:51 PM PDT 24
Peak memory 217584 kb
Host smart-0cece970-8fd8-4d17-b47c-3ac93aba5f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981502399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2981502399
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.255185515
Short name T909
Test name
Test status
Simulation time 54764908 ps
CPU time 1.17 seconds
Started Jul 23 07:10:38 PM PDT 24
Finished Jul 23 07:10:49 PM PDT 24
Peak memory 220528 kb
Host smart-4c17d8a2-e112-4858-9de3-9b256578450b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255185515 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.255185515
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.1393786592
Short name T499
Test name
Test status
Simulation time 96257387 ps
CPU time 1.42 seconds
Started Jul 23 07:10:48 PM PDT 24
Finished Jul 23 07:11:00 PM PDT 24
Peak memory 219244 kb
Host smart-791de807-5b56-4797-8733-5b72399eddc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393786592 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1393786592
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.3267268065
Short name T407
Test name
Test status
Simulation time 37125540 ps
CPU time 1.14 seconds
Started Jul 23 07:10:45 PM PDT 24
Finished Jul 23 07:10:57 PM PDT 24
Peak memory 219976 kb
Host smart-0d46b7d2-477c-409b-bd96-3405f18afdbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267268065 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.3267268065
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.281660409
Short name T512
Test name
Test status
Simulation time 45290749 ps
CPU time 1.82 seconds
Started Jul 23 07:10:46 PM PDT 24
Finished Jul 23 07:10:59 PM PDT 24
Peak memory 218896 kb
Host smart-5de104b6-0f7b-4c06-9f5b-be8ce36d6279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281660409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.281660409
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.2367451847
Short name T312
Test name
Test status
Simulation time 44597401 ps
CPU time 1.13 seconds
Started Jul 23 07:10:45 PM PDT 24
Finished Jul 23 07:10:56 PM PDT 24
Peak memory 219068 kb
Host smart-550f0620-ea10-4e36-b389-de380772111e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367451847 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.2367451847
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.850576063
Short name T587
Test name
Test status
Simulation time 53532075 ps
CPU time 1.26 seconds
Started Jul 23 07:10:43 PM PDT 24
Finished Jul 23 07:10:55 PM PDT 24
Peak memory 217536 kb
Host smart-26038bd6-d9bc-4a0b-bcb0-e2ebd9ab68f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850576063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.850576063
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.3594681860
Short name T783
Test name
Test status
Simulation time 36334972 ps
CPU time 1.08 seconds
Started Jul 23 07:10:40 PM PDT 24
Finished Jul 23 07:10:52 PM PDT 24
Peak memory 220136 kb
Host smart-446764e8-d202-4a18-a7a2-7379eff234e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594681860 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.3594681860
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.1957579571
Short name T466
Test name
Test status
Simulation time 62178859 ps
CPU time 1.7 seconds
Started Jul 23 07:10:43 PM PDT 24
Finished Jul 23 07:10:55 PM PDT 24
Peak memory 219152 kb
Host smart-01758b44-08dc-46c5-8b7c-2ceae1b4a705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957579571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.1957579571
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.3691022262
Short name T187
Test name
Test status
Simulation time 29436867 ps
CPU time 1.25 seconds
Started Jul 23 07:10:40 PM PDT 24
Finished Jul 23 07:10:51 PM PDT 24
Peak memory 220156 kb
Host smart-fa000f4e-3793-4d00-8bad-ff0d8f2eca05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691022262 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.3691022262
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.3883233944
Short name T643
Test name
Test status
Simulation time 203212025 ps
CPU time 2.65 seconds
Started Jul 23 07:10:42 PM PDT 24
Finished Jul 23 07:10:55 PM PDT 24
Peak memory 220796 kb
Host smart-eb8616f3-e021-461b-9942-1fc591f882e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883233944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.3883233944
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.4284326563
Short name T935
Test name
Test status
Simulation time 43732094 ps
CPU time 1.58 seconds
Started Jul 23 07:10:47 PM PDT 24
Finished Jul 23 07:11:01 PM PDT 24
Peak memory 219020 kb
Host smart-c4bcc85e-03b0-4599-a353-cb03c1731135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284326563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.4284326563
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.3626916287
Short name T873
Test name
Test status
Simulation time 74956119 ps
CPU time 1.23 seconds
Started Jul 23 07:10:47 PM PDT 24
Finished Jul 23 07:11:00 PM PDT 24
Peak memory 218800 kb
Host smart-e4c4fee4-761a-4a46-92bb-d39bf14617f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626916287 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.3626916287
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.3445342652
Short name T804
Test name
Test status
Simulation time 83455619 ps
CPU time 1.4 seconds
Started Jul 23 07:10:48 PM PDT 24
Finished Jul 23 07:11:00 PM PDT 24
Peak memory 220280 kb
Host smart-7bf2d07b-6e7f-4609-9ec5-d7346f82ce9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445342652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3445342652
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.1266651932
Short name T844
Test name
Test status
Simulation time 87604745 ps
CPU time 1.17 seconds
Started Jul 23 07:10:43 PM PDT 24
Finished Jul 23 07:10:54 PM PDT 24
Peak memory 216052 kb
Host smart-204f4aa7-a079-4718-85bb-afd813bb1657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266651932 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.1266651932
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.2354146510
Short name T507
Test name
Test status
Simulation time 31962295 ps
CPU time 1.22 seconds
Started Jul 23 07:10:44 PM PDT 24
Finished Jul 23 07:10:55 PM PDT 24
Peak memory 218760 kb
Host smart-4d2ddd98-3f12-4003-b521-66e3fa591db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354146510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.2354146510
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.1718375337
Short name T459
Test name
Test status
Simulation time 78141131 ps
CPU time 1.1 seconds
Started Jul 23 07:10:43 PM PDT 24
Finished Jul 23 07:10:55 PM PDT 24
Peak memory 219288 kb
Host smart-575f375e-8b5e-4f93-a54d-6add5550c8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718375337 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.1718375337
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.2876646794
Short name T686
Test name
Test status
Simulation time 137082135 ps
CPU time 1.29 seconds
Started Jul 23 07:10:41 PM PDT 24
Finished Jul 23 07:10:52 PM PDT 24
Peak memory 220028 kb
Host smart-7f231c1a-a8d7-4394-8b8c-8b5e6a673d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876646794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.2876646794
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.1792918450
Short name T861
Test name
Test status
Simulation time 35986409 ps
CPU time 1.24 seconds
Started Jul 23 07:09:12 PM PDT 24
Finished Jul 23 07:09:18 PM PDT 24
Peak memory 219856 kb
Host smart-9ed13530-0851-4f7e-b035-2fa38571ab58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792918450 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.1792918450
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.3980231072
Short name T438
Test name
Test status
Simulation time 111903269 ps
CPU time 0.99 seconds
Started Jul 23 07:09:13 PM PDT 24
Finished Jul 23 07:09:19 PM PDT 24
Peak memory 215200 kb
Host smart-449ae058-2c33-4782-af1a-836b29414147
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980231072 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3980231072
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.3765227469
Short name T596
Test name
Test status
Simulation time 17712274 ps
CPU time 0.85 seconds
Started Jul 23 07:09:10 PM PDT 24
Finished Jul 23 07:09:13 PM PDT 24
Peak memory 215792 kb
Host smart-ff090daf-7046-495b-90ae-f057cdc9c3d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765227469 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.3765227469
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_err.2575396043
Short name T411
Test name
Test status
Simulation time 21420913 ps
CPU time 0.96 seconds
Started Jul 23 07:09:15 PM PDT 24
Finished Jul 23 07:09:23 PM PDT 24
Peak memory 218452 kb
Host smart-241a410e-76f8-4f34-a47f-83dc7d97e4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575396043 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.2575396043
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.4174686402
Short name T517
Test name
Test status
Simulation time 86439262 ps
CPU time 1.47 seconds
Started Jul 23 07:09:10 PM PDT 24
Finished Jul 23 07:09:14 PM PDT 24
Peak memory 219424 kb
Host smart-de50e12c-87c7-4eff-8251-47458f6c037a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174686402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.4174686402
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_smoke.1811866653
Short name T838
Test name
Test status
Simulation time 18904350 ps
CPU time 0.97 seconds
Started Jul 23 07:09:12 PM PDT 24
Finished Jul 23 07:09:17 PM PDT 24
Peak memory 215528 kb
Host smart-473ee235-dfa3-4414-85c5-27dfd479f14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811866653 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.1811866653
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.2561256548
Short name T230
Test name
Test status
Simulation time 103617950290 ps
CPU time 611.09 seconds
Started Jul 23 07:09:10 PM PDT 24
Finished Jul 23 07:19:23 PM PDT 24
Peak memory 224104 kb
Host smart-5579c0d7-e51e-4f47-8703-784aa5035537
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561256548 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.2561256548
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.1165375590
Short name T125
Test name
Test status
Simulation time 25771701 ps
CPU time 1.24 seconds
Started Jul 23 07:10:41 PM PDT 24
Finished Jul 23 07:10:52 PM PDT 24
Peak memory 219992 kb
Host smart-f331efb0-d6b4-44db-bcfa-6ef17234aad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165375590 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.1165375590
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.3037175994
Short name T383
Test name
Test status
Simulation time 52155524 ps
CPU time 1.93 seconds
Started Jul 23 07:10:38 PM PDT 24
Finished Jul 23 07:10:49 PM PDT 24
Peak memory 215608 kb
Host smart-4062b6d5-61ff-4b60-821f-4bb0d6d5ceb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037175994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3037175994
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.3108794208
Short name T105
Test name
Test status
Simulation time 31159415 ps
CPU time 1.26 seconds
Started Jul 23 07:10:40 PM PDT 24
Finished Jul 23 07:10:52 PM PDT 24
Peak memory 220116 kb
Host smart-6222a0a2-e12f-42e8-aeb2-0a78bda04404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108794208 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.3108794208
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.235461048
Short name T86
Test name
Test status
Simulation time 66629169 ps
CPU time 1.25 seconds
Started Jul 23 07:10:41 PM PDT 24
Finished Jul 23 07:10:53 PM PDT 24
Peak memory 219040 kb
Host smart-9515315f-e851-430b-8b67-7476c43174d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235461048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.235461048
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.669378549
Short name T620
Test name
Test status
Simulation time 61545923 ps
CPU time 1.26 seconds
Started Jul 23 07:10:43 PM PDT 24
Finished Jul 23 07:10:55 PM PDT 24
Peak memory 219648 kb
Host smart-924efb19-ebf1-4465-aeea-e9590a6d1693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669378549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.669378549
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.2198993442
Short name T386
Test name
Test status
Simulation time 22903618 ps
CPU time 1.14 seconds
Started Jul 23 07:10:45 PM PDT 24
Finished Jul 23 07:10:57 PM PDT 24
Peak memory 219088 kb
Host smart-71ac3a7f-4bc3-4c73-a9fe-3b9713d4f66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198993442 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.2198993442
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/124.edn_alert.1991704173
Short name T25
Test name
Test status
Simulation time 94360617 ps
CPU time 1.15 seconds
Started Jul 23 07:10:43 PM PDT 24
Finished Jul 23 07:10:54 PM PDT 24
Peak memory 220140 kb
Host smart-25ab3f95-7fbd-4dcd-8012-e9c6b775f203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991704173 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.1991704173
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/125.edn_alert.1427478116
Short name T903
Test name
Test status
Simulation time 32204315 ps
CPU time 1.11 seconds
Started Jul 23 07:10:44 PM PDT 24
Finished Jul 23 07:10:55 PM PDT 24
Peak memory 218992 kb
Host smart-98dd6d76-6645-4dea-ac74-6a50f63fc524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427478116 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.1427478116
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.312030183
Short name T361
Test name
Test status
Simulation time 83165892 ps
CPU time 1.17 seconds
Started Jul 23 07:10:43 PM PDT 24
Finished Jul 23 07:10:55 PM PDT 24
Peak memory 217584 kb
Host smart-43018576-4a3e-471e-bfa2-089a47a81c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312030183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.312030183
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.129699805
Short name T803
Test name
Test status
Simulation time 77337914 ps
CPU time 1.02 seconds
Started Jul 23 07:10:41 PM PDT 24
Finished Jul 23 07:10:52 PM PDT 24
Peak memory 217584 kb
Host smart-ef91ef6b-bdfa-4a67-8cd4-c9b168dc76b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129699805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.129699805
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.1037354016
Short name T75
Test name
Test status
Simulation time 32876489 ps
CPU time 1.22 seconds
Started Jul 23 07:10:39 PM PDT 24
Finished Jul 23 07:10:51 PM PDT 24
Peak memory 221588 kb
Host smart-74a4ab9d-530e-4ed2-a5aa-c97de0195331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037354016 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.1037354016
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.2046530210
Short name T916
Test name
Test status
Simulation time 32388033 ps
CPU time 1.26 seconds
Started Jul 23 07:10:44 PM PDT 24
Finished Jul 23 07:10:56 PM PDT 24
Peak memory 217660 kb
Host smart-70338fbb-7aa6-4805-909f-81803a3f87a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046530210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.2046530210
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.3030017966
Short name T399
Test name
Test status
Simulation time 30027773 ps
CPU time 1.28 seconds
Started Jul 23 07:10:54 PM PDT 24
Finished Jul 23 07:11:06 PM PDT 24
Peak memory 221088 kb
Host smart-e4cdde9a-2738-4c1c-9c06-182d8ec23bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030017966 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.3030017966
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.1240187495
Short name T340
Test name
Test status
Simulation time 29747329 ps
CPU time 1.3 seconds
Started Jul 23 07:10:42 PM PDT 24
Finished Jul 23 07:10:54 PM PDT 24
Peak memory 220168 kb
Host smart-5477c585-15bc-490c-b78e-7fbe142089e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240187495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.1240187495
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert_test.1083493916
Short name T891
Test name
Test status
Simulation time 27781566 ps
CPU time 0.96 seconds
Started Jul 23 07:09:17 PM PDT 24
Finished Jul 23 07:09:24 PM PDT 24
Peak memory 215436 kb
Host smart-3ede6d3c-ad37-4770-b170-62fb7d0fa6f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083493916 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.1083493916
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_err.1641463802
Short name T591
Test name
Test status
Simulation time 36445323 ps
CPU time 1.24 seconds
Started Jul 23 07:09:12 PM PDT 24
Finished Jul 23 07:09:18 PM PDT 24
Peak memory 225848 kb
Host smart-9d620893-67fd-4f54-a0be-7df32eb0f8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641463802 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.1641463802
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.193622664
Short name T728
Test name
Test status
Simulation time 66661186 ps
CPU time 1.37 seconds
Started Jul 23 07:09:10 PM PDT 24
Finished Jul 23 07:09:15 PM PDT 24
Peak memory 219136 kb
Host smart-3ab35f68-4af5-4b92-9f5d-cce9c7d3a19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193622664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.193622664
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.2653230223
Short name T812
Test name
Test status
Simulation time 47727877 ps
CPU time 0.94 seconds
Started Jul 23 07:09:10 PM PDT 24
Finished Jul 23 07:09:14 PM PDT 24
Peak memory 215484 kb
Host smart-7351652e-0a9c-4c9b-852e-c7afe16fc916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653230223 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.2653230223
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.947798927
Short name T906
Test name
Test status
Simulation time 16619259 ps
CPU time 0.94 seconds
Started Jul 23 07:09:10 PM PDT 24
Finished Jul 23 07:09:13 PM PDT 24
Peak memory 215636 kb
Host smart-303bfd50-5db1-4878-af10-0f6b02b4d1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947798927 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.947798927
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.2371172718
Short name T796
Test name
Test status
Simulation time 364286799 ps
CPU time 7.18 seconds
Started Jul 23 07:09:09 PM PDT 24
Finished Jul 23 07:09:18 PM PDT 24
Peak memory 217440 kb
Host smart-9caab31d-9929-45df-af90-0414659e9fec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371172718 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.2371172718
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2429730407
Short name T220
Test name
Test status
Simulation time 26652243545 ps
CPU time 553.25 seconds
Started Jul 23 07:09:13 PM PDT 24
Finished Jul 23 07:18:32 PM PDT 24
Peak memory 218540 kb
Host smart-e9598ed5-310c-4891-8364-6c21e25bb1b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429730407 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.2429730407
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.3178353159
Short name T428
Test name
Test status
Simulation time 489774391 ps
CPU time 3.92 seconds
Started Jul 23 07:10:48 PM PDT 24
Finished Jul 23 07:11:03 PM PDT 24
Peak memory 217784 kb
Host smart-0111b9b5-aaee-404d-a2da-aed23a1e0a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178353159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.3178353159
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.3694192190
Short name T267
Test name
Test status
Simulation time 50513237 ps
CPU time 1.2 seconds
Started Jul 23 07:10:52 PM PDT 24
Finished Jul 23 07:11:03 PM PDT 24
Peak memory 218904 kb
Host smart-2118848f-4de4-46bc-a4dd-a8ec58c21cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694192190 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.3694192190
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.58746589
Short name T995
Test name
Test status
Simulation time 113725745 ps
CPU time 1.55 seconds
Started Jul 23 07:10:58 PM PDT 24
Finished Jul 23 07:11:10 PM PDT 24
Peak memory 219132 kb
Host smart-3f0b445f-79e8-4d39-aa23-11aacd97c1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58746589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.58746589
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.1715350154
Short name T535
Test name
Test status
Simulation time 58495334 ps
CPU time 1.22 seconds
Started Jul 23 07:10:48 PM PDT 24
Finished Jul 23 07:11:01 PM PDT 24
Peak memory 219520 kb
Host smart-cccc7f4e-a190-4355-bb46-fcef867efc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715350154 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.1715350154
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.290991549
Short name T292
Test name
Test status
Simulation time 114121720 ps
CPU time 1.15 seconds
Started Jul 23 07:10:48 PM PDT 24
Finished Jul 23 07:11:00 PM PDT 24
Peak memory 220184 kb
Host smart-d44a85b6-9c0e-4265-b08e-c3226ba97f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290991549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.290991549
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.3363502312
Short name T462
Test name
Test status
Simulation time 44299293 ps
CPU time 1.13 seconds
Started Jul 23 07:10:52 PM PDT 24
Finished Jul 23 07:11:03 PM PDT 24
Peak memory 219916 kb
Host smart-3a92ea2f-62f6-4825-9706-cfd6902df3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363502312 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.3363502312
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.483005247
Short name T234
Test name
Test status
Simulation time 84624791 ps
CPU time 0.95 seconds
Started Jul 23 07:10:46 PM PDT 24
Finished Jul 23 07:10:58 PM PDT 24
Peak memory 215552 kb
Host smart-52da7344-3b8c-4a86-8326-56df61cb2d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483005247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.483005247
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.2135611562
Short name T358
Test name
Test status
Simulation time 23072183 ps
CPU time 1.16 seconds
Started Jul 23 07:10:53 PM PDT 24
Finished Jul 23 07:11:04 PM PDT 24
Peak memory 221504 kb
Host smart-cfd1f967-253e-428a-baab-e66cb3dc5c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135611562 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.2135611562
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.2076944721
Short name T345
Test name
Test status
Simulation time 51711799 ps
CPU time 1.56 seconds
Started Jul 23 07:10:48 PM PDT 24
Finished Jul 23 07:11:01 PM PDT 24
Peak memory 218788 kb
Host smart-52cbaf00-d334-4d48-be7f-e53aadbc4604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076944721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2076944721
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.3168429758
Short name T398
Test name
Test status
Simulation time 47656312 ps
CPU time 1.26 seconds
Started Jul 23 07:10:51 PM PDT 24
Finished Jul 23 07:11:02 PM PDT 24
Peak memory 219072 kb
Host smart-96b24127-07ed-438a-bca0-f696f47a9638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168429758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.3168429758
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.803472582
Short name T318
Test name
Test status
Simulation time 280845442 ps
CPU time 1.36 seconds
Started Jul 23 07:10:47 PM PDT 24
Finished Jul 23 07:10:59 PM PDT 24
Peak memory 220740 kb
Host smart-d4ab3098-2a1f-4da4-8697-37f211a92ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803472582 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.803472582
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.1837402661
Short name T590
Test name
Test status
Simulation time 46678855 ps
CPU time 1.58 seconds
Started Jul 23 07:10:46 PM PDT 24
Finished Jul 23 07:10:58 PM PDT 24
Peak memory 218888 kb
Host smart-bd176f48-bd91-4e0f-9030-b2c6b9c96121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837402661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.1837402661
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.1463955748
Short name T168
Test name
Test status
Simulation time 25452243 ps
CPU time 1.2 seconds
Started Jul 23 07:10:46 PM PDT 24
Finished Jul 23 07:10:58 PM PDT 24
Peak memory 220068 kb
Host smart-0b6e3483-8ea2-40c4-8c15-78604c95f898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463955748 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.1463955748
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.777005164
Short name T525
Test name
Test status
Simulation time 33205010 ps
CPU time 1.35 seconds
Started Jul 23 07:10:47 PM PDT 24
Finished Jul 23 07:10:59 PM PDT 24
Peak memory 217764 kb
Host smart-46bee4fd-d279-499e-b7a6-7379ce2f82d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777005164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.777005164
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.175419201
Short name T621
Test name
Test status
Simulation time 47777254 ps
CPU time 1.36 seconds
Started Jul 23 07:10:58 PM PDT 24
Finished Jul 23 07:11:09 PM PDT 24
Peak memory 219820 kb
Host smart-a5007e75-dd75-4bff-9e65-345dc146d4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175419201 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.175419201
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.2843974779
Short name T731
Test name
Test status
Simulation time 242485136 ps
CPU time 1.8 seconds
Started Jul 23 07:10:48 PM PDT 24
Finished Jul 23 07:11:01 PM PDT 24
Peak memory 219264 kb
Host smart-3cd5a4b3-81bb-4819-b303-412fb8c03e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843974779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.2843974779
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.491572342
Short name T636
Test name
Test status
Simulation time 30638567 ps
CPU time 1.23 seconds
Started Jul 23 07:10:48 PM PDT 24
Finished Jul 23 07:11:01 PM PDT 24
Peak memory 221304 kb
Host smart-2889f2f8-6c5f-47c5-a81c-dc441fe975c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491572342 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.491572342
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.145916422
Short name T943
Test name
Test status
Simulation time 221439427 ps
CPU time 3.04 seconds
Started Jul 23 07:10:45 PM PDT 24
Finished Jul 23 07:11:00 PM PDT 24
Peak memory 220468 kb
Host smart-cf88f2f5-0cdb-4878-8d4c-f35e89a11bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145916422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.145916422
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.1589431531
Short name T756
Test name
Test status
Simulation time 69787038 ps
CPU time 1.09 seconds
Started Jul 23 07:09:10 PM PDT 24
Finished Jul 23 07:09:12 PM PDT 24
Peak memory 219132 kb
Host smart-d05d733b-f0e8-4ce1-92f2-a053b363b1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589431531 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.1589431531
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.1729173026
Short name T73
Test name
Test status
Simulation time 25625883 ps
CPU time 0.93 seconds
Started Jul 23 07:09:10 PM PDT 24
Finished Jul 23 07:09:13 PM PDT 24
Peak memory 215212 kb
Host smart-eb6a3397-5f1e-4b0d-9e91-acefa03e315a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729173026 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1729173026
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.1757957480
Short name T563
Test name
Test status
Simulation time 43902973 ps
CPU time 0.81 seconds
Started Jul 23 07:09:11 PM PDT 24
Finished Jul 23 07:09:16 PM PDT 24
Peak memory 216532 kb
Host smart-bf42b229-7ddf-43d6-82a2-10a51e8a864d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757957480 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1757957480
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.3415420862
Short name T74
Test name
Test status
Simulation time 28957070 ps
CPU time 1.08 seconds
Started Jul 23 07:09:10 PM PDT 24
Finished Jul 23 07:09:12 PM PDT 24
Peak memory 218808 kb
Host smart-085c049f-4a4e-48fd-b39c-802b7e0e4ca4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415420862 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.3415420862
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.3347433125
Short name T961
Test name
Test status
Simulation time 66421533 ps
CPU time 1.02 seconds
Started Jul 23 07:09:10 PM PDT 24
Finished Jul 23 07:09:12 PM PDT 24
Peak memory 219980 kb
Host smart-a70592e1-864e-4db4-a1d7-64f93805da88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347433125 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.3347433125
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.3865638414
Short name T91
Test name
Test status
Simulation time 43295404 ps
CPU time 1.55 seconds
Started Jul 23 07:09:10 PM PDT 24
Finished Jul 23 07:09:15 PM PDT 24
Peak memory 218912 kb
Host smart-bf123c46-f08d-4f53-b6f7-d49ac9e4cc23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865638414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3865638414
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.969063881
Short name T625
Test name
Test status
Simulation time 26026901 ps
CPU time 0.95 seconds
Started Jul 23 07:09:13 PM PDT 24
Finished Jul 23 07:09:19 PM PDT 24
Peak memory 215904 kb
Host smart-0493bfbb-4fe9-4524-91ae-0cafd786eb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969063881 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.969063881
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.4165694774
Short name T580
Test name
Test status
Simulation time 24428985 ps
CPU time 0.98 seconds
Started Jul 23 07:09:14 PM PDT 24
Finished Jul 23 07:09:21 PM PDT 24
Peak memory 215804 kb
Host smart-e7a85269-935e-46ac-9c6c-d6747599c82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165694774 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.4165694774
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.1952860871
Short name T64
Test name
Test status
Simulation time 397764934 ps
CPU time 7.44 seconds
Started Jul 23 07:09:13 PM PDT 24
Finished Jul 23 07:09:26 PM PDT 24
Peak memory 217508 kb
Host smart-b9d92e23-68da-45af-ae5d-6001283103a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952860871 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1952860871
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.3304636414
Short name T38
Test name
Test status
Simulation time 700291791132 ps
CPU time 1325.86 seconds
Started Jul 23 07:09:11 PM PDT 24
Finished Jul 23 07:31:21 PM PDT 24
Peak memory 224028 kb
Host smart-709b9378-e4b1-481d-9d3e-388a43bdb402
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304636414 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.3304636414
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.2068452142
Short name T939
Test name
Test status
Simulation time 23286975 ps
CPU time 1.12 seconds
Started Jul 23 07:10:49 PM PDT 24
Finished Jul 23 07:11:01 PM PDT 24
Peak memory 220096 kb
Host smart-cbba825c-e371-437e-b0cc-1f4ce6c98b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068452142 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.2068452142
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.3000777154
Short name T832
Test name
Test status
Simulation time 48537537 ps
CPU time 1.52 seconds
Started Jul 23 07:10:48 PM PDT 24
Finished Jul 23 07:11:01 PM PDT 24
Peak memory 218804 kb
Host smart-ec230374-d962-4cb9-a3d4-e4e2cf53e102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000777154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.3000777154
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.1139169092
Short name T859
Test name
Test status
Simulation time 27704710 ps
CPU time 1.21 seconds
Started Jul 23 07:10:52 PM PDT 24
Finished Jul 23 07:11:03 PM PDT 24
Peak memory 221016 kb
Host smart-1f804087-21da-4670-88c1-f6ec3b3137fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139169092 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.1139169092
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.1578956076
Short name T826
Test name
Test status
Simulation time 271283373 ps
CPU time 2.51 seconds
Started Jul 23 07:10:57 PM PDT 24
Finished Jul 23 07:11:09 PM PDT 24
Peak memory 219748 kb
Host smart-de0dec60-3682-4e95-93cf-bd5c35907f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578956076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1578956076
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.2530689512
Short name T136
Test name
Test status
Simulation time 160319230 ps
CPU time 1.24 seconds
Started Jul 23 07:10:52 PM PDT 24
Finished Jul 23 07:11:04 PM PDT 24
Peak memory 220368 kb
Host smart-d77c1a97-d64a-4501-9c45-54e7f2d9489a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530689512 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.2530689512
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.740459907
Short name T59
Test name
Test status
Simulation time 51808430 ps
CPU time 1.73 seconds
Started Jul 23 07:10:57 PM PDT 24
Finished Jul 23 07:11:09 PM PDT 24
Peak memory 218776 kb
Host smart-d7a9967f-56ad-45e4-b3ec-f91718a2fa33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740459907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.740459907
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.1789180012
Short name T496
Test name
Test status
Simulation time 21675710 ps
CPU time 1.15 seconds
Started Jul 23 07:10:46 PM PDT 24
Finished Jul 23 07:10:58 PM PDT 24
Peak memory 220288 kb
Host smart-56a7eea5-a25f-41b2-81c1-4c8a3dbe1f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789180012 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.1789180012
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/144.edn_alert.3966795262
Short name T845
Test name
Test status
Simulation time 27008220 ps
CPU time 1.2 seconds
Started Jul 23 07:10:45 PM PDT 24
Finished Jul 23 07:10:58 PM PDT 24
Peak memory 221312 kb
Host smart-e74c34a3-c13f-487c-ad5c-dc076583a2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966795262 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.3966795262
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.1620924158
Short name T13
Test name
Test status
Simulation time 50575796 ps
CPU time 1.47 seconds
Started Jul 23 07:10:53 PM PDT 24
Finished Jul 23 07:11:04 PM PDT 24
Peak memory 220088 kb
Host smart-561d7b96-3ecf-4742-b44c-3628f684e804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620924158 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.1620924158
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.1998846359
Short name T333
Test name
Test status
Simulation time 34840278 ps
CPU time 1.05 seconds
Started Jul 23 07:10:48 PM PDT 24
Finished Jul 23 07:11:00 PM PDT 24
Peak memory 220224 kb
Host smart-189f4990-f23b-4e29-843e-c719f5b15929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998846359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.1998846359
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.2481031948
Short name T132
Test name
Test status
Simulation time 53445854 ps
CPU time 1.33 seconds
Started Jul 23 07:10:56 PM PDT 24
Finished Jul 23 07:11:08 PM PDT 24
Peak memory 220196 kb
Host smart-112b716e-56fa-479a-a7dd-d1a4b85fbf65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481031948 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.2481031948
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.1680813427
Short name T646
Test name
Test status
Simulation time 51948023 ps
CPU time 1.2 seconds
Started Jul 23 07:10:48 PM PDT 24
Finished Jul 23 07:11:01 PM PDT 24
Peak memory 217628 kb
Host smart-17552aa3-804d-4485-b946-094756d8c621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680813427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1680813427
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.3882447056
Short name T798
Test name
Test status
Simulation time 32576402 ps
CPU time 1.5 seconds
Started Jul 23 07:10:58 PM PDT 24
Finished Jul 23 07:11:10 PM PDT 24
Peak memory 217628 kb
Host smart-b9ff5c77-e159-4cff-99cb-563afe3d18a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882447056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3882447056
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.2155508294
Short name T955
Test name
Test status
Simulation time 42140851 ps
CPU time 1.07 seconds
Started Jul 23 07:10:53 PM PDT 24
Finished Jul 23 07:11:04 PM PDT 24
Peak memory 216060 kb
Host smart-dea4aebe-5005-4f95-b910-eb960d408e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155508294 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.2155508294
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.185656092
Short name T957
Test name
Test status
Simulation time 24653159 ps
CPU time 1.16 seconds
Started Jul 23 07:10:48 PM PDT 24
Finished Jul 23 07:11:01 PM PDT 24
Peak memory 217600 kb
Host smart-7556542e-83d9-4c97-9b74-3e855e3d8d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185656092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.185656092
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.1569405759
Short name T18
Test name
Test status
Simulation time 21722650 ps
CPU time 1.21 seconds
Started Jul 23 07:10:58 PM PDT 24
Finished Jul 23 07:11:09 PM PDT 24
Peak memory 220284 kb
Host smart-d3e68595-dead-404d-8ef4-410a3c663d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569405759 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.1569405759
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.311775725
Short name T648
Test name
Test status
Simulation time 77112332 ps
CPU time 1.13 seconds
Started Jul 23 07:10:46 PM PDT 24
Finished Jul 23 07:10:58 PM PDT 24
Peak memory 217876 kb
Host smart-0182caa5-52ec-45c1-b340-8b95968e6b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311775725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.311775725
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.3542974834
Short name T703
Test name
Test status
Simulation time 80002342 ps
CPU time 1.24 seconds
Started Jul 23 07:09:11 PM PDT 24
Finished Jul 23 07:09:15 PM PDT 24
Peak memory 218976 kb
Host smart-2487a056-d0b7-4773-b577-2d5e11ecd60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542974834 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3542974834
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.2153273898
Short name T681
Test name
Test status
Simulation time 11005059 ps
CPU time 0.91 seconds
Started Jul 23 07:09:11 PM PDT 24
Finished Jul 23 07:09:16 PM PDT 24
Peak memory 207100 kb
Host smart-fd026f87-abfd-4717-aa47-002247abcfdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153273898 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2153273898
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.957696920
Short name T212
Test name
Test status
Simulation time 31419354 ps
CPU time 0.83 seconds
Started Jul 23 07:09:09 PM PDT 24
Finished Jul 23 07:09:11 PM PDT 24
Peak memory 216580 kb
Host smart-4fe8eb27-8feb-4557-a83d-685b4b98921c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957696920 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.957696920
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.2513446864
Short name T140
Test name
Test status
Simulation time 95143536 ps
CPU time 1.05 seconds
Started Jul 23 07:09:15 PM PDT 24
Finished Jul 23 07:09:23 PM PDT 24
Peak memory 218784 kb
Host smart-9593d298-f4ef-484b-b8e2-a8a2d3f7ed91
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513446864 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.2513446864
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.4177201053
Short name T120
Test name
Test status
Simulation time 46631953 ps
CPU time 0.99 seconds
Started Jul 23 07:09:11 PM PDT 24
Finished Jul 23 07:09:15 PM PDT 24
Peak memory 219972 kb
Host smart-b593c2cf-86cf-4cde-a3c7-e00cb16692ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177201053 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.4177201053
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.1346061516
Short name T666
Test name
Test status
Simulation time 49196264 ps
CPU time 1.75 seconds
Started Jul 23 07:09:10 PM PDT 24
Finished Jul 23 07:09:14 PM PDT 24
Peak memory 218916 kb
Host smart-d48cd788-43fe-4b82-84e0-af4b682c6c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346061516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1346061516
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.1473859697
Short name T996
Test name
Test status
Simulation time 24953091 ps
CPU time 1 seconds
Started Jul 23 07:09:11 PM PDT 24
Finished Jul 23 07:09:16 PM PDT 24
Peak memory 215692 kb
Host smart-e0064e8b-c192-4ff5-ad4c-957f0c3d3914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473859697 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.1473859697
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.1863233495
Short name T664
Test name
Test status
Simulation time 44173360 ps
CPU time 0.95 seconds
Started Jul 23 07:09:15 PM PDT 24
Finished Jul 23 07:09:22 PM PDT 24
Peak memory 215624 kb
Host smart-1c5627a5-eabd-415c-bf35-c5a6cb16d54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863233495 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.1863233495
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.4192074750
Short name T444
Test name
Test status
Simulation time 1401084431 ps
CPU time 2.61 seconds
Started Jul 23 07:09:11 PM PDT 24
Finished Jul 23 07:09:17 PM PDT 24
Peak memory 217672 kb
Host smart-4b67a3bb-2245-4d22-bf96-76ff58d30e28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192074750 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.4192074750
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.1362580328
Short name T219
Test name
Test status
Simulation time 43249306266 ps
CPU time 1077.98 seconds
Started Jul 23 07:09:11 PM PDT 24
Finished Jul 23 07:27:13 PM PDT 24
Peak memory 224120 kb
Host smart-6a833fd7-50d0-4488-a045-ff9641d2d867
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362580328 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.1362580328
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.3450129991
Short name T30
Test name
Test status
Simulation time 48869995 ps
CPU time 1.57 seconds
Started Jul 23 07:10:48 PM PDT 24
Finished Jul 23 07:11:01 PM PDT 24
Peak memory 219024 kb
Host smart-fd3062c8-4b79-443a-9509-7a6065429165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450129991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3450129991
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.1568419929
Short name T899
Test name
Test status
Simulation time 192704328 ps
CPU time 1.36 seconds
Started Jul 23 07:10:45 PM PDT 24
Finished Jul 23 07:10:58 PM PDT 24
Peak memory 219008 kb
Host smart-694db591-7e8e-43ce-95ea-cc647455baf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568419929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.1568419929
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.2361960033
Short name T546
Test name
Test status
Simulation time 21896184 ps
CPU time 1.14 seconds
Started Jul 23 07:10:56 PM PDT 24
Finished Jul 23 07:11:07 PM PDT 24
Peak memory 219980 kb
Host smart-c2490082-74ca-4439-95a6-020eb926f699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361960033 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.2361960033
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.3653329092
Short name T720
Test name
Test status
Simulation time 62256317 ps
CPU time 2.23 seconds
Started Jul 23 07:10:54 PM PDT 24
Finished Jul 23 07:11:06 PM PDT 24
Peak memory 219348 kb
Host smart-e2557b2b-fddc-423d-a5cb-898be86bba52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653329092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.3653329092
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.2160973891
Short name T871
Test name
Test status
Simulation time 75747290 ps
CPU time 1.05 seconds
Started Jul 23 07:10:54 PM PDT 24
Finished Jul 23 07:11:05 PM PDT 24
Peak memory 219236 kb
Host smart-c0bfda14-eb68-4505-abac-a731d22c8790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160973891 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.2160973891
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.182798171
Short name T469
Test name
Test status
Simulation time 72796000 ps
CPU time 1.03 seconds
Started Jul 23 07:10:55 PM PDT 24
Finished Jul 23 07:11:07 PM PDT 24
Peak memory 219120 kb
Host smart-5f7f8c4c-d073-4dee-a1c7-530c0c46eae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182798171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.182798171
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.1437862144
Short name T552
Test name
Test status
Simulation time 182672555 ps
CPU time 1.33 seconds
Started Jul 23 07:10:56 PM PDT 24
Finished Jul 23 07:11:08 PM PDT 24
Peak memory 216080 kb
Host smart-78b4a85e-03a9-4883-9936-785c1f96b703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437862144 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.1437862144
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.1071690829
Short name T897
Test name
Test status
Simulation time 76475549 ps
CPU time 1.63 seconds
Started Jul 23 07:10:54 PM PDT 24
Finished Jul 23 07:11:05 PM PDT 24
Peak memory 218884 kb
Host smart-87daba02-b5a8-4736-895b-e61b9a954fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071690829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1071690829
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.2593949722
Short name T849
Test name
Test status
Simulation time 296157361 ps
CPU time 1.26 seconds
Started Jul 23 07:10:52 PM PDT 24
Finished Jul 23 07:11:03 PM PDT 24
Peak memory 216080 kb
Host smart-0fac881b-509b-4724-93c0-4fcc4968d05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593949722 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.2593949722
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.3488671497
Short name T898
Test name
Test status
Simulation time 41895184 ps
CPU time 1.12 seconds
Started Jul 23 07:10:56 PM PDT 24
Finished Jul 23 07:11:07 PM PDT 24
Peak memory 220012 kb
Host smart-7ed52d5e-37c2-4db4-9dcd-1a8409581f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488671497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3488671497
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.3995450819
Short name T808
Test name
Test status
Simulation time 26791652 ps
CPU time 1.2 seconds
Started Jul 23 07:10:52 PM PDT 24
Finished Jul 23 07:11:03 PM PDT 24
Peak memory 218960 kb
Host smart-e27162c1-2e16-481b-8f68-232fe03c5ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995450819 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.3995450819
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.3524558128
Short name T70
Test name
Test status
Simulation time 142951187 ps
CPU time 1.25 seconds
Started Jul 23 07:10:53 PM PDT 24
Finished Jul 23 07:11:04 PM PDT 24
Peak memory 217740 kb
Host smart-2c3aabbb-bb32-4853-b669-6cf43feb8e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524558128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3524558128
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.3109853134
Short name T319
Test name
Test status
Simulation time 68771630 ps
CPU time 1.04 seconds
Started Jul 23 07:10:54 PM PDT 24
Finished Jul 23 07:11:05 PM PDT 24
Peak memory 219068 kb
Host smart-a5c34e94-51bc-4ba7-b40c-1e7b6feca7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109853134 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.3109853134
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.130653800
Short name T764
Test name
Test status
Simulation time 48486088 ps
CPU time 1.3 seconds
Started Jul 23 07:10:54 PM PDT 24
Finished Jul 23 07:11:04 PM PDT 24
Peak memory 219028 kb
Host smart-5c5dde1b-fe87-46e9-928e-d9b48ff5618f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130653800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.130653800
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.469470226
Short name T639
Test name
Test status
Simulation time 28772272 ps
CPU time 1.23 seconds
Started Jul 23 07:10:52 PM PDT 24
Finished Jul 23 07:11:03 PM PDT 24
Peak memory 216036 kb
Host smart-094c7bd3-eab3-4603-a74c-4f618adeef11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469470226 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.469470226
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.721670269
Short name T779
Test name
Test status
Simulation time 196948208 ps
CPU time 1.4 seconds
Started Jul 23 07:10:53 PM PDT 24
Finished Jul 23 07:11:04 PM PDT 24
Peak memory 217720 kb
Host smart-880f8546-e0b2-4ec9-afdc-e7ff0a946bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721670269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.721670269
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.1418157667
Short name T65
Test name
Test status
Simulation time 79418467 ps
CPU time 1.16 seconds
Started Jul 23 07:10:58 PM PDT 24
Finished Jul 23 07:11:09 PM PDT 24
Peak memory 221188 kb
Host smart-30bd158a-bc9a-4725-808c-ed914592d8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418157667 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.1418157667
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.3077758989
Short name T921
Test name
Test status
Simulation time 41755823 ps
CPU time 1.63 seconds
Started Jul 23 07:10:54 PM PDT 24
Finished Jul 23 07:11:05 PM PDT 24
Peak memory 218928 kb
Host smart-1cf0c1e2-5d44-4115-8d8f-58ad32f80564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077758989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.3077758989
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.3388199620
Short name T626
Test name
Test status
Simulation time 54523220 ps
CPU time 1.35 seconds
Started Jul 23 07:09:13 PM PDT 24
Finished Jul 23 07:09:21 PM PDT 24
Peak memory 216032 kb
Host smart-96a307fa-fc27-4524-a3c7-5347ce238705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388199620 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3388199620
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.504843413
Short name T968
Test name
Test status
Simulation time 18005311 ps
CPU time 0.81 seconds
Started Jul 23 07:09:38 PM PDT 24
Finished Jul 23 07:09:45 PM PDT 24
Peak memory 207088 kb
Host smart-f8c74924-df6e-4a01-8e4f-569093b0593a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504843413 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.504843413
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.2760737572
Short name T162
Test name
Test status
Simulation time 58964354 ps
CPU time 0.83 seconds
Started Jul 23 07:09:37 PM PDT 24
Finished Jul 23 07:09:44 PM PDT 24
Peak memory 215816 kb
Host smart-9691764f-2272-4a01-88fb-58094c2af8f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760737572 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2760737572
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2945655895
Short name T123
Test name
Test status
Simulation time 96382220 ps
CPU time 1.19 seconds
Started Jul 23 07:09:37 PM PDT 24
Finished Jul 23 07:09:44 PM PDT 24
Peak memory 217380 kb
Host smart-0dc3d95e-3f6c-4b3e-aff2-6bf077cdeb5d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945655895 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2945655895
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.1814453527
Short name T143
Test name
Test status
Simulation time 32575011 ps
CPU time 0.89 seconds
Started Jul 23 07:09:39 PM PDT 24
Finished Jul 23 07:09:48 PM PDT 24
Peak memory 218760 kb
Host smart-91805e75-bdbe-4bae-bc5f-45d6936f353c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814453527 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1814453527
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.2117985147
Short name T372
Test name
Test status
Simulation time 148736089 ps
CPU time 3.18 seconds
Started Jul 23 07:09:11 PM PDT 24
Finished Jul 23 07:09:18 PM PDT 24
Peak memory 220396 kb
Host smart-92b8abcd-5f8a-4fdf-b290-e6b2fffc11a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117985147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2117985147
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.2941547999
Short name T495
Test name
Test status
Simulation time 30912367 ps
CPU time 1.05 seconds
Started Jul 23 07:09:12 PM PDT 24
Finished Jul 23 07:09:18 PM PDT 24
Peak memory 215844 kb
Host smart-74547e2a-1ec8-4eae-b386-8ab8d8cf7711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941547999 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.2941547999
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.178556707
Short name T908
Test name
Test status
Simulation time 45361843 ps
CPU time 0.96 seconds
Started Jul 23 07:09:13 PM PDT 24
Finished Jul 23 07:09:20 PM PDT 24
Peak memory 215608 kb
Host smart-37045308-4ae2-4907-aff6-ab5befce8140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178556707 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.178556707
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.943705305
Short name T470
Test name
Test status
Simulation time 316643383 ps
CPU time 1.32 seconds
Started Jul 23 07:09:12 PM PDT 24
Finished Jul 23 07:09:17 PM PDT 24
Peak memory 215692 kb
Host smart-7bb96b80-63cb-4fb3-af6e-aba0710a7843
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943705305 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.943705305
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2722636498
Short name T520
Test name
Test status
Simulation time 25102256444 ps
CPU time 568.27 seconds
Started Jul 23 07:09:13 PM PDT 24
Finished Jul 23 07:18:47 PM PDT 24
Peak memory 218696 kb
Host smart-7213db60-42d7-4d7b-a84a-8c2eabacf4bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722636498 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2722636498
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.1267640691
Short name T609
Test name
Test status
Simulation time 46058965 ps
CPU time 1.14 seconds
Started Jul 23 07:10:55 PM PDT 24
Finished Jul 23 07:11:07 PM PDT 24
Peak memory 219116 kb
Host smart-b257f05a-a7b1-4369-8069-0212a1545bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267640691 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.1267640691
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.778778412
Short name T545
Test name
Test status
Simulation time 59715760 ps
CPU time 1.11 seconds
Started Jul 23 07:10:55 PM PDT 24
Finished Jul 23 07:11:06 PM PDT 24
Peak memory 219384 kb
Host smart-c86993ce-9c09-4752-aa3f-79311183cd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778778412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.778778412
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.1292883404
Short name T994
Test name
Test status
Simulation time 36909870 ps
CPU time 1.14 seconds
Started Jul 23 07:10:52 PM PDT 24
Finished Jul 23 07:11:03 PM PDT 24
Peak memory 220348 kb
Host smart-33a0d1fb-d024-426e-a651-6cae62f86ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292883404 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.1292883404
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.1098128906
Short name T680
Test name
Test status
Simulation time 48390643 ps
CPU time 1.34 seconds
Started Jul 23 07:10:53 PM PDT 24
Finished Jul 23 07:11:04 PM PDT 24
Peak memory 220088 kb
Host smart-896e5b90-64e2-4fc2-9f9a-b4833701d502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098128906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1098128906
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.1824207511
Short name T159
Test name
Test status
Simulation time 91513418 ps
CPU time 1.19 seconds
Started Jul 23 07:10:55 PM PDT 24
Finished Jul 23 07:11:06 PM PDT 24
Peak memory 220108 kb
Host smart-19c53521-03b9-4611-88ec-077fa2b27fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824207511 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.1824207511
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.3025461579
Short name T745
Test name
Test status
Simulation time 40745113 ps
CPU time 1.49 seconds
Started Jul 23 07:10:55 PM PDT 24
Finished Jul 23 07:11:07 PM PDT 24
Peak memory 217744 kb
Host smart-29953e84-1b02-4b2d-9a24-7f99a19c5cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025461579 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.3025461579
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.2827489085
Short name T954
Test name
Test status
Simulation time 67416572 ps
CPU time 1.11 seconds
Started Jul 23 07:10:56 PM PDT 24
Finished Jul 23 07:11:07 PM PDT 24
Peak memory 219792 kb
Host smart-01ab2f5b-0b90-482c-9145-f145d0259217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827489085 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.2827489085
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.1567974160
Short name T305
Test name
Test status
Simulation time 54827985 ps
CPU time 1.33 seconds
Started Jul 23 07:10:54 PM PDT 24
Finished Jul 23 07:11:04 PM PDT 24
Peak memory 217584 kb
Host smart-24edf0e5-0c65-4fe7-b91a-aa85a2c8ff70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567974160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.1567974160
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.1681020211
Short name T152
Test name
Test status
Simulation time 64171541 ps
CPU time 1.14 seconds
Started Jul 23 07:10:52 PM PDT 24
Finished Jul 23 07:11:03 PM PDT 24
Peak memory 220184 kb
Host smart-dfd8ffb0-35c8-46af-bbb3-800b017498e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681020211 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.1681020211
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/165.edn_alert.422743475
Short name T843
Test name
Test status
Simulation time 37148225 ps
CPU time 1.1 seconds
Started Jul 23 07:10:54 PM PDT 24
Finished Jul 23 07:11:04 PM PDT 24
Peak memory 218832 kb
Host smart-2fd5c124-622e-49f4-aa93-fd5bc240b927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422743475 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.422743475
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/166.edn_alert.2225773965
Short name T915
Test name
Test status
Simulation time 158343400 ps
CPU time 1.17 seconds
Started Jul 23 07:10:55 PM PDT 24
Finished Jul 23 07:11:06 PM PDT 24
Peak memory 218904 kb
Host smart-b3587fad-e83d-453c-b401-d57ce6502e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225773965 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.2225773965
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.4059520969
Short name T912
Test name
Test status
Simulation time 38643069 ps
CPU time 1.2 seconds
Started Jul 23 07:10:55 PM PDT 24
Finished Jul 23 07:11:07 PM PDT 24
Peak memory 219916 kb
Host smart-678690db-0e92-4fbd-a0d4-3690e1877297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059520969 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.4059520969
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.1153164339
Short name T842
Test name
Test status
Simulation time 132535497 ps
CPU time 1.11 seconds
Started Jul 23 07:10:54 PM PDT 24
Finished Jul 23 07:11:04 PM PDT 24
Peak memory 219480 kb
Host smart-6e072670-e29a-4ee1-9ab2-42b7e27c7d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153164339 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.1153164339
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.2919560669
Short name T885
Test name
Test status
Simulation time 77947839 ps
CPU time 1.13 seconds
Started Jul 23 07:10:57 PM PDT 24
Finished Jul 23 07:11:09 PM PDT 24
Peak memory 220320 kb
Host smart-7e1d04a1-91a0-459a-afaf-650c1cb15ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919560669 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.2919560669
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.572835891
Short name T270
Test name
Test status
Simulation time 30369822 ps
CPU time 1.32 seconds
Started Jul 23 07:10:52 PM PDT 24
Finished Jul 23 07:11:03 PM PDT 24
Peak memory 219680 kb
Host smart-9c5cfa4f-f269-4247-af79-2266a067b63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572835891 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.572835891
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.1131659748
Short name T385
Test name
Test status
Simulation time 45487490 ps
CPU time 1.59 seconds
Started Jul 23 07:10:54 PM PDT 24
Finished Jul 23 07:11:06 PM PDT 24
Peak memory 218908 kb
Host smart-0b082703-d424-40fc-b44f-1ba03914eb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131659748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1131659748
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.958203270
Short name T118
Test name
Test status
Simulation time 62089461 ps
CPU time 1.19 seconds
Started Jul 23 07:11:04 PM PDT 24
Finished Jul 23 07:11:15 PM PDT 24
Peak memory 216104 kb
Host smart-f18affc5-158b-473e-b19f-98af0c01764a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958203270 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.958203270
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.2956355903
Short name T304
Test name
Test status
Simulation time 40590433 ps
CPU time 1.44 seconds
Started Jul 23 07:11:01 PM PDT 24
Finished Jul 23 07:11:13 PM PDT 24
Peak memory 218980 kb
Host smart-be9f6055-c7c9-4822-a245-93547305a666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956355903 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.2956355903
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.3503188454
Short name T665
Test name
Test status
Simulation time 35675530 ps
CPU time 1.09 seconds
Started Jul 23 07:09:39 PM PDT 24
Finished Jul 23 07:09:48 PM PDT 24
Peak memory 219040 kb
Host smart-ab89ca6d-9dfc-4b5c-9e00-4a5ef8df4de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503188454 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.3503188454
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.219401081
Short name T991
Test name
Test status
Simulation time 74011254 ps
CPU time 0.92 seconds
Started Jul 23 07:09:40 PM PDT 24
Finished Jul 23 07:09:50 PM PDT 24
Peak memory 214988 kb
Host smart-e03c47e5-28bd-4cf2-96a1-72601c0ffc86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219401081 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.219401081
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.2351309033
Short name T494
Test name
Test status
Simulation time 13565174 ps
CPU time 0.92 seconds
Started Jul 23 07:09:37 PM PDT 24
Finished Jul 23 07:09:43 PM PDT 24
Peak memory 216200 kb
Host smart-380148d6-8dc6-4e2a-8c40-ced11a1c68d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351309033 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.2351309033
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.4015535597
Short name T951
Test name
Test status
Simulation time 28026509 ps
CPU time 1.11 seconds
Started Jul 23 07:09:39 PM PDT 24
Finished Jul 23 07:09:48 PM PDT 24
Peak memory 217172 kb
Host smart-ad82facc-c0c9-4248-9f9a-1143efc51034
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015535597 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.4015535597
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.1675505966
Short name T128
Test name
Test status
Simulation time 27889783 ps
CPU time 1.23 seconds
Started Jul 23 07:09:41 PM PDT 24
Finished Jul 23 07:09:53 PM PDT 24
Peak memory 220944 kb
Host smart-1ffbdc30-0131-4859-923e-483a694763b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675505966 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.1675505966
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.1185116245
Short name T104
Test name
Test status
Simulation time 75867805 ps
CPU time 1.17 seconds
Started Jul 23 07:09:41 PM PDT 24
Finished Jul 23 07:09:53 PM PDT 24
Peak memory 218988 kb
Host smart-18d290c2-4db0-45f8-a1fe-8bfa9ac2d4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185116245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1185116245
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3959436714
Short name T992
Test name
Test status
Simulation time 28330171 ps
CPU time 0.99 seconds
Started Jul 23 07:09:36 PM PDT 24
Finished Jul 23 07:09:40 PM PDT 24
Peak memory 216088 kb
Host smart-fdd445bd-bad8-4f9c-ba08-49740939b85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959436714 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3959436714
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.4182315221
Short name T913
Test name
Test status
Simulation time 25109533 ps
CPU time 0.98 seconds
Started Jul 23 07:09:36 PM PDT 24
Finished Jul 23 07:09:42 PM PDT 24
Peak memory 215668 kb
Host smart-c4f86b09-9445-4b37-b848-63eb8f10ba59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182315221 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.4182315221
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1416465069
Short name T400
Test name
Test status
Simulation time 634258868 ps
CPU time 3.95 seconds
Started Jul 23 07:09:40 PM PDT 24
Finished Jul 23 07:09:54 PM PDT 24
Peak memory 220064 kb
Host smart-b44a8605-459a-4294-a620-a109859fa2c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416465069 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1416465069
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.3814251219
Short name T743
Test name
Test status
Simulation time 407603248016 ps
CPU time 1970.55 seconds
Started Jul 23 07:09:35 PM PDT 24
Finished Jul 23 07:42:30 PM PDT 24
Peak memory 227180 kb
Host smart-8e052929-6a99-479f-b99c-6b0c160433df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814251219 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.3814251219
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.3089114228
Short name T781
Test name
Test status
Simulation time 85223044 ps
CPU time 1.14 seconds
Started Jul 23 07:11:00 PM PDT 24
Finished Jul 23 07:11:12 PM PDT 24
Peak memory 217528 kb
Host smart-a0b17899-cbac-4556-bf89-8cc1ac51e70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089114228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.3089114228
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.1471824
Short name T215
Test name
Test status
Simulation time 62827931 ps
CPU time 1.09 seconds
Started Jul 23 07:11:00 PM PDT 24
Finished Jul 23 07:11:11 PM PDT 24
Peak memory 220044 kb
Host smart-951791eb-968c-4a5c-ae24-79ab99d24aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471824 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.1471824
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.3163500752
Short name T565
Test name
Test status
Simulation time 53238189 ps
CPU time 1.05 seconds
Started Jul 23 07:11:00 PM PDT 24
Finished Jul 23 07:11:10 PM PDT 24
Peak memory 217664 kb
Host smart-fbdfd3dd-b2dc-4ed3-a161-c909e025fa28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163500752 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.3163500752
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.1854416902
Short name T490
Test name
Test status
Simulation time 31641040 ps
CPU time 1.5 seconds
Started Jul 23 07:10:59 PM PDT 24
Finished Jul 23 07:11:10 PM PDT 24
Peak memory 217672 kb
Host smart-f07230f8-e508-424d-b1d1-eb691b8ca0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854416902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.1854416902
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.1237425438
Short name T371
Test name
Test status
Simulation time 32079428 ps
CPU time 1.33 seconds
Started Jul 23 07:11:01 PM PDT 24
Finished Jul 23 07:11:13 PM PDT 24
Peak memory 219996 kb
Host smart-3a1365b8-0333-4d13-b6e2-52e534fc5e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237425438 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.1237425438
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.441246331
Short name T754
Test name
Test status
Simulation time 77413950 ps
CPU time 1.3 seconds
Started Jul 23 07:11:02 PM PDT 24
Finished Jul 23 07:11:13 PM PDT 24
Peak memory 219072 kb
Host smart-a4a767c9-fc4c-4f1f-9290-2b4fc701322f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441246331 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.441246331
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.1881964721
Short name T920
Test name
Test status
Simulation time 39116409 ps
CPU time 1.08 seconds
Started Jul 23 07:11:00 PM PDT 24
Finished Jul 23 07:11:12 PM PDT 24
Peak memory 218976 kb
Host smart-67478a76-2148-464a-b40e-72107d6aed6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881964721 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.1881964721
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/175.edn_alert.1567289615
Short name T778
Test name
Test status
Simulation time 66883188 ps
CPU time 1.07 seconds
Started Jul 23 07:11:07 PM PDT 24
Finished Jul 23 07:11:17 PM PDT 24
Peak memory 221196 kb
Host smart-2b3c2d6b-ab8d-4d1f-914c-23e453002548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567289615 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.1567289615
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.1715167656
Short name T487
Test name
Test status
Simulation time 70552034 ps
CPU time 1.06 seconds
Started Jul 23 07:10:58 PM PDT 24
Finished Jul 23 07:11:09 PM PDT 24
Peak memory 217696 kb
Host smart-16a96ba0-53dd-4f8b-be5c-5ac6964c64ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715167656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.1715167656
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.3391494634
Short name T24
Test name
Test status
Simulation time 60697685 ps
CPU time 1.01 seconds
Started Jul 23 07:11:09 PM PDT 24
Finished Jul 23 07:11:19 PM PDT 24
Peak memory 219944 kb
Host smart-0cf819fa-c8df-4d4b-9ce8-4ac76bd6b5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391494634 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.3391494634
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/177.edn_alert.3465241036
Short name T414
Test name
Test status
Simulation time 45340937 ps
CPU time 1.19 seconds
Started Jul 23 07:11:01 PM PDT 24
Finished Jul 23 07:11:13 PM PDT 24
Peak memory 219832 kb
Host smart-767d1e9e-16a9-4e32-88f6-c350c3a49f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465241036 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.3465241036
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.3123280612
Short name T730
Test name
Test status
Simulation time 138012459 ps
CPU time 2.64 seconds
Started Jul 23 07:11:08 PM PDT 24
Finished Jul 23 07:11:20 PM PDT 24
Peak memory 220292 kb
Host smart-03dcdb21-28e4-4706-97f1-08d5d95474e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123280612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.3123280612
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.2068153242
Short name T473
Test name
Test status
Simulation time 73025965 ps
CPU time 1.1 seconds
Started Jul 23 07:11:08 PM PDT 24
Finished Jul 23 07:11:18 PM PDT 24
Peak memory 220084 kb
Host smart-4414218e-312a-46a2-b573-b42e9b35e033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068153242 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.2068153242
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.3901469213
Short name T645
Test name
Test status
Simulation time 54429224 ps
CPU time 1.61 seconds
Started Jul 23 07:11:03 PM PDT 24
Finished Jul 23 07:11:15 PM PDT 24
Peak memory 218744 kb
Host smart-9fde160f-86d0-4f51-8e07-316a2fed1a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901469213 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3901469213
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.2456441783
Short name T315
Test name
Test status
Simulation time 47327269 ps
CPU time 1.09 seconds
Started Jul 23 07:11:02 PM PDT 24
Finished Jul 23 07:11:13 PM PDT 24
Peak memory 220480 kb
Host smart-93d34f28-76b9-4cc6-ab44-ec47c4021e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456441783 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.2456441783
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.3796630773
Short name T814
Test name
Test status
Simulation time 53624550 ps
CPU time 1.21 seconds
Started Jul 23 07:11:01 PM PDT 24
Finished Jul 23 07:11:13 PM PDT 24
Peak memory 217612 kb
Host smart-c9f51176-097c-41cf-923c-fa116a163fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796630773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3796630773
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.2647519992
Short name T611
Test name
Test status
Simulation time 54339013 ps
CPU time 1.19 seconds
Started Jul 23 07:09:39 PM PDT 24
Finished Jul 23 07:09:47 PM PDT 24
Peak memory 220304 kb
Host smart-901e016f-150d-4139-a695-3b2b11e3d760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647519992 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.2647519992
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.3294517369
Short name T923
Test name
Test status
Simulation time 66498315 ps
CPU time 0.95 seconds
Started Jul 23 07:09:33 PM PDT 24
Finished Jul 23 07:09:36 PM PDT 24
Peak memory 207176 kb
Host smart-d51a52ec-eaf9-4999-bc91-4bbae936e8f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294517369 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.3294517369
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.1348571528
Short name T60
Test name
Test status
Simulation time 63708148 ps
CPU time 0.81 seconds
Started Jul 23 07:09:36 PM PDT 24
Finished Jul 23 07:09:40 PM PDT 24
Peak memory 216780 kb
Host smart-f6606131-aa0f-4f9d-888e-5d198302194d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348571528 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.1348571528
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_err.431313638
Short name T910
Test name
Test status
Simulation time 31682531 ps
CPU time 0.87 seconds
Started Jul 23 07:09:35 PM PDT 24
Finished Jul 23 07:09:38 PM PDT 24
Peak memory 218540 kb
Host smart-bd698093-be69-4418-ae1d-f8f595f84912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431313638 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.431313638
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.498454161
Short name T718
Test name
Test status
Simulation time 56121823 ps
CPU time 1.2 seconds
Started Jul 23 07:09:37 PM PDT 24
Finished Jul 23 07:09:45 PM PDT 24
Peak memory 217664 kb
Host smart-06957c02-392b-4ee0-aa97-bbb24eb1b748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498454161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.498454161
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.2219448640
Short name T753
Test name
Test status
Simulation time 43238913 ps
CPU time 0.88 seconds
Started Jul 23 07:09:38 PM PDT 24
Finished Jul 23 07:09:46 PM PDT 24
Peak memory 215672 kb
Host smart-bf2b2ff7-c15f-47db-8b46-e22f4b9b35fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219448640 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.2219448640
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.2954897673
Short name T366
Test name
Test status
Simulation time 46133804 ps
CPU time 0.91 seconds
Started Jul 23 07:09:37 PM PDT 24
Finished Jul 23 07:09:44 PM PDT 24
Peak memory 215632 kb
Host smart-a0183693-bdc5-4967-afa6-1ad5b68dea1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954897673 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2954897673
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1634697765
Short name T521
Test name
Test status
Simulation time 253200693 ps
CPU time 5.15 seconds
Started Jul 23 07:09:37 PM PDT 24
Finished Jul 23 07:09:46 PM PDT 24
Peak memory 218804 kb
Host smart-e2d940e2-e2d5-4742-bd2a-52a8de6b0b64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634697765 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1634697765
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.4116599588
Short name T813
Test name
Test status
Simulation time 69491602340 ps
CPU time 356.46 seconds
Started Jul 23 07:09:35 PM PDT 24
Finished Jul 23 07:15:35 PM PDT 24
Peak memory 218236 kb
Host smart-12fdb11c-8da3-478f-80d9-e8e0bd1f9e22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116599588 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.4116599588
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.3989522979
Short name T738
Test name
Test status
Simulation time 33055185 ps
CPU time 1.12 seconds
Started Jul 23 07:11:02 PM PDT 24
Finished Jul 23 07:11:13 PM PDT 24
Peak memory 218772 kb
Host smart-682a62f8-b8ea-4721-b2e2-c9b1546167ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989522979 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.3989522979
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.2347084467
Short name T739
Test name
Test status
Simulation time 39150764 ps
CPU time 1.42 seconds
Started Jul 23 07:11:03 PM PDT 24
Finished Jul 23 07:11:15 PM PDT 24
Peak memory 218388 kb
Host smart-b15f573c-cf23-4eb7-ae11-2014d806452c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347084467 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.2347084467
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.1612429858
Short name T241
Test name
Test status
Simulation time 92627417 ps
CPU time 1.2 seconds
Started Jul 23 07:11:04 PM PDT 24
Finished Jul 23 07:11:16 PM PDT 24
Peak memory 221072 kb
Host smart-b8687dba-fd15-493a-bc16-422a20ca86bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612429858 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.1612429858
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.3110684016
Short name T429
Test name
Test status
Simulation time 38165686 ps
CPU time 1.08 seconds
Started Jul 23 07:11:05 PM PDT 24
Finished Jul 23 07:11:16 PM PDT 24
Peak memory 217520 kb
Host smart-44c21d01-c5db-44dc-a727-f0fea4b80a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110684016 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3110684016
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.3650766140
Short name T965
Test name
Test status
Simulation time 67542638 ps
CPU time 1.21 seconds
Started Jul 23 07:11:07 PM PDT 24
Finished Jul 23 07:11:18 PM PDT 24
Peak memory 219852 kb
Host smart-56867b6b-2bf3-49ec-9042-cc1391c9083d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650766140 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.3650766140
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.2390097165
Short name T821
Test name
Test status
Simulation time 42902432 ps
CPU time 1.55 seconds
Started Jul 23 07:11:04 PM PDT 24
Finished Jul 23 07:11:16 PM PDT 24
Peak memory 218784 kb
Host smart-72098348-e47a-4da0-898a-2b1fd53864e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390097165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.2390097165
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.200661464
Short name T865
Test name
Test status
Simulation time 176478553 ps
CPU time 1.12 seconds
Started Jul 23 07:11:08 PM PDT 24
Finished Jul 23 07:11:18 PM PDT 24
Peak memory 219100 kb
Host smart-ab18dede-1bec-4e11-811c-180aa0c7e59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200661464 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.200661464
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.1971091580
Short name T421
Test name
Test status
Simulation time 55953681 ps
CPU time 1.35 seconds
Started Jul 23 07:11:01 PM PDT 24
Finished Jul 23 07:11:14 PM PDT 24
Peak memory 217748 kb
Host smart-ff651dfb-384f-443c-8270-91793df2f8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971091580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.1971091580
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.4204166560
Short name T142
Test name
Test status
Simulation time 67851028 ps
CPU time 1.05 seconds
Started Jul 23 07:11:03 PM PDT 24
Finished Jul 23 07:11:14 PM PDT 24
Peak memory 218824 kb
Host smart-1ab51dc6-7de8-4750-9c46-74640f5c7187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204166560 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.4204166560
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.1248532984
Short name T397
Test name
Test status
Simulation time 52458245 ps
CPU time 1.72 seconds
Started Jul 23 07:11:08 PM PDT 24
Finished Jul 23 07:11:19 PM PDT 24
Peak memory 219020 kb
Host smart-4643135d-9f5f-4650-a889-8fc684d10466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248532984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.1248532984
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.2875442942
Short name T190
Test name
Test status
Simulation time 108351955 ps
CPU time 1.37 seconds
Started Jul 23 07:11:07 PM PDT 24
Finished Jul 23 07:11:17 PM PDT 24
Peak memory 216000 kb
Host smart-83c8fa81-4f86-4f56-8c31-2511f9ac0dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875442942 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.2875442942
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.2416340065
Short name T483
Test name
Test status
Simulation time 38174111 ps
CPU time 1.36 seconds
Started Jul 23 07:11:09 PM PDT 24
Finished Jul 23 07:11:19 PM PDT 24
Peak memory 218868 kb
Host smart-ebc73df2-d6eb-420e-b122-ca65ee052c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416340065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2416340065
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.4000202210
Short name T284
Test name
Test status
Simulation time 25880319 ps
CPU time 1.22 seconds
Started Jul 23 07:11:01 PM PDT 24
Finished Jul 23 07:11:12 PM PDT 24
Peak memory 218988 kb
Host smart-0497e182-4fb1-4a9e-9806-c170c6fbfcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000202210 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.4000202210
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.658198883
Short name T293
Test name
Test status
Simulation time 276064434 ps
CPU time 1.16 seconds
Started Jul 23 07:11:08 PM PDT 24
Finished Jul 23 07:11:18 PM PDT 24
Peak memory 217488 kb
Host smart-d2d02a57-605b-4349-8d83-480947d4563a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658198883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.658198883
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.1858183729
Short name T436
Test name
Test status
Simulation time 81989542 ps
CPU time 1.09 seconds
Started Jul 23 07:11:06 PM PDT 24
Finished Jul 23 07:11:16 PM PDT 24
Peak memory 220020 kb
Host smart-6fe09f35-6a15-492e-8555-073d498e5558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858183729 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.1858183729
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.189835642
Short name T39
Test name
Test status
Simulation time 166059599 ps
CPU time 1.63 seconds
Started Jul 23 07:10:59 PM PDT 24
Finished Jul 23 07:11:10 PM PDT 24
Peak memory 219008 kb
Host smart-7a4c0d4d-56c0-411b-8417-b2a862188e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189835642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.189835642
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.2863063520
Short name T807
Test name
Test status
Simulation time 47127051 ps
CPU time 1.33 seconds
Started Jul 23 07:11:01 PM PDT 24
Finished Jul 23 07:11:12 PM PDT 24
Peak memory 216056 kb
Host smart-7eb28f38-aaf0-40c3-82fd-3af4942c7745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863063520 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.2863063520
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.421577933
Short name T655
Test name
Test status
Simulation time 83719573 ps
CPU time 1.2 seconds
Started Jul 23 07:11:05 PM PDT 24
Finished Jul 23 07:11:16 PM PDT 24
Peak memory 217608 kb
Host smart-7b1dc7af-4c01-4fc7-bda8-3f7c3a85841e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421577933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.421577933
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.2750364462
Short name T668
Test name
Test status
Simulation time 39383006 ps
CPU time 1.08 seconds
Started Jul 23 07:10:59 PM PDT 24
Finished Jul 23 07:11:10 PM PDT 24
Peak memory 219872 kb
Host smart-6ad7dfb9-93a5-47d0-af88-ca10b452283e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750364462 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.2750364462
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.4038895167
Short name T419
Test name
Test status
Simulation time 29579166 ps
CPU time 1.18 seconds
Started Jul 23 07:11:06 PM PDT 24
Finished Jul 23 07:11:16 PM PDT 24
Peak memory 220192 kb
Host smart-27997ea2-1d69-4c01-9085-cf15a273afb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038895167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.4038895167
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.600083072
Short name T480
Test name
Test status
Simulation time 32419888 ps
CPU time 1.1 seconds
Started Jul 23 07:09:41 PM PDT 24
Finished Jul 23 07:09:53 PM PDT 24
Peak memory 218672 kb
Host smart-0d93b027-0fb4-43bf-9820-7899bbaf3122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600083072 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.600083072
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.1701453657
Short name T574
Test name
Test status
Simulation time 14719817 ps
CPU time 0.87 seconds
Started Jul 23 07:09:34 PM PDT 24
Finished Jul 23 07:09:37 PM PDT 24
Peak memory 215196 kb
Host smart-80ed8ea1-916d-4b12-9aff-627cb8663047
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701453657 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.1701453657
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.3623830889
Short name T331
Test name
Test status
Simulation time 65103315 ps
CPU time 1.2 seconds
Started Jul 23 07:09:33 PM PDT 24
Finished Jul 23 07:09:36 PM PDT 24
Peak memory 218844 kb
Host smart-a3d1524e-e3b8-43bb-98bc-5cce130c2514
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623830889 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.3623830889
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.1123434784
Short name T79
Test name
Test status
Simulation time 28628983 ps
CPU time 0.82 seconds
Started Jul 23 07:09:36 PM PDT 24
Finished Jul 23 07:09:41 PM PDT 24
Peak memory 218556 kb
Host smart-a6a88e0d-6dea-4cf6-9836-d08ec0da9abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123434784 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.1123434784
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.3711614118
Short name T556
Test name
Test status
Simulation time 202645220 ps
CPU time 2.66 seconds
Started Jul 23 07:09:34 PM PDT 24
Finished Jul 23 07:09:38 PM PDT 24
Peak memory 219264 kb
Host smart-c2fbe779-3e44-41c1-a3a6-0a8c3e1be29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711614118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3711614118
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3552280822
Short name T862
Test name
Test status
Simulation time 38911071 ps
CPU time 0.96 seconds
Started Jul 23 07:09:35 PM PDT 24
Finished Jul 23 07:09:40 PM PDT 24
Peak memory 224344 kb
Host smart-87d3fee3-c900-414c-91fe-de283eefda5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552280822 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3552280822
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.1034021921
Short name T514
Test name
Test status
Simulation time 115577341 ps
CPU time 0.92 seconds
Started Jul 23 07:09:39 PM PDT 24
Finished Jul 23 07:09:47 PM PDT 24
Peak memory 215396 kb
Host smart-9e13ccb5-80b2-456a-b55b-8d759dd9a275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034021921 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.1034021921
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.2197641901
Short name T442
Test name
Test status
Simulation time 198000368 ps
CPU time 4.06 seconds
Started Jul 23 07:09:36 PM PDT 24
Finished Jul 23 07:09:45 PM PDT 24
Peak memory 215644 kb
Host smart-884782ff-0965-46af-b26f-4dcd0a8e6f62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197641901 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.2197641901
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.3269512689
Short name T221
Test name
Test status
Simulation time 15256112671 ps
CPU time 346.79 seconds
Started Jul 23 07:09:37 PM PDT 24
Finished Jul 23 07:15:28 PM PDT 24
Peak memory 218748 kb
Host smart-3dda13d2-76a5-4e16-9cce-9f9012aec4a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269512689 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.3269512689
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.959939967
Short name T138
Test name
Test status
Simulation time 90012658 ps
CPU time 1.28 seconds
Started Jul 23 07:10:58 PM PDT 24
Finished Jul 23 07:11:09 PM PDT 24
Peak memory 220064 kb
Host smart-02cdf478-a900-4652-bf3d-054ce54b3bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959939967 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.959939967
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.2681666658
Short name T347
Test name
Test status
Simulation time 2260478817 ps
CPU time 70.52 seconds
Started Jul 23 07:11:03 PM PDT 24
Finished Jul 23 07:12:23 PM PDT 24
Peak memory 219452 kb
Host smart-5e082f24-e73f-4555-812f-1ecaa69c1545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681666658 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.2681666658
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.994176195
Short name T628
Test name
Test status
Simulation time 27457287 ps
CPU time 1.18 seconds
Started Jul 23 07:11:04 PM PDT 24
Finished Jul 23 07:11:15 PM PDT 24
Peak memory 218712 kb
Host smart-6f5dfa9c-e291-40cd-8d23-94b1898e7827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994176195 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.994176195
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/192.edn_alert.3249787551
Short name T748
Test name
Test status
Simulation time 37003868 ps
CPU time 1.13 seconds
Started Jul 23 07:11:09 PM PDT 24
Finished Jul 23 07:11:20 PM PDT 24
Peak memory 220248 kb
Host smart-e6e247f3-a88a-4069-af2b-926c43f5e387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249787551 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.3249787551
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.824346473
Short name T289
Test name
Test status
Simulation time 39060857 ps
CPU time 1.45 seconds
Started Jul 23 07:11:06 PM PDT 24
Finished Jul 23 07:11:16 PM PDT 24
Peak memory 220400 kb
Host smart-fe0a771a-4c51-46b0-ab84-f50a05bce9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824346473 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.824346473
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.3829732044
Short name T137
Test name
Test status
Simulation time 29366278 ps
CPU time 1.28 seconds
Started Jul 23 07:11:05 PM PDT 24
Finished Jul 23 07:11:16 PM PDT 24
Peak memory 220108 kb
Host smart-921d41ac-94ee-41b8-a178-bfaa2e963993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829732044 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.3829732044
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.978550420
Short name T367
Test name
Test status
Simulation time 30569396 ps
CPU time 1.38 seconds
Started Jul 23 07:11:12 PM PDT 24
Finished Jul 23 07:11:23 PM PDT 24
Peak memory 218700 kb
Host smart-930d16d8-b2a3-48dc-86d0-cf9b84dfdbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978550420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.978550420
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.3086495097
Short name T488
Test name
Test status
Simulation time 35815370 ps
CPU time 1.55 seconds
Started Jul 23 07:11:09 PM PDT 24
Finished Jul 23 07:11:19 PM PDT 24
Peak memory 218812 kb
Host smart-8de02d93-4b51-4d0a-8592-c17c02668dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086495097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3086495097
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.2772754910
Short name T742
Test name
Test status
Simulation time 24136255 ps
CPU time 1.1 seconds
Started Jul 23 07:11:09 PM PDT 24
Finished Jul 23 07:11:20 PM PDT 24
Peak memory 219992 kb
Host smart-c2349be2-f2cb-4a64-8710-8b7206cb7fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772754910 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.2772754910
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.218700206
Short name T278
Test name
Test status
Simulation time 108421204 ps
CPU time 2.77 seconds
Started Jul 23 07:11:14 PM PDT 24
Finished Jul 23 07:11:27 PM PDT 24
Peak memory 220360 kb
Host smart-dd148a62-806a-4437-8ed2-faa56daa3af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218700206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.218700206
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.120089339
Short name T661
Test name
Test status
Simulation time 23025523 ps
CPU time 1.17 seconds
Started Jul 23 07:11:08 PM PDT 24
Finished Jul 23 07:11:19 PM PDT 24
Peak memory 221396 kb
Host smart-80a709bb-2a36-4ccc-ab45-99eab830e3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120089339 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.120089339
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.3373227071
Short name T588
Test name
Test status
Simulation time 32790027 ps
CPU time 1.3 seconds
Started Jul 23 07:11:09 PM PDT 24
Finished Jul 23 07:11:21 PM PDT 24
Peak memory 217428 kb
Host smart-7e8148a6-e301-43ce-93d7-347fe0b01589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373227071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3373227071
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.2454069419
Short name T174
Test name
Test status
Simulation time 76173280 ps
CPU time 1.21 seconds
Started Jul 23 07:11:09 PM PDT 24
Finished Jul 23 07:11:20 PM PDT 24
Peak memory 219932 kb
Host smart-0dc3abec-5ba2-4c8e-ab36-b4a0a3fb9fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454069419 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.2454069419
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.3173426755
Short name T589
Test name
Test status
Simulation time 69041589 ps
CPU time 1.54 seconds
Started Jul 23 07:11:09 PM PDT 24
Finished Jul 23 07:11:19 PM PDT 24
Peak memory 218920 kb
Host smart-28d8935c-6478-4a0c-96f6-f7760397080b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173426755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3173426755
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.563465669
Short name T524
Test name
Test status
Simulation time 43067935 ps
CPU time 1.13 seconds
Started Jul 23 07:11:08 PM PDT 24
Finished Jul 23 07:11:19 PM PDT 24
Peak memory 218928 kb
Host smart-b4f056fb-0b1e-4caa-823f-7d7b8ffdf7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563465669 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.563465669
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.1521062060
Short name T554
Test name
Test status
Simulation time 908559103 ps
CPU time 5.11 seconds
Started Jul 23 07:11:09 PM PDT 24
Finished Jul 23 07:11:24 PM PDT 24
Peak memory 217748 kb
Host smart-f5121745-59aa-47bc-90d3-af4c2568cbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521062060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.1521062060
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.2066356248
Short name T334
Test name
Test status
Simulation time 33354130 ps
CPU time 1.19 seconds
Started Jul 23 07:11:07 PM PDT 24
Finished Jul 23 07:11:17 PM PDT 24
Peak memory 218996 kb
Host smart-f4e672be-7efc-493a-9a2b-3a6166398046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066356248 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.2066356248
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.1468868729
Short name T387
Test name
Test status
Simulation time 62188172 ps
CPU time 1.14 seconds
Started Jul 23 07:11:10 PM PDT 24
Finished Jul 23 07:11:21 PM PDT 24
Peak memory 220300 kb
Host smart-5b160415-c432-42e8-a703-a45dab1934fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468868729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.1468868729
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.3879894225
Short name T321
Test name
Test status
Simulation time 43018746 ps
CPU time 1.23 seconds
Started Jul 23 07:08:42 PM PDT 24
Finished Jul 23 07:08:45 PM PDT 24
Peak memory 218788 kb
Host smart-fb1a9901-0e28-45ad-87fb-588e2dbbcecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879894225 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.3879894225
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.3018432057
Short name T581
Test name
Test status
Simulation time 18637432 ps
CPU time 0.86 seconds
Started Jul 23 07:08:41 PM PDT 24
Finished Jul 23 07:08:44 PM PDT 24
Peak memory 207028 kb
Host smart-d3169361-4197-45b3-952c-0e3933deda33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018432057 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3018432057
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.2120074603
Short name T863
Test name
Test status
Simulation time 16422911 ps
CPU time 0.88 seconds
Started Jul 23 07:08:46 PM PDT 24
Finished Jul 23 07:08:48 PM PDT 24
Peak memory 215732 kb
Host smart-611ab814-f7be-46f0-aae9-ee608c2489dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120074603 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2120074603
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.3272248776
Short name T984
Test name
Test status
Simulation time 151483886 ps
CPU time 1.06 seconds
Started Jul 23 07:08:45 PM PDT 24
Finished Jul 23 07:08:48 PM PDT 24
Peak memory 217264 kb
Host smart-441fd433-6c2a-415b-afae-6e9bdce3f288
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272248776 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.3272248776
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.1745755491
Short name T974
Test name
Test status
Simulation time 23045596 ps
CPU time 0.99 seconds
Started Jul 23 07:08:41 PM PDT 24
Finished Jul 23 07:08:43 PM PDT 24
Peak memory 224244 kb
Host smart-bd66acb5-abcc-4dd4-9c12-291b9a7382cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745755491 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.1745755491
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.2795574172
Short name T550
Test name
Test status
Simulation time 38262045 ps
CPU time 1.33 seconds
Started Jul 23 07:08:47 PM PDT 24
Finished Jul 23 07:08:50 PM PDT 24
Peak memory 220156 kb
Host smart-f12aa6e6-b3be-45b6-b4af-2462d4430453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795574172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.2795574172
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.2539752824
Short name T990
Test name
Test status
Simulation time 22081966 ps
CPU time 1.17 seconds
Started Jul 23 07:08:48 PM PDT 24
Finished Jul 23 07:08:53 PM PDT 24
Peak memory 215776 kb
Host smart-f7eec417-e2f9-4b60-bb6f-7f26108ad051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539752824 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.2539752824
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.1078349500
Short name T28
Test name
Test status
Simulation time 17761907 ps
CPU time 1.06 seconds
Started Jul 23 07:08:44 PM PDT 24
Finished Jul 23 07:08:46 PM PDT 24
Peak memory 207456 kb
Host smart-246f1380-9610-4e09-95d2-556b6860d9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078349500 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.1078349500
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_smoke.2436642367
Short name T560
Test name
Test status
Simulation time 46745253 ps
CPU time 0.89 seconds
Started Jul 23 07:08:41 PM PDT 24
Finished Jul 23 07:08:43 PM PDT 24
Peak memory 207344 kb
Host smart-9f40602e-7fa5-45e2-a047-79bc501fc7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436642367 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.2436642367
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.2133042838
Short name T335
Test name
Test status
Simulation time 431181370 ps
CPU time 5.12 seconds
Started Jul 23 07:08:42 PM PDT 24
Finished Jul 23 07:08:49 PM PDT 24
Peak memory 217608 kb
Host smart-4b8e017a-836b-489f-a97c-886a86232f7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133042838 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2133042838
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1992862437
Short name T707
Test name
Test status
Simulation time 9805373145 ps
CPU time 215.76 seconds
Started Jul 23 07:08:44 PM PDT 24
Finished Jul 23 07:12:22 PM PDT 24
Peak memory 218452 kb
Host smart-9f3a68b8-ef47-4d8c-ae7c-a8409f1bc9a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992862437 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1992862437
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.3222488506
Short name T567
Test name
Test status
Simulation time 38561633 ps
CPU time 1.07 seconds
Started Jul 23 07:09:36 PM PDT 24
Finished Jul 23 07:09:42 PM PDT 24
Peak memory 218772 kb
Host smart-1ecf5aea-d00c-4f50-b98e-246cf821ff6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222488506 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.3222488506
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.143796857
Short name T729
Test name
Test status
Simulation time 24618905 ps
CPU time 0.95 seconds
Started Jul 23 07:09:37 PM PDT 24
Finished Jul 23 07:09:42 PM PDT 24
Peak memory 215484 kb
Host smart-d4dc2dc1-f24b-44f8-b8e8-29194bf9dd51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143796857 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.143796857
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.3808264610
Short name T534
Test name
Test status
Simulation time 25977805 ps
CPU time 0.98 seconds
Started Jul 23 07:09:34 PM PDT 24
Finished Jul 23 07:09:37 PM PDT 24
Peak memory 218840 kb
Host smart-2bc191c8-c81f-4082-9390-4307dc1eaccc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808264610 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.3808264610
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.943106317
Short name T8
Test name
Test status
Simulation time 34900598 ps
CPU time 0.91 seconds
Started Jul 23 07:09:35 PM PDT 24
Finished Jul 23 07:09:37 PM PDT 24
Peak memory 219972 kb
Host smart-1a29f611-9e0b-4460-82a1-65dde051f9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943106317 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.943106317
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.759226955
Short name T901
Test name
Test status
Simulation time 48513726 ps
CPU time 1.45 seconds
Started Jul 23 07:09:33 PM PDT 24
Finished Jul 23 07:09:35 PM PDT 24
Peak memory 219772 kb
Host smart-3293d2c0-47a3-44e7-9a24-9bf083b321b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759226955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.759226955
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.3286668248
Short name T34
Test name
Test status
Simulation time 23924585 ps
CPU time 0.92 seconds
Started Jul 23 07:09:37 PM PDT 24
Finished Jul 23 07:09:42 PM PDT 24
Peak memory 216060 kb
Host smart-ab020412-6e4b-46ff-8e2d-fcbcda0a3487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286668248 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.3286668248
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.3761869502
Short name T953
Test name
Test status
Simulation time 72790816 ps
CPU time 0.84 seconds
Started Jul 23 07:09:35 PM PDT 24
Finished Jul 23 07:09:39 PM PDT 24
Peak memory 215348 kb
Host smart-c9c4875c-130e-419b-95e8-77108d23dd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761869502 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.3761869502
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.490134292
Short name T415
Test name
Test status
Simulation time 400804296 ps
CPU time 2.68 seconds
Started Jul 23 07:09:39 PM PDT 24
Finished Jul 23 07:09:49 PM PDT 24
Peak memory 215624 kb
Host smart-df2cc02f-8eda-49af-a65f-862822e7dd50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490134292 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.490134292
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.3608584241
Short name T225
Test name
Test status
Simulation time 220724200349 ps
CPU time 2594.41 seconds
Started Jul 23 07:09:35 PM PDT 24
Finished Jul 23 07:52:52 PM PDT 24
Peak memory 229232 kb
Host smart-c1df337c-7fc9-4270-b186-81801186d977
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608584241 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.3608584241
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.793017008
Short name T354
Test name
Test status
Simulation time 46575983 ps
CPU time 1.22 seconds
Started Jul 23 07:11:10 PM PDT 24
Finished Jul 23 07:11:21 PM PDT 24
Peak memory 218052 kb
Host smart-952569af-1184-45ab-bbe5-2ce2bb3fa60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793017008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.793017008
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.2948990537
Short name T422
Test name
Test status
Simulation time 22493114 ps
CPU time 1.16 seconds
Started Jul 23 07:11:13 PM PDT 24
Finished Jul 23 07:11:24 PM PDT 24
Peak memory 217556 kb
Host smart-71c770df-e751-4810-90c8-afa6276c47eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948990537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.2948990537
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.1083202387
Short name T638
Test name
Test status
Simulation time 38141432 ps
CPU time 1.52 seconds
Started Jul 23 07:11:04 PM PDT 24
Finished Jul 23 07:11:16 PM PDT 24
Peak memory 217788 kb
Host smart-69ede8ad-1b70-4c54-ba40-14bf7ad26ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083202387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.1083202387
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.788676358
Short name T647
Test name
Test status
Simulation time 46313528 ps
CPU time 1.77 seconds
Started Jul 23 07:11:05 PM PDT 24
Finished Jul 23 07:11:16 PM PDT 24
Peak memory 218784 kb
Host smart-18758eee-ed9c-46bc-a38b-02fa2786893c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788676358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.788676358
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.2670477929
Short name T789
Test name
Test status
Simulation time 156069250 ps
CPU time 3.18 seconds
Started Jul 23 07:11:05 PM PDT 24
Finished Jul 23 07:11:18 PM PDT 24
Peak memory 219668 kb
Host smart-b22c5108-eccb-4e24-82a1-d58b73727372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670477929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.2670477929
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3311968681
Short name T441
Test name
Test status
Simulation time 90993490 ps
CPU time 1.1 seconds
Started Jul 23 07:11:07 PM PDT 24
Finished Jul 23 07:11:18 PM PDT 24
Peak memory 217632 kb
Host smart-bceb908b-ffa2-4baa-adbf-c606077acdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311968681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3311968681
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2569033850
Short name T368
Test name
Test status
Simulation time 147294779 ps
CPU time 2.2 seconds
Started Jul 23 07:11:10 PM PDT 24
Finished Jul 23 07:11:22 PM PDT 24
Peak memory 220484 kb
Host smart-f51f26fd-5ee2-4c80-8060-0da031db5707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569033850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2569033850
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.4089621755
Short name T12
Test name
Test status
Simulation time 31861418 ps
CPU time 1.59 seconds
Started Jul 23 07:11:11 PM PDT 24
Finished Jul 23 07:11:22 PM PDT 24
Peak memory 220464 kb
Host smart-2266d098-0550-449a-8318-1bd40d2cef57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089621755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.4089621755
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.3781808003
Short name T884
Test name
Test status
Simulation time 89694566 ps
CPU time 3.13 seconds
Started Jul 23 07:11:08 PM PDT 24
Finished Jul 23 07:11:20 PM PDT 24
Peak memory 220452 kb
Host smart-afa94f37-01ee-49d1-a78f-eedb011bc292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781808003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.3781808003
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.4128021854
Short name T451
Test name
Test status
Simulation time 23167610 ps
CPU time 1.15 seconds
Started Jul 23 07:09:39 PM PDT 24
Finished Jul 23 07:09:48 PM PDT 24
Peak memory 220264 kb
Host smart-6303248a-ebf0-4937-bd12-eeaf21551052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128021854 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.4128021854
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.1471598251
Short name T110
Test name
Test status
Simulation time 24794703 ps
CPU time 0.9 seconds
Started Jul 23 07:09:36 PM PDT 24
Finished Jul 23 07:09:40 PM PDT 24
Peak memory 215476 kb
Host smart-189c71b3-20db-4a58-ab77-cc504beaa9c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471598251 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.1471598251
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.3037527531
Short name T327
Test name
Test status
Simulation time 46762571 ps
CPU time 0.86 seconds
Started Jul 23 07:09:37 PM PDT 24
Finished Jul 23 07:09:43 PM PDT 24
Peak memory 216736 kb
Host smart-7a2f1180-1691-4971-b457-fcee9428d4c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037527531 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.3037527531
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.3438859879
Short name T447
Test name
Test status
Simulation time 52175327 ps
CPU time 1.03 seconds
Started Jul 23 07:09:36 PM PDT 24
Finished Jul 23 07:09:40 PM PDT 24
Peak memory 220148 kb
Host smart-b42b24c3-1996-43fa-8e1b-5e2cafe497ab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438859879 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.3438859879
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.1809612451
Short name T445
Test name
Test status
Simulation time 34692516 ps
CPU time 0.93 seconds
Started Jul 23 07:09:37 PM PDT 24
Finished Jul 23 07:09:44 PM PDT 24
Peak memory 219992 kb
Host smart-2156712d-3167-4a75-80ec-dadd835d5628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809612451 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.1809612451
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.3174533829
Short name T485
Test name
Test status
Simulation time 80526966 ps
CPU time 1.51 seconds
Started Jul 23 07:09:36 PM PDT 24
Finished Jul 23 07:09:41 PM PDT 24
Peak memory 219016 kb
Host smart-2dc65b5b-3699-4f84-8ca3-c5e9baa6a651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174533829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.3174533829
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_smoke.787147387
Short name T518
Test name
Test status
Simulation time 24562365 ps
CPU time 0.92 seconds
Started Jul 23 07:09:35 PM PDT 24
Finished Jul 23 07:09:38 PM PDT 24
Peak memory 215620 kb
Host smart-156c2d03-0fda-4c7f-800b-a2e05de1352f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787147387 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.787147387
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.1203632821
Short name T481
Test name
Test status
Simulation time 538226794 ps
CPU time 3.29 seconds
Started Jul 23 07:09:33 PM PDT 24
Finished Jul 23 07:09:38 PM PDT 24
Peak memory 215712 kb
Host smart-3913037e-740d-4191-aa37-e40432ef8446
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203632821 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.1203632821
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.813663335
Short name T709
Test name
Test status
Simulation time 91426384033 ps
CPU time 1224.26 seconds
Started Jul 23 07:09:35 PM PDT 24
Finished Jul 23 07:30:02 PM PDT 24
Peak memory 225316 kb
Host smart-9eeef315-e6bd-4239-adf3-4434fbaa1854
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813663335 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.813663335
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.911593125
Short name T747
Test name
Test status
Simulation time 56889856 ps
CPU time 1.8 seconds
Started Jul 23 07:11:06 PM PDT 24
Finished Jul 23 07:11:17 PM PDT 24
Peak memory 218800 kb
Host smart-c93544eb-2a45-4e69-8d90-4818255717ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911593125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.911593125
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.1410360124
Short name T378
Test name
Test status
Simulation time 148549056 ps
CPU time 1.8 seconds
Started Jul 23 07:11:10 PM PDT 24
Finished Jul 23 07:11:22 PM PDT 24
Peak memory 220000 kb
Host smart-0fb7be8d-dfe5-45b0-a629-b92461b07c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410360124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.1410360124
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.723687093
Short name T301
Test name
Test status
Simulation time 78909670 ps
CPU time 1.1 seconds
Started Jul 23 07:11:05 PM PDT 24
Finished Jul 23 07:11:16 PM PDT 24
Peak memory 217732 kb
Host smart-c779e632-b4e7-4720-8912-01ba313c8969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723687093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.723687093
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3176339591
Short name T10
Test name
Test status
Simulation time 61741431 ps
CPU time 1.14 seconds
Started Jul 23 07:11:09 PM PDT 24
Finished Jul 23 07:11:19 PM PDT 24
Peak memory 220484 kb
Host smart-a2c15dbc-d95f-4e06-9551-236b262a16ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176339591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3176339591
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.4206332665
Short name T486
Test name
Test status
Simulation time 91562163 ps
CPU time 1.06 seconds
Started Jul 23 07:11:08 PM PDT 24
Finished Jul 23 07:11:18 PM PDT 24
Peak memory 217704 kb
Host smart-c140b6fa-af38-4a57-98e6-55123760a869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206332665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.4206332665
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.272358182
Short name T828
Test name
Test status
Simulation time 22688477 ps
CPU time 1.12 seconds
Started Jul 23 07:11:14 PM PDT 24
Finished Jul 23 07:11:26 PM PDT 24
Peak memory 217436 kb
Host smart-0320527d-81aa-4b6a-bb2b-554e0065f60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272358182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.272358182
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.923442636
Short name T878
Test name
Test status
Simulation time 40698951 ps
CPU time 1.09 seconds
Started Jul 23 07:11:07 PM PDT 24
Finished Jul 23 07:11:17 PM PDT 24
Peak memory 218692 kb
Host smart-a8626c56-678b-4518-bbea-7be3363c15a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923442636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.923442636
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.2578633887
Short name T732
Test name
Test status
Simulation time 79588614 ps
CPU time 1.88 seconds
Started Jul 23 07:11:10 PM PDT 24
Finished Jul 23 07:11:22 PM PDT 24
Peak memory 220504 kb
Host smart-75d794f6-4845-4baa-a1ee-49dcb23b36de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578633887 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.2578633887
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.62360650
Short name T484
Test name
Test status
Simulation time 50364379 ps
CPU time 1.31 seconds
Started Jul 23 07:11:09 PM PDT 24
Finished Jul 23 07:11:21 PM PDT 24
Peak memory 218624 kb
Host smart-76f335ac-b6e7-4d93-8701-82313199344b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62360650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.62360650
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.1247505022
Short name T894
Test name
Test status
Simulation time 36013321 ps
CPU time 1.18 seconds
Started Jul 23 07:11:10 PM PDT 24
Finished Jul 23 07:11:21 PM PDT 24
Peak memory 217368 kb
Host smart-2e76f1b6-8555-4a24-a444-04c4c2f23314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247505022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1247505022
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.3958610090
Short name T835
Test name
Test status
Simulation time 47346030 ps
CPU time 1.16 seconds
Started Jul 23 07:09:40 PM PDT 24
Finished Jul 23 07:09:51 PM PDT 24
Peak memory 219208 kb
Host smart-7106dd4d-c5b7-45cc-a061-94dd4008dd87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958610090 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.3958610090
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.1820094048
Short name T401
Test name
Test status
Simulation time 27126323 ps
CPU time 0.89 seconds
Started Jul 23 07:09:32 PM PDT 24
Finished Jul 23 07:09:34 PM PDT 24
Peak memory 207048 kb
Host smart-69609ed7-762e-467c-8d2c-145873ea4419
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820094048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1820094048
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.292743597
Short name T177
Test name
Test status
Simulation time 13050303 ps
CPU time 0.91 seconds
Started Jul 23 07:09:34 PM PDT 24
Finished Jul 23 07:09:37 PM PDT 24
Peak memory 216788 kb
Host smart-3c6415d0-ae78-4a5d-9680-45d3e1f8b782
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292743597 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.292743597
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_err.2283781187
Short name T614
Test name
Test status
Simulation time 18332685 ps
CPU time 0.98 seconds
Started Jul 23 07:09:36 PM PDT 24
Finished Jul 23 07:09:40 PM PDT 24
Peak memory 218844 kb
Host smart-f1662951-b236-40ab-a330-cf153f3d9722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283781187 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.2283781187
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.3719937156
Short name T236
Test name
Test status
Simulation time 52777854 ps
CPU time 1.68 seconds
Started Jul 23 07:09:36 PM PDT 24
Finished Jul 23 07:09:43 PM PDT 24
Peak memory 215536 kb
Host smart-ada92574-be3f-45c6-92c8-42538a83f3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719937156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.3719937156
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.1321368569
Short name T914
Test name
Test status
Simulation time 23154364 ps
CPU time 0.94 seconds
Started Jul 23 07:09:37 PM PDT 24
Finished Jul 23 07:09:43 PM PDT 24
Peak memory 216224 kb
Host smart-a685f675-1a30-4d66-9411-481420173bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321368569 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1321368569
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.2085516705
Short name T446
Test name
Test status
Simulation time 71350392 ps
CPU time 0.97 seconds
Started Jul 23 07:09:36 PM PDT 24
Finished Jul 23 07:09:41 PM PDT 24
Peak memory 215676 kb
Host smart-7a1298ce-aee0-4e62-b503-e79d9e81f44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085516705 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2085516705
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.4073080656
Short name T977
Test name
Test status
Simulation time 343388740 ps
CPU time 6.1 seconds
Started Jul 23 07:09:38 PM PDT 24
Finished Jul 23 07:09:50 PM PDT 24
Peak memory 218776 kb
Host smart-d0551007-49db-4d6c-946a-741925f508df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073080656 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.4073080656
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.990959068
Short name T291
Test name
Test status
Simulation time 41992728427 ps
CPU time 954.13 seconds
Started Jul 23 07:09:35 PM PDT 24
Finished Jul 23 07:25:31 PM PDT 24
Peak memory 224064 kb
Host smart-feab90dd-cca6-48cb-84e7-2a013297b7e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990959068 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.990959068
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.3182728691
Short name T302
Test name
Test status
Simulation time 44451501 ps
CPU time 1.59 seconds
Started Jul 23 07:11:10 PM PDT 24
Finished Jul 23 07:11:21 PM PDT 24
Peak memory 218832 kb
Host smart-ff331bb5-89bb-4d4e-8586-f3cd0bcd83ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182728691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.3182728691
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.4237765959
Short name T791
Test name
Test status
Simulation time 284172601 ps
CPU time 4.04 seconds
Started Jul 23 07:11:13 PM PDT 24
Finished Jul 23 07:11:27 PM PDT 24
Peak memory 219208 kb
Host smart-0269aeb9-e62c-41e6-8783-0eb9d7a4c6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237765959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.4237765959
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.635267273
Short name T551
Test name
Test status
Simulation time 41444887 ps
CPU time 1.4 seconds
Started Jul 23 07:11:18 PM PDT 24
Finished Jul 23 07:11:31 PM PDT 24
Peak memory 215676 kb
Host smart-fea6bf6f-6278-4d11-9450-c4cf644adb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635267273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.635267273
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.1817037823
Short name T688
Test name
Test status
Simulation time 38976585 ps
CPU time 1.26 seconds
Started Jul 23 07:11:12 PM PDT 24
Finished Jul 23 07:11:22 PM PDT 24
Peak memory 217504 kb
Host smart-0cff8eb7-ff76-4d0f-8896-9b9dab492a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817037823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.1817037823
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.1026684665
Short name T307
Test name
Test status
Simulation time 52846716 ps
CPU time 1.27 seconds
Started Jul 23 07:11:12 PM PDT 24
Finished Jul 23 07:11:23 PM PDT 24
Peak memory 219012 kb
Host smart-bbecd944-f5c5-46d3-b793-7b579f63382d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026684665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.1026684665
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.3363878093
Short name T776
Test name
Test status
Simulation time 64030545 ps
CPU time 1.41 seconds
Started Jul 23 07:11:18 PM PDT 24
Finished Jul 23 07:11:30 PM PDT 24
Peak memory 218788 kb
Host smart-b44a2db8-ed5f-4a19-abbe-5e61d07936a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363878093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.3363878093
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.2947384282
Short name T506
Test name
Test status
Simulation time 42763863 ps
CPU time 1.34 seconds
Started Jul 23 07:11:22 PM PDT 24
Finished Jul 23 07:11:35 PM PDT 24
Peak memory 218860 kb
Host smart-8aea3a53-1c0a-48e9-820c-6125ed3353d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947384282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2947384282
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.3169943465
Short name T601
Test name
Test status
Simulation time 46724764 ps
CPU time 1.01 seconds
Started Jul 23 07:11:16 PM PDT 24
Finished Jul 23 07:11:28 PM PDT 24
Peak memory 217748 kb
Host smart-44a0c010-bf63-4f71-9685-90dd20c95929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169943465 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3169943465
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.475344761
Short name T606
Test name
Test status
Simulation time 2275901282 ps
CPU time 75.54 seconds
Started Jul 23 07:11:16 PM PDT 24
Finished Jul 23 07:12:43 PM PDT 24
Peak memory 220768 kb
Host smart-85dad645-d579-421c-930e-8ea198ec135c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475344761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.475344761
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.497860680
Short name T543
Test name
Test status
Simulation time 23596920 ps
CPU time 1.16 seconds
Started Jul 23 07:11:19 PM PDT 24
Finished Jul 23 07:11:32 PM PDT 24
Peak memory 218944 kb
Host smart-83106558-a87a-43ba-ad08-1ce2decdafc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497860680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.497860680
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.3422162697
Short name T147
Test name
Test status
Simulation time 29801043 ps
CPU time 1.32 seconds
Started Jul 23 07:09:37 PM PDT 24
Finished Jul 23 07:09:45 PM PDT 24
Peak memory 220128 kb
Host smart-4909f51b-8149-4b0d-a844-798c202ebab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422162697 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.3422162697
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.1405569912
Short name T839
Test name
Test status
Simulation time 27438238 ps
CPU time 0.85 seconds
Started Jul 23 07:09:37 PM PDT 24
Finished Jul 23 07:09:43 PM PDT 24
Peak memory 215216 kb
Host smart-4c8bc0e4-eeb0-4b0d-aa12-c253d5a186b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405569912 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.1405569912
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.532352662
Short name T931
Test name
Test status
Simulation time 44161931 ps
CPU time 0.88 seconds
Started Jul 23 07:09:37 PM PDT 24
Finished Jul 23 07:09:44 PM PDT 24
Peak memory 216260 kb
Host smart-5679984a-bf8a-4f54-b3b5-f3fdb748b2e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532352662 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.532352662
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_err.581111527
Short name T629
Test name
Test status
Simulation time 279824511 ps
CPU time 1.29 seconds
Started Jul 23 07:09:37 PM PDT 24
Finished Jul 23 07:09:44 PM PDT 24
Peak memory 220072 kb
Host smart-e39e5658-6653-4714-9cd7-8dc84346ea85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581111527 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.581111527
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.1079922899
Short name T471
Test name
Test status
Simulation time 51257293 ps
CPU time 1.07 seconds
Started Jul 23 07:09:39 PM PDT 24
Finished Jul 23 07:09:48 PM PDT 24
Peak memory 215736 kb
Host smart-c39203f9-83b0-4c32-800b-a2188a1e545f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079922899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.1079922899
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.3692497451
Short name T80
Test name
Test status
Simulation time 25470030 ps
CPU time 1.05 seconds
Started Jul 23 07:09:37 PM PDT 24
Finished Jul 23 07:09:43 PM PDT 24
Peak memory 215704 kb
Host smart-cb02233d-dddf-41ea-961e-da806662fd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692497451 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3692497451
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.1896782758
Short name T103
Test name
Test status
Simulation time 16273888 ps
CPU time 0.98 seconds
Started Jul 23 07:09:35 PM PDT 24
Finished Jul 23 07:09:38 PM PDT 24
Peak memory 215544 kb
Host smart-73d3c31a-5680-491c-a1c5-19c66e6f505d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896782758 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.1896782758
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.3569935073
Short name T949
Test name
Test status
Simulation time 195261345 ps
CPU time 4.11 seconds
Started Jul 23 07:09:36 PM PDT 24
Finished Jul 23 07:09:43 PM PDT 24
Peak memory 220680 kb
Host smart-41082cac-21d0-484a-b5e5-600c301b7514
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569935073 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3569935073
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.4136639555
Short name T790
Test name
Test status
Simulation time 37481230943 ps
CPU time 806.07 seconds
Started Jul 23 07:09:37 PM PDT 24
Finished Jul 23 07:23:09 PM PDT 24
Peak memory 217992 kb
Host smart-17c7612e-a852-428d-a0cf-f0847fce13c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136639555 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.4136639555
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/231.edn_genbits.1822780516
Short name T592
Test name
Test status
Simulation time 41319749 ps
CPU time 1.28 seconds
Started Jul 23 07:11:12 PM PDT 24
Finished Jul 23 07:11:23 PM PDT 24
Peak memory 218416 kb
Host smart-403df1d8-f6b8-406a-a55b-43c194fb3efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822780516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1822780516
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.2687254357
Short name T465
Test name
Test status
Simulation time 54974936 ps
CPU time 1.26 seconds
Started Jul 23 07:11:11 PM PDT 24
Finished Jul 23 07:11:22 PM PDT 24
Peak memory 217536 kb
Host smart-b5a42ae3-665d-440a-b706-12f139eb84d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687254357 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.2687254357
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.1541513709
Short name T299
Test name
Test status
Simulation time 136781768 ps
CPU time 1.86 seconds
Started Jul 23 07:11:12 PM PDT 24
Finished Jul 23 07:11:23 PM PDT 24
Peak memory 220340 kb
Host smart-d67b42d8-8382-4a8f-8e51-7114bbf6d8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541513709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.1541513709
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.1234429119
Short name T836
Test name
Test status
Simulation time 21579259 ps
CPU time 1.08 seconds
Started Jul 23 07:11:13 PM PDT 24
Finished Jul 23 07:11:24 PM PDT 24
Peak memory 217628 kb
Host smart-7c7a1c03-7560-44da-a545-bad8894088c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234429119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.1234429119
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.4062950129
Short name T493
Test name
Test status
Simulation time 377064265 ps
CPU time 3.8 seconds
Started Jul 23 07:11:16 PM PDT 24
Finished Jul 23 07:11:31 PM PDT 24
Peak memory 219208 kb
Host smart-ba5ed5d8-7c10-496f-9a8f-ab6a38bb441c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062950129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.4062950129
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.286027564
Short name T969
Test name
Test status
Simulation time 245206628 ps
CPU time 2.71 seconds
Started Jul 23 07:11:23 PM PDT 24
Finished Jul 23 07:11:37 PM PDT 24
Peak memory 220144 kb
Host smart-63c60d07-14f5-42f0-9e72-3e10f56f53a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286027564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.286027564
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.3279408129
Short name T933
Test name
Test status
Simulation time 68833493 ps
CPU time 1.14 seconds
Started Jul 23 07:11:24 PM PDT 24
Finished Jul 23 07:11:36 PM PDT 24
Peak memory 217600 kb
Host smart-7c168e1f-c9c1-42f2-b25d-ae6603b077bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279408129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.3279408129
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.933299786
Short name T987
Test name
Test status
Simulation time 71692495 ps
CPU time 1.01 seconds
Started Jul 23 07:11:15 PM PDT 24
Finished Jul 23 07:11:26 PM PDT 24
Peak memory 217588 kb
Host smart-437c7416-975c-4d6d-aeb6-d45dcb3e4c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933299786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.933299786
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert_test.2637612080
Short name T468
Test name
Test status
Simulation time 28918849 ps
CPU time 1.16 seconds
Started Jul 23 07:09:40 PM PDT 24
Finished Jul 23 07:09:51 PM PDT 24
Peak memory 207072 kb
Host smart-324ce719-ce1c-47a4-a26f-15fbb68d41e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637612080 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.2637612080
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.3738697619
Short name T704
Test name
Test status
Simulation time 38246475 ps
CPU time 1.29 seconds
Started Jul 23 07:09:41 PM PDT 24
Finished Jul 23 07:09:53 PM PDT 24
Peak memory 216084 kb
Host smart-85c803b0-3a78-4dc5-8584-be8762bc92b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738697619 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.3738697619
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.1904695890
Short name T511
Test name
Test status
Simulation time 19405546 ps
CPU time 1.15 seconds
Started Jul 23 07:09:42 PM PDT 24
Finished Jul 23 07:09:55 PM PDT 24
Peak memory 224300 kb
Host smart-d81e3bb2-a593-4be2-a1c8-6d51bc83a433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904695890 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.1904695890
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.1591090845
Short name T553
Test name
Test status
Simulation time 38411002 ps
CPU time 1.08 seconds
Started Jul 23 07:09:40 PM PDT 24
Finished Jul 23 07:09:51 PM PDT 24
Peak memory 215716 kb
Host smart-be6bc4a5-35ce-4cb1-8872-b1f2bc5f0033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591090845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1591090845
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.3594126636
Short name T649
Test name
Test status
Simulation time 22627904 ps
CPU time 1.04 seconds
Started Jul 23 07:09:38 PM PDT 24
Finished Jul 23 07:09:46 PM PDT 24
Peak memory 216376 kb
Host smart-fbf83017-7fec-46c7-b9be-72feeb938628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594126636 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3594126636
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.1753945095
Short name T613
Test name
Test status
Simulation time 56579977 ps
CPU time 0.89 seconds
Started Jul 23 07:09:39 PM PDT 24
Finished Jul 23 07:09:48 PM PDT 24
Peak memory 215616 kb
Host smart-7e075afd-57c0-400d-a346-49520a2a4296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753945095 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.1753945095
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.1451316887
Short name T475
Test name
Test status
Simulation time 58791046 ps
CPU time 1.72 seconds
Started Jul 23 07:09:39 PM PDT 24
Finished Jul 23 07:09:48 PM PDT 24
Peak memory 217544 kb
Host smart-b1b7ce8d-55a1-4d17-9871-5743614a1944
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451316887 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.1451316887
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.3533347183
Short name T467
Test name
Test status
Simulation time 87892732216 ps
CPU time 2400.69 seconds
Started Jul 23 07:09:37 PM PDT 24
Finished Jul 23 07:49:45 PM PDT 24
Peak memory 232640 kb
Host smart-c7a8af4a-e46e-44f4-948c-a2109e2a350e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533347183 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.3533347183
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.814636049
Short name T772
Test name
Test status
Simulation time 49695507 ps
CPU time 1.28 seconds
Started Jul 23 07:11:13 PM PDT 24
Finished Jul 23 07:11:24 PM PDT 24
Peak memory 219104 kb
Host smart-c72fa3bc-1423-409a-a1c0-f282bdd55981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814636049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.814636049
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.4272560903
Short name T952
Test name
Test status
Simulation time 45018888 ps
CPU time 1.25 seconds
Started Jul 23 07:11:16 PM PDT 24
Finished Jul 23 07:11:29 PM PDT 24
Peak memory 217688 kb
Host smart-698ca1fd-a7ce-4ab7-9e31-e6b09572aed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272560903 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.4272560903
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1385975547
Short name T671
Test name
Test status
Simulation time 62290431 ps
CPU time 1.43 seconds
Started Jul 23 07:11:15 PM PDT 24
Finished Jul 23 07:11:27 PM PDT 24
Peak memory 219048 kb
Host smart-a73610a2-68bd-47e6-8ccb-795690b991b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385975547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1385975547
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.3282889613
Short name T962
Test name
Test status
Simulation time 49354539 ps
CPU time 0.96 seconds
Started Jul 23 07:11:16 PM PDT 24
Finished Jul 23 07:11:28 PM PDT 24
Peak memory 217588 kb
Host smart-4ed5f602-2089-4825-8686-ea16ccd5d800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282889613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3282889613
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.1714147232
Short name T41
Test name
Test status
Simulation time 263999417 ps
CPU time 3.73 seconds
Started Jul 23 07:11:14 PM PDT 24
Finished Jul 23 07:11:28 PM PDT 24
Peak memory 220436 kb
Host smart-f9a45149-28dc-4e58-add7-93aeacbce1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714147232 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.1714147232
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.3284527975
Short name T794
Test name
Test status
Simulation time 124227868 ps
CPU time 1.67 seconds
Started Jul 23 07:11:16 PM PDT 24
Finished Jul 23 07:11:29 PM PDT 24
Peak memory 219244 kb
Host smart-7c6157be-88a0-4a94-845a-9625c2d575a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284527975 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.3284527975
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.3141748305
Short name T538
Test name
Test status
Simulation time 40818543 ps
CPU time 1.12 seconds
Started Jul 23 07:11:12 PM PDT 24
Finished Jul 23 07:11:23 PM PDT 24
Peak memory 217840 kb
Host smart-f822eb71-f377-47c7-820e-0c9f38d1767a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141748305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.3141748305
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.127095399
Short name T276
Test name
Test status
Simulation time 50245670 ps
CPU time 1.17 seconds
Started Jul 23 07:11:20 PM PDT 24
Finished Jul 23 07:11:32 PM PDT 24
Peak memory 218668 kb
Host smart-cb206bd1-f8da-47f6-a194-5b0e805ad5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127095399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.127095399
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.2596591939
Short name T58
Test name
Test status
Simulation time 63512820 ps
CPU time 2.07 seconds
Started Jul 23 07:11:15 PM PDT 24
Finished Jul 23 07:11:28 PM PDT 24
Peak memory 220404 kb
Host smart-6c9e074a-218b-4dad-8196-e699710ff97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596591939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.2596591939
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.3720679704
Short name T337
Test name
Test status
Simulation time 44476373 ps
CPU time 1.05 seconds
Started Jul 23 07:11:15 PM PDT 24
Finished Jul 23 07:11:27 PM PDT 24
Peak memory 217576 kb
Host smart-6c0308a0-2012-416a-96a7-784d07ee0d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720679704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.3720679704
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.2056690509
Short name T269
Test name
Test status
Simulation time 27215888 ps
CPU time 1.23 seconds
Started Jul 23 07:09:48 PM PDT 24
Finished Jul 23 07:10:02 PM PDT 24
Peak memory 219028 kb
Host smart-0a180b97-0df8-4011-8335-dc1b9a94ee7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056690509 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.2056690509
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.2408430050
Short name T623
Test name
Test status
Simulation time 49401650 ps
CPU time 0.86 seconds
Started Jul 23 07:09:41 PM PDT 24
Finished Jul 23 07:09:54 PM PDT 24
Peak memory 215232 kb
Host smart-1585359c-f022-4ee1-8346-ace4cb4cc38d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408430050 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2408430050
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.913185490
Short name T178
Test name
Test status
Simulation time 12038050 ps
CPU time 0.88 seconds
Started Jul 23 07:09:40 PM PDT 24
Finished Jul 23 07:09:50 PM PDT 24
Peak memory 216708 kb
Host smart-8bccc8ba-329e-4792-9c5b-1d6af6d156ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913185490 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.913185490
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.4018008334
Short name T659
Test name
Test status
Simulation time 91073829 ps
CPU time 1.05 seconds
Started Jul 23 07:09:35 PM PDT 24
Finished Jul 23 07:09:38 PM PDT 24
Peak memory 217236 kb
Host smart-58f1e59b-9f94-479c-a41b-994d3b8f9109
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018008334 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.4018008334
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.251901371
Short name T116
Test name
Test status
Simulation time 27125129 ps
CPU time 1.3 seconds
Started Jul 23 07:09:38 PM PDT 24
Finished Jul 23 07:09:47 PM PDT 24
Peak memory 229800 kb
Host smart-398c7034-fdfe-4a45-98b8-df42d7b626f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251901371 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.251901371
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.2878160039
Short name T413
Test name
Test status
Simulation time 37744951 ps
CPU time 1.37 seconds
Started Jul 23 07:09:41 PM PDT 24
Finished Jul 23 07:09:52 PM PDT 24
Peak memory 217628 kb
Host smart-5b159b03-a7d9-43da-a91b-8d8625d1eb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878160039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.2878160039
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_smoke.2351651194
Short name T350
Test name
Test status
Simulation time 17628017 ps
CPU time 0.99 seconds
Started Jul 23 07:09:37 PM PDT 24
Finished Jul 23 07:09:44 PM PDT 24
Peak memory 207428 kb
Host smart-4f53cce1-4b58-4ea3-b129-725901a94257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351651194 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.2351651194
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.665527289
Short name T658
Test name
Test status
Simulation time 254356259 ps
CPU time 5.05 seconds
Started Jul 23 07:09:39 PM PDT 24
Finished Jul 23 07:09:53 PM PDT 24
Peak memory 217376 kb
Host smart-09ced48b-3e96-4583-82a9-027847d01213
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665527289 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.665527289
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.1168328995
Short name T229
Test name
Test status
Simulation time 321106370477 ps
CPU time 1824.59 seconds
Started Jul 23 07:09:39 PM PDT 24
Finished Jul 23 07:40:13 PM PDT 24
Peak memory 225948 kb
Host smart-a8e9fe19-6798-41ea-8436-c9833808b89f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168328995 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.1168328995
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.1532046161
Short name T827
Test name
Test status
Simulation time 38613177 ps
CPU time 1.41 seconds
Started Jul 23 07:11:11 PM PDT 24
Finished Jul 23 07:11:22 PM PDT 24
Peak memory 219124 kb
Host smart-60ba5777-8b37-4669-b310-d5d1614dadbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532046161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.1532046161
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.4027850541
Short name T528
Test name
Test status
Simulation time 31643869 ps
CPU time 1.3 seconds
Started Jul 23 07:11:15 PM PDT 24
Finished Jul 23 07:11:26 PM PDT 24
Peak memory 217668 kb
Host smart-9dc34dad-ca84-4378-8a65-3bfd3f6337e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027850541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.4027850541
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2759922066
Short name T841
Test name
Test status
Simulation time 247839563 ps
CPU time 3.24 seconds
Started Jul 23 07:11:16 PM PDT 24
Finished Jul 23 07:11:30 PM PDT 24
Peak memory 220132 kb
Host smart-dcae6105-d38b-4a9f-9aea-9cc02777323d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759922066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2759922066
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.2675672675
Short name T82
Test name
Test status
Simulation time 35044340 ps
CPU time 1.58 seconds
Started Jul 23 07:11:16 PM PDT 24
Finished Jul 23 07:11:28 PM PDT 24
Peak memory 219024 kb
Host smart-0eb5b1fe-fb6d-44aa-a204-9f14e2a000f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675672675 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.2675672675
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.4056242463
Short name T515
Test name
Test status
Simulation time 35292178 ps
CPU time 1.11 seconds
Started Jul 23 07:11:16 PM PDT 24
Finished Jul 23 07:11:28 PM PDT 24
Peak memory 220228 kb
Host smart-c737b739-c4c8-4973-be2f-e4bb3ebbbbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056242463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.4056242463
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.256127078
Short name T700
Test name
Test status
Simulation time 80856964 ps
CPU time 1.08 seconds
Started Jul 23 07:11:16 PM PDT 24
Finished Jul 23 07:11:28 PM PDT 24
Peak memory 215620 kb
Host smart-8a9a3ee7-54d4-4e41-8630-3b17c17013ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256127078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.256127078
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.4218146577
Short name T405
Test name
Test status
Simulation time 52954704 ps
CPU time 1.44 seconds
Started Jul 23 07:11:14 PM PDT 24
Finished Jul 23 07:11:26 PM PDT 24
Peak memory 218928 kb
Host smart-6e12ccfa-6c3e-48d4-a436-e2797919448f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218146577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.4218146577
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.4016983265
Short name T820
Test name
Test status
Simulation time 40663003 ps
CPU time 1.38 seconds
Started Jul 23 07:11:20 PM PDT 24
Finished Jul 23 07:11:33 PM PDT 24
Peak memory 218652 kb
Host smart-10dff3c5-6b4b-4ab4-a370-b23f38442ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016983265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.4016983265
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.3114866270
Short name T412
Test name
Test status
Simulation time 28898006 ps
CPU time 1.18 seconds
Started Jul 23 07:11:16 PM PDT 24
Finished Jul 23 07:11:28 PM PDT 24
Peak memory 217672 kb
Host smart-73b8faa3-55f9-46a9-a27a-62d637f79903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114866270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.3114866270
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.1278153579
Short name T559
Test name
Test status
Simulation time 41252372 ps
CPU time 1.62 seconds
Started Jul 23 07:11:14 PM PDT 24
Finished Jul 23 07:11:25 PM PDT 24
Peak memory 218820 kb
Host smart-f599fd46-e89e-4dc3-8ece-382ea7a4ffd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278153579 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.1278153579
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.1363879740
Short name T408
Test name
Test status
Simulation time 33625840 ps
CPU time 1.31 seconds
Started Jul 23 07:09:39 PM PDT 24
Finished Jul 23 07:09:50 PM PDT 24
Peak memory 220300 kb
Host smart-7f69a43a-cd4c-4e06-9276-737d7926789a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363879740 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.1363879740
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.4270698785
Short name T864
Test name
Test status
Simulation time 32341453 ps
CPU time 0.95 seconds
Started Jul 23 07:09:42 PM PDT 24
Finished Jul 23 07:09:54 PM PDT 24
Peak memory 215232 kb
Host smart-47c62853-cc79-4ca4-a491-a118779a129f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270698785 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.4270698785
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.1665038965
Short name T866
Test name
Test status
Simulation time 20887675 ps
CPU time 0.83 seconds
Started Jul 23 07:09:41 PM PDT 24
Finished Jul 23 07:09:53 PM PDT 24
Peak memory 216260 kb
Host smart-377a3984-04b7-417b-900d-81c9d896bfc6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665038965 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1665038965
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.3159172239
Short name T449
Test name
Test status
Simulation time 41665277 ps
CPU time 1.33 seconds
Started Jul 23 07:09:38 PM PDT 24
Finished Jul 23 07:09:46 PM PDT 24
Peak memory 217184 kb
Host smart-4d35b1c6-7066-48d9-90d5-9599fcbdd12b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159172239 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.3159172239
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.2018602303
Short name T523
Test name
Test status
Simulation time 18365921 ps
CPU time 1.02 seconds
Started Jul 23 07:09:38 PM PDT 24
Finished Jul 23 07:09:46 PM PDT 24
Peak memory 218640 kb
Host smart-e5db3d5a-8f43-4c06-8f3b-c8c92a8c14cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018602303 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.2018602303
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.2922081987
Short name T970
Test name
Test status
Simulation time 68103478 ps
CPU time 1.05 seconds
Started Jul 23 07:09:38 PM PDT 24
Finished Jul 23 07:09:47 PM PDT 24
Peak memory 217524 kb
Host smart-93d481f0-f7bd-4b83-a4e2-63013affbc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922081987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.2922081987
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.307587626
Short name T96
Test name
Test status
Simulation time 33084562 ps
CPU time 0.86 seconds
Started Jul 23 07:09:42 PM PDT 24
Finished Jul 23 07:09:54 PM PDT 24
Peak memory 215964 kb
Host smart-c78b5f5e-cdb7-4e54-a919-fbe8a028d0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307587626 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.307587626
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.3518452336
Short name T787
Test name
Test status
Simulation time 19973079 ps
CPU time 0.94 seconds
Started Jul 23 07:09:40 PM PDT 24
Finished Jul 23 07:09:50 PM PDT 24
Peak memory 214976 kb
Host smart-4ca96645-5884-4122-9568-e11c3d27015c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518452336 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.3518452336
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.1329203388
Short name T615
Test name
Test status
Simulation time 606669819 ps
CPU time 4.66 seconds
Started Jul 23 07:09:37 PM PDT 24
Finished Jul 23 07:09:47 PM PDT 24
Peak memory 217720 kb
Host smart-1adf6ec2-6377-45b9-a697-9cee9b509832
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329203388 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.1329203388
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.2471846010
Short name T692
Test name
Test status
Simulation time 90557755349 ps
CPU time 1015.71 seconds
Started Jul 23 07:09:41 PM PDT 24
Finished Jul 23 07:26:47 PM PDT 24
Peak memory 223216 kb
Host smart-e815c77a-e5ab-437f-976d-e8e189863b16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471846010 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.2471846010
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.1151558416
Short name T708
Test name
Test status
Simulation time 57889832 ps
CPU time 1.53 seconds
Started Jul 23 07:11:14 PM PDT 24
Finished Jul 23 07:11:26 PM PDT 24
Peak memory 218720 kb
Host smart-fd87a34e-da38-4a12-871e-cd53f623a125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151558416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.1151558416
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.1442937615
Short name T654
Test name
Test status
Simulation time 67256913 ps
CPU time 1.33 seconds
Started Jul 23 07:11:12 PM PDT 24
Finished Jul 23 07:11:23 PM PDT 24
Peak memory 218712 kb
Host smart-1c8e2c71-5f91-4624-a956-af5fdce1cfae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442937615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1442937615
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.740675397
Short name T561
Test name
Test status
Simulation time 97916908 ps
CPU time 0.96 seconds
Started Jul 23 07:11:16 PM PDT 24
Finished Jul 23 07:11:28 PM PDT 24
Peak memory 217584 kb
Host smart-94d2293f-a92b-40a6-bee1-9c8740d85384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740675397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.740675397
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.3048130829
Short name T595
Test name
Test status
Simulation time 55426049 ps
CPU time 1.63 seconds
Started Jul 23 07:11:16 PM PDT 24
Finished Jul 23 07:11:29 PM PDT 24
Peak memory 218844 kb
Host smart-8574205c-faac-4b50-968c-6c281ddfb44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048130829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.3048130829
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.1806053835
Short name T868
Test name
Test status
Simulation time 42774276 ps
CPU time 1.05 seconds
Started Jul 23 07:11:16 PM PDT 24
Finished Jul 23 07:11:28 PM PDT 24
Peak memory 217468 kb
Host smart-ac56f3b4-e8e2-4d79-b6e7-9d9dca5effe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806053835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.1806053835
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.3992493275
Short name T930
Test name
Test status
Simulation time 102263303 ps
CPU time 1.28 seconds
Started Jul 23 07:11:14 PM PDT 24
Finished Jul 23 07:11:25 PM PDT 24
Peak memory 217968 kb
Host smart-8243239d-c4ee-453b-9f1b-3a3f70522f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992493275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.3992493275
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.1683052415
Short name T604
Test name
Test status
Simulation time 181316200 ps
CPU time 1.18 seconds
Started Jul 23 07:11:15 PM PDT 24
Finished Jul 23 07:11:27 PM PDT 24
Peak memory 217628 kb
Host smart-adbb94dc-f0a2-466f-bf4f-fdad124b2023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683052415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.1683052415
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.1179991245
Short name T536
Test name
Test status
Simulation time 49434146 ps
CPU time 1.19 seconds
Started Jul 23 07:11:20 PM PDT 24
Finished Jul 23 07:11:33 PM PDT 24
Peak memory 217508 kb
Host smart-7072bbc0-e0ce-42fd-aa15-bcb190e14e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179991245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.1179991245
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.4163126144
Short name T102
Test name
Test status
Simulation time 45492885 ps
CPU time 1.41 seconds
Started Jul 23 07:11:16 PM PDT 24
Finished Jul 23 07:11:28 PM PDT 24
Peak memory 217852 kb
Host smart-c9368dc7-7963-4e57-b7e6-3bc49514fab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163126144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.4163126144
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.1544781188
Short name T516
Test name
Test status
Simulation time 175993601 ps
CPU time 1.03 seconds
Started Jul 23 07:11:18 PM PDT 24
Finished Jul 23 07:11:30 PM PDT 24
Peak memory 217620 kb
Host smart-f497bbc8-aaea-48f4-ba12-a3ef8ac8072c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544781188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.1544781188
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.3874410759
Short name T890
Test name
Test status
Simulation time 31640325 ps
CPU time 1.3 seconds
Started Jul 23 07:09:42 PM PDT 24
Finished Jul 23 07:09:55 PM PDT 24
Peak memory 216060 kb
Host smart-982b8dc0-eb3b-46e9-8b1e-a64e478f9ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874410759 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.3874410759
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1784118033
Short name T830
Test name
Test status
Simulation time 19718849 ps
CPU time 0.96 seconds
Started Jul 23 07:09:40 PM PDT 24
Finished Jul 23 07:09:50 PM PDT 24
Peak memory 215584 kb
Host smart-2c8565ae-73be-4b8e-a997-2e09c699c825
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784118033 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1784118033
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.2838705832
Short name T375
Test name
Test status
Simulation time 75860989 ps
CPU time 1.05 seconds
Started Jul 23 07:09:39 PM PDT 24
Finished Jul 23 07:09:49 PM PDT 24
Peak memory 215976 kb
Host smart-777be9ec-bb51-41b1-bd7e-cf1cbe167940
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838705832 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.2838705832
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.1141772202
Short name T208
Test name
Test status
Simulation time 25343453 ps
CPU time 0.85 seconds
Started Jul 23 07:09:41 PM PDT 24
Finished Jul 23 07:09:52 PM PDT 24
Peak memory 218776 kb
Host smart-ed408e18-a06e-4f68-94de-66748cf7c23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141772202 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.1141772202
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.2974777340
Short name T724
Test name
Test status
Simulation time 58291061 ps
CPU time 1.35 seconds
Started Jul 23 07:09:37 PM PDT 24
Finished Jul 23 07:09:44 PM PDT 24
Peak memory 219060 kb
Host smart-6f5e82b6-6a64-41f8-af9d-38531e8a4dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974777340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.2974777340
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.471521416
Short name T539
Test name
Test status
Simulation time 39333174 ps
CPU time 0.91 seconds
Started Jul 23 07:09:40 PM PDT 24
Finished Jul 23 07:09:50 PM PDT 24
Peak memory 215208 kb
Host smart-0fcdde20-a6ba-4907-9b13-dd260efee67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471521416 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.471521416
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.71634579
Short name T547
Test name
Test status
Simulation time 26290958 ps
CPU time 1 seconds
Started Jul 23 07:09:42 PM PDT 24
Finished Jul 23 07:09:55 PM PDT 24
Peak memory 215596 kb
Host smart-c3db188d-c71c-4b9f-b262-70c6e5bf1182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71634579 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.71634579
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.2725734137
Short name T696
Test name
Test status
Simulation time 243224714 ps
CPU time 2.73 seconds
Started Jul 23 07:09:39 PM PDT 24
Finished Jul 23 07:09:50 PM PDT 24
Peak memory 215620 kb
Host smart-b7f4a00d-c26e-41f3-b05e-52c632d2fd30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725734137 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2725734137
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.4042166399
Short name T224
Test name
Test status
Simulation time 90824690837 ps
CPU time 2367.74 seconds
Started Jul 23 07:09:36 PM PDT 24
Finished Jul 23 07:49:09 PM PDT 24
Peak memory 232264 kb
Host smart-18c425bf-54ee-4d08-b12f-34f3be55aff0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042166399 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.4042166399
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.4204201002
Short name T981
Test name
Test status
Simulation time 53082751 ps
CPU time 0.99 seconds
Started Jul 23 07:11:22 PM PDT 24
Finished Jul 23 07:11:34 PM PDT 24
Peak memory 219844 kb
Host smart-036584b2-1b9b-4230-a810-796daac73c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204201002 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.4204201002
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.3295601686
Short name T782
Test name
Test status
Simulation time 45789717 ps
CPU time 1.28 seconds
Started Jul 23 07:11:18 PM PDT 24
Finished Jul 23 07:11:31 PM PDT 24
Peak memory 220248 kb
Host smart-1fb6ab10-fec1-40f3-95be-9209979e826f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295601686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.3295601686
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1615802575
Short name T513
Test name
Test status
Simulation time 86264287 ps
CPU time 1.34 seconds
Started Jul 23 07:11:19 PM PDT 24
Finished Jul 23 07:11:32 PM PDT 24
Peak memory 217840 kb
Host smart-1272bd89-4ff5-4fb2-8f25-b902784bc5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615802575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1615802575
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.3999741845
Short name T437
Test name
Test status
Simulation time 84431942 ps
CPU time 1.44 seconds
Started Jul 23 07:11:26 PM PDT 24
Finished Jul 23 07:11:38 PM PDT 24
Peak memory 218732 kb
Host smart-8ff5068f-3bb3-411f-8eec-c39e3465739c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999741845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.3999741845
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.2286672506
Short name T660
Test name
Test status
Simulation time 82572945 ps
CPU time 1.74 seconds
Started Jul 23 07:11:21 PM PDT 24
Finished Jul 23 07:11:34 PM PDT 24
Peak memory 220868 kb
Host smart-12e0902c-b8b8-4742-86d6-ba7ee95b7e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286672506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.2286672506
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.349462766
Short name T644
Test name
Test status
Simulation time 53039366 ps
CPU time 1.3 seconds
Started Jul 23 07:11:27 PM PDT 24
Finished Jul 23 07:11:38 PM PDT 24
Peak memory 219836 kb
Host smart-913e7026-5a1c-40d7-b3f5-07e270968a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349462766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.349462766
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3936857255
Short name T593
Test name
Test status
Simulation time 26730778 ps
CPU time 1.17 seconds
Started Jul 23 07:11:23 PM PDT 24
Finished Jul 23 07:11:35 PM PDT 24
Peak memory 219044 kb
Host smart-14ae959d-5e82-4a2a-9ae1-6ce4295e45f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936857255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3936857255
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.634835840
Short name T960
Test name
Test status
Simulation time 81013066 ps
CPU time 1.17 seconds
Started Jul 23 07:11:20 PM PDT 24
Finished Jul 23 07:11:32 PM PDT 24
Peak memory 220440 kb
Host smart-4e452072-8722-4f85-8b3d-7f1f1fbae5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634835840 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.634835840
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.166903517
Short name T69
Test name
Test status
Simulation time 49206830 ps
CPU time 1.4 seconds
Started Jul 23 07:11:20 PM PDT 24
Finished Jul 23 07:11:33 PM PDT 24
Peak memory 220356 kb
Host smart-7066af8e-f098-4979-bd0c-155862bf1db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166903517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.166903517
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.2647517561
Short name T854
Test name
Test status
Simulation time 26231346 ps
CPU time 1.2 seconds
Started Jul 23 07:09:43 PM PDT 24
Finished Jul 23 07:09:57 PM PDT 24
Peak memory 220868 kb
Host smart-e3260b4b-4f3f-40f0-a72f-5283ed113062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647517561 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2647517561
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.1929762043
Short name T749
Test name
Test status
Simulation time 19861454 ps
CPU time 0.8 seconds
Started Jul 23 07:09:39 PM PDT 24
Finished Jul 23 07:09:49 PM PDT 24
Peak memory 206760 kb
Host smart-a0dd818c-1e25-4aa7-9a24-34835c44a36a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929762043 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.1929762043
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.3854447062
Short name T56
Test name
Test status
Simulation time 15237823 ps
CPU time 0.85 seconds
Started Jul 23 07:09:40 PM PDT 24
Finished Jul 23 07:09:51 PM PDT 24
Peak memory 216660 kb
Host smart-c90d8bdc-3c1d-4eb5-a8e9-4097502d5b55
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854447062 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.3854447062
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_genbits.1573196914
Short name T392
Test name
Test status
Simulation time 63578510 ps
CPU time 1.07 seconds
Started Jul 23 07:09:42 PM PDT 24
Finished Jul 23 07:09:55 PM PDT 24
Peak memory 215800 kb
Host smart-ff030781-7da2-4a68-a23a-40de2fcfce66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573196914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.1573196914
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.2343761098
Short name T570
Test name
Test status
Simulation time 27968974 ps
CPU time 0.92 seconds
Started Jul 23 07:09:43 PM PDT 24
Finished Jul 23 07:09:56 PM PDT 24
Peak memory 215764 kb
Host smart-f337c936-e3d4-4f8e-ba75-de64c337d75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343761098 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.2343761098
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.519891910
Short name T667
Test name
Test status
Simulation time 18113560 ps
CPU time 0.97 seconds
Started Jul 23 07:09:33 PM PDT 24
Finished Jul 23 07:09:36 PM PDT 24
Peak memory 215632 kb
Host smart-fe3affff-3004-49c4-94c6-ea0de9554618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519891910 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.519891910
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.2146893035
Short name T48
Test name
Test status
Simulation time 346566785 ps
CPU time 2.64 seconds
Started Jul 23 07:09:43 PM PDT 24
Finished Jul 23 07:09:59 PM PDT 24
Peak memory 217544 kb
Host smart-3909be1b-5802-4bfd-a234-2dd9234e27f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146893035 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2146893035
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.2800750505
Short name T959
Test name
Test status
Simulation time 388779014139 ps
CPU time 2292.54 seconds
Started Jul 23 07:09:42 PM PDT 24
Finished Jul 23 07:48:07 PM PDT 24
Peak memory 227784 kb
Host smart-f21e6284-92b4-4c77-bc5a-58261beab39a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800750505 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.2800750505
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.1384333182
Short name T669
Test name
Test status
Simulation time 49243792 ps
CPU time 1.66 seconds
Started Jul 23 07:11:23 PM PDT 24
Finished Jul 23 07:11:36 PM PDT 24
Peak memory 217724 kb
Host smart-26dfe406-8ad3-40c2-b70f-4c8c07265fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384333182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.1384333182
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.765895705
Short name T675
Test name
Test status
Simulation time 39818547 ps
CPU time 1.27 seconds
Started Jul 23 07:11:19 PM PDT 24
Finished Jul 23 07:11:31 PM PDT 24
Peak memory 218992 kb
Host smart-8773f3d2-a32e-469f-849c-d4a8635e72d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765895705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.765895705
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.40614789
Short name T500
Test name
Test status
Simulation time 90732481 ps
CPU time 1.33 seconds
Started Jul 23 07:11:26 PM PDT 24
Finished Jul 23 07:11:38 PM PDT 24
Peak memory 219028 kb
Host smart-99236a4c-8256-4ae0-8150-360d43d28abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40614789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.40614789
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.294135333
Short name T393
Test name
Test status
Simulation time 58630393 ps
CPU time 1.67 seconds
Started Jul 23 07:11:22 PM PDT 24
Finished Jul 23 07:11:35 PM PDT 24
Peak memory 218780 kb
Host smart-2a6a61f9-f38c-4ff4-beac-0353abb40525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294135333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.294135333
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.3742737822
Short name T717
Test name
Test status
Simulation time 9101597745 ps
CPU time 123.1 seconds
Started Jul 23 07:11:21 PM PDT 24
Finished Jul 23 07:13:36 PM PDT 24
Peak memory 220724 kb
Host smart-54b5efd5-4162-493b-83a6-687b90f6baaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742737822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3742737822
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.4132882097
Short name T650
Test name
Test status
Simulation time 31594081 ps
CPU time 1.44 seconds
Started Jul 23 07:11:18 PM PDT 24
Finished Jul 23 07:11:30 PM PDT 24
Peak memory 218756 kb
Host smart-80aee56a-8ef5-4f08-93c0-a602447dd269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132882097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.4132882097
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.2672052682
Short name T733
Test name
Test status
Simulation time 50501449 ps
CPU time 1.24 seconds
Started Jul 23 07:11:20 PM PDT 24
Finished Jul 23 07:11:33 PM PDT 24
Peak memory 218680 kb
Host smart-b17d1954-c319-49ac-b6e2-e529c25c4d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672052682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2672052682
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.3737756820
Short name T76
Test name
Test status
Simulation time 33636092 ps
CPU time 1.29 seconds
Started Jul 23 07:11:19 PM PDT 24
Finished Jul 23 07:11:31 PM PDT 24
Peak memory 217648 kb
Host smart-48ccde92-3dfd-4732-9945-1bb8b6a9e170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737756820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.3737756820
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.3608837338
Short name T657
Test name
Test status
Simulation time 81838512 ps
CPU time 1.01 seconds
Started Jul 23 07:11:20 PM PDT 24
Finished Jul 23 07:11:32 PM PDT 24
Peak memory 219784 kb
Host smart-fbe71d77-84b8-4c84-8ed4-a277be0a7907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608837338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3608837338
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.1549436
Short name T497
Test name
Test status
Simulation time 86207192 ps
CPU time 1.21 seconds
Started Jul 23 07:11:24 PM PDT 24
Finished Jul 23 07:11:37 PM PDT 24
Peak memory 217572 kb
Host smart-5bda669f-6389-4e57-8f12-db5e6cb623ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1549436
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.927703017
Short name T108
Test name
Test status
Simulation time 66753825 ps
CPU time 1.11 seconds
Started Jul 23 07:09:38 PM PDT 24
Finished Jul 23 07:09:47 PM PDT 24
Peak memory 220040 kb
Host smart-164040a3-43bf-43a1-bf89-482ad7c97663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927703017 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.927703017
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.651074844
Short name T585
Test name
Test status
Simulation time 36782304 ps
CPU time 0.83 seconds
Started Jul 23 07:09:46 PM PDT 24
Finished Jul 23 07:09:59 PM PDT 24
Peak memory 206836 kb
Host smart-7bf6ca8c-21f5-43c2-81c7-5a5f66198538
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651074844 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.651074844
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.2819713808
Short name T795
Test name
Test status
Simulation time 177622322 ps
CPU time 1.06 seconds
Started Jul 23 07:09:40 PM PDT 24
Finished Jul 23 07:09:51 PM PDT 24
Peak memory 217068 kb
Host smart-4c41e61b-0cc8-4333-9e83-2c1849456eff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819713808 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.2819713808
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.2011591727
Short name T635
Test name
Test status
Simulation time 19010636 ps
CPU time 1.03 seconds
Started Jul 23 07:09:42 PM PDT 24
Finished Jul 23 07:09:55 PM PDT 24
Peak memory 218784 kb
Host smart-c69248b8-7105-4f53-be09-7eec5a118c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011591727 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2011591727
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.2170113139
Short name T945
Test name
Test status
Simulation time 102544850 ps
CPU time 1.16 seconds
Started Jul 23 07:09:42 PM PDT 24
Finished Jul 23 07:09:55 PM PDT 24
Peak memory 220116 kb
Host smart-bb5b55d5-6aa2-496b-9c5a-4a0442242bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170113139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.2170113139
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.2495848495
Short name T780
Test name
Test status
Simulation time 32005674 ps
CPU time 1 seconds
Started Jul 23 07:09:40 PM PDT 24
Finished Jul 23 07:09:51 PM PDT 24
Peak memory 215724 kb
Host smart-55ba241e-aec0-4151-827a-62eb2a976b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495848495 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2495848495
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.2438617028
Short name T759
Test name
Test status
Simulation time 63702835 ps
CPU time 0.93 seconds
Started Jul 23 07:09:43 PM PDT 24
Finished Jul 23 07:09:56 PM PDT 24
Peak memory 215332 kb
Host smart-fc0a595f-d803-4db5-9598-b5277830f428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438617028 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.2438617028
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.3501520138
Short name T346
Test name
Test status
Simulation time 319300768 ps
CPU time 3.7 seconds
Started Jul 23 07:09:42 PM PDT 24
Finished Jul 23 07:09:58 PM PDT 24
Peak memory 215688 kb
Host smart-23839411-8d90-46bc-903e-246514855706
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501520138 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.3501520138
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/290.edn_genbits.999873630
Short name T381
Test name
Test status
Simulation time 149317792 ps
CPU time 3.24 seconds
Started Jul 23 07:11:22 PM PDT 24
Finished Jul 23 07:11:36 PM PDT 24
Peak memory 220468 kb
Host smart-f8518b9c-fff5-4c59-bde5-7e6c7db7fdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999873630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.999873630
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.2626760146
Short name T300
Test name
Test status
Simulation time 244319710 ps
CPU time 1.16 seconds
Started Jul 23 07:11:20 PM PDT 24
Finished Jul 23 07:11:33 PM PDT 24
Peak memory 217504 kb
Host smart-8a37a34b-b4f2-429d-be9c-3d9f17bc90da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626760146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2626760146
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.3773196127
Short name T379
Test name
Test status
Simulation time 34311801 ps
CPU time 1.47 seconds
Started Jul 23 07:11:17 PM PDT 24
Finished Jul 23 07:11:29 PM PDT 24
Peak memory 219704 kb
Host smart-9e3d6566-9df5-48c2-aeb8-9096fe346dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773196127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.3773196127
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.4210940296
Short name T627
Test name
Test status
Simulation time 74702857 ps
CPU time 1.49 seconds
Started Jul 23 07:11:18 PM PDT 24
Finished Jul 23 07:11:31 PM PDT 24
Peak memory 219132 kb
Host smart-b63277b9-fe37-4c10-9155-27bfa2c726c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210940296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.4210940296
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3960471595
Short name T940
Test name
Test status
Simulation time 119596252 ps
CPU time 3.15 seconds
Started Jul 23 07:11:19 PM PDT 24
Finished Jul 23 07:11:33 PM PDT 24
Peak memory 218888 kb
Host smart-0dccf3e2-e48c-4e15-a72a-78cb4363d813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960471595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3960471595
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.1424797641
Short name T975
Test name
Test status
Simulation time 279902106 ps
CPU time 1.3 seconds
Started Jul 23 07:11:25 PM PDT 24
Finished Jul 23 07:11:37 PM PDT 24
Peak memory 219240 kb
Host smart-1c7399d0-2544-47c1-9999-b60b62e4d2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424797641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.1424797641
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3367156156
Short name T391
Test name
Test status
Simulation time 99592860 ps
CPU time 1.16 seconds
Started Jul 23 07:11:19 PM PDT 24
Finished Jul 23 07:11:31 PM PDT 24
Peak memory 219928 kb
Host smart-f4df4e0e-5997-434e-bea3-bed4c09cea87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367156156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3367156156
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.3253138364
Short name T736
Test name
Test status
Simulation time 233446335 ps
CPU time 1.22 seconds
Started Jul 23 07:11:19 PM PDT 24
Finished Jul 23 07:11:31 PM PDT 24
Peak memory 217708 kb
Host smart-23aa5fbf-a502-4e32-9f6d-6d826261d865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253138364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.3253138364
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.108979717
Short name T757
Test name
Test status
Simulation time 202696316 ps
CPU time 1.29 seconds
Started Jul 23 07:11:18 PM PDT 24
Finished Jul 23 07:11:31 PM PDT 24
Peak memory 219160 kb
Host smart-3d84add7-83b1-4acf-9a11-cd2ded2184dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108979717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.108979717
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.672023080
Short name T310
Test name
Test status
Simulation time 95809805 ps
CPU time 1.33 seconds
Started Jul 23 07:11:23 PM PDT 24
Finished Jul 23 07:11:35 PM PDT 24
Peak memory 219164 kb
Host smart-a2a34379-9855-4d0f-a27f-94cd572f254b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672023080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.672023080
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.733359246
Short name T450
Test name
Test status
Simulation time 129411900 ps
CPU time 1.01 seconds
Started Jul 23 07:08:49 PM PDT 24
Finished Jul 23 07:08:53 PM PDT 24
Peak memory 219020 kb
Host smart-9eb13a49-3452-4dab-b9a6-407671c67f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733359246 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.733359246
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.1362971199
Short name T540
Test name
Test status
Simulation time 59634926 ps
CPU time 0.89 seconds
Started Jul 23 07:08:50 PM PDT 24
Finished Jul 23 07:08:54 PM PDT 24
Peak memory 207024 kb
Host smart-23082480-27c9-4aaf-b98e-67af815acb4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362971199 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.1362971199
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.1378807895
Short name T455
Test name
Test status
Simulation time 10786395 ps
CPU time 0.86 seconds
Started Jul 23 07:08:47 PM PDT 24
Finished Jul 23 07:08:50 PM PDT 24
Peak memory 216232 kb
Host smart-a6710a9e-f528-4558-a50c-01f15b18a3fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378807895 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1378807895
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.1904248335
Short name T141
Test name
Test status
Simulation time 150152428 ps
CPU time 1.06 seconds
Started Jul 23 07:08:42 PM PDT 24
Finished Jul 23 07:08:45 PM PDT 24
Peak memory 217348 kb
Host smart-0d884344-3d65-4837-bade-ee183fada166
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904248335 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.1904248335
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.1697516504
Short name T78
Test name
Test status
Simulation time 45285514 ps
CPU time 1.13 seconds
Started Jul 23 07:08:46 PM PDT 24
Finished Jul 23 07:08:48 PM PDT 24
Peak memory 219840 kb
Host smart-2b70a573-c12f-4ec9-bd59-c97a75fec827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697516504 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.1697516504
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.2539748099
Short name T432
Test name
Test status
Simulation time 88798095 ps
CPU time 1.28 seconds
Started Jul 23 07:08:41 PM PDT 24
Finished Jul 23 07:08:45 PM PDT 24
Peak memory 219176 kb
Host smart-9eaf2156-8408-4b61-85ba-f43dbe1a1992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539748099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.2539748099
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.1531744023
Short name T31
Test name
Test status
Simulation time 24741077 ps
CPU time 0.89 seconds
Started Jul 23 07:08:43 PM PDT 24
Finished Jul 23 07:08:46 PM PDT 24
Peak memory 216336 kb
Host smart-85671ea8-2250-4557-8c8e-27f3d83e8bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531744023 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.1531744023
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.2648073152
Short name T29
Test name
Test status
Simulation time 18807427 ps
CPU time 1.05 seconds
Started Jul 23 07:08:42 PM PDT 24
Finished Jul 23 07:08:45 PM PDT 24
Peak memory 207392 kb
Host smart-8bb652ed-4ca5-4a1e-b913-3e1a04f83675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648073152 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.2648073152
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.1818177944
Short name T20
Test name
Test status
Simulation time 852710371 ps
CPU time 4 seconds
Started Jul 23 07:08:46 PM PDT 24
Finished Jul 23 07:08:51 PM PDT 24
Peak memory 235628 kb
Host smart-6ec5e27d-a0ab-4d21-b26d-4e42e7311c21
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818177944 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.1818177944
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.1784477156
Short name T492
Test name
Test status
Simulation time 14568797 ps
CPU time 0.98 seconds
Started Jul 23 07:08:44 PM PDT 24
Finished Jul 23 07:08:46 PM PDT 24
Peak memory 215636 kb
Host smart-b28146a1-9087-4c6c-b280-7a61e5176adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784477156 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.1784477156
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.1446205243
Short name T792
Test name
Test status
Simulation time 89615968 ps
CPU time 2.32 seconds
Started Jul 23 07:08:41 PM PDT 24
Finished Jul 23 07:08:45 PM PDT 24
Peak memory 217660 kb
Host smart-d9b456dc-81bd-4a03-89b9-fd0cb9bca11d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446205243 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1446205243
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3297676988
Short name T876
Test name
Test status
Simulation time 398641239255 ps
CPU time 2453.77 seconds
Started Jul 23 07:08:43 PM PDT 24
Finished Jul 23 07:49:39 PM PDT 24
Peak memory 231368 kb
Host smart-97dd1c46-f26a-4457-b015-5a3413888fa8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297676988 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3297676988
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.3927824155
Short name T597
Test name
Test status
Simulation time 88687592 ps
CPU time 1.21 seconds
Started Jul 23 07:09:43 PM PDT 24
Finished Jul 23 07:09:58 PM PDT 24
Peak memory 220168 kb
Host smart-09e639f1-ac83-4476-b7bc-4f4c6cb2b774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927824155 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.3927824155
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.2052503833
Short name T946
Test name
Test status
Simulation time 20502058 ps
CPU time 1.01 seconds
Started Jul 23 07:09:42 PM PDT 24
Finished Jul 23 07:09:55 PM PDT 24
Peak memory 207032 kb
Host smart-204122df-9e3d-4fd8-aa98-125e7904c103
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052503833 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.2052503833
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.2347921661
Short name T163
Test name
Test status
Simulation time 18642439 ps
CPU time 0.83 seconds
Started Jul 23 07:09:43 PM PDT 24
Finished Jul 23 07:09:56 PM PDT 24
Peak memory 215804 kb
Host smart-be06f2e9-e4cd-47e9-8533-8b671db64dd3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347921661 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.2347921661
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.1592954210
Short name T150
Test name
Test status
Simulation time 35964056 ps
CPU time 1.29 seconds
Started Jul 23 07:09:40 PM PDT 24
Finished Jul 23 07:09:51 PM PDT 24
Peak memory 217396 kb
Host smart-cc078272-8e5d-4a50-9ed0-04e121bcd642
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592954210 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.1592954210
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.1373566863
Short name T530
Test name
Test status
Simulation time 30382865 ps
CPU time 1.02 seconds
Started Jul 23 07:09:43 PM PDT 24
Finished Jul 23 07:09:56 PM PDT 24
Peak memory 224108 kb
Host smart-490dc204-ab2d-4e7a-a5fb-3b31354fba30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373566863 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.1373566863
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.3331680261
Short name T817
Test name
Test status
Simulation time 59599761 ps
CPU time 1.08 seconds
Started Jul 23 07:09:40 PM PDT 24
Finished Jul 23 07:09:50 PM PDT 24
Peak memory 217692 kb
Host smart-a192b0c2-75ab-45d0-83a4-aecf1032eab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331680261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3331680261
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.1332211349
Short name T98
Test name
Test status
Simulation time 24494830 ps
CPU time 0.95 seconds
Started Jul 23 07:09:43 PM PDT 24
Finished Jul 23 07:09:56 PM PDT 24
Peak memory 215872 kb
Host smart-d4921c1a-d143-4593-9914-4c37823a717e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332211349 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.1332211349
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.3745528666
Short name T637
Test name
Test status
Simulation time 23303578 ps
CPU time 0.88 seconds
Started Jul 23 07:09:46 PM PDT 24
Finished Jul 23 07:09:59 PM PDT 24
Peak memory 215628 kb
Host smart-c3c02dd9-cbc7-437a-9ed9-24482305ded5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745528666 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3745528666
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.3649473469
Short name T238
Test name
Test status
Simulation time 1349713018 ps
CPU time 2.74 seconds
Started Jul 23 07:09:42 PM PDT 24
Finished Jul 23 07:09:57 PM PDT 24
Peak memory 217784 kb
Host smart-b3fe5a8a-2046-4f7a-961d-605e7d54d40a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649473469 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.3649473469
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.605386930
Short name T562
Test name
Test status
Simulation time 207825248774 ps
CPU time 1881.05 seconds
Started Jul 23 07:09:43 PM PDT 24
Finished Jul 23 07:41:17 PM PDT 24
Peak memory 233680 kb
Host smart-d20b9a55-301f-4d70-8acd-9f1feaa9141b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605386930 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.605386930
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.1839384621
Short name T926
Test name
Test status
Simulation time 51266789 ps
CPU time 1.21 seconds
Started Jul 23 07:09:43 PM PDT 24
Finished Jul 23 07:09:58 PM PDT 24
Peak memory 215972 kb
Host smart-fe3f4045-efd1-458d-a88e-c48a3f19a390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839384621 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1839384621
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.32941434
Short name T663
Test name
Test status
Simulation time 13499948 ps
CPU time 0.87 seconds
Started Jul 23 07:09:41 PM PDT 24
Finished Jul 23 07:09:51 PM PDT 24
Peak memory 207276 kb
Host smart-72efa5ba-fd3f-4f0f-9765-f3e030271a9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32941434 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.32941434
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.2246041125
Short name T210
Test name
Test status
Simulation time 26811816 ps
CPU time 0.9 seconds
Started Jul 23 07:09:41 PM PDT 24
Finished Jul 23 07:09:54 PM PDT 24
Peak memory 216612 kb
Host smart-f5fdcc97-1832-470f-825b-b82b82cf628c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246041125 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2246041125
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_err.1444807960
Short name T617
Test name
Test status
Simulation time 193064675 ps
CPU time 0.98 seconds
Started Jul 23 07:09:39 PM PDT 24
Finished Jul 23 07:09:49 PM PDT 24
Peak memory 221008 kb
Host smart-13b989c1-4677-4b15-aedf-f38b58e154b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444807960 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.1444807960
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.1109461945
Short name T356
Test name
Test status
Simulation time 71188986 ps
CPU time 1.03 seconds
Started Jul 23 07:09:42 PM PDT 24
Finished Jul 23 07:09:55 PM PDT 24
Peak memory 217524 kb
Host smart-2a2fe997-dd84-43b1-92ba-e153ea1ce499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109461945 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.1109461945
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.3681973450
Short name T763
Test name
Test status
Simulation time 31102730 ps
CPU time 0.88 seconds
Started Jul 23 07:09:41 PM PDT 24
Finished Jul 23 07:09:53 PM PDT 24
Peak memory 215688 kb
Host smart-641affca-fbdb-4cb7-b5f4-cce337e2cadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681973450 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.3681973450
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.822836319
Short name T719
Test name
Test status
Simulation time 45726160 ps
CPU time 0.87 seconds
Started Jul 23 07:09:40 PM PDT 24
Finished Jul 23 07:09:50 PM PDT 24
Peak memory 215728 kb
Host smart-8d800a9d-243e-4cdb-8fa7-2cd51eaa1a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822836319 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.822836319
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.3744551833
Short name T72
Test name
Test status
Simulation time 911532615 ps
CPU time 5.28 seconds
Started Jul 23 07:09:46 PM PDT 24
Finished Jul 23 07:10:04 PM PDT 24
Peak memory 220580 kb
Host smart-d3d5e361-0ea2-4390-8414-671a631b5a6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744551833 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.3744551833
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.2655187644
Short name T852
Test name
Test status
Simulation time 15322107575 ps
CPU time 390.25 seconds
Started Jul 23 07:09:42 PM PDT 24
Finished Jul 23 07:16:24 PM PDT 24
Peak memory 218828 kb
Host smart-a1c9655f-988b-4cf3-bf83-ba3006dffaae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655187644 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.2655187644
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.1404129285
Short name T715
Test name
Test status
Simulation time 64342690 ps
CPU time 1.1 seconds
Started Jul 23 07:09:40 PM PDT 24
Finished Jul 23 07:09:51 PM PDT 24
Peak memory 215876 kb
Host smart-cd002dfb-07ef-4fd1-8dc5-5521d502d628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404129285 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.1404129285
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.3980548242
Short name T721
Test name
Test status
Simulation time 20389846 ps
CPU time 0.8 seconds
Started Jul 23 07:09:48 PM PDT 24
Finished Jul 23 07:10:01 PM PDT 24
Peak memory 207068 kb
Host smart-dbafec17-115b-49eb-8f24-25ebdbb0817f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980548242 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3980548242
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.1703668204
Short name T193
Test name
Test status
Simulation time 13422270 ps
CPU time 0.9 seconds
Started Jul 23 07:09:41 PM PDT 24
Finished Jul 23 07:09:51 PM PDT 24
Peak memory 216800 kb
Host smart-4d241566-c353-4bf1-9698-258f2581d560
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703668204 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.1703668204
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.1235324661
Short name T877
Test name
Test status
Simulation time 143579514 ps
CPU time 0.97 seconds
Started Jul 23 07:09:48 PM PDT 24
Finished Jul 23 07:10:01 PM PDT 24
Peak memory 218676 kb
Host smart-b141767f-b36f-47ab-bc9c-9dcf35ea6c5a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235324661 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.1235324661
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.3347363363
Short name T800
Test name
Test status
Simulation time 18604804 ps
CPU time 1.05 seconds
Started Jul 23 07:09:48 PM PDT 24
Finished Jul 23 07:10:02 PM PDT 24
Peak memory 218876 kb
Host smart-600d1641-e23d-4b15-982e-7101cd065b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347363363 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.3347363363
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.2979268886
Short name T948
Test name
Test status
Simulation time 52050862 ps
CPU time 1.52 seconds
Started Jul 23 07:09:41 PM PDT 24
Finished Jul 23 07:09:54 PM PDT 24
Peak memory 218720 kb
Host smart-43a2d03d-0874-45fe-9218-baded12c1223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979268886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2979268886
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.3045845596
Short name T51
Test name
Test status
Simulation time 47306059 ps
CPU time 0.99 seconds
Started Jul 23 07:09:41 PM PDT 24
Finished Jul 23 07:09:53 PM PDT 24
Peak memory 224176 kb
Host smart-ede6ca13-7a1b-4bce-8ce8-6662de86f0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045845596 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3045845596
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.3458314470
Short name T338
Test name
Test status
Simulation time 15727285 ps
CPU time 0.9 seconds
Started Jul 23 07:09:39 PM PDT 24
Finished Jul 23 07:09:48 PM PDT 24
Peak memory 215600 kb
Host smart-ce970c23-ee4e-4b9c-9863-a0f0b4807edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458314470 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.3458314470
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.4176170100
Short name T653
Test name
Test status
Simulation time 347880560 ps
CPU time 2.71 seconds
Started Jul 23 07:09:40 PM PDT 24
Finished Jul 23 07:09:53 PM PDT 24
Peak memory 217656 kb
Host smart-4cb594f2-cbf8-48f5-bfdc-fc746e0ee713
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176170100 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.4176170100
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.872988972
Short name T752
Test name
Test status
Simulation time 114605406064 ps
CPU time 1381.22 seconds
Started Jul 23 07:09:40 PM PDT 24
Finished Jul 23 07:32:51 PM PDT 24
Peak memory 222476 kb
Host smart-b3bbe901-eeac-4f36-855a-a52a6ee99cd0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872988972 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.872988972
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.3376041939
Short name T875
Test name
Test status
Simulation time 29336211 ps
CPU time 1.25 seconds
Started Jul 23 07:09:49 PM PDT 24
Finished Jul 23 07:10:02 PM PDT 24
Peak memory 218916 kb
Host smart-f7c7a4db-5255-4697-b289-45f94b7e349c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376041939 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3376041939
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.4209830012
Short name T785
Test name
Test status
Simulation time 28653622 ps
CPU time 0.9 seconds
Started Jul 23 07:09:48 PM PDT 24
Finished Jul 23 07:10:01 PM PDT 24
Peak memory 215040 kb
Host smart-0bc12d4d-9c1b-49dd-a73c-87310a32eb12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209830012 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.4209830012
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.1610601259
Short name T332
Test name
Test status
Simulation time 42205503 ps
CPU time 1.08 seconds
Started Jul 23 07:09:46 PM PDT 24
Finished Jul 23 07:10:00 PM PDT 24
Peak memory 217352 kb
Host smart-a9cecd61-331e-483b-852f-09c436f4f3e0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610601259 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.1610601259
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.2326183912
Short name T716
Test name
Test status
Simulation time 23381041 ps
CPU time 1.05 seconds
Started Jul 23 07:09:48 PM PDT 24
Finished Jul 23 07:10:02 PM PDT 24
Peak memory 224340 kb
Host smart-8327b008-0182-41bd-837c-9ae90cc92051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326183912 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.2326183912
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.3988141081
Short name T505
Test name
Test status
Simulation time 74561143 ps
CPU time 1.43 seconds
Started Jul 23 07:09:50 PM PDT 24
Finished Jul 23 07:10:03 PM PDT 24
Peak memory 219176 kb
Host smart-152447de-1190-4922-a631-840e0b345c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988141081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.3988141081
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.542629552
Short name T95
Test name
Test status
Simulation time 35627821 ps
CPU time 0.85 seconds
Started Jul 23 07:09:50 PM PDT 24
Finished Jul 23 07:10:03 PM PDT 24
Peak memory 215980 kb
Host smart-7fa50c8f-9c04-4b71-81a3-4b7303936aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542629552 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.542629552
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.2083828261
Short name T572
Test name
Test status
Simulation time 21363058 ps
CPU time 0.86 seconds
Started Jul 23 07:09:41 PM PDT 24
Finished Jul 23 07:09:52 PM PDT 24
Peak memory 215644 kb
Host smart-8403c541-f120-44c8-9fd4-5a8420241e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083828261 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.2083828261
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.867034252
Short name T712
Test name
Test status
Simulation time 296002241 ps
CPU time 6 seconds
Started Jul 23 07:09:50 PM PDT 24
Finished Jul 23 07:10:08 PM PDT 24
Peak memory 217672 kb
Host smart-d18f59f7-5759-4ecc-a9ad-4cbeb0068cec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867034252 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.867034252
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.2418848784
Short name T231
Test name
Test status
Simulation time 43964924697 ps
CPU time 447.33 seconds
Started Jul 23 07:09:51 PM PDT 24
Finished Jul 23 07:17:30 PM PDT 24
Peak memory 217008 kb
Host smart-c655ce81-57fc-4e76-9eb4-60de6e5d52f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418848784 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.2418848784
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.1887774679
Short name T431
Test name
Test status
Simulation time 32781102 ps
CPU time 1.29 seconds
Started Jul 23 07:09:41 PM PDT 24
Finished Jul 23 07:09:54 PM PDT 24
Peak memory 215976 kb
Host smart-9ad12622-faa0-4315-9d30-efc4cd3faade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887774679 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.1887774679
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.3364467186
Short name T410
Test name
Test status
Simulation time 13530668 ps
CPU time 0.88 seconds
Started Jul 23 07:09:41 PM PDT 24
Finished Jul 23 07:09:54 PM PDT 24
Peak memory 207036 kb
Host smart-e3fd5e1d-0f0d-48f4-839e-1509d753411f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364467186 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.3364467186
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.1221385263
Short name T84
Test name
Test status
Simulation time 27968953 ps
CPU time 0.84 seconds
Started Jul 23 07:09:46 PM PDT 24
Finished Jul 23 07:09:59 PM PDT 24
Peak memory 216548 kb
Host smart-65987f03-1d8c-4638-aebf-edc36dedcf01
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221385263 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1221385263
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.4198519896
Short name T846
Test name
Test status
Simulation time 357698186 ps
CPU time 1.09 seconds
Started Jul 23 07:09:50 PM PDT 24
Finished Jul 23 07:10:03 PM PDT 24
Peak memory 217340 kb
Host smart-88bfd62c-9eb4-4050-8692-05321b0b0906
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198519896 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.4198519896
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.3294000176
Short name T713
Test name
Test status
Simulation time 29240055 ps
CPU time 1.22 seconds
Started Jul 23 07:09:43 PM PDT 24
Finished Jul 23 07:09:57 PM PDT 24
Peak memory 215800 kb
Host smart-a04c29a3-893c-483b-95ae-62d1af0a16aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294000176 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.3294000176
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.3504590031
Short name T771
Test name
Test status
Simulation time 46070064 ps
CPU time 1.52 seconds
Started Jul 23 07:09:51 PM PDT 24
Finished Jul 23 07:10:05 PM PDT 24
Peak memory 215716 kb
Host smart-4e044258-b60f-4295-965b-a6bcc95d77f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504590031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.3504590031
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.1585509488
Short name T424
Test name
Test status
Simulation time 23271691 ps
CPU time 1.16 seconds
Started Jul 23 07:09:42 PM PDT 24
Finished Jul 23 07:09:55 PM PDT 24
Peak memory 224364 kb
Host smart-dc73237a-e458-456c-96c0-f717a7a5aaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585509488 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1585509488
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.4041216487
Short name T491
Test name
Test status
Simulation time 19349064 ps
CPU time 1.05 seconds
Started Jul 23 07:09:42 PM PDT 24
Finished Jul 23 07:09:55 PM PDT 24
Peak memory 215656 kb
Host smart-2e14dda8-1042-43db-894b-55d781055c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041216487 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.4041216487
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.1971655032
Short name T239
Test name
Test status
Simulation time 1603971038 ps
CPU time 2.29 seconds
Started Jul 23 07:09:50 PM PDT 24
Finished Jul 23 07:10:04 PM PDT 24
Peak memory 215608 kb
Host smart-d55fdaf6-3f28-4021-af63-5a82700773ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971655032 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1971655032
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.1154818792
Short name T793
Test name
Test status
Simulation time 48697487535 ps
CPU time 414.19 seconds
Started Jul 23 07:09:50 PM PDT 24
Finished Jul 23 07:16:56 PM PDT 24
Peak memory 224072 kb
Host smart-3602573f-f42c-4969-b0dc-8e37dbe18229
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154818792 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.1154818792
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.3884670855
Short name T453
Test name
Test status
Simulation time 119764748 ps
CPU time 1.27 seconds
Started Jul 23 07:09:48 PM PDT 24
Finished Jul 23 07:10:02 PM PDT 24
Peak memory 216076 kb
Host smart-883e4c93-9024-4286-99b7-c9bbba4333bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884670855 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.3884670855
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.2690343264
Short name T777
Test name
Test status
Simulation time 86648893 ps
CPU time 0.83 seconds
Started Jul 23 07:09:48 PM PDT 24
Finished Jul 23 07:10:01 PM PDT 24
Peak memory 206824 kb
Host smart-6d510515-e6fe-4a26-8bc8-f8b6ab0d90bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690343264 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.2690343264
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.3020120585
Short name T218
Test name
Test status
Simulation time 107545911 ps
CPU time 0.88 seconds
Started Jul 23 07:09:50 PM PDT 24
Finished Jul 23 07:10:02 PM PDT 24
Peak memory 216720 kb
Host smart-3cb30df6-335f-4eee-a769-0cb0fe81b437
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020120585 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.3020120585
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.462379829
Short name T268
Test name
Test status
Simulation time 41330351 ps
CPU time 0.95 seconds
Started Jul 23 07:09:43 PM PDT 24
Finished Jul 23 07:09:56 PM PDT 24
Peak memory 218768 kb
Host smart-d19ceb59-3ccd-4804-a4e2-7a9f02616721
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462379829 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_di
sable_auto_req_mode.462379829
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.421115927
Short name T633
Test name
Test status
Simulation time 45131628 ps
CPU time 0.83 seconds
Started Jul 23 07:09:42 PM PDT 24
Finished Jul 23 07:09:54 PM PDT 24
Peak memory 218496 kb
Host smart-646f1924-5261-4352-b4d3-598c7e1de10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421115927 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.421115927
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.2116815174
Short name T755
Test name
Test status
Simulation time 79357035 ps
CPU time 1.13 seconds
Started Jul 23 07:09:42 PM PDT 24
Finished Jul 23 07:09:55 PM PDT 24
Peak memory 217512 kb
Host smart-ed945461-2f5d-4ef5-878e-20563a969685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116815174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.2116815174
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.1659817136
Short name T685
Test name
Test status
Simulation time 26224364 ps
CPU time 1.05 seconds
Started Jul 23 07:09:50 PM PDT 24
Finished Jul 23 07:10:03 PM PDT 24
Peak memory 224316 kb
Host smart-e336c604-7922-4346-abac-60c19fbfe439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659817136 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.1659817136
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.175220430
Short name T941
Test name
Test status
Simulation time 17550981 ps
CPU time 0.95 seconds
Started Jul 23 07:09:50 PM PDT 24
Finished Jul 23 07:10:02 PM PDT 24
Peak memory 215584 kb
Host smart-5ed0985c-340f-4f0e-a6c6-4ba4af8ee8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175220430 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.175220430
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.3260576200
Short name T343
Test name
Test status
Simulation time 73453367 ps
CPU time 1.98 seconds
Started Jul 23 07:09:44 PM PDT 24
Finished Jul 23 07:09:59 PM PDT 24
Peak memory 215512 kb
Host smart-4953ed4a-b812-4a19-89f6-b5544a41a9b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260576200 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.3260576200
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1887459035
Short name T308
Test name
Test status
Simulation time 73442877154 ps
CPU time 1607.37 seconds
Started Jul 23 07:09:51 PM PDT 24
Finished Jul 23 07:36:51 PM PDT 24
Peak memory 222940 kb
Host smart-a14c9f28-0007-4798-bfe2-26df71c6c181
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887459035 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1887459035
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert_test.4269830281
Short name T766
Test name
Test status
Simulation time 15992333 ps
CPU time 0.93 seconds
Started Jul 23 07:09:44 PM PDT 24
Finished Jul 23 07:09:58 PM PDT 24
Peak memory 207020 kb
Host smart-fcdee5f7-c5e9-4c63-89c5-a165d7787e98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269830281 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.4269830281
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.2506261671
Short name T458
Test name
Test status
Simulation time 43351180 ps
CPU time 1.01 seconds
Started Jul 23 07:09:50 PM PDT 24
Finished Jul 23 07:10:03 PM PDT 24
Peak memory 217156 kb
Host smart-87b55cc3-9202-4bd6-bda2-e6b30a38d0fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506261671 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.2506261671
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.2520137091
Short name T737
Test name
Test status
Simulation time 20259192 ps
CPU time 1.05 seconds
Started Jul 23 07:09:43 PM PDT 24
Finished Jul 23 07:09:57 PM PDT 24
Peak memory 215884 kb
Host smart-7e0bee43-6ff8-4c2a-a31c-fd4efe943355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520137091 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.2520137091
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.1077931359
Short name T508
Test name
Test status
Simulation time 143387749 ps
CPU time 1.13 seconds
Started Jul 23 07:09:52 PM PDT 24
Finished Jul 23 07:10:04 PM PDT 24
Peak memory 219068 kb
Host smart-d15d6892-cfbd-48a6-88e9-9eccda1ace57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077931359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1077931359
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.153035089
Short name T582
Test name
Test status
Simulation time 35868691 ps
CPU time 1.04 seconds
Started Jul 23 07:09:46 PM PDT 24
Finished Jul 23 07:09:59 PM PDT 24
Peak memory 224388 kb
Host smart-89341bf6-cdf4-433b-bcec-789e0b22dcb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153035089 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.153035089
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.297150952
Short name T904
Test name
Test status
Simulation time 153284764 ps
CPU time 0.92 seconds
Started Jul 23 07:09:48 PM PDT 24
Finished Jul 23 07:10:01 PM PDT 24
Peak memory 215404 kb
Host smart-466dc100-fa04-40f2-9547-1e37a708f8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297150952 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.297150952
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.2695322983
Short name T404
Test name
Test status
Simulation time 359112852 ps
CPU time 3.84 seconds
Started Jul 23 07:09:49 PM PDT 24
Finished Jul 23 07:10:05 PM PDT 24
Peak memory 215608 kb
Host smart-102d1a8c-a510-4371-bb10-2c421a4b7765
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695322983 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.2695322983
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.1981265809
Short name T978
Test name
Test status
Simulation time 13306020636 ps
CPU time 329.75 seconds
Started Jul 23 07:09:50 PM PDT 24
Finished Jul 23 07:15:31 PM PDT 24
Peak memory 224032 kb
Host smart-cbc002e3-57c4-4605-b21b-0f1c478a1efc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981265809 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.1981265809
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.2508689775
Short name T905
Test name
Test status
Simulation time 30162142 ps
CPU time 1.24 seconds
Started Jul 23 07:09:45 PM PDT 24
Finished Jul 23 07:09:59 PM PDT 24
Peak memory 220996 kb
Host smart-faf519a6-5619-4f66-8d28-386e625ff8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508689775 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.2508689775
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.3508834936
Short name T822
Test name
Test status
Simulation time 122396359 ps
CPU time 0.88 seconds
Started Jul 23 07:09:52 PM PDT 24
Finished Jul 23 07:10:04 PM PDT 24
Peak memory 215224 kb
Host smart-5aadd95d-fad3-4c32-911e-07105351bee6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508834936 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.3508834936
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.2804620556
Short name T165
Test name
Test status
Simulation time 39748322 ps
CPU time 0.84 seconds
Started Jul 23 07:09:51 PM PDT 24
Finished Jul 23 07:10:04 PM PDT 24
Peak memory 216600 kb
Host smart-a86e1d8d-e43d-4a53-ac7c-2c35f1dcd1ad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804620556 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.2804620556
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.2040456999
Short name T156
Test name
Test status
Simulation time 76265009 ps
CPU time 1.06 seconds
Started Jul 23 07:09:44 PM PDT 24
Finished Jul 23 07:09:58 PM PDT 24
Peak memory 217244 kb
Host smart-12ab673f-b2af-40b8-a4bb-d4731605a85b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040456999 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.2040456999
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.4180933664
Short name T575
Test name
Test status
Simulation time 19979587 ps
CPU time 0.96 seconds
Started Jul 23 07:09:51 PM PDT 24
Finished Jul 23 07:10:04 PM PDT 24
Peak memory 219128 kb
Host smart-3fd8f259-ffb4-4536-af41-cd96f44b2b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180933664 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.4180933664
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.1208708238
Short name T489
Test name
Test status
Simulation time 8762035721 ps
CPU time 119.09 seconds
Started Jul 23 07:09:49 PM PDT 24
Finished Jul 23 07:12:00 PM PDT 24
Peak memory 217816 kb
Host smart-219c3fcd-d9a1-43ed-83e2-f521ec3796c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208708238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1208708238
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.1053756791
Short name T925
Test name
Test status
Simulation time 19994559 ps
CPU time 1.07 seconds
Started Jul 23 07:09:46 PM PDT 24
Finished Jul 23 07:10:00 PM PDT 24
Peak memory 216140 kb
Host smart-aa7972b2-6d3f-451d-b200-b45e7026c3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053756791 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.1053756791
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.4030712517
Short name T722
Test name
Test status
Simulation time 51157426 ps
CPU time 0.93 seconds
Started Jul 23 07:09:49 PM PDT 24
Finished Jul 23 07:10:01 PM PDT 24
Peak memory 215656 kb
Host smart-8acd4277-406d-439c-89fa-77b57ff60fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030712517 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.4030712517
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.1069328262
Short name T461
Test name
Test status
Simulation time 215723424 ps
CPU time 4.36 seconds
Started Jul 23 07:09:51 PM PDT 24
Finished Jul 23 07:10:07 PM PDT 24
Peak memory 217592 kb
Host smart-183e421e-96ce-4ac0-89f8-3bc05474d2c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069328262 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1069328262
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.3493557241
Short name T831
Test name
Test status
Simulation time 43054734309 ps
CPU time 260.24 seconds
Started Jul 23 07:09:49 PM PDT 24
Finished Jul 23 07:14:21 PM PDT 24
Peak memory 218708 kb
Host smart-a8b11a02-1b65-480c-80e5-d8407346dba0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493557241 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.3493557241
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.4017436156
Short name T423
Test name
Test status
Simulation time 89532225 ps
CPU time 1.18 seconds
Started Jul 23 07:09:57 PM PDT 24
Finished Jul 23 07:10:10 PM PDT 24
Peak memory 219124 kb
Host smart-79943f03-5d32-42ab-b04e-2037717ccff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017436156 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.4017436156
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.1817016360
Short name T879
Test name
Test status
Simulation time 60357053 ps
CPU time 0.96 seconds
Started Jul 23 07:09:54 PM PDT 24
Finished Jul 23 07:10:06 PM PDT 24
Peak memory 215512 kb
Host smart-5b9a1085-78fa-4405-b7d4-d8c4a6a5264c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817016360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.1817016360
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.4269347000
Short name T980
Test name
Test status
Simulation time 14780552 ps
CPU time 0.94 seconds
Started Jul 23 07:09:55 PM PDT 24
Finished Jul 23 07:10:07 PM PDT 24
Peak memory 216908 kb
Host smart-976ccffc-24a4-4600-8b46-913020cdc6e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269347000 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.4269347000
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.3543495086
Short name T522
Test name
Test status
Simulation time 125037237 ps
CPU time 1.02 seconds
Started Jul 23 07:09:55 PM PDT 24
Finished Jul 23 07:10:07 PM PDT 24
Peak memory 217132 kb
Host smart-f9727d5f-e7e7-44ef-831f-f514b0bc2eac
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543495086 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.3543495086
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.123175203
Short name T740
Test name
Test status
Simulation time 86877297 ps
CPU time 1.23 seconds
Started Jul 23 07:09:58 PM PDT 24
Finished Jul 23 07:10:10 PM PDT 24
Peak memory 226020 kb
Host smart-4a72b571-cadc-4d1c-81c7-6dc33dc84d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123175203 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.123175203
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.2429057031
Short name T339
Test name
Test status
Simulation time 71253745 ps
CPU time 1.56 seconds
Started Jul 23 07:09:51 PM PDT 24
Finished Jul 23 07:10:04 PM PDT 24
Peak memory 220516 kb
Host smart-784911e6-e3c2-4038-89d6-11d69bed865f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429057031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2429057031
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.468287668
Short name T53
Test name
Test status
Simulation time 23650883 ps
CPU time 1.08 seconds
Started Jul 23 07:09:50 PM PDT 24
Finished Jul 23 07:10:03 PM PDT 24
Peak memory 224440 kb
Host smart-1aeb21ac-9b19-4d69-b25e-bb6eb5d10e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468287668 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.468287668
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.755459490
Short name T323
Test name
Test status
Simulation time 19717577 ps
CPU time 0.98 seconds
Started Jul 23 07:09:45 PM PDT 24
Finished Jul 23 07:09:58 PM PDT 24
Peak memory 215720 kb
Host smart-553382bd-07ae-443c-bf2a-dc32bb7416d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755459490 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.755459490
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.1909433525
Short name T758
Test name
Test status
Simulation time 286442856 ps
CPU time 5.62 seconds
Started Jul 23 07:09:46 PM PDT 24
Finished Jul 23 07:10:04 PM PDT 24
Peak memory 218744 kb
Host smart-2103c524-ae5e-4e55-b97d-be897d01d1ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909433525 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.1909433525
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.3747735724
Short name T223
Test name
Test status
Simulation time 223139665438 ps
CPU time 1597.23 seconds
Started Jul 23 07:09:50 PM PDT 24
Finished Jul 23 07:36:39 PM PDT 24
Peak memory 226588 kb
Host smart-c00e8e5f-0668-434a-ac00-3d4dea22dc70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747735724 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.3747735724
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2799734747
Short name T348
Test name
Test status
Simulation time 37687567 ps
CPU time 1.1 seconds
Started Jul 23 07:09:59 PM PDT 24
Finished Jul 23 07:10:13 PM PDT 24
Peak memory 219048 kb
Host smart-8195b82c-8e0f-40a2-925f-43275bb2b2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799734747 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2799734747
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.3907645421
Short name T47
Test name
Test status
Simulation time 95897654 ps
CPU time 0.88 seconds
Started Jul 23 07:10:01 PM PDT 24
Finished Jul 23 07:10:14 PM PDT 24
Peak memory 207004 kb
Host smart-894c9234-bf82-4311-8faf-1fd731f27560
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907645421 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3907645421
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.3022954594
Short name T474
Test name
Test status
Simulation time 12471296 ps
CPU time 0.93 seconds
Started Jul 23 07:09:55 PM PDT 24
Finished Jul 23 07:10:07 PM PDT 24
Peak memory 216276 kb
Host smart-e1a7c7df-f1ab-4111-bf7e-e544106667c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022954594 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.3022954594
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.1769456713
Short name T151
Test name
Test status
Simulation time 70880249 ps
CPU time 1.18 seconds
Started Jul 23 07:10:03 PM PDT 24
Finished Jul 23 07:10:15 PM PDT 24
Peak memory 219744 kb
Host smart-de74dbfe-e499-4710-999b-f57787efa0b0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769456713 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.1769456713
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.1347143116
Short name T699
Test name
Test status
Simulation time 55781538 ps
CPU time 1.05 seconds
Started Jul 23 07:10:03 PM PDT 24
Finished Jul 23 07:10:15 PM PDT 24
Peak memory 220948 kb
Host smart-f0773f0a-b936-4c94-bc1e-618bc65f55dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347143116 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.1347143116
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.4228247102
Short name T42
Test name
Test status
Simulation time 41422673 ps
CPU time 1.83 seconds
Started Jul 23 07:09:57 PM PDT 24
Finished Jul 23 07:10:10 PM PDT 24
Peak memory 218808 kb
Host smart-b17b070c-05ad-49ce-8adc-ddab3399c5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228247102 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.4228247102
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.1802053036
Short name T893
Test name
Test status
Simulation time 27930036 ps
CPU time 1.03 seconds
Started Jul 23 07:09:58 PM PDT 24
Finished Jul 23 07:10:11 PM PDT 24
Peak memory 224340 kb
Host smart-e3060f89-901b-484a-8fbd-b52f59ac3418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802053036 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.1802053036
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.860878517
Short name T673
Test name
Test status
Simulation time 19003808 ps
CPU time 1.04 seconds
Started Jul 23 07:09:56 PM PDT 24
Finished Jul 23 07:10:08 PM PDT 24
Peak memory 215612 kb
Host smart-1d866f5d-5ef1-456e-bf4c-1a165f7245bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860878517 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.860878517
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.3028213437
Short name T837
Test name
Test status
Simulation time 301405145 ps
CPU time 5.75 seconds
Started Jul 23 07:09:55 PM PDT 24
Finished Jul 23 07:10:12 PM PDT 24
Peak memory 217492 kb
Host smart-c7fe2565-8253-47c8-bb76-0e2594c623d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028213437 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3028213437
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.2109472835
Short name T734
Test name
Test status
Simulation time 202956768938 ps
CPU time 2630.84 seconds
Started Jul 23 07:09:59 PM PDT 24
Finished Jul 23 07:54:02 PM PDT 24
Peak memory 233248 kb
Host smart-03de337b-e378-44e5-8d9d-fd360c945b8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109472835 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.2109472835
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.688065522
Short name T510
Test name
Test status
Simulation time 72902353 ps
CPU time 1 seconds
Started Jul 23 07:08:48 PM PDT 24
Finished Jul 23 07:08:52 PM PDT 24
Peak memory 218732 kb
Host smart-5ec03ea4-2f44-4c97-aa79-e23cead29c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688065522 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.688065522
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.1491853113
Short name T874
Test name
Test status
Simulation time 20541869 ps
CPU time 0.93 seconds
Started Jul 23 07:08:49 PM PDT 24
Finished Jul 23 07:08:53 PM PDT 24
Peak memory 215496 kb
Host smart-3512e4b7-fe40-4da0-9639-e30d0d3c16ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491853113 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.1491853113
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.3920341351
Short name T170
Test name
Test status
Simulation time 16590680 ps
CPU time 0.85 seconds
Started Jul 23 07:08:45 PM PDT 24
Finished Jul 23 07:08:47 PM PDT 24
Peak memory 216620 kb
Host smart-88db4f07-622a-4c8b-af1f-b1150c5bc2a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920341351 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.3920341351
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.3965459561
Short name T662
Test name
Test status
Simulation time 63770131 ps
CPU time 1.03 seconds
Started Jul 23 07:08:47 PM PDT 24
Finished Jul 23 07:08:51 PM PDT 24
Peak memory 218948 kb
Host smart-82fedd0c-fc73-437e-b92a-727b8d2a821c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965459561 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.3965459561
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.4053174820
Short name T684
Test name
Test status
Simulation time 17732934 ps
CPU time 1.04 seconds
Started Jul 23 07:08:44 PM PDT 24
Finished Jul 23 07:08:47 PM PDT 24
Peak memory 218796 kb
Host smart-61d916a5-67c3-4d26-9a88-47680b5a8631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053174820 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.4053174820
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.2955376531
Short name T632
Test name
Test status
Simulation time 81454673 ps
CPU time 1.33 seconds
Started Jul 23 07:08:49 PM PDT 24
Finished Jul 23 07:08:53 PM PDT 24
Peak memory 219008 kb
Host smart-943d5c12-4357-4099-9d4f-2321a30ee3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955376531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.2955376531
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.728442215
Short name T883
Test name
Test status
Simulation time 32436179 ps
CPU time 0.85 seconds
Started Jul 23 07:08:47 PM PDT 24
Finished Jul 23 07:08:50 PM PDT 24
Peak memory 216060 kb
Host smart-2741b4a8-5f74-4aab-b165-ead398a8a9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728442215 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.728442215
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.1527961198
Short name T824
Test name
Test status
Simulation time 15638427 ps
CPU time 0.99 seconds
Started Jul 23 07:08:48 PM PDT 24
Finished Jul 23 07:08:52 PM PDT 24
Peak memory 207436 kb
Host smart-b11af7d3-1a1a-46a6-ba63-433871deb431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527961198 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.1527961198
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.1994183322
Short name T61
Test name
Test status
Simulation time 1479247035 ps
CPU time 7.79 seconds
Started Jul 23 07:08:49 PM PDT 24
Finished Jul 23 07:08:59 PM PDT 24
Peak memory 242796 kb
Host smart-0c580628-2921-4080-a3ad-08dc45306b5b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994183322 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.1994183322
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.3685170379
Short name T564
Test name
Test status
Simulation time 15712011 ps
CPU time 0.95 seconds
Started Jul 23 07:08:48 PM PDT 24
Finished Jul 23 07:08:51 PM PDT 24
Peak memory 215636 kb
Host smart-0976e99d-80da-44d6-abb6-1db2ca484bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685170379 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3685170379
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.909872030
Short name T427
Test name
Test status
Simulation time 179912689 ps
CPU time 3.9 seconds
Started Jul 23 07:08:48 PM PDT 24
Finished Jul 23 07:08:55 PM PDT 24
Peak memory 215800 kb
Host smart-ca5a4f24-b791-400e-aa1f-8703b77880cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909872030 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.909872030
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.1480337621
Short name T531
Test name
Test status
Simulation time 255773378318 ps
CPU time 793.77 seconds
Started Jul 23 07:08:48 PM PDT 24
Finished Jul 23 07:22:04 PM PDT 24
Peak memory 221164 kb
Host smart-555379a1-6d74-4b6d-b5c9-2b027a7bc4fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480337621 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.1480337621
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.2294204745
Short name T109
Test name
Test status
Simulation time 22710910 ps
CPU time 1.15 seconds
Started Jul 23 07:09:58 PM PDT 24
Finished Jul 23 07:10:11 PM PDT 24
Peak memory 220188 kb
Host smart-861cfc35-e005-4f8e-8e85-c499ad4c6203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294204745 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.2294204745
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.4292685892
Short name T418
Test name
Test status
Simulation time 18149800 ps
CPU time 0.91 seconds
Started Jul 23 07:10:07 PM PDT 24
Finished Jul 23 07:10:18 PM PDT 24
Peak memory 206980 kb
Host smart-dfc5b3dd-9961-46a3-946c-d49e59a63f0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292685892 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.4292685892
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.2010503568
Short name T847
Test name
Test status
Simulation time 33199488 ps
CPU time 0.87 seconds
Started Jul 23 07:09:54 PM PDT 24
Finished Jul 23 07:10:06 PM PDT 24
Peak memory 215804 kb
Host smart-5df2e2df-d377-46a5-acde-1013e0865be2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010503568 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.2010503568
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.4169640605
Short name T682
Test name
Test status
Simulation time 35148230 ps
CPU time 1.2 seconds
Started Jul 23 07:09:57 PM PDT 24
Finished Jul 23 07:10:09 PM PDT 24
Peak memory 220252 kb
Host smart-0b8faca8-ccde-49db-9e82-f5f570c33d3b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169640605 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.4169640605
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.946245515
Short name T145
Test name
Test status
Simulation time 23177555 ps
CPU time 1.18 seconds
Started Jul 23 07:09:54 PM PDT 24
Finished Jul 23 07:10:06 PM PDT 24
Peak memory 218704 kb
Host smart-827d3056-07b7-4985-8192-59ab2b0caca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946245515 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.946245515
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.3856208570
Short name T856
Test name
Test status
Simulation time 79802578 ps
CPU time 1.08 seconds
Started Jul 23 07:09:54 PM PDT 24
Finished Jul 23 07:10:06 PM PDT 24
Peak memory 217464 kb
Host smart-027a8bd1-8a7d-41bf-85a4-cbcfb07b5073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856208570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.3856208570
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.3378776639
Short name T101
Test name
Test status
Simulation time 38348925 ps
CPU time 0.8 seconds
Started Jul 23 07:10:06 PM PDT 24
Finished Jul 23 07:10:18 PM PDT 24
Peak memory 215864 kb
Host smart-dbf63607-3a9d-4cdb-866c-9a98b6afe1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378776639 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.3378776639
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.2622133802
Short name T329
Test name
Test status
Simulation time 92369051 ps
CPU time 0.86 seconds
Started Jul 23 07:09:55 PM PDT 24
Finished Jul 23 07:10:07 PM PDT 24
Peak memory 215400 kb
Host smart-7c8a4029-7f45-4cd8-94b0-b80018242bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622133802 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.2622133802
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.366738004
Short name T855
Test name
Test status
Simulation time 225404957 ps
CPU time 4.59 seconds
Started Jul 23 07:10:04 PM PDT 24
Finished Jul 23 07:10:20 PM PDT 24
Peak memory 218780 kb
Host smart-b3c3a34b-7d03-4c4c-a414-dcf68779d4bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366738004 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.366738004
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.48964460
Short name T233
Test name
Test status
Simulation time 23464366474 ps
CPU time 513.01 seconds
Started Jul 23 07:09:54 PM PDT 24
Finished Jul 23 07:18:38 PM PDT 24
Peak memory 224028 kb
Host smart-919a094f-d55d-4f35-be39-409cffac5569
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48964460 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.48964460
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.2057791823
Short name T705
Test name
Test status
Simulation time 27899322 ps
CPU time 1.21 seconds
Started Jul 23 07:09:54 PM PDT 24
Finished Jul 23 07:10:06 PM PDT 24
Peak memory 219084 kb
Host smart-7572c521-0e29-4bef-8917-76bb7813a904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057791823 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.2057791823
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.939439198
Short name T357
Test name
Test status
Simulation time 19627026 ps
CPU time 0.83 seconds
Started Jul 23 07:09:55 PM PDT 24
Finished Jul 23 07:10:07 PM PDT 24
Peak memory 206820 kb
Host smart-0d20ea66-3b7f-44f2-afbc-e52d0ae7f1e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939439198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.939439198
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.2907509002
Short name T979
Test name
Test status
Simulation time 10903959 ps
CPU time 0.86 seconds
Started Jul 23 07:09:54 PM PDT 24
Finished Jul 23 07:10:06 PM PDT 24
Peak memory 215744 kb
Host smart-f7674e3c-28b8-44fb-9fca-f5641fce4330
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907509002 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2907509002
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.3612428037
Short name T204
Test name
Test status
Simulation time 99316578 ps
CPU time 1.12 seconds
Started Jul 23 07:09:55 PM PDT 24
Finished Jul 23 07:10:07 PM PDT 24
Peak memory 217260 kb
Host smart-81b661ee-4427-4d55-bb12-0a1af8dcb531
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612428037 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.3612428037
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.2188278879
Short name T144
Test name
Test status
Simulation time 48805706 ps
CPU time 1.27 seconds
Started Jul 23 07:09:58 PM PDT 24
Finished Jul 23 07:10:11 PM PDT 24
Peak memory 224276 kb
Host smart-d456b05c-9c44-40e5-bb41-dfee1af199ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188278879 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2188278879
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.4094610540
Short name T741
Test name
Test status
Simulation time 265704119 ps
CPU time 4.13 seconds
Started Jul 23 07:09:58 PM PDT 24
Finished Jul 23 07:10:15 PM PDT 24
Peak memory 220640 kb
Host smart-c074f077-85d9-461e-ac17-4d3485c085e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094610540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.4094610540
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.2233851106
Short name T341
Test name
Test status
Simulation time 23863144 ps
CPU time 1.11 seconds
Started Jul 23 07:09:55 PM PDT 24
Finished Jul 23 07:10:07 PM PDT 24
Peak memory 215704 kb
Host smart-e0802a3d-e0bf-4ac8-b60b-d4792718ce17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233851106 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2233851106
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.1427203549
Short name T373
Test name
Test status
Simulation time 35130720 ps
CPU time 0.93 seconds
Started Jul 23 07:09:55 PM PDT 24
Finished Jul 23 07:10:07 PM PDT 24
Peak memory 215552 kb
Host smart-a9655e20-a46f-4fff-8c59-f1e05bfaf402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427203549 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.1427203549
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.3709103456
Short name T958
Test name
Test status
Simulation time 351426806 ps
CPU time 3.91 seconds
Started Jul 23 07:10:00 PM PDT 24
Finished Jul 23 07:10:16 PM PDT 24
Peak memory 215636 kb
Host smart-4b0032f0-3735-42fb-8ced-9cde09372619
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709103456 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3709103456
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1189087830
Short name T501
Test name
Test status
Simulation time 522765186077 ps
CPU time 1425.14 seconds
Started Jul 23 07:10:02 PM PDT 24
Finished Jul 23 07:33:59 PM PDT 24
Peak memory 223520 kb
Host smart-3bc584dc-bea2-4ef6-9c2a-1f6c2dede4ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189087830 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.1189087830
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.1976834597
Short name T900
Test name
Test status
Simulation time 70534346 ps
CPU time 1.15 seconds
Started Jul 23 07:09:57 PM PDT 24
Finished Jul 23 07:10:10 PM PDT 24
Peak memory 220204 kb
Host smart-4a10aaa4-9fe6-44b6-b97c-2893f0fbccf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976834597 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1976834597
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.2839213837
Short name T689
Test name
Test status
Simulation time 25576998 ps
CPU time 0.99 seconds
Started Jul 23 07:09:54 PM PDT 24
Finished Jul 23 07:10:06 PM PDT 24
Peak memory 215132 kb
Host smart-8d6867a5-c38a-43c4-bd00-a291ecfe50b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839213837 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2839213837
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.4142862851
Short name T986
Test name
Test status
Simulation time 40256595 ps
CPU time 0.89 seconds
Started Jul 23 07:10:00 PM PDT 24
Finished Jul 23 07:10:13 PM PDT 24
Peak memory 216640 kb
Host smart-9aabff2f-e442-42a6-a5fd-5f616ee845b0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142862851 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.4142862851
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.3032982772
Short name T130
Test name
Test status
Simulation time 154762440 ps
CPU time 1.12 seconds
Started Jul 23 07:09:59 PM PDT 24
Finished Jul 23 07:10:12 PM PDT 24
Peak memory 217308 kb
Host smart-1c461359-6ab7-43f2-8a58-528e38842d54
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032982772 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.3032982772
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.2098526896
Short name T702
Test name
Test status
Simulation time 77734556 ps
CPU time 0.82 seconds
Started Jul 23 07:10:05 PM PDT 24
Finished Jul 23 07:10:17 PM PDT 24
Peak memory 218420 kb
Host smart-03e343f8-0481-47e0-a3bb-fa363a9010f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098526896 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.2098526896
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.1990570148
Short name T330
Test name
Test status
Simulation time 46094185 ps
CPU time 1.5 seconds
Started Jul 23 07:09:58 PM PDT 24
Finished Jul 23 07:10:11 PM PDT 24
Peak memory 218816 kb
Host smart-caaf7965-6a83-4e9e-8e7f-d4a05c53e7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990570148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.1990570148
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.552228709
Short name T97
Test name
Test status
Simulation time 21399622 ps
CPU time 1.1 seconds
Started Jul 23 07:10:05 PM PDT 24
Finished Jul 23 07:10:18 PM PDT 24
Peak memory 215992 kb
Host smart-83b5e81e-839b-43ff-869e-031c67c378fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552228709 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.552228709
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.882261580
Short name T395
Test name
Test status
Simulation time 17592302 ps
CPU time 1.06 seconds
Started Jul 23 07:09:57 PM PDT 24
Finished Jul 23 07:10:09 PM PDT 24
Peak memory 215740 kb
Host smart-48fd176a-56c0-4ba9-bbdd-dfd2dffe0aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882261580 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.882261580
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.2431080713
Short name T641
Test name
Test status
Simulation time 217030002 ps
CPU time 2.66 seconds
Started Jul 23 07:09:56 PM PDT 24
Finished Jul 23 07:10:10 PM PDT 24
Peak memory 215676 kb
Host smart-c48203a3-13df-4a20-8fdd-e11e98ba2171
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431080713 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2431080713
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_alert.2887736269
Short name T672
Test name
Test status
Simulation time 157839006 ps
CPU time 1.24 seconds
Started Jul 23 07:09:54 PM PDT 24
Finished Jul 23 07:10:07 PM PDT 24
Peak memory 220804 kb
Host smart-ebc86181-dc22-41ac-8fcf-3c3db1af63f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887736269 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2887736269
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.2641323670
Short name T377
Test name
Test status
Simulation time 18033563 ps
CPU time 0.99 seconds
Started Jul 23 07:10:01 PM PDT 24
Finished Jul 23 07:10:14 PM PDT 24
Peak memory 215188 kb
Host smart-72b1f6ec-a9d4-4f06-b8ed-abbf98c4cf6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641323670 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2641323670
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.2689354910
Short name T201
Test name
Test status
Simulation time 11837662 ps
CPU time 0.91 seconds
Started Jul 23 07:09:58 PM PDT 24
Finished Jul 23 07:10:11 PM PDT 24
Peak memory 216572 kb
Host smart-af7db41a-c7e3-473d-abc6-6ad62b383c53
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689354910 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2689354910
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.11357174
Short name T652
Test name
Test status
Simulation time 193105357 ps
CPU time 1.14 seconds
Started Jul 23 07:09:58 PM PDT 24
Finished Jul 23 07:10:11 PM PDT 24
Peak memory 217444 kb
Host smart-e207477d-8f5f-4b92-8d27-da8fe7ceea2b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11357174 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_dis
able_auto_req_mode.11357174
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.1847846169
Short name T164
Test name
Test status
Simulation time 18490819 ps
CPU time 1.05 seconds
Started Jul 23 07:10:00 PM PDT 24
Finished Jul 23 07:10:14 PM PDT 24
Peak memory 218804 kb
Host smart-06839278-0380-4d19-a2bb-37f0628c8949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847846169 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.1847846169
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.761572512
Short name T23
Test name
Test status
Simulation time 58620339 ps
CPU time 1.17 seconds
Started Jul 23 07:10:01 PM PDT 24
Finished Jul 23 07:10:14 PM PDT 24
Peak memory 217600 kb
Host smart-cd48caeb-0e44-4bbb-b8d6-6f7d7807420d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761572512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.761572512
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.373632518
Short name T502
Test name
Test status
Simulation time 40232287 ps
CPU time 0.84 seconds
Started Jul 23 07:10:01 PM PDT 24
Finished Jul 23 07:10:14 PM PDT 24
Peak memory 215876 kb
Host smart-70cc8f2f-0b43-4e3b-9037-41f26a2a28c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373632518 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.373632518
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.2729508761
Short name T382
Test name
Test status
Simulation time 20046807 ps
CPU time 1.06 seconds
Started Jul 23 07:09:57 PM PDT 24
Finished Jul 23 07:10:09 PM PDT 24
Peak memory 215628 kb
Host smart-067c435a-b0b9-4eb7-996d-1ba3e4383ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729508761 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2729508761
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.3671736857
Short name T235
Test name
Test status
Simulation time 92890644 ps
CPU time 2.14 seconds
Started Jul 23 07:10:06 PM PDT 24
Finished Jul 23 07:10:19 PM PDT 24
Peak memory 207468 kb
Host smart-5b20be50-8fa4-4177-9615-9a9089362789
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671736857 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3671736857
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2547467293
Short name T227
Test name
Test status
Simulation time 38794287717 ps
CPU time 434.55 seconds
Started Jul 23 07:10:02 PM PDT 24
Finished Jul 23 07:17:28 PM PDT 24
Peak memory 218492 kb
Host smart-9b66d125-09f4-4892-9a62-aa400006b110
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547467293 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.2547467293
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.1351804762
Short name T818
Test name
Test status
Simulation time 22329502 ps
CPU time 1.09 seconds
Started Jul 23 07:10:09 PM PDT 24
Finished Jul 23 07:10:20 PM PDT 24
Peak memory 221116 kb
Host smart-a320b7ce-4176-4799-ab78-a3a0a00f5524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351804762 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.1351804762
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.903129339
Short name T907
Test name
Test status
Simulation time 28464029 ps
CPU time 1.02 seconds
Started Jul 23 07:10:06 PM PDT 24
Finished Jul 23 07:10:18 PM PDT 24
Peak memory 207132 kb
Host smart-084e05fc-a11a-43f1-a8a0-1a6a75fe6719
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903129339 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.903129339
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.2185851752
Short name T326
Test name
Test status
Simulation time 23404388 ps
CPU time 0.9 seconds
Started Jul 23 07:10:01 PM PDT 24
Finished Jul 23 07:10:14 PM PDT 24
Peak memory 216424 kb
Host smart-38efbdb1-cadb-41ed-8262-d1d8cfe97449
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185851752 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2185851752
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.456165155
Short name T71
Test name
Test status
Simulation time 47727502 ps
CPU time 1.36 seconds
Started Jul 23 07:10:04 PM PDT 24
Finished Jul 23 07:10:17 PM PDT 24
Peak memory 218824 kb
Host smart-73b2f1c9-f00a-477e-afa6-277b86b18a79
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456165155 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_di
sable_auto_req_mode.456165155
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.3988032877
Short name T188
Test name
Test status
Simulation time 24606445 ps
CPU time 1.07 seconds
Started Jul 23 07:10:02 PM PDT 24
Finished Jul 23 07:10:15 PM PDT 24
Peak memory 218784 kb
Host smart-95c1fab1-a6cb-4b2f-8c5c-7c92f63238be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988032877 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.3988032877
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.734650290
Short name T694
Test name
Test status
Simulation time 49287642 ps
CPU time 1.76 seconds
Started Jul 23 07:10:04 PM PDT 24
Finished Jul 23 07:10:18 PM PDT 24
Peak memory 218984 kb
Host smart-c37f8498-90be-40db-838c-73c4446a5145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734650290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.734650290
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.4089364548
Short name T37
Test name
Test status
Simulation time 23882398 ps
CPU time 0.89 seconds
Started Jul 23 07:10:10 PM PDT 24
Finished Jul 23 07:10:20 PM PDT 24
Peak memory 216224 kb
Host smart-ae0aa664-6b5b-4eed-b299-ef269e00be36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089364548 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.4089364548
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.651626494
Short name T936
Test name
Test status
Simulation time 15681153 ps
CPU time 1.01 seconds
Started Jul 23 07:10:05 PM PDT 24
Finished Jul 23 07:10:17 PM PDT 24
Peak memory 215632 kb
Host smart-f5c5664d-7f75-4485-a4d9-f9852fc349ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651626494 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.651626494
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.1891615792
Short name T600
Test name
Test status
Simulation time 481397444 ps
CPU time 2.69 seconds
Started Jul 23 07:10:07 PM PDT 24
Finished Jul 23 07:10:21 PM PDT 24
Peak memory 217640 kb
Host smart-90b736fd-21a0-4a00-af1e-4f4856dec67d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891615792 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1891615792
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.4187149592
Short name T226
Test name
Test status
Simulation time 99450363467 ps
CPU time 596.34 seconds
Started Jul 23 07:10:08 PM PDT 24
Finished Jul 23 07:20:15 PM PDT 24
Peak memory 224116 kb
Host smart-4b718a93-d5bc-448a-bdb1-20f45ea14f10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187149592 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.4187149592
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.681208670
Short name T610
Test name
Test status
Simulation time 68542887 ps
CPU time 1.18 seconds
Started Jul 23 07:10:02 PM PDT 24
Finished Jul 23 07:10:15 PM PDT 24
Peak memory 220756 kb
Host smart-4d5f4d67-c1f8-4d7c-b3d9-5b521d193506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681208670 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.681208670
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.1153104632
Short name T409
Test name
Test status
Simulation time 28064294 ps
CPU time 0.88 seconds
Started Jul 23 07:10:06 PM PDT 24
Finished Jul 23 07:10:18 PM PDT 24
Peak memory 215112 kb
Host smart-b9024da8-7bee-4fac-81be-ab81a211adaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153104632 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.1153104632
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.2816249283
Short name T198
Test name
Test status
Simulation time 11869854 ps
CPU time 0.92 seconds
Started Jul 23 07:10:02 PM PDT 24
Finished Jul 23 07:10:15 PM PDT 24
Peak memory 216808 kb
Host smart-efb309ba-6d91-42eb-90f0-62d670e92429
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816249283 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2816249283
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.3780408463
Short name T155
Test name
Test status
Simulation time 49111919 ps
CPU time 1.1 seconds
Started Jul 23 07:10:03 PM PDT 24
Finished Jul 23 07:10:16 PM PDT 24
Peak memory 217224 kb
Host smart-0e1b735f-e175-45ab-9c58-f66eea58464d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780408463 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.3780408463
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.3544232985
Short name T154
Test name
Test status
Simulation time 44914536 ps
CPU time 1.19 seconds
Started Jul 23 07:10:06 PM PDT 24
Finished Jul 23 07:10:18 PM PDT 24
Peak memory 230000 kb
Host smart-5dbcae6a-31f1-45b6-b3fa-cc1a480976ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544232985 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.3544232985
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.4235549221
Short name T509
Test name
Test status
Simulation time 89162613 ps
CPU time 1.19 seconds
Started Jul 23 07:10:02 PM PDT 24
Finished Jul 23 07:10:15 PM PDT 24
Peak memory 217816 kb
Host smart-aa797ddb-6d26-4063-b0dd-8b2acd1a58e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235549221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.4235549221
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.1392682753
Short name T433
Test name
Test status
Simulation time 23554439 ps
CPU time 0.95 seconds
Started Jul 23 07:10:02 PM PDT 24
Finished Jul 23 07:10:14 PM PDT 24
Peak memory 215816 kb
Host smart-6a78e277-f64f-436f-ae65-64d23b095b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392682753 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.1392682753
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.2754129388
Short name T573
Test name
Test status
Simulation time 29740603 ps
CPU time 0.92 seconds
Started Jul 23 07:10:06 PM PDT 24
Finished Jul 23 07:10:18 PM PDT 24
Peak memory 215624 kb
Host smart-803a752d-2f0e-4b11-8697-84f90b58acd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754129388 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.2754129388
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1649112066
Short name T988
Test name
Test status
Simulation time 424060598 ps
CPU time 3.35 seconds
Started Jul 23 07:10:02 PM PDT 24
Finished Jul 23 07:10:17 PM PDT 24
Peak memory 217636 kb
Host smart-892bb1e6-a096-4f57-aa20-5a59fdf6dfdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649112066 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1649112066
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.1948564337
Short name T549
Test name
Test status
Simulation time 115058138153 ps
CPU time 1315.33 seconds
Started Jul 23 07:10:03 PM PDT 24
Finished Jul 23 07:32:11 PM PDT 24
Peak memory 226352 kb
Host smart-c78c30bb-6935-41c0-9d5e-c0d9783e1179
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948564337 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.1948564337
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.3764671962
Short name T683
Test name
Test status
Simulation time 23220458 ps
CPU time 1.21 seconds
Started Jul 23 07:10:05 PM PDT 24
Finished Jul 23 07:10:18 PM PDT 24
Peak memory 219932 kb
Host smart-0964d660-aad1-4398-a81a-35f88c21f740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764671962 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.3764671962
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.1954292660
Short name T892
Test name
Test status
Simulation time 24958313 ps
CPU time 0.91 seconds
Started Jul 23 07:10:04 PM PDT 24
Finished Jul 23 07:10:16 PM PDT 24
Peak memory 215164 kb
Host smart-a5398996-87d4-4bbd-ba29-21ad269d08ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954292660 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.1954292660
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.816544596
Short name T57
Test name
Test status
Simulation time 13038809 ps
CPU time 0.93 seconds
Started Jul 23 07:10:05 PM PDT 24
Finished Jul 23 07:10:17 PM PDT 24
Peak memory 216764 kb
Host smart-b752204d-3287-4706-9bc2-73b44c12cf10
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816544596 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.816544596
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.884203852
Short name T881
Test name
Test status
Simulation time 305576401 ps
CPU time 1.1 seconds
Started Jul 23 07:10:06 PM PDT 24
Finished Jul 23 07:10:18 PM PDT 24
Peak memory 219952 kb
Host smart-5de4712b-748b-4ca1-892d-58d991c3f3dd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884203852 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_di
sable_auto_req_mode.884203852
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.1176178214
Short name T569
Test name
Test status
Simulation time 21736785 ps
CPU time 1.04 seconds
Started Jul 23 07:10:03 PM PDT 24
Finished Jul 23 07:10:16 PM PDT 24
Peak memory 229864 kb
Host smart-47dc6a8a-791e-4f67-8e25-a64ff62bb8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176178214 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1176178214
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.2262621274
Short name T526
Test name
Test status
Simulation time 32127467 ps
CPU time 1.3 seconds
Started Jul 23 07:10:03 PM PDT 24
Finished Jul 23 07:10:17 PM PDT 24
Peak memory 220100 kb
Host smart-60532a19-d86a-4037-8460-cc387a015842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262621274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.2262621274
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.2752005325
Short name T541
Test name
Test status
Simulation time 33261393 ps
CPU time 0.86 seconds
Started Jul 23 07:10:04 PM PDT 24
Finished Jul 23 07:10:16 PM PDT 24
Peak memory 215712 kb
Host smart-e868282e-8bd2-466c-9e92-bf08b06c2551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752005325 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.2752005325
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.71480716
Short name T973
Test name
Test status
Simulation time 24127761 ps
CPU time 0.9 seconds
Started Jul 23 07:10:06 PM PDT 24
Finished Jul 23 07:10:18 PM PDT 24
Peak memory 215648 kb
Host smart-1a384238-a183-43ec-b54c-8f479ea1c33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71480716 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.71480716
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.3976602336
Short name T760
Test name
Test status
Simulation time 361468309 ps
CPU time 5.74 seconds
Started Jul 23 07:10:05 PM PDT 24
Finished Jul 23 07:10:22 PM PDT 24
Peak memory 220476 kb
Host smart-f1dd3f01-2acf-4eb7-8a20-813e22f7aafd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976602336 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.3976602336
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.2289579219
Short name T222
Test name
Test status
Simulation time 69052328234 ps
CPU time 1605.81 seconds
Started Jul 23 07:10:02 PM PDT 24
Finished Jul 23 07:37:00 PM PDT 24
Peak memory 224024 kb
Host smart-96e9e111-1dec-4097-9dc1-f5e7677613b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289579219 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.2289579219
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.633014354
Short name T895
Test name
Test status
Simulation time 200142627 ps
CPU time 1.2 seconds
Started Jul 23 07:10:16 PM PDT 24
Finished Jul 23 07:10:23 PM PDT 24
Peak memory 215992 kb
Host smart-fa03bdf2-1d8d-4701-81c9-1129caab82ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633014354 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.633014354
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.1792909278
Short name T850
Test name
Test status
Simulation time 15159928 ps
CPU time 0.99 seconds
Started Jul 23 07:10:15 PM PDT 24
Finished Jul 23 07:10:23 PM PDT 24
Peak memory 207016 kb
Host smart-6d68d54f-2d90-4d6f-86d4-7490c43114d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792909278 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1792909278
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.2848306498
Short name T200
Test name
Test status
Simulation time 11168349 ps
CPU time 0.88 seconds
Started Jul 23 07:10:19 PM PDT 24
Finished Jul 23 07:10:26 PM PDT 24
Peak memory 216700 kb
Host smart-170d5e69-e2fa-4ee3-9698-ef8726b58930
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848306498 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.2848306498
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1079456198
Short name T542
Test name
Test status
Simulation time 42484711 ps
CPU time 1.31 seconds
Started Jul 23 07:10:13 PM PDT 24
Finished Jul 23 07:10:22 PM PDT 24
Peak memory 218948 kb
Host smart-5eb591e2-70d9-4ee0-b34b-6273058e0ee1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079456198 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1079456198
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.2484597678
Short name T810
Test name
Test status
Simulation time 25419777 ps
CPU time 1.18 seconds
Started Jul 23 07:10:16 PM PDT 24
Finished Jul 23 07:10:24 PM PDT 24
Peak memory 221048 kb
Host smart-55d8fcd8-8d6d-4070-acd5-16e0aad17781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484597678 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.2484597678
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.1815835307
Short name T360
Test name
Test status
Simulation time 37483264 ps
CPU time 1.36 seconds
Started Jul 23 07:10:16 PM PDT 24
Finished Jul 23 07:10:24 PM PDT 24
Peak memory 217552 kb
Host smart-13f8baec-0526-4dd1-bc42-7ee8684116ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815835307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1815835307
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.3187439716
Short name T425
Test name
Test status
Simulation time 23774755 ps
CPU time 1.1 seconds
Started Jul 23 07:10:24 PM PDT 24
Finished Jul 23 07:10:33 PM PDT 24
Peak memory 215904 kb
Host smart-fb735b57-334c-4588-a11e-a4e5852e59f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187439716 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.3187439716
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.4204058804
Short name T328
Test name
Test status
Simulation time 16510551 ps
CPU time 1.01 seconds
Started Jul 23 07:10:14 PM PDT 24
Finished Jul 23 07:10:22 PM PDT 24
Peak memory 215696 kb
Host smart-fe43c308-ad46-4eb7-8283-3169d234041b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204058804 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.4204058804
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.422789790
Short name T599
Test name
Test status
Simulation time 179004827 ps
CPU time 2.37 seconds
Started Jul 23 07:10:20 PM PDT 24
Finished Jul 23 07:10:28 PM PDT 24
Peak memory 219864 kb
Host smart-5b5385c5-a3b4-47ce-b8f0-5db5e996478b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422789790 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.422789790
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.276479724
Short name T967
Test name
Test status
Simulation time 36699557318 ps
CPU time 488.96 seconds
Started Jul 23 07:10:15 PM PDT 24
Finished Jul 23 07:18:31 PM PDT 24
Peak memory 224240 kb
Host smart-ec75cd72-3f7e-4766-ae67-6222ebc6b6ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276479724 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.276479724
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.2504892701
Short name T598
Test name
Test status
Simulation time 28816199 ps
CPU time 1.24 seconds
Started Jul 23 07:10:17 PM PDT 24
Finished Jul 23 07:10:24 PM PDT 24
Peak memory 216052 kb
Host smart-5c1e3acc-e283-4264-8115-00cf1198d926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504892701 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.2504892701
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.617335998
Short name T761
Test name
Test status
Simulation time 204475106 ps
CPU time 3.56 seconds
Started Jul 23 07:10:14 PM PDT 24
Finished Jul 23 07:10:25 PM PDT 24
Peak memory 207476 kb
Host smart-f9f6b6b7-4c8a-448a-9752-911b34e36f3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617335998 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.617335998
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.1595595421
Short name T166
Test name
Test status
Simulation time 30736140 ps
CPU time 0.86 seconds
Started Jul 23 07:10:15 PM PDT 24
Finished Jul 23 07:10:23 PM PDT 24
Peak memory 216772 kb
Host smart-3d53c994-6c77-45e1-8136-db99aed46f5f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595595421 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.1595595421
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.1524022699
Short name T129
Test name
Test status
Simulation time 62934760 ps
CPU time 1.09 seconds
Started Jul 23 07:10:15 PM PDT 24
Finished Jul 23 07:10:23 PM PDT 24
Peak memory 217468 kb
Host smart-0f972526-e9d8-4a2e-b300-18c795aca023
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524022699 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.1524022699
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.4155466995
Short name T698
Test name
Test status
Simulation time 61456138 ps
CPU time 1.01 seconds
Started Jul 23 07:10:24 PM PDT 24
Finished Jul 23 07:10:33 PM PDT 24
Peak memory 220932 kb
Host smart-79e8504c-7a64-4a4e-bc68-a22688faa942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155466995 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.4155466995
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.476690056
Short name T355
Test name
Test status
Simulation time 48650719 ps
CPU time 1.13 seconds
Started Jul 23 07:10:17 PM PDT 24
Finished Jul 23 07:10:24 PM PDT 24
Peak memory 217472 kb
Host smart-38419ba2-85ca-4e0c-ab78-b2d1fb02b7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476690056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.476690056
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.2317496716
Short name T527
Test name
Test status
Simulation time 32929682 ps
CPU time 0.89 seconds
Started Jul 23 07:10:12 PM PDT 24
Finished Jul 23 07:10:21 PM PDT 24
Peak memory 215704 kb
Host smart-a9fb6fc0-1384-4f29-8267-75646644a025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317496716 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.2317496716
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.949464736
Short name T762
Test name
Test status
Simulation time 23983294 ps
CPU time 0.91 seconds
Started Jul 23 07:10:12 PM PDT 24
Finished Jul 23 07:10:21 PM PDT 24
Peak memory 215620 kb
Host smart-4c500b43-3782-477c-9e45-cdf3b4a5797d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949464736 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.949464736
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.1177864109
Short name T928
Test name
Test status
Simulation time 451725953 ps
CPU time 4.49 seconds
Started Jul 23 07:10:18 PM PDT 24
Finished Jul 23 07:10:28 PM PDT 24
Peak memory 217504 kb
Host smart-0b818457-51f6-4cc8-8471-6e41340a1cbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177864109 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1177864109
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.3710047565
Short name T476
Test name
Test status
Simulation time 176891497044 ps
CPU time 693.05 seconds
Started Jul 23 07:10:17 PM PDT 24
Finished Jul 23 07:21:56 PM PDT 24
Peak memory 221560 kb
Host smart-194d6872-db02-4c77-820a-4225ef9fe5bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710047565 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.3710047565
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.3392733857
Short name T167
Test name
Test status
Simulation time 66592659 ps
CPU time 1.1 seconds
Started Jul 23 07:10:24 PM PDT 24
Finished Jul 23 07:10:33 PM PDT 24
Peak memory 219560 kb
Host smart-b0289ae5-e4b1-4314-94db-b7458be0a939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392733857 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.3392733857
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.2039278323
Short name T571
Test name
Test status
Simulation time 19830561 ps
CPU time 1 seconds
Started Jul 23 07:10:19 PM PDT 24
Finished Jul 23 07:10:25 PM PDT 24
Peak memory 207036 kb
Host smart-b0d0cd71-942a-4631-8ed6-3962ccafb0fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039278323 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.2039278323
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.4134369063
Short name T216
Test name
Test status
Simulation time 12995721 ps
CPU time 0.85 seconds
Started Jul 23 07:10:13 PM PDT 24
Finished Jul 23 07:10:21 PM PDT 24
Peak memory 216740 kb
Host smart-074abfef-28ea-48e2-b596-f4a452a41116
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134369063 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.4134369063
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.3946391935
Short name T819
Test name
Test status
Simulation time 211501893 ps
CPU time 1.18 seconds
Started Jul 23 07:10:19 PM PDT 24
Finished Jul 23 07:10:26 PM PDT 24
Peak memory 217188 kb
Host smart-ace3e94a-a615-4654-9181-cf8889dc8077
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946391935 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.3946391935
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.1338013982
Short name T54
Test name
Test status
Simulation time 30086982 ps
CPU time 0.95 seconds
Started Jul 23 07:10:14 PM PDT 24
Finished Jul 23 07:10:22 PM PDT 24
Peak memory 224108 kb
Host smart-ef6c48db-62f3-4b83-9d31-29ad68f22602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338013982 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.1338013982
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.2773047997
Short name T359
Test name
Test status
Simulation time 39635405 ps
CPU time 1.45 seconds
Started Jul 23 07:10:17 PM PDT 24
Finished Jul 23 07:10:25 PM PDT 24
Peak memory 217544 kb
Host smart-b13fa8ec-6e46-47b8-b053-84b5c3b8a7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773047997 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2773047997
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.85628119
Short name T342
Test name
Test status
Simulation time 27249191 ps
CPU time 1.03 seconds
Started Jul 23 07:10:20 PM PDT 24
Finished Jul 23 07:10:27 PM PDT 24
Peak memory 215688 kb
Host smart-d39dd164-d334-45ca-aaf1-cd4dde4daa23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85628119 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.85628119
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.865636358
Short name T325
Test name
Test status
Simulation time 34277982 ps
CPU time 0.87 seconds
Started Jul 23 07:10:18 PM PDT 24
Finished Jul 23 07:10:25 PM PDT 24
Peak memory 215564 kb
Host smart-2a0d50ce-ffa6-416b-a555-7c45ca399a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865636358 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.865636358
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.1358313232
Short name T107
Test name
Test status
Simulation time 691430577 ps
CPU time 3.94 seconds
Started Jul 23 07:10:24 PM PDT 24
Finished Jul 23 07:10:36 PM PDT 24
Peak memory 217676 kb
Host smart-71ed2908-046a-4628-b8a5-0057e491e26c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358313232 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.1358313232
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.899919384
Short name T440
Test name
Test status
Simulation time 25755798501 ps
CPU time 424.95 seconds
Started Jul 23 07:10:13 PM PDT 24
Finished Jul 23 07:17:26 PM PDT 24
Peak memory 221956 kb
Host smart-376a416d-a75e-4eb1-8310-b55e817e17e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899919384 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.899919384
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.1949480872
Short name T602
Test name
Test status
Simulation time 25704171 ps
CPU time 1.17 seconds
Started Jul 23 07:08:49 PM PDT 24
Finished Jul 23 07:08:53 PM PDT 24
Peak memory 220912 kb
Host smart-5ffcfb53-a32e-48f4-acc6-ddec09024a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949480872 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.1949480872
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.853620305
Short name T768
Test name
Test status
Simulation time 16028992 ps
CPU time 0.91 seconds
Started Jul 23 07:08:47 PM PDT 24
Finished Jul 23 07:08:51 PM PDT 24
Peak memory 215120 kb
Host smart-f443219b-d477-4e2d-8a0a-868cd766a3a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853620305 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.853620305
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.3547883959
Short name T691
Test name
Test status
Simulation time 43507910 ps
CPU time 0.86 seconds
Started Jul 23 07:08:47 PM PDT 24
Finished Jul 23 07:08:50 PM PDT 24
Peak memory 216228 kb
Host smart-7f7f447e-d2ea-43fd-b773-9d098b5b8dcd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547883959 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.3547883959
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.67207103
Short name T548
Test name
Test status
Simulation time 89026167 ps
CPU time 0.97 seconds
Started Jul 23 07:08:47 PM PDT 24
Finished Jul 23 07:08:49 PM PDT 24
Peak memory 218792 kb
Host smart-ab18be82-5a46-4454-899e-3016b34d0213
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67207103 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disa
ble_auto_req_mode.67207103
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.4205550877
Short name T902
Test name
Test status
Simulation time 26790332 ps
CPU time 1.26 seconds
Started Jul 23 07:08:47 PM PDT 24
Finished Jul 23 07:08:51 PM PDT 24
Peak memory 224252 kb
Host smart-d532b154-7e04-4335-8128-985c1bf593f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205550877 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.4205550877
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.931001174
Short name T388
Test name
Test status
Simulation time 77855732 ps
CPU time 1.11 seconds
Started Jul 23 07:08:48 PM PDT 24
Finished Jul 23 07:08:52 PM PDT 24
Peak memory 217720 kb
Host smart-54170880-6f9b-4681-b5a4-26cecc96445e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931001174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.931001174
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.642941696
Short name T363
Test name
Test status
Simulation time 35809142 ps
CPU time 0.86 seconds
Started Jul 23 07:08:47 PM PDT 24
Finished Jul 23 07:08:49 PM PDT 24
Peak memory 215592 kb
Host smart-1078c406-719e-429d-98ec-9385071ca8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642941696 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.642941696
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.3448799315
Short name T322
Test name
Test status
Simulation time 18388216 ps
CPU time 1.02 seconds
Started Jul 23 07:08:49 PM PDT 24
Finished Jul 23 07:08:53 PM PDT 24
Peak memory 207432 kb
Host smart-73d1013a-4330-45c5-b368-04ff5e44da6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448799315 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.3448799315
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.2738416777
Short name T478
Test name
Test status
Simulation time 18548967 ps
CPU time 1.03 seconds
Started Jul 23 07:08:47 PM PDT 24
Finished Jul 23 07:08:49 PM PDT 24
Peak memory 215748 kb
Host smart-8360d6f6-6508-409d-bbd7-ebef2904fb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738416777 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.2738416777
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.2825611749
Short name T576
Test name
Test status
Simulation time 788544457 ps
CPU time 3.4 seconds
Started Jul 23 07:08:47 PM PDT 24
Finished Jul 23 07:08:53 PM PDT 24
Peak memory 217428 kb
Host smart-1f6ef622-602a-4fd7-a858-4278240b7294
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825611749 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2825611749
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1291687175
Short name T416
Test name
Test status
Simulation time 27166349311 ps
CPU time 647.26 seconds
Started Jul 23 07:08:48 PM PDT 24
Finished Jul 23 07:19:38 PM PDT 24
Peak memory 224132 kb
Host smart-bdccb18e-f854-43d8-9b1d-b572d264975a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291687175 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.1291687175
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.2833491868
Short name T919
Test name
Test status
Simulation time 38135898 ps
CPU time 1.11 seconds
Started Jul 23 07:10:14 PM PDT 24
Finished Jul 23 07:10:22 PM PDT 24
Peak memory 219164 kb
Host smart-91ec9b4f-b1a5-40bc-b2c3-28b06dd47058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833491868 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.2833491868
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_genbits.1463314346
Short name T816
Test name
Test status
Simulation time 39344675 ps
CPU time 1.38 seconds
Started Jul 23 07:10:17 PM PDT 24
Finished Jul 23 07:10:25 PM PDT 24
Peak memory 217524 kb
Host smart-c88fd1ff-0218-43a5-9988-b34f4c58fbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463314346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1463314346
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.2748365465
Short name T240
Test name
Test status
Simulation time 69418065 ps
CPU time 1.23 seconds
Started Jul 23 07:10:16 PM PDT 24
Finished Jul 23 07:10:24 PM PDT 24
Peak memory 220836 kb
Host smart-cdf8b3f9-4f83-4352-93e7-1b2f39a3e57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748365465 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.2748365465
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.727891955
Short name T119
Test name
Test status
Simulation time 50347049 ps
CPU time 1.12 seconds
Started Jul 23 07:10:13 PM PDT 24
Finished Jul 23 07:10:21 PM PDT 24
Peak memory 229916 kb
Host smart-f17efa6c-4988-4a2e-a053-de0fd3d905a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727891955 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.727891955
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.3986170063
Short name T815
Test name
Test status
Simulation time 88988169 ps
CPU time 1.1 seconds
Started Jul 23 07:10:14 PM PDT 24
Finished Jul 23 07:10:22 PM PDT 24
Peak memory 217600 kb
Host smart-f2a353d7-27ec-47e3-98bb-7cd2da8a6a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986170063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.3986170063
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.4065358933
Short name T529
Test name
Test status
Simulation time 141525646 ps
CPU time 1.13 seconds
Started Jul 23 07:10:14 PM PDT 24
Finished Jul 23 07:10:22 PM PDT 24
Peak memory 221116 kb
Host smart-30a4944a-49a4-4718-84fa-3c40bec4386c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065358933 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.4065358933
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.448694268
Short name T498
Test name
Test status
Simulation time 20052515 ps
CPU time 1.05 seconds
Started Jul 23 07:10:20 PM PDT 24
Finished Jul 23 07:10:28 PM PDT 24
Peak memory 218752 kb
Host smart-52ca889c-17df-4154-8df1-b996834574ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448694268 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.448694268
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.1005307216
Short name T448
Test name
Test status
Simulation time 31266945 ps
CPU time 1.35 seconds
Started Jul 23 07:10:20 PM PDT 24
Finished Jul 23 07:10:27 PM PDT 24
Peak memory 220436 kb
Host smart-63ca6314-8819-4ef9-aad4-b79f08666d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005307216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.1005307216
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.2497019857
Short name T701
Test name
Test status
Simulation time 24081216 ps
CPU time 1.14 seconds
Started Jul 23 07:10:13 PM PDT 24
Finished Jul 23 07:10:21 PM PDT 24
Peak memory 219160 kb
Host smart-850f1b72-66e1-4742-beca-fa28bd981921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497019857 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.2497019857
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_genbits.2854164402
Short name T583
Test name
Test status
Simulation time 57174383 ps
CPU time 2 seconds
Started Jul 23 07:10:12 PM PDT 24
Finished Jul 23 07:10:22 PM PDT 24
Peak memory 218848 kb
Host smart-22fe638d-0c78-4744-9d53-46e8e80d2756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854164402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.2854164402
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.1824713616
Short name T364
Test name
Test status
Simulation time 28000547 ps
CPU time 1.19 seconds
Started Jul 23 07:10:21 PM PDT 24
Finished Jul 23 07:10:29 PM PDT 24
Peak memory 220204 kb
Host smart-bd7cda34-9ccf-4fba-ad4b-64d5997a4646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824713616 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.1824713616
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.1077758990
Short name T121
Test name
Test status
Simulation time 41313415 ps
CPU time 1.07 seconds
Started Jul 23 07:10:20 PM PDT 24
Finished Jul 23 07:10:28 PM PDT 24
Peak memory 220796 kb
Host smart-f46ee9d3-f7ab-4416-a2c3-cafd10e8c5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077758990 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.1077758990
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.1015393255
Short name T532
Test name
Test status
Simulation time 33869351 ps
CPU time 1.26 seconds
Started Jul 23 07:10:19 PM PDT 24
Finished Jul 23 07:10:27 PM PDT 24
Peak memory 217652 kb
Host smart-c14a0d86-ff82-4bd5-97e2-9ca7d67f651d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015393255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1015393255
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.1969870100
Short name T503
Test name
Test status
Simulation time 26501307 ps
CPU time 1.21 seconds
Started Jul 23 07:10:23 PM PDT 24
Finished Jul 23 07:10:31 PM PDT 24
Peak memory 218852 kb
Host smart-b08436d5-cfe1-4240-ab58-0230f5e39de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969870100 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.1969870100
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.3816518504
Short name T829
Test name
Test status
Simulation time 25527978 ps
CPU time 1.28 seconds
Started Jul 23 07:10:23 PM PDT 24
Finished Jul 23 07:10:31 PM PDT 24
Peak memory 224308 kb
Host smart-c45e389e-9c0b-4b6b-b66e-4b245477c276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816518504 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.3816518504
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.4201738775
Short name T288
Test name
Test status
Simulation time 45141375 ps
CPU time 1.11 seconds
Started Jul 23 07:10:24 PM PDT 24
Finished Jul 23 07:10:33 PM PDT 24
Peak memory 219080 kb
Host smart-3ee5b020-2880-4c8d-a32d-b23c1731bc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201738775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.4201738775
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.2882878190
Short name T678
Test name
Test status
Simulation time 44119932 ps
CPU time 1.18 seconds
Started Jul 23 07:10:23 PM PDT 24
Finished Jul 23 07:10:32 PM PDT 24
Peak memory 221020 kb
Host smart-a6fa1ef5-9f88-4564-a4e2-710289553c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882878190 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.2882878190
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.942148051
Short name T834
Test name
Test status
Simulation time 34225489 ps
CPU time 1 seconds
Started Jul 23 07:10:20 PM PDT 24
Finished Jul 23 07:10:28 PM PDT 24
Peak memory 224096 kb
Host smart-e3e5e6c1-685b-4708-9d94-eb12a108ff4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942148051 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.942148051
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.2806966101
Short name T296
Test name
Test status
Simulation time 27194608 ps
CPU time 1.27 seconds
Started Jul 23 07:10:22 PM PDT 24
Finished Jul 23 07:10:31 PM PDT 24
Peak memory 220208 kb
Host smart-e5f6713c-8fd3-4f30-91c4-8b3865f06c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806966101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2806966101
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.1849392678
Short name T351
Test name
Test status
Simulation time 36138112 ps
CPU time 1.17 seconds
Started Jul 23 07:10:21 PM PDT 24
Finished Jul 23 07:10:29 PM PDT 24
Peak memory 220864 kb
Host smart-081a5cb8-0770-495b-abf4-62e7b4419b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849392678 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.1849392678
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_genbits.1517044375
Short name T277
Test name
Test status
Simulation time 37140516 ps
CPU time 1.08 seconds
Started Jul 23 07:10:20 PM PDT 24
Finished Jul 23 07:10:28 PM PDT 24
Peak memory 217652 kb
Host smart-9834ccba-76ad-4211-96e9-ff952892ecf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517044375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.1517044375
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.3411055897
Short name T929
Test name
Test status
Simulation time 50995798 ps
CPU time 1.24 seconds
Started Jul 23 07:10:20 PM PDT 24
Finished Jul 23 07:10:28 PM PDT 24
Peak memory 220360 kb
Host smart-687c8bea-dd9a-4a64-a299-433e06d52485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411055897 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.3411055897
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.3090933241
Short name T127
Test name
Test status
Simulation time 34983846 ps
CPU time 1.04 seconds
Started Jul 23 07:10:22 PM PDT 24
Finished Jul 23 07:10:30 PM PDT 24
Peak memory 220008 kb
Host smart-c5e220e9-dfdc-4a99-b731-fc9b8cea3152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090933241 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.3090933241
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/59.edn_alert.2419168131
Short name T479
Test name
Test status
Simulation time 77128106 ps
CPU time 1.16 seconds
Started Jul 23 07:10:20 PM PDT 24
Finished Jul 23 07:10:27 PM PDT 24
Peak memory 220844 kb
Host smart-8550200b-cdf1-4705-8a0a-e47cd027d751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419168131 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.2419168131
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.2065352025
Short name T857
Test name
Test status
Simulation time 33998550 ps
CPU time 1.44 seconds
Started Jul 23 07:10:20 PM PDT 24
Finished Jul 23 07:10:27 PM PDT 24
Peak memory 226116 kb
Host smart-aecc58e0-f42c-4db5-a939-c36315af9bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065352025 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.2065352025
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.951671158
Short name T403
Test name
Test status
Simulation time 19825115 ps
CPU time 1.09 seconds
Started Jul 23 07:10:22 PM PDT 24
Finished Jul 23 07:10:30 PM PDT 24
Peak memory 218880 kb
Host smart-961351aa-2b3d-492e-bbce-b4d7b5e47d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951671158 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.951671158
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.736568638
Short name T464
Test name
Test status
Simulation time 37423065 ps
CPU time 1.06 seconds
Started Jul 23 07:08:54 PM PDT 24
Finished Jul 23 07:08:57 PM PDT 24
Peak memory 219036 kb
Host smart-a4e8e4ee-19ac-46bf-80c5-59fa8869ed0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736568638 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.736568638
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.692459787
Short name T477
Test name
Test status
Simulation time 32098831 ps
CPU time 0.82 seconds
Started Jul 23 07:08:55 PM PDT 24
Finished Jul 23 07:08:57 PM PDT 24
Peak memory 215296 kb
Host smart-27386262-1c75-482c-828c-a1f4c0bc3387
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692459787 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.692459787
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.3882246408
Short name T197
Test name
Test status
Simulation time 21193866 ps
CPU time 0.87 seconds
Started Jul 23 07:08:53 PM PDT 24
Finished Jul 23 07:08:56 PM PDT 24
Peak memory 216600 kb
Host smart-ed4aa4c3-0905-40a0-9e4e-f37d1d900982
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882246408 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.3882246408
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.3489654700
Short name T202
Test name
Test status
Simulation time 32702456 ps
CPU time 1.18 seconds
Started Jul 23 07:08:53 PM PDT 24
Finished Jul 23 07:08:56 PM PDT 24
Peak memory 220076 kb
Host smart-919e9409-fe33-42f2-85b3-988a172fd408
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489654700 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.3489654700
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.11177664
Short name T922
Test name
Test status
Simulation time 23389066 ps
CPU time 1.16 seconds
Started Jul 23 07:08:51 PM PDT 24
Finished Jul 23 07:08:55 PM PDT 24
Peak memory 229868 kb
Host smart-b4e3a691-5e67-4adb-918b-03251659a3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11177664 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.11177664
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.4187132936
Short name T430
Test name
Test status
Simulation time 168338326 ps
CPU time 2.39 seconds
Started Jul 23 07:08:47 PM PDT 24
Finished Jul 23 07:08:52 PM PDT 24
Peak memory 220388 kb
Host smart-cb2d3c88-86ae-45dd-8d6b-8c8cd5154600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187132936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.4187132936
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.189413078
Short name T825
Test name
Test status
Simulation time 59106837 ps
CPU time 0.86 seconds
Started Jul 23 07:08:49 PM PDT 24
Finished Jul 23 07:08:53 PM PDT 24
Peak memory 215708 kb
Host smart-3d79dbbf-9042-465e-aaad-532e74405e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189413078 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.189413078
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.15900203
Short name T746
Test name
Test status
Simulation time 25901141 ps
CPU time 0.93 seconds
Started Jul 23 07:08:47 PM PDT 24
Finished Jul 23 07:08:50 PM PDT 24
Peak memory 207424 kb
Host smart-636c1170-e1d7-4563-b0f3-01547434f3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15900203 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.15900203
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.1411439843
Short name T690
Test name
Test status
Simulation time 23592103 ps
CPU time 0.92 seconds
Started Jul 23 07:08:48 PM PDT 24
Finished Jul 23 07:08:52 PM PDT 24
Peak memory 215576 kb
Host smart-078fd98d-d29c-4ca0-a83f-5fb78bd96c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411439843 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.1411439843
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.937446346
Short name T869
Test name
Test status
Simulation time 686784130 ps
CPU time 4.77 seconds
Started Jul 23 07:08:48 PM PDT 24
Finished Jul 23 07:08:55 PM PDT 24
Peak memory 215556 kb
Host smart-89757a22-be52-4995-a08a-63dcdd01539b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937446346 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.937446346
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.818275468
Short name T390
Test name
Test status
Simulation time 69787422157 ps
CPU time 924.62 seconds
Started Jul 23 07:08:49 PM PDT 24
Finished Jul 23 07:24:17 PM PDT 24
Peak memory 222676 kb
Host smart-ebdc6603-0c25-4789-b25b-da43ef93c595
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818275468 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.818275468
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.3975628647
Short name T85
Test name
Test status
Simulation time 82971556 ps
CPU time 1.25 seconds
Started Jul 23 07:10:19 PM PDT 24
Finished Jul 23 07:10:26 PM PDT 24
Peak memory 220132 kb
Host smart-3c14958c-6d41-4c3d-98de-0ff84776b19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975628647 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.3975628647
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.3982785330
Short name T199
Test name
Test status
Simulation time 27289785 ps
CPU time 1.15 seconds
Started Jul 23 07:10:19 PM PDT 24
Finished Jul 23 07:10:25 PM PDT 24
Peak memory 224304 kb
Host smart-a6a1f027-351a-4b5c-8aa3-0fcd444818a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982785330 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.3982785330
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.3165076653
Short name T434
Test name
Test status
Simulation time 88867012 ps
CPU time 1.35 seconds
Started Jul 23 07:10:24 PM PDT 24
Finished Jul 23 07:10:33 PM PDT 24
Peak memory 219096 kb
Host smart-f25fe195-8993-4bbd-8d2e-024f0843cb7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165076653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3165076653
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.17771516
Short name T55
Test name
Test status
Simulation time 34127143 ps
CPU time 1.1 seconds
Started Jul 23 07:10:21 PM PDT 24
Finished Jul 23 07:10:29 PM PDT 24
Peak memory 218872 kb
Host smart-2d3a9ee9-bf1b-467c-8d9f-c81244d142d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17771516 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.17771516
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.1882367905
Short name T735
Test name
Test status
Simulation time 42151941 ps
CPU time 1 seconds
Started Jul 23 07:10:20 PM PDT 24
Finished Jul 23 07:10:27 PM PDT 24
Peak memory 218908 kb
Host smart-6615e51f-0d1e-4bfe-952a-7bb62951f1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882367905 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1882367905
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.4020709638
Short name T872
Test name
Test status
Simulation time 73834842 ps
CPU time 1.19 seconds
Started Jul 23 07:10:21 PM PDT 24
Finished Jul 23 07:10:30 PM PDT 24
Peak memory 219252 kb
Host smart-4d3a1339-6f16-4553-992c-0df0ce424d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020709638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.4020709638
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.938907142
Short name T214
Test name
Test status
Simulation time 51144317 ps
CPU time 1.23 seconds
Started Jul 23 07:10:22 PM PDT 24
Finished Jul 23 07:10:30 PM PDT 24
Peak memory 216056 kb
Host smart-a449ff20-078f-4387-a261-f701d72c7d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938907142 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.938907142
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.3198924500
Short name T723
Test name
Test status
Simulation time 56796347 ps
CPU time 1.29 seconds
Started Jul 23 07:10:22 PM PDT 24
Finished Jul 23 07:10:30 PM PDT 24
Peak memory 220176 kb
Host smart-a4cc45e8-0909-4c91-a20c-98d96b13e36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198924500 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.3198924500
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.2012800861
Short name T656
Test name
Test status
Simulation time 56453389 ps
CPU time 2.08 seconds
Started Jul 23 07:10:22 PM PDT 24
Finished Jul 23 07:10:31 PM PDT 24
Peak memory 218896 kb
Host smart-6b086ca6-3885-4f54-983e-2d1b763dcb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012800861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.2012800861
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.1077316264
Short name T751
Test name
Test status
Simulation time 62498485 ps
CPU time 1.23 seconds
Started Jul 23 07:10:24 PM PDT 24
Finished Jul 23 07:10:34 PM PDT 24
Peak memory 216248 kb
Host smart-8b5a78f7-866f-40a5-b0ec-4039e35cba3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077316264 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.1077316264
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.463113595
Short name T365
Test name
Test status
Simulation time 20326092 ps
CPU time 1.04 seconds
Started Jul 23 07:10:22 PM PDT 24
Finished Jul 23 07:10:30 PM PDT 24
Peak memory 218764 kb
Host smart-3c170aef-4ce2-41fa-8be3-c153848a0eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463113595 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.463113595
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.2619404293
Short name T294
Test name
Test status
Simulation time 53085828 ps
CPU time 1.41 seconds
Started Jul 23 07:10:21 PM PDT 24
Finished Jul 23 07:10:30 PM PDT 24
Peak memory 219116 kb
Host smart-34de7cc8-f96d-4be1-bb20-619ea18bd14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619404293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.2619404293
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.4066607862
Short name T775
Test name
Test status
Simulation time 69484722 ps
CPU time 1.14 seconds
Started Jul 23 07:10:23 PM PDT 24
Finished Jul 23 07:10:31 PM PDT 24
Peak memory 219048 kb
Host smart-c0bb5b62-4a10-4189-88be-a56c9dae8dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066607862 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.4066607862
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.1699798482
Short name T313
Test name
Test status
Simulation time 46176698 ps
CPU time 1.13 seconds
Started Jul 23 07:10:23 PM PDT 24
Finished Jul 23 07:10:32 PM PDT 24
Peak memory 219828 kb
Host smart-c7c312a6-0a89-41d3-b68e-adce4ab36d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699798482 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.1699798482
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.1103548991
Short name T982
Test name
Test status
Simulation time 138791051 ps
CPU time 1.41 seconds
Started Jul 23 07:10:21 PM PDT 24
Finished Jul 23 07:10:29 PM PDT 24
Peak memory 218788 kb
Host smart-0d51e27f-8db4-4150-b312-04fb2c19def3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103548991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.1103548991
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.691588918
Short name T184
Test name
Test status
Simulation time 221601579 ps
CPU time 1.3 seconds
Started Jul 23 07:10:22 PM PDT 24
Finished Jul 23 07:10:30 PM PDT 24
Peak memory 219564 kb
Host smart-776f73f1-3c9c-49b2-9e90-9271876b9a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691588918 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.691588918
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.3992667058
Short name T68
Test name
Test status
Simulation time 18753083 ps
CPU time 1.06 seconds
Started Jul 23 07:10:24 PM PDT 24
Finished Jul 23 07:10:33 PM PDT 24
Peak memory 218816 kb
Host smart-4fea9721-2c17-49d4-be54-45a3b8a29848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992667058 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.3992667058
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.55605322
Short name T985
Test name
Test status
Simulation time 59418913 ps
CPU time 1.34 seconds
Started Jul 23 07:10:28 PM PDT 24
Finished Jul 23 07:10:38 PM PDT 24
Peak memory 219704 kb
Host smart-ceebe06b-0088-41d3-a67c-85fa43bf2588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55605322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.55605322
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.2019199945
Short name T435
Test name
Test status
Simulation time 24539650 ps
CPU time 1.16 seconds
Started Jul 23 07:10:22 PM PDT 24
Finished Jul 23 07:10:30 PM PDT 24
Peak memory 220904 kb
Host smart-97c3aa2c-c985-44d1-9728-1fb43e2eb4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019199945 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.2019199945
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.3035568187
Short name T175
Test name
Test status
Simulation time 19229482 ps
CPU time 1.14 seconds
Started Jul 23 07:10:22 PM PDT 24
Finished Jul 23 07:10:30 PM PDT 24
Peak memory 224280 kb
Host smart-aa31351c-a527-40f1-9621-464f042c5e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035568187 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.3035568187
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.2285647895
Short name T456
Test name
Test status
Simulation time 106771058 ps
CPU time 1 seconds
Started Jul 23 07:10:22 PM PDT 24
Finished Jul 23 07:10:30 PM PDT 24
Peak memory 217568 kb
Host smart-0aa74488-b919-4fef-8da4-b889a1e5bc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285647895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.2285647895
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.1419099133
Short name T384
Test name
Test status
Simulation time 38392002 ps
CPU time 1.2 seconds
Started Jul 23 07:10:26 PM PDT 24
Finished Jul 23 07:10:36 PM PDT 24
Peak memory 219840 kb
Host smart-1297a4ec-387f-43dd-b0d8-e36e6fc3b3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419099133 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.1419099133
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.353446250
Short name T870
Test name
Test status
Simulation time 21730019 ps
CPU time 0.87 seconds
Started Jul 23 07:10:26 PM PDT 24
Finished Jul 23 07:10:36 PM PDT 24
Peak memory 218660 kb
Host smart-982ea366-9109-4290-8c06-701d96c44b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353446250 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.353446250
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.2922392402
Short name T586
Test name
Test status
Simulation time 141167861 ps
CPU time 1.22 seconds
Started Jul 23 07:10:22 PM PDT 24
Finished Jul 23 07:10:30 PM PDT 24
Peak memory 217552 kb
Host smart-7cb15788-c33b-452e-8e23-fcb6fe7d84f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922392402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.2922392402
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.2965770887
Short name T157
Test name
Test status
Simulation time 29959485 ps
CPU time 1.37 seconds
Started Jul 23 07:10:28 PM PDT 24
Finished Jul 23 07:10:39 PM PDT 24
Peak memory 218936 kb
Host smart-6a06c76f-6df4-4938-9b92-f2cdc0525fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965770887 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.2965770887
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.238009714
Short name T52
Test name
Test status
Simulation time 23820139 ps
CPU time 1.01 seconds
Started Jul 23 07:10:29 PM PDT 24
Finished Jul 23 07:10:39 PM PDT 24
Peak memory 224252 kb
Host smart-0dc3fdbc-8479-45d9-8e05-6290ea56fa7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238009714 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.238009714
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.1648772717
Short name T956
Test name
Test status
Simulation time 70541883 ps
CPU time 1.04 seconds
Started Jul 23 07:10:28 PM PDT 24
Finished Jul 23 07:10:38 PM PDT 24
Peak memory 217704 kb
Host smart-6f7b5407-6bb8-4f6f-8147-033c9c2c79c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648772717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.1648772717
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.1877421114
Short name T840
Test name
Test status
Simulation time 54346824 ps
CPU time 1.26 seconds
Started Jul 23 07:10:29 PM PDT 24
Finished Jul 23 07:10:39 PM PDT 24
Peak memory 220524 kb
Host smart-8b710647-f216-401c-8e08-d68e2b11e0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877421114 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.1877421114
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.1828343419
Short name T396
Test name
Test status
Simulation time 25819067 ps
CPU time 0.92 seconds
Started Jul 23 07:10:32 PM PDT 24
Finished Jul 23 07:10:42 PM PDT 24
Peak memory 218868 kb
Host smart-fa37a155-3b38-45b3-b392-b506d92dd4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828343419 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.1828343419
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.4195382122
Short name T336
Test name
Test status
Simulation time 119340840 ps
CPU time 1.33 seconds
Started Jul 23 07:10:32 PM PDT 24
Finished Jul 23 07:10:42 PM PDT 24
Peak memory 218924 kb
Host smart-c49d97e5-6a2e-4768-b301-cdbfca831a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195382122 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.4195382122
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.2491605265
Short name T750
Test name
Test status
Simulation time 74740297 ps
CPU time 1.13 seconds
Started Jul 23 07:08:51 PM PDT 24
Finished Jul 23 07:08:55 PM PDT 24
Peak memory 218940 kb
Host smart-872fcdc5-fcf6-4382-9e4b-72f46e1b9085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491605265 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.2491605265
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.3343961469
Short name T911
Test name
Test status
Simulation time 227030157 ps
CPU time 0.96 seconds
Started Jul 23 07:08:54 PM PDT 24
Finished Jul 23 07:08:57 PM PDT 24
Peak memory 215392 kb
Host smart-934e5e93-7a25-411a-8448-054eaa9aaea1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343961469 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.3343961469
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.119682258
Short name T161
Test name
Test status
Simulation time 86073215 ps
CPU time 0.85 seconds
Started Jul 23 07:08:52 PM PDT 24
Finished Jul 23 07:08:55 PM PDT 24
Peak memory 215736 kb
Host smart-e45fa2da-9601-4481-9c26-4fb72a13c0d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119682258 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.119682258
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.330502895
Short name T774
Test name
Test status
Simulation time 107660490 ps
CPU time 1 seconds
Started Jul 23 07:08:51 PM PDT 24
Finished Jul 23 07:08:54 PM PDT 24
Peak memory 218980 kb
Host smart-a0fb1a82-ff1d-467f-8df9-9519acd36b83
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330502895 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_dis
able_auto_req_mode.330502895
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.3804250606
Short name T191
Test name
Test status
Simulation time 39242810 ps
CPU time 0.97 seconds
Started Jul 23 07:08:51 PM PDT 24
Finished Jul 23 07:08:54 PM PDT 24
Peak memory 229596 kb
Host smart-095f1c43-d334-48ce-a46b-35bb10786988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804250606 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3804250606
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.1884285046
Short name T853
Test name
Test status
Simulation time 50384407 ps
CPU time 1.38 seconds
Started Jul 23 07:08:51 PM PDT 24
Finished Jul 23 07:08:55 PM PDT 24
Peak memory 219048 kb
Host smart-0aa6bae9-f6f3-4a9f-b397-e5c28cdd55ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884285046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1884285046
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.3949617974
Short name T394
Test name
Test status
Simulation time 48461766 ps
CPU time 0.82 seconds
Started Jul 23 07:08:52 PM PDT 24
Finished Jul 23 07:08:55 PM PDT 24
Peak memory 215712 kb
Host smart-e08b5ddc-a1ce-42ac-9bba-be3908326c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949617974 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.3949617974
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.2816811050
Short name T27
Test name
Test status
Simulation time 17589970 ps
CPU time 0.99 seconds
Started Jul 23 07:08:53 PM PDT 24
Finished Jul 23 07:08:56 PM PDT 24
Peak memory 207412 kb
Host smart-ae46484f-0a8f-488a-9b23-28667d4c79c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816811050 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.2816811050
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.2757204573
Short name T784
Test name
Test status
Simulation time 17893640 ps
CPU time 0.98 seconds
Started Jul 23 07:08:51 PM PDT 24
Finished Jul 23 07:08:55 PM PDT 24
Peak memory 215628 kb
Host smart-ba16bdd9-df32-4d5f-bf0c-55d1b4653b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757204573 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.2757204573
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.1493175342
Short name T298
Test name
Test status
Simulation time 550298519 ps
CPU time 2.16 seconds
Started Jul 23 07:08:50 PM PDT 24
Finished Jul 23 07:08:55 PM PDT 24
Peak memory 217740 kb
Host smart-9f014838-effe-49e4-b009-f1d78cdf5a0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493175342 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1493175342
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2217808328
Short name T482
Test name
Test status
Simulation time 64603760491 ps
CPU time 523.2 seconds
Started Jul 23 07:08:53 PM PDT 24
Finished Jul 23 07:17:38 PM PDT 24
Peak memory 224036 kb
Host smart-363f1180-1f2a-4eb0-a565-6dc3d4fb67ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217808328 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.2217808328
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.255706333
Short name T126
Test name
Test status
Simulation time 34567220 ps
CPU time 1.34 seconds
Started Jul 23 07:10:25 PM PDT 24
Finished Jul 23 07:10:35 PM PDT 24
Peak memory 216076 kb
Host smart-e7a83f80-0269-4725-ac66-83becc869c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255706333 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.255706333
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.2026573334
Short name T160
Test name
Test status
Simulation time 43744597 ps
CPU time 1.22 seconds
Started Jul 23 07:10:24 PM PDT 24
Finished Jul 23 07:10:33 PM PDT 24
Peak memory 225964 kb
Host smart-171121e5-8e20-4491-b1d0-8ffdb040d6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026573334 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.2026573334
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.3793952370
Short name T802
Test name
Test status
Simulation time 55084455 ps
CPU time 1.19 seconds
Started Jul 23 07:10:29 PM PDT 24
Finished Jul 23 07:10:39 PM PDT 24
Peak memory 217848 kb
Host smart-f718b982-68c1-425e-b09c-a42238b17e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793952370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3793952370
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.2028151879
Short name T942
Test name
Test status
Simulation time 24424558 ps
CPU time 1.13 seconds
Started Jul 23 07:10:25 PM PDT 24
Finished Jul 23 07:10:35 PM PDT 24
Peak memory 219872 kb
Host smart-3fa733d5-e111-4df0-954b-5cd0add0c435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028151879 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.2028151879
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.134066789
Short name T50
Test name
Test status
Simulation time 72884877 ps
CPU time 1.22 seconds
Started Jul 23 07:10:24 PM PDT 24
Finished Jul 23 07:10:34 PM PDT 24
Peak memory 226052 kb
Host smart-d43a35aa-410a-4f93-ada6-cb85e81d4fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134066789 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.134066789
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.275090827
Short name T603
Test name
Test status
Simulation time 97105511 ps
CPU time 1.27 seconds
Started Jul 23 07:10:28 PM PDT 24
Finished Jul 23 07:10:38 PM PDT 24
Peak memory 217524 kb
Host smart-5fb652ae-21a3-4929-a199-6fb25256ef3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275090827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.275090827
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.3597994832
Short name T92
Test name
Test status
Simulation time 49689594 ps
CPU time 1.25 seconds
Started Jul 23 07:10:25 PM PDT 24
Finished Jul 23 07:10:35 PM PDT 24
Peak memory 219676 kb
Host smart-49fa53f6-eb7a-4022-b139-eb3408cd97be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597994832 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.3597994832
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.2294080291
Short name T149
Test name
Test status
Simulation time 20747500 ps
CPU time 1.12 seconds
Started Jul 23 07:10:30 PM PDT 24
Finished Jul 23 07:10:40 PM PDT 24
Peak memory 220136 kb
Host smart-3bca80c6-cb0e-414a-ae8f-04352d600200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294080291 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.2294080291
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.367008644
Short name T45
Test name
Test status
Simulation time 200379042 ps
CPU time 3.52 seconds
Started Jul 23 07:10:26 PM PDT 24
Finished Jul 23 07:10:39 PM PDT 24
Peak memory 220480 kb
Host smart-9f3f48b9-ad49-4053-885e-25a327fcc0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367008644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.367008644
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.3054571256
Short name T344
Test name
Test status
Simulation time 88919296 ps
CPU time 1.15 seconds
Started Jul 23 07:10:27 PM PDT 24
Finished Jul 23 07:10:37 PM PDT 24
Peak memory 219960 kb
Host smart-c6d9c8d7-5d62-4006-a3e7-0a3f7fa52ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054571256 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.3054571256
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.2290364324
Short name T889
Test name
Test status
Simulation time 21805156 ps
CPU time 1.15 seconds
Started Jul 23 07:10:29 PM PDT 24
Finished Jul 23 07:10:39 PM PDT 24
Peak memory 229908 kb
Host smart-9daf46f4-4aea-4c7f-b606-68b466594b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290364324 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.2290364324
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.2790513640
Short name T533
Test name
Test status
Simulation time 105251319 ps
CPU time 2.51 seconds
Started Jul 23 07:10:31 PM PDT 24
Finished Jul 23 07:10:42 PM PDT 24
Peak memory 220692 kb
Host smart-9f170a14-a5e6-454d-9b63-10dbb8fbd4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790513640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.2790513640
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.964231109
Short name T172
Test name
Test status
Simulation time 49972900 ps
CPU time 1.06 seconds
Started Jul 23 07:10:26 PM PDT 24
Finished Jul 23 07:10:36 PM PDT 24
Peak memory 216200 kb
Host smart-819b893b-154a-412c-87a9-17eae1c23037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964231109 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.964231109
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.2495133415
Short name T112
Test name
Test status
Simulation time 35696747 ps
CPU time 1.18 seconds
Started Jul 23 07:10:25 PM PDT 24
Finished Jul 23 07:10:36 PM PDT 24
Peak memory 230024 kb
Host smart-02b36b84-b8a5-4875-82ec-30f9fb3bc2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495133415 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.2495133415
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.1280421144
Short name T993
Test name
Test status
Simulation time 60502572 ps
CPU time 1.51 seconds
Started Jul 23 07:10:28 PM PDT 24
Finished Jul 23 07:10:39 PM PDT 24
Peak memory 218992 kb
Host smart-c219e31e-7329-4fd5-9129-61f480677304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280421144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.1280421144
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.488286203
Short name T676
Test name
Test status
Simulation time 46008352 ps
CPU time 1.17 seconds
Started Jul 23 07:10:30 PM PDT 24
Finished Jul 23 07:10:40 PM PDT 24
Peak memory 221156 kb
Host smart-7e4648bc-9e51-43db-b8ee-b96b18157818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488286203 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.488286203
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.3308135614
Short name T710
Test name
Test status
Simulation time 50816236 ps
CPU time 1.01 seconds
Started Jul 23 07:10:32 PM PDT 24
Finished Jul 23 07:10:42 PM PDT 24
Peak memory 219936 kb
Host smart-71be6744-f444-4a27-a5ab-b4f7e8eaecd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308135614 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3308135614
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.1351062872
Short name T964
Test name
Test status
Simulation time 426333890 ps
CPU time 3.78 seconds
Started Jul 23 07:10:29 PM PDT 24
Finished Jul 23 07:10:42 PM PDT 24
Peak memory 220084 kb
Host smart-f14a4654-d8b3-4902-b856-40d1a31b088c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351062872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.1351062872
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.1988579051
Short name T317
Test name
Test status
Simulation time 26459949 ps
CPU time 1.13 seconds
Started Jul 23 07:10:28 PM PDT 24
Finished Jul 23 07:10:39 PM PDT 24
Peak memory 220116 kb
Host smart-5b07b616-65b8-44f4-af37-4df0f862fef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988579051 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.1988579051
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.1936730182
Short name T211
Test name
Test status
Simulation time 30649163 ps
CPU time 0.88 seconds
Started Jul 23 07:10:32 PM PDT 24
Finished Jul 23 07:10:42 PM PDT 24
Peak memory 218776 kb
Host smart-bd040f38-51a4-4b2a-bde9-db97125123fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936730182 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.1936730182
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.3470864756
Short name T687
Test name
Test status
Simulation time 31950859 ps
CPU time 1.03 seconds
Started Jul 23 07:10:27 PM PDT 24
Finished Jul 23 07:10:36 PM PDT 24
Peak memory 217760 kb
Host smart-f6978c17-614b-47e2-a386-a3d6dee68652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470864756 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3470864756
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.1253606998
Short name T886
Test name
Test status
Simulation time 84239552 ps
CPU time 1.29 seconds
Started Jul 23 07:10:29 PM PDT 24
Finished Jul 23 07:10:39 PM PDT 24
Peak memory 220768 kb
Host smart-62a1f56b-26ca-4155-8df3-a2c0e60d36a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253606998 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.1253606998
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.1255208280
Short name T767
Test name
Test status
Simulation time 32771909 ps
CPU time 1.02 seconds
Started Jul 23 07:10:26 PM PDT 24
Finished Jul 23 07:10:36 PM PDT 24
Peak memory 224400 kb
Host smart-15718690-3999-4630-9eb8-220cbd30b7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255208280 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.1255208280
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.980374394
Short name T616
Test name
Test status
Simulation time 37686399 ps
CPU time 1.39 seconds
Started Jul 23 07:10:25 PM PDT 24
Finished Jul 23 07:10:35 PM PDT 24
Peak memory 215624 kb
Host smart-66ec424c-a0b2-4a8c-8163-93effbadd69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980374394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.980374394
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.3966154915
Short name T630
Test name
Test status
Simulation time 24158676 ps
CPU time 1.14 seconds
Started Jul 23 07:10:29 PM PDT 24
Finished Jul 23 07:10:39 PM PDT 24
Peak memory 216048 kb
Host smart-d75c5252-ebbd-45c3-a190-e6ba51e008f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966154915 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.3966154915
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.70321685
Short name T17
Test name
Test status
Simulation time 20967641 ps
CPU time 1.12 seconds
Started Jul 23 07:10:26 PM PDT 24
Finished Jul 23 07:10:36 PM PDT 24
Peak memory 224316 kb
Host smart-00df14f6-bccb-4b99-ab2b-671b72f4428a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70321685 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.70321685
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.3453488422
Short name T290
Test name
Test status
Simulation time 170293915 ps
CPU time 1.36 seconds
Started Jul 23 07:10:28 PM PDT 24
Finished Jul 23 07:10:39 PM PDT 24
Peak memory 219432 kb
Host smart-bc0f2d5a-eaf8-4e2d-b182-66c4f6d83c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453488422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.3453488422
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.783096276
Short name T932
Test name
Test status
Simulation time 70496858 ps
CPU time 1.19 seconds
Started Jul 23 07:10:28 PM PDT 24
Finished Jul 23 07:10:38 PM PDT 24
Peak memory 219468 kb
Host smart-23ef0110-c31e-4c35-ac89-34b774671446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783096276 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.783096276
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.2266211836
Short name T463
Test name
Test status
Simulation time 80123294 ps
CPU time 1.06 seconds
Started Jul 23 07:10:27 PM PDT 24
Finished Jul 23 07:10:36 PM PDT 24
Peak memory 221112 kb
Host smart-541a1f38-971b-4bc3-9696-3e6c98f7e507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266211836 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.2266211836
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.3439315689
Short name T439
Test name
Test status
Simulation time 42069306 ps
CPU time 1.58 seconds
Started Jul 23 07:10:30 PM PDT 24
Finished Jul 23 07:10:41 PM PDT 24
Peak memory 218868 kb
Host smart-d170fcdd-0a06-46ed-90a9-a37ee9622868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439315689 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3439315689
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.1160930839
Short name T618
Test name
Test status
Simulation time 26351609 ps
CPU time 1.2 seconds
Started Jul 23 07:08:52 PM PDT 24
Finished Jul 23 07:08:56 PM PDT 24
Peak memory 218924 kb
Host smart-bed3d6ff-0314-40eb-8654-c98b1afcc08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160930839 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.1160930839
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.3471207482
Short name T579
Test name
Test status
Simulation time 71776202 ps
CPU time 0.99 seconds
Started Jul 23 07:08:58 PM PDT 24
Finished Jul 23 07:09:01 PM PDT 24
Peak memory 207084 kb
Host smart-4ae415f3-5993-47ba-9581-85801c4dc045
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471207482 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3471207482
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.1757196487
Short name T947
Test name
Test status
Simulation time 10828886 ps
CPU time 0.87 seconds
Started Jul 23 07:08:55 PM PDT 24
Finished Jul 23 07:08:57 PM PDT 24
Peak memory 216220 kb
Host smart-844f1636-2c90-40a6-aa6c-29351328c11b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757196487 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.1757196487
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.1114155672
Short name T67
Test name
Test status
Simulation time 43273389 ps
CPU time 1.41 seconds
Started Jul 23 07:08:53 PM PDT 24
Finished Jul 23 07:08:56 PM PDT 24
Peak memory 217224 kb
Host smart-fef9d0b9-5c6e-4c44-8bb6-0413d10ebf78
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114155672 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.1114155672
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.4235683759
Short name T196
Test name
Test status
Simulation time 32389017 ps
CPU time 0.88 seconds
Started Jul 23 07:08:52 PM PDT 24
Finished Jul 23 07:08:55 PM PDT 24
Peak memory 218844 kb
Host smart-d3ad0020-f5d9-44a8-a4d2-3f5ec9bac4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235683759 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.4235683759
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.1064577421
Short name T353
Test name
Test status
Simulation time 101748457 ps
CPU time 1.4 seconds
Started Jul 23 07:08:53 PM PDT 24
Finished Jul 23 07:08:57 PM PDT 24
Peak memory 217840 kb
Host smart-2dabd216-a706-4223-bcce-ded58eca905f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064577421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1064577421
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.471752127
Short name T33
Test name
Test status
Simulation time 58027497 ps
CPU time 0.85 seconds
Started Jul 23 07:08:54 PM PDT 24
Finished Jul 23 07:08:57 PM PDT 24
Peak memory 216048 kb
Host smart-2beb419b-a38e-4000-ba89-82518641eebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471752127 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.471752127
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.1539913571
Short name T806
Test name
Test status
Simulation time 18608830 ps
CPU time 0.99 seconds
Started Jul 23 07:08:59 PM PDT 24
Finished Jul 23 07:09:01 PM PDT 24
Peak memory 207404 kb
Host smart-a61cc6a9-8642-4511-ba30-303fe58cca85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539913571 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.1539913571
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.435125547
Short name T443
Test name
Test status
Simulation time 44760009 ps
CPU time 0.88 seconds
Started Jul 23 07:08:55 PM PDT 24
Finished Jul 23 07:08:57 PM PDT 24
Peak memory 215640 kb
Host smart-73b90167-f044-48bd-9c47-346ecfc1b918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435125547 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.435125547
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.3598999183
Short name T287
Test name
Test status
Simulation time 762957679 ps
CPU time 2.91 seconds
Started Jul 23 07:08:52 PM PDT 24
Finished Jul 23 07:08:57 PM PDT 24
Peak memory 217712 kb
Host smart-8ec65f7f-f047-4a8b-84b7-656793f2881d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598999183 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.3598999183
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.1560850966
Short name T454
Test name
Test status
Simulation time 2216901459445 ps
CPU time 4086.9 seconds
Started Jul 23 07:08:53 PM PDT 24
Finished Jul 23 08:17:02 PM PDT 24
Peak memory 234976 kb
Host smart-8585b702-dc53-4759-bae0-00ea84ae2a0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560850966 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.1560850966
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.1267345686
Short name T972
Test name
Test status
Simulation time 26204067 ps
CPU time 1.15 seconds
Started Jul 23 07:10:32 PM PDT 24
Finished Jul 23 07:10:42 PM PDT 24
Peak memory 219012 kb
Host smart-952c974c-18dc-4ae0-ac36-dd19fe9cfc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267345686 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.1267345686
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.2812411020
Short name T100
Test name
Test status
Simulation time 37305964 ps
CPU time 0.9 seconds
Started Jul 23 07:10:29 PM PDT 24
Finished Jul 23 07:10:38 PM PDT 24
Peak memory 218800 kb
Host smart-5795871a-d8b5-4fbe-86da-c928d99ef6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812411020 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.2812411020
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.789937619
Short name T417
Test name
Test status
Simulation time 48509338 ps
CPU time 1.82 seconds
Started Jul 23 07:10:24 PM PDT 24
Finished Jul 23 07:10:34 PM PDT 24
Peak memory 218924 kb
Host smart-48e5543d-29bd-454d-8e02-39d013a82816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789937619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.789937619
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.3826062675
Short name T851
Test name
Test status
Simulation time 27473535 ps
CPU time 1.2 seconds
Started Jul 23 07:10:31 PM PDT 24
Finished Jul 23 07:10:41 PM PDT 24
Peak memory 219380 kb
Host smart-0c040a76-0078-4ee6-b872-4d72a9774b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826062675 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.3826062675
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.1305180275
Short name T7
Test name
Test status
Simulation time 38751020 ps
CPU time 1.04 seconds
Started Jul 23 07:10:26 PM PDT 24
Finished Jul 23 07:10:36 PM PDT 24
Peak memory 219940 kb
Host smart-e3d32fb4-c0d1-47eb-8833-0c07cf66eb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305180275 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.1305180275
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.2593810075
Short name T519
Test name
Test status
Simulation time 42725774 ps
CPU time 1.52 seconds
Started Jul 23 07:10:26 PM PDT 24
Finished Jul 23 07:10:37 PM PDT 24
Peak memory 219072 kb
Host smart-d7163493-3916-4d33-96b8-c87f67c4f351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593810075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.2593810075
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.2782534753
Short name T848
Test name
Test status
Simulation time 39599303 ps
CPU time 1.32 seconds
Started Jul 23 07:10:30 PM PDT 24
Finished Jul 23 07:10:40 PM PDT 24
Peak memory 216028 kb
Host smart-a41dd4ad-d086-4b3f-98fb-cbe39336cda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782534753 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.2782534753
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.286833006
Short name T153
Test name
Test status
Simulation time 26108456 ps
CPU time 1.33 seconds
Started Jul 23 07:10:31 PM PDT 24
Finished Jul 23 07:10:41 PM PDT 24
Peak memory 230020 kb
Host smart-426b88db-bcfb-4c9f-8b37-1ea928a75dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286833006 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.286833006
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.1452180841
Short name T87
Test name
Test status
Simulation time 51330870 ps
CPU time 1.6 seconds
Started Jul 23 07:10:31 PM PDT 24
Finished Jul 23 07:10:41 PM PDT 24
Peak memory 218860 kb
Host smart-e95b8df8-8da0-4af1-b0bf-a07a5a73cc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452180841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.1452180841
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.1151996160
Short name T888
Test name
Test status
Simulation time 28832286 ps
CPU time 1.29 seconds
Started Jul 23 07:10:30 PM PDT 24
Finished Jul 23 07:10:40 PM PDT 24
Peak memory 220344 kb
Host smart-ebb56600-0c56-4925-8955-d34ef9933d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151996160 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.1151996160
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.3702828692
Short name T927
Test name
Test status
Simulation time 33832959 ps
CPU time 0.9 seconds
Started Jul 23 07:10:32 PM PDT 24
Finished Jul 23 07:10:42 PM PDT 24
Peak memory 218672 kb
Host smart-ab4eb6a7-bbcf-4611-9e4a-a442ef58cf1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702828692 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.3702828692
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.2526477700
Short name T918
Test name
Test status
Simulation time 46060160 ps
CPU time 1.67 seconds
Started Jul 23 07:10:28 PM PDT 24
Finished Jul 23 07:10:39 PM PDT 24
Peak memory 218956 kb
Host smart-10d21f11-5e35-4257-8337-5f24d8e7d4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526477700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.2526477700
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.1350406982
Short name T619
Test name
Test status
Simulation time 80832981 ps
CPU time 1.23 seconds
Started Jul 23 07:10:29 PM PDT 24
Finished Jul 23 07:10:39 PM PDT 24
Peak memory 218932 kb
Host smart-c58a9ef3-e9f5-4609-abe1-95899b987dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350406982 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.1350406982
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.3092328146
Short name T4
Test name
Test status
Simulation time 21313626 ps
CPU time 1.08 seconds
Started Jul 23 07:10:32 PM PDT 24
Finished Jul 23 07:10:42 PM PDT 24
Peak memory 218752 kb
Host smart-75401948-daa3-4750-a61f-301ebbb8efbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092328146 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.3092328146
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.3915030382
Short name T420
Test name
Test status
Simulation time 73923438 ps
CPU time 1.38 seconds
Started Jul 23 07:10:33 PM PDT 24
Finished Jul 23 07:10:43 PM PDT 24
Peak memory 218784 kb
Host smart-11d0aaae-fe5c-4a28-bbd9-18e4966ea7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915030382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3915030382
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.219253998
Short name T799
Test name
Test status
Simulation time 168149810 ps
CPU time 1.13 seconds
Started Jul 23 07:10:34 PM PDT 24
Finished Jul 23 07:10:45 PM PDT 24
Peak memory 218912 kb
Host smart-454577aa-2fb4-4ef1-af36-b003d8b851db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219253998 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.219253998
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.3767122730
Short name T950
Test name
Test status
Simulation time 23291281 ps
CPU time 0.89 seconds
Started Jul 23 07:10:33 PM PDT 24
Finished Jul 23 07:10:42 PM PDT 24
Peak memory 218904 kb
Host smart-edb97afa-1134-43a9-bbcc-7fa687b6d685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767122730 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.3767122730
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.2479917065
Short name T867
Test name
Test status
Simulation time 29680586 ps
CPU time 1.22 seconds
Started Jul 23 07:10:30 PM PDT 24
Finished Jul 23 07:10:40 PM PDT 24
Peak memory 217544 kb
Host smart-9b5cc981-f4c5-4569-8a84-49202342f44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479917065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.2479917065
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.99929825
Short name T452
Test name
Test status
Simulation time 23829171 ps
CPU time 1.21 seconds
Started Jul 23 07:10:31 PM PDT 24
Finished Jul 23 07:10:41 PM PDT 24
Peak memory 219844 kb
Host smart-82977a9e-8bdf-4e33-a7b4-82ce7420ad5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99929825 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.99929825
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.289439905
Short name T887
Test name
Test status
Simulation time 33458600 ps
CPU time 0.9 seconds
Started Jul 23 07:10:34 PM PDT 24
Finished Jul 23 07:10:44 PM PDT 24
Peak memory 218960 kb
Host smart-3fc3c562-c503-46d8-9789-050a4f444711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289439905 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.289439905
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.3589009814
Short name T303
Test name
Test status
Simulation time 187352013 ps
CPU time 2.78 seconds
Started Jul 23 07:10:36 PM PDT 24
Finished Jul 23 07:10:48 PM PDT 24
Peak memory 220352 kb
Host smart-c9a0c750-aae5-42c8-bb8b-48f7ad7c355c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589009814 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3589009814
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.1967762052
Short name T314
Test name
Test status
Simulation time 58202138 ps
CPU time 1.11 seconds
Started Jul 23 07:10:32 PM PDT 24
Finished Jul 23 07:10:42 PM PDT 24
Peak memory 219756 kb
Host smart-aa5c10fb-feca-478b-9ac0-35f91d063d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967762052 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.1967762052
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.1668600294
Short name T584
Test name
Test status
Simulation time 45670246 ps
CPU time 0.97 seconds
Started Jul 23 07:10:40 PM PDT 24
Finished Jul 23 07:10:51 PM PDT 24
Peak memory 220228 kb
Host smart-191568fd-88f4-4dae-a215-e0fd757d782c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668600294 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.1668600294
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.3725603884
Short name T773
Test name
Test status
Simulation time 60160303 ps
CPU time 1.24 seconds
Started Jul 23 07:10:37 PM PDT 24
Finished Jul 23 07:10:48 PM PDT 24
Peak memory 218808 kb
Host smart-3934197e-858a-478b-bd94-7bd17c0a0d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725603884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.3725603884
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.1033406373
Short name T146
Test name
Test status
Simulation time 24465805 ps
CPU time 1.24 seconds
Started Jul 23 07:10:33 PM PDT 24
Finished Jul 23 07:10:43 PM PDT 24
Peak memory 221204 kb
Host smart-0a77529a-72a7-43e6-acb0-04f2897280f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033406373 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.1033406373
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.973935476
Short name T115
Test name
Test status
Simulation time 67657113 ps
CPU time 0.88 seconds
Started Jul 23 07:10:35 PM PDT 24
Finished Jul 23 07:10:45 PM PDT 24
Peak memory 220104 kb
Host smart-be4d317f-6dcc-4584-8f31-94c45646016d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973935476 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.973935476
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1441425889
Short name T765
Test name
Test status
Simulation time 45161423 ps
CPU time 1.16 seconds
Started Jul 23 07:10:40 PM PDT 24
Finished Jul 23 07:10:51 PM PDT 24
Peak memory 217844 kb
Host smart-c09a260f-1cf9-4f4b-83f3-b02c0acad611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441425889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1441425889
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.270062026
Short name T624
Test name
Test status
Simulation time 57573384 ps
CPU time 1.23 seconds
Started Jul 23 07:10:34 PM PDT 24
Finished Jul 23 07:10:45 PM PDT 24
Peak memory 219968 kb
Host smart-d8764403-f972-4980-a167-15b1ea951d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270062026 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.270062026
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.1510441054
Short name T809
Test name
Test status
Simulation time 57078266 ps
CPU time 0.99 seconds
Started Jul 23 07:10:43 PM PDT 24
Finished Jul 23 07:10:55 PM PDT 24
Peak memory 219780 kb
Host smart-568c1d48-ccfc-4b00-96ed-a9051f4c1cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510441054 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.1510441054
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.514384917
Short name T306
Test name
Test status
Simulation time 39907722 ps
CPU time 1.48 seconds
Started Jul 23 07:10:34 PM PDT 24
Finished Jul 23 07:10:44 PM PDT 24
Peak memory 218796 kb
Host smart-97699993-f4f2-48bc-9e4d-618e10942f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514384917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.514384917
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.43043462
Short name T937
Test name
Test status
Simulation time 30067424 ps
CPU time 1.24 seconds
Started Jul 23 07:09:03 PM PDT 24
Finished Jul 23 07:09:06 PM PDT 24
Peak memory 219036 kb
Host smart-76087fcd-15f4-4c39-95c0-56714cdf274a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43043462 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.43043462
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.3756787303
Short name T612
Test name
Test status
Simulation time 22804824 ps
CPU time 0.83 seconds
Started Jul 23 07:09:00 PM PDT 24
Finished Jul 23 07:09:03 PM PDT 24
Peak memory 207120 kb
Host smart-057ea859-fdc2-4786-9d99-467c1db805bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756787303 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.3756787303
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.2547907242
Short name T93
Test name
Test status
Simulation time 16459001 ps
CPU time 0.79 seconds
Started Jul 23 07:09:00 PM PDT 24
Finished Jul 23 07:09:03 PM PDT 24
Peak memory 216728 kb
Host smart-ac9abf10-1243-4d08-9af0-9ee61527d5ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547907242 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.2547907242
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.3546165874
Short name T727
Test name
Test status
Simulation time 43922296 ps
CPU time 1.39 seconds
Started Jul 23 07:09:00 PM PDT 24
Finished Jul 23 07:09:04 PM PDT 24
Peak memory 219672 kb
Host smart-57ddb241-64f7-4ce8-82da-82749e624e43
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546165874 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.3546165874
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.3912073372
Short name T966
Test name
Test status
Simulation time 19532268 ps
CPU time 1.07 seconds
Started Jul 23 07:09:03 PM PDT 24
Finished Jul 23 07:09:06 PM PDT 24
Peak memory 218584 kb
Host smart-ce2d870b-729e-43ef-96c4-911c0222f9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912073372 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.3912073372
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.594036645
Short name T369
Test name
Test status
Simulation time 36857353 ps
CPU time 1.23 seconds
Started Jul 23 07:08:59 PM PDT 24
Finished Jul 23 07:09:02 PM PDT 24
Peak memory 217524 kb
Host smart-9c36301b-3e50-477e-aa74-4b386d3641e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594036645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.594036645
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2437714313
Short name T35
Test name
Test status
Simulation time 35141067 ps
CPU time 0.86 seconds
Started Jul 23 07:09:00 PM PDT 24
Finished Jul 23 07:09:02 PM PDT 24
Peak memory 216072 kb
Host smart-dee09ad9-4854-4b3a-9740-a4ed73d3b25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437714313 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2437714313
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.2867959429
Short name T311
Test name
Test status
Simulation time 17290517 ps
CPU time 0.98 seconds
Started Jul 23 07:08:55 PM PDT 24
Finished Jul 23 07:08:57 PM PDT 24
Peak memory 207352 kb
Host smart-1a89f6c5-c471-4618-b2e6-2eaaf0fa58f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867959429 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2867959429
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.2907340912
Short name T406
Test name
Test status
Simulation time 18246729 ps
CPU time 1 seconds
Started Jul 23 07:08:58 PM PDT 24
Finished Jul 23 07:09:01 PM PDT 24
Peak memory 215604 kb
Host smart-1e16651a-b0c0-4232-a199-9241edca30bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907340912 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2907340912
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.3391656824
Short name T989
Test name
Test status
Simulation time 78577988 ps
CPU time 1.99 seconds
Started Jul 23 07:09:04 PM PDT 24
Finished Jul 23 07:09:07 PM PDT 24
Peak memory 215640 kb
Host smart-cf7b37b2-77fa-45bf-8e75-84c1afd14b29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391656824 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.3391656824
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.3509660940
Short name T640
Test name
Test status
Simulation time 71295426866 ps
CPU time 497.11 seconds
Started Jul 23 07:09:00 PM PDT 24
Finished Jul 23 07:17:20 PM PDT 24
Peak memory 219292 kb
Host smart-dbe4d683-7c3a-4c4a-84bb-e357fe66e285
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509660940 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.3509660940
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.799062135
Short name T578
Test name
Test status
Simulation time 130868198 ps
CPU time 1.22 seconds
Started Jul 23 07:10:43 PM PDT 24
Finished Jul 23 07:10:55 PM PDT 24
Peak memory 220296 kb
Host smart-21b78e2e-b1f7-4388-91f8-8a378d292c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799062135 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.799062135
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.1923278874
Short name T135
Test name
Test status
Simulation time 80243126 ps
CPU time 1.17 seconds
Started Jul 23 07:10:37 PM PDT 24
Finished Jul 23 07:10:48 PM PDT 24
Peak memory 229976 kb
Host smart-e288c1d7-2323-4ccc-9ec2-9d07382b8a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923278874 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.1923278874
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.3956088221
Short name T938
Test name
Test status
Simulation time 146762170 ps
CPU time 3.33 seconds
Started Jul 23 07:10:36 PM PDT 24
Finished Jul 23 07:10:49 PM PDT 24
Peak memory 218872 kb
Host smart-70b5c424-9826-4bef-b127-b33a0824b955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956088221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3956088221
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.3702676057
Short name T679
Test name
Test status
Simulation time 29567700 ps
CPU time 1.16 seconds
Started Jul 23 07:10:43 PM PDT 24
Finished Jul 23 07:10:55 PM PDT 24
Peak memory 220116 kb
Host smart-ad1b6e15-4e2d-47b5-871f-ae6e8d18dd9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702676057 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.3702676057
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.2322878106
Short name T117
Test name
Test status
Simulation time 25886888 ps
CPU time 1.2 seconds
Started Jul 23 07:10:36 PM PDT 24
Finished Jul 23 07:10:47 PM PDT 24
Peak memory 220972 kb
Host smart-d4552122-e0f9-4d72-8aa4-3504ca35426b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322878106 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.2322878106
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.1461241088
Short name T376
Test name
Test status
Simulation time 98750528 ps
CPU time 1.54 seconds
Started Jul 23 07:10:34 PM PDT 24
Finished Jul 23 07:10:44 PM PDT 24
Peak memory 218988 kb
Host smart-f1f602ac-f577-42b4-a5c0-901f0a903ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461241088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.1461241088
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.3971484385
Short name T389
Test name
Test status
Simulation time 87428983 ps
CPU time 1.07 seconds
Started Jul 23 07:10:41 PM PDT 24
Finished Jul 23 07:10:52 PM PDT 24
Peak memory 220384 kb
Host smart-d4863d9c-88ab-4cd2-affc-40552f56a9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971484385 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.3971484385
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.3598697520
Short name T714
Test name
Test status
Simulation time 36301714 ps
CPU time 0.89 seconds
Started Jul 23 07:10:38 PM PDT 24
Finished Jul 23 07:10:49 PM PDT 24
Peak memory 218628 kb
Host smart-d8c4b150-3941-465a-b697-cc391c2145f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598697520 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3598697520
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.2767134676
Short name T77
Test name
Test status
Simulation time 43448497 ps
CPU time 1.23 seconds
Started Jul 23 07:10:38 PM PDT 24
Finished Jul 23 07:10:50 PM PDT 24
Peak memory 220076 kb
Host smart-db58f14f-2acb-4a70-862a-6229513d933e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767134676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.2767134676
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.3320626072
Short name T320
Test name
Test status
Simulation time 78445681 ps
CPU time 1.07 seconds
Started Jul 23 07:10:37 PM PDT 24
Finished Jul 23 07:10:48 PM PDT 24
Peak memory 219040 kb
Host smart-49a2013f-22ec-45a5-87d4-02f1f06826a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320626072 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.3320626072
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.3279393277
Short name T634
Test name
Test status
Simulation time 28095921 ps
CPU time 1.05 seconds
Started Jul 23 07:10:37 PM PDT 24
Finished Jul 23 07:10:48 PM PDT 24
Peak memory 218656 kb
Host smart-249946a5-e1ed-44fe-bcbe-144175b283c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279393277 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3279393277
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.3813941281
Short name T677
Test name
Test status
Simulation time 124643420 ps
CPU time 1.37 seconds
Started Jul 23 07:10:39 PM PDT 24
Finished Jul 23 07:10:51 PM PDT 24
Peak memory 219756 kb
Host smart-4d581eb3-7b33-4bc5-a3ac-c04deaa5f0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813941281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.3813941281
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.1956672449
Short name T272
Test name
Test status
Simulation time 61415649 ps
CPU time 1.05 seconds
Started Jul 23 07:10:34 PM PDT 24
Finished Jul 23 07:10:44 PM PDT 24
Peak memory 218988 kb
Host smart-36601f6a-2f88-4f4d-b42d-8909984ee937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956672449 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.1956672449
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.3592727953
Short name T693
Test name
Test status
Simulation time 29120536 ps
CPU time 1.2 seconds
Started Jul 23 07:10:35 PM PDT 24
Finished Jul 23 07:10:45 PM PDT 24
Peak memory 220036 kb
Host smart-9a7b1e43-edbe-4793-8d42-5409321ec481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592727953 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3592727953
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.3920004695
Short name T697
Test name
Test status
Simulation time 33524921 ps
CPU time 1.41 seconds
Started Jul 23 07:10:30 PM PDT 24
Finished Jul 23 07:10:40 PM PDT 24
Peak memory 217764 kb
Host smart-ddcb8914-3f58-4157-ba5a-255a01901df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920004695 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.3920004695
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.4150332481
Short name T631
Test name
Test status
Simulation time 26653444 ps
CPU time 1.18 seconds
Started Jul 23 07:10:37 PM PDT 24
Finished Jul 23 07:10:48 PM PDT 24
Peak memory 220304 kb
Host smart-e00eabc6-bc58-46ca-b5e3-bcd6bd88189a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150332481 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.4150332481
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.565036318
Short name T194
Test name
Test status
Simulation time 27878551 ps
CPU time 0.86 seconds
Started Jul 23 07:10:34 PM PDT 24
Finished Jul 23 07:10:44 PM PDT 24
Peak memory 219956 kb
Host smart-57d4bd9b-242b-49f2-8b38-81f4537d3141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565036318 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.565036318
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.1821445748
Short name T917
Test name
Test status
Simulation time 75871948 ps
CPU time 1.26 seconds
Started Jul 23 07:10:36 PM PDT 24
Finished Jul 23 07:10:47 PM PDT 24
Peak memory 220236 kb
Host smart-f3737ed8-e98d-4c14-968e-a8ae04b0256f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821445748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.1821445748
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.3350360618
Short name T133
Test name
Test status
Simulation time 23916142 ps
CPU time 1.2 seconds
Started Jul 23 07:10:40 PM PDT 24
Finished Jul 23 07:10:52 PM PDT 24
Peak memory 220888 kb
Host smart-1625f688-e090-4fb1-9081-5fa8a69094fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350360618 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.3350360618
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.819732444
Short name T195
Test name
Test status
Simulation time 19856321 ps
CPU time 1.01 seconds
Started Jul 23 07:10:36 PM PDT 24
Finished Jul 23 07:10:46 PM PDT 24
Peak memory 219852 kb
Host smart-4c368326-64ee-4ee6-a24c-b398a251c465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819732444 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.819732444
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.4200182557
Short name T297
Test name
Test status
Simulation time 57587764 ps
CPU time 1.03 seconds
Started Jul 23 07:10:35 PM PDT 24
Finished Jul 23 07:10:45 PM PDT 24
Peak memory 217552 kb
Host smart-bf491f22-e02e-408f-af1e-dea2b31c26be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200182557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.4200182557
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.2852544731
Short name T577
Test name
Test status
Simulation time 42613936 ps
CPU time 1.09 seconds
Started Jul 23 07:10:35 PM PDT 24
Finished Jul 23 07:10:46 PM PDT 24
Peak memory 219084 kb
Host smart-97c237eb-d73a-42a2-8a10-4cd1a1768777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852544731 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.2852544731
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.1161034539
Short name T192
Test name
Test status
Simulation time 40034300 ps
CPU time 0.87 seconds
Started Jul 23 07:10:32 PM PDT 24
Finished Jul 23 07:10:41 PM PDT 24
Peak memory 219580 kb
Host smart-d92a3359-da96-46ab-82d3-b16d79b84327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161034539 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.1161034539
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.1214995718
Short name T786
Test name
Test status
Simulation time 66167815 ps
CPU time 1.51 seconds
Started Jul 23 07:10:38 PM PDT 24
Finished Jul 23 07:10:50 PM PDT 24
Peak memory 219108 kb
Host smart-591b520d-e7a2-4133-9350-6b7c29a66e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214995718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.1214995718
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.3900253245
Short name T113
Test name
Test status
Simulation time 102321514 ps
CPU time 1.28 seconds
Started Jul 23 07:10:39 PM PDT 24
Finished Jul 23 07:10:51 PM PDT 24
Peak memory 216012 kb
Host smart-51ab5685-e5ff-4630-a7fd-e7393bc493d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900253245 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.3900253245
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.2174039738
Short name T139
Test name
Test status
Simulation time 68570970 ps
CPU time 1.01 seconds
Started Jul 23 07:10:36 PM PDT 24
Finished Jul 23 07:10:46 PM PDT 24
Peak memory 220084 kb
Host smart-951d7c5a-42c7-48c5-b472-10f2edeb21b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174039738 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.2174039738
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2993862828
Short name T976
Test name
Test status
Simulation time 38812912 ps
CPU time 1.43 seconds
Started Jul 23 07:10:40 PM PDT 24
Finished Jul 23 07:10:52 PM PDT 24
Peak memory 217740 kb
Host smart-b0175c0c-4ee0-4310-ac6b-7e7fe62a9086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993862828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2993862828
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.1996278148
Short name T43
Test name
Test status
Simulation time 55296505 ps
CPU time 1.04 seconds
Started Jul 23 07:10:40 PM PDT 24
Finished Jul 23 07:10:51 PM PDT 24
Peak memory 218832 kb
Host smart-a89eb47a-c167-4808-9bf8-42f80d78afed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996278148 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.1996278148
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.2881920152
Short name T134
Test name
Test status
Simulation time 28289822 ps
CPU time 1.23 seconds
Started Jul 23 07:10:36 PM PDT 24
Finished Jul 23 07:10:46 PM PDT 24
Peak memory 220816 kb
Host smart-85880ff5-dfe2-4983-878c-4413fb6f3dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881920152 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.2881920152
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.4211448239
Short name T460
Test name
Test status
Simulation time 108529437 ps
CPU time 1.03 seconds
Started Jul 23 07:10:32 PM PDT 24
Finished Jul 23 07:10:42 PM PDT 24
Peak memory 217720 kb
Host smart-b52451c9-26b1-4d1b-b7c7-3a4a36bc60de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211448239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.4211448239
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%